package/rt2x00/src/rt2500pci.c

   1 /*
   2         Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt2500pci
  23         Abstract: rt2500pci device specific routines.
  24         Supported chipsets: RT2560.
  25  */
  26
  27 /*
  28  * Set enviroment defines for rt2x00.h
  29  */
  30 #define DRV_NAME "rt2500pci"
  31
  32 #include <linux/kernel.h>
  33 #include <linux/module.h>
  34 #include <linux/version.h>
  35 #include <linux/init.h>
  36 #include <linux/pci.h>
  37 #include <linux/dma-mapping.h>
  38 #include <linux/delay.h>
  39 #include <linux/etherdevice.h>
  40 #include <linux/eeprom_93cx6.h>
  41
  42 #include <asm/io.h>
  43
  44 #include "rt2x00.h"
  45 #include "rt2x00pci.h"
  46 #include "rt2500pci.h"
  47
  48 /*
  49  * Register access.
  50  * All access to the CSR registers will go through the methods
  51  * rt2x00pci_register_read and rt2x00pci_register_write.
  52  * BBP and RF register require indirect register access,
  53  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  54  * These indirect registers work with busy bits,
  55  * and we will try maximal REGISTER_BUSY_COUNT times to access
  56  * the register while taking a REGISTER_BUSY_DELAY us delay
  57  * between each attampt. When the busy bit is still set at that time,
  58  * the access attempt is considered to have failed,
  59  * and we will print an error.
  60  */
  61 static u32 rt2500pci_bbp_check(const struct rt2x00_dev *rt2x00dev)
  62 {
  63         u32 reg;
  64         unsigned int i;
  65
  66         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  67                 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
  68                 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
  69                         break;
  70                 udelay(REGISTER_BUSY_DELAY);
  71         }
  72
  73         return reg;
  74 }
  75
  76 static void rt2500pci_bbp_write(const struct rt2x00_dev *rt2x00dev,
  77         const u8 reg_id, const u8 value)
  78 {
  79         u32 reg;
  80
  81         /*
  82          *  Wait until the BBP becomes ready.
  83          */
  84         reg = rt2500pci_bbp_check(rt2x00dev);
  85         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
  86                 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
  87                 return;
  88         }
  89
  90         /*
  91          * Write the data into the BBP.
  92          */
  93         reg = 0;
  94         rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
  95         rt2x00_set_field32(&reg, BBPCSR_REGNUM, reg_id);
  96         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
  97         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
  98
  99         rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
 100 }
 101
 102 static void rt2500pci_bbp_read(const struct rt2x00_dev *rt2x00dev,
 103         const u8 reg_id, u8 *value)
 104 {
 105         u32 reg;
 106
 107         /*
 108          *  Wait until the BBP becomes ready.
 109          */
 110         reg = rt2500pci_bbp_check(rt2x00dev);
 111         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
 112                 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
 113                 return;
 114         }
 115
 116         /*
 117          * Write the request into the BBP.
 118          */
 119         reg = 0;
 120         rt2x00_set_field32(&reg, BBPCSR_REGNUM, reg_id);
 121         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
 122         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
 123
 124         rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
 125
 126         /*
 127          *  Wait until the BBP becomes ready.
 128          */
 129         reg = rt2500pci_bbp_check(rt2x00dev);
 130         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
 131                 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
 132                 *value = 0xff;
 133                 return;
 134         }
 135
 136         *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
 137 }
 138
 139 static void rt2500pci_rf_write(const struct rt2x00_dev *rt2x00dev,
 140         const u32 value)
 141 {
 142         u32 reg;
 143         unsigned int i;
 144
 145         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 146                 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
 147                 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
 148                         goto rf_write;
 149                 udelay(REGISTER_BUSY_DELAY);
 150         }
 151
 152         ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
 153         return;
 154
 155 rf_write:
 156         reg = 0;
 157         rt2x00_set_field32(&reg, RFCSR_VALUE, value);
 158         rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
 159         rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
 160         rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
 161
 162         rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
 163 }
 164
 165 static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 166 {
 167         struct rt2x00_dev *rt2x00dev = eeprom->data;
 168         u32 reg;
 169
 170         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
 171
 172         eeprom->reg_data_in = !!rt2x00_get_field32(reg,
 173                 CSR21_EEPROM_DATA_IN);
 174         eeprom->reg_data_out = !!rt2x00_get_field32(reg,
 175                 CSR21_EEPROM_DATA_OUT);
 176         eeprom->reg_data_clock = !!rt2x00_get_field32(reg,
 177                 CSR21_EEPROM_DATA_CLOCK);
 178         eeprom->reg_chip_select = !!rt2x00_get_field32(reg,
 179                 CSR21_EEPROM_CHIP_SELECT);
 180 }
 181
 182 static void rt2500pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 183 {
 184         struct rt2x00_dev *rt2x00dev = eeprom->data;
 185         u32 reg = 0;
 186
 187         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN,
 188                 !!eeprom->reg_data_in);
 189         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT,
 190                 !!eeprom->reg_data_out);
 191         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
 192                 !!eeprom->reg_data_clock);
 193         rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
 194                 !!eeprom->reg_chip_select);
 195
 196         rt2x00pci_register_write(rt2x00dev, CSR21, reg);
 197 }
 198
 199 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 200 #define CSR_OFFSET(__word)      ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
 201
 202 static void rt2500pci_read_csr(struct rt2x00_dev *rt2x00dev,
 203         const unsigned long word, void *data)
 204 {
 205         rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
 206 }
 207
 208 static void rt2500pci_write_csr(struct rt2x00_dev *rt2x00dev,
 209         const unsigned long word, void *data)
 210 {
 211         rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), *((u32*)data));
 212 }
 213
 214 static void rt2500pci_read_eeprom(struct rt2x00_dev *rt2x00dev,
 215         const unsigned long word, void *data)
 216 {
 217         rt2x00_eeprom_read(rt2x00dev, word, data);
 218 }
 219
 220 static void rt2500pci_write_eeprom(struct rt2x00_dev *rt2x00dev,
 221         const unsigned long word, void *data)
 222 {
 223         rt2x00_eeprom_write(rt2x00dev, word, *((u16*)data));
 224 }
 225
 226 static void rt2500pci_read_bbp(struct rt2x00_dev *rt2x00dev,
 227         const unsigned long word, void *data)
 228 {
 229         rt2500pci_bbp_read(rt2x00dev, word, data);
 230 }
 231
 232 static void rt2500pci_write_bbp(struct rt2x00_dev *rt2x00dev,
 233         const unsigned long word, void *data)
 234 {
 235         rt2500pci_bbp_write(rt2x00dev, word, *((u8*)data));
 236 }
 237
 238 static const struct rt2x00debug rt2500pci_rt2x00debug = {
 239         .owner          = THIS_MODULE,
 240         .reg_csr        = {
 241                 .read           = rt2500pci_read_csr,
 242                 .write          = rt2500pci_write_csr,
 243                 .word_size      = sizeof(u32),
 244                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 245         },
 246         .reg_eeprom     = {
 247                 .read           = rt2500pci_read_eeprom,
 248                 .write          = rt2500pci_write_eeprom,
 249                 .word_size      = sizeof(u16),
 250                 .word_count     = EEPROM_SIZE / sizeof(u16),
 251         },
 252         .reg_bbp        = {
 253                 .read           = rt2500pci_read_bbp,
 254                 .write          = rt2500pci_write_bbp,
 255                 .word_size      = sizeof(u8),
 256                 .word_count     = BBP_SIZE / sizeof(u8),
 257         },
 258 };
 259 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 260
 261 #ifdef CONFIG_RT2500PCI_RFKILL
 262 static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 263 {
 264         u32 reg;
 265
 266         rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
 267         return rt2x00_get_field32(reg, GPIOCSR_BIT0);
 268 }
 269 #endif /* CONFIG_RT2400PCI_RFKILL */
 270
 271 /*
 272  * Configuration handlers.
 273  */
 274 static void rt2500pci_config_bssid(struct rt2x00_dev *rt2x00dev, u8 *bssid)
 275 {
 276         u32 reg[2];
 277
 278         memset(&reg, 0, sizeof(reg));
 279         memcpy(&reg, bssid, ETH_ALEN);
 280
 281         /*
 282          * The BSSID is passed to us as an array of bytes,
 283          * that array is little endian, so no need for byte ordering.
 284          */
 285         rt2x00pci_register_multiwrite(rt2x00dev, CSR5, &reg, sizeof(reg));
 286 }
 287
 288 static void rt2500pci_config_promisc(struct rt2x00_dev *rt2x00dev,
 289         const int promisc)
 290 {
 291         u32 reg;
 292
 293         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
 294         rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME, !promisc);
 295         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
 296 }
 297
 298 static void rt2500pci_config_type(struct rt2x00_dev *rt2x00dev,
 299         const int type)
 300 {
 301         u32 reg;
 302
 303         rt2x00pci_register_write(rt2x00dev, CSR14, 0);
 304
 305         /*
 306          * Apply hardware packet filter.
 307          */
 308         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
 309
 310         if (!is_monitor_present(&rt2x00dev->interface) &&
 311             (type == IEEE80211_IF_TYPE_IBSS || type == IEEE80211_IF_TYPE_STA))
 312                 rt2x00_set_field32(&reg, RXCSR0_DROP_TODS, 1);
 313         else
 314                 rt2x00_set_field32(&reg, RXCSR0_DROP_TODS, 0);
 315
 316         rt2x00_set_field32(&reg, RXCSR0_DROP_CRC, 1);
 317         if (is_monitor_present(&rt2x00dev->interface)) {
 318                 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL, 0);
 319                 rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL, 0);
 320                 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 0);
 321         } else {
 322                 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL, 1);
 323                 rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL, 1);
 324                 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
 325         }
 326
 327         rt2x00_set_field32(&reg, RXCSR0_DROP_MCAST, 0);
 328         rt2x00_set_field32(&reg, RXCSR0_DROP_BCAST, 0);
 329
 330         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
 331
 332         /*
 333          * Enable beacon config
 334          */
 335         rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
 336         rt2x00_set_field32(&reg, BCNCSR1_PRELOAD,
 337                 PREAMBLE + get_duration(IEEE80211_HEADER, 2));
 338         rt2x00_set_field32(&reg, BCNCSR1_BEACON_CWMIN,
 339                 rt2x00_get_ring(rt2x00dev, IEEE80211_TX_QUEUE_BEACON)
 340                         ->tx_params.cw_min);
 341         rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
 342
 343         /*
 344          * Enable synchronisation.
 345          */
 346         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
 347         if (is_interface_present(&rt2x00dev->interface)) {
 348                 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
 349                 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
 350         }
 351
 352         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
 353         if (type == IEEE80211_IF_TYPE_IBSS || type == IEEE80211_IF_TYPE_AP)
 354                 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 2);
 355         else if (type == IEEE80211_IF_TYPE_STA)
 356                 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 1);
 357         else if (is_monitor_present(&rt2x00dev->interface) &&
 358                  !is_interface_present(&rt2x00dev->interface))
 359                 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
 360
 361         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
 362 }
 363
 364 static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev,
 365         const int value, const int channel, const int txpower)
 366 {
 367         u32 rf1 = rt2x00dev->rf1;
 368         u32 rf2 = value;
 369         u32 rf3 = rt2x00dev->rf3;
 370         u32 rf4 = rt2x00dev->rf4;
 371
 372         if (rt2x00_rf(&rt2x00dev->chip, RF2525) ||
 373             rt2x00_rf(&rt2x00dev->chip, RF2525E))
 374                 rf2 |= 0x00080000;
 375
 376         if (rt2x00_rf(&rt2x00dev->chip, RF2525E) && channel == 14)
 377                 rf4 |= 0x00000010;
 378
 379         if (rt2x00_rf(&rt2x00dev->chip, RF5222)) {
 380                 if (channel < 14) {
 381                         rf1 = 0x00022020;
 382                         rf4 = 0x00000a0b;
 383                 } else if (channel == 14) {
 384                         rf1 = 0x00022010;
 385                         rf4 = 0x00000a1b;
 386                 } else if (channel < 64) {
 387                         rf1 = 0x00022010;
 388                         rf4 = 0x00000a1f;
 389                 } else if (channel < 140) {
 390                         rf1 = 0x00022010;
 391                         rf4 = 0x00000a0f;
 392                 } else if (channel < 161) {
 393                         rf1 = 0x00022020;
 394                         rf4 = 0x00000a07;
 395                 }
 396         }
 397
 398         /*
 399          * Set TXpower.
 400          */
 401         rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
 402
 403         /*
 404          * Switch on tuning bits.
 405          * For RT2523 devices we do not need to update the R1 register.
 406          */
 407         if (!rt2x00_rf(&rt2x00dev->chip, RF2523))
 408                 rt2x00_set_field32(&rf1, RF1_TUNER, 1);
 409         rt2x00_set_field32(&rf3, RF3_TUNER, 1);
 410
 411         /*
 412          * For RT2525 we should first set the channel to half band higher.
 413          */
 414         if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
 415                 static const u32 vals[] = {
 416                         0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a,
 417                         0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a,
 418                         0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a,
 419                         0x00080d2e, 0x00080d3a
 420                 };
 421
 422                 rt2500pci_rf_write(rt2x00dev, rf1);
 423                 rt2500pci_rf_write(rt2x00dev, vals[channel - 1]);
 424                 rt2500pci_rf_write(rt2x00dev, rf3);
 425                 if (rf4)
 426                         rt2500pci_rf_write(rt2x00dev, rf4);
 427         }
 428
 429         rt2500pci_rf_write(rt2x00dev, rf1);
 430         rt2500pci_rf_write(rt2x00dev, rf2);
 431         rt2500pci_rf_write(rt2x00dev, rf3);
 432         if (rf4)
 433                 rt2500pci_rf_write(rt2x00dev, rf4);
 434
 435         /*
 436          * Channel 14 requires the Japan filter bit to be set.
 437          */
 438         rt2500pci_bbp_write(rt2x00dev, 70, (channel == 14) ? 0x4e : 0x46);
 439
 440         msleep(1);
 441
 442         /*
 443          * Switch off tuning bits.
 444          * For RT2523 devices we do not need to update the R1 register.
 445          */
 446         rt2x00_set_field32(&rf1, RF1_TUNER, 0);
 447         rt2x00_set_field32(&rf3, RF3_TUNER, 0);
 448
 449
 450         if (!rt2x00_rf(&rt2x00dev->chip, RF2523))
 451                 rt2500pci_rf_write(rt2x00dev, rf1);
 452
 453         rt2500pci_rf_write(rt2x00dev, rf3);
 454
 455         /*
 456          * Update rf fields
 457          */
 458         rt2x00dev->rf1 = rf1;
 459         rt2x00dev->rf2 = rf2;
 460         rt2x00dev->rf3 = rf3;
 461         rt2x00dev->rf4 = rf4;
 462         rt2x00dev->tx_power = txpower;
 463
 464         /*
 465          * Clear false CRC during channel switch.
 466          */
 467         rt2x00pci_register_read(rt2x00dev, CNT0, &rf1);
 468 }
 469
 470 static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev,
 471         const int txpower)
 472 {
 473         rt2x00_set_field32(&rt2x00dev->rf3, RF3_TXPOWER,
 474                 TXPOWER_TO_DEV(txpower));
 475         rt2500pci_rf_write(rt2x00dev, rt2x00dev->rf3);
 476
 477 }
 478
 479 static void rt2500pci_config_antenna(struct rt2x00_dev *rt2x00dev,
 480         const int antenna_tx, const int antenna_rx)
 481 {
 482         u32 reg;
 483         u8 r14;
 484         u8 r2;
 485
 486         rt2x00pci_register_read(rt2x00dev, BBPCSR1, &reg);
 487         rt2500pci_bbp_read(rt2x00dev, 14, &r14);
 488         rt2500pci_bbp_read(rt2x00dev, 2, &r2);
 489
 490         /*
 491          * Configure the TX antenna.
 492          */
 493         if (antenna_tx == ANTENNA_DIVERSITY) {
 494                 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
 495                 rt2x00_set_field32(&reg, BBPCSR1_CCK, 2);
 496                 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 2);
 497         } else if (antenna_tx == ANTENNA_A) {
 498                 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0);
 499                 rt2x00_set_field32(&reg, BBPCSR1_CCK, 0);
 500                 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 0);
 501         } else if (antenna_tx == ANTENNA_B) {
 502                 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
 503                 rt2x00_set_field32(&reg, BBPCSR1_CCK, 2);
 504                 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 2);
 505         }
 506
 507         /*
 508          * Configure the RX antenna.
 509          */
 510         if (antenna_rx == ANTENNA_DIVERSITY)
 511                 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
 512         else if (antenna_rx == ANTENNA_A)
 513                 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0);
 514         else if (antenna_rx == ANTENNA_B)
 515                 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
 516
 517         /*
 518          * RT2525E and RT5222 need to flip TX I/Q
 519          */
 520         if (rt2x00_rf(&rt2x00dev->chip, RF2525E) ||
 521             rt2x00_rf(&rt2x00dev->chip, RF5222)) {
 522                 rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1);
 523                 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 1);
 524                 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 1);
 525
 526                 /*
 527                  * RT2525E does not need RX I/Q Flip.
 528                  */
 529                 if (rt2x00_rf(&rt2x00dev->chip, RF2525E))
 530                         rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0);
 531         } else {
 532                 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 0);
 533                 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 0);
 534         }
 535
 536         rt2x00pci_register_write(rt2x00dev, BBPCSR1, reg);
 537         rt2500pci_bbp_write(rt2x00dev, 14, r14);
 538         rt2500pci_bbp_write(rt2x00dev, 2, r2);
 539 }
 540
 541 static void rt2500pci_config_duration(struct rt2x00_dev *rt2x00dev,
 542         const int short_slot_time, const int beacon_int)
 543 {
 544         u32 reg;
 545
 546         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 547         rt2x00_set_field32(&reg, CSR11_SLOT_TIME,
 548                 short_slot_time ? SHORT_SLOT_TIME : SLOT_TIME);
 549         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 550
 551         rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
 552         rt2x00_set_field32(&reg, CSR18_SIFS, SIFS);
 553         rt2x00_set_field32(&reg, CSR18_PIFS,
 554                 short_slot_time ? SHORT_PIFS : PIFS);
 555         rt2x00pci_register_write(rt2x00dev, CSR18, reg);
 556
 557         rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
 558         rt2x00_set_field32(&reg, CSR19_DIFS,
 559                 short_slot_time ? SHORT_DIFS : DIFS);
 560         rt2x00_set_field32(&reg, CSR19_EIFS, EIFS);
 561         rt2x00pci_register_write(rt2x00dev, CSR19, reg);
 562
 563         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
 564         rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
 565         rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
 566         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
 567
 568         rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
 569         rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL, beacon_int * 16);
 570         rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION, beacon_int * 16);
 571         rt2x00pci_register_write(rt2x00dev, CSR12, reg);
 572 }
 573
 574 static void rt2500pci_config_rate(struct rt2x00_dev *rt2x00dev, const int rate)
 575 {
 576         struct ieee80211_conf *conf = &rt2x00dev->hw->conf;
 577         u32 reg;
 578         u32 preamble;
 579         u16 value;
 580
 581         preamble = DEVICE_GET_RATE_FIELD(rate, PREAMBLE)
 582                 ? SHORT_PREAMBLE : PREAMBLE;
 583
 584         reg = DEVICE_GET_RATE_FIELD(rate, RATEMASK) & DEV_BASIC_RATE;
 585         rt2x00pci_register_write(rt2x00dev, ARCSR1, reg);
 586
 587         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
 588         value = ((conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME) ?
 589                  SHORT_DIFS :  DIFS) +
 590                 PLCP + preamble + get_duration(ACK_SIZE, 10);
 591         rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, value);
 592         value = SIFS + PLCP + preamble + get_duration(ACK_SIZE, 10);
 593         rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, value);
 594         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
 595
 596         preamble = DEVICE_GET_RATE_FIELD(rate, PREAMBLE) ? 0x08 : 0x00;
 597
 598         rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
 599         rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00 | preamble);
 600         rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
 601         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
 602         rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
 603
 604         rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
 605         rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble);
 606         rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
 607         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
 608         rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
 609
 610         rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
 611         rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble);
 612         rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
 613         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
 614         rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
 615
 616         rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
 617         rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble);
 618         rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
 619         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
 620         rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
 621 }
 622
 623 static void rt2500pci_config_phymode(struct rt2x00_dev *rt2x00dev,
 624         const int phymode)
 625 {
 626         struct ieee80211_hw_mode *mode;
 627         struct ieee80211_rate *rate;
 628
 629         if (phymode == MODE_IEEE80211A)
 630                 rt2x00dev->curr_hwmode = HWMODE_A;
 631         else if (phymode == MODE_IEEE80211B)
 632                 rt2x00dev->curr_hwmode = HWMODE_B;
 633         else
 634                 rt2x00dev->curr_hwmode = HWMODE_G;
 635
 636         mode = &rt2x00dev->hwmodes[rt2x00dev->curr_hwmode];
 637         rate = &mode->rates[mode->num_rates - 1];
 638
 639         rt2500pci_config_rate(rt2x00dev, rate->val2);
 640 }
 641
 642 static void rt2500pci_config_mac_addr(struct rt2x00_dev *rt2x00dev, u8 *addr)
 643 {
 644         u32 reg[2];
 645
 646         memset(&reg, 0, sizeof(reg));
 647         memcpy(&reg, addr, ETH_ALEN);
 648
 649         /*
 650          * The MAC address is passed to us as an array of bytes,
 651          * that array is little endian, so no need for byte ordering.
 652          */
 653         rt2x00pci_register_multiwrite(rt2x00dev, CSR3, &reg, sizeof(reg));
 654 }
 655
 656 /*
 657  * LED functions.
 658  */
 659 static void rt2500pci_enable_led(struct rt2x00_dev *rt2x00dev)
 660 {
 661         u32 reg;
 662
 663         rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
 664
 665         rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, 70);
 666         rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, 30);
 667
 668         if (rt2x00dev->led_mode == LED_MODE_TXRX_ACTIVITY) {
 669                 rt2x00_set_field32(&reg, LEDCSR_LINK, 1);
 670                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 0);
 671         } else if (rt2x00dev->led_mode == LED_MODE_ASUS) {
 672                 rt2x00_set_field32(&reg, LEDCSR_LINK, 0);
 673                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 1);
 674         } else {
 675                 rt2x00_set_field32(&reg, LEDCSR_LINK, 1);
 676                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 1);
 677         }
 678
 679         rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
 680 }
 681
 682 static void rt2500pci_disable_led(struct rt2x00_dev *rt2x00dev)
 683 {
 684         u32 reg;
 685
 686         rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
 687         rt2x00_set_field32(&reg, LEDCSR_LINK, 0);
 688         rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 0);
 689         rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
 690 }
 691
 692 /*
 693  * Link tuning
 694  */
 695 static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev, int rssi)
 696 {
 697         u32 reg;
 698         u8 r17;
 699
 700         /*
 701          * To prevent collisions with MAC ASIC on chipsets
 702          * up to version C the link tuning should halt after 20
 703          * seconds.
 704          */
 705         if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D &&
 706             rt2x00dev->link.count > 20)
 707                 return;
 708
 709         rt2500pci_bbp_read(rt2x00dev, 17, &r17);
 710
 711         /*
 712          * Chipset versions C and lower should directly continue
 713          * to the dynamic CCA tuning.
 714          */
 715         if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D)
 716                 goto dynamic_cca_tune;
 717
 718         /*
 719          * A too low RSSI will cause too much false CCA which will
 720          * then corrupt the R17 tuning. To remidy this the tuning should
 721          * be stopped (While making sure the R17 value will not exceed limits)
 722          */
 723         if (rssi < -80 && rt2x00dev->link.count > 20) {
 724                 if (r17 >= 0x41) {
 725                         r17 = rt2x00dev->link.curr_noise;
 726                         rt2500pci_bbp_write(rt2x00dev, 17, r17);
 727                 }
 728                 return;
 729         }
 730
 731         /*
 732          * Special big-R17 for short distance
 733          */
 734         if (rssi >= -58) {
 735                 if (r17 != 0x50)
 736                         rt2500pci_bbp_write(rt2x00dev, 17, 0x50);
 737                 return;
 738         }
 739
 740         /*
 741          * Special mid-R17 for middle distance
 742          */
 743         if (rssi >= -74) {
 744                 if (r17 != 0x41)
 745                         rt2500pci_bbp_write(rt2x00dev, 17, 0x41);
 746                 return;
 747         }
 748
 749         /*
 750          * Leave short or middle distance condition, restore r17
 751          * to the dynamic tuning range.
 752          */
 753         if (r17 >= 0x41) {
 754                 rt2500pci_bbp_write(rt2x00dev, 17, rt2x00dev->link.curr_noise);
 755                 return;
 756         }
 757
 758 dynamic_cca_tune:
 759
 760         /*
 761          * R17 is inside the dynamic tuning range,
 762          * start tuning the link based on the false cca counter.
 763          */
 764         rt2x00pci_register_read(rt2x00dev, CNT3, &reg);
 765         rt2x00dev->link.false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA);
 766
 767         if (rt2x00dev->link.false_cca > 512 && r17 < 0x40) {
 768                 rt2500pci_bbp_write(rt2x00dev, 17, ++r17);
 769                 rt2x00dev->link.curr_noise = r17;
 770         } else if (rt2x00dev->link.false_cca < 100 && r17 > 0x32) {
 771                 rt2500pci_bbp_write(rt2x00dev, 17, --r17);
 772                 rt2x00dev->link.curr_noise = r17;
 773         }
 774 }
 775
 776 /*
 777  * Initialization functions.
 778  */
 779 static void rt2500pci_init_rxring(struct rt2x00_dev *rt2x00dev)
 780 {
 781         struct data_desc *rxd;
 782         unsigned int i;
 783         u32 word;
 784
 785         memset(rt2x00dev->rx->data_addr, 0x00,
 786                 rt2x00_get_ring_size(rt2x00dev->rx));
 787
 788         for (i = 0; i < rt2x00dev->rx->stats.limit; i++) {
 789                 rxd = rt2x00dev->rx->entry[i].priv;
 790
 791                 rt2x00_desc_read(rxd, 1, &word);
 792                 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS,
 793                         rt2x00dev->rx->entry[i].data_dma);
 794                 rt2x00_desc_write(rxd, 1, word);
 795
 796                 rt2x00_desc_read(rxd, 0, &word);
 797                 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
 798                 rt2x00_desc_write(rxd, 0, word);
 799         }
 800
 801         rt2x00_ring_index_clear(rt2x00dev->rx);
 802 }
 803
 804 static void rt2500pci_init_txring(struct rt2x00_dev *rt2x00dev,
 805         const int queue)
 806 {
 807         struct data_ring *ring = rt2x00_get_ring(rt2x00dev, queue);
 808         struct data_desc *txd;
 809         unsigned int i;
 810         u32 word;
 811
 812         memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
 813
 814         for (i = 0; i < ring->stats.limit; i++) {
 815                 txd = ring->entry[i].priv;
 816
 817                 rt2x00_desc_read(txd, 1, &word);
 818                 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS,
 819                         ring->entry[i].data_dma);
 820                 rt2x00_desc_write(txd, 1, word);
 821
 822                 rt2x00_desc_read(txd, 0, &word);
 823                 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
 824                 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
 825                 rt2x00_desc_write(txd, 0, word);
 826         }
 827
 828         rt2x00_ring_index_clear(ring);
 829 }
 830
 831 static int rt2500pci_init_rings(struct rt2x00_dev *rt2x00dev)
 832 {
 833         u32 reg;
 834
 835         /*
 836          * Initialize rings.
 837          */
 838         rt2500pci_init_rxring(rt2x00dev);
 839         rt2500pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
 840         rt2500pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
 841         rt2500pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON);
 842         rt2500pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
 843
 844         /*
 845          * Initialize registers.
 846          */
 847         rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
 848         rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE,
 849                 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].desc_size);
 850         rt2x00_set_field32(&reg, TXCSR2_NUM_TXD,
 851                 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].stats.limit);
 852         rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM,
 853                 rt2x00dev->bcn[1].stats.limit);
 854         rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO,
 855                 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].stats.limit);
 856         rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
 857
 858         rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
 859         rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
 860                 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].data_dma);
 861         rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
 862
 863         rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
 864         rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
 865                 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].data_dma);
 866         rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
 867
 868         rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
 869         rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
 870                 rt2x00dev->bcn[1].data_dma);
 871         rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
 872
 873         rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
 874         rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
 875                 rt2x00dev->bcn[0].data_dma);
 876         rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
 877
 878         rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
 879         rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE,
 880                 rt2x00dev->rx->desc_size);
 881         rt2x00_set_field32(&reg, RXCSR1_NUM_RXD,
 882                 rt2x00dev->rx->stats.limit);
 883         rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
 884
 885         rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
 886         rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
 887                 rt2x00dev->rx->data_dma);
 888         rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
 889
 890         return 0;
 891 }
 892
 893 static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
 894 {
 895         u32 reg;
 896
 897         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
 898                 return -EBUSY;
 899
 900         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
 901         rt2x00pci_register_write(rt2x00dev, PCICSR, 0x000003b8);
 902
 903         rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
 904         rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
 905         rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00020002);
 906         rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
 907
 908         rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
 909         rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
 910         rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
 911         rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
 912         rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
 913
 914         rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
 915         rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
 916                 rt2x00dev->rx->data_size / 128);
 917         rt2x00pci_register_write(rt2x00dev, CSR9, reg);
 918
 919         rt2x00pci_register_write(rt2x00dev, CNT3, 0);
 920
 921         rt2x00pci_register_write(rt2x00dev, GPIOCSR, 0x0000ff00);
 922         rt2x00pci_register_write(rt2x00dev, TESTCSR, 0x000000f0);
 923
 924         rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00213223);
 925         rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
 926
 927         rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
 928         rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
 929         rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
 930
 931         /*
 932          * Always use CWmin and CWmax set in descriptor.
 933          */
 934         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 935         rt2x00_set_field32(&reg, CSR11_CW_SELECT, 0);
 936         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 937
 938         rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
 939         /*
 940          * Signal.
 941          */
 942         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 47);
 943         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
 944         /*
 945          * Rssi.
 946          */
 947         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 51);
 948         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
 949         /*
 950          * OFDM Rate.
 951          */
 952         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 42);
 953         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
 954         /*
 955          * OFDM.
 956          */
 957         rt2x00_set_field32(&reg, RXCSR3_BBP_ID3, 51);
 958         rt2x00_set_field32(&reg, RXCSR3_BBP_ID3_VALID, 1);
 959         rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
 960
 961         rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
 962         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
 963         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 26);
 964         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID0, 1);
 965         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
 966         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 26);
 967         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID1, 1);
 968         rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
 969
 970         rt2x00pci_register_write(rt2x00dev, BBPCSR1, 0x82188200);
 971
 972         rt2x00pci_register_write(rt2x00dev, TXACKCSR0, 0x00000020);
 973
 974         rt2x00pci_register_write(rt2x00dev, ARTCSR0, 0x7038140a);
 975         rt2x00pci_register_write(rt2x00dev, ARTCSR1, 0x1d21252d);
 976         rt2x00pci_register_write(rt2x00dev, ARTCSR2, 0x1919191d);
 977
 978         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
 979         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
 980         rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
 981         rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
 982         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
 983
 984         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
 985         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
 986         rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
 987         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
 988
 989         /*
 990          * We must clear the FCS and FIFO error count.
 991          * These registers are cleared on read,
 992          * so we may pass a useless variable to store the value.
 993          */
 994         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 995         rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
 996
 997         return 0;
 998 }
 999
1000 static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1001 {
1002         unsigned int i;
1003         u16 eeprom;
1004         u8 reg_id;
1005         u8 value;
1006
1007         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1008                 rt2500pci_bbp_read(rt2x00dev, 0, &value);
1009                 if ((value != 0xff) && (value != 0x00))
1010                         goto continue_csr_init;
1011                 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
1012                 udelay(REGISTER_BUSY_DELAY);
1013         }
1014
1015         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1016         return -EACCES;
1017
1018 continue_csr_init:
1019         rt2500pci_bbp_write(rt2x00dev, 3, 0x02);
1020         rt2500pci_bbp_write(rt2x00dev, 4, 0x19);
1021         rt2500pci_bbp_write(rt2x00dev, 14, 0x1c);
1022         rt2500pci_bbp_write(rt2x00dev, 15, 0x30);
1023         rt2500pci_bbp_write(rt2x00dev, 16, 0xac);
1024         rt2500pci_bbp_write(rt2x00dev, 17, 0x48);
1025         rt2500pci_bbp_write(rt2x00dev, 18, 0x18);
1026         rt2500pci_bbp_write(rt2x00dev, 19, 0xff);
1027         rt2500pci_bbp_write(rt2x00dev, 20, 0x1e);
1028         rt2500pci_bbp_write(rt2x00dev, 21, 0x08);
1029         rt2500pci_bbp_write(rt2x00dev, 22, 0x08);
1030         rt2500pci_bbp_write(rt2x00dev, 23, 0x08);
1031         rt2500pci_bbp_write(rt2x00dev, 24, 0x70);
1032         rt2500pci_bbp_write(rt2x00dev, 25, 0x40);
1033         rt2500pci_bbp_write(rt2x00dev, 26, 0x08);
1034         rt2500pci_bbp_write(rt2x00dev, 27, 0x23);
1035         rt2500pci_bbp_write(rt2x00dev, 30, 0x10);
1036         rt2500pci_bbp_write(rt2x00dev, 31, 0x2b);
1037         rt2500pci_bbp_write(rt2x00dev, 32, 0xb9);
1038         rt2500pci_bbp_write(rt2x00dev, 34, 0x12);
1039         rt2500pci_bbp_write(rt2x00dev, 35, 0x50);
1040         rt2500pci_bbp_write(rt2x00dev, 39, 0xc4);
1041         rt2500pci_bbp_write(rt2x00dev, 40, 0x02);
1042         rt2500pci_bbp_write(rt2x00dev, 41, 0x60);
1043         rt2500pci_bbp_write(rt2x00dev, 53, 0x10);
1044         rt2500pci_bbp_write(rt2x00dev, 54, 0x18);
1045         rt2500pci_bbp_write(rt2x00dev, 56, 0x08);
1046         rt2500pci_bbp_write(rt2x00dev, 57, 0x10);
1047         rt2500pci_bbp_write(rt2x00dev, 58, 0x08);
1048         rt2500pci_bbp_write(rt2x00dev, 61, 0x6d);
1049         rt2500pci_bbp_write(rt2x00dev, 62, 0x10);
1050
1051         DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
1052         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1053                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1054
1055                 if (eeprom != 0xffff && eeprom != 0x0000) {
1056                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1057                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1058                         DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
1059                                 reg_id, value);
1060                         rt2500pci_bbp_write(rt2x00dev, reg_id, value);
1061                 }
1062         }
1063         DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
1064
1065         return 0;
1066 }
1067
1068 /*
1069  * Device state switch handlers.
1070  */
1071 static void rt2500pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1072         enum dev_state state)
1073 {
1074         u32 reg;
1075
1076         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1077         rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
1078                 state == STATE_RADIO_RX_OFF);
1079         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1080 }
1081
1082 static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1083 {
1084         u32 reg;
1085
1086         /*
1087          * Initialize all registers.
1088          */
1089         if (rt2500pci_init_rings(rt2x00dev) ||
1090             rt2500pci_init_registers(rt2x00dev) ||
1091             rt2500pci_init_bbp(rt2x00dev)) {
1092                 ERROR(rt2x00dev, "Register initialization failed.\n");
1093                 return -EIO;
1094         }
1095
1096         /*
1097          * Clear interrupts.
1098          */
1099         rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1100         rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1101
1102         /*
1103          * Enable interrupts.
1104          */
1105         rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1106         rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, 0);
1107         rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, 0);
1108         rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, 0);
1109         rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, 0);
1110         rt2x00_set_field32(&reg, CSR8_RXDONE, 0);
1111         rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1112
1113         /*
1114          * Enable LED
1115          */
1116         rt2500pci_enable_led(rt2x00dev);
1117
1118         return 0;
1119 }
1120
1121 static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1122 {
1123         u32 reg;
1124
1125         /*
1126          * Disable LED
1127          */
1128         rt2500pci_disable_led(rt2x00dev);
1129
1130         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
1131
1132         /*
1133          * Disable synchronisation.
1134          */
1135         rt2x00pci_register_write(rt2x00dev, CSR14, 0);
1136
1137         /*
1138          * Cancel RX and TX.
1139          */
1140         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1141         rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
1142         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1143
1144         /*
1145          * Disable interrupts.
1146          */
1147         rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1148         rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, 1);
1149         rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, 1);
1150         rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, 1);
1151         rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, 1);
1152         rt2x00_set_field32(&reg, CSR8_RXDONE, 1);
1153         rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1154 }
1155
1156 static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
1157         enum dev_state state)
1158 {
1159         u32 reg;
1160         unsigned int i;
1161         char put_to_sleep;
1162         char bbp_state;
1163         char rf_state;
1164
1165         put_to_sleep = (state != STATE_AWAKE);
1166
1167         rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1168         rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1169         rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1170         rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1171         rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1172         rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1173
1174         /*
1175          * Device is not guaranteed to be in the requested state yet.
1176          * We must wait until the register indicates that the
1177          * device has entered the correct state.
1178          */
1179         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1180                 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1181                 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
1182                 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
1183                 if (bbp_state == state && rf_state == state)
1184                         return 0;
1185                 msleep(10);
1186         }
1187
1188         NOTICE(rt2x00dev, "Device failed to enter state %d, "
1189                 "current device state: bbp %d and rf %d.\n",
1190                 state, bbp_state, rf_state);
1191
1192         return -EBUSY;
1193 }
1194
1195 static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1196         enum dev_state state)
1197 {
1198         int retval = 0;
1199
1200         switch (state) {
1201                 case STATE_RADIO_ON:
1202                         retval = rt2500pci_enable_radio(rt2x00dev);
1203                 break;
1204                 case STATE_RADIO_OFF:
1205                         rt2500pci_disable_radio(rt2x00dev);
1206                 break;
1207                 case STATE_RADIO_RX_ON:
1208                 case STATE_RADIO_RX_OFF:
1209                         rt2500pci_toggle_rx(rt2x00dev, state);
1210                 break;
1211                 case STATE_DEEP_SLEEP:
1212                 case STATE_SLEEP:
1213                 case STATE_STANDBY:
1214                 case STATE_AWAKE:
1215                         retval = rt2500pci_set_state(rt2x00dev, state);
1216                 break;
1217                 default:
1218                         retval = -ENOTSUPP;
1219                 break;
1220         }
1221
1222         return retval;
1223 }
1224
1225 /*
1226  * TX descriptor initialization
1227  */
1228 static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1229         struct data_entry *entry, struct data_desc *txd,
1230         struct data_entry_desc *desc, struct ieee80211_hdr *ieee80211hdr,
1231         unsigned int length, struct ieee80211_tx_control *control)
1232 {
1233         u32 word;
1234
1235         /*
1236          * Start writing the descriptor words.
1237          */
1238         rt2x00_desc_read(txd, 2, &word);
1239         rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
1240         rt2x00_set_field32(&word, TXD_W2_AIFS, entry->ring->tx_params.aifs);
1241         rt2x00_set_field32(&word, TXD_W2_CWMIN, entry->ring->tx_params.cw_min);
1242         rt2x00_set_field32(&word, TXD_W2_CWMAX, entry->ring->tx_params.cw_max);
1243         rt2x00_desc_write(txd, 2, word);
1244
1245         rt2x00_desc_read(txd, 3, &word);
1246         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, desc->signal);
1247         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, desc->service);
1248         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, desc->length_low);
1249         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH, desc->length_high);
1250         rt2x00_desc_write(txd, 3, word);
1251
1252         rt2x00_desc_read(txd, 10, &word);
1253         rt2x00_set_field32(&word, TXD_W10_RTS,
1254                 test_bit(ENTRY_TXD_RTS_FRAME, &entry->flags));
1255         rt2x00_desc_write(txd, 10, word);
1256
1257         rt2x00_desc_read(txd, 0, &word);
1258         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1259         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1260         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1261                 test_bit(ENTRY_TXD_MORE_FRAG, &entry->flags));
1262         rt2x00_set_field32(&word, TXD_W0_ACK,
1263                 test_bit(ENTRY_TXD_REQ_ACK, &entry->flags));
1264         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1265                 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &entry->flags));
1266         rt2x00_set_field32(&word, TXD_W0_OFDM,
1267                 test_bit(ENTRY_TXD_OFDM_RATE, &entry->flags));
1268         rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);
1269         rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs);
1270         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, 0);
1271         rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, length);
1272         rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1273         rt2x00_desc_write(txd, 0, word);
1274 }
1275
1276 /*
1277  * TX data initialization
1278  */
1279 static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev, int queue)
1280 {
1281         u32 reg;
1282
1283         if (queue == IEEE80211_TX_QUEUE_BEACON) {
1284                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1285                 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1286                         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1287                         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1288                 }
1289                 return;
1290         }
1291
1292         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1293         if (queue == IEEE80211_TX_QUEUE_DATA0)
1294                 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, 1);
1295         else if (queue == IEEE80211_TX_QUEUE_DATA1)
1296                 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, 1);
1297         else if (queue == IEEE80211_TX_QUEUE_AFTER_BEACON)
1298                 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, 1);
1299         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1300 }
1301
1302 /*
1303  * Interrupt functions.
1304  */
1305 static void rt2500pci_rxdone(struct rt2x00_dev *rt2x00dev)
1306 {
1307         struct data_ring *ring = rt2x00dev->rx;
1308         struct data_entry *entry;
1309         struct data_desc *rxd;
1310         u32 word0;
1311         u32 word2;
1312         int signal;
1313         int rssi;
1314         int ofdm;
1315         u16 size;
1316
1317         while (1) {
1318                 entry = rt2x00_get_data_entry(ring);
1319                 rxd = entry->priv;
1320                 rt2x00_desc_read(rxd, 0, &word0);
1321                 rt2x00_desc_read(rxd, 2, &word2);
1322
1323                 if (rt2x00_get_field32(word0, RXD_W0_OWNER_NIC))
1324                         break;
1325
1326                 /*
1327                  * TODO: Don't we need to keep statistics
1328                  * updated about events like CRC and physical errors?
1329                  */
1330                 if (rt2x00_get_field32(word0, RXD_W0_CRC) ||
1331                     rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1332                         goto skip_entry;
1333
1334                 /*
1335                  * Obtain the status about this packet.
1336                  */
1337                 size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1338                 signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1339                 rssi = rt2x00_get_field32(word2, RXD_W2_RSSI);
1340                 ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
1341
1342                 /*
1343                  * Send the packet to upper layer.
1344                  */
1345                 rt2x00lib_rxdone(entry, entry->data_addr, size,
1346                         signal, rssi, ofdm);
1347
1348 skip_entry:
1349                 if (test_bit(DEVICE_ENABLED_RADIO, &ring->rt2x00dev->flags)) {
1350                         rt2x00_set_field32(&word0, RXD_W0_OWNER_NIC, 1);
1351                         rt2x00_desc_write(rxd, 0, word0);
1352                 }
1353
1354                 rt2x00_ring_index_inc(ring);
1355         }
1356 }
1357
1358 static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev, const int queue)
1359 {
1360         struct data_ring *ring = rt2x00_get_ring(rt2x00dev, queue);
1361         struct data_entry *entry;
1362         struct data_desc *txd;
1363         u32 word;
1364         int tx_status;
1365         int retry;
1366
1367         while (!rt2x00_ring_empty(ring)) {
1368                 entry = rt2x00_get_data_entry_done(ring);
1369                 txd = entry->priv;
1370                 rt2x00_desc_read(txd, 0, &word);
1371
1372                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1373                     !rt2x00_get_field32(word, TXD_W0_VALID))
1374                         break;
1375
1376                 /*
1377                  * Obtain the status about this packet.
1378                  */
1379                 tx_status = rt2x00_get_field32(word, TXD_W0_RESULT);
1380                 retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1381
1382                 rt2x00lib_txdone(entry, tx_status, retry);
1383
1384                 /*
1385                  * Make this entry available for reuse.
1386                  */
1387                 entry->flags = 0;
1388                 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1389                 rt2x00_desc_write(txd, 0, word);
1390                 rt2x00_ring_index_done_inc(ring);
1391         }
1392
1393         /*
1394          * If the data ring was full before the txdone handler
1395          * we must make sure the packet queue in the mac80211 stack
1396          * is reenabled when the txdone handler has finished.
1397          */
1398         entry = ring->entry;
1399         if (!rt2x00_ring_full(ring))
1400                 ieee80211_wake_queue(rt2x00dev->hw,
1401                         entry->tx_status.control.queue);
1402 }
1403
1404 static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
1405 {
1406         struct rt2x00_dev *rt2x00dev = dev_instance;
1407         u32 reg;
1408
1409         /*
1410          * Get the interrupt sources & saved to local variable.
1411          * Write register value back to clear pending interrupts.
1412          */
1413         rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1414         rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1415
1416         if (!reg)
1417                 return IRQ_NONE;
1418
1419         if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1420                 return IRQ_HANDLED;
1421
1422         /*
1423          * Handle interrupts, walk through all bits
1424          * and run the tasks, the bits are checked in order of
1425          * priority.
1426          */
1427
1428         /*
1429          * 1 - Beacon timer expired interrupt.
1430          */
1431         if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1432                 rt2x00pci_beacondone(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
1433
1434         /*
1435          * 2 - Rx ring done interrupt.
1436          */
1437         if (rt2x00_get_field32(reg, CSR7_RXDONE))
1438                 rt2500pci_rxdone(rt2x00dev);
1439
1440         /*
1441          * 3 - Atim ring transmit done interrupt.
1442          */
1443         if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1444                 rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON);
1445
1446         /*
1447          * 4 - Priority ring transmit done interrupt.
1448          */
1449         if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1450                 rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
1451
1452         /*
1453          * 5 - Tx ring transmit done interrupt.
1454          */
1455         if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1456                 rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
1457
1458         return IRQ_HANDLED;
1459 }
1460
1461 /*
1462  * Device initialization functions.
1463  */
1464 static int rt2500pci_alloc_eeprom(struct rt2x00_dev *rt2x00dev)
1465 {
1466         struct eeprom_93cx6 eeprom;
1467         u32 reg;
1468         u16 word;
1469
1470         /*
1471          * Allocate the eeprom memory, check the eeprom width
1472          * and copy the entire eeprom into this allocated memory.
1473          */
1474         rt2x00dev->eeprom = kzalloc(EEPROM_SIZE, GFP_KERNEL);
1475         if (!rt2x00dev->eeprom)
1476                 return -ENOMEM;
1477
1478         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1479
1480         eeprom.data = rt2x00dev;
1481         eeprom.register_read = rt2500pci_eepromregister_read;
1482         eeprom.register_write = rt2500pci_eepromregister_write;
1483         eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1484                 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1485         eeprom.reg_data_in = 0;
1486         eeprom.reg_data_out = 0;
1487         eeprom.reg_data_clock = 0;
1488         eeprom.reg_chip_select = 0;
1489
1490         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1491                 EEPROM_SIZE / sizeof(u16));
1492
1493         /*
1494          * Start validation of the data that has been read.
1495          */
1496         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1497         if (word == 0xffff) {
1498                 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1499                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT, 0);
1500                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT, 0);
1501                 rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE, 0);
1502                 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1503                 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1504                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522);
1505                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1506                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1507         }
1508
1509         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1510         if (word == 0xffff) {
1511                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1512                 rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0);
1513                 rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0);
1514                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1515                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1516         }
1517
1518         rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word);
1519         if (word == 0xffff) {
1520                 rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
1521                         MAX_RX_SSI);
1522                 rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
1523                 EEPROM(rt2x00dev, "Calibrate offset: 0x%04x\n", word);
1524         }
1525
1526         return 0;
1527 }
1528
1529 static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1530 {
1531         u32 reg;
1532         u16 value;
1533         u16 eeprom;
1534
1535         /*
1536          * Read EEPROM word for configuration.
1537          */
1538         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1539
1540         /*
1541          * Identify RF chipset.
1542          */
1543         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1544         rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1545         rt2x00_set_chip(rt2x00dev, RT2560, value, reg);
1546
1547         if (!rt2x00_rf(&rt2x00dev->chip, RF2522) &&
1548             !rt2x00_rf(&rt2x00dev->chip, RF2523) &&
1549             !rt2x00_rf(&rt2x00dev->chip, RF2524) &&
1550             !rt2x00_rf(&rt2x00dev->chip, RF2525) &&
1551             !rt2x00_rf(&rt2x00dev->chip, RF2525E) &&
1552             !rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1553                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1554                 return -ENODEV;
1555         }
1556
1557         /*
1558          * Identify default antenna configuration.
1559          */
1560         rt2x00dev->hw->conf.antenna_sel_tx = rt2x00_get_field16(eeprom,
1561                 EEPROM_ANTENNA_TX_DEFAULT);
1562         rt2x00dev->hw->conf.antenna_sel_rx = rt2x00_get_field16(eeprom,
1563                 EEPROM_ANTENNA_RX_DEFAULT);
1564
1565         /*
1566          * Store led mode, for correct led behaviour.
1567          */
1568         rt2x00dev->led_mode = rt2x00_get_field16(eeprom,
1569                 EEPROM_ANTENNA_LED_MODE);
1570
1571         /*
1572          * Detect if this device has an hardware controlled radio.
1573          */
1574         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1575                 __set_bit(DEVICE_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1576
1577         /*
1578          * Check if the BBP tuning should be enabled.
1579          */
1580         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1581
1582         if (rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE))
1583                 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1584
1585         /*
1586          * Read the RSSI <-> dBm offset information.
1587          */
1588         rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom);
1589         rt2x00dev->hw->max_rssi =
1590                 rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
1591
1592         return 0;
1593 }
1594
1595 static const struct {
1596         unsigned int chip;
1597         u32 val[3];
1598 } rf_vals[] = {
1599         { RF2522,       { 0x00002050, 0x00000101, 0x00000000 } },
1600         { RF2523,       { 0x00022010, 0x000e0111, 0x00000a1b } },
1601         { RF2524,       { 0x00032020, 0x00000101, 0x00000a1b } },
1602         { RF2525,       { 0x00022020, 0x00060111, 0x00000a1b } },
1603         { RF2525E,      { 0x00022020, 0x00060111, 0x00000a0b } },
1604         { RF5222,       { 0x00000000, 0x00000101, 0x00000000 } },
1605 };
1606
1607 /*
1608  * RF value list for RF2522
1609  * Supports: 2.4 GHz
1610  */
1611 static const u32 rf_vals_bg_2522[] = {
1612         0x000c1fda, 0x000c1fee, 0x000c2002, 0x000c2016, 0x000c202a,
1613         0x000c203e, 0x000c2052, 0x000c2066, 0x000c207a, 0x000c208e,
1614         0x000c20a2, 0x000c20b6, 0x000c20ca, 0x000c20fa
1615 };
1616
1617 /*
1618  * RF value list for RF2523, RF2524 & RF2525
1619  * Supports: 2.4 GHz
1620  */
1621 static const u32 rf_vals_bg_252x[] = {
1622         0x00000c9e, 0x00000ca2, 0x00000ca6, 0x00000caa, 0x00000cae,
1623         0x00000cb2, 0x00000cb6, 0x00000cba, 0x00000cbe, 0x00000d02,
1624         0x00000d06, 0x00000d0a, 0x00000d0e, 0x00000d1a
1625 };
1626
1627 /*
1628  * RF value list for RF2525E & RF5222
1629  * Supports: 2.4 GHz
1630  */
1631 static const u32 rf_vals_bg_5x[] = {
1632         0x00001136, 0x0000113a, 0x0000113e, 0x00001182, 0x00001186,
1633         0x0000118a, 0x0000118e, 0x00001192, 0x00001196, 0x0000119a,
1634         0x0000119e, 0x000011a2, 0x000011a6, 0x000011ae
1635 };
1636
1637 /*
1638  * RF value list for RF5222 (supplement to rf_vals_bg_5x)
1639  * Supports: 5.2 GHz
1640  */
1641 static const u32 rf_vals_a_5x[] = {
1642         0x00018896, 0x0001889a, 0x0001889e, 0x000188a2, 0x000188a6,
1643         0x000188aa, 0x000188ae, 0x000188b2, 0x00008802, 0x00008806,
1644         0x0000880a, 0x0000880e, 0x00008812, 0x00008816, 0x0000881a,
1645         0x0000881e, 0x00008822, 0x00008826, 0x0000882a, 0x000090a6,
1646         0x000090ae, 0x000090b6, 0x000090be
1647 };
1648
1649 static void rt2500pci_init_hw_mode(struct rt2x00_dev *rt2x00dev)
1650 {
1651         struct hw_mode_spec *spec = &rt2x00dev->spec;
1652         u8 *txpower;
1653         unsigned int i;
1654
1655         /*
1656          * Initialize all hw fields.
1657          */
1658         rt2x00dev->hw->flags =  IEEE80211_HW_HOST_GEN_BEACON |
1659                 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1660                 IEEE80211_HW_WEP_INCLUDE_IV |
1661                 IEEE80211_HW_DATA_NULLFUNC_ACK |
1662                 IEEE80211_HW_NO_TKIP_WMM_HWACCEL |
1663                 IEEE80211_HW_MONITOR_DURING_OPER;
1664         rt2x00dev->hw->extra_tx_headroom = 0;
1665         rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1666         rt2x00dev->hw->max_noise = MAX_RX_NOISE;
1667         rt2x00dev->hw->queues = 2;
1668
1669         /*
1670          * This device supports ATIM
1671          */
1672         __set_bit(DEVICE_SUPPORT_ATIM, &rt2x00dev->flags);
1673
1674         /*
1675          * Set device specific, but channel independent RF values.
1676          */
1677         for (i = 0; i < ARRAY_SIZE(rf_vals); i++) {
1678                 if (rt2x00_rf(&rt2x00dev->chip, rf_vals[i].chip)) {
1679                         rt2x00dev->rf1 = rf_vals[i].val[0];
1680                         rt2x00dev->rf3 = rf_vals[i].val[1];
1681                         rt2x00dev->rf4 = rf_vals[i].val[2];
1682                 }
1683         }
1684
1685         /*
1686          * Convert tx_power array in eeprom.
1687          */
1688         txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1689         for (i = 0; i < 14; i++)
1690                 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1691
1692         /*
1693          * Initialize hw_mode information.
1694          */
1695         spec->mac_addr = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1696         spec->num_modes = 2;
1697         spec->num_rates = 12;
1698         spec->num_channels = 14;
1699         spec->tx_power_a = NULL;
1700         spec->tx_power_bg = txpower;
1701         spec->tx_power_default = DEFAULT_TXPOWER;
1702         spec->chan_val_a = NULL;
1703
1704         if (rt2x00_rf(&rt2x00dev->chip, RF2522))
1705                 spec->chan_val_bg = rf_vals_bg_2522;
1706         else if (rt2x00_rf(&rt2x00dev->chip, RF2523) ||
1707                  rt2x00_rf(&rt2x00dev->chip, RF2524) ||
1708                  rt2x00_rf(&rt2x00dev->chip, RF2525))
1709                 spec->chan_val_bg = rf_vals_bg_252x;
1710         else if (rt2x00_rf(&rt2x00dev->chip, RF2525E) ||
1711                  rt2x00_rf(&rt2x00dev->chip, RF5222))
1712                 spec->chan_val_bg = rf_vals_bg_5x;
1713
1714         if (rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1715                 spec->num_modes = 3;
1716                 spec->num_channels += 23;
1717                 spec->chan_val_a = rf_vals_a_5x;
1718         }
1719 }
1720
1721 static int rt2500pci_init_hw(struct rt2x00_dev *rt2x00dev)
1722 {
1723         int retval;
1724
1725         /*
1726          * Allocate eeprom data.
1727          */
1728         retval = rt2500pci_alloc_eeprom(rt2x00dev);
1729         if (retval)
1730                 return retval;
1731
1732         retval = rt2500pci_init_eeprom(rt2x00dev);
1733         if (retval)
1734                 return retval;
1735
1736         /*
1737          * Initialize hw specifications.
1738          */
1739         rt2500pci_init_hw_mode(rt2x00dev);
1740
1741         return 0;
1742 }
1743
1744 /*
1745  * IEEE80211 stack callback functions.
1746  */
1747 static int rt2500pci_get_stats(struct ieee80211_hw *hw,
1748         struct ieee80211_low_level_stats *stats)
1749 {
1750         struct rt2x00_dev *rt2x00dev = hw->priv;
1751         u32 reg;
1752
1753         /*
1754          * Update FCS error count from register.
1755          * The dot11ACKFailureCount, dot11RTSFailureCount and
1756          * dot11RTSSuccessCount are updated in interrupt time.
1757          */
1758         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
1759         rt2x00dev->low_level_stats.dot11FCSErrorCount +=
1760                 rt2x00_get_field32(reg, CNT0_FCS_ERROR);
1761
1762         memcpy(stats, &rt2x00dev->low_level_stats, sizeof(*stats));
1763
1764         return 0;
1765 }
1766
1767 static int rt2500pci_set_retry_limit(struct ieee80211_hw *hw,
1768         u32 short_retry, u32 long_retry)
1769 {
1770         struct rt2x00_dev *rt2x00dev = hw->priv;
1771         u32 reg;
1772
1773         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
1774         rt2x00_set_field32(&reg, CSR11_LONG_RETRY, long_retry);
1775         rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, short_retry);
1776         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
1777
1778         return 0;
1779 }
1780
1781 static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw)
1782 {
1783         struct rt2x00_dev *rt2x00dev = hw->priv;
1784         u64 tsf;
1785         u32 reg;
1786
1787         rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1788         tsf = (u64)rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1789         rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1790         tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1791
1792         return tsf;
1793 }
1794
1795 static void rt2500pci_reset_tsf(struct ieee80211_hw *hw)
1796 {
1797         struct rt2x00_dev *rt2x00dev = hw->priv;
1798
1799         rt2x00pci_register_write(rt2x00dev, CSR16, 0);
1800         rt2x00pci_register_write(rt2x00dev, CSR17, 0);
1801 }
1802
1803 static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw)
1804 {
1805         struct rt2x00_dev *rt2x00dev = hw->priv;
1806         u32 reg;
1807
1808         rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1809         return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1810 }
1811
1812 static const struct ieee80211_ops rt2500pci_mac80211_ops = {
1813         .tx                     = rt2x00lib_tx,
1814         .reset                  = rt2x00lib_reset,
1815         .open                   = rt2x00lib_open,
1816         .stop                   = rt2x00lib_stop,
1817         .add_interface          = rt2x00lib_add_interface,
1818         .remove_interface       = rt2x00lib_remove_interface,
1819         .config                 = rt2x00lib_config,
1820         .config_interface       = rt2x00lib_config_interface,
1821         .set_multicast_list     = rt2x00lib_set_multicast_list,
1822         .get_stats              = rt2500pci_get_stats,
1823         .set_retry_limit        = rt2500pci_set_retry_limit,
1824         .conf_tx                = rt2x00lib_conf_tx,
1825         .get_tx_stats           = rt2x00lib_get_tx_stats,
1826         .get_tsf                = rt2500pci_get_tsf,
1827         .reset_tsf              = rt2500pci_reset_tsf,
1828         .beacon_update          = rt2x00pci_beacon_update,
1829         .tx_last_beacon         = rt2500pci_tx_last_beacon,
1830 };
1831
1832 static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
1833         .irq_handler            = rt2500pci_interrupt,
1834         .init_hw                = rt2500pci_init_hw,
1835         .initialize             = rt2x00pci_initialize,
1836         .uninitialize           = rt2x00pci_uninitialize,
1837         .set_device_state       = rt2500pci_set_device_state,
1838 #ifdef CONFIG_RT2500PCI_RFKILL
1839         .rfkill_poll            = rt2500pci_rfkill_poll,
1840 #endif /* CONFIG_RT2500PCI_RFKILL */
1841         .link_tuner             = rt2500pci_link_tuner,
1842         .write_tx_desc          = rt2500pci_write_tx_desc,
1843         .write_tx_data          = rt2x00pci_write_tx_data,
1844         .kick_tx_queue          = rt2500pci_kick_tx_queue,
1845         .config_type            = rt2500pci_config_type,
1846         .config_phymode         = rt2500pci_config_phymode,
1847         .config_channel         = rt2500pci_config_channel,
1848         .config_mac_addr        = rt2500pci_config_mac_addr,
1849         .config_bssid           = rt2500pci_config_bssid,
1850         .config_promisc         = rt2500pci_config_promisc,
1851         .config_txpower         = rt2500pci_config_txpower,
1852         .config_antenna         = rt2500pci_config_antenna,
1853         .config_duration        = rt2500pci_config_duration,
1854 };
1855
1856 static const struct rt2x00_ops rt2500pci_ops = {
1857         .name   = DRV_NAME,
1858         .rxd_size = RXD_DESC_SIZE,
1859         .txd_size = TXD_DESC_SIZE,
1860         .lib    = &rt2500pci_rt2x00_ops,
1861         .hw     = &rt2500pci_mac80211_ops,
1862 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1863         .debugfs = &rt2500pci_rt2x00debug,
1864 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1865 };
1866
1867 /*
1868  * RT2500pci module information.
1869  */
1870 static struct pci_device_id rt2500pci_device_table[] = {
1871         { PCI_DEVICE(0x1814, 0x0201), PCI_DEVICE_DATA(&rt2500pci_ops) },
1872         { 0, }
1873 };
1874
1875 MODULE_AUTHOR(DRV_PROJECT);
1876 MODULE_VERSION(DRV_VERSION);
1877 MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver.");
1878 MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards");
1879 MODULE_DEVICE_TABLE(pci, rt2500pci_device_table);
1880 MODULE_LICENSE("GPL");
1881
1882 static struct pci_driver rt2500pci_driver = {
1883         .name           = DRV_NAME,
1884         .id_table       = rt2500pci_device_table,
1885         .probe          = rt2x00pci_probe,
1886         .remove         = __devexit_p(rt2x00pci_remove),
1887 #ifdef CONFIG_PM
1888         .suspend        = rt2x00pci_suspend,
1889         .resume         = rt2x00pci_resume,
1890 #endif /* CONFIG_PM */
1891 };
1892
1893 static int __init rt2500pci_init(void)
1894 {
1895         printk(KERN_INFO "Loading module: %s - %s by %s.\n",
1896                 DRV_NAME, DRV_VERSION, DRV_PROJECT);
1897         return pci_register_driver(&rt2500pci_driver);
1898 }
1899
1900 static void __exit rt2500pci_exit(void)
1901 {
1902         printk(KERN_INFO "Unloading module: %s.\n", DRV_NAME);
1903         pci_unregister_driver(&rt2500pci_driver);
1904 }
1905
1906 module_init(rt2500pci_init);
1907 module_exit(rt2500pci_exit);