package/rt2x00/src/rt2400pci.c

   1 /*
   2         Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt2400pci
  23         Abstract: rt2400pci device specific routines.
  24         Supported chipsets: RT2460.
  25  */
  26
  27 /*
  28  * Set enviroment defines for rt2x00.h
  29  */
  30 #define DRV_NAME "rt2400pci"
  31
  32 #include <linux/kernel.h>
  33 #include <linux/module.h>
  34 #include <linux/version.h>
  35 #include <linux/init.h>
  36 #include <linux/pci.h>
  37 #include <linux/dma-mapping.h>
  38 #include <linux/delay.h>
  39 #include <linux/etherdevice.h>
  40 #include <linux/eeprom_93cx6.h>
  41
  42 #include <asm/io.h>
  43
  44 #include "rt2x00.h"
  45 #include "rt2x00pci.h"
  46 #include "rt2400pci.h"
  47
  48 /*
  49  * Register access.
  50  * All access to the CSR registers will go through the methods
  51  * rt2x00pci_register_read and rt2x00pci_register_write.
  52  * BBP and RF register require indirect register access,
  53  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  54  * These indirect registers work with busy bits,
  55  * and we will try maximal REGISTER_BUSY_COUNT times to access
  56  * the register while taking a REGISTER_BUSY_DELAY us delay
  57  * between each attampt. When the busy bit is still set at that time,
  58  * the access attempt is considered to have failed,
  59  * and we will print an error.
  60  */
  61 static u32 rt2400pci_bbp_check(const struct rt2x00_dev *rt2x00dev)
  62 {
  63         u32 reg;
  64         unsigned int i;
  65
  66         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  67                 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
  68                 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
  69                         break;
  70                 udelay(REGISTER_BUSY_DELAY);
  71         }
  72
  73         return reg;
  74 }
  75
  76 static void rt2400pci_bbp_write(const struct rt2x00_dev *rt2x00dev,
  77         const u8 reg_id, const u8 value)
  78 {
  79         u32 reg;
  80
  81         /*
  82          *  Wait until the BBP becomes ready.
  83          */
  84         reg = rt2400pci_bbp_check(rt2x00dev);
  85         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
  86                 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
  87                 return;
  88         }
  89
  90         /*
  91          * Write the data into the BBP.
  92          */
  93         reg = 0;
  94         rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
  95         rt2x00_set_field32(&reg, BBPCSR_REGNUM, reg_id);
  96         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
  97         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
  98
  99         rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
 100 }
 101
 102 static void rt2400pci_bbp_read(const struct rt2x00_dev *rt2x00dev,
 103         const u8 reg_id, u8 *value)
 104 {
 105         u32 reg;
 106
 107         /*
 108          *  Wait until the BBP becomes ready.
 109          */
 110         reg = rt2400pci_bbp_check(rt2x00dev);
 111         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
 112                 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
 113                 return;
 114         }
 115
 116         /*
 117          * Write the request into the BBP.
 118          */
 119         reg = 0;
 120         rt2x00_set_field32(&reg, BBPCSR_REGNUM, reg_id);
 121         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
 122         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
 123
 124         rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
 125
 126         /*
 127          *  Wait until the BBP becomes ready.
 128          */
 129         reg = rt2400pci_bbp_check(rt2x00dev);
 130         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
 131                 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
 132                 *value = 0xff;
 133                 return;
 134         }
 135
 136         *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
 137 }
 138
 139 static void rt2400pci_rf_write(const struct rt2x00_dev *rt2x00dev,
 140         const u32 value)
 141 {
 142         u32 reg;
 143         unsigned int i;
 144
 145         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 146                 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
 147                 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
 148                         goto rf_write;
 149                 udelay(REGISTER_BUSY_DELAY);
 150         }
 151
 152         ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
 153         return;
 154
 155 rf_write:
 156         reg = 0;
 157         rt2x00_set_field32(&reg, RFCSR_VALUE, value);
 158         rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
 159         rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
 160         rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
 161
 162         rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
 163 }
 164
 165 static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 166 {
 167         struct rt2x00_dev *rt2x00dev = eeprom->data;
 168         u32 reg;
 169
 170         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
 171
 172         eeprom->reg_data_in = !!rt2x00_get_field32(reg,
 173                 CSR21_EEPROM_DATA_IN);
 174         eeprom->reg_data_out = !!rt2x00_get_field32(reg,
 175                 CSR21_EEPROM_DATA_OUT);
 176         eeprom->reg_data_clock = !!rt2x00_get_field32(reg,
 177                 CSR21_EEPROM_DATA_CLOCK);
 178         eeprom->reg_chip_select = !!rt2x00_get_field32(reg,
 179                 CSR21_EEPROM_CHIP_SELECT);
 180 }
 181
 182 static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 183 {
 184         struct rt2x00_dev *rt2x00dev = eeprom->data;
 185         u32 reg = 0;
 186
 187         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN,
 188                 !!eeprom->reg_data_in);
 189         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT,
 190                 !!eeprom->reg_data_out);
 191         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
 192                 !!eeprom->reg_data_clock);
 193         rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
 194                 !!eeprom->reg_chip_select);
 195
 196         rt2x00pci_register_write(rt2x00dev, CSR21, reg);
 197 }
 198
 199 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 200 #define CSR_OFFSET(__word)      ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
 201
 202 static void rt2400pci_read_csr(struct rt2x00_dev *rt2x00dev,
 203         const unsigned long word, void *data)
 204 {
 205         rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
 206 }
 207
 208 static void rt2400pci_write_csr(struct rt2x00_dev *rt2x00dev,
 209         const unsigned long word, void *data)
 210 {
 211         rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), *((u32*)data));
 212 }
 213
 214 static void rt2400pci_read_eeprom(struct rt2x00_dev *rt2x00dev,
 215         const unsigned long word, void *data)
 216 {
 217         rt2x00_eeprom_read(rt2x00dev, word, data);
 218 }
 219
 220 static void rt2400pci_write_eeprom(struct rt2x00_dev *rt2x00dev,
 221         const unsigned long word, void *data)
 222 {
 223         rt2x00_eeprom_write(rt2x00dev, word, *((u16*)data));
 224 }
 225
 226 static void rt2400pci_read_bbp(struct rt2x00_dev *rt2x00dev,
 227         const unsigned long word, void *data)
 228 {
 229         rt2400pci_bbp_read(rt2x00dev, word, data);
 230 }
 231
 232 static void rt2400pci_write_bbp(struct rt2x00_dev *rt2x00dev,
 233         const unsigned long word, void *data)
 234 {
 235         rt2400pci_bbp_write(rt2x00dev, word, *((u8*)data));
 236 }
 237
 238 static const struct rt2x00debug rt2400pci_rt2x00debug = {
 239         .owner          = THIS_MODULE,
 240         .reg_csr        = {
 241                 .read           = rt2400pci_read_csr,
 242                 .write          = rt2400pci_write_csr,
 243                 .word_size      = sizeof(u32),
 244                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 245         },
 246         .reg_eeprom     = {
 247                 .read           = rt2400pci_read_eeprom,
 248                 .write          = rt2400pci_write_eeprom,
 249                 .word_size      = sizeof(u16),
 250                 .word_count     = EEPROM_SIZE / sizeof(u16),
 251         },
 252         .reg_bbp        = {
 253                 .read           = rt2400pci_read_bbp,
 254                 .write          = rt2400pci_write_bbp,
 255                 .word_size      = sizeof(u8),
 256                 .word_count     = BBP_SIZE / sizeof(u8),
 257         },
 258 };
 259 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 260
 261 #ifdef CONFIG_RT2400PCI_RFKILL
 262 static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 263 {
 264         u32 reg;
 265
 266         rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
 267         return rt2x00_get_field32(reg, GPIOCSR_BIT0);
 268 }
 269 #endif /* CONFIG_RT2400PCI_RFKILL */
 270
 271 /*
 272  * Configuration handlers.
 273  */
 274 static void rt2400pci_config_bssid(struct rt2x00_dev *rt2x00dev, u8 *bssid)
 275 {
 276         u32 reg[2];
 277
 278         memset(&reg, 0, sizeof(reg));
 279         memcpy(&reg, bssid, ETH_ALEN);
 280
 281         /*
 282          * The BSSID is passed to us as an array of bytes,
 283          * that array is little endian, so no need for byte ordering.
 284          */
 285         rt2x00pci_register_multiwrite(rt2x00dev, CSR5, &reg, sizeof(reg));
 286 }
 287
 288 static void rt2400pci_config_promisc(struct rt2x00_dev *rt2x00dev,
 289         const int promisc)
 290 {
 291         u32 reg;
 292
 293         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
 294         rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME, !promisc);
 295         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
 296 }
 297
 298 static void rt2400pci_config_type(struct rt2x00_dev *rt2x00dev, int type)
 299 {
 300         u32 reg;
 301
 302         rt2x00pci_register_write(rt2x00dev, CSR14, 0);
 303
 304         /*
 305          * Apply hardware packet filter.
 306          */
 307         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
 308
 309         if (!is_monitor_present(&rt2x00dev->interface) &&
 310             (type == IEEE80211_IF_TYPE_IBSS || type == IEEE80211_IF_TYPE_STA))
 311                 rt2x00_set_field32(&reg, RXCSR0_DROP_TODS, 1);
 312         else
 313                 rt2x00_set_field32(&reg, RXCSR0_DROP_TODS, 0);
 314
 315         rt2x00_set_field32(&reg, RXCSR0_DROP_CRC, 1);
 316         if (is_monitor_present(&rt2x00dev->interface)) {
 317                 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL, 0);
 318                 rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL, 0);
 319                 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 0);
 320         } else {
 321                 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL, 1);
 322                 rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL, 1);
 323                 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
 324         }
 325
 326         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
 327
 328         /*
 329          * Enable beacon config
 330          */
 331         rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
 332         rt2x00_set_field32(&reg, BCNCSR1_PRELOAD,
 333                 PREAMBLE + get_duration(IEEE80211_HEADER, 2));
 334         rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
 335
 336         /*
 337          * Enable synchronisation.
 338          */
 339         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
 340         if (is_interface_present(&rt2x00dev->interface)) {
 341                 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
 342                 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
 343         }
 344
 345         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
 346         if (type == IEEE80211_IF_TYPE_IBSS || type == IEEE80211_IF_TYPE_AP)
 347                 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 2);
 348         else if (type == IEEE80211_IF_TYPE_STA)
 349                 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 1);
 350         else if (is_monitor_present(&rt2x00dev->interface) &&
 351                  !is_interface_present(&rt2x00dev->interface))
 352                 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
 353
 354         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
 355 }
 356
 357 static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
 358         const int value, const int channel, const int txpower)
 359 {
 360         u32 rf1 = rt2x00dev->rf1;
 361         u32 rf2 = value;
 362         u32 rf3 = rt2x00dev->rf3;
 363
 364         /*
 365          * Switch on tuning bits.
 366          */
 367         rt2x00_set_field32(&rf1, RF1_TUNER, 1);
 368         rt2x00_set_field32(&rf3, RF3_TUNER, 1);
 369
 370         rt2400pci_rf_write(rt2x00dev, rf1);
 371         rt2400pci_rf_write(rt2x00dev, rf2);
 372         rt2400pci_rf_write(rt2x00dev, rf3);
 373
 374         /*
 375          * RF2420 chipset don't need any additional actions.
 376          */
 377         if (rt2x00_rf(&rt2x00dev->chip, RF2420))
 378                 return;
 379
 380         /*
 381          * For the RT2421 chipsets we need to write an invalid
 382          * reference clock rate to activate auto_tune.
 383          * After that we set the value back to the correct channel.
 384          */
 385         rt2400pci_rf_write(rt2x00dev, rf1);
 386         rt2400pci_rf_write(rt2x00dev, 0x000c2a32);
 387         rt2400pci_rf_write(rt2x00dev, rf3);
 388
 389         msleep(1);
 390
 391         rt2400pci_rf_write(rt2x00dev, rf1);
 392         rt2400pci_rf_write(rt2x00dev, rf2);
 393         rt2400pci_rf_write(rt2x00dev, rf3);
 394
 395         msleep(1);
 396
 397         /*
 398          * Switch off tuning bits.
 399          */
 400         rt2x00_set_field32(&rf1, RF1_TUNER, 0);
 401         rt2x00_set_field32(&rf3, RF3_TUNER, 0);
 402
 403         rt2400pci_rf_write(rt2x00dev, rf1);
 404         rt2400pci_rf_write(rt2x00dev, rf3);
 405
 406         /*
 407          * Update rf fields
 408          */
 409         rt2x00dev->rf1 = rf1;
 410         rt2x00dev->rf2 = rf2;
 411         rt2x00dev->rf3 = rf3;
 412
 413         /*
 414          * Clear false CRC during channel switch.
 415          */
 416         rt2x00pci_register_read(rt2x00dev, CNT0, &rf1);
 417 }
 418
 419 static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
 420 {
 421         rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
 422 }
 423
 424 static void rt2400pci_config_antenna(struct rt2x00_dev *rt2x00dev,
 425         int antenna_tx, int antenna_rx)
 426 {
 427         u8 r1;
 428         u8 r4;
 429
 430         rt2400pci_bbp_read(rt2x00dev, 4, &r4);
 431         rt2400pci_bbp_read(rt2x00dev, 1, &r1);
 432
 433         /*
 434          * Configure the TX antenna.
 435          */
 436         if (antenna_tx == ANTENNA_DIVERSITY)
 437                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
 438         else if (antenna_tx == ANTENNA_A)
 439                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
 440         else if (antenna_tx == ANTENNA_B)
 441                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
 442
 443         /*
 444          * Configure the RX antenna.
 445          */
 446         if (antenna_rx == ANTENNA_DIVERSITY)
 447                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
 448         else if (antenna_rx == ANTENNA_A)
 449                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
 450         else if (antenna_rx == ANTENNA_B)
 451                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
 452
 453         rt2400pci_bbp_write(rt2x00dev, 4, r4);
 454         rt2400pci_bbp_write(rt2x00dev, 1, r1);
 455 }
 456
 457 static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
 458         struct ieee80211_tx_queue_params *params)
 459 {
 460         u32 reg;
 461
 462         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 463         rt2x00_set_field32(&reg, CSR11_CWMIN, params->cw_min);
 464         rt2x00_set_field32(&reg, CSR11_CWMAX, params->cw_max);
 465         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 466 }
 467
 468 static void rt2400pci_config_duration(struct rt2x00_dev *rt2x00dev,
 469         int short_slot_time, int beacon_int)
 470 {
 471         u32 reg;
 472
 473         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 474         rt2x00_set_field32(&reg, CSR11_SLOT_TIME,
 475                 short_slot_time ? SHORT_SLOT_TIME : SLOT_TIME);
 476         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 477
 478         rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
 479         rt2x00_set_field32(&reg, CSR18_SIFS, SIFS);
 480         rt2x00_set_field32(&reg, CSR18_PIFS,
 481                 short_slot_time ? SHORT_PIFS :  PIFS);
 482         rt2x00pci_register_write(rt2x00dev, CSR18, reg);
 483
 484         rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
 485         rt2x00_set_field32(&reg, CSR19_DIFS,
 486                 short_slot_time ? SHORT_DIFS : DIFS);
 487         rt2x00_set_field32(&reg, CSR19_EIFS, EIFS);
 488         rt2x00pci_register_write(rt2x00dev, CSR19, reg);
 489
 490         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
 491         rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
 492         rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
 493         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
 494
 495         rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
 496         rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL, beacon_int * 16);
 497         rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION, beacon_int * 16);
 498         rt2x00pci_register_write(rt2x00dev, CSR12, reg);
 499 }
 500
 501 static void rt2400pci_config_rate(struct rt2x00_dev *rt2x00dev, const int rate)
 502 {
 503         struct ieee80211_conf *conf = &rt2x00dev->hw->conf;
 504         u32 reg;
 505         u32 preamble;
 506         u16 value;
 507
 508         preamble = DEVICE_GET_RATE_FIELD(rate, PREAMBLE)
 509                 ? SHORT_PREAMBLE : PREAMBLE;
 510
 511         reg = DEVICE_GET_RATE_FIELD(rate, RATEMASK) & DEV_BASIC_RATE;
 512         rt2x00pci_register_write(rt2x00dev, ARCSR1, reg);
 513
 514         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
 515         value = ((conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME) ?
 516                  SHORT_DIFS :  DIFS) +
 517                 PLCP + preamble + get_duration(ACK_SIZE, 10);
 518         rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, value);
 519         value = SIFS + PLCP + preamble + get_duration(ACK_SIZE, 10);
 520         rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, value);
 521         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
 522
 523         preamble = DEVICE_GET_RATE_FIELD(rate, PREAMBLE) ? 0x08 : 0x00;
 524
 525         rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
 526         rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00 | preamble);
 527         rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
 528         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
 529         rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
 530
 531         rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
 532         rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble);
 533         rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
 534         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
 535         rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
 536
 537         rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
 538         rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble);
 539         rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
 540         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
 541         rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
 542
 543         rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
 544         rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble);
 545         rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
 546         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
 547         rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
 548 }
 549
 550 static void rt2400pci_config_phymode(struct rt2x00_dev *rt2x00dev,
 551         const int phymode)
 552 {
 553         struct ieee80211_hw_mode *mode;
 554         struct ieee80211_rate *rate;
 555
 556         rt2x00dev->curr_hwmode = HWMODE_B;
 557
 558         mode = &rt2x00dev->hwmodes[rt2x00dev->curr_hwmode];
 559         rate = &mode->rates[mode->num_rates - 1];
 560
 561         rt2400pci_config_rate(rt2x00dev, rate->val2);
 562 }
 563
 564 static void rt2400pci_config_mac_addr(struct rt2x00_dev *rt2x00dev, u8 *addr)
 565 {
 566         u32 reg[2];
 567
 568         memset(&reg, 0, sizeof(reg));
 569         memcpy(&reg, addr, ETH_ALEN);
 570
 571         /*
 572          * The MAC address is passed to us as an array of bytes,
 573          * that array is little endian, so no need for byte ordering.
 574          */
 575         rt2x00pci_register_multiwrite(rt2x00dev, CSR3, &reg, sizeof(reg));
 576 }
 577
 578 /*
 579  * LED functions.
 580  */
 581 static void rt2400pci_enable_led(struct rt2x00_dev *rt2x00dev)
 582 {
 583         u32 reg;
 584
 585         rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
 586
 587         rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, 70);
 588         rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, 30);
 589
 590         if (rt2x00dev->led_mode == LED_MODE_TXRX_ACTIVITY) {
 591                 rt2x00_set_field32(&reg, LEDCSR_LINK, 1);
 592                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 0);
 593         } else if (rt2x00dev->led_mode == LED_MODE_ASUS) {
 594                 rt2x00_set_field32(&reg, LEDCSR_LINK, 0);
 595                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 1);
 596         } else {
 597                 rt2x00_set_field32(&reg, LEDCSR_LINK, 1);
 598                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 1);
 599         }
 600
 601         rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
 602 }
 603
 604 static void rt2400pci_disable_led(struct rt2x00_dev *rt2x00dev)
 605 {
 606         u32 reg;
 607
 608         rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
 609         rt2x00_set_field32(&reg, LEDCSR_LINK, 0);
 610         rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 0);
 611         rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
 612 }
 613
 614 /*
 615  * Link tuning
 616  */
 617 static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev, int rssi)
 618 {
 619         u8 reg;
 620         char false_cca_delta;
 621
 622         /*
 623          * The link tuner should not run longer then 60 seconds,
 624          * and should run once every 2 seconds.
 625          */
 626         if (rt2x00dev->link.count > 60 || !(rt2x00dev->link.count % 1))
 627                 return;
 628
 629         /*
 630          * Read false CCA counter.
 631          */
 632         rt2400pci_bbp_read(rt2x00dev, 39, &reg);
 633
 634         /*
 635          * Determine difference with previous CCA counter.
 636          */
 637         false_cca_delta = reg - rt2x00dev->link.false_cca;
 638         rt2x00dev->link.false_cca = reg;
 639
 640         /*
 641          * Check if the difference is higher than the
 642          * threshold and if so, tune the link.
 643          */
 644         if (false_cca_delta >= 8) {
 645                 /*
 646                  * Read and update RX AGC VGC.
 647                  */
 648                 rt2400pci_bbp_read(rt2x00dev, 13, &reg);
 649                 reg += 2;
 650                 if (reg < 0x20)
 651                         rt2400pci_bbp_write(rt2x00dev, 13, reg);
 652         }
 653 }
 654
 655 /*
 656  * Initialization functions.
 657  */
 658 static void rt2400pci_init_rxring(struct rt2x00_dev *rt2x00dev)
 659 {
 660         struct data_desc *rxd;
 661         unsigned int i;
 662         u32 word;
 663
 664         memset(rt2x00dev->rx->data_addr, 0x00,
 665                 rt2x00_get_ring_size(rt2x00dev->rx));
 666
 667         for (i = 0; i < rt2x00dev->rx->stats.limit; i++) {
 668                 rxd = rt2x00dev->rx->entry[i].priv;
 669
 670                 rt2x00_desc_read(rxd, 2, &word);
 671                 rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH,
 672                         rt2x00dev->rx->data_size);
 673                 rt2x00_desc_write(rxd, 2, word);
 674
 675                 rt2x00_desc_read(rxd, 1, &word);
 676                 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS,
 677                         rt2x00dev->rx->entry[i].data_dma);
 678                 rt2x00_desc_write(rxd, 1, word);
 679
 680                 rt2x00_desc_read(rxd, 0, &word);
 681                 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
 682                 rt2x00_desc_write(rxd, 0, word);
 683         }
 684
 685         rt2x00_ring_index_clear(rt2x00dev->rx);
 686 }
 687
 688 static void rt2400pci_init_txring(struct rt2x00_dev *rt2x00dev,
 689         const int queue)
 690 {
 691         struct data_ring *ring = rt2x00_get_ring(rt2x00dev, queue);
 692         struct data_desc *txd;
 693         unsigned int i;
 694         u32 word;
 695
 696         memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
 697
 698         for (i = 0; i < ring->stats.limit; i++) {
 699                 txd = ring->entry[i].priv;
 700
 701                 rt2x00_desc_read(txd, 1, &word);
 702                 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS,
 703                         ring->entry[i].data_dma);
 704                 rt2x00_desc_write(txd, 1, word);
 705
 706                 rt2x00_desc_read(txd, 2, &word);
 707                 rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH,
 708                         ring->data_size);
 709                 rt2x00_desc_write(txd, 2, word);
 710
 711                 rt2x00_desc_read(txd, 0, &word);
 712                 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
 713                 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
 714                 rt2x00_desc_write(txd, 0, word);
 715         }
 716
 717         rt2x00_ring_index_clear(ring);
 718 }
 719
 720 static int rt2400pci_init_rings(struct rt2x00_dev *rt2x00dev)
 721 {
 722         u32 reg;
 723
 724         /*
 725          * Initialize rings.
 726          */
 727         rt2400pci_init_rxring(rt2x00dev);
 728         rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
 729         rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
 730         rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON);
 731         rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
 732
 733         /*
 734          * Initialize registers.
 735          */
 736         rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
 737         rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE,
 738                 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].desc_size);
 739         rt2x00_set_field32(&reg, TXCSR2_NUM_TXD,
 740                 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].stats.limit);
 741         rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM,
 742                 rt2x00dev->bcn[1].stats.limit);
 743         rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO,
 744                 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].stats.limit);
 745         rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
 746
 747         rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
 748         rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
 749                 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].data_dma);
 750         rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
 751
 752         rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
 753         rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
 754                 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].data_dma);
 755         rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
 756
 757         rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
 758         rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
 759                 rt2x00dev->bcn[1].data_dma);
 760         rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
 761
 762         rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
 763         rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
 764                 rt2x00dev->bcn[0].data_dma);
 765         rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
 766
 767         rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
 768         rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE,
 769                 rt2x00dev->rx->desc_size);
 770         rt2x00_set_field32(&reg, RXCSR1_NUM_RXD,
 771                 rt2x00dev->rx->stats.limit);
 772         rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
 773
 774         rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
 775         rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
 776                 rt2x00dev->rx->data_dma);
 777         rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
 778
 779         return 0;
 780 }
 781
 782 static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
 783 {
 784         u32 reg;
 785
 786         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
 787                 return -EBUSY;
 788
 789         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
 790
 791         rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
 792         rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
 793         rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00020002);
 794         rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
 795
 796         rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
 797         rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
 798         rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
 799         rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
 800         rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
 801
 802         rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
 803         rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
 804                 (rt2x00dev->rx->data_size / 128));
 805         rt2x00pci_register_write(rt2x00dev, CSR9, reg);
 806
 807         rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
 808
 809         rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
 810         rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
 811
 812         rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
 813         rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
 814         rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
 815
 816         rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
 817         /*
 818          * Tx power.
 819          */
 820         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3);
 821         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
 822         /*
 823          * Signal.
 824          */
 825         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32);
 826         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
 827         /*
 828          * Rssi.
 829          */
 830         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36);
 831         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
 832         rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
 833
 834         rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
 835         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
 836         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
 837         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
 838         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
 839         rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
 840
 841         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
 842         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
 843         rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
 844         rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
 845         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
 846
 847         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
 848         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
 849         rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
 850         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
 851
 852         /*
 853          * We must clear the FCS and FIFO error count.
 854          * These registers are cleared on read,
 855          * so we may pass a useless variable to store the value.
 856          */
 857         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 858         rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
 859
 860         return 0;
 861 }
 862
 863 static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
 864 {
 865         unsigned int i;
 866         u16 eeprom;
 867         u8 reg_id;
 868         u8 value;
 869
 870         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 871                 rt2400pci_bbp_read(rt2x00dev, 0, &value);
 872                 if ((value != 0xff) && (value != 0x00))
 873                         goto continue_csr_init;
 874                 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
 875                 udelay(REGISTER_BUSY_DELAY);
 876         }
 877
 878         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
 879         return -EACCES;
 880
 881 continue_csr_init:
 882         rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
 883         rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
 884         rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
 885         rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
 886         rt2400pci_bbp_write(rt2x00dev, 13, 0x08);
 887         rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
 888         rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
 889         rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
 890         rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
 891         rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
 892         rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
 893         rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
 894         rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
 895         rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
 896         rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
 897
 898         DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
 899         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
 900                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
 901
 902                 if (eeprom != 0xffff && eeprom != 0x0000) {
 903                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
 904                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
 905                         DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
 906                                 reg_id, value);
 907                         rt2400pci_bbp_write(rt2x00dev, reg_id, value);
 908                 }
 909         }
 910         DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
 911
 912         return 0;
 913 }
 914
 915 /*
 916  * Device state switch handlers.
 917  */
 918 static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
 919         enum dev_state state)
 920 {
 921         u32 reg;
 922
 923         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
 924         rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
 925                 state == STATE_RADIO_RX_OFF);
 926         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
 927 }
 928
 929 static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
 930 {
 931         u32 reg;
 932
 933         /*
 934          * Initialize all registers.
 935          */
 936         if (rt2400pci_init_rings(rt2x00dev) ||
 937             rt2400pci_init_registers(rt2x00dev) ||
 938             rt2400pci_init_bbp(rt2x00dev)) {
 939                 ERROR(rt2x00dev, "Register initialization failed.\n");
 940                 return -EIO;
 941         }
 942
 943         /*
 944          * Clear interrupts.
 945          */
 946         rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
 947         rt2x00pci_register_write(rt2x00dev, CSR7, reg);
 948
 949         /*
 950          * Enable interrupts.
 951          */
 952         rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
 953         rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, 0);
 954         rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, 0);
 955         rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, 0);
 956         rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, 0);
 957         rt2x00_set_field32(&reg, CSR8_RXDONE, 0);
 958         rt2x00pci_register_write(rt2x00dev, CSR8, reg);
 959
 960         /*
 961          * Enable LED
 962          */
 963         rt2400pci_enable_led(rt2x00dev);
 964
 965         return 0;
 966 }
 967
 968 static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
 969 {
 970         u32 reg;
 971
 972         /*
 973          * Disable LED
 974          */
 975         rt2400pci_disable_led(rt2x00dev);
 976
 977         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
 978
 979         /*
 980          * Disable synchronisation.
 981          */
 982         rt2x00pci_register_write(rt2x00dev, CSR14, 0);
 983
 984         /*
 985          * Cancel RX and TX.
 986          */
 987         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
 988         rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
 989         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
 990
 991         /*
 992          * Disable interrupts.
 993          */
 994         rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
 995         rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, 1);
 996         rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, 1);
 997         rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, 1);
 998         rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, 1);
 999         rt2x00_set_field32(&reg, CSR8_RXDONE, 1);
1000         rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1001 }
1002
1003 static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
1004         enum dev_state state)
1005 {
1006         u32 reg;
1007         unsigned int i;
1008         char put_to_sleep;
1009         char bbp_state;
1010         char rf_state;
1011
1012         put_to_sleep = (state != STATE_AWAKE);
1013
1014         rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1015         rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1016         rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1017         rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1018         rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1019         rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1020
1021         /*
1022          * Device is not guaranteed to be in the requested state yet.
1023          * We must wait until the register indicates that the
1024          * device has entered the correct state.
1025          */
1026         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1027                 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1028                 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
1029                 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
1030                 if (bbp_state == state && rf_state == state)
1031                         return 0;
1032                 msleep(10);
1033         }
1034
1035         NOTICE(rt2x00dev, "Device failed to enter state %d, "
1036                 "current device state: bbp %d and rf %d.\n",
1037                 state, bbp_state, rf_state);
1038
1039         return -EBUSY;
1040 }
1041
1042 static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1043         enum dev_state state)
1044 {
1045         int retval = 0;
1046
1047         switch (state) {
1048                 case STATE_RADIO_ON:
1049                         retval = rt2400pci_enable_radio(rt2x00dev);
1050                 break;
1051                 case STATE_RADIO_OFF:
1052                         rt2400pci_disable_radio(rt2x00dev);
1053                 break;
1054                 case STATE_RADIO_RX_ON:
1055                 case STATE_RADIO_RX_OFF:
1056                         rt2400pci_toggle_rx(rt2x00dev, state);
1057                 break;
1058                 case STATE_DEEP_SLEEP:
1059                 case STATE_SLEEP:
1060                 case STATE_STANDBY:
1061                 case STATE_AWAKE:
1062                         retval = rt2400pci_set_state(rt2x00dev, state);
1063                 break;
1064                 default:
1065                         retval = -ENOTSUPP;
1066                 break;
1067         }
1068
1069         return retval;
1070 }
1071
1072 /*
1073  * TX descriptor initialization
1074  */
1075 static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1076         struct data_entry *entry, struct data_desc *txd,
1077         struct data_entry_desc *desc, struct ieee80211_hdr *ieee80211hdr,
1078         unsigned int length, struct ieee80211_tx_control *control)
1079 {
1080         u32 word;
1081         u32 signal = 0;
1082         u32 service = 0;
1083         u32 length_high = 0;
1084         u32 length_low = 0;
1085
1086         /*
1087          * The PLCP values should be treated as if they
1088          * were BBP values.
1089          */
1090         rt2x00_set_field32(&signal, BBPCSR_VALUE, desc->signal);
1091         rt2x00_set_field32(&signal, BBPCSR_REGNUM, 5);
1092         rt2x00_set_field32(&signal, BBPCSR_BUSY, 1);
1093
1094         rt2x00_set_field32(&service, BBPCSR_VALUE, desc->service);
1095         rt2x00_set_field32(&service, BBPCSR_REGNUM, 6);
1096         rt2x00_set_field32(&service, BBPCSR_BUSY, 1);
1097
1098         rt2x00_set_field32(&length_high, BBPCSR_VALUE, desc->length_high);
1099         rt2x00_set_field32(&length_high, BBPCSR_REGNUM, 7);
1100         rt2x00_set_field32(&length_high, BBPCSR_BUSY, 1);
1101
1102         rt2x00_set_field32(&length_low, BBPCSR_VALUE, desc->length_low);
1103         rt2x00_set_field32(&length_low, BBPCSR_REGNUM, 8);
1104         rt2x00_set_field32(&length_low, BBPCSR_BUSY, 1);
1105
1106         /*
1107          * Start writing the descriptor words.
1108          */
1109         rt2x00_desc_read(txd, 2, &word);
1110         rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, length);
1111         rt2x00_desc_write(txd, 2, word);
1112
1113         rt2x00_desc_read(txd, 3, &word);
1114         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, signal);
1115         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, service);
1116         rt2x00_desc_write(txd, 3, word);
1117
1118         rt2x00_desc_read(txd, 4, &word);
1119         rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, length_low);
1120         rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, length_high);
1121         rt2x00_desc_write(txd, 4, word);
1122
1123         rt2x00_desc_read(txd, 0, &word);
1124         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1125         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1126         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1127                 test_bit(ENTRY_TXD_MORE_FRAG, &entry->flags));
1128         rt2x00_set_field32(&word, TXD_W0_ACK,
1129                 test_bit(ENTRY_TXD_REQ_ACK, &entry->flags));
1130         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1131                 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &entry->flags));
1132         rt2x00_set_field32(&word, TXD_W0_RTS,
1133                 test_bit(ENTRY_TXD_RTS_FRAME, &entry->flags));
1134         rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs);
1135         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, 0);
1136         rt2x00_desc_write(txd, 0, word);
1137 }
1138
1139 /*
1140  * TX data initialization
1141  */
1142 static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev, int queue)
1143 {
1144         u32 reg;
1145
1146         if (queue == IEEE80211_TX_QUEUE_BEACON) {
1147                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1148                 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1149                         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1150                         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1151                 }
1152                 return;
1153         }
1154
1155         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1156         if (queue == IEEE80211_TX_QUEUE_DATA0)
1157                 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, 1);
1158         else if (queue == IEEE80211_TX_QUEUE_DATA1)
1159                 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, 1);
1160         else if (queue == IEEE80211_TX_QUEUE_AFTER_BEACON)
1161                 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, 1);
1162         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1163 }
1164
1165 /*
1166  * Interrupt functions.
1167  */
1168 static void rt2400pci_rxdone(struct rt2x00_dev *rt2x00dev)
1169 {
1170         struct data_ring *ring = rt2x00dev->rx;
1171         struct data_entry *entry;
1172         struct data_desc *rxd;
1173         u32 word0;
1174         u32 word2;
1175         int signal;
1176         int rssi;
1177         u16 size;
1178
1179         while (1) {
1180                 entry = rt2x00_get_data_entry(ring);
1181                 rxd = entry->priv;
1182                 rt2x00_desc_read(rxd, 0, &word0);
1183                 rt2x00_desc_read(rxd, 2, &word2);
1184
1185                 if (rt2x00_get_field32(word0, RXD_W0_OWNER_NIC))
1186                         break;
1187
1188                 /*
1189                  * TODO: Don't we need to keep statistics
1190                  * updated about events like CRC and physical errors?
1191                  */
1192                 if (rt2x00_get_field32(word0, RXD_W0_CRC) ||
1193                     rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1194                         goto skip_entry;
1195
1196                 /*
1197                  * Obtain the status about this packet.
1198                  */
1199                 size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1200                 signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1201                 rssi = rt2x00_get_field32(word2, RXD_W2_RSSI);
1202
1203                 /*
1204                  * Send the packet to upper layer.
1205                  */
1206                 rt2x00lib_rxdone(entry, entry->data_addr, size,
1207                         signal, rssi, 0);
1208
1209 skip_entry:
1210                 if (test_bit(DEVICE_ENABLED_RADIO, &ring->rt2x00dev->flags)) {
1211                         rt2x00_set_field32(&word0, RXD_W0_OWNER_NIC, 1);
1212                         rt2x00_desc_write(rxd, 0, word0);
1213                 }
1214
1215                 rt2x00_ring_index_inc(ring);
1216         }
1217 }
1218
1219 static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev, const int queue)
1220 {
1221         struct data_ring *ring = rt2x00_get_ring(rt2x00dev, queue);
1222         struct data_entry *entry;
1223         struct data_desc *txd;
1224         u32 word;
1225         int tx_status;
1226         int retry;
1227
1228         while (!rt2x00_ring_empty(ring)) {
1229                 entry = rt2x00_get_data_entry_done(ring);
1230                 txd = entry->priv;
1231                 rt2x00_desc_read(txd, 0, &word);
1232
1233                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1234                     !rt2x00_get_field32(word, TXD_W0_VALID))
1235                         break;
1236
1237                 /*
1238                  * Obtain the status about this packet.
1239                  */
1240                 tx_status = rt2x00_get_field32(word, TXD_W0_RESULT);
1241                 retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1242
1243                 rt2x00lib_txdone(entry, tx_status, retry);
1244
1245                 /*
1246                  * Make this entry available for reuse.
1247                  */
1248                 entry->flags = 0;
1249                 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1250                 rt2x00_desc_write(txd, 0, word);
1251                 rt2x00_ring_index_done_inc(ring);
1252         }
1253
1254         /*
1255          * If the data ring was full before the txdone handler
1256          * we must make sure the packet queue in the mac80211 stack
1257          * is reenabled when the txdone handler has finished.
1258          */
1259         entry = ring->entry;
1260         if (!rt2x00_ring_full(ring))
1261                 ieee80211_wake_queue(rt2x00dev->hw,
1262                         entry->tx_status.control.queue);
1263 }
1264
1265 static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1266 {
1267         struct rt2x00_dev *rt2x00dev = dev_instance;
1268         u32 reg;
1269
1270         /*
1271          * Get the interrupt sources & saved to local variable.
1272          * Write register value back to clear pending interrupts.
1273          */
1274         rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1275         rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1276
1277         if (!reg)
1278                 return IRQ_NONE;
1279
1280         if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1281                 return IRQ_HANDLED;
1282
1283         /*
1284          * Handle interrupts, walk through all bits
1285          * and run the tasks, the bits are checked in order of
1286          * priority.
1287          */
1288
1289         /*
1290          * 1 - Beacon timer expired interrupt.
1291          */
1292         if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1293                 rt2x00pci_beacondone(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
1294
1295         /*
1296          * 2 - Rx ring done interrupt.
1297          */
1298         if (rt2x00_get_field32(reg, CSR7_RXDONE))
1299                 rt2400pci_rxdone(rt2x00dev);
1300
1301         /*
1302          * 3 - Atim ring transmit done interrupt.
1303          */
1304         if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1305                 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON);
1306
1307         /*
1308          * 4 - Priority ring transmit done interrupt.
1309          */
1310         if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1311                 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
1312
1313         /*
1314          * 5 - Tx ring transmit done interrupt.
1315          */
1316         if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1317                 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
1318
1319         return IRQ_HANDLED;
1320 }
1321
1322 /*
1323  * Device initialization functions.
1324  */
1325 static int rt2400pci_alloc_eeprom(struct rt2x00_dev *rt2x00dev)
1326 {
1327         struct eeprom_93cx6 eeprom;
1328         u32 reg;
1329         u16 word;
1330
1331         /*
1332          * Allocate the eeprom memory, check the eeprom width
1333          * and copy the entire eeprom into this allocated memory.
1334          */
1335         rt2x00dev->eeprom = kzalloc(EEPROM_SIZE, GFP_KERNEL);
1336         if (!rt2x00dev->eeprom)
1337                 return -ENOMEM;
1338
1339         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1340
1341         eeprom.data = rt2x00dev;
1342         eeprom.register_read = rt2400pci_eepromregister_read;
1343         eeprom.register_write = rt2400pci_eepromregister_write;
1344         eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1345                 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1346         eeprom.reg_data_in = 0;
1347         eeprom.reg_data_out = 0;
1348         eeprom.reg_data_clock = 0;
1349         eeprom.reg_chip_select = 0;
1350
1351         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1352                 EEPROM_SIZE / sizeof(u16));
1353
1354         /*
1355          * Start validation of the data that has been read.
1356          */
1357         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1358         if (word == 0xffff) {
1359                 ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
1360                 return -EINVAL;
1361         }
1362
1363         return 0;
1364 }
1365
1366 static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1367 {
1368         u32 reg;
1369         u16 value;
1370         u16 eeprom;
1371
1372         /*
1373          * Read EEPROM word for configuration.
1374          */
1375         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1376
1377         /*
1378          * Identify RF chipset.
1379          */
1380         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1381         rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1382         rt2x00_set_chip(rt2x00dev, RT2460, value, reg);
1383
1384         if (!rt2x00_rf(&rt2x00dev->chip, RF2420) &&
1385             !rt2x00_rf(&rt2x00dev->chip, RF2421)) {
1386                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1387                 return -ENODEV;
1388         }
1389
1390         /*
1391          * Identify default antenna configuration.
1392          */
1393         rt2x00dev->hw->conf.antenna_sel_tx = rt2x00_get_field16(eeprom,
1394                 EEPROM_ANTENNA_TX_DEFAULT);
1395         rt2x00dev->hw->conf.antenna_sel_rx = rt2x00_get_field16(eeprom,
1396                 EEPROM_ANTENNA_RX_DEFAULT);
1397
1398         /*
1399          * Store led mode, for correct led behaviour.
1400          */
1401         rt2x00dev->led_mode = rt2x00_get_field16(eeprom,
1402                 EEPROM_ANTENNA_LED_MODE);
1403
1404         /*
1405          * Detect if this device has an hardware controlled radio.
1406          */
1407         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1408                 __set_bit(DEVICE_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1409
1410         /*
1411          * Check if the BBP tuning should be enabled.
1412          */
1413         if (!rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1414                 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1415
1416         return 0;
1417 }
1418
1419 /*
1420  * RF value list for RF2420 & RF2421
1421  * Supports: 2.4 GHz
1422  */
1423 static const u32 rf_vals_bg[] = {
1424         0x000c1fda, 0x000c1fee, 0x000c2002, 0x000c2016, 0x000c202a,
1425         0x000c203e, 0x000c2052, 0x000c2066, 0x000c207a, 0x000c208e,
1426         0x000c20a2, 0x000c20b6, 0x000c20ca, 0x000c20fa
1427 };
1428
1429 static void rt2400pci_init_hw_mode(struct rt2x00_dev *rt2x00dev)
1430 {
1431         struct hw_mode_spec *spec = &rt2x00dev->spec;
1432         u8 *txpower;
1433         unsigned int i;
1434
1435         /*
1436          * Initialize all hw fields.
1437          */
1438         rt2x00dev->hw->flags = IEEE80211_HW_HOST_GEN_BEACON |
1439                 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1440                 IEEE80211_HW_WEP_INCLUDE_IV |
1441                 IEEE80211_HW_DATA_NULLFUNC_ACK |
1442                 IEEE80211_HW_NO_TKIP_WMM_HWACCEL |
1443                 IEEE80211_HW_MONITOR_DURING_OPER;
1444         rt2x00dev->hw->extra_tx_headroom = 0;
1445         rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1446         rt2x00dev->hw->max_noise = MAX_RX_NOISE;
1447         rt2x00dev->hw->queues = 2;
1448
1449         /*
1450          * This device supports ATIM
1451          */
1452         __set_bit(DEVICE_SUPPORT_ATIM, &rt2x00dev->flags);
1453
1454         /*
1455          * Set device specific, but channel independent RF values.
1456          */
1457         rt2x00dev->rf1 = 0x00022058;
1458         if (rt2x00_rf(&rt2x00dev->chip, RF2420))
1459                 rt2x00dev->rf3 = 0x00000111;
1460         else
1461                 rt2x00dev->rf3 = 0x00000101;
1462
1463         /*
1464          * Convert tx_power array in eeprom.
1465          */
1466         txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1467         for (i = 0; i < 14; i++)
1468                 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1469
1470         /*
1471          * Initialize hw_mode information.
1472          */
1473         spec->mac_addr = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1474         spec->num_modes = 1;
1475         spec->num_rates = 4;
1476         spec->num_channels = 14;
1477         spec->tx_power_a = NULL;
1478         spec->tx_power_bg = txpower;
1479         spec->tx_power_default = DEFAULT_TXPOWER;
1480         spec->chan_val_a = NULL;
1481         spec->chan_val_bg = rf_vals_bg;
1482 }
1483
1484 static int rt2400pci_init_hw(struct rt2x00_dev *rt2x00dev)
1485 {
1486         int retval;
1487
1488         /*
1489          * Allocate eeprom data.
1490          */
1491         retval = rt2400pci_alloc_eeprom(rt2x00dev);
1492         if (retval)
1493                 return retval;
1494
1495         retval = rt2400pci_init_eeprom(rt2x00dev);
1496         if (retval)
1497                 return retval;
1498
1499         /*
1500          * Initialize hw specifications.
1501          */
1502         rt2400pci_init_hw_mode(rt2x00dev);
1503
1504         return 0;
1505 }
1506
1507 /*
1508  * IEEE80211 stack callback functions.
1509  */
1510 static int rt2400pci_get_stats(struct ieee80211_hw *hw,
1511         struct ieee80211_low_level_stats *stats)
1512 {
1513         struct rt2x00_dev *rt2x00dev = hw->priv;
1514         u32 reg;
1515
1516         /*
1517          * Update FCS error count from register.
1518          * The dot11ACKFailureCount, dot11RTSFailureCount and
1519          * dot11RTSSuccessCount are updated in interrupt time.
1520          */
1521         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
1522         rt2x00dev->low_level_stats.dot11FCSErrorCount +=
1523                 rt2x00_get_field32(reg, CNT0_FCS_ERROR);
1524
1525         memcpy(stats, &rt2x00dev->low_level_stats, sizeof(*stats));
1526
1527         return 0;
1528 }
1529
1530 static int rt2400pci_set_retry_limit(struct ieee80211_hw *hw,
1531         u32 short_retry, u32 long_retry)
1532 {
1533         struct rt2x00_dev *rt2x00dev = hw->priv;
1534         u32 reg;
1535
1536         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
1537         rt2x00_set_field32(&reg, CSR11_LONG_RETRY, long_retry);
1538         rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, short_retry);
1539         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
1540
1541         return 0;
1542 }
1543
1544 static int rt2400pci_conf_tx(struct ieee80211_hw *hw,
1545         int queue, const struct ieee80211_tx_queue_params *params)
1546 {
1547         struct rt2x00_dev *rt2x00dev = hw->priv;
1548
1549         /*
1550          * We don't support variating cw_min and cw_max variables
1551          * per queue. So by default we only configure the TX queue,
1552          * and ignore all other configurations.
1553          */
1554         if (queue != IEEE80211_TX_QUEUE_DATA0)
1555                 return -EINVAL;
1556
1557         if (rt2x00lib_conf_tx(hw, queue, params))
1558                 return -EINVAL;
1559
1560         /*
1561          * Write configuration to register.
1562          */
1563         rt2400pci_config_cw(rt2x00dev, &rt2x00dev->tx->tx_params);
1564
1565         return 0;
1566 }
1567
1568 static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw)
1569 {
1570         struct rt2x00_dev *rt2x00dev = hw->priv;
1571         u64 tsf;
1572         u32 reg;
1573
1574         rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1575         tsf = (u64)rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1576         rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1577         tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1578
1579         return tsf;
1580 }
1581
1582 static void rt2400pci_reset_tsf(struct ieee80211_hw *hw)
1583 {
1584         struct rt2x00_dev *rt2x00dev = hw->priv;
1585
1586         rt2x00pci_register_write(rt2x00dev, CSR16, 0);
1587         rt2x00pci_register_write(rt2x00dev, CSR17, 0);
1588 }
1589
1590 static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1591 {
1592         struct rt2x00_dev *rt2x00dev = hw->priv;
1593         u32 reg;
1594
1595         rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1596         return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1597 }
1598
1599 static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1600         .tx                     = rt2x00lib_tx,
1601         .reset                  = rt2x00lib_reset,
1602         .open                   = rt2x00lib_open,
1603         .stop                   = rt2x00lib_stop,
1604         .add_interface          = rt2x00lib_add_interface,
1605         .remove_interface       = rt2x00lib_remove_interface,
1606         .config                 = rt2x00lib_config,
1607         .config_interface       = rt2x00lib_config_interface,
1608         .set_multicast_list     = rt2x00lib_set_multicast_list,
1609         .get_stats              = rt2400pci_get_stats,
1610         .set_retry_limit        = rt2400pci_set_retry_limit,
1611         .conf_tx                = rt2400pci_conf_tx,
1612         .get_tx_stats           = rt2x00lib_get_tx_stats,
1613         .get_tsf                = rt2400pci_get_tsf,
1614         .reset_tsf              = rt2400pci_reset_tsf,
1615         .beacon_update          = rt2x00pci_beacon_update,
1616         .tx_last_beacon         = rt2400pci_tx_last_beacon,
1617 };
1618
1619 static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1620         .irq_handler            = rt2400pci_interrupt,
1621         .init_hw                = rt2400pci_init_hw,
1622         .initialize             = rt2x00pci_initialize,
1623         .uninitialize           = rt2x00pci_uninitialize,
1624         .set_device_state       = rt2400pci_set_device_state,
1625 #ifdef CONFIG_RT2400PCI_RFKILL
1626         .rfkill_poll            = rt2400pci_rfkill_poll,
1627 #endif /* CONFIG_RT2400PCI_RFKILL */
1628         .link_tuner             = rt2400pci_link_tuner,
1629         .write_tx_desc          = rt2400pci_write_tx_desc,
1630         .write_tx_data          = rt2x00pci_write_tx_data,
1631         .kick_tx_queue          = rt2400pci_kick_tx_queue,
1632         .config_type            = rt2400pci_config_type,
1633         .config_phymode         = rt2400pci_config_phymode,
1634         .config_channel         = rt2400pci_config_channel,
1635         .config_mac_addr        = rt2400pci_config_mac_addr,
1636         .config_bssid           = rt2400pci_config_bssid,
1637         .config_promisc         = rt2400pci_config_promisc,
1638         .config_txpower         = rt2400pci_config_txpower,
1639         .config_antenna         = rt2400pci_config_antenna,
1640         .config_duration        = rt2400pci_config_duration,
1641 };
1642
1643 static const struct rt2x00_ops rt2400pci_ops = {
1644         .name   = DRV_NAME,
1645         .rxd_size = RXD_DESC_SIZE,
1646         .txd_size = TXD_DESC_SIZE,
1647         .lib    = &rt2400pci_rt2x00_ops,
1648         .hw     = &rt2400pci_mac80211_ops,
1649 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1650         .debugfs = &rt2400pci_rt2x00debug,
1651 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1652 };
1653
1654 /*
1655  * RT2400pci module information.
1656  */
1657 static struct pci_device_id rt2400pci_device_table[] = {
1658         { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops) },
1659         { 0, }
1660 };
1661
1662 MODULE_AUTHOR(DRV_PROJECT);
1663 MODULE_VERSION(DRV_VERSION);
1664 MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1665 MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1666 MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1667 MODULE_LICENSE("GPL");
1668
1669 static struct pci_driver rt2400pci_driver = {
1670         .name           = DRV_NAME,
1671         .id_table       = rt2400pci_device_table,
1672         .probe          = rt2x00pci_probe,
1673         .remove         = __devexit_p(rt2x00pci_remove),
1674 #ifdef CONFIG_PM
1675         .suspend        = rt2x00pci_suspend,
1676         .resume         = rt2x00pci_resume,
1677 #endif /* CONFIG_PM */
1678 };
1679
1680 static int __init rt2400pci_init(void)
1681 {
1682         printk(KERN_INFO "Loading module: %s - %s by %s.\n",
1683                 DRV_NAME, DRV_VERSION, DRV_PROJECT);
1684         return pci_register_driver(&rt2400pci_driver);
1685 }
1686
1687 static void __exit rt2400pci_exit(void)
1688 {
1689         printk(KERN_INFO "Unloading module: %s.\n", DRV_NAME);
1690         pci_unregister_driver(&rt2400pci_driver);
1691 }
1692
1693 module_init(rt2400pci_init);
1694 module_exit(rt2400pci_exit);