package/platform/lantiq/ltq-atm/src/ltq_atm.c

   1 /******************************************************************************
   2 **
   3 ** FILE NAME    : ifxmips_atm_core.c
   4 ** PROJECT      : UEIP
   5 ** MODULES      : ATM
   6 **
   7 ** DATE         : 7 Jul 2009
   8 ** AUTHOR       : Xu Liang
   9 ** DESCRIPTION  : ATM driver common source file (core functions)
  10 ** COPYRIGHT    :       Copyright (c) 2006
  11 **                      Infineon Technologies AG
  12 **                      Am Campeon 1-12, 85579 Neubiberg, Germany
  13 **
  14 **    This program is free software; you can redistribute it and/or modify
  15 **    it under the terms of the GNU General Public License as published by
  16 **    the Free Software Foundation; either version 2 of the License, or
  17 **    (at your option) any later version.
  18 **
  19 ** HISTORY
  20 ** $Date        $Author         $Comment
  21 ** 07 JUL 2009  Xu Liang        Init Version
  22 *******************************************************************************/
  23
  24 #define IFX_ATM_VER_MAJOR               1
  25 #define IFX_ATM_VER_MID                 0
  26 #define IFX_ATM_VER_MINOR               26
  27
  28 #include <linux/kernel.h>
  29 #include <linux/module.h>
  30 #include <linux/version.h>
  31 #include <linux/types.h>
  32 #include <linux/errno.h>
  33 #include <linux/proc_fs.h>
  34 #include <linux/init.h>
  35 #include <linux/ioctl.h>
  36 #include <linux/atmdev.h>
  37 #include <linux/platform_device.h>
  38 #include <linux/of_device.h>
  39 #include <linux/atm.h>
  40 #include <linux/clk.h>
  41 #include <linux/interrupt.h>
  42 #ifdef CONFIG_XFRM
  43   #include <net/xfrm.h>
  44 #endif
  45
  46 #include <lantiq_soc.h>
  47
  48 #include "ifxmips_atm_core.h"
  49
  50 #define MODULE_PARM_ARRAY(a, b)   module_param_array(a, int, NULL, 0)
  51 #define MODULE_PARM(a, b)         module_param(a, int, 0)
  52
  53 /*!
  54   \brief QSB cell delay variation due to concurrency
  55  */
  56 static int qsb_tau   = 1;                       /*  QSB cell delay variation due to concurrency     */
  57 /*!
  58   \brief QSB scheduler burst length
  59  */
  60 static int qsb_srvm  = 0x0F;                    /*  QSB scheduler burst length                      */
  61 /*!
  62   \brief QSB time step, all legal values are 1, 2, 4
  63  */
  64 static int qsb_tstep = 4 ;                      /*  QSB time step, all legal values are 1, 2, 4     */
  65
  66 /*!
  67   \brief Write descriptor delay
  68  */
  69 static int write_descriptor_delay  = 0x20;      /*  Write descriptor delay                          */
  70
  71 /*!
  72   \brief AAL5 padding byte ('~')
  73  */
  74 static int aal5_fill_pattern       = 0x007E;    /*  AAL5 padding byte ('~')                         */
  75 /*!
  76   \brief Max frame size for RX
  77  */
  78 static int aal5r_max_packet_size   = 0x0700;    /*  Max frame size for RX                           */
  79 /*!
  80   \brief Min frame size for RX
  81  */
  82 static int aal5r_min_packet_size   = 0x0000;    /*  Min frame size for RX                           */
  83 /*!
  84   \brief Max frame size for TX
  85  */
  86 static int aal5s_max_packet_size   = 0x0700;    /*  Max frame size for TX                           */
  87 /*!
  88   \brief Min frame size for TX
  89  */
  90 static int aal5s_min_packet_size   = 0x0000;    /*  Min frame size for TX                           */
  91 /*!
  92   \brief Drop error packet in RX path
  93  */
  94 static int aal5r_drop_error_packet = 1;         /*  Drop error packet in RX path                    */
  95
  96 /*!
  97   \brief Number of descriptors per DMA RX channel
  98  */
  99 static int dma_rx_descriptor_length = 128;      /*  Number of descriptors per DMA RX channel        */
 100 /*!
 101   \brief Number of descriptors per DMA TX channel
 102  */
 103 static int dma_tx_descriptor_length = 64;       /*  Number of descriptors per DMA TX channel        */
 104 /*!
 105   \brief PPE core clock cycles between descriptor write and effectiveness in external RAM
 106  */
 107 static int dma_rx_clp1_descriptor_threshold = 38;
 108 /*@}*/
 109
 110 MODULE_PARM(qsb_tau, "i");
 111 MODULE_PARM_DESC(qsb_tau, "Cell delay variation. Value must be > 0");
 112 MODULE_PARM(qsb_srvm, "i");
 113 MODULE_PARM_DESC(qsb_srvm, "Maximum burst size");
 114 MODULE_PARM(qsb_tstep, "i");
 115 MODULE_PARM_DESC(qsb_tstep, "n*32 cycles per sbs cycles n=1,2,4");
 116
 117 MODULE_PARM(write_descriptor_delay, "i");
 118 MODULE_PARM_DESC(write_descriptor_delay, "PPE core clock cycles between descriptor write and effectiveness in external RAM");
 119
 120 MODULE_PARM(aal5_fill_pattern, "i");
 121 MODULE_PARM_DESC(aal5_fill_pattern, "Filling pattern (PAD) for AAL5 frames");
 122 MODULE_PARM(aal5r_max_packet_size, "i");
 123 MODULE_PARM_DESC(aal5r_max_packet_size, "Max packet size in byte for downstream AAL5 frames");
 124 MODULE_PARM(aal5r_min_packet_size, "i");
 125 MODULE_PARM_DESC(aal5r_min_packet_size, "Min packet size in byte for downstream AAL5 frames");
 126 MODULE_PARM(aal5s_max_packet_size, "i");
 127 MODULE_PARM_DESC(aal5s_max_packet_size, "Max packet size in byte for upstream AAL5 frames");
 128 MODULE_PARM(aal5s_min_packet_size, "i");
 129 MODULE_PARM_DESC(aal5s_min_packet_size, "Min packet size in byte for upstream AAL5 frames");
 130 MODULE_PARM(aal5r_drop_error_packet, "i");
 131 MODULE_PARM_DESC(aal5r_drop_error_packet, "Non-zero value to drop error packet for downstream");
 132
 133 MODULE_PARM(dma_rx_descriptor_length, "i");
 134 MODULE_PARM_DESC(dma_rx_descriptor_length, "Number of descriptor assigned to DMA RX channel (>16)");
 135 MODULE_PARM(dma_tx_descriptor_length, "i");
 136 MODULE_PARM_DESC(dma_tx_descriptor_length, "Number of descriptor assigned to DMA TX channel (>16)");
 137 MODULE_PARM(dma_rx_clp1_descriptor_threshold, "i");
 138 MODULE_PARM_DESC(dma_rx_clp1_descriptor_threshold, "Descriptor threshold for cells with cell loss priority 1");
 139
 140
 141
 142 /*
 143  * ####################################
 144  *              Definition
 145  * ####################################
 146  */
 147
 148 #ifdef CONFIG_AMAZON_SE
 149   #define ENABLE_LESS_CACHE_INV                 1
 150   #define LESS_CACHE_INV_LEN                    96
 151 #endif
 152
 153 #define DUMP_SKB_LEN                            ~0
 154
 155
 156
 157 /*
 158  * ####################################
 159  *             Declaration
 160  * ####################################
 161  */
 162
 163 /*
 164  *  Network Operations
 165  */
 166 static int ppe_ioctl(struct atm_dev *, unsigned int, void *);
 167 static int ppe_open(struct atm_vcc *);
 168 static void ppe_close(struct atm_vcc *);
 169 static int ppe_send(struct atm_vcc *, struct sk_buff *);
 170 static int ppe_send_oam(struct atm_vcc *, void *, int);
 171 static int ppe_change_qos(struct atm_vcc *, struct atm_qos *, int);
 172
 173 /*
 174  *  ADSL LED
 175  */
 176 static inline void adsl_led_flash(void);
 177
 178 /*
 179  *  64-bit operation used by MIB calculation
 180  */
 181 static inline void u64_add_u32(ppe_u64_t, unsigned int, ppe_u64_t *);
 182
 183 /*
 184  *  buffer manage functions
 185  */
 186 static inline struct sk_buff* alloc_skb_rx(void);
 187 static inline struct sk_buff* alloc_skb_tx(unsigned int);
 188 struct sk_buff* atm_alloc_tx(struct atm_vcc *, unsigned int);
 189 static inline void atm_free_tx_skb_vcc(struct sk_buff *, struct atm_vcc *);
 190 static inline struct sk_buff *get_skb_rx_pointer(unsigned int);
 191 static inline int get_tx_desc(unsigned int);
 192 static struct sk_buff* skb_duplicate(struct sk_buff *);
 193 static struct sk_buff* skb_break_away_from_protocol(struct sk_buff *);
 194
 195 /*
 196  *  mailbox handler and signal function
 197  */
 198 static inline void mailbox_oam_rx_handler(void);
 199 static inline void mailbox_aal_rx_handler(void);
 200 static irqreturn_t mailbox_irq_handler(int, void *);
 201 static inline void mailbox_signal(unsigned int, int);
 202
 203 /*
 204  *  QSB & HTU setting functions
 205  */
 206 static void set_qsb(struct atm_vcc *, struct atm_qos *, unsigned int);
 207 static void qsb_global_set(void);
 208 static inline void set_htu_entry(unsigned int, unsigned int, unsigned int, int, int);
 209 static inline void clear_htu_entry(unsigned int);
 210 static void validate_oam_htu_entry(void);
 211 static void invalidate_oam_htu_entry(void);
 212
 213 /*
 214  *  look up for connection ID
 215  */
 216 static inline int find_vpi(unsigned int);
 217 static inline int find_vpivci(unsigned int, unsigned int);
 218 static inline int find_vcc(struct atm_vcc *);
 219
 220 static inline int ifx_atm_version(const struct ltq_atm_ops *ops, char *);
 221
 222 /*
 223  *  Init & clean-up functions
 224  */
 225 static inline void check_parameters(void);
 226 static inline int init_priv_data(void);
 227 static inline void clear_priv_data(void);
 228 static inline void init_rx_tables(void);
 229 static inline void init_tx_tables(void);
 230
 231 /*
 232  *  Exteranl Function
 233  */
 234 #if defined(CONFIG_IFX_OAM) || defined(CONFIG_IFX_OAM_MODULE)
 235 extern void ifx_push_oam(unsigned char *);
 236 #else
 237 static inline void ifx_push_oam(unsigned char *dummy) {}
 238 #endif
 239
 240 #if defined(CONFIG_IFXMIPS_DSL_CPE_MEI) || defined(CONFIG_IFXMIPS_DSL_CPE_MEI_MODULE)
 241 extern int ifx_mei_atm_showtime_check(int *is_showtime, struct port_cell_info *port_cell, void **xdata_addr);
 242 extern int (*ifx_mei_atm_showtime_enter)(struct port_cell_info *, void *);
 243
 244 extern int (*ifx_mei_atm_showtime_exit)(void);
 245 extern int ifx_mei_atm_led_blink(void);
 246 #else
 247 static inline int ifx_mei_atm_led_blink(void) { return 0; }
 248 static inline int ifx_mei_atm_showtime_check(int *is_showtime, struct port_cell_info *port_cell, void **xdata_addr)
 249 {
 250         if ( is_showtime != NULL )
 251                 *is_showtime = 0;
 252         return 0;
 253 }
 254 int (*ifx_mei_atm_showtime_enter)(struct port_cell_info *, void *) = NULL;
 255 EXPORT_SYMBOL(ifx_mei_atm_showtime_enter);
 256
 257 int (*ifx_mei_atm_showtime_exit)(void) = NULL;
 258 EXPORT_SYMBOL(ifx_mei_atm_showtime_exit);
 259
 260 #endif
 261
 262 static struct sk_buff* (*ifx_atm_alloc_tx)(struct atm_vcc *, unsigned int) = NULL;
 263
 264 static struct atm_priv_data g_atm_priv_data;
 265
 266 static struct atmdev_ops g_ifx_atm_ops = {
 267         .open = ppe_open,
 268         .close = ppe_close,
 269         .ioctl = ppe_ioctl,
 270         .send = ppe_send,
 271         .send_oam = ppe_send_oam,
 272         .change_qos = ppe_change_qos,
 273         .owner = THIS_MODULE,
 274 };
 275
 276 static int g_showtime = 0;
 277 static void *g_xdata_addr = NULL;
 278
 279 static int ppe_ioctl(struct atm_dev *dev, unsigned int cmd, void *arg)
 280 {
 281         int ret = 0;
 282         atm_cell_ifEntry_t mib_cell;
 283         atm_aal5_ifEntry_t mib_aal5;
 284         atm_aal5_vcc_x_t mib_vcc;
 285         unsigned int value;
 286         int conn;
 287
 288         if ( _IOC_TYPE(cmd) != PPE_ATM_IOC_MAGIC
 289                         || _IOC_NR(cmd) >= PPE_ATM_IOC_MAXNR )
 290                 return -ENOTTY;
 291
 292         if ( _IOC_DIR(cmd) & _IOC_READ )
 293                 ret = !access_ok(VERIFY_WRITE, arg, _IOC_SIZE(cmd));
 294         else if ( _IOC_DIR(cmd) & _IOC_WRITE )
 295                 ret = !access_ok(VERIFY_READ, arg, _IOC_SIZE(cmd));
 296         if ( ret )
 297                 return -EFAULT;
 298
 299         switch (cmd) {
 300         case PPE_ATM_MIB_CELL:  /*  cell level  MIB */
 301                 /*  These MIB should be read at ARC side, now put zero only.    */
 302                 mib_cell.ifHCInOctets_h = 0;
 303                 mib_cell.ifHCInOctets_l = 0;
 304                 mib_cell.ifHCOutOctets_h = 0;
 305                 mib_cell.ifHCOutOctets_l = 0;
 306                 mib_cell.ifInErrors = 0;
 307                 mib_cell.ifInUnknownProtos = WAN_MIB_TABLE->wrx_drophtu_cell;
 308                 mib_cell.ifOutErrors = 0;
 309
 310                 ret = sizeof(mib_cell) - copy_to_user(arg, &mib_cell, sizeof(mib_cell));
 311                 break;
 312
 313         case PPE_ATM_MIB_AAL5:  /*  AAL5 MIB    */
 314                 value = WAN_MIB_TABLE->wrx_total_byte;
 315                 u64_add_u32(g_atm_priv_data.wrx_total_byte, value - g_atm_priv_data.prev_wrx_total_byte, &g_atm_priv_data.wrx_total_byte);
 316                 g_atm_priv_data.prev_wrx_total_byte = value;
 317                 mib_aal5.ifHCInOctets_h = g_atm_priv_data.wrx_total_byte.h;
 318                 mib_aal5.ifHCInOctets_l = g_atm_priv_data.wrx_total_byte.l;
 319
 320                 value = WAN_MIB_TABLE->wtx_total_byte;
 321                 u64_add_u32(g_atm_priv_data.wtx_total_byte, value - g_atm_priv_data.prev_wtx_total_byte, &g_atm_priv_data.wtx_total_byte);
 322                 g_atm_priv_data.prev_wtx_total_byte = value;
 323                 mib_aal5.ifHCOutOctets_h = g_atm_priv_data.wtx_total_byte.h;
 324                 mib_aal5.ifHCOutOctets_l = g_atm_priv_data.wtx_total_byte.l;
 325
 326                 mib_aal5.ifInUcastPkts  = g_atm_priv_data.wrx_pdu;
 327                 mib_aal5.ifOutUcastPkts = WAN_MIB_TABLE->wtx_total_pdu;
 328                 mib_aal5.ifInErrors     = WAN_MIB_TABLE->wrx_err_pdu;
 329                 mib_aal5.ifInDiscards   = WAN_MIB_TABLE->wrx_dropdes_pdu + g_atm_priv_data.wrx_drop_pdu;
 330                 mib_aal5.ifOutErros     = g_atm_priv_data.wtx_err_pdu;
 331                 mib_aal5.ifOutDiscards  = g_atm_priv_data.wtx_drop_pdu;
 332
 333                 ret = sizeof(mib_aal5) - copy_to_user(arg, &mib_aal5, sizeof(mib_aal5));
 334                 break;
 335
 336         case PPE_ATM_MIB_VCC:   /*  VCC related MIB */
 337                 copy_from_user(&mib_vcc, arg, sizeof(mib_vcc));
 338                 conn = find_vpivci(mib_vcc.vpi, mib_vcc.vci);
 339                 if (conn >= 0) {
 340                         mib_vcc.mib_vcc.aal5VccCrcErrors     = g_atm_priv_data.conn[conn].aal5_vcc_crc_err;
 341                         mib_vcc.mib_vcc.aal5VccOverSizedSDUs = g_atm_priv_data.conn[conn].aal5_vcc_oversize_sdu;
 342                         mib_vcc.mib_vcc.aal5VccSarTimeOuts   = 0;   /*  no timer support    */
 343                         ret = sizeof(mib_vcc) - copy_to_user(arg, &mib_vcc, sizeof(mib_vcc));
 344                 } else
 345                         ret = -EINVAL;
 346                 break;
 347
 348         default:
 349                 ret = -ENOIOCTLCMD;
 350         }
 351
 352         return ret;
 353 }
 354
 355 static int ppe_open(struct atm_vcc *vcc)
 356 {
 357         int ret;
 358         short vpi = vcc->vpi;
 359         int   vci = vcc->vci;
 360         struct port *port = &g_atm_priv_data.port[(int)vcc->dev->dev_data];
 361         int conn;
 362         int f_enable_irq = 0;
 363
 364         if ( vcc->qos.aal != ATM_AAL5 && vcc->qos.aal != ATM_AAL0 )
 365                 return -EPROTONOSUPPORT;
 366
 367 #if !defined(DISABLE_QOS_WORKAROUND) || !DISABLE_QOS_WORKAROUND
 368         /*  check bandwidth */
 369         if ( (vcc->qos.txtp.traffic_class == ATM_CBR && vcc->qos.txtp.max_pcr > (port->tx_max_cell_rate - port->tx_current_cell_rate))
 370                 || (vcc->qos.txtp.traffic_class == ATM_VBR_RT && vcc->qos.txtp.max_pcr > (port->tx_max_cell_rate - port->tx_current_cell_rate))
 371                 || (vcc->qos.txtp.traffic_class == ATM_VBR_NRT && vcc->qos.txtp.scr > (port->tx_max_cell_rate - port->tx_current_cell_rate))
 372                 || (vcc->qos.txtp.traffic_class == ATM_UBR_PLUS && vcc->qos.txtp.min_pcr > (port->tx_max_cell_rate - port->tx_current_cell_rate)) )
 373         {
 374                 ret = -EINVAL;
 375                 goto PPE_OPEN_EXIT;
 376         }
 377 #endif
 378
 379         /*  check existing vpi,vci  */
 380         conn = find_vpivci(vpi, vci);
 381         if ( conn >= 0 ) {
 382                 ret = -EADDRINUSE;
 383                 goto PPE_OPEN_EXIT;
 384         }
 385
 386         /*  check whether it need to enable irq */
 387         if ( g_atm_priv_data.conn_table == 0 )
 388                 f_enable_irq = 1;
 389
 390         /*  allocate connection */
 391         for ( conn = 0; conn < MAX_PVC_NUMBER; conn++ ) {
 392                 if ( test_and_set_bit(conn, &g_atm_priv_data.conn_table) == 0 ) {
 393                         g_atm_priv_data.conn[conn].vcc = vcc;
 394                         break;
 395                 }
 396         }
 397         if ( conn == MAX_PVC_NUMBER ) {
 398                 ret = -EINVAL;
 399                 goto PPE_OPEN_EXIT;
 400         }
 401
 402         /*  reserve bandwidth   */
 403         switch ( vcc->qos.txtp.traffic_class ) {
 404         case ATM_CBR:
 405         case ATM_VBR_RT:
 406                 port->tx_current_cell_rate += vcc->qos.txtp.max_pcr;
 407                 break;
 408         case ATM_VBR_NRT:
 409                 port->tx_current_cell_rate += vcc->qos.txtp.scr;
 410                 break;
 411         case ATM_UBR_PLUS:
 412                 port->tx_current_cell_rate += vcc->qos.txtp.min_pcr;
 413                 break;
 414         }
 415
 416         /*  set qsb */
 417         set_qsb(vcc, &vcc->qos, conn);
 418
 419         /*  update atm_vcc structure    */
 420         vcc->itf = (int)vcc->dev->dev_data;
 421         vcc->vpi = vpi;
 422         vcc->vci = vci;
 423         set_bit(ATM_VF_READY, &vcc->flags);
 424
 425         /*  enable irq  */
 426         if ( f_enable_irq ) {
 427                 ifx_atm_alloc_tx = atm_alloc_tx;
 428
 429                 *MBOX_IGU1_ISRC = (1 << RX_DMA_CH_AAL) | (1 << RX_DMA_CH_OAM);
 430                 *MBOX_IGU1_IER  = (1 << RX_DMA_CH_AAL) | (1 << RX_DMA_CH_OAM);
 431
 432                 enable_irq(PPE_MAILBOX_IGU1_INT);
 433         }
 434
 435         /*  set port    */
 436         WTX_QUEUE_CONFIG(conn + FIRST_QSB_QID)->sbid = (int)vcc->dev->dev_data;
 437
 438         /*  set htu entry   */
 439         set_htu_entry(vpi, vci, conn, vcc->qos.aal == ATM_AAL5 ? 1 : 0, 0);
 440
 441         ret = 0;
 442
 443 PPE_OPEN_EXIT:
 444         return ret;
 445 }
 446
 447 static void ppe_close(struct atm_vcc *vcc)
 448 {
 449         int conn;
 450         struct port *port;
 451         struct connection *connection;
 452         if ( vcc == NULL )
 453                 return;
 454
 455         /*  get connection id   */
 456         conn = find_vcc(vcc);
 457         if ( conn < 0 ) {
 458                 pr_err("can't find vcc\n");
 459                 goto PPE_CLOSE_EXIT;
 460         }
 461         connection = &g_atm_priv_data.conn[conn];
 462         port = &g_atm_priv_data.port[connection->port];
 463
 464         /*  clear htu   */
 465         clear_htu_entry(conn);
 466
 467         /*  release connection  */
 468         connection->vcc = NULL;
 469         connection->aal5_vcc_crc_err = 0;
 470         connection->aal5_vcc_oversize_sdu = 0;
 471         clear_bit(conn, &g_atm_priv_data.conn_table);
 472
 473         /*  disable irq */
 474         if ( g_atm_priv_data.conn_table == 0 ) {
 475                 disable_irq(PPE_MAILBOX_IGU1_INT);
 476                 ifx_atm_alloc_tx = NULL;
 477         }
 478
 479         /*  release bandwidth   */
 480         switch ( vcc->qos.txtp.traffic_class )
 481         {
 482         case ATM_CBR:
 483         case ATM_VBR_RT:
 484                 port->tx_current_cell_rate -= vcc->qos.txtp.max_pcr;
 485                 break;
 486         case ATM_VBR_NRT:
 487                 port->tx_current_cell_rate -= vcc->qos.txtp.scr;
 488                 break;
 489         case ATM_UBR_PLUS:
 490                 port->tx_current_cell_rate -= vcc->qos.txtp.min_pcr;
 491                 break;
 492         }
 493
 494 PPE_CLOSE_EXIT:
 495         return;
 496 }
 497
 498 static int ppe_send(struct atm_vcc *vcc, struct sk_buff *skb)
 499 {
 500         int ret;
 501         int conn;
 502         int desc_base;
 503         struct tx_descriptor reg_desc = {0};
 504         struct sk_buff *new_skb;
 505
 506         if ( vcc == NULL || skb == NULL )
 507                 return -EINVAL;
 508
 509         skb_get(skb);
 510         atm_free_tx_skb_vcc(skb, vcc);
 511
 512         conn = find_vcc(vcc);
 513         if ( conn < 0 ) {
 514                 ret = -EINVAL;
 515                 goto FIND_VCC_FAIL;
 516         }
 517
 518         if ( !g_showtime ) {
 519                 pr_debug("not in showtime\n");
 520                 ret = -EIO;
 521                 goto PPE_SEND_FAIL;
 522         }
 523
 524         if ( vcc->qos.aal == ATM_AAL5 ) {
 525                 int byteoff;
 526                 int datalen;
 527                 struct tx_inband_header *header;
 528
 529                 byteoff = (unsigned int)skb->data & (DATA_BUFFER_ALIGNMENT - 1);
 530                 if ( skb_headroom(skb) < byteoff + TX_INBAND_HEADER_LENGTH )
 531                         new_skb = skb_duplicate(skb);
 532                 else
 533                         new_skb = skb_break_away_from_protocol(skb);
 534                 if ( new_skb == NULL ) {
 535                         pr_err("either skb_duplicate or skb_break_away_from_protocol fail\n");
 536                         ret = -ENOMEM;
 537                         goto PPE_SEND_FAIL;
 538                 }
 539                 dev_kfree_skb_any(skb);
 540                 skb = new_skb;
 541
 542                 datalen = skb->len;
 543                 byteoff = (unsigned int)skb->data & (DATA_BUFFER_ALIGNMENT - 1);
 544
 545                 skb_push(skb, byteoff + TX_INBAND_HEADER_LENGTH);
 546
 547                 header = (struct tx_inband_header *)skb->data;
 548
 549                 /*  setup inband trailer    */
 550                 header->uu   = 0;
 551                 header->cpi  = 0;
 552                 header->pad  = aal5_fill_pattern;
 553                 header->res1 = 0;
 554
 555                 /*  setup cell header   */
 556                 header->clp  = (vcc->atm_options & ATM_ATMOPT_CLP) ? 1 : 0;
 557                 header->pti  = ATM_PTI_US0;
 558                 header->vci  = vcc->vci;
 559                 header->vpi  = vcc->vpi;
 560                 header->gfc  = 0;
 561
 562                 /*  setup descriptor    */
 563                 reg_desc.dataptr = (unsigned int)skb->data >> 2;
 564                 reg_desc.datalen = datalen;
 565                 reg_desc.byteoff = byteoff;
 566                 reg_desc.iscell  = 0;
 567         } else {
 568                 /*  if data pointer is not aligned, allocate new sk_buff    */
 569                 if ( ((unsigned int)skb->data & (DATA_BUFFER_ALIGNMENT - 1)) != 0 ) {
 570                         pr_err("skb->data not aligned\n");
 571                         new_skb = skb_duplicate(skb);
 572                 } else
 573                         new_skb = skb_break_away_from_protocol(skb);
 574                 if ( new_skb == NULL ) {
 575                         pr_err("either skb_duplicate or skb_break_away_from_protocol fail\n");
 576                         ret = -ENOMEM;
 577                         goto PPE_SEND_FAIL;
 578                 }
 579                 dev_kfree_skb_any(skb);
 580                 skb = new_skb;
 581
 582                 reg_desc.dataptr = (unsigned int)skb->data >> 2;
 583                 reg_desc.datalen = skb->len;
 584                 reg_desc.byteoff = 0;
 585                 reg_desc.iscell  = 1;
 586         }
 587
 588         reg_desc.own = 1;
 589         reg_desc.c = 1;
 590         reg_desc.sop = reg_desc.eop = 1;
 591
 592         desc_base = get_tx_desc(conn);
 593         if ( desc_base < 0 ) {
 594                 pr_debug("ALLOC_TX_CONNECTION_FAIL\n");
 595                 ret = -EIO;
 596                 goto PPE_SEND_FAIL;
 597         }
 598
 599         if ( vcc->stats )
 600                 atomic_inc(&vcc->stats->tx);
 601         if ( vcc->qos.aal == ATM_AAL5 )
 602                 g_atm_priv_data.wtx_pdu++;
 603
 604         /*  update descriptor send pointer  */
 605         if ( g_atm_priv_data.conn[conn].tx_skb[desc_base] != NULL )
 606                 dev_kfree_skb_any(g_atm_priv_data.conn[conn].tx_skb[desc_base]);
 607         g_atm_priv_data.conn[conn].tx_skb[desc_base] = skb;
 608
 609         /*  write discriptor to memory and write back cache */
 610         g_atm_priv_data.conn[conn].tx_desc[desc_base] = reg_desc;
 611         dma_cache_wback((unsigned long)skb->data, skb->len);
 612
 613         mailbox_signal(conn, 1);
 614
 615         adsl_led_flash();
 616
 617         return 0;
 618
 619 FIND_VCC_FAIL:
 620         pr_err("FIND_VCC_FAIL\n");
 621         g_atm_priv_data.wtx_err_pdu++;
 622         dev_kfree_skb_any(skb);
 623         return ret;
 624
 625 PPE_SEND_FAIL:
 626         if ( vcc->qos.aal == ATM_AAL5 )
 627                 g_atm_priv_data.wtx_drop_pdu++;
 628         if ( vcc->stats )
 629                 atomic_inc(&vcc->stats->tx_err);
 630         dev_kfree_skb_any(skb);
 631         return ret;
 632 }
 633
 634 /* operation and maintainance */
 635 static int ppe_send_oam(struct atm_vcc *vcc, void *cell, int flags)
 636 {
 637         int conn;
 638         struct uni_cell_header *uni_cell_header = (struct uni_cell_header *)cell;
 639         int desc_base;
 640         struct sk_buff *skb;
 641         struct tx_descriptor reg_desc = {0};
 642
 643         if ( ((uni_cell_header->pti == ATM_PTI_SEGF5 || uni_cell_header->pti == ATM_PTI_E2EF5)
 644                         && find_vpivci(uni_cell_header->vpi, uni_cell_header->vci) < 0)
 645                         || ((uni_cell_header->vci == 0x03 || uni_cell_header->vci == 0x04)
 646                         && find_vpi(uni_cell_header->vpi) < 0) )
 647         {
 648                 g_atm_priv_data.wtx_err_oam++;
 649                 return -EINVAL;
 650         }
 651
 652         if ( !g_showtime ) {
 653                 pr_err("not in showtime\n");
 654                 g_atm_priv_data.wtx_drop_oam++;
 655                 return -EIO;
 656         }
 657
 658         conn = find_vcc(vcc);
 659         if ( conn < 0 ) {
 660                 pr_err("FIND_VCC_FAIL\n");
 661                 g_atm_priv_data.wtx_drop_oam++;
 662                 return -EINVAL;
 663         }
 664
 665         skb = alloc_skb_tx(CELL_SIZE);
 666         if ( skb == NULL ) {
 667                 pr_err("ALLOC_SKB_TX_FAIL\n");
 668                 g_atm_priv_data.wtx_drop_oam++;
 669                 return -ENOMEM;
 670         }
 671         skb_put(skb, CELL_SIZE);
 672         memcpy(skb->data, cell, CELL_SIZE);
 673
 674         reg_desc.dataptr = (unsigned int)skb->data >> 2;
 675         reg_desc.datalen = CELL_SIZE;
 676         reg_desc.byteoff = 0;
 677         reg_desc.iscell  = 1;
 678
 679         reg_desc.own = 1;
 680         reg_desc.c = 1;
 681         reg_desc.sop = reg_desc.eop = 1;
 682
 683         desc_base = get_tx_desc(conn);
 684         if ( desc_base < 0 ) {
 685                 dev_kfree_skb_any(skb);
 686                 pr_err("ALLOC_TX_CONNECTION_FAIL\n");
 687                 g_atm_priv_data.wtx_drop_oam++;
 688                 return -EIO;
 689         }
 690
 691         if ( vcc->stats )
 692                 atomic_inc(&vcc->stats->tx);
 693
 694         /*  update descriptor send pointer  */
 695         if ( g_atm_priv_data.conn[conn].tx_skb[desc_base] != NULL )
 696                 dev_kfree_skb_any(g_atm_priv_data.conn[conn].tx_skb[desc_base]);
 697         g_atm_priv_data.conn[conn].tx_skb[desc_base] = skb;
 698
 699         /*  write discriptor to memory and write back cache */
 700         g_atm_priv_data.conn[conn].tx_desc[desc_base] = reg_desc;
 701         dma_cache_wback((unsigned long)skb->data, CELL_SIZE);
 702
 703         mailbox_signal(conn, 1);
 704
 705         g_atm_priv_data.wtx_oam++;
 706         adsl_led_flash();
 707
 708         return 0;
 709 }
 710
 711 static int ppe_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, int flags)
 712 {
 713         int conn;
 714
 715         if ( vcc == NULL || qos == NULL )
 716                 return -EINVAL;
 717
 718         conn = find_vcc(vcc);
 719         if ( conn < 0 )
 720                 return -EINVAL;
 721
 722         set_qsb(vcc, qos, conn);
 723
 724         return 0;
 725 }
 726
 727 static inline void adsl_led_flash(void)
 728 {
 729         ifx_mei_atm_led_blink();
 730 }
 731
 732 /*
 733 *  Description:
 734 *    Add a 32-bit value to 64-bit value, and put result in a 64-bit variable.
 735 *  Input:
 736 *    opt1 --- ppe_u64_t, first operand, a 64-bit unsigned integer value
 737 *    opt2 --- unsigned int, second operand, a 32-bit unsigned integer value
 738 *    ret  --- ppe_u64_t, pointer to a variable to hold result
 739 *  Output:
 740 *    none
 741 */
 742 static inline void u64_add_u32(ppe_u64_t opt1, unsigned int opt2, ppe_u64_t *ret)
 743 {
 744         ret->l = opt1.l + opt2;
 745         if ( ret->l < opt1.l || ret->l < opt2 )
 746                 ret->h++;
 747 }
 748
 749 static inline struct sk_buff* alloc_skb_rx(void)
 750 {
 751         struct sk_buff *skb;
 752
 753         skb = dev_alloc_skb(RX_DMA_CH_AAL_BUF_SIZE + DATA_BUFFER_ALIGNMENT);
 754         if ( skb != NULL ) {
 755                 /*  must be burst length alignment  */
 756                 if ( ((unsigned int)skb->data & (DATA_BUFFER_ALIGNMENT - 1)) != 0 )
 757                         skb_reserve(skb, ~((unsigned int)skb->data + (DATA_BUFFER_ALIGNMENT - 1)) & (DATA_BUFFER_ALIGNMENT - 1));
 758                 /*  pub skb in reserved area "skb->data - 4"    */
 759                 *((struct sk_buff **)skb->data - 1) = skb;
 760                 /*  write back and invalidate cache */
 761                 dma_cache_wback_inv((unsigned long)skb->data - sizeof(skb), sizeof(skb));
 762                 /*  invalidate cache    */
 763 #if defined(ENABLE_LESS_CACHE_INV) && ENABLE_LESS_CACHE_INV
 764                 dma_cache_inv((unsigned long)skb->data, LESS_CACHE_INV_LEN);
 765 #else
 766                 dma_cache_inv((unsigned long)skb->data, RX_DMA_CH_AAL_BUF_SIZE);
 767 #endif
 768         }
 769         return skb;
 770 }
 771
 772 static inline struct sk_buff* alloc_skb_tx(unsigned int size)
 773 {
 774         struct sk_buff *skb;
 775
 776         /*  allocate memory including header and padding    */
 777         size += TX_INBAND_HEADER_LENGTH + MAX_TX_PACKET_ALIGN_BYTES + MAX_TX_PACKET_PADDING_BYTES;
 778         size &= ~(DATA_BUFFER_ALIGNMENT - 1);
 779         skb = dev_alloc_skb(size + DATA_BUFFER_ALIGNMENT);
 780         /*  must be burst length alignment  */
 781         if ( skb != NULL )
 782                 skb_reserve(skb, (~((unsigned int)skb->data + (DATA_BUFFER_ALIGNMENT - 1)) & (DATA_BUFFER_ALIGNMENT - 1)) + TX_INBAND_HEADER_LENGTH);
 783         return skb;
 784 }
 785
 786 struct sk_buff* atm_alloc_tx(struct atm_vcc *vcc, unsigned int size)
 787 {
 788         int conn;
 789         struct sk_buff *skb;
 790
 791         /*  oversize packet */
 792         if ( size > aal5s_max_packet_size ) {
 793                 pr_err("atm_alloc_tx: oversize packet\n");
 794                 return NULL;
 795         }
 796         /*  send buffer overflow    */
 797         if ( sk_wmem_alloc_get(sk_atm(vcc)) && !atm_may_send(vcc, size) ) {
 798                 pr_err("atm_alloc_tx: send buffer overflow\n");
 799                 return NULL;
 800         }
 801         conn = find_vcc(vcc);
 802         if ( conn < 0 ) {
 803                 pr_err("atm_alloc_tx: unknown VCC\n");
 804                 return NULL;
 805         }
 806
 807         skb = dev_alloc_skb(size);
 808         if ( skb == NULL ) {
 809                 pr_err("atm_alloc_tx: sk buffer is used up\n");
 810                 return NULL;
 811         }
 812
 813         atomic_add(skb->truesize, &sk_atm(vcc)->sk_wmem_alloc);
 814
 815         return skb;
 816 }
 817
 818 static inline void atm_free_tx_skb_vcc(struct sk_buff *skb, struct atm_vcc *vcc)
 819 {
 820         if ( vcc->pop != NULL )
 821                 vcc->pop(vcc, skb);
 822         else
 823                 dev_kfree_skb_any(skb);
 824 }
 825
 826 static inline struct sk_buff *get_skb_rx_pointer(unsigned int dataptr)
 827 {
 828         unsigned int skb_dataptr;
 829         struct sk_buff *skb;
 830
 831         skb_dataptr = ((dataptr - 1) << 2) | KSEG1;
 832         skb = *(struct sk_buff **)skb_dataptr;
 833
 834         ASSERT((unsigned int)skb >= KSEG0, "invalid skb - skb = %#08x, dataptr = %#08x", (unsigned int)skb, dataptr);
 835         ASSERT(((unsigned int)skb->data | KSEG1) == ((dataptr << 2) | KSEG1), "invalid skb - skb = %#08x, skb->data = %#08x, dataptr = %#08x", (unsigned int)skb, (unsigned int)skb->data, dataptr);
 836
 837         return skb;
 838 }
 839
 840 static inline int get_tx_desc(unsigned int conn)
 841 {
 842         int desc_base = -1;
 843         struct connection *p_conn = &g_atm_priv_data.conn[conn];
 844
 845         if ( p_conn->tx_desc[p_conn->tx_desc_pos].own == 0 ) {
 846                 desc_base = p_conn->tx_desc_pos;
 847                 if ( ++(p_conn->tx_desc_pos) == dma_tx_descriptor_length )
 848                         p_conn->tx_desc_pos = 0;
 849         }
 850
 851         return desc_base;
 852 }
 853
 854 static struct sk_buff* skb_duplicate(struct sk_buff *skb)
 855 {
 856         struct sk_buff *new_skb;
 857
 858         new_skb = alloc_skb_tx(skb->len);
 859         if ( new_skb == NULL )
 860                 return NULL;
 861
 862         skb_put(new_skb, skb->len);
 863         memcpy(new_skb->data, skb->data, skb->len);
 864
 865         return new_skb;
 866 }
 867
 868 static struct sk_buff* skb_break_away_from_protocol(struct sk_buff *skb)
 869 {
 870         struct sk_buff *new_skb;
 871
 872         if ( skb_shared(skb) ) {
 873                 new_skb = skb_clone(skb, GFP_ATOMIC);
 874                 if ( new_skb == NULL )
 875                         return NULL;
 876         } else
 877                 new_skb = skb_get(skb);
 878
 879         skb_dst_drop(new_skb);
 880 #if defined(CONFIG_NF_CONNTRACK) || defined(CONFIG_NF_CONNTRACK_MODULE)
 881         nf_conntrack_put(new_skb->nfct);
 882         new_skb->nfct = NULL;
 883         nf_conntrack_put_reasm(new_skb->nfct_reasm);
 884         new_skb->nfct_reasm = NULL;
 885   #ifdef CONFIG_BRIDGE_NETFILTER
 886         nf_bridge_put(new_skb->nf_bridge);
 887         new_skb->nf_bridge = NULL;
 888   #endif
 889 #endif
 890
 891         return new_skb;
 892 }
 893
 894 static inline void mailbox_oam_rx_handler(void)
 895 {
 896         unsigned int vlddes = WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_OAM)->vlddes;
 897         struct rx_descriptor reg_desc;
 898         struct uni_cell_header *header;
 899         int conn;
 900         struct atm_vcc *vcc;
 901         unsigned int i;
 902
 903         for ( i = 0; i < vlddes; i++ ) {
 904                 unsigned int loop_count = 0;
 905
 906                 do {
 907                         reg_desc = g_atm_priv_data.oam_desc[g_atm_priv_data.oam_desc_pos];
 908                         if ( ++loop_count == 1000 )
 909                                 break;
 910                 } while ( reg_desc.own || !reg_desc.c );    //  keep test OWN and C bit until data is ready
 911                 ASSERT(loop_count == 1, "loop_count = %u, own = %d, c = %d, oam_desc_pos = %u", loop_count, (int)reg_desc.own, (int)reg_desc.c, g_atm_priv_data.oam_desc_pos);
 912
 913                 header = (struct uni_cell_header *)&g_atm_priv_data.oam_buf[g_atm_priv_data.oam_desc_pos * RX_DMA_CH_OAM_BUF_SIZE];
 914
 915                 if ( header->pti == ATM_PTI_SEGF5 || header->pti == ATM_PTI_E2EF5 )
 916                         conn = find_vpivci(header->vpi, header->vci);
 917                 else if ( header->vci == 0x03 || header->vci == 0x04 )
 918                         conn = find_vpi(header->vpi);
 919                 else
 920                         conn = -1;
 921
 922                 if ( conn >= 0 && g_atm_priv_data.conn[conn].vcc != NULL ) {
 923                         vcc = g_atm_priv_data.conn[conn].vcc;
 924
 925                         if ( vcc->push_oam != NULL )
 926                                 vcc->push_oam(vcc, header);
 927                         else
 928                                 ifx_push_oam((unsigned char *)header);
 929
 930                         g_atm_priv_data.wrx_oam++;
 931
 932                         adsl_led_flash();
 933                 } else
 934                         g_atm_priv_data.wrx_drop_oam++;
 935
 936                 reg_desc.byteoff = 0;
 937                 reg_desc.datalen = RX_DMA_CH_OAM_BUF_SIZE;
 938                 reg_desc.own = 1;
 939                 reg_desc.c   = 0;
 940
 941                 g_atm_priv_data.oam_desc[g_atm_priv_data.oam_desc_pos] = reg_desc;
 942                 if ( ++g_atm_priv_data.oam_desc_pos == RX_DMA_CH_OAM_DESC_LEN )
 943                         g_atm_priv_data.oam_desc_pos = 0;
 944
 945                 dma_cache_inv((unsigned long)header, CELL_SIZE);
 946                 mailbox_signal(RX_DMA_CH_OAM, 0);
 947         }
 948 }
 949
 950 static inline void mailbox_aal_rx_handler(void)
 951 {
 952         unsigned int vlddes = WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_AAL)->vlddes;
 953         struct rx_descriptor reg_desc;
 954         int conn;
 955         struct atm_vcc *vcc;
 956         struct sk_buff *skb, *new_skb;
 957         struct rx_inband_trailer *trailer;
 958         unsigned int i;
 959
 960         for ( i = 0; i < vlddes; i++ ) {
 961                 unsigned int loop_count = 0;
 962
 963                 do {
 964                         reg_desc = g_atm_priv_data.aal_desc[g_atm_priv_data.aal_desc_pos];
 965                         if ( ++loop_count == 1000 )
 966                                 break;
 967                 } while ( reg_desc.own || !reg_desc.c );    //  keep test OWN and C bit until data is ready
 968                 ASSERT(loop_count == 1, "loop_count = %u, own = %d, c = %d, aal_desc_pos = %u", loop_count, (int)reg_desc.own, (int)reg_desc.c, g_atm_priv_data.aal_desc_pos);
 969
 970                 conn = reg_desc.id;
 971
 972                 if ( g_atm_priv_data.conn[conn].vcc != NULL ) {
 973                         vcc = g_atm_priv_data.conn[conn].vcc;
 974
 975                         skb = get_skb_rx_pointer(reg_desc.dataptr);
 976
 977                         if ( reg_desc.err ) {
 978                                 if ( vcc->qos.aal == ATM_AAL5 ) {
 979                                         trailer = (struct rx_inband_trailer *)((unsigned int)skb->data + ((reg_desc.byteoff + reg_desc.datalen + MAX_RX_PACKET_PADDING_BYTES) & ~MAX_RX_PACKET_PADDING_BYTES));
 980                                         if ( trailer->stw_crc )
 981                                                 g_atm_priv_data.conn[conn].aal5_vcc_crc_err++;
 982                                         if ( trailer->stw_ovz )
 983                                                 g_atm_priv_data.conn[conn].aal5_vcc_oversize_sdu++;
 984                                         g_atm_priv_data.wrx_drop_pdu++;
 985                                 }
 986                                 if ( vcc->stats ) {
 987                                         atomic_inc(&vcc->stats->rx_drop);
 988                                         atomic_inc(&vcc->stats->rx_err);
 989                                 }
 990                                 reg_desc.err = 0;
 991                         } else if ( atm_charge(vcc, skb->truesize) ) {
 992                                 new_skb = alloc_skb_rx();
 993                                 if ( new_skb != NULL ) {
 994 #if defined(ENABLE_LESS_CACHE_INV) && ENABLE_LESS_CACHE_INV
 995                                         if ( reg_desc.byteoff + reg_desc.datalen > LESS_CACHE_INV_LEN )
 996                                                 dma_cache_inv((unsigned long)skb->data + LESS_CACHE_INV_LEN, reg_desc.byteoff + reg_desc.datalen - LESS_CACHE_INV_LEN);
 997 #endif
 998
 999                                         skb_reserve(skb, reg_desc.byteoff);
1000                                         skb_put(skb, reg_desc.datalen);
1001                                         ATM_SKB(skb)->vcc = vcc;
1002
1003                                         vcc->push(vcc, skb);
1004
1005                                         if ( vcc->qos.aal == ATM_AAL5 )
1006                                                 g_atm_priv_data.wrx_pdu++;
1007                                         if ( vcc->stats )
1008                                                 atomic_inc(&vcc->stats->rx);
1009                                         adsl_led_flash();
1010
1011                                         reg_desc.dataptr = (unsigned int)new_skb->data >> 2;
1012                                 } else {
1013                                         atm_return(vcc, skb->truesize);
1014                                         if ( vcc->qos.aal == ATM_AAL5 )
1015                                                 g_atm_priv_data.wrx_drop_pdu++;
1016                                         if ( vcc->stats )
1017                                                 atomic_inc(&vcc->stats->rx_drop);
1018                                 }
1019                         } else {
1020                                 if ( vcc->qos.aal == ATM_AAL5 )
1021                                         g_atm_priv_data.wrx_drop_pdu++;
1022                                 if ( vcc->stats )
1023                                         atomic_inc(&vcc->stats->rx_drop);
1024                         }
1025                 } else {
1026                         g_atm_priv_data.wrx_drop_pdu++;
1027                 }
1028
1029                 reg_desc.byteoff = 0;
1030                 reg_desc.datalen = RX_DMA_CH_AAL_BUF_SIZE;
1031                 reg_desc.own = 1;
1032                 reg_desc.c   = 0;
1033
1034                 g_atm_priv_data.aal_desc[g_atm_priv_data.aal_desc_pos] = reg_desc;
1035                 if ( ++g_atm_priv_data.aal_desc_pos == dma_rx_descriptor_length )
1036                         g_atm_priv_data.aal_desc_pos = 0;
1037
1038                 mailbox_signal(RX_DMA_CH_AAL, 0);
1039         }
1040 }
1041
1042 static irqreturn_t mailbox_irq_handler(int irq, void *dev_id)
1043 {
1044         if ( !*MBOX_IGU1_ISR )
1045                 return IRQ_HANDLED;
1046
1047         *MBOX_IGU1_ISRC = *MBOX_IGU1_ISR;
1048         mailbox_oam_rx_handler();
1049         mailbox_aal_rx_handler();
1050
1051         return IRQ_HANDLED;
1052 }
1053
1054 static inline void mailbox_signal(unsigned int queue, int is_tx)
1055 {
1056         int count = 1000;
1057
1058         if ( is_tx ) {
1059                 while ( MBOX_IGU3_ISR_ISR(queue + FIRST_QSB_QID + 16) && count > 0 )
1060                         count--;
1061                 *MBOX_IGU3_ISRS = MBOX_IGU3_ISRS_SET(queue + FIRST_QSB_QID + 16);
1062         } else {
1063                 while ( MBOX_IGU3_ISR_ISR(queue) && count > 0 )
1064                         count--;
1065                 *MBOX_IGU3_ISRS = MBOX_IGU3_ISRS_SET(queue);
1066         }
1067
1068         ASSERT(count > 0, "queue = %u, is_tx = %d, MBOX_IGU3_ISR = 0x%08x", queue, is_tx, IFX_REG_R32(MBOX_IGU3_ISR));
1069 }
1070
1071 static void set_qsb(struct atm_vcc *vcc, struct atm_qos *qos, unsigned int queue)
1072 {
1073         struct clk *fpi_clk = clk_get_fpi();
1074         unsigned int qsb_clk = clk_get_rate(fpi_clk);
1075         unsigned int qsb_qid = queue + FIRST_QSB_QID;
1076         union qsb_queue_parameter_table qsb_queue_parameter_table = {{0}};
1077         union qsb_queue_vbr_parameter_table qsb_queue_vbr_parameter_table = {{0}};
1078         unsigned int tmp;
1079
1080
1081         /*
1082          *  Peak Cell Rate (PCR) Limiter
1083          */
1084         if ( qos->txtp.max_pcr == 0 )
1085                 qsb_queue_parameter_table.bit.tp = 0;   /*  disable PCR limiter */
1086         else {
1087                 /*  peak cell rate would be slightly lower than requested [maximum_rate / pcr = (qsb_clock / 8) * (time_step / 4) / pcr] */
1088                 tmp = ((qsb_clk * qsb_tstep) >> 5) / qos->txtp.max_pcr + 1;
1089                 /*  check if overflow takes place   */
1090                 qsb_queue_parameter_table.bit.tp = tmp > QSB_TP_TS_MAX ? QSB_TP_TS_MAX : tmp;
1091         }
1092
1093 #if !defined(DISABLE_QOS_WORKAROUND) || !DISABLE_QOS_WORKAROUND
1094         //  A funny issue. Create two PVCs, one UBR and one UBR with max_pcr.
1095         //  Send packets to these two PVCs at same time, it trigger strange behavior.
1096         //  In A1, RAM from 0x80000000 to 0x0x8007FFFF was corrupted with fixed pattern 0x00000000 0x40000000.
1097         //  In A4, PPE firmware keep emiting unknown cell and do not respond to driver.
1098         //  To work around, create UBR always with max_pcr.
1099         //  If user want to create UBR without max_pcr, we give a default one larger than line-rate.
1100         if ( qos->txtp.traffic_class == ATM_UBR && qsb_queue_parameter_table.bit.tp == 0 ) {
1101                 int port = g_atm_priv_data.conn[queue].port;
1102                 unsigned int max_pcr = g_atm_priv_data.port[port].tx_max_cell_rate + 1000;
1103
1104                 tmp = ((qsb_clk * qsb_tstep) >> 5) / max_pcr + 1;
1105                 if ( tmp > QSB_TP_TS_MAX )
1106                         tmp = QSB_TP_TS_MAX;
1107                 else if ( tmp < 1 )
1108                         tmp = 1;
1109                 qsb_queue_parameter_table.bit.tp = tmp;
1110         }
1111 #endif
1112
1113         /*
1114          *  Weighted Fair Queueing Factor (WFQF)
1115          */
1116         switch ( qos->txtp.traffic_class ) {
1117         case ATM_CBR:
1118         case ATM_VBR_RT:
1119                 /*  real time queue gets weighted fair queueing bypass  */
1120                 qsb_queue_parameter_table.bit.wfqf = 0;
1121                 break;
1122         case ATM_VBR_NRT:
1123         case ATM_UBR_PLUS:
1124                 /*  WFQF calculation here is based on virtual cell rates, to reduce granularity for high rates  */
1125                 /*  WFQF is maximum cell rate / garenteed cell rate                                             */
1126                 /*  wfqf = qsb_minimum_cell_rate * QSB_WFQ_NONUBR_MAX / requested_minimum_peak_cell_rate        */
1127                 if ( qos->txtp.min_pcr == 0 )
1128                         qsb_queue_parameter_table.bit.wfqf = QSB_WFQ_NONUBR_MAX;
1129                 else {
1130                         tmp = QSB_GCR_MIN * QSB_WFQ_NONUBR_MAX / qos->txtp.min_pcr;
1131                         if ( tmp == 0 )
1132                                 qsb_queue_parameter_table.bit.wfqf = 1;
1133                         else if ( tmp > QSB_WFQ_NONUBR_MAX )
1134                                 qsb_queue_parameter_table.bit.wfqf = QSB_WFQ_NONUBR_MAX;
1135                         else
1136                                 qsb_queue_parameter_table.bit.wfqf = tmp;
1137                 }
1138                 break;
1139         default:
1140         case ATM_UBR:
1141                 qsb_queue_parameter_table.bit.wfqf = QSB_WFQ_UBR_BYPASS;
1142         }
1143
1144         /*
1145          *  Sustained Cell Rate (SCR) Leaky Bucket Shaper VBR.0/VBR.1
1146          */
1147         if ( qos->txtp.traffic_class == ATM_VBR_RT || qos->txtp.traffic_class == ATM_VBR_NRT ) {
1148                 if ( qos->txtp.scr == 0 ) {
1149                         /*  disable shaper  */
1150                         qsb_queue_vbr_parameter_table.bit.taus = 0;
1151                         qsb_queue_vbr_parameter_table.bit.ts = 0;
1152                 } else {
1153                         /*  Cell Loss Priority  (CLP)   */
1154                         if ( (vcc->atm_options & ATM_ATMOPT_CLP) )
1155                                 /*  CLP1    */
1156                                 qsb_queue_parameter_table.bit.vbr = 1;
1157                         else
1158                                 /*  CLP0    */
1159                                 qsb_queue_parameter_table.bit.vbr = 0;
1160                         /*  Rate Shaper Parameter (TS) and Burst Tolerance Parameter for SCR (tauS) */
1161                         tmp = ((qsb_clk * qsb_tstep) >> 5) / qos->txtp.scr + 1;
1162                         qsb_queue_vbr_parameter_table.bit.ts = tmp > QSB_TP_TS_MAX ? QSB_TP_TS_MAX : tmp;
1163                         tmp = (qos->txtp.mbs - 1) * (qsb_queue_vbr_parameter_table.bit.ts - qsb_queue_parameter_table.bit.tp) / 64;
1164                         if ( tmp == 0 )
1165                                 qsb_queue_vbr_parameter_table.bit.taus = 1;
1166                         else if ( tmp > QSB_TAUS_MAX )
1167                                 qsb_queue_vbr_parameter_table.bit.taus = QSB_TAUS_MAX;
1168                         else
1169                                 qsb_queue_vbr_parameter_table.bit.taus = tmp;
1170                 }
1171         } else {
1172                 qsb_queue_vbr_parameter_table.bit.taus = 0;
1173                 qsb_queue_vbr_parameter_table.bit.ts = 0;
1174         }
1175
1176         /*  Queue Parameter Table (QPT) */
1177         *QSB_RTM   = QSB_RTM_DM_SET(QSB_QPT_SET_MASK);
1178         *QSB_RTD   = QSB_RTD_TTV_SET(qsb_queue_parameter_table.dword);
1179         *QSB_RAMAC = QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE) | QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_QPT) | QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW) | QSB_RAMAC_TESEL_SET(qsb_qid);
1180         /*  Queue VBR Paramter Table (QVPT) */
1181         *QSB_RTM   = QSB_RTM_DM_SET(QSB_QVPT_SET_MASK);
1182         *QSB_RTD   = QSB_RTD_TTV_SET(qsb_queue_vbr_parameter_table.dword);
1183         *QSB_RAMAC = QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE) | QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_VBR) | QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW) | QSB_RAMAC_TESEL_SET(qsb_qid);
1184
1185 }
1186
1187 static void qsb_global_set(void)
1188 {
1189         struct clk *fpi_clk = clk_get_fpi();
1190         unsigned int qsb_clk = clk_get_rate(fpi_clk);
1191         int i;
1192         unsigned int tmp1, tmp2, tmp3;
1193
1194         *QSB_ICDV = QSB_ICDV_TAU_SET(qsb_tau);
1195         *QSB_SBL  = QSB_SBL_SBL_SET(qsb_srvm);
1196         *QSB_CFG  = QSB_CFG_TSTEPC_SET(qsb_tstep >> 1);
1197
1198         /*
1199          *  set SCT and SPT per port
1200          */
1201         for ( i = 0; i < ATM_PORT_NUMBER; i++ ) {
1202                 if ( g_atm_priv_data.port[i].tx_max_cell_rate != 0 ) {
1203                         tmp1 = ((qsb_clk * qsb_tstep) >> 1) / g_atm_priv_data.port[i].tx_max_cell_rate;
1204                         tmp2 = tmp1 >> 6;                   /*  integer value of Tsb    */
1205                         tmp3 = (tmp1 & ((1 << 6) - 1)) + 1; /*  fractional part of Tsb  */
1206                         /*  carry over to integer part (?)  */
1207                         if ( tmp3 == (1 << 6) ) {
1208                                 tmp3 = 0;
1209                                 tmp2++;
1210                         }
1211                         if ( tmp2 == 0 )
1212                                 tmp2 = tmp3 = 1;
1213                         /*  1. set mask                                 */
1214                         /*  2. write value to data transfer register    */
1215                         /*  3. start the tranfer                        */
1216                         /*  SCT (FracRate)  */
1217                         *QSB_RTM   = QSB_RTM_DM_SET(QSB_SET_SCT_MASK);
1218                         *QSB_RTD   = QSB_RTD_TTV_SET(tmp3);
1219                         *QSB_RAMAC = QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE) |
1220                                         QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_SCT) |
1221                                         QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW) |
1222                                         QSB_RAMAC_TESEL_SET(i & 0x01);
1223                         /*  SPT (SBV + PN + IntRage)    */
1224                         *QSB_RTM   = QSB_RTM_DM_SET(QSB_SET_SPT_MASK);
1225                         *QSB_RTD   = QSB_RTD_TTV_SET(QSB_SPT_SBV_VALID | QSB_SPT_PN_SET(i & 0x01) | QSB_SPT_INTRATE_SET(tmp2));
1226                         *QSB_RAMAC = QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE) |
1227                                 QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_SPT) |
1228                                 QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW) |
1229                                 QSB_RAMAC_TESEL_SET(i & 0x01);
1230                 }
1231         }
1232 }
1233
1234 static inline void set_htu_entry(unsigned int vpi, unsigned int vci, unsigned int queue, int aal5, int is_retx)
1235 {
1236         struct htu_entry htu_entry = {
1237                 res1:       0x00,
1238                 clp:        is_retx ? 0x01 : 0x00,
1239                 pid:        g_atm_priv_data.conn[queue].port & 0x01,
1240                 vpi:        vpi,
1241                 vci:        vci,
1242                 pti:        0x00,
1243                 vld:        0x01};
1244
1245         struct htu_mask htu_mask = {
1246                 set:        0x01,
1247                 clp:        0x01,
1248                 pid_mask:   0x02,
1249                 vpi_mask:   0x00,
1250                 vci_mask:   0x0000,
1251                 pti_mask:   0x03,   //  0xx, user data
1252                 clear:      0x00};
1253
1254         struct htu_result htu_result = {
1255                 res1:       0x00,
1256                 cellid:     queue,
1257                 res2:       0x00,
1258                 type:       aal5 ? 0x00 : 0x01,
1259                 ven:        0x01,
1260                 res3:       0x00,
1261                 qid:        queue};
1262
1263         *HTU_RESULT(queue + OAM_HTU_ENTRY_NUMBER) = htu_result;
1264         *HTU_MASK(queue + OAM_HTU_ENTRY_NUMBER)   = htu_mask;
1265         *HTU_ENTRY(queue + OAM_HTU_ENTRY_NUMBER)  = htu_entry;
1266 }
1267
1268 static inline void clear_htu_entry(unsigned int queue)
1269 {
1270         HTU_ENTRY(queue + OAM_HTU_ENTRY_NUMBER)->vld = 0;
1271 }
1272
1273 static void validate_oam_htu_entry(void)
1274 {
1275         HTU_ENTRY(OAM_F4_SEG_HTU_ENTRY)->vld = 1;
1276         HTU_ENTRY(OAM_F4_TOT_HTU_ENTRY)->vld = 1;
1277         HTU_ENTRY(OAM_F5_HTU_ENTRY)->vld = 1;
1278 }
1279
1280 static void invalidate_oam_htu_entry(void)
1281 {
1282         HTU_ENTRY(OAM_F4_SEG_HTU_ENTRY)->vld = 0;
1283         HTU_ENTRY(OAM_F4_TOT_HTU_ENTRY)->vld = 0;
1284         HTU_ENTRY(OAM_F5_HTU_ENTRY)->vld = 0;
1285 }
1286
1287 static inline int find_vpi(unsigned int vpi)
1288 {
1289         int i;
1290         unsigned int bit;
1291
1292         for ( i = 0, bit = 1; i < MAX_PVC_NUMBER; i++, bit <<= 1 ) {
1293                 if ( (g_atm_priv_data.conn_table & bit) != 0
1294                                 && g_atm_priv_data.conn[i].vcc != NULL
1295                                 && vpi == g_atm_priv_data.conn[i].vcc->vpi )
1296                         return i;
1297         }
1298
1299         return -1;
1300 }
1301
1302 static inline int find_vpivci(unsigned int vpi, unsigned int vci)
1303 {
1304         int i;
1305         unsigned int bit;
1306
1307         for ( i = 0, bit = 1; i < MAX_PVC_NUMBER; i++, bit <<= 1 ) {
1308                 if ( (g_atm_priv_data.conn_table & bit) != 0
1309                                 && g_atm_priv_data.conn[i].vcc != NULL
1310                                 && vpi == g_atm_priv_data.conn[i].vcc->vpi
1311                                 && vci == g_atm_priv_data.conn[i].vcc->vci )
1312                         return i;
1313         }
1314
1315         return -1;
1316 }
1317
1318 static inline int find_vcc(struct atm_vcc *vcc)
1319 {
1320         int i;
1321         unsigned int bit;
1322
1323         for ( i = 0, bit = 1; i < MAX_PVC_NUMBER; i++, bit <<= 1 ) {
1324                 if ( (g_atm_priv_data.conn_table & bit) != 0
1325                         && g_atm_priv_data.conn[i].vcc == vcc )
1326                 return i;
1327         }
1328
1329         return -1;
1330 }
1331
1332 static inline int ifx_atm_version(const struct ltq_atm_ops *ops, char *buf)
1333 {
1334         int len = 0;
1335         unsigned int major, minor;
1336
1337         ops->fw_ver(&major, &minor);
1338
1339         len += sprintf(buf + len, "ATM%d.%d.%d", IFX_ATM_VER_MAJOR, IFX_ATM_VER_MID, IFX_ATM_VER_MINOR);
1340         len += sprintf(buf + len, "    ATM (A1) firmware version %d.%d\n", major, minor);
1341
1342         return len;
1343 }
1344
1345 static inline void check_parameters(void)
1346 {
1347         /*  Please refer to Amazon spec 15.4 for setting these values.  */
1348         if ( qsb_tau < 1 )
1349                 qsb_tau = 1;
1350         if ( qsb_tstep < 1 )
1351                 qsb_tstep = 1;
1352         else if ( qsb_tstep > 4 )
1353                 qsb_tstep = 4;
1354         else if ( qsb_tstep == 3 )
1355                 qsb_tstep = 2;
1356
1357         /*  There is a delay between PPE write descriptor and descriptor is       */
1358         /*  really stored in memory. Host also has this delay when writing        */
1359         /*  descriptor. So PPE will use this value to determine if the write      */
1360         /*  operation makes effect.                                               */
1361         if ( write_descriptor_delay < 0 )
1362                 write_descriptor_delay = 0;
1363
1364         if ( aal5_fill_pattern < 0 )
1365                 aal5_fill_pattern = 0;
1366         else
1367                 aal5_fill_pattern &= 0xFF;
1368
1369         /*  Because of the limitation of length field in descriptors, the packet  */
1370         /*  size could not be larger than 64K minus overhead size.                */
1371         if ( aal5r_max_packet_size < 0 )
1372                 aal5r_max_packet_size = 0;
1373         else if ( aal5r_max_packet_size >= 65535 - MAX_RX_FRAME_EXTRA_BYTES )
1374                 aal5r_max_packet_size = 65535 - MAX_RX_FRAME_EXTRA_BYTES;
1375         if ( aal5r_min_packet_size < 0 )
1376                 aal5r_min_packet_size = 0;
1377         else if ( aal5r_min_packet_size > aal5r_max_packet_size )
1378                 aal5r_min_packet_size = aal5r_max_packet_size;
1379         if ( aal5s_max_packet_size < 0 )
1380                 aal5s_max_packet_size = 0;
1381         else if ( aal5s_max_packet_size >= 65535 - MAX_TX_FRAME_EXTRA_BYTES )
1382                 aal5s_max_packet_size = 65535 - MAX_TX_FRAME_EXTRA_BYTES;
1383         if ( aal5s_min_packet_size < 0 )
1384                 aal5s_min_packet_size = 0;
1385         else if ( aal5s_min_packet_size > aal5s_max_packet_size )
1386                 aal5s_min_packet_size = aal5s_max_packet_size;
1387
1388         if ( dma_rx_descriptor_length < 2 )
1389                 dma_rx_descriptor_length = 2;
1390         if ( dma_tx_descriptor_length < 2 )
1391                 dma_tx_descriptor_length = 2;
1392         if ( dma_rx_clp1_descriptor_threshold < 0 )
1393                 dma_rx_clp1_descriptor_threshold = 0;
1394         else if ( dma_rx_clp1_descriptor_threshold > dma_rx_descriptor_length )
1395                 dma_rx_clp1_descriptor_threshold = dma_rx_descriptor_length;
1396
1397         if ( dma_tx_descriptor_length < 2 )
1398                 dma_tx_descriptor_length = 2;
1399 }
1400
1401 static inline int init_priv_data(void)
1402 {
1403         void *p;
1404         int i;
1405         struct rx_descriptor rx_desc = {0};
1406         struct sk_buff *skb;
1407         volatile struct tx_descriptor *p_tx_desc;
1408         struct sk_buff **ppskb;
1409
1410         //  clear atm private data structure
1411         memset(&g_atm_priv_data, 0, sizeof(g_atm_priv_data));
1412
1413         //  allocate memory for RX (AAL) descriptors
1414         p = kzalloc(dma_rx_descriptor_length * sizeof(struct rx_descriptor) + DESC_ALIGNMENT, GFP_KERNEL);
1415         if ( p == NULL )
1416                 return -1;
1417         dma_cache_wback_inv((unsigned long)p, dma_rx_descriptor_length * sizeof(struct rx_descriptor) + DESC_ALIGNMENT);
1418         g_atm_priv_data.aal_desc_base = p;
1419         p = (void *)((((unsigned int)p + DESC_ALIGNMENT - 1) & ~(DESC_ALIGNMENT - 1)) | KSEG1);
1420         g_atm_priv_data.aal_desc = (volatile struct rx_descriptor *)p;
1421
1422         //  allocate memory for RX (OAM) descriptors
1423         p = kzalloc(RX_DMA_CH_OAM_DESC_LEN * sizeof(struct rx_descriptor) + DESC_ALIGNMENT, GFP_KERNEL);
1424         if ( p == NULL )
1425                 return -1;
1426         dma_cache_wback_inv((unsigned long)p, RX_DMA_CH_OAM_DESC_LEN * sizeof(struct rx_descriptor) + DESC_ALIGNMENT);
1427         g_atm_priv_data.oam_desc_base = p;
1428         p = (void *)((((unsigned int)p + DESC_ALIGNMENT - 1) & ~(DESC_ALIGNMENT - 1)) | KSEG1);
1429         g_atm_priv_data.oam_desc = (volatile struct rx_descriptor *)p;
1430
1431         //  allocate memory for RX (OAM) buffer
1432         p = kzalloc(RX_DMA_CH_OAM_DESC_LEN * RX_DMA_CH_OAM_BUF_SIZE + DATA_BUFFER_ALIGNMENT, GFP_KERNEL);
1433         if ( p == NULL )
1434                 return -1;
1435         dma_cache_wback_inv((unsigned long)p, RX_DMA_CH_OAM_DESC_LEN * RX_DMA_CH_OAM_BUF_SIZE + DATA_BUFFER_ALIGNMENT);
1436         g_atm_priv_data.oam_buf_base = p;
1437         p = (void *)(((unsigned int)p + DATA_BUFFER_ALIGNMENT - 1) & ~(DATA_BUFFER_ALIGNMENT - 1));
1438         g_atm_priv_data.oam_buf = p;
1439
1440         //  allocate memory for TX descriptors
1441         p = kzalloc(MAX_PVC_NUMBER * dma_tx_descriptor_length * sizeof(struct tx_descriptor) + DESC_ALIGNMENT, GFP_KERNEL);
1442         if ( p == NULL )
1443                 return -1;
1444         dma_cache_wback_inv((unsigned long)p, MAX_PVC_NUMBER * dma_tx_descriptor_length * sizeof(struct tx_descriptor) + DESC_ALIGNMENT);
1445         g_atm_priv_data.tx_desc_base = p;
1446
1447         //  allocate memory for TX skb pointers
1448         p = kzalloc(MAX_PVC_NUMBER * dma_tx_descriptor_length * sizeof(struct sk_buff *) + 4, GFP_KERNEL);
1449         if ( p == NULL )
1450                 return -1;
1451         dma_cache_wback_inv((unsigned long)p, MAX_PVC_NUMBER * dma_tx_descriptor_length * sizeof(struct sk_buff *) + 4);
1452         g_atm_priv_data.tx_skb_base = p;
1453
1454         //  setup RX (AAL) descriptors
1455         rx_desc.own     = 1;
1456         rx_desc.c       = 0;
1457         rx_desc.sop     = 1;
1458         rx_desc.eop     = 1;
1459         rx_desc.byteoff = 0;
1460         rx_desc.id      = 0;
1461         rx_desc.err     = 0;
1462         rx_desc.datalen = RX_DMA_CH_AAL_BUF_SIZE;
1463         for ( i = 0; i < dma_rx_descriptor_length; i++ ) {
1464                 skb = alloc_skb_rx();
1465                 if ( skb == NULL )
1466                         return -1;
1467                 rx_desc.dataptr = ((unsigned int)skb->data >> 2) & 0x0FFFFFFF;
1468                 g_atm_priv_data.aal_desc[i] = rx_desc;
1469         }
1470
1471         //  setup RX (OAM) descriptors
1472         p = (void *)((unsigned int)g_atm_priv_data.oam_buf | KSEG1);
1473         rx_desc.own     = 1;
1474         rx_desc.c       = 0;
1475         rx_desc.sop     = 1;
1476         rx_desc.eop     = 1;
1477         rx_desc.byteoff = 0;
1478         rx_desc.id      = 0;
1479         rx_desc.err     = 0;
1480         rx_desc.datalen = RX_DMA_CH_OAM_BUF_SIZE;
1481         for ( i = 0; i < RX_DMA_CH_OAM_DESC_LEN; i++ ) {
1482                 rx_desc.dataptr = ((unsigned int)p >> 2) & 0x0FFFFFFF;
1483                 g_atm_priv_data.oam_desc[i] = rx_desc;
1484                 p = (void *)((unsigned int)p + RX_DMA_CH_OAM_BUF_SIZE);
1485         }
1486
1487         //  setup TX descriptors and skb pointers
1488         p_tx_desc = (volatile struct tx_descriptor *)((((unsigned int)g_atm_priv_data.tx_desc_base + DESC_ALIGNMENT - 1) & ~(DESC_ALIGNMENT - 1)) | KSEG1);
1489         ppskb = (struct sk_buff **)(((unsigned int)g_atm_priv_data.tx_skb_base + 3) & ~3);
1490         for ( i = 0; i < MAX_PVC_NUMBER; i++ ) {
1491                 g_atm_priv_data.conn[i].tx_desc = &p_tx_desc[i * dma_tx_descriptor_length];
1492                 g_atm_priv_data.conn[i].tx_skb  = &ppskb[i * dma_tx_descriptor_length];
1493         }
1494
1495         for ( i = 0; i < ATM_PORT_NUMBER; i++ )
1496                 g_atm_priv_data.port[i].tx_max_cell_rate = DEFAULT_TX_LINK_RATE;
1497
1498         return 0;
1499 }
1500
1501 static inline void clear_priv_data(void)
1502 {
1503         int i, j;
1504         struct sk_buff *skb;
1505
1506         for ( i = 0; i < MAX_PVC_NUMBER; i++ ) {
1507                 if ( g_atm_priv_data.conn[i].tx_skb != NULL ) {
1508                         for ( j = 0; j < dma_tx_descriptor_length; j++ )
1509                                 if ( g_atm_priv_data.conn[i].tx_skb[j] != NULL )
1510                                         dev_kfree_skb_any(g_atm_priv_data.conn[i].tx_skb[j]);
1511                 }
1512         }
1513
1514         if ( g_atm_priv_data.tx_skb_base != NULL )
1515                 kfree(g_atm_priv_data.tx_skb_base);
1516
1517         if ( g_atm_priv_data.tx_desc_base != NULL )
1518                 kfree(g_atm_priv_data.tx_desc_base);
1519
1520         if ( g_atm_priv_data.oam_buf_base != NULL )
1521                 kfree(g_atm_priv_data.oam_buf_base);
1522
1523         if ( g_atm_priv_data.oam_desc_base != NULL )
1524                 kfree(g_atm_priv_data.oam_desc_base);
1525
1526         if ( g_atm_priv_data.aal_desc_base != NULL ) {
1527                 for ( i = 0; i < dma_rx_descriptor_length; i++ ) {
1528                         if ( g_atm_priv_data.aal_desc[i].sop || g_atm_priv_data.aal_desc[i].eop ) { //  descriptor initialized
1529                                 skb = get_skb_rx_pointer(g_atm_priv_data.aal_desc[i].dataptr);
1530                                 dev_kfree_skb_any(skb);
1531                         }
1532                 }
1533                 kfree(g_atm_priv_data.aal_desc_base);
1534         }
1535 }
1536
1537 static inline void init_rx_tables(void)
1538 {
1539         int i;
1540         struct wrx_queue_config wrx_queue_config = {0};
1541         struct wrx_dma_channel_config wrx_dma_channel_config = {0};
1542         struct htu_entry htu_entry = {0};
1543         struct htu_result htu_result = {0};
1544         struct htu_mask htu_mask = {
1545                 set:        0x01,
1546                 clp:        0x01,
1547                 pid_mask:   0x00,
1548                 vpi_mask:   0x00,
1549                 vci_mask:   0x00,
1550                 pti_mask:   0x00,
1551                 clear:      0x00
1552         };
1553
1554         /*
1555          *  General Registers
1556          */
1557         *CFG_WRX_HTUTS  = MAX_PVC_NUMBER + OAM_HTU_ENTRY_NUMBER;
1558 #ifndef CONFIG_AMAZON_SE
1559         *CFG_WRX_QNUM   = MAX_QUEUE_NUMBER;
1560 #endif
1561         *CFG_WRX_DCHNUM = RX_DMA_CH_TOTAL;
1562         *WRX_DMACH_ON   = (1 << RX_DMA_CH_TOTAL) - 1;
1563         *WRX_HUNT_BITTH = DEFAULT_RX_HUNT_BITTH;
1564
1565         /*
1566          *  WRX Queue Configuration Table
1567          */
1568         wrx_queue_config.uumask    = 0xFF;
1569         wrx_queue_config.cpimask   = 0xFF;
1570         wrx_queue_config.uuexp     = 0;
1571         wrx_queue_config.cpiexp    = 0;
1572         wrx_queue_config.mfs       = aal5r_max_packet_size;
1573         wrx_queue_config.oversize  = aal5r_max_packet_size;
1574         wrx_queue_config.undersize = aal5r_min_packet_size;
1575         wrx_queue_config.errdp     = aal5r_drop_error_packet;
1576         wrx_queue_config.dmach     = RX_DMA_CH_AAL;
1577         for ( i = 0; i < MAX_QUEUE_NUMBER; i++ )
1578                 *WRX_QUEUE_CONFIG(i) = wrx_queue_config;
1579         WRX_QUEUE_CONFIG(OAM_RX_QUEUE)->dmach = RX_DMA_CH_OAM;
1580
1581         /*
1582          *  WRX DMA Channel Configuration Table
1583          */
1584         wrx_dma_channel_config.chrl   = 0;
1585         wrx_dma_channel_config.clp1th = dma_rx_clp1_descriptor_threshold;
1586         wrx_dma_channel_config.mode   = 0;
1587         wrx_dma_channel_config.rlcfg  = 0;
1588
1589         wrx_dma_channel_config.deslen = RX_DMA_CH_OAM_DESC_LEN;
1590         wrx_dma_channel_config.desba  = ((unsigned int)g_atm_priv_data.oam_desc >> 2) & 0x0FFFFFFF;
1591         *WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_OAM) = wrx_dma_channel_config;
1592
1593         wrx_dma_channel_config.deslen = dma_rx_descriptor_length;
1594         wrx_dma_channel_config.desba  = ((unsigned int)g_atm_priv_data.aal_desc >> 2) & 0x0FFFFFFF;
1595         *WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_AAL) = wrx_dma_channel_config;
1596
1597         /*
1598          *  HTU Tables
1599          */
1600         for (i = 0; i < MAX_PVC_NUMBER; i++) {
1601                 htu_result.qid = (unsigned int)i;
1602
1603                 *HTU_ENTRY(i + OAM_HTU_ENTRY_NUMBER)  = htu_entry;
1604                 *HTU_MASK(i + OAM_HTU_ENTRY_NUMBER)   = htu_mask;
1605                 *HTU_RESULT(i + OAM_HTU_ENTRY_NUMBER) = htu_result;
1606         }
1607
1608         /*  OAM HTU Entry   */
1609         htu_entry.vci = 0x03;
1610         htu_mask.pid_mask = 0x03;
1611         htu_mask.vpi_mask = 0xFF;
1612         htu_mask.vci_mask = 0x0000;
1613         htu_mask.pti_mask = 0x07;
1614         htu_result.cellid = OAM_RX_QUEUE;
1615         htu_result.type   = 1;
1616         htu_result.ven    = 1;
1617         htu_result.qid    = OAM_RX_QUEUE;
1618         *HTU_RESULT(OAM_F4_SEG_HTU_ENTRY) = htu_result;
1619         *HTU_MASK(OAM_F4_SEG_HTU_ENTRY)   = htu_mask;
1620         *HTU_ENTRY(OAM_F4_SEG_HTU_ENTRY)  = htu_entry;
1621         htu_entry.vci     = 0x04;
1622         htu_result.cellid = OAM_RX_QUEUE;
1623         htu_result.type   = 1;
1624         htu_result.ven    = 1;
1625         htu_result.qid    = OAM_RX_QUEUE;
1626         *HTU_RESULT(OAM_F4_TOT_HTU_ENTRY) = htu_result;
1627         *HTU_MASK(OAM_F4_TOT_HTU_ENTRY)   = htu_mask;
1628         *HTU_ENTRY(OAM_F4_TOT_HTU_ENTRY)  = htu_entry;
1629         htu_entry.vci     = 0x00;
1630         htu_entry.pti     = 0x04;
1631         htu_mask.vci_mask = 0xFFFF;
1632         htu_mask.pti_mask = 0x01;
1633         htu_result.cellid = OAM_RX_QUEUE;
1634         htu_result.type   = 1;
1635         htu_result.ven    = 1;
1636         htu_result.qid    = OAM_RX_QUEUE;
1637         *HTU_RESULT(OAM_F5_HTU_ENTRY) = htu_result;
1638         *HTU_MASK(OAM_F5_HTU_ENTRY)   = htu_mask;
1639         *HTU_ENTRY(OAM_F5_HTU_ENTRY)  = htu_entry;
1640 }
1641
1642 static inline void init_tx_tables(void)
1643 {
1644         int i;
1645         struct wtx_queue_config wtx_queue_config = {0};
1646         struct wtx_dma_channel_config wtx_dma_channel_config = {0};
1647         struct wtx_port_config wtx_port_config = {
1648                 res1:   0,
1649                 qid:    0,
1650                 qsben:  1
1651         };
1652
1653         /*
1654          *  General Registers
1655          */
1656         *CFG_WTX_DCHNUM     = MAX_TX_DMA_CHANNEL_NUMBER;
1657         *WTX_DMACH_ON       = ((1 << MAX_TX_DMA_CHANNEL_NUMBER) - 1) ^ ((1 << FIRST_QSB_QID) - 1);
1658         *CFG_WRDES_DELAY    = write_descriptor_delay;
1659
1660         /*
1661          *  WTX Port Configuration Table
1662          */
1663         for ( i = 0; i < ATM_PORT_NUMBER; i++ )
1664                 *WTX_PORT_CONFIG(i) = wtx_port_config;
1665
1666         /*
1667          *  WTX Queue Configuration Table
1668          */
1669         wtx_queue_config.qsben = 1;
1670         wtx_queue_config.sbid  = 0;
1671         for ( i = 0; i < MAX_TX_DMA_CHANNEL_NUMBER; i++ ) {
1672                 wtx_queue_config.qsb_vcid = i;
1673                 *WTX_QUEUE_CONFIG(i) = wtx_queue_config;
1674         }
1675
1676         /*
1677          *  WTX DMA Channel Configuration Table
1678          */
1679         wtx_dma_channel_config.mode   = 0;
1680         wtx_dma_channel_config.deslen = 0;
1681         wtx_dma_channel_config.desba  = 0;
1682         for ( i = 0; i < FIRST_QSB_QID; i++ )
1683                 *WTX_DMA_CHANNEL_CONFIG(i) = wtx_dma_channel_config;
1684         /*  normal connection   */
1685         wtx_dma_channel_config.deslen = dma_tx_descriptor_length;
1686         for ( ; i < MAX_TX_DMA_CHANNEL_NUMBER ; i++ ) {
1687                 wtx_dma_channel_config.desba = ((unsigned int)g_atm_priv_data.conn[i - FIRST_QSB_QID].tx_desc >> 2) & 0x0FFFFFFF;
1688                 *WTX_DMA_CHANNEL_CONFIG(i) = wtx_dma_channel_config;
1689         }
1690 }
1691
1692 static int atm_showtime_enter(struct port_cell_info *port_cell, void *xdata_addr)
1693 {
1694         int i, j;
1695
1696         ASSERT(port_cell != NULL, "port_cell is NULL");
1697         ASSERT(xdata_addr != NULL, "xdata_addr is NULL");
1698
1699         for ( j = 0; j < ATM_PORT_NUMBER && j < port_cell->port_num; j++ )
1700                 if ( port_cell->tx_link_rate[j] > 0 )
1701                         break;
1702         for ( i = 0; i < ATM_PORT_NUMBER && i < port_cell->port_num; i++ )
1703                 g_atm_priv_data.port[i].tx_max_cell_rate =
1704                         port_cell->tx_link_rate[i] > 0 ? port_cell->tx_link_rate[i] : port_cell->tx_link_rate[j];
1705
1706         qsb_global_set();
1707
1708         for ( i = 0; i < MAX_PVC_NUMBER; i++ )
1709                 if ( g_atm_priv_data.conn[i].vcc != NULL )
1710                         set_qsb(g_atm_priv_data.conn[i].vcc, &g_atm_priv_data.conn[i].vcc->qos, i);
1711
1712         //  TODO: ReTX set xdata_addr
1713         g_xdata_addr = xdata_addr;
1714
1715         g_showtime = 1;
1716
1717 #if defined(CONFIG_VR9)
1718         IFX_REG_W32(0x0F, UTP_CFG);
1719 #endif
1720
1721         printk("enter showtime, cell rate: 0 - %d, 1 - %d, xdata addr: 0x%08x\n",
1722                 g_atm_priv_data.port[0].tx_max_cell_rate,
1723                 g_atm_priv_data.port[1].tx_max_cell_rate,
1724                 (unsigned int)g_xdata_addr);
1725
1726         return 0;
1727 }
1728
1729 static int atm_showtime_exit(void)
1730 {
1731         if ( !g_showtime )
1732                 return -1;
1733
1734 #if defined(CONFIG_VR9)
1735         IFX_REG_W32(0x00, UTP_CFG);
1736 #endif
1737         g_showtime = 0;
1738         g_xdata_addr = NULL;
1739         printk("leave showtime\n");
1740         return 0;
1741 }
1742
1743 extern struct ltq_atm_ops ar9_ops;
1744 extern struct ltq_atm_ops vr9_ops;
1745 extern struct ltq_atm_ops danube_ops;
1746 extern struct ltq_atm_ops ase_ops;
1747
1748 static const struct of_device_id ltq_atm_match[] = {
1749 #ifdef CONFIG_DANUBE
1750         { .compatible = "lantiq,ppe-danube", .data = &danube_ops },
1751 #elif defined CONFIG_AMAZON_SE
1752         { .compatible = "lantiq,ppe-ase", .data = &ase_ops },
1753 #elif defined CONFIG_AR9
1754         { .compatible = "lantiq,ppe-arx100", .data = &ar9_ops },
1755 #elif defined CONFIG_VR9
1756         { .compatible = "lantiq,ppe-xrx200", .data = &vr9_ops },
1757 #endif
1758         {},
1759 };
1760 MODULE_DEVICE_TABLE(of, ltq_atm_match);
1761
1762 static int ltq_atm_probe(struct platform_device *pdev)
1763 {
1764         const struct of_device_id *match;
1765         struct ltq_atm_ops *ops = NULL;
1766         int ret;
1767         int port_num;
1768         struct port_cell_info port_cell = {0};
1769         int i, j;
1770         char ver_str[256];
1771
1772         match = of_match_device(ltq_atm_match, &pdev->dev);
1773         if (!match) {
1774                 dev_err(&pdev->dev, "failed to find matching device\n");
1775                 return -ENOENT;
1776         }
1777         ops = (struct ltq_atm_ops *) match->data;
1778
1779         check_parameters();
1780
1781         ret = init_priv_data();
1782         if ( ret != 0 ) {
1783                 pr_err("INIT_PRIV_DATA_FAIL\n");
1784                 goto INIT_PRIV_DATA_FAIL;
1785         }
1786
1787         ops->init();
1788         init_rx_tables();
1789         init_tx_tables();
1790
1791         /*  create devices  */
1792         for ( port_num = 0; port_num < ATM_PORT_NUMBER; port_num++ ) {
1793                 g_atm_priv_data.port[port_num].dev = atm_dev_register("ifxmips_atm", NULL, &g_ifx_atm_ops, -1, NULL);
1794                 if ( !g_atm_priv_data.port[port_num].dev ) {
1795                         pr_err("failed to register atm device %d!\n", port_num);
1796                         ret = -EIO;
1797                         goto ATM_DEV_REGISTER_FAIL;
1798                 } else {
1799                         g_atm_priv_data.port[port_num].dev->ci_range.vpi_bits = 8;
1800                         g_atm_priv_data.port[port_num].dev->ci_range.vci_bits = 16;
1801                         g_atm_priv_data.port[port_num].dev->link_rate = g_atm_priv_data.port[port_num].tx_max_cell_rate;
1802                         g_atm_priv_data.port[port_num].dev->dev_data = (void*)port_num;
1803                 }
1804         }
1805
1806         /*  register interrupt handler  */
1807         ret = request_irq(PPE_MAILBOX_IGU1_INT, mailbox_irq_handler, IRQF_DISABLED, "atm_mailbox_isr", &g_atm_priv_data);
1808         if ( ret ) {
1809                 if ( ret == -EBUSY ) {
1810                         pr_err("IRQ may be occupied by other driver, please reconfig to disable it.\n");
1811                 } else {
1812                         pr_err("request_irq fail irq:%d\n", PPE_MAILBOX_IGU1_INT);
1813                 }
1814                 goto REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL;
1815         }
1816         disable_irq(PPE_MAILBOX_IGU1_INT);
1817
1818
1819         ret = ops->start(0);
1820         if ( ret ) {
1821                 pr_err("ifx_pp32_start fail!\n");
1822                 goto PP32_START_FAIL;
1823         }
1824
1825         port_cell.port_num = ATM_PORT_NUMBER;
1826         ifx_mei_atm_showtime_check(&g_showtime, &port_cell, &g_xdata_addr);
1827         if ( g_showtime ) {
1828                 for ( i = 0; i < ATM_PORT_NUMBER; i++ )
1829                         if ( port_cell.tx_link_rate[i] != 0 )
1830                                 break;
1831                 for ( j = 0; j < ATM_PORT_NUMBER; j++ )
1832                         g_atm_priv_data.port[j].tx_max_cell_rate =
1833                                 port_cell.tx_link_rate[j] != 0 ? port_cell.tx_link_rate[j] : port_cell.tx_link_rate[i];
1834         }
1835
1836         qsb_global_set();
1837         validate_oam_htu_entry();
1838
1839         ifx_mei_atm_showtime_enter = atm_showtime_enter;
1840         ifx_mei_atm_showtime_exit  = atm_showtime_exit;
1841
1842         ifx_atm_version(ops, ver_str);
1843         printk(KERN_INFO "%s", ver_str);
1844         platform_set_drvdata(pdev, ops);
1845         printk("ifxmips_atm: ATM init succeed\n");
1846
1847         return 0;
1848
1849 PP32_START_FAIL:
1850         free_irq(PPE_MAILBOX_IGU1_INT, &g_atm_priv_data);
1851 REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL:
1852 ATM_DEV_REGISTER_FAIL:
1853         while ( port_num-- > 0 )
1854                 atm_dev_deregister(g_atm_priv_data.port[port_num].dev);
1855 INIT_PRIV_DATA_FAIL:
1856         clear_priv_data();
1857         printk("ifxmips_atm: ATM init failed\n");
1858         return ret;
1859 }
1860
1861 static int ltq_atm_remove(struct platform_device *pdev)
1862 {
1863         int port_num;
1864         struct ltq_atm_ops *ops = platform_get_drvdata(pdev);
1865
1866         ifx_mei_atm_showtime_enter = NULL;
1867         ifx_mei_atm_showtime_exit  = NULL;
1868
1869         invalidate_oam_htu_entry();
1870
1871         ops->stop(0);
1872
1873         free_irq(PPE_MAILBOX_IGU1_INT, &g_atm_priv_data);
1874
1875         for ( port_num = 0; port_num < ATM_PORT_NUMBER; port_num++ )
1876                 atm_dev_deregister(g_atm_priv_data.port[port_num].dev);
1877
1878         ops->shutdown();
1879
1880         clear_priv_data();
1881
1882         return 0;
1883 }
1884
1885 static struct platform_driver ltq_atm_driver = {
1886         .probe = ltq_atm_probe,
1887         .remove = ltq_atm_remove,
1888         .driver = {
1889                 .name = "atm",
1890                 .owner = THIS_MODULE,
1891                 .of_match_table = ltq_atm_match,
1892         },
1893 };
1894
1895 module_platform_driver(ltq_atm_driver);
1896
1897 MODULE_LICENSE("Dual BSD/GPL");