package/mac80211/patches/620-rt2x00-support-rt3352.patch

   1 From 03839951515b0ea2b21d649b1fe7b63f9817d0c8 Mon Sep 17 00:00:00 2001
   2 From: Daniel Golle <dgolle@allnet.de>
   3 Date: Sun, 9 Sep 2012 14:24:39 +0300
   4 Subject: [PATCH] rt2x00: add MediaTek/RaLink Rt3352 WiSoC
   5
   6 Support for the RT3352 WiSoC was developed for and tested with the ALL5002
   7 devboard running OpenWrt. For now, this supports only devices with internal
   8 TXALC. Corrections were made according to the remarks of Stanislaw Gruszka and
   9 Gertjan van Wingerde, thank you guys for reviewing!
  10
  11 Signed-off-by: Daniel Golle <dgolle@allnet.de>
  12 Signed-off-by: John W. Linville <linville@tuxdriver.com>
  13 ---
  14  drivers/net/wireless/rt2x00/rt2800.h    |   5 +
  15  drivers/net/wireless/rt2x00/rt2800lib.c | 211 +++++++++++++++++++++++++++++++-
  16  drivers/net/wireless/rt2x00/rt2x00.h    |   1 +
  17  3 files changed, 212 insertions(+), 5 deletions(-)
  18
  19 diff --git a/drivers/net/wireless/rt2x00/rt2800.h b/drivers/net/wireless/rt2x00/rt2800.h
  20 index e13916f..6d67c3e 100644
  21 --- a/drivers/net/wireless/rt2x00/rt2800.h
  22 +++ b/drivers/net/wireless/rt2x00/rt2800.h
  23 @@ -1943,6 +1943,11 @@ struct mac_iveiv_entry {
  24  #define BBP47_TSSI_ADC6                        FIELD8(0x80)
  25
  26  /*
  27 + * BBP 49
  28 + */
  29 +#define BBP49_UPDATE_FLAG              FIELD8(0x01)
  30 +
  31 +/*
  32   * BBP 109
  33   */
  34  #define BBP109_TX0_POWER               FIELD8(0x0f)
  35 diff --git a/drivers/net/wireless/rt2x00/rt2800lib.c b/drivers/net/wireless/rt2x00/rt2800lib.c
  36 index a04e222..9e09367 100644
  37 --- a/drivers/net/wireless/rt2x00/rt2800lib.c
  38 +++ b/drivers/net/wireless/rt2x00/rt2800lib.c
  39 @@ -1615,6 +1615,7 @@ void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
  40         case 1:
  41                 if (rt2x00_rt(rt2x00dev, RT3070) ||
  42                     rt2x00_rt(rt2x00dev, RT3090) ||
  43 +                   rt2x00_rt(rt2x00dev, RT3352) ||
  44                     rt2x00_rt(rt2x00dev, RT3390)) {
  45                         rt2x00_eeprom_read(rt2x00dev,
  46                                            EEPROM_NIC_CONF1, &eeprom);
  47 @@ -2053,6 +2054,60 @@ static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
  48         }
  49  }
  50
  51 +static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev,
  52 +                                        struct ieee80211_conf *conf,
  53 +                                        struct rf_channel *rf,
  54 +                                        struct channel_info *info)
  55 +{
  56 +       u8 rfcsr;
  57 +
  58 +       rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
  59 +       rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
  60 +
  61 +       rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
  62 +       rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
  63 +       rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
  64 +
  65 +       if (info->default_power1 > POWER_BOUND)
  66 +               rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND);
  67 +       else
  68 +               rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1);
  69 +
  70 +       if (info->default_power2 > POWER_BOUND)
  71 +               rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND);
  72 +       else
  73 +               rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2);
  74 +
  75 +       rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
  76 +       if (rt2x00dev->freq_offset > FREQ_OFFSET_BOUND)
  77 +               rt2x00_set_field8(&rfcsr, RFCSR17_CODE, FREQ_OFFSET_BOUND);
  78 +       else
  79 +               rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
  80 +
  81 +       rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
  82 +
  83 +       rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
  84 +       rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
  85 +       rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
  86 +
  87 +       if ( rt2x00dev->default_ant.tx_chain_num == 2 )
  88 +               rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
  89 +       else
  90 +               rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
  91 +
  92 +       if ( rt2x00dev->default_ant.rx_chain_num == 2 )
  93 +               rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
  94 +       else
  95 +               rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
  96 +
  97 +       rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
  98 +       rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
  99 +
 100 +       rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
 101 +
 102 +       rt2800_rfcsr_write(rt2x00dev, 31, 80);
 103 +}
 104 +
 105  static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
 106                                          struct ieee80211_conf *conf,
 107                                          struct rf_channel *rf,
 108 @@ -2182,6 +2237,9 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
 109         case RF3290:
 110                 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
 111                 break;
 112 +       case RF3322:
 113 +               rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
 114 +               break;
 115         case RF5360:
 116         case RF5370:
 117         case RF5372:
 118 @@ -2194,6 +2252,7 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
 119         }
 120
 121         if (rt2x00_rf(rt2x00dev, RF3290) ||
 122 +           rt2x00_rf(rt2x00dev, RF3322) ||
 123             rt2x00_rf(rt2x00dev, RF5360) ||
 124             rt2x00_rf(rt2x00dev, RF5370) ||
 125             rt2x00_rf(rt2x00dev, RF5372) ||
 126 @@ -2212,10 +2271,17 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
 127         /*
 128          * Change BBP settings
 129          */
 130 -       rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
 131 -       rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
 132 -       rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
 133 -       rt2800_bbp_write(rt2x00dev, 86, 0);
 134 +       if (rt2x00_rt(rt2x00dev, RT3352)) {
 135 +               rt2800_bbp_write(rt2x00dev, 27, 0x0);
 136 +               rt2800_bbp_write(rt2x00dev, 62, 0x26 + rt2x00dev->lna_gain);
 137 +               rt2800_bbp_write(rt2x00dev, 27, 0x20);
 138 +               rt2800_bbp_write(rt2x00dev, 62, 0x26 + rt2x00dev->lna_gain);
 139 +       } else {
 140 +               rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
 141 +               rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
 142 +               rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
 143 +               rt2800_bbp_write(rt2x00dev, 86, 0);
 144 +       }
 145
 146         if (rf->channel <= 14) {
 147                 if (!rt2x00_rt(rt2x00dev, RT5390) &&
 148 @@ -2310,6 +2376,15 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
 149         rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
 150         rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
 151         rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
 152 +
 153 +       /*
 154 +        * Clear update flag
 155 +        */
 156 +       if (rt2x00_rt(rt2x00dev, RT3352)) {
 157 +               rt2800_bbp_read(rt2x00dev, 49, &bbp);
 158 +               rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0);
 159 +               rt2800_bbp_write(rt2x00dev, 49, bbp);
 160 +       }
 161  }
 162
 163  static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
 164 @@ -2998,6 +3073,10 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
 165                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
 166                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
 167                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
 168 +       } else if (rt2x00_rt(rt2x00dev, RT3352)) {
 169 +               rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
 170 +               rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
 171 +               rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
 172         } else if (rt2x00_rt(rt2x00dev, RT3572)) {
 173                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
 174                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
 175 @@ -3378,6 +3457,11 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
 176                      rt2800_wait_bbp_ready(rt2x00dev)))
 177                 return -EACCES;
 178
 179 +       if (rt2x00_rt(rt2x00dev, RT3352)) {
 180 +               rt2800_bbp_write(rt2x00dev, 3, 0x00);
 181 +               rt2800_bbp_write(rt2x00dev, 4, 0x50);
 182 +       }
 183 +
 184         if (rt2x00_rt(rt2x00dev, RT3290) ||
 185             rt2x00_rt(rt2x00dev, RT5390) ||
 186             rt2x00_rt(rt2x00dev, RT5392)) {
 187 @@ -3388,15 +3472,20 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
 188
 189         if (rt2800_is_305x_soc(rt2x00dev) ||
 190             rt2x00_rt(rt2x00dev, RT3290) ||
 191 +           rt2x00_rt(rt2x00dev, RT3352) ||
 192             rt2x00_rt(rt2x00dev, RT3572) ||
 193             rt2x00_rt(rt2x00dev, RT5390) ||
 194             rt2x00_rt(rt2x00dev, RT5392))
 195                 rt2800_bbp_write(rt2x00dev, 31, 0x08);
 196
 197 +       if (rt2x00_rt(rt2x00dev, RT3352))
 198 +               rt2800_bbp_write(rt2x00dev, 47, 0x48);
 199 +
 200         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
 201         rt2800_bbp_write(rt2x00dev, 66, 0x38);
 202
 203         if (rt2x00_rt(rt2x00dev, RT3290) ||
 204 +           rt2x00_rt(rt2x00dev, RT3352) ||
 205             rt2x00_rt(rt2x00dev, RT5390) ||
 206             rt2x00_rt(rt2x00dev, RT5392))
 207                 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
 208 @@ -3405,6 +3494,7 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
 209                 rt2800_bbp_write(rt2x00dev, 69, 0x16);
 210                 rt2800_bbp_write(rt2x00dev, 73, 0x12);
 211         } else if (rt2x00_rt(rt2x00dev, RT3290) ||
 212 +                  rt2x00_rt(rt2x00dev, RT3352) ||
 213                    rt2x00_rt(rt2x00dev, RT5390) ||
 214                    rt2x00_rt(rt2x00dev, RT5392)) {
 215                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
 216 @@ -3436,6 +3526,10 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
 217         } else if (rt2800_is_305x_soc(rt2x00dev)) {
 218                 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
 219                 rt2800_bbp_write(rt2x00dev, 80, 0x08);
 220 +       } else if (rt2x00_rt(rt2x00dev, RT3352)) {
 221 +               rt2800_bbp_write(rt2x00dev, 78, 0x0e);
 222 +               rt2800_bbp_write(rt2x00dev, 80, 0x08);
 223 +               rt2800_bbp_write(rt2x00dev, 81, 0x37);
 224         } else {
 225                 rt2800_bbp_write(rt2x00dev, 81, 0x37);
 226         }
 227 @@ -3465,18 +3559,21 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
 228                 rt2800_bbp_write(rt2x00dev, 84, 0x99);
 229
 230         if (rt2x00_rt(rt2x00dev, RT3290) ||
 231 +           rt2x00_rt(rt2x00dev, RT3352) ||
 232             rt2x00_rt(rt2x00dev, RT5390) ||
 233             rt2x00_rt(rt2x00dev, RT5392))
 234                 rt2800_bbp_write(rt2x00dev, 86, 0x38);
 235         else
 236                 rt2800_bbp_write(rt2x00dev, 86, 0x00);
 237
 238 -       if (rt2x00_rt(rt2x00dev, RT5392))
 239 +       if (rt2x00_rt(rt2x00dev, RT3352) ||
 240 +           rt2x00_rt(rt2x00dev, RT5392))
 241                 rt2800_bbp_write(rt2x00dev, 88, 0x90);
 242
 243         rt2800_bbp_write(rt2x00dev, 91, 0x04);
 244
 245         if (rt2x00_rt(rt2x00dev, RT3290) ||
 246 +           rt2x00_rt(rt2x00dev, RT3352) ||
 247             rt2x00_rt(rt2x00dev, RT5390) ||
 248             rt2x00_rt(rt2x00dev, RT5392))
 249                 rt2800_bbp_write(rt2x00dev, 92, 0x02);
 250 @@ -3493,6 +3590,7 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
 251             rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
 252             rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
 253             rt2x00_rt(rt2x00dev, RT3290) ||
 254 +           rt2x00_rt(rt2x00dev, RT3352) ||
 255             rt2x00_rt(rt2x00dev, RT3572) ||
 256             rt2x00_rt(rt2x00dev, RT5390) ||
 257             rt2x00_rt(rt2x00dev, RT5392) ||
 258 @@ -3502,6 +3600,7 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
 259                 rt2800_bbp_write(rt2x00dev, 103, 0x00);
 260
 261         if (rt2x00_rt(rt2x00dev, RT3290) ||
 262 +           rt2x00_rt(rt2x00dev, RT3352) ||
 263             rt2x00_rt(rt2x00dev, RT5390) ||
 264             rt2x00_rt(rt2x00dev, RT5392))
 265                 rt2800_bbp_write(rt2x00dev, 104, 0x92);
 266 @@ -3510,6 +3609,8 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
 267                 rt2800_bbp_write(rt2x00dev, 105, 0x01);
 268         else if (rt2x00_rt(rt2x00dev, RT3290))
 269                 rt2800_bbp_write(rt2x00dev, 105, 0x1c);
 270 +       else if (rt2x00_rt(rt2x00dev, RT3352))
 271 +               rt2800_bbp_write(rt2x00dev, 105, 0x34);
 272         else if (rt2x00_rt(rt2x00dev, RT5390) ||
 273                          rt2x00_rt(rt2x00dev, RT5392))
 274                 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
 275 @@ -3519,11 +3620,16 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
 276         if (rt2x00_rt(rt2x00dev, RT3290) ||
 277             rt2x00_rt(rt2x00dev, RT5390))
 278                 rt2800_bbp_write(rt2x00dev, 106, 0x03);
 279 +       else if (rt2x00_rt(rt2x00dev, RT3352))
 280 +               rt2800_bbp_write(rt2x00dev, 106, 0x05);
 281         else if (rt2x00_rt(rt2x00dev, RT5392))
 282                 rt2800_bbp_write(rt2x00dev, 106, 0x12);
 283         else
 284                 rt2800_bbp_write(rt2x00dev, 106, 0x35);
 285
 286 +       if (rt2x00_rt(rt2x00dev, RT3352))
 287 +               rt2800_bbp_write(rt2x00dev, 120, 0x50);
 288 +
 289         if (rt2x00_rt(rt2x00dev, RT3290) ||
 290             rt2x00_rt(rt2x00dev, RT5390) ||
 291             rt2x00_rt(rt2x00dev, RT5392))
 292 @@ -3534,6 +3640,9 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
 293                 rt2800_bbp_write(rt2x00dev, 135, 0xf6);
 294         }
 295
 296 +       if (rt2x00_rt(rt2x00dev, RT3352))
 297 +               rt2800_bbp_write(rt2x00dev, 137, 0x0f);
 298 +
 299         if (rt2x00_rt(rt2x00dev, RT3071) ||
 300             rt2x00_rt(rt2x00dev, RT3090) ||
 301             rt2x00_rt(rt2x00dev, RT3390) ||
 302 @@ -3574,6 +3683,28 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
 303                 rt2800_bbp_write(rt2x00dev, 3, value);
 304         }
 305
 306 +       if (rt2x00_rt(rt2x00dev, RT3352)) {
 307 +               rt2800_bbp_write(rt2x00dev, 163, 0xbd);
 308 +               /* Set ITxBF timeout to 0x9c40=1000msec */
 309 +               rt2800_bbp_write(rt2x00dev, 179, 0x02);
 310 +               rt2800_bbp_write(rt2x00dev, 180, 0x00);
 311 +               rt2800_bbp_write(rt2x00dev, 182, 0x40);
 312 +               rt2800_bbp_write(rt2x00dev, 180, 0x01);
 313 +               rt2800_bbp_write(rt2x00dev, 182, 0x9c);
 314 +               rt2800_bbp_write(rt2x00dev, 179, 0x00);
 315 +               /* Reprogram the inband interface to put right values in RXWI */
 316 +               rt2800_bbp_write(rt2x00dev, 142, 0x04);
 317 +               rt2800_bbp_write(rt2x00dev, 143, 0x3b);
 318 +               rt2800_bbp_write(rt2x00dev, 142, 0x06);
 319 +               rt2800_bbp_write(rt2x00dev, 143, 0xa0);
 320 +               rt2800_bbp_write(rt2x00dev, 142, 0x07);
 321 +               rt2800_bbp_write(rt2x00dev, 143, 0xa1);
 322 +               rt2800_bbp_write(rt2x00dev, 142, 0x08);
 323 +               rt2800_bbp_write(rt2x00dev, 143, 0xa2);
 324 +
 325 +               rt2800_bbp_write(rt2x00dev, 148, 0xc8);
 326 +       }
 327 +
 328         if (rt2x00_rt(rt2x00dev, RT5390) ||
 329                 rt2x00_rt(rt2x00dev, RT5392)) {
 330                 int ant, div_mode;
 331 @@ -3707,6 +3838,7 @@ static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
 332             !rt2x00_rt(rt2x00dev, RT3071) &&
 333             !rt2x00_rt(rt2x00dev, RT3090) &&
 334             !rt2x00_rt(rt2x00dev, RT3290) &&
 335 +           !rt2x00_rt(rt2x00dev, RT3352) &&
 336             !rt2x00_rt(rt2x00dev, RT3390) &&
 337             !rt2x00_rt(rt2x00dev, RT3572) &&
 338             !rt2x00_rt(rt2x00dev, RT5390) &&
 339 @@ -3903,6 +4035,70 @@ static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
 340                 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
 341                 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
 342                 return 0;
 343 +       } else if (rt2x00_rt(rt2x00dev, RT3352)) {
 344 +               rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
 345 +               rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
 346 +               rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
 347 +               rt2800_rfcsr_write(rt2x00dev, 3, 0x18);
 348 +               rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
 349 +               rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
 350 +               rt2800_rfcsr_write(rt2x00dev, 6, 0x33);
 351 +               rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
 352 +               rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
 353 +               rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
 354 +               rt2800_rfcsr_write(rt2x00dev, 10, 0xd2);
 355 +               rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
 356 +               rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
 357 +               rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
 358 +               rt2800_rfcsr_write(rt2x00dev, 14, 0x5a);
 359 +               rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
 360 +               rt2800_rfcsr_write(rt2x00dev, 16, 0x01);
 361 +               rt2800_rfcsr_write(rt2x00dev, 18, 0x45);
 362 +               rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
 363 +               rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
 364 +               rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
 365 +               rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
 366 +               rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
 367 +               rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
 368 +               rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
 369 +               rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
 370 +               rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
 371 +               rt2800_rfcsr_write(rt2x00dev, 28, 0x03);
 372 +               rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
 373 +               rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
 374 +               rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
 375 +               rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
 376 +               rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
 377 +               rt2800_rfcsr_write(rt2x00dev, 34, 0x01);
 378 +               rt2800_rfcsr_write(rt2x00dev, 35, 0x03);
 379 +               rt2800_rfcsr_write(rt2x00dev, 36, 0xbd);
 380 +               rt2800_rfcsr_write(rt2x00dev, 37, 0x3c);
 381 +               rt2800_rfcsr_write(rt2x00dev, 38, 0x5f);
 382 +               rt2800_rfcsr_write(rt2x00dev, 39, 0xc5);
 383 +               rt2800_rfcsr_write(rt2x00dev, 40, 0x33);
 384 +               rt2800_rfcsr_write(rt2x00dev, 41, 0x5b);
 385 +               rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
 386 +               rt2800_rfcsr_write(rt2x00dev, 43, 0xdb);
 387 +               rt2800_rfcsr_write(rt2x00dev, 44, 0xdb);
 388 +               rt2800_rfcsr_write(rt2x00dev, 45, 0xdb);
 389 +               rt2800_rfcsr_write(rt2x00dev, 46, 0xdd);
 390 +               rt2800_rfcsr_write(rt2x00dev, 47, 0x0d);
 391 +               rt2800_rfcsr_write(rt2x00dev, 48, 0x14);
 392 +               rt2800_rfcsr_write(rt2x00dev, 49, 0x00);
 393 +               rt2800_rfcsr_write(rt2x00dev, 50, 0x2d);
 394 +               rt2800_rfcsr_write(rt2x00dev, 51, 0x7f);
 395 +               rt2800_rfcsr_write(rt2x00dev, 52, 0x00);
 396 +               rt2800_rfcsr_write(rt2x00dev, 53, 0x52);
 397 +               rt2800_rfcsr_write(rt2x00dev, 54, 0x1b);
 398 +               rt2800_rfcsr_write(rt2x00dev, 55, 0x7f);
 399 +               rt2800_rfcsr_write(rt2x00dev, 56, 0x00);
 400 +               rt2800_rfcsr_write(rt2x00dev, 57, 0x52);
 401 +               rt2800_rfcsr_write(rt2x00dev, 58, 0x1b);
 402 +               rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
 403 +               rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
 404 +               rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
 405 +               rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
 406 +               rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
 407         } else if (rt2x00_rt(rt2x00dev, RT5390)) {
 408                 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
 409                 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
 410 @@ -4104,6 +4300,7 @@ static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
 411                         rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
 412         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
 413                    rt2x00_rt(rt2x00dev, RT3090) ||
 414 +                  rt2x00_rt(rt2x00dev, RT3352) ||
 415                    rt2x00_rt(rt2x00dev, RT3390) ||
 416                    rt2x00_rt(rt2x00dev, RT3572)) {
 417                 drv_data->calibration_bw20 =
 418 @@ -4566,6 +4763,7 @@ static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
 419         case RT3071:
 420         case RT3090:
 421         case RT3290:
 422 +       case RT3352:
 423         case RT3390:
 424         case RT3572:
 425         case RT5390:
 426 @@ -4588,6 +4786,7 @@ static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
 427         case RF3052:
 428         case RF3290:
 429         case RF3320:
 430 +       case RF3322:
 431         case RF5360:
 432         case RF5370:
 433         case RF5372:
 434 @@ -4612,6 +4811,7 @@ static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
 435
 436         if (rt2x00_rt(rt2x00dev, RT3070) ||
 437             rt2x00_rt(rt2x00dev, RT3090) ||
 438 +           rt2x00_rt(rt2x00dev, RT3352) ||
 439             rt2x00_rt(rt2x00dev, RT3390)) {
 440                 value = rt2x00_get_field16(eeprom,
 441                                 EEPROM_NIC_CONF1_ANT_DIVERSITY);
 442 @@ -4904,6 +5104,7 @@ static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
 443                    rt2x00_rf(rt2x00dev, RF3022) ||
 444                    rt2x00_rf(rt2x00dev, RF3290) ||
 445                    rt2x00_rf(rt2x00dev, RF3320) ||
 446 +                  rt2x00_rf(rt2x00dev, RF3322) ||
 447                    rt2x00_rf(rt2x00dev, RF5360) ||
 448                    rt2x00_rf(rt2x00dev, RF5370) ||
 449                    rt2x00_rf(rt2x00dev, RF5372) ||
 450 diff --git a/drivers/net/wireless/rt2x00/rt2x00.h b/drivers/net/wireless/rt2x00/rt2x00.h
 451 index f991e8b..49375c8 100644
 452 --- a/drivers/net/wireless/rt2x00/rt2x00.h
 453 +++ b/drivers/net/wireless/rt2x00/rt2x00.h
 454 @@ -188,6 +188,7 @@ struct rt2x00_chip {
 455  #define RT3071         0x3071
 456  #define RT3090         0x3090  /* 2.4GHz PCIe */
 457  #define RT3290         0x3290
 458 +#define RT3352         0x3352  /* WSOC */
 459  #define RT3390         0x3390
 460  #define RT3572         0x3572
 461  #define RT3593         0x3593
 462 --
 463 1.7.12.2
 464