package/mac80211/patches/573-ath9k_xlna_bias.patch

   1 --- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
   2 +++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
   3 @@ -131,8 +131,9 @@ static const struct ar9300_eeprom ar9300
   4                 .thresh62 = 28,
   5                 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
   6                 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
   7 +               .xlna_bias_strength = 0,
   8                 .futureModal = {
   9 -                       0, 0, 0, 0, 0, 0, 0, 0,
  10 +                       0, 0, 0, 0, 0, 0, 0,
  11                 },
  12          },
  13         .base_ext1 = {
  14 @@ -331,8 +332,9 @@ static const struct ar9300_eeprom ar9300
  15                 .thresh62 = 28,
  16                 .papdRateMaskHt20 = LE32(0x0c80c080),
  17                 .papdRateMaskHt40 = LE32(0x0080c080),
  18 +               .xlna_bias_strength = 0,
  19                 .futureModal = {
  20 -                       0, 0, 0, 0, 0, 0, 0, 0,
  21 +                       0, 0, 0, 0, 0, 0, 0,
  22                 },
  23          },
  24         .base_ext2 = {
  25 @@ -704,8 +706,9 @@ static const struct ar9300_eeprom ar9300
  26                 .thresh62 = 28,
  27                 .papdRateMaskHt20 = LE32(0x0c80c080),
  28                 .papdRateMaskHt40 = LE32(0x0080c080),
  29 +               .xlna_bias_strength = 0,
  30                 .futureModal = {
  31 -                       0, 0, 0, 0, 0, 0, 0, 0,
  32 +                       0, 0, 0, 0, 0, 0, 0,
  33                 },
  34          },
  35          .base_ext1 = {
  36 @@ -904,8 +907,9 @@ static const struct ar9300_eeprom ar9300
  37                 .thresh62 = 28,
  38                 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
  39                 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
  40 +               .xlna_bias_strength = 0,
  41                 .futureModal = {
  42 -                       0, 0, 0, 0, 0, 0, 0, 0,
  43 +                       0, 0, 0, 0, 0, 0, 0,
  44                 },
  45          },
  46         .base_ext2 = {
  47 @@ -1278,8 +1282,9 @@ static const struct ar9300_eeprom ar9300
  48                 .thresh62 = 28,
  49                 .papdRateMaskHt20 = LE32(0x0c80c080),
  50                 .papdRateMaskHt40 = LE32(0x0080c080),
  51 +               .xlna_bias_strength = 0,
  52                 .futureModal = {
  53 -                       0, 0, 0, 0, 0, 0, 0, 0,
  54 +                       0, 0, 0, 0, 0, 0, 0,
  55                 },
  56         },
  57         .base_ext1 = {
  58 @@ -1478,8 +1483,9 @@ static const struct ar9300_eeprom ar9300
  59                 .thresh62 = 28,
  60                 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
  61                 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
  62 +               .xlna_bias_strength = 0,
  63                 .futureModal = {
  64 -                       0, 0, 0, 0, 0, 0, 0, 0,
  65 +                       0, 0, 0, 0, 0, 0, 0,
  66                 },
  67         },
  68         .base_ext2 = {
  69 @@ -1852,8 +1858,9 @@ static const struct ar9300_eeprom ar9300
  70                 .thresh62 = 28,
  71                 .papdRateMaskHt20 = LE32(0x0c80c080),
  72                 .papdRateMaskHt40 = LE32(0x0080c080),
  73 +               .xlna_bias_strength = 0,
  74                 .futureModal = {
  75 -                       0, 0, 0, 0, 0, 0, 0, 0,
  76 +                       0, 0, 0, 0, 0, 0, 0,
  77                 },
  78         },
  79         .base_ext1 = {
  80 @@ -2052,8 +2059,9 @@ static const struct ar9300_eeprom ar9300
  81                 .thresh62 = 28,
  82                 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
  83                 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
  84 +               .xlna_bias_strength = 0,
  85                 .futureModal = {
  86 -                       0, 0, 0, 0, 0, 0, 0, 0,
  87 +                       0, 0, 0, 0, 0, 0, 0,
  88                 },
  89         },
  90         .base_ext2 = {
  91 @@ -2425,8 +2433,9 @@ static const struct ar9300_eeprom ar9300
  92                 .thresh62 = 28,
  93                 .papdRateMaskHt20 = LE32(0x0c80C080),
  94                 .papdRateMaskHt40 = LE32(0x0080C080),
  95 +               .xlna_bias_strength = 0,
  96                 .futureModal = {
  97 -                       0, 0, 0, 0, 0, 0, 0, 0,
  98 +                       0, 0, 0, 0, 0, 0, 0,
  99                 },
 100          },
 101          .base_ext1 = {
 102 @@ -2625,8 +2634,9 @@ static const struct ar9300_eeprom ar9300
 103                 .thresh62 = 28,
 104                 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
 105                 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
 106 +               .xlna_bias_strength = 0,
 107                 .futureModal = {
 108 -                       0, 0, 0, 0, 0, 0, 0, 0,
 109 +                       0, 0, 0, 0, 0, 0, 0,
 110                 },
 111          },
 112         .base_ext2 = {
 113 @@ -3942,6 +3952,28 @@ static void ar9003_hw_xpa_timing_control
 114                               AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON, xpa_ctl);
 115  }
 116
 117 +static void ar9003_hw_xlna_bias_strength_apply(struct ath_hw *ah, bool is2ghz)
 118 +{
 119 +       struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
 120 +       u8 bias;
 121 +
 122 +       if (!(eep->baseEepHeader.featureEnable & 0x40))
 123 +               return;
 124 +
 125 +       if (!AR_SREV_9300(ah))
 126 +               return;
 127 +
 128 +       bias = ar9003_modal_header(ah, is2ghz)->xlna_bias_strength;
 129 +       REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX4, AR_PHY_65NM_RXTX4_XLNA_BIAS,
 130 +                     bias & 0x3);
 131 +       bias >>= 2;
 132 +       REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX4, AR_PHY_65NM_RXTX4_XLNA_BIAS,
 133 +                     bias & 0x3);
 134 +       bias >>= 2;
 135 +       REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX4, AR_PHY_65NM_RXTX4_XLNA_BIAS,
 136 +                     bias & 0x3);
 137 +}
 138 +
 139  static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
 140                                              struct ath9k_channel *chan)
 141  {
 142 @@ -3950,6 +3982,7 @@ static void ath9k_hw_ar9300_set_board_va
 143         ar9003_hw_xpa_bias_level_apply(ah, is2ghz);
 144         ar9003_hw_ant_ctrl_apply(ah, is2ghz);
 145         ar9003_hw_drive_strength_apply(ah);
 146 +       ar9003_hw_xlna_bias_strength_apply(ah, is2ghz);
 147         ar9003_hw_atten_apply(ah, chan);
 148         ar9003_hw_quick_drop_apply(ah, chan->channel);
 149         if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah) && !AR_SREV_9550(ah))
 150 --- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
 151 +++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
 152 @@ -231,7 +231,8 @@ struct ar9300_modal_eep_header {
 153         __le32 papdRateMaskHt20;
 154         __le32 papdRateMaskHt40;
 155         __le16 switchcomspdt;
 156 -       u8 futureModal[8];
 157 +       u8 xlna_bias_strength;
 158 +       u8 futureModal[7];
 159  } __packed;
 160
 161  struct ar9300_cal_data_per_freq_op_loop {
 162 --- a/drivers/net/wireless/ath/ath9k/ar9003_phy.h
 163 +++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
 164 @@ -633,6 +633,8 @@
 165  #define AR_PHY_65NM_CH0_BIAS2       0x160c4
 166  #define AR_PHY_65NM_CH0_BIAS4       0x160cc
 167  #define AR_PHY_65NM_CH0_RXTX4       0x1610c
 168 +#define AR_PHY_65NM_CH1_RXTX4       0x1650c
 169 +#define AR_PHY_65NM_CH2_RXTX4       0x1690c
 170
 171  #define AR_CH0_TOP     (AR_SREV_9300(ah) ? 0x16288 : \
 172                                 ((AR_SREV_9462(ah) ? 0x1628c : 0x16280)))
 173 @@ -876,6 +878,9 @@
 174  #define AR_PHY_65NM_CH0_RXTX4_THERM_ON          0x10000000
 175  #define AR_PHY_65NM_CH0_RXTX4_THERM_ON_S        28
 176
 177 +#define AR_PHY_65NM_RXTX4_XLNA_BIAS            0xC0000000
 178 +#define AR_PHY_65NM_RXTX4_XLNA_BIAS_S          30
 179 +
 180  /*
 181   * Channel 1 Register Map
 182   */