package/mac80211/patches/566-ath9k_fix_initval_array.patch

   1 --- a/drivers/net/wireless/ath/ath9k/ar9002_hw.c
   2 +++ b/drivers/net/wireless/ath/ath9k/ar9002_hw.c
   3 @@ -26,101 +26,70 @@
   4  static void ar9002_hw_init_mode_regs(struct ath_hw *ah)
   5  {
   6         if (AR_SREV_9271(ah)) {
   7 -               INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271,
   8 -                              ARRAY_SIZE(ar9271Modes_9271), 5);
   9 -               INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
  10 -                              ARRAY_SIZE(ar9271Common_9271), 2);
  11 -               INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg,
  12 -                              ARRAY_SIZE(ar9271Modes_9271_ANI_reg), 5);
  13 +               INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271);
  14 +               INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271);
  15 +               INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg);
  16                 return;
  17         }
  18
  19         if (ah->config.pcie_clock_req)
  20                 INIT_INI_ARRAY(&ah->iniPcieSerdes,
  21 -                          ar9280PciePhy_clkreq_off_L1_9280,
  22 -                          ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280), 2);
  23 +                          ar9280PciePhy_clkreq_off_L1_9280);
  24         else
  25                 INIT_INI_ARRAY(&ah->iniPcieSerdes,
  26 -                          ar9280PciePhy_clkreq_always_on_L1_9280,
  27 -                          ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
  28 +                          ar9280PciePhy_clkreq_always_on_L1_9280);
  29
  30         if (AR_SREV_9287_11_OR_LATER(ah)) {
  31 -               INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
  32 -                               ARRAY_SIZE(ar9287Modes_9287_1_1), 5);
  33 -               INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
  34 -                               ARRAY_SIZE(ar9287Common_9287_1_1), 2);
  35 +               INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1);
  36 +               INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1);
  37         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
  38 -               INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
  39 -                              ARRAY_SIZE(ar9285Modes_9285_1_2), 5);
  40 -               INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
  41 -                              ARRAY_SIZE(ar9285Common_9285_1_2), 2);
  42 +               INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2);
  43 +               INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2);
  44         } else if (AR_SREV_9280_20_OR_LATER(ah)) {
  45 -               INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
  46 -                              ARRAY_SIZE(ar9280Modes_9280_2), 5);
  47 -               INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
  48 -                              ARRAY_SIZE(ar9280Common_9280_2), 2);
  49 +               INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2);
  50 +               INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2);
  51
  52                 INIT_INI_ARRAY(&ah->iniModesFastClock,
  53 -                              ar9280Modes_fast_clock_9280_2,
  54 -                              ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
  55 +                              ar9280Modes_fast_clock_9280_2);
  56         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
  57 -               INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
  58 -                              ARRAY_SIZE(ar5416Modes_9160), 5);
  59 -               INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
  60 -                              ARRAY_SIZE(ar5416Common_9160), 2);
  61 +               INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160);
  62 +               INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160);
  63                 if (AR_SREV_9160_11(ah)) {
  64                         INIT_INI_ARRAY(&ah->iniAddac,
  65 -                                      ar5416Addac_9160_1_1,
  66 -                                      ARRAY_SIZE(ar5416Addac_9160_1_1), 2);
  67 +                                      ar5416Addac_9160_1_1);
  68                 } else {
  69 -                       INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
  70 -                                      ARRAY_SIZE(ar5416Addac_9160), 2);
  71 +                       INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160);
  72                 }
  73         } else if (AR_SREV_9100_OR_LATER(ah)) {
  74 -               INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
  75 -                              ARRAY_SIZE(ar5416Modes_9100), 5);
  76 -               INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
  77 -                              ARRAY_SIZE(ar5416Common_9100), 2);
  78 -               INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
  79 -                              ARRAY_SIZE(ar5416Bank6_9100), 3);
  80 -               INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
  81 -                              ARRAY_SIZE(ar5416Addac_9100), 2);
  82 +               INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100);
  83 +               INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100);
  84 +               INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100);
  85 +               INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100);
  86         } else {
  87 -               INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
  88 -                              ARRAY_SIZE(ar5416Modes), 5);
  89 -               INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
  90 -                              ARRAY_SIZE(ar5416Common), 2);
  91 -               INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
  92 -                              ARRAY_SIZE(ar5416Bank6TPC), 3);
  93 -               INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
  94 -                              ARRAY_SIZE(ar5416Addac), 2);
  95 +               INIT_INI_ARRAY(&ah->iniModes, ar5416Modes);
  96 +               INIT_INI_ARRAY(&ah->iniCommon, ar5416Common);
  97 +               INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC);
  98 +               INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac);
  99         }
 100
 101         if (!AR_SREV_9280_20_OR_LATER(ah)) {
 102                 /* Common for AR5416, AR913x, AR9160 */
 103 -               INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
 104 -                              ARRAY_SIZE(ar5416BB_RfGain), 3);
 105 +               INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain);
 106
 107 -               INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
 108 -                              ARRAY_SIZE(ar5416Bank0), 2);
 109 -               INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
 110 -                              ARRAY_SIZE(ar5416Bank1), 2);
 111 -               INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
 112 -                              ARRAY_SIZE(ar5416Bank2), 2);
 113 -               INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
 114 -                              ARRAY_SIZE(ar5416Bank3), 3);
 115 -               INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
 116 -                              ARRAY_SIZE(ar5416Bank7), 2);
 117 +               INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0);
 118 +               INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1);
 119 +               INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2);
 120 +               INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3);
 121 +               INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7);
 122
 123                 /* Common for AR5416, AR9160 */
 124                 if (!AR_SREV_9100(ah))
 125 -                       INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
 126 -                                      ARRAY_SIZE(ar5416Bank6), 3);
 127 +                       INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6);
 128
 129                 /* Common for AR913x, AR9160 */
 130                 if (!AR_SREV_5416(ah))
 131 -                       INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
 132 -                                      ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
 133 +                       INIT_INI_ARRAY(&ah->iniBank6TPC,
 134 +                                     ar5416Bank6TPC_9100);
 135         }
 136
 137         /* iniAddac needs to be modified for these chips */
 138 @@ -143,13 +112,9 @@ static void ar9002_hw_init_mode_regs(str
 139         }
 140         if (AR_SREV_9287_11_OR_LATER(ah)) {
 141                 INIT_INI_ARRAY(&ah->iniCckfirNormal,
 142 -                      ar9287Common_normal_cck_fir_coeff_9287_1_1,
 143 -                      ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_9287_1_1),
 144 -                      2);
 145 +                      ar9287Common_normal_cck_fir_coeff_9287_1_1);
 146                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 147 -                      ar9287Common_japan_2484_cck_fir_coeff_9287_1_1,
 148 -                      ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_9287_1_1),
 149 -                      2);
 150 +                      ar9287Common_japan_2484_cck_fir_coeff_9287_1_1);
 151         }
 152  }
 153
 154 @@ -163,20 +128,16 @@ static void ar9280_20_hw_init_rxgain_ini
 155
 156                 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
 157                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 158 -                       ar9280Modes_backoff_13db_rxgain_9280_2,
 159 -                       ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 5);
 160 +                                      ar9280Modes_backoff_13db_rxgain_9280_2);
 161                 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
 162                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 163 -                       ar9280Modes_backoff_23db_rxgain_9280_2,
 164 -                       ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 5);
 165 +                                      ar9280Modes_backoff_23db_rxgain_9280_2);
 166                 else
 167                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 168 -                       ar9280Modes_original_rxgain_9280_2,
 169 -                       ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 5);
 170 +                                      ar9280Modes_original_rxgain_9280_2);
 171         } else {
 172                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 173 -                       ar9280Modes_original_rxgain_9280_2,
 174 -                       ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 5);
 175 +                              ar9280Modes_original_rxgain_9280_2);
 176         }
 177  }
 178
 179 @@ -186,16 +147,13 @@ static void ar9280_20_hw_init_txgain_ini
 180             AR5416_EEP_MINOR_VER_19) {
 181                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
 182                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 183 -                       ar9280Modes_high_power_tx_gain_9280_2,
 184 -                       ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 5);
 185 +                                      ar9280Modes_high_power_tx_gain_9280_2);
 186                 else
 187                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 188 -                       ar9280Modes_original_tx_gain_9280_2,
 189 -                       ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 5);
 190 +                                      ar9280Modes_original_tx_gain_9280_2);
 191         } else {
 192                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 193 -               ar9280Modes_original_tx_gain_9280_2,
 194 -               ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 5);
 195 +                              ar9280Modes_original_tx_gain_9280_2);
 196         }
 197  }
 198
 199 @@ -203,12 +161,10 @@ static void ar9271_hw_init_txgain_ini(st
 200  {
 201         if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
 202                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 203 -                              ar9271Modes_high_power_tx_gain_9271,
 204 -                              ARRAY_SIZE(ar9271Modes_high_power_tx_gain_9271), 5);
 205 +                              ar9271Modes_high_power_tx_gain_9271);
 206         else
 207                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 208 -                              ar9271Modes_normal_power_tx_gain_9271,
 209 -                              ARRAY_SIZE(ar9271Modes_normal_power_tx_gain_9271), 5);
 210 +                              ar9271Modes_normal_power_tx_gain_9271);
 211  }
 212
 213  static void ar9002_hw_init_mode_gain_regs(struct ath_hw *ah)
 214 @@ -217,8 +173,7 @@ static void ar9002_hw_init_mode_gain_reg
 215
 216         if (AR_SREV_9287_11_OR_LATER(ah))
 217                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 218 -               ar9287Modes_rx_gain_9287_1_1,
 219 -               ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 5);
 220 +                              ar9287Modes_rx_gain_9287_1_1);
 221         else if (AR_SREV_9280_20(ah))
 222                 ar9280_20_hw_init_rxgain_ini(ah);
 223
 224 @@ -226,8 +181,7 @@ static void ar9002_hw_init_mode_gain_reg
 225                 ar9271_hw_init_txgain_ini(ah, txgain_type);
 226         } else if (AR_SREV_9287_11_OR_LATER(ah)) {
 227                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 228 -               ar9287Modes_tx_gain_9287_1_1,
 229 -               ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 5);
 230 +                              ar9287Modes_tx_gain_9287_1_1);
 231         } else if (AR_SREV_9280_20(ah)) {
 232                 ar9280_20_hw_init_txgain_ini(ah, txgain_type);
 233         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
 234 @@ -235,26 +189,18 @@ static void ar9002_hw_init_mode_gain_reg
 235                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
 236                         if (AR_SREV_9285E_20(ah)) {
 237                                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 238 -                               ar9285Modes_XE2_0_high_power,
 239 -                               ARRAY_SIZE(
 240 -                                 ar9285Modes_XE2_0_high_power), 5);
 241 +                                              ar9285Modes_XE2_0_high_power);
 242                         } else {
 243                                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 244 -                               ar9285Modes_high_power_tx_gain_9285_1_2,
 245 -                               ARRAY_SIZE(
 246 -                                 ar9285Modes_high_power_tx_gain_9285_1_2), 5);
 247 +                                       ar9285Modes_high_power_tx_gain_9285_1_2);
 248                         }
 249                 } else {
 250                         if (AR_SREV_9285E_20(ah)) {
 251                                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 252 -                               ar9285Modes_XE2_0_normal_power,
 253 -                               ARRAY_SIZE(
 254 -                                 ar9285Modes_XE2_0_normal_power), 5);
 255 +                                              ar9285Modes_XE2_0_normal_power);
 256                         } else {
 257                                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 258 -                               ar9285Modes_original_tx_gain_9285_1_2,
 259 -                               ARRAY_SIZE(
 260 -                                 ar9285Modes_original_tx_gain_9285_1_2), 5);
 261 +                                       ar9285Modes_original_tx_gain_9285_1_2);
 262                         }
 263                 }
 264         }
 265 --- a/drivers/net/wireless/ath/ath9k/calib.h
 266 +++ b/drivers/net/wireless/ath/ath9k/calib.h
 267 @@ -30,10 +30,10 @@ struct ar5416IniArray {
 268         u32 ia_columns;
 269  };
 270
 271 -#define INIT_INI_ARRAY(iniarray, array, rows, columns) do {    \
 272 +#define INIT_INI_ARRAY(iniarray, array) do {   \
 273                 (iniarray)->ia_array = (u32 *)(array);          \
 274 -               (iniarray)->ia_rows = (rows);                   \
 275 -               (iniarray)->ia_columns = (columns);             \
 276 +               (iniarray)->ia_rows = ARRAY_SIZE(array);        \
 277 +               (iniarray)->ia_columns = ARRAY_SIZE(array[0]);  \
 278         } while (0)
 279
 280  #define INI_RA(iniarray, row, column) \
 281 --- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c
 282 +++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
 283 @@ -44,462 +44,310 @@ static void ar9003_hw_init_mode_regs(str
 284                 ar9462_2p0_baseband_core_txfir_coeff_japan_2484
 285         if (AR_SREV_9330_11(ah)) {
 286                 /* mac */
 287 -               INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
 288                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 289 -                               ar9331_1p1_mac_core,
 290 -                               ARRAY_SIZE(ar9331_1p1_mac_core), 2);
 291 +                               ar9331_1p1_mac_core);
 292                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 293 -                               ar9331_1p1_mac_postamble,
 294 -                               ARRAY_SIZE(ar9331_1p1_mac_postamble), 5);
 295 +                               ar9331_1p1_mac_postamble);
 296
 297                 /* bb */
 298 -               INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
 299                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 300 -                               ar9331_1p1_baseband_core,
 301 -                               ARRAY_SIZE(ar9331_1p1_baseband_core), 2);
 302 +                               ar9331_1p1_baseband_core);
 303                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 304 -                               ar9331_1p1_baseband_postamble,
 305 -                               ARRAY_SIZE(ar9331_1p1_baseband_postamble), 5);
 306 +                               ar9331_1p1_baseband_postamble);
 307
 308                 /* radio */
 309 -               INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
 310                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 311 -                               ar9331_1p1_radio_core,
 312 -                               ARRAY_SIZE(ar9331_1p1_radio_core), 2);
 313 -               INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], NULL, 0, 0);
 314 +                               ar9331_1p1_radio_core);
 315
 316                 /* soc */
 317                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 318 -                               ar9331_1p1_soc_preamble,
 319 -                               ARRAY_SIZE(ar9331_1p1_soc_preamble), 2);
 320 -               INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
 321 +                               ar9331_1p1_soc_preamble);
 322                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 323 -                               ar9331_1p1_soc_postamble,
 324 -                               ARRAY_SIZE(ar9331_1p1_soc_postamble), 2);
 325 +                               ar9331_1p1_soc_postamble);
 326
 327                 /* rx/tx gain */
 328                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 329 -                               ar9331_common_rx_gain_1p1,
 330 -                               ARRAY_SIZE(ar9331_common_rx_gain_1p1), 2);
 331 +                               ar9331_common_rx_gain_1p1);
 332                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 333 -                       ar9331_modes_lowest_ob_db_tx_gain_1p1,
 334 -                       ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p1),
 335 -                       5);
 336 +                               ar9331_modes_lowest_ob_db_tx_gain_1p1);
 337
 338                 /* additional clock settings */
 339                 if (ah->is_clk_25mhz)
 340                         INIT_INI_ARRAY(&ah->iniAdditional,
 341 -                                       ar9331_1p1_xtal_25M,
 342 -                                       ARRAY_SIZE(ar9331_1p1_xtal_25M), 2);
 343 +                                       ar9331_1p1_xtal_25M);
 344                 else
 345                         INIT_INI_ARRAY(&ah->iniAdditional,
 346 -                                       ar9331_1p1_xtal_40M,
 347 -                                       ARRAY_SIZE(ar9331_1p1_xtal_40M), 2);
 348 +                                       ar9331_1p1_xtal_40M);
 349         } else if (AR_SREV_9330_12(ah)) {
 350                 /* mac */
 351 -               INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
 352                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 353 -                               ar9331_1p2_mac_core,
 354 -                               ARRAY_SIZE(ar9331_1p2_mac_core), 2);
 355 +                               ar9331_1p2_mac_core);
 356                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 357 -                               ar9331_1p2_mac_postamble,
 358 -                               ARRAY_SIZE(ar9331_1p2_mac_postamble), 5);
 359 +                               ar9331_1p2_mac_postamble);
 360
 361                 /* bb */
 362 -               INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
 363                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 364 -                               ar9331_1p2_baseband_core,
 365 -                               ARRAY_SIZE(ar9331_1p2_baseband_core), 2);
 366 +                               ar9331_1p2_baseband_core);
 367                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 368 -                               ar9331_1p2_baseband_postamble,
 369 -                               ARRAY_SIZE(ar9331_1p2_baseband_postamble), 5);
 370 +                               ar9331_1p2_baseband_postamble);
 371
 372                 /* radio */
 373 -               INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
 374                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 375 -                               ar9331_1p2_radio_core,
 376 -                               ARRAY_SIZE(ar9331_1p2_radio_core), 2);
 377 -               INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], NULL, 0, 0);
 378 +                               ar9331_1p2_radio_core);
 379
 380                 /* soc */
 381                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 382 -                               ar9331_1p2_soc_preamble,
 383 -                               ARRAY_SIZE(ar9331_1p2_soc_preamble), 2);
 384 -               INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
 385 +                               ar9331_1p2_soc_preamble);
 386                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 387 -                               ar9331_1p2_soc_postamble,
 388 -                               ARRAY_SIZE(ar9331_1p2_soc_postamble), 2);
 389 +                               ar9331_1p2_soc_postamble);
 390
 391                 /* rx/tx gain */
 392                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 393 -                               ar9331_common_rx_gain_1p2,
 394 -                               ARRAY_SIZE(ar9331_common_rx_gain_1p2), 2);
 395 +                               ar9331_common_rx_gain_1p2);
 396                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 397 -                       ar9331_modes_lowest_ob_db_tx_gain_1p2,
 398 -                       ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p2),
 399 -                       5);
 400 +                               ar9331_modes_lowest_ob_db_tx_gain_1p2);
 401
 402                 /* additional clock settings */
 403                 if (ah->is_clk_25mhz)
 404                         INIT_INI_ARRAY(&ah->iniAdditional,
 405 -                                       ar9331_1p2_xtal_25M,
 406 -                                       ARRAY_SIZE(ar9331_1p2_xtal_25M), 2);
 407 +                                       ar9331_1p2_xtal_25M);
 408                 else
 409                         INIT_INI_ARRAY(&ah->iniAdditional,
 410 -                                       ar9331_1p2_xtal_40M,
 411 -                                       ARRAY_SIZE(ar9331_1p2_xtal_40M), 2);
 412 +                                       ar9331_1p2_xtal_40M);
 413         } else if (AR_SREV_9340(ah)) {
 414                 /* mac */
 415 -               INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
 416                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 417 -                               ar9340_1p0_mac_core,
 418 -                               ARRAY_SIZE(ar9340_1p0_mac_core), 2);
 419 +                               ar9340_1p0_mac_core);
 420                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 421 -                               ar9340_1p0_mac_postamble,
 422 -                               ARRAY_SIZE(ar9340_1p0_mac_postamble), 5);
 423 +                               ar9340_1p0_mac_postamble);
 424
 425                 /* bb */
 426 -               INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
 427                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 428 -                               ar9340_1p0_baseband_core,
 429 -                               ARRAY_SIZE(ar9340_1p0_baseband_core), 2);
 430 +                               ar9340_1p0_baseband_core);
 431                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 432 -                               ar9340_1p0_baseband_postamble,
 433 -                               ARRAY_SIZE(ar9340_1p0_baseband_postamble), 5);
 434 +                               ar9340_1p0_baseband_postamble);
 435
 436                 /* radio */
 437 -               INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
 438                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 439 -                               ar9340_1p0_radio_core,
 440 -                               ARRAY_SIZE(ar9340_1p0_radio_core), 2);
 441 +                               ar9340_1p0_radio_core);
 442                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 443 -                               ar9340_1p0_radio_postamble,
 444 -                               ARRAY_SIZE(ar9340_1p0_radio_postamble), 5);
 445 +                               ar9340_1p0_radio_postamble);
 446
 447                 /* soc */
 448                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 449 -                               ar9340_1p0_soc_preamble,
 450 -                               ARRAY_SIZE(ar9340_1p0_soc_preamble), 2);
 451 -               INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
 452 +                               ar9340_1p0_soc_preamble);
 453                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 454 -                               ar9340_1p0_soc_postamble,
 455 -                               ARRAY_SIZE(ar9340_1p0_soc_postamble), 5);
 456 +                               ar9340_1p0_soc_postamble);
 457
 458                 /* rx/tx gain */
 459                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 460 -                               ar9340Common_wo_xlna_rx_gain_table_1p0,
 461 -                               ARRAY_SIZE(ar9340Common_wo_xlna_rx_gain_table_1p0),
 462 -                               5);
 463 -               INIT_INI_ARRAY(&ah->iniModesTxGain,
 464 -                               ar9340Modes_high_ob_db_tx_gain_table_1p0,
 465 -                               ARRAY_SIZE(ar9340Modes_high_ob_db_tx_gain_table_1p0),
 466 -                               5);
 467 +                               ar9340Common_wo_xlna_rx_gain_table_1p0);
 468 +               INIT_INI_ARRAY(&ah->iniModesTxGain,
 469 +                               ar9340Modes_high_ob_db_tx_gain_table_1p0);
 470
 471                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 472 -                               ar9340Modes_fast_clock_1p0,
 473 -                               ARRAY_SIZE(ar9340Modes_fast_clock_1p0),
 474 -                               3);
 475 +                               ar9340Modes_fast_clock_1p0);
 476
 477                 if (!ah->is_clk_25mhz)
 478                         INIT_INI_ARRAY(&ah->iniAdditional,
 479 -                                      ar9340_1p0_radio_core_40M,
 480 -                                      ARRAY_SIZE(ar9340_1p0_radio_core_40M),
 481 -                                      2);
 482 +                                      ar9340_1p0_radio_core_40M);
 483         } else if (AR_SREV_9485_11(ah)) {
 484                 /* mac */
 485 -               INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
 486                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 487 -                               ar9485_1_1_mac_core,
 488 -                               ARRAY_SIZE(ar9485_1_1_mac_core), 2);
 489 +                               ar9485_1_1_mac_core);
 490                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 491 -                               ar9485_1_1_mac_postamble,
 492 -                               ARRAY_SIZE(ar9485_1_1_mac_postamble), 5);
 493 +                               ar9485_1_1_mac_postamble);
 494
 495                 /* bb */
 496 -               INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_1,
 497 -                               ARRAY_SIZE(ar9485_1_1), 2);
 498 +               INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_1);
 499                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 500 -                               ar9485_1_1_baseband_core,
 501 -                               ARRAY_SIZE(ar9485_1_1_baseband_core), 2);
 502 +                               ar9485_1_1_baseband_core);
 503                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 504 -                               ar9485_1_1_baseband_postamble,
 505 -                               ARRAY_SIZE(ar9485_1_1_baseband_postamble), 5);
 506 +                               ar9485_1_1_baseband_postamble);
 507
 508                 /* radio */
 509 -               INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
 510                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 511 -                               ar9485_1_1_radio_core,
 512 -                               ARRAY_SIZE(ar9485_1_1_radio_core), 2);
 513 +                               ar9485_1_1_radio_core);
 514                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 515 -                               ar9485_1_1_radio_postamble,
 516 -                               ARRAY_SIZE(ar9485_1_1_radio_postamble), 2);
 517 +                               ar9485_1_1_radio_postamble);
 518
 519                 /* soc */
 520                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 521 -                               ar9485_1_1_soc_preamble,
 522 -                               ARRAY_SIZE(ar9485_1_1_soc_preamble), 2);
 523 -               INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
 524 -               INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], NULL, 0, 0);
 525 +                               ar9485_1_1_soc_preamble);
 526
 527                 /* rx/tx gain */
 528                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 529 -                               ar9485Common_wo_xlna_rx_gain_1_1,
 530 -                               ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1), 2);
 531 +                               ar9485Common_wo_xlna_rx_gain_1_1);
 532                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 533 -                               ar9485_modes_lowest_ob_db_tx_gain_1_1,
 534 -                               ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1),
 535 -                               5);
 536 +                               ar9485_modes_lowest_ob_db_tx_gain_1_1);
 537
 538                 /* Load PCIE SERDES settings from INI */
 539
 540                 /* Awake Setting */
 541
 542                 INIT_INI_ARRAY(&ah->iniPcieSerdes,
 543 -                               ar9485_1_1_pcie_phy_clkreq_disable_L1,
 544 -                               ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1),
 545 -                               2);
 546 +                               ar9485_1_1_pcie_phy_clkreq_disable_L1);
 547
 548                 /* Sleep Setting */
 549
 550                 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 551 -                               ar9485_1_1_pcie_phy_clkreq_disable_L1,
 552 -                               ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1),
 553 -                               2);
 554 +                               ar9485_1_1_pcie_phy_clkreq_disable_L1);
 555         } else if (AR_SREV_9462_20(ah)) {
 556
 557 -               INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
 558 -               INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core,
 559 -                               ARRAY_SIZE(ar9462_2p0_mac_core), 2);
 560 +               INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core);
 561                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 562 -                               ar9462_2p0_mac_postamble,
 563 -                               ARRAY_SIZE(ar9462_2p0_mac_postamble), 5);
 564 +                               ar9462_2p0_mac_postamble);
 565
 566 -               INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
 567                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 568 -                               ar9462_2p0_baseband_core,
 569 -                               ARRAY_SIZE(ar9462_2p0_baseband_core), 2);
 570 +                               ar9462_2p0_baseband_core);
 571                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 572 -                               ar9462_2p0_baseband_postamble,
 573 -                               ARRAY_SIZE(ar9462_2p0_baseband_postamble), 5);
 574 +                               ar9462_2p0_baseband_postamble);
 575
 576 -               INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
 577                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 578 -                               ar9462_2p0_radio_core,
 579 -                               ARRAY_SIZE(ar9462_2p0_radio_core), 2);
 580 +                               ar9462_2p0_radio_core);
 581                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 582 -                               ar9462_2p0_radio_postamble,
 583 -                               ARRAY_SIZE(ar9462_2p0_radio_postamble), 5);
 584 +                               ar9462_2p0_radio_postamble);
 585                 INIT_INI_ARRAY(&ah->ini_radio_post_sys2ant,
 586 -                               ar9462_2p0_radio_postamble_sys2ant,
 587 -                               ARRAY_SIZE(ar9462_2p0_radio_postamble_sys2ant),
 588 -                               5);
 589 +                               ar9462_2p0_radio_postamble_sys2ant);
 590
 591                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 592 -                               ar9462_2p0_soc_preamble,
 593 -                               ARRAY_SIZE(ar9462_2p0_soc_preamble), 2);
 594 -               INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
 595 +                               ar9462_2p0_soc_preamble);
 596                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 597 -                               ar9462_2p0_soc_postamble,
 598 -                               ARRAY_SIZE(ar9462_2p0_soc_postamble), 5);
 599 +                               ar9462_2p0_soc_postamble);
 600
 601                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 602 -                               ar9462_common_rx_gain_table_2p0,
 603 -                               ARRAY_SIZE(ar9462_common_rx_gain_table_2p0), 2);
 604 +                               ar9462_common_rx_gain_table_2p0);
 605
 606                 /* Awake -> Sleep Setting */
 607                 INIT_INI_ARRAY(&ah->iniPcieSerdes,
 608 -                               PCIE_PLL_ON_CREQ_DIS_L1_2P0,
 609 -                               ARRAY_SIZE(PCIE_PLL_ON_CREQ_DIS_L1_2P0),
 610 -                               2);
 611 +                               PCIE_PLL_ON_CREQ_DIS_L1_2P0);
 612                 /* Sleep -> Awake Setting */
 613                 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 614 -                               PCIE_PLL_ON_CREQ_DIS_L1_2P0,
 615 -                               ARRAY_SIZE(PCIE_PLL_ON_CREQ_DIS_L1_2P0),
 616 -                               2);
 617 +                               PCIE_PLL_ON_CREQ_DIS_L1_2P0);
 618
 619                 /* Fast clock modal settings */
 620                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 621 -                               ar9462_modes_fast_clock_2p0,
 622 -                               ARRAY_SIZE(ar9462_modes_fast_clock_2p0), 3);
 623 +                               ar9462_modes_fast_clock_2p0);
 624
 625                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 626 -                               AR9462_BB_CTX_COEFJ(2p0),
 627 -                               ARRAY_SIZE(AR9462_BB_CTX_COEFJ(2p0)), 2);
 628 +                               AR9462_BB_CTX_COEFJ(2p0));
 629
 630 -               INIT_INI_ARRAY(&ah->ini_japan2484, AR9462_BBC_TXIFR_COEFFJ,
 631 -                               ARRAY_SIZE(AR9462_BBC_TXIFR_COEFFJ), 2);
 632 +               INIT_INI_ARRAY(&ah->ini_japan2484, AR9462_BBC_TXIFR_COEFFJ);
 633         } else if (AR_SREV_9550(ah)) {
 634                 /* mac */
 635 -               INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
 636                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 637 -                               ar955x_1p0_mac_core,
 638 -                               ARRAY_SIZE(ar955x_1p0_mac_core), 2);
 639 +                               ar955x_1p0_mac_core);
 640                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 641 -                               ar955x_1p0_mac_postamble,
 642 -                               ARRAY_SIZE(ar955x_1p0_mac_postamble), 5);
 643 +                               ar955x_1p0_mac_postamble);
 644
 645                 /* bb */
 646 -               INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
 647                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 648 -                               ar955x_1p0_baseband_core,
 649 -                               ARRAY_SIZE(ar955x_1p0_baseband_core), 2);
 650 +                               ar955x_1p0_baseband_core);
 651                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 652 -                               ar955x_1p0_baseband_postamble,
 653 -                               ARRAY_SIZE(ar955x_1p0_baseband_postamble), 5);
 654 +                               ar955x_1p0_baseband_postamble);
 655
 656                 /* radio */
 657 -               INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
 658                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 659 -                               ar955x_1p0_radio_core,
 660 -                               ARRAY_SIZE(ar955x_1p0_radio_core), 2);
 661 +                               ar955x_1p0_radio_core);
 662                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 663 -                               ar955x_1p0_radio_postamble,
 664 -                               ARRAY_SIZE(ar955x_1p0_radio_postamble), 5);
 665 +                               ar955x_1p0_radio_postamble);
 666
 667                 /* soc */
 668                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 669 -                               ar955x_1p0_soc_preamble,
 670 -                               ARRAY_SIZE(ar955x_1p0_soc_preamble), 2);
 671 -               INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
 672 +                               ar955x_1p0_soc_preamble);
 673                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 674 -                               ar955x_1p0_soc_postamble,
 675 -                               ARRAY_SIZE(ar955x_1p0_soc_postamble), 5);
 676 +                               ar955x_1p0_soc_postamble);
 677
 678                 /* rx/tx gain */
 679                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 680 -                       ar955x_1p0_common_wo_xlna_rx_gain_table,
 681 -                       ARRAY_SIZE(ar955x_1p0_common_wo_xlna_rx_gain_table),
 682 -                       2);
 683 +                       ar955x_1p0_common_wo_xlna_rx_gain_table);
 684                 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
 685 -                       ar955x_1p0_common_wo_xlna_rx_gain_bounds,
 686 -                       ARRAY_SIZE(ar955x_1p0_common_wo_xlna_rx_gain_bounds),
 687 -                       5);
 688 -               INIT_INI_ARRAY(&ah->iniModesTxGain,
 689 -                               ar955x_1p0_modes_xpa_tx_gain_table,
 690 -                               ARRAY_SIZE(ar955x_1p0_modes_xpa_tx_gain_table),
 691 -                               9);
 692 +                       ar955x_1p0_common_wo_xlna_rx_gain_bounds);
 693 +               INIT_INI_ARRAY(&ah->iniModesTxGain,
 694 +                               ar955x_1p0_modes_xpa_tx_gain_table);
 695
 696                 /* Fast clock modal settings */
 697                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 698 -                               ar955x_1p0_modes_fast_clock,
 699 -                               ARRAY_SIZE(ar955x_1p0_modes_fast_clock), 3);
 700 +                               ar955x_1p0_modes_fast_clock);
 701         } else if (AR_SREV_9580(ah)) {
 702                 /* mac */
 703 -               INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
 704                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 705 -                               ar9580_1p0_mac_core,
 706 -                               ARRAY_SIZE(ar9580_1p0_mac_core), 2);
 707 +                               ar9580_1p0_mac_core);
 708                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 709 -                               ar9580_1p0_mac_postamble,
 710 -                               ARRAY_SIZE(ar9580_1p0_mac_postamble), 5);
 711 +                               ar9580_1p0_mac_postamble);
 712
 713                 /* bb */
 714 -               INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
 715                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 716 -                               ar9580_1p0_baseband_core,
 717 -                               ARRAY_SIZE(ar9580_1p0_baseband_core), 2);
 718 +                               ar9580_1p0_baseband_core);
 719                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 720 -                               ar9580_1p0_baseband_postamble,
 721 -                               ARRAY_SIZE(ar9580_1p0_baseband_postamble), 5);
 722 +                               ar9580_1p0_baseband_postamble);
 723
 724                 /* radio */
 725 -               INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
 726                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 727 -                               ar9580_1p0_radio_core,
 728 -                               ARRAY_SIZE(ar9580_1p0_radio_core), 2);
 729 +                               ar9580_1p0_radio_core);
 730                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 731 -                               ar9580_1p0_radio_postamble,
 732 -                               ARRAY_SIZE(ar9580_1p0_radio_postamble), 5);
 733 +                               ar9580_1p0_radio_postamble);
 734
 735                 /* soc */
 736                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 737 -                               ar9580_1p0_soc_preamble,
 738 -                               ARRAY_SIZE(ar9580_1p0_soc_preamble), 2);
 739 -               INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
 740 +                               ar9580_1p0_soc_preamble);
 741                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 742 -                               ar9580_1p0_soc_postamble,
 743 -                               ARRAY_SIZE(ar9580_1p0_soc_postamble), 5);
 744 +                               ar9580_1p0_soc_postamble);
 745
 746                 /* rx/tx gain */
 747                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 748 -                               ar9580_1p0_rx_gain_table,
 749 -                               ARRAY_SIZE(ar9580_1p0_rx_gain_table), 2);
 750 +                               ar9580_1p0_rx_gain_table);
 751                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 752 -                               ar9580_1p0_low_ob_db_tx_gain_table,
 753 -                               ARRAY_SIZE(ar9580_1p0_low_ob_db_tx_gain_table),
 754 -                               5);
 755 +                               ar9580_1p0_low_ob_db_tx_gain_table);
 756
 757                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 758 -                               ar9580_1p0_modes_fast_clock,
 759 -                               ARRAY_SIZE(ar9580_1p0_modes_fast_clock),
 760 -                               3);
 761 +                               ar9580_1p0_modes_fast_clock);
 762         } else {
 763                 /* mac */
 764 -               INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
 765                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 766 -                               ar9300_2p2_mac_core,
 767 -                               ARRAY_SIZE(ar9300_2p2_mac_core), 2);
 768 +                               ar9300_2p2_mac_core);
 769                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 770 -                               ar9300_2p2_mac_postamble,
 771 -                               ARRAY_SIZE(ar9300_2p2_mac_postamble), 5);
 772 +                               ar9300_2p2_mac_postamble);
 773
 774                 /* bb */
 775 -               INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
 776                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 777 -                               ar9300_2p2_baseband_core,
 778 -                               ARRAY_SIZE(ar9300_2p2_baseband_core), 2);
 779 +                               ar9300_2p2_baseband_core);
 780                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 781 -                               ar9300_2p2_baseband_postamble,
 782 -                               ARRAY_SIZE(ar9300_2p2_baseband_postamble), 5);
 783 +                               ar9300_2p2_baseband_postamble);
 784
 785                 /* radio */
 786 -               INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
 787                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 788 -                               ar9300_2p2_radio_core,
 789 -                               ARRAY_SIZE(ar9300_2p2_radio_core), 2);
 790 +                               ar9300_2p2_radio_core);
 791                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 792 -                               ar9300_2p2_radio_postamble,
 793 -                               ARRAY_SIZE(ar9300_2p2_radio_postamble), 5);
 794 +                               ar9300_2p2_radio_postamble);
 795
 796                 /* soc */
 797                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 798 -                               ar9300_2p2_soc_preamble,
 799 -                               ARRAY_SIZE(ar9300_2p2_soc_preamble), 2);
 800 -               INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
 801 +                               ar9300_2p2_soc_preamble);
 802                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 803 -                               ar9300_2p2_soc_postamble,
 804 -                               ARRAY_SIZE(ar9300_2p2_soc_postamble), 5);
 805 +                               ar9300_2p2_soc_postamble);
 806
 807                 /* rx/tx gain */
 808                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 809 -                               ar9300Common_rx_gain_table_2p2,
 810 -                               ARRAY_SIZE(ar9300Common_rx_gain_table_2p2), 2);
 811 +                               ar9300Common_rx_gain_table_2p2);
 812                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 813 -                               ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
 814 -                               ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
 815 -                               5);
 816 +                               ar9300Modes_lowest_ob_db_tx_gain_table_2p2);
 817
 818                 /* Load PCIE SERDES settings from INI */
 819
 820                 /* Awake Setting */
 821
 822                 INIT_INI_ARRAY(&ah->iniPcieSerdes,
 823 -                               ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,
 824 -                               ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
 825 -                               2);
 826 +                               ar9300PciePhy_pll_on_clkreq_disable_L1_2p2);
 827
 828                 /* Sleep Setting */
 829
 830                 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 831 -                               ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,
 832 -                               ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
 833 -                               2);
 834 +                               ar9300PciePhy_pll_on_clkreq_disable_L1_2p2);
 835
 836                 /* Fast clock modal settings */
 837                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 838 -                               ar9300Modes_fast_clock_2p2,
 839 -                               ARRAY_SIZE(ar9300Modes_fast_clock_2p2),
 840 -                               3);
 841 +                               ar9300Modes_fast_clock_2p2);
 842         }
 843  }
 844
 845 @@ -507,170 +355,110 @@ static void ar9003_tx_gain_table_mode0(s
 846  {
 847         if (AR_SREV_9330_12(ah))
 848                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 849 -                       ar9331_modes_lowest_ob_db_tx_gain_1p2,
 850 -                       ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p2),
 851 -                       5);
 852 +                       ar9331_modes_lowest_ob_db_tx_gain_1p2);
 853         else if (AR_SREV_9330_11(ah))
 854                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 855 -                       ar9331_modes_lowest_ob_db_tx_gain_1p1,
 856 -                       ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p1),
 857 -                       5);
 858 +                       ar9331_modes_lowest_ob_db_tx_gain_1p1);
 859         else if (AR_SREV_9340(ah))
 860                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 861 -                       ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
 862 -                       ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
 863 -                       5);
 864 +                       ar9340Modes_lowest_ob_db_tx_gain_table_1p0);
 865         else if (AR_SREV_9485_11(ah))
 866                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 867 -                       ar9485_modes_lowest_ob_db_tx_gain_1_1,
 868 -                       ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1),
 869 -                       5);
 870 +                       ar9485_modes_lowest_ob_db_tx_gain_1_1);
 871         else if (AR_SREV_9550(ah))
 872                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 873 -                       ar955x_1p0_modes_xpa_tx_gain_table,
 874 -                       ARRAY_SIZE(ar955x_1p0_modes_xpa_tx_gain_table),
 875 -                       9);
 876 +                       ar955x_1p0_modes_xpa_tx_gain_table);
 877         else if (AR_SREV_9580(ah))
 878                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 879 -                       ar9580_1p0_lowest_ob_db_tx_gain_table,
 880 -                       ARRAY_SIZE(ar9580_1p0_lowest_ob_db_tx_gain_table),
 881 -                       5);
 882 +                       ar9580_1p0_lowest_ob_db_tx_gain_table);
 883         else if (AR_SREV_9462_20(ah))
 884                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 885 -                       ar9462_modes_low_ob_db_tx_gain_table_2p0,
 886 -                       ARRAY_SIZE(ar9462_modes_low_ob_db_tx_gain_table_2p0),
 887 -                       5);
 888 +                       ar9462_modes_low_ob_db_tx_gain_table_2p0);
 889         else
 890                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 891 -                       ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
 892 -                       ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
 893 -                       5);
 894 +                       ar9300Modes_lowest_ob_db_tx_gain_table_2p2);
 895  }
 896
 897  static void ar9003_tx_gain_table_mode1(struct ath_hw *ah)
 898  {
 899         if (AR_SREV_9330_12(ah))
 900                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 901 -                       ar9331_modes_high_ob_db_tx_gain_1p2,
 902 -                       ARRAY_SIZE(ar9331_modes_high_ob_db_tx_gain_1p2),
 903 -                       5);
 904 +                       ar9331_modes_high_ob_db_tx_gain_1p2);
 905         else if (AR_SREV_9330_11(ah))
 906                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 907 -                       ar9331_modes_high_ob_db_tx_gain_1p1,
 908 -                       ARRAY_SIZE(ar9331_modes_high_ob_db_tx_gain_1p1),
 909 -                       5);
 910 +                       ar9331_modes_high_ob_db_tx_gain_1p1);
 911         else if (AR_SREV_9340(ah))
 912                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 913 -                       ar9340Modes_high_ob_db_tx_gain_table_1p0,
 914 -                       ARRAY_SIZE(ar9340Modes_high_ob_db_tx_gain_table_1p0),
 915 -                       5);
 916 +                       ar9340Modes_high_ob_db_tx_gain_table_1p0);
 917         else if (AR_SREV_9485_11(ah))
 918                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 919 -                       ar9485Modes_high_ob_db_tx_gain_1_1,
 920 -                       ARRAY_SIZE(ar9485Modes_high_ob_db_tx_gain_1_1),
 921 -                       5);
 922 +                       ar9485Modes_high_ob_db_tx_gain_1_1);
 923         else if (AR_SREV_9580(ah))
 924                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 925 -                       ar9580_1p0_high_ob_db_tx_gain_table,
 926 -                       ARRAY_SIZE(ar9580_1p0_high_ob_db_tx_gain_table),
 927 -                       5);
 928 +                       ar9580_1p0_high_ob_db_tx_gain_table);
 929         else if (AR_SREV_9550(ah))
 930                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 931 -                       ar955x_1p0_modes_no_xpa_tx_gain_table,
 932 -                       ARRAY_SIZE(ar955x_1p0_modes_no_xpa_tx_gain_table),
 933 -                       9);
 934 +                       ar955x_1p0_modes_no_xpa_tx_gain_table);
 935         else if (AR_SREV_9462_20(ah))
 936                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 937 -                       ar9462_modes_high_ob_db_tx_gain_table_2p0,
 938 -                       ARRAY_SIZE(ar9462_modes_high_ob_db_tx_gain_table_2p0),
 939 -                       5);
 940 +                       ar9462_modes_high_ob_db_tx_gain_table_2p0);
 941         else
 942                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 943 -                       ar9300Modes_high_ob_db_tx_gain_table_2p2,
 944 -                       ARRAY_SIZE(ar9300Modes_high_ob_db_tx_gain_table_2p2),
 945 -                       5);
 946 +                       ar9300Modes_high_ob_db_tx_gain_table_2p2);
 947  }
 948
 949  static void ar9003_tx_gain_table_mode2(struct ath_hw *ah)
 950  {
 951         if (AR_SREV_9330_12(ah))
 952                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 953 -                       ar9331_modes_low_ob_db_tx_gain_1p2,
 954 -                       ARRAY_SIZE(ar9331_modes_low_ob_db_tx_gain_1p2),
 955 -                       5);
 956 +                       ar9331_modes_low_ob_db_tx_gain_1p2);
 957         else if (AR_SREV_9330_11(ah))
 958                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 959 -                       ar9331_modes_low_ob_db_tx_gain_1p1,
 960 -                       ARRAY_SIZE(ar9331_modes_low_ob_db_tx_gain_1p1),
 961 -                       5);
 962 +                       ar9331_modes_low_ob_db_tx_gain_1p1);
 963         else if (AR_SREV_9340(ah))
 964                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 965 -                       ar9340Modes_low_ob_db_tx_gain_table_1p0,
 966 -                       ARRAY_SIZE(ar9340Modes_low_ob_db_tx_gain_table_1p0),
 967 -                       5);
 968 +                       ar9340Modes_low_ob_db_tx_gain_table_1p0);
 969         else if (AR_SREV_9485_11(ah))
 970                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 971 -                       ar9485Modes_low_ob_db_tx_gain_1_1,
 972 -                       ARRAY_SIZE(ar9485Modes_low_ob_db_tx_gain_1_1),
 973 -                       5);
 974 +                       ar9485Modes_low_ob_db_tx_gain_1_1);
 975         else if (AR_SREV_9580(ah))
 976                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 977 -                       ar9580_1p0_low_ob_db_tx_gain_table,
 978 -                       ARRAY_SIZE(ar9580_1p0_low_ob_db_tx_gain_table),
 979 -                       5);
 980 +                       ar9580_1p0_low_ob_db_tx_gain_table);
 981         else
 982                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 983 -                       ar9300Modes_low_ob_db_tx_gain_table_2p2,
 984 -                       ARRAY_SIZE(ar9300Modes_low_ob_db_tx_gain_table_2p2),
 985 -                       5);
 986 +                       ar9300Modes_low_ob_db_tx_gain_table_2p2);
 987  }
 988
 989  static void ar9003_tx_gain_table_mode3(struct ath_hw *ah)
 990  {
 991         if (AR_SREV_9330_12(ah))
 992                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 993 -                       ar9331_modes_high_power_tx_gain_1p2,
 994 -                       ARRAY_SIZE(ar9331_modes_high_power_tx_gain_1p2),
 995 -                       5);
 996 +                       ar9331_modes_high_power_tx_gain_1p2);
 997         else if (AR_SREV_9330_11(ah))
 998                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 999 -                       ar9331_modes_high_power_tx_gain_1p1,
1000 -                       ARRAY_SIZE(ar9331_modes_high_power_tx_gain_1p1),
1001 -                       5);
1002 +                       ar9331_modes_high_power_tx_gain_1p1);
1003         else if (AR_SREV_9340(ah))
1004                 INIT_INI_ARRAY(&ah->iniModesTxGain,
1005 -                       ar9340Modes_high_power_tx_gain_table_1p0,
1006 -                       ARRAY_SIZE(ar9340Modes_high_power_tx_gain_table_1p0),
1007 -                       5);
1008 +                       ar9340Modes_high_power_tx_gain_table_1p0);
1009         else if (AR_SREV_9485_11(ah))
1010                 INIT_INI_ARRAY(&ah->iniModesTxGain,
1011 -                       ar9485Modes_high_power_tx_gain_1_1,
1012 -                       ARRAY_SIZE(ar9485Modes_high_power_tx_gain_1_1),
1013 -                       5);
1014 +                       ar9485Modes_high_power_tx_gain_1_1);
1015         else if (AR_SREV_9580(ah))
1016                 INIT_INI_ARRAY(&ah->iniModesTxGain,
1017 -                       ar9580_1p0_high_power_tx_gain_table,
1018 -                       ARRAY_SIZE(ar9580_1p0_high_power_tx_gain_table),
1019 -                       5);
1020 +                       ar9580_1p0_high_power_tx_gain_table);
1021         else
1022                 INIT_INI_ARRAY(&ah->iniModesTxGain,
1023 -                       ar9300Modes_high_power_tx_gain_table_2p2,
1024 -                       ARRAY_SIZE(ar9300Modes_high_power_tx_gain_table_2p2),
1025 -                       5);
1026 +                       ar9300Modes_high_power_tx_gain_table_2p2);
1027  }
1028
1029  static void ar9003_tx_gain_table_mode4(struct ath_hw *ah)
1030  {
1031         if (AR_SREV_9340(ah))
1032                 INIT_INI_ARRAY(&ah->iniModesTxGain,
1033 -                       ar9340Modes_mixed_ob_db_tx_gain_table_1p0,
1034 -                       ARRAY_SIZE(ar9340Modes_mixed_ob_db_tx_gain_table_1p0),
1035 -                       5);
1036 +                       ar9340Modes_mixed_ob_db_tx_gain_table_1p0);
1037         else if (AR_SREV_9580(ah))
1038                 INIT_INI_ARRAY(&ah->iniModesTxGain,
1039 -                       ar9580_1p0_mixed_ob_db_tx_gain_table,
1040 -                       ARRAY_SIZE(ar9580_1p0_mixed_ob_db_tx_gain_table),
1041 -                       5);
1042 +                       ar9580_1p0_mixed_ob_db_tx_gain_table);
1043  }
1044
1045  static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
1046 @@ -699,104 +487,67 @@ static void ar9003_rx_gain_table_mode0(s
1047  {
1048         if (AR_SREV_9330_12(ah))
1049                 INIT_INI_ARRAY(&ah->iniModesRxGain,
1050 -                               ar9331_common_rx_gain_1p2,
1051 -                               ARRAY_SIZE(ar9331_common_rx_gain_1p2),
1052 -                               2);
1053 +                               ar9331_common_rx_gain_1p2);
1054         else if (AR_SREV_9330_11(ah))
1055                 INIT_INI_ARRAY(&ah->iniModesRxGain,
1056 -                               ar9331_common_rx_gain_1p1,
1057 -                               ARRAY_SIZE(ar9331_common_rx_gain_1p1),
1058 -                               2);
1059 +                               ar9331_common_rx_gain_1p1);
1060         else if (AR_SREV_9340(ah))
1061                 INIT_INI_ARRAY(&ah->iniModesRxGain,
1062 -                               ar9340Common_rx_gain_table_1p0,
1063 -                               ARRAY_SIZE(ar9340Common_rx_gain_table_1p0),
1064 -                               2);
1065 +                               ar9340Common_rx_gain_table_1p0);
1066         else if (AR_SREV_9485_11(ah))
1067                 INIT_INI_ARRAY(&ah->iniModesRxGain,
1068 -                               ar9485Common_wo_xlna_rx_gain_1_1,
1069 -                               ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
1070 -                               2);
1071 +                               ar9485Common_wo_xlna_rx_gain_1_1);
1072         else if (AR_SREV_9550(ah)) {
1073                 INIT_INI_ARRAY(&ah->iniModesRxGain,
1074 -                               ar955x_1p0_common_rx_gain_table,
1075 -                               ARRAY_SIZE(ar955x_1p0_common_rx_gain_table),
1076 -                               2);
1077 +                               ar955x_1p0_common_rx_gain_table);
1078                 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
1079 -                               ar955x_1p0_common_rx_gain_bounds,
1080 -                               ARRAY_SIZE(ar955x_1p0_common_rx_gain_bounds),
1081 -                               5);
1082 +                               ar955x_1p0_common_rx_gain_bounds);
1083         } else if (AR_SREV_9580(ah))
1084                 INIT_INI_ARRAY(&ah->iniModesRxGain,
1085 -                               ar9580_1p0_rx_gain_table,
1086 -                               ARRAY_SIZE(ar9580_1p0_rx_gain_table),
1087 -                               2);
1088 +                               ar9580_1p0_rx_gain_table);
1089         else if (AR_SREV_9462_20(ah))
1090                 INIT_INI_ARRAY(&ah->iniModesRxGain,
1091 -                               ar9462_common_rx_gain_table_2p0,
1092 -                               ARRAY_SIZE(ar9462_common_rx_gain_table_2p0),
1093 -                               2);
1094 +                               ar9462_common_rx_gain_table_2p0);
1095         else
1096                 INIT_INI_ARRAY(&ah->iniModesRxGain,
1097 -                               ar9300Common_rx_gain_table_2p2,
1098 -                               ARRAY_SIZE(ar9300Common_rx_gain_table_2p2),
1099 -                               2);
1100 +                               ar9300Common_rx_gain_table_2p2);
1101  }
1102
1103  static void ar9003_rx_gain_table_mode1(struct ath_hw *ah)
1104  {
1105         if (AR_SREV_9330_12(ah))
1106                 INIT_INI_ARRAY(&ah->iniModesRxGain,
1107 -                       ar9331_common_wo_xlna_rx_gain_1p2,
1108 -                       ARRAY_SIZE(ar9331_common_wo_xlna_rx_gain_1p2),
1109 -                       2);
1110 +                       ar9331_common_wo_xlna_rx_gain_1p2);
1111         else if (AR_SREV_9330_11(ah))
1112                 INIT_INI_ARRAY(&ah->iniModesRxGain,
1113 -                       ar9331_common_wo_xlna_rx_gain_1p1,
1114 -                       ARRAY_SIZE(ar9331_common_wo_xlna_rx_gain_1p1),
1115 -                       2);
1116 +                       ar9331_common_wo_xlna_rx_gain_1p1);
1117         else if (AR_SREV_9340(ah))
1118                 INIT_INI_ARRAY(&ah->iniModesRxGain,
1119 -                       ar9340Common_wo_xlna_rx_gain_table_1p0,
1120 -                       ARRAY_SIZE(ar9340Common_wo_xlna_rx_gain_table_1p0),
1121 -                       2);
1122 +                       ar9340Common_wo_xlna_rx_gain_table_1p0);
1123         else if (AR_SREV_9485_11(ah))
1124                 INIT_INI_ARRAY(&ah->iniModesRxGain,
1125 -                       ar9485Common_wo_xlna_rx_gain_1_1,
1126 -                       ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
1127 -                       2);
1128 +                       ar9485Common_wo_xlna_rx_gain_1_1);
1129         else if (AR_SREV_9462_20(ah))
1130                 INIT_INI_ARRAY(&ah->iniModesRxGain,
1131 -                       ar9462_common_wo_xlna_rx_gain_table_2p0,
1132 -                       ARRAY_SIZE(ar9462_common_wo_xlna_rx_gain_table_2p0),
1133 -                       2);
1134 +                       ar9462_common_wo_xlna_rx_gain_table_2p0);
1135         else if (AR_SREV_9550(ah)) {
1136                 INIT_INI_ARRAY(&ah->iniModesRxGain,
1137 -                       ar955x_1p0_common_wo_xlna_rx_gain_table,
1138 -                       ARRAY_SIZE(ar955x_1p0_common_wo_xlna_rx_gain_table),
1139 -                       2);
1140 +                       ar955x_1p0_common_wo_xlna_rx_gain_table);
1141                 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
1142 -                       ar955x_1p0_common_wo_xlna_rx_gain_bounds,
1143 -                       ARRAY_SIZE(ar955x_1p0_common_wo_xlna_rx_gain_bounds),
1144 -                       5);
1145 +                       ar955x_1p0_common_wo_xlna_rx_gain_bounds);
1146         } else if (AR_SREV_9580(ah))
1147                 INIT_INI_ARRAY(&ah->iniModesRxGain,
1148 -                       ar9580_1p0_wo_xlna_rx_gain_table,
1149 -                       ARRAY_SIZE(ar9580_1p0_wo_xlna_rx_gain_table),
1150 -                       2);
1151 +                       ar9580_1p0_wo_xlna_rx_gain_table);
1152         else
1153                 INIT_INI_ARRAY(&ah->iniModesRxGain,
1154 -                       ar9300Common_wo_xlna_rx_gain_table_2p2,
1155 -                       ARRAY_SIZE(ar9300Common_wo_xlna_rx_gain_table_2p2),
1156 -                       2);
1157 +                       ar9300Common_wo_xlna_rx_gain_table_2p2);
1158  }
1159
1160  static void ar9003_rx_gain_table_mode2(struct ath_hw *ah)
1161  {
1162         if (AR_SREV_9462_20(ah))
1163                 INIT_INI_ARRAY(&ah->iniModesRxGain,
1164 -                              ar9462_common_mixed_rx_gain_table_2p0,
1165 -                              ARRAY_SIZE(ar9462_common_mixed_rx_gain_table_2p0), 2);
1166 +                              ar9462_common_mixed_rx_gain_table_2p0);
1167  }
1168
1169  static void ar9003_rx_gain_table_apply(struct ath_hw *ah)