package/mac80211/patches/548-ath9k-add-AR9330-specific-PLL-initialization.patch

   1 diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
   2 index ade8655..826ed5d 100644
   3 --- a/drivers/net/wireless/ath/ath9k/hw.c
   4 +++ b/drivers/net/wireless/ath/ath9k/hw.c
   5 @@ -733,6 +733,39 @@ static void ath9k_hw_init_pll(struct ath_hw *ah,
   6                 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
   7                               AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
   8                 udelay(1000);
   9 +       } else if (AR_SREV_9330(ah)) {
  10 +               u32 ddr_dpll2, pll_control2, kd;
  11 +
  12 +               if (ah->is_clk_25mhz) {
  13 +                       ddr_dpll2 = 0x18e82f01;
  14 +                       pll_control2 = 0xe04a3d;
  15 +                       kd = 0x1d;
  16 +               } else {
  17 +                       ddr_dpll2 = 0x19e82f01;
  18 +                       pll_control2 = 0x886666;
  19 +                       kd = 0x3d;
  20 +               }
  21 +
  22 +               /* program DDR PLL ki and kd value */
  23 +               REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);
  24 +
  25 +               /* program DDR PLL phase_shift */
  26 +               REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
  27 +                             AR_CH0_DPLL3_PHASE_SHIFT, 0x1);
  28 +
  29 +               REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
  30 +               udelay(1000);
  31 +
  32 +               /* program refdiv, nint, frac to RTC register */
  33 +               REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);
  34 +
  35 +               /* program BB PLL kd and ki value */
  36 +               REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd);
  37 +               REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06);
  38 +
  39 +               /* program BB PLL phase_shift */
  40 +               REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
  41 +                             AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
  42         } else if (AR_SREV_9340(ah)) {
  43                 u32 regval, pll2_divint, pll2_divfrac, refdiv;
  44
  45 @@ -774,7 +807,7 @@ static void ath9k_hw_init_pll(struct ath_hw *ah,
  46
  47         REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
  48
  49 -       if (AR_SREV_9485(ah) || AR_SREV_9340(ah))
  50 +       if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah))
  51                 udelay(1000);
  52
  53         /* Switch the core clock for ar9271 to 117Mhz */
  54