package/mac80211/patches/310-rt2800_experimental.patch

   1 automatically generated from wireless-testing..rt2x00/experimental
   2 do not edit
   3
   4 --- a/drivers/net/wireless/rt2x00/Makefile
   5 +++ b/drivers/net/wireless/rt2x00/Makefile
   6 @@ -14,5 +14,7 @@ obj-$(CONFIG_RT2X00_LIB_USB)          += rt2x00u
   7  obj-$(CONFIG_RT2400PCI)                        += rt2400pci.o
   8  obj-$(CONFIG_RT2500PCI)                        += rt2500pci.o
   9  obj-$(CONFIG_RT61PCI)                  += rt61pci.o
  10 +obj-$(CONFIG_RT2800PCI)                        += rt2800pci.o
  11  obj-$(CONFIG_RT2500USB)                        += rt2500usb.o
  12  obj-$(CONFIG_RT73USB)                  += rt73usb.o
  13 +obj-$(CONFIG_RT2800USB)                        += rt2800usb.o
  14 --- a/drivers/net/wireless/rt2x00/rt2500usb.c
  15 +++ b/drivers/net/wireless/rt2x00/rt2500usb.c
  16 @@ -36,6 +36,13 @@
  17  #include "rt2500usb.h"
  18
  19  /*
  20 + * Allow hardware encryption to be disabled.
  21 + */
  22 +static int modparam_nohwcrypt = 0;
  23 +module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
  24 +MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  25 +
  26 +/*
  27   * Register access.
  28   * All access to the CSR registers will go through the methods
  29   * rt2500usb_register_read and rt2500usb_register_write.
  30 @@ -343,6 +350,85 @@ static void rt2500usb_init_led(struct rt
  31  /*
  32   * Configuration handlers.
  33   */
  34 +
  35 +/*
  36 + * rt2500usb does not differentiate between shared and pairwise
  37 + * keys, so we should use the same function for both key types.
  38 + */
  39 +static int rt2500usb_config_key(struct rt2x00_dev *rt2x00dev,
  40 +                               struct rt2x00lib_crypto *crypto,
  41 +                               struct ieee80211_key_conf *key)
  42 +{
  43 +       int timeout;
  44 +       u32 mask;
  45 +       u16 reg;
  46 +
  47 +       /* Support up to 4 keys */
  48 +       if (key->hw_key_idx >= 4)
  49 +               return -ENOSPC;
  50 +
  51 +       if (crypto->cmd == SET_KEY) {
  52 +               /*
  53 +                * Pairwise key will always be entry 0, but this
  54 +                * could collide with a shared key on the same
  55 +                * position...
  56 +                */
  57 +               mask = TXRX_CSR0_KEY_ID.bit_mask;
  58 +
  59 +               rt2500usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
  60 +
  61 +               if ((reg & mask) && (reg & mask) == mask)
  62 +                       return -ENOSPC;
  63 +
  64 +               reg = rt2x00_get_field16(reg, TXRX_CSR0_KEY_ID);
  65 +
  66 +               key->hw_key_idx += reg ? ffz(reg) : 0;
  67 +
  68 +               /*
  69 +                * The encryption key doesn't fit within the CSR cache,
  70 +                * this means we should allocate it seperately and use
  71 +                * rt2x00usb_vendor_request() to send the key to the hardware.
  72 +                */
  73 +               reg = KEY_ENTRY(key->hw_key_idx);
  74 +               timeout = REGISTER_TIMEOUT32(sizeof(crypto->key));
  75 +               rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
  76 +                                                   USB_VENDOR_REQUEST_OUT, reg,
  77 +                                                   crypto->key,
  78 +                                                   sizeof(crypto->key),
  79 +                                                   timeout);
  80 +
  81 +               /*
  82 +                * The driver does not support the IV/EIV generation
  83 +                * in hardware. However it doesn't support the IV/EIV
  84 +                * inside the ieee80211 frame either, but requires it
  85 +                * to be provided seperately for the descriptor.
  86 +                * rt2x00lib will cut the IV/EIV data out of all frames
  87 +                * given to us by mac80211, but we must tell mac80211
  88 +                * to generate the IV/EIV data.
  89 +                */
  90 +               key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  91 +               key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
  92 +       }
  93 +
  94 +       /*
  95 +        * TXRX_CSR0_KEY_ID contains only single-bit fields to indicate
  96 +        * a particular key is valid.
  97 +        */
  98 +       rt2500usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
  99 +       rt2x00_set_field16(&reg, TXRX_CSR0_ALGORITHM, crypto->cipher);
 100 +       rt2x00_set_field16(&reg, TXRX_CSR0_IV_OFFSET, IEEE80211_HEADER);
 101 +
 102 +       mask = rt2x00_get_field16(reg, TXRX_CSR0_KEY_ID);
 103 +       if (crypto->cmd == SET_KEY)
 104 +               mask |= 1 << key->hw_key_idx;
 105 +       else if (crypto->cmd == DISABLE_KEY)
 106 +               mask &= ~(1 << key->hw_key_idx);
 107 +       rt2x00_set_field16(&reg, TXRX_CSR0_KEY_ID, mask);
 108 +       rt2500usb_register_write(rt2x00dev, TXRX_CSR0, reg);
 109 +
 110 +       return 0;
 111 +}
 112 +
 113  static void rt2500usb_config_filter(struct rt2x00_dev *rt2x00dev,
 114                                     const unsigned int filter_flags)
 115  {
 116 @@ -864,7 +950,7 @@ static int rt2500usb_init_registers(stru
 117
 118         rt2500usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
 119         rt2x00_set_field16(&reg, TXRX_CSR0_IV_OFFSET, IEEE80211_HEADER);
 120 -       rt2x00_set_field16(&reg, TXRX_CSR0_KEY_ID, 0xff);
 121 +       rt2x00_set_field16(&reg, TXRX_CSR0_KEY_ID, 0);
 122         rt2500usb_register_write(rt2x00dev, TXRX_CSR0, reg);
 123
 124         rt2500usb_register_read(rt2x00dev, MAC_CSR18, &reg);
 125 @@ -1086,7 +1172,7 @@ static void rt2500usb_write_tx_desc(stru
 126          * Start writing the descriptor words.
 127          */
 128         rt2x00_desc_read(txd, 1, &word);
 129 -       rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
 130 +       rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
 131         rt2x00_set_field32(&word, TXD_W1_AIFS, txdesc->aifs);
 132         rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
 133         rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
 134 @@ -1099,6 +1185,11 @@ static void rt2500usb_write_tx_desc(stru
 135         rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
 136         rt2x00_desc_write(txd, 2, word);
 137
 138 +       if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
 139 +               _rt2x00_desc_write(txd, 3, skbdesc->iv);
 140 +               _rt2x00_desc_write(txd, 4, skbdesc->eiv);
 141 +       }
 142 +
 143         rt2x00_desc_read(txd, 0, &word);
 144         rt2x00_set_field32(&word, TXD_W0_RETRY_LIMIT, txdesc->retry_limit);
 145         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
 146 @@ -1113,7 +1204,8 @@ static void rt2500usb_write_tx_desc(stru
 147                            test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags));
 148         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
 149         rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skb->len);
 150 -       rt2x00_set_field32(&word, TXD_W0_CIPHER, CIPHER_NONE);
 151 +       rt2x00_set_field32(&word, TXD_W0_CIPHER, txdesc->cipher);
 152 +       rt2x00_set_field32(&word, TXD_W0_KEY_ID, txdesc->key_idx);
 153         rt2x00_desc_write(txd, 0, word);
 154  }
 155
 156 @@ -1225,6 +1317,7 @@ static void rt2500usb_kick_tx_queue(stru
 157  static void rt2500usb_fill_rxdone(struct queue_entry *entry,
 158                                   struct rxdone_entry_desc *rxdesc)
 159  {
 160 +       struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 161         struct queue_entry_priv_usb *entry_priv = entry->priv_data;
 162         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 163         __le32 *rxd =
 164 @@ -1252,6 +1345,31 @@ static void rt2500usb_fill_rxdone(struct
 165         if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
 166                 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
 167
 168 +       if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
 169 +               rxdesc->cipher = rt2x00_get_field32(word0, RXD_W0_CIPHER);
 170 +               if (rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR))
 171 +                       rxdesc->cipher_status = RX_CRYPTO_FAIL_KEY;
 172 +       }
 173 +
 174 +       if (rxdesc->cipher != CIPHER_NONE) {
 175 +               _rt2x00_desc_read(rxd, 2, &rxdesc->iv);
 176 +               _rt2x00_desc_read(rxd, 3, &rxdesc->eiv);
 177 +               /* ICV is located at the end of frame */
 178 +
 179 +               /*
 180 +                * Hardware has stripped IV/EIV data from 802.11 frame during
 181 +                * decryption. It has provided the data seperately but rt2x00lib
 182 +                * should decide if it should be reinserted.
 183 +                */
 184 +               rxdesc->flags |= RX_FLAG_IV_STRIPPED;
 185 +               if (rxdesc->cipher != CIPHER_TKIP)
 186 +                       rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
 187 +               if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
 188 +                       rxdesc->flags |= RX_FLAG_DECRYPTED;
 189 +               else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
 190 +                       rxdesc->flags |= RX_FLAG_MMIC_ERROR;
 191 +       }
 192 +
 193         /*
 194          * Obtain the status about this packet.
 195          * When frame was received with an OFDM bitrate,
 196 @@ -1259,8 +1377,8 @@ static void rt2500usb_fill_rxdone(struct
 197          * a CCK bitrate the signal is the rate in 100kbit/s.
 198          */
 199         rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
 200 -       rxdesc->rssi = rt2x00_get_field32(word1, RXD_W1_RSSI) -
 201 -           entry->queue->rt2x00dev->rssi_offset;
 202 +       rxdesc->rssi =
 203 +           rt2x00_get_field32(word1, RXD_W1_RSSI) - rt2x00dev->rssi_offset;
 204         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
 205
 206         if (rt2x00_get_field32(word0, RXD_W0_OFDM))
 207 @@ -1750,6 +1868,8 @@ static int rt2500usb_probe_hw(struct rt2
 208         __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
 209         __set_bit(DRIVER_REQUIRE_BEACON_GUARD, &rt2x00dev->flags);
 210         __set_bit(DRIVER_REQUIRE_SCHEDULED, &rt2x00dev->flags);
 211 +       if (!modparam_nohwcrypt)
 212 +               __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
 213         __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
 214
 215         /*
 216 @@ -1769,6 +1889,7 @@ static const struct ieee80211_ops rt2500
 217         .config                 = rt2x00mac_config,
 218         .config_interface       = rt2x00mac_config_interface,
 219         .configure_filter       = rt2x00mac_configure_filter,
 220 +       .set_key                = rt2x00mac_set_key,
 221         .get_stats              = rt2x00mac_get_stats,
 222         .bss_info_changed       = rt2x00mac_bss_info_changed,
 223         .conf_tx                = rt2x00mac_conf_tx,
 224 @@ -1791,6 +1912,8 @@ static const struct rt2x00lib_ops rt2500
 225         .get_tx_data_len        = rt2500usb_get_tx_data_len,
 226         .kick_tx_queue          = rt2500usb_kick_tx_queue,
 227         .fill_rxdone            = rt2500usb_fill_rxdone,
 228 +       .config_shared_key      = rt2500usb_config_key,
 229 +       .config_pairwise_key    = rt2500usb_config_key,
 230         .config_filter          = rt2500usb_config_filter,
 231         .config_intf            = rt2500usb_config_intf,
 232         .config_erp             = rt2500usb_config_erp,
 233 --- a/drivers/net/wireless/rt2x00/rt2500usb.h
 234 +++ b/drivers/net/wireless/rt2x00/rt2500usb.h
 235 @@ -447,6 +447,9 @@
 236  #define SEC_CSR30                      0x04bc
 237  #define SEC_CSR31                      0x04be
 238
 239 +#define KEY_ENTRY(__idx) \
 240 +       ( SEC_CSR0 + ((__idx) * 16) )
 241 +
 242  /*
 243   * PHY control registers.
 244   */
 245 --- /dev/null
 246 +++ b/drivers/net/wireless/rt2x00/rt2800pci.c
 247 @@ -0,0 +1,2556 @@
 248 +/*
 249 +       Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
 250 +       <http://rt2x00.serialmonkey.com>
 251 +
 252 +       This program is free software; you can redistribute it and/or modify
 253 +       it under the terms of the GNU General Public License as published by
 254 +       the Free Software Foundation; either version 2 of the License, or
 255 +       (at your option) any later version.
 256 +
 257 +       This program is distributed in the hope that it will be useful,
 258 +       but WITHOUT ANY WARRANTY; without even the implied warranty of
 259 +       MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 260 +       GNU General Public License for more details.
 261 +
 262 +       You should have received a copy of the GNU General Public License
 263 +       along with this program; if not, write to the
 264 +       Free Software Foundation, Inc.,
 265 +       59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 266 + */
 267 +
 268 +/*
 269 +       Module: rt2800pci
 270 +       Abstract: rt2800pci device specific routines.
 271 +       Supported chipsets: RT2800E & RT2800ED.
 272 + */
 273 +
 274 +#include <linux/crc-ccitt.h>
 275 +#include <linux/delay.h>
 276 +#include <linux/etherdevice.h>
 277 +#include <linux/init.h>
 278 +#include <linux/kernel.h>
 279 +#include <linux/module.h>
 280 +#include <linux/pci.h>
 281 +#include <linux/eeprom_93cx6.h>
 282 +
 283 +#include "rt2x00.h"
 284 +#include "rt2x00pci.h"
 285 +#include "rt2800pci.h"
 286 +
 287 +/*
 288 + * Allow hardware encryption to be disabled.
 289 + */
 290 +static int modparam_nohwcrypt = 0;
 291 +module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
 292 +MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
 293 +
 294 +/*
 295 + * Register access.
 296 + * BBP and RF register require indirect register access,
 297 + * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
 298 + * These indirect registers work with busy bits,
 299 + * and we will try maximal REGISTER_BUSY_COUNT times to access
 300 + * the register while taking a REGISTER_BUSY_DELAY us delay
 301 + * between each attampt. When the busy bit is still set at that time,
 302 + * the access attempt is considered to have failed,
 303 + * and we will print an error.
 304 + */
 305 +static u32 rt2800pci_bbp_check(struct rt2x00_dev *rt2x00dev)
 306 +{
 307 +       u32 reg;
 308 +       unsigned int i;
 309 +
 310 +       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 311 +               rt2x00pci_register_read(rt2x00dev, BBP_CSR_CFG, &reg);
 312 +               if (!rt2x00_get_field32(reg, BBP_CSR_CFG_BUSY))
 313 +                       break;
 314 +               udelay(REGISTER_BUSY_DELAY);
 315 +       }
 316 +
 317 +       return reg;
 318 +}
 319 +
 320 +static void rt2800pci_bbp_write(struct rt2x00_dev *rt2x00dev,
 321 +                               const unsigned int word, const u8 value)
 322 +{
 323 +       u32 reg;
 324 +
 325 +       /*
 326 +        * Wait until the BBP becomes ready.
 327 +        */
 328 +       reg = rt2800pci_bbp_check(rt2x00dev);
 329 +       if (rt2x00_get_field32(reg, BBP_CSR_CFG_BUSY)) {
 330 +               ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
 331 +               return;
 332 +       }
 333 +
 334 +       /*
 335 +        * Write the data into the BBP.
 336 +        */
 337 +       reg = 0;
 338 +       rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
 339 +       rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 340 +       rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 341 +       rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
 342 +       rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 343 +
 344 +       rt2x00pci_register_write(rt2x00dev, BBP_CSR_CFG, reg);
 345 +}
 346 +
 347 +static void rt2800pci_bbp_read(struct rt2x00_dev *rt2x00dev,
 348 +                              const unsigned int word, u8 *value)
 349 +{
 350 +       u32 reg;
 351 +
 352 +       /*
 353 +        * Wait until the BBP becomes ready.
 354 +        */
 355 +       reg = rt2800pci_bbp_check(rt2x00dev);
 356 +       if (rt2x00_get_field32(reg, BBP_CSR_CFG_BUSY)) {
 357 +               ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
 358 +               return;
 359 +       }
 360 +
 361 +       /*
 362 +        * Write the request into the BBP.
 363 +        */
 364 +       reg = 0;
 365 +       rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 366 +       rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 367 +       rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
 368 +       rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 369 +
 370 +       rt2x00pci_register_write(rt2x00dev, BBP_CSR_CFG, reg);
 371 +
 372 +       /*
 373 +        * Wait until the BBP becomes ready.
 374 +        */
 375 +       reg = rt2800pci_bbp_check(rt2x00dev);
 376 +       if (rt2x00_get_field32(reg, BBP_CSR_CFG_BUSY)) {
 377 +               ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
 378 +               *value = 0xff;
 379 +               return;
 380 +       }
 381 +
 382 +       *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
 383 +}
 384 +
 385 +static void rt2800pci_rf_write(struct rt2x00_dev *rt2x00dev,
 386 +                              const unsigned int word, const u32 value)
 387 +{
 388 +       u32 reg;
 389 +       unsigned int i;
 390 +
 391 +       if (!word)
 392 +               return;
 393 +
 394 +       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 395 +               rt2x00pci_register_read(rt2x00dev, RF_CSR_CFG0, &reg);
 396 +               if (!rt2x00_get_field32(reg, RF_CSR_CFG0_BUSY))
 397 +                       goto rf_write;
 398 +               udelay(REGISTER_BUSY_DELAY);
 399 +       }
 400 +
 401 +       ERROR(rt2x00dev, "RF_CSR_CFG0 register busy. Write failed.\n");
 402 +       return;
 403 +
 404 +rf_write:
 405 +       reg = 0;
 406 +       rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
 407 +       rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
 408 +       rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
 409 +       rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
 410 +
 411 +       rt2x00pci_register_write(rt2x00dev, RF_CSR_CFG0, reg);
 412 +       rt2x00_rf_write(rt2x00dev, word, value);
 413 +}
 414 +
 415 +static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 416 +{
 417 +       struct rt2x00_dev *rt2x00dev = eeprom->data;
 418 +       u32 reg;
 419 +
 420 +       rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
 421 +
 422 +       eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
 423 +       eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
 424 +       eeprom->reg_data_clock =
 425 +           !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
 426 +       eeprom->reg_chip_select =
 427 +           !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
 428 +}
 429 +
 430 +static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 431 +{
 432 +       struct rt2x00_dev *rt2x00dev = eeprom->data;
 433 +       u32 reg = 0;
 434 +
 435 +       rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
 436 +       rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
 437 +       rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
 438 +                          !!eeprom->reg_data_clock);
 439 +       rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
 440 +                          !!eeprom->reg_chip_select);
 441 +
 442 +       rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
 443 +}
 444 +
 445 +static void rt2800pci_mcu_request(struct rt2x00_dev *rt2x00dev,
 446 +                                 const u8 command, const u8 token,
 447 +                                 const u8 arg0, const u8 arg1)
 448 +{
 449 +       unsigned int i;
 450 +       u32 reg;
 451 +
 452 +       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 453 +               rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CSR, &reg);
 454 +               if (!rt2x00_get_field32(reg, H2M_MAILBOX_CSR_OWNER))
 455 +                       goto mcu_write;
 456 +               udelay(REGISTER_BUSY_DELAY);
 457 +       }
 458 +
 459 +       ERROR(rt2x00dev, "mcu request error. "
 460 +             "Request 0x%02x failed for token 0x%02x.\n",
 461 +             command, token);
 462 +       return;
 463 +
 464 +mcu_write:
 465 +       rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 466 +       rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 467 +       rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 468 +       rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 469 +       rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
 470 +
 471 +       reg = 0;
 472 +       rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 473 +       rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
 474 +}
 475 +
 476 +#ifdef CONFIG_RT2X00_LIB_DEBUGFS
 477 +static const struct rt2x00debug rt2800pci_rt2x00debug = {
 478 +       .owner  = THIS_MODULE,
 479 +       .csr    = {
 480 +               .read           = rt2x00pci_register_read,
 481 +               .write          = rt2x00pci_register_write,
 482 +               .flags          = RT2X00DEBUGFS_OFFSET,
 483 +               .word_base      = CSR_REG_BASE,
 484 +               .word_size      = sizeof(u32),
 485 +               .word_count     = CSR_REG_SIZE / sizeof(u32),
 486 +       },
 487 +       .eeprom = {
 488 +               .read           = rt2x00_eeprom_read,
 489 +               .write          = rt2x00_eeprom_write,
 490 +               .word_base      = EEPROM_BASE,
 491 +               .word_size      = sizeof(u16),
 492 +               .word_count     = EEPROM_SIZE / sizeof(u16),
 493 +       },
 494 +       .bbp    = {
 495 +               .read           = rt2800pci_bbp_read,
 496 +               .write          = rt2800pci_bbp_write,
 497 +               .word_base      = BBP_BASE,
 498 +               .word_size      = sizeof(u8),
 499 +               .word_count     = BBP_SIZE / sizeof(u8),
 500 +       },
 501 +       .rf     = {
 502 +               .read           = rt2x00_rf_read,
 503 +               .write          = rt2800pci_rf_write,
 504 +               .word_base      = RF_BASE,
 505 +               .word_size      = sizeof(u32),
 506 +               .word_count     = RF_SIZE / sizeof(u32),
 507 +       },
 508 +};
 509 +#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 510 +
 511 +#ifdef CONFIG_RT2X00_LIB_RFKILL
 512 +static int rt2800pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 513 +{
 514 +       u32 reg;
 515 +
 516 +       rt2x00pci_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
 517 +       return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
 518 +}
 519 +#else
 520 +#define rt2800pci_rfkill_poll  NULL
 521 +#endif /* CONFIG_RT2X00_LIB_RFKILL */
 522 +
 523 +#ifdef CONFIG_RT2X00_LIB_LEDS
 524 +static void rt2800pci_brightness_set(struct led_classdev *led_cdev,
 525 +                                    enum led_brightness brightness)
 526 +{
 527 +       struct rt2x00_led *led =
 528 +           container_of(led_cdev, struct rt2x00_led, led_dev);
 529 +       unsigned int enabled = brightness != LED_OFF;
 530 +       unsigned int bg_mode =
 531 +           (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 532 +       unsigned int polarity =
 533 +               rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 534 +                                  EEPROM_FREQ_LED_POLARITY);
 535 +       unsigned int ledmode =
 536 +               rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 537 +                                  EEPROM_FREQ_LED_MODE);
 538 +
 539 +       if (led->type == LED_TYPE_RADIO) {
 540 +               rt2800pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 541 +                                     enabled ? 0x20 : 0);
 542 +       } else if (led->type == LED_TYPE_ASSOC) {
 543 +               rt2800pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 544 +                                     enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
 545 +       } else if (led->type == LED_TYPE_QUALITY) {
 546 +               /*
 547 +                * The brightness is divided into 6 levels (0 - 5),
 548 +                * The specs tell us the following levels:
 549 +                *      0, 1 ,3, 7, 15, 31
 550 +                * to determine the level in a simple way we can simply
 551 +                * work with bitshifting:
 552 +                *      (1 << level) - 1
 553 +                */
 554 +               rt2800pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
 555 +                                     (1 << brightness / (LED_FULL / 6)) - 1,
 556 +                                     polarity);
 557 +       }
 558 +}
 559 +
 560 +static int rt2800pci_blink_set(struct led_classdev *led_cdev,
 561 +                              unsigned long *delay_on,
 562 +                              unsigned long *delay_off)
 563 +{
 564 +       struct rt2x00_led *led =
 565 +           container_of(led_cdev, struct rt2x00_led, led_dev);
 566 +       u32 reg;
 567 +
 568 +       rt2x00pci_register_read(led->rt2x00dev, LED_CFG, &reg);
 569 +       rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
 570 +       rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
 571 +       rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
 572 +       rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
 573 +       rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 12);
 574 +       rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
 575 +       rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
 576 +       rt2x00pci_register_write(led->rt2x00dev, LED_CFG, reg);
 577 +
 578 +       return 0;
 579 +}
 580 +
 581 +static void rt2800pci_init_led(struct rt2x00_dev *rt2x00dev,
 582 +                              struct rt2x00_led *led,
 583 +                              enum led_type type)
 584 +{
 585 +       led->rt2x00dev = rt2x00dev;
 586 +       led->type = type;
 587 +       led->led_dev.brightness_set = rt2800pci_brightness_set;
 588 +       led->led_dev.blink_set = rt2800pci_blink_set;
 589 +       led->flags = LED_INITIALIZED;
 590 +}
 591 +#endif /* CONFIG_RT2X00_LIB_LEDS */
 592 +
 593 +/*
 594 + * Configuration handlers.
 595 + */
 596 +static void rt2800pci_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
 597 +                                      struct rt2x00lib_crypto *crypto,
 598 +                                      struct ieee80211_key_conf *key)
 599 +{
 600 +       u32 offset;
 601 +       u32 reg;
 602 +
 603 +       offset = MAC_WCID_ATTR_ENTRY(crypto->aid);
 604 +
 605 +       reg = 0;
 606 +       rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
 607 +                          !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
 608 +       rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_PAIRKEY_MODE,
 609 +                          crypto->cipher);
 610 +       rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
 611 +                          (crypto->cmd == SET_KEY) ? crypto->bssidx : 0);
 612 +       rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
 613 +       rt2x00pci_register_write(rt2x00dev, offset, reg);
 614 +}
 615 +
 616 +static int rt2800pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
 617 +                                      struct rt2x00lib_crypto *crypto,
 618 +                                      struct ieee80211_key_conf *key)
 619 +{
 620 +       struct hw_key_entry key_entry;
 621 +       struct rt2x00_field32 field;
 622 +       u32 offset;
 623 +       u32 mask;
 624 +       u32 reg;
 625 +
 626 +       if (crypto->cmd == SET_KEY) {
 627 +               memcpy(key_entry.key, crypto->key,
 628 +                      sizeof(key_entry.key));
 629 +               memcpy(key_entry.tx_mic, crypto->tx_mic,
 630 +                      sizeof(key_entry.tx_mic));
 631 +               memcpy(key_entry.rx_mic, crypto->rx_mic,
 632 +                      sizeof(key_entry.rx_mic));
 633 +
 634 +               offset = SHARED_KEY_ENTRY(key->hw_key_idx);
 635 +               rt2x00pci_register_multiwrite(rt2x00dev, offset,
 636 +                                             &key_entry, sizeof(key_entry));
 637 +
 638 +               /*
 639 +                * The driver does not support the IV/EIV generation
 640 +                * in hardware. However it doesn't support the IV/EIV
 641 +                * inside the ieee80211 frame either, but requires it
 642 +                * to be provided seperately for the descriptor.
 643 +                * rt2x00lib will cut the IV/EIV data out of all frames
 644 +                * given to us by mac80211, but we must tell mac80211
 645 +                * to generate the IV/EIV data.
 646 +                */
 647 +               key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
 648 +       }
 649 +
 650 +       /*
 651 +        * The cipher types are stored over multiple registers
 652 +        * starting with SHARED_KEY_MODE_BASE each word will have
 653 +        * 32 bits and contains the cipher types for 2 modes each.
 654 +        * Using the correct defines correctly will cause overhead,
 655 +        * so just calculate the correct offset.
 656 +        */
 657 +       mask = key->hw_key_idx % 8;
 658 +       field.bit_offset = (3 * mask);
 659 +       field.bit_mask = 0x7 << field.bit_offset;
 660 +
 661 +       offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
 662 +       rt2x00pci_register_read(rt2x00dev, offset, &reg);
 663 +       rt2x00_set_field32(&reg, field,
 664 +                          (crypto->cmd == SET_KEY) ? crypto->cipher : 0);
 665 +       rt2x00pci_register_write(rt2x00dev, offset, reg);
 666 +
 667 +       /*
 668 +        * Update WCID information
 669 +        */
 670 +       rt2800pci_config_wcid_attr(rt2x00dev, crypto, key);
 671 +
 672 +       return 0;
 673 +}
 674 +
 675 +static int rt2800pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
 676 +                                        struct rt2x00lib_crypto *crypto,
 677 +                                        struct ieee80211_key_conf *key)
 678 +{
 679 +       struct hw_key_entry key_entry;
 680 +       u32 offset;
 681 +
 682 +       /*
 683 +        * 1 pairwise key is possible per AID, this means that the AID
 684 +        * equals our hw_key_idx.
 685 +        */
 686 +       key->hw_key_idx = crypto->aid;
 687 +
 688 +       if (crypto->cmd == SET_KEY) {
 689 +               memcpy(key_entry.key, crypto->key,
 690 +                      sizeof(key_entry.key));
 691 +               memcpy(key_entry.tx_mic, crypto->tx_mic,
 692 +                      sizeof(key_entry.tx_mic));
 693 +               memcpy(key_entry.rx_mic, crypto->rx_mic,
 694 +                      sizeof(key_entry.rx_mic));
 695 +
 696 +               offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
 697 +               rt2x00pci_register_multiwrite(rt2x00dev, offset,
 698 +                                             &key_entry, sizeof(key_entry));
 699 +
 700 +               /*
 701 +                * The driver does not support the IV/EIV generation
 702 +                * in hardware. However it doesn't support the IV/EIV
 703 +                * inside the ieee80211 frame either, but requires it
 704 +                * to be provided seperately for the descriptor.
 705 +                * rt2x00lib will cut the IV/EIV data out of all frames
 706 +                * given to us by mac80211, but we must tell mac80211
 707 +                * to generate the IV/EIV data.
 708 +                */
 709 +               key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
 710 +       }
 711 +
 712 +       /*
 713 +        * Update WCID information
 714 +        */
 715 +       rt2800pci_config_wcid_attr(rt2x00dev, crypto, key);
 716 +
 717 +       return 0;
 718 +}
 719 +
 720 +static void rt2800pci_config_filter(struct rt2x00_dev *rt2x00dev,
 721 +                                   const unsigned int filter_flags)
 722 +{
 723 +       u32 reg;
 724 +
 725 +       /*
 726 +        * Start configuration steps.
 727 +        * Note that the version error will always be dropped
 728 +        * and broadcast frames will always be accepted since
 729 +        * there is no filter for it at this time.
 730 +        */
 731 +       rt2x00pci_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
 732 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
 733 +                          !(filter_flags & FIF_FCSFAIL));
 734 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
 735 +                          !(filter_flags & FIF_PLCPFAIL));
 736 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
 737 +                          !(filter_flags & FIF_PROMISC_IN_BSS));
 738 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
 739 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
 740 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
 741 +                          !(filter_flags & FIF_ALLMULTI));
 742 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
 743 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
 744 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
 745 +                          !(filter_flags & FIF_CONTROL));
 746 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
 747 +                          !(filter_flags & FIF_CONTROL));
 748 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
 749 +                          !(filter_flags & FIF_CONTROL));
 750 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
 751 +                          !(filter_flags & FIF_CONTROL));
 752 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
 753 +                          !(filter_flags & FIF_CONTROL));
 754 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
 755 +                          !(filter_flags & FIF_CONTROL));
 756 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
 757 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 1);
 758 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
 759 +                          !(filter_flags & FIF_CONTROL));
 760 +       rt2x00pci_register_write(rt2x00dev, RX_FILTER_CFG, reg);
 761 +}
 762 +
 763 +static void rt2800pci_config_intf(struct rt2x00_dev *rt2x00dev,
 764 +                                 struct rt2x00_intf *intf,
 765 +                                 struct rt2x00intf_conf *conf,
 766 +                                 const unsigned int flags)
 767 +{
 768 +       unsigned int beacon_base;
 769 +       u32 reg;
 770 +
 771 +       if (flags & CONFIG_UPDATE_TYPE) {
 772 +               /*
 773 +                * Clear current synchronisation setup.
 774 +                * For the Beacon base registers we only need to clear
 775 +                * the first byte since that byte contains the VALID and OWNER
 776 +                * bits which (when set to 0) will invalidate the entire beacon.
 777 +                */
 778 +               beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
 779 +               rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
 780 +
 781 +               /*
 782 +                * Enable synchronisation.
 783 +                */
 784 +               rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 785 +               rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
 786 +               rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
 787 +               rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
 788 +               rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 789 +       }
 790 +
 791 +       if (flags & CONFIG_UPDATE_MAC) {
 792 +               reg = le32_to_cpu(conf->mac[1]);
 793 +               rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
 794 +               conf->mac[1] = cpu_to_le32(reg);
 795 +
 796 +               rt2x00pci_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
 797 +                                             conf->mac, sizeof(conf->mac));
 798 +       }
 799 +
 800 +       if (flags & CONFIG_UPDATE_BSSID) {
 801 +               reg = le32_to_cpu(conf->bssid[1]);
 802 +               rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
 803 +               rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
 804 +               conf->bssid[1] = cpu_to_le32(reg);
 805 +
 806 +               rt2x00pci_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
 807 +                                             conf->bssid, sizeof(conf->bssid));
 808 +       }
 809 +}
 810 +
 811 +static void rt2800pci_config_erp(struct rt2x00_dev *rt2x00dev,
 812 +                                struct rt2x00lib_erp *erp)
 813 +{
 814 +       u32 reg;
 815 +
 816 +       rt2x00pci_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
 817 +       rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT,
 818 +                          erp->ack_timeout);
 819 +       rt2x00pci_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
 820 +
 821 +       rt2x00pci_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
 822 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
 823 +                          !!erp->short_preamble);
 824 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
 825 +                          !!erp->short_preamble);
 826 +       rt2x00pci_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
 827 +
 828 +       rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
 829 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
 830 +                          erp->cts_protection ? 2 : 0);
 831 +       rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
 832 +
 833 +       rt2x00pci_register_write(rt2x00dev, LEGACY_BASIC_RATE,
 834 +                                erp->basic_rates);
 835 +       rt2x00pci_register_write(rt2x00dev, HT_BASIC_RATE,
 836 +                                erp->basic_rates >> 32);
 837 +
 838 +       rt2x00pci_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
 839 +       rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
 840 +       rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
 841 +       rt2x00pci_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
 842 +
 843 +       rt2x00pci_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
 844 +       rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
 845 +       rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
 846 +       rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
 847 +       rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
 848 +       rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
 849 +       rt2x00pci_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
 850 +}
 851 +
 852 +static void rt2800pci_config_ant(struct rt2x00_dev *rt2x00dev,
 853 +                                struct antenna_setup *ant)
 854 +{
 855 +       u16 eeprom;
 856 +       u8 r1;
 857 +       u8 r3;
 858 +
 859 +       /*
 860 +        * FIXME: Use requested antenna configuration.
 861 +        */
 862 +
 863 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
 864 +
 865 +       rt2800pci_bbp_read(rt2x00dev, 1, &r1);
 866 +       rt2800pci_bbp_read(rt2x00dev, 3, &r3);
 867 +
 868 +       /*
 869 +        * Configure the TX antenna.
 870 +        */
 871 +       switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH)) {
 872 +       case 1:
 873 +               rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
 874 +               break;
 875 +       case 2:
 876 +       case 3:
 877 +               /* Do nothing */
 878 +               break;
 879 +       }
 880 +
 881 +       /*
 882 +        * Configure the RX antenna.
 883 +        */
 884 +       switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
 885 +       case 1:
 886 +               rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
 887 +               break;
 888 +       case 2:
 889 +               rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
 890 +               break;
 891 +       case 3:
 892 +               rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
 893 +               break;
 894 +       }
 895 +
 896 +       rt2800pci_bbp_write(rt2x00dev, 3, r3);
 897 +       rt2800pci_bbp_write(rt2x00dev, 1, r1);
 898 +}
 899 +
 900 +static void rt2800pci_config_lna_gain(struct rt2x00_dev *rt2x00dev,
 901 +                                     struct rt2x00lib_conf *libconf)
 902 +{
 903 +       u16 eeprom;
 904 +       short lna_gain;
 905 +
 906 +       if (libconf->rf.channel <= 14) {
 907 +               rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
 908 +               lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
 909 +       } else if (libconf->rf.channel <= 64) {
 910 +               rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
 911 +               lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
 912 +       } else if (libconf->rf.channel <= 128) {
 913 +               rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
 914 +               lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
 915 +       } else {
 916 +               rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
 917 +               lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
 918 +       }
 919 +
 920 +       rt2x00dev->lna_gain = lna_gain;
 921 +}
 922 +
 923 +static void rt2800pci_config_channel(struct rt2x00_dev *rt2x00dev,
 924 +                                    struct rf_channel *rf,
 925 +                                    struct channel_info *info)
 926 +{
 927 +       u32 reg;
 928 +       unsigned int tx_pin;
 929 +       u16 eeprom;
 930 +
 931 +       tx_pin = 0;
 932 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
 933 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
 934 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
 935 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
 936 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
 937 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
 938 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
 939 +
 940 +       rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
 941 +
 942 +       /*
 943 +        * Determine antenna settings from EEPROM
 944 +        */
 945 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
 946 +       if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1) {
 947 +               rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
 948 +               /* Turn off unused PA or LNA when only 1T or 1R */
 949 +               rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 0);
 950 +               rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 0);
 951 +       }
 952 +
 953 +       if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1) {
 954 +               rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
 955 +               rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
 956 +               /* Turn off unused PA or LNA when only 1T or 1R */
 957 +               rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 0);
 958 +               rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 0);
 959 +       } else if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 2)
 960 +               rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
 961 +
 962 +       if (rf->channel > 14) {
 963 +               /*
 964 +                * When TX power is below 0, we should increase it by 7 to
 965 +                * make it a positive value (Minumum value is -7).
 966 +                * However this means that values between 0 and 7 have
 967 +                * double meaning, and we should set a 7DBm boost flag.
 968 +                */
 969 +               rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
 970 +                                  (info->tx_power1 >= 0));
 971 +
 972 +               if (info->tx_power1 < 0)
 973 +                       info->tx_power1 += 7;
 974 +
 975 +               rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
 976 +                                  TXPOWER_A_TO_DEV(info->tx_power1));
 977 +
 978 +               rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
 979 +                                  (info->tx_power2 >= 0));
 980 +
 981 +               if (info->tx_power2 < 0)
 982 +                       info->tx_power2 += 7;
 983 +
 984 +               rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
 985 +                                  TXPOWER_A_TO_DEV(info->tx_power2));
 986 +
 987 +               rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
 988 +       } else {
 989 +               rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
 990 +                                  TXPOWER_G_TO_DEV(info->tx_power1));
 991 +               rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
 992 +                                  TXPOWER_G_TO_DEV(info->tx_power2));
 993 +
 994 +               rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
 995 +       }
 996 +
 997 +       /* FIXME: How to determine bandwidth
 998 +       rt2x00_set_field32(&rf->rf4, RF4_BW40, !!(BBPCurrentBW == BW_40));
 999 +       */
1000 +
1001 +       rt2800pci_rf_write(rt2x00dev, 1, rf->rf1);
1002 +       rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
1003 +       rt2800pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1004 +       rt2800pci_rf_write(rt2x00dev, 4, rf->rf4);
1005 +
1006 +       udelay(200);
1007 +
1008 +       rt2800pci_rf_write(rt2x00dev, 1, rf->rf1);
1009 +       rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
1010 +       rt2800pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1011 +       rt2800pci_rf_write(rt2x00dev, 4, rf->rf4);
1012 +
1013 +       udelay(200);
1014 +
1015 +       rt2800pci_rf_write(rt2x00dev, 1, rf->rf1);
1016 +       rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
1017 +       rt2800pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1018 +       rt2800pci_rf_write(rt2x00dev, 4, rf->rf4);
1019 +
1020 +       /*
1021 +        * Change BBP settings
1022 +        */
1023 +       rt2800pci_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
1024 +       rt2800pci_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
1025 +       rt2800pci_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
1026 +       rt2800pci_bbp_write(rt2x00dev, 86, 0);
1027 +
1028 +       if (rf->channel <= 14) {
1029 +               if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
1030 +                       rt2800pci_bbp_write(rt2x00dev, 82, 0x62);
1031 +                       rt2800pci_bbp_write(rt2x00dev, 75, 0x46);
1032 +               } else {
1033 +                       rt2800pci_bbp_write(rt2x00dev, 82, 0x84);
1034 +                       rt2800pci_bbp_write(rt2x00dev, 75, 0x50);
1035 +               }
1036 +
1037 +               rt2x00pci_register_read(rt2x00dev, TX_BAND_CFG, &reg);
1038 +               rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_A, 0);
1039 +               rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_BG, 1);
1040 +               rt2x00pci_register_write(rt2x00dev, TX_BAND_CFG, reg);
1041 +       } else {
1042 +               rt2800pci_bbp_write(rt2x00dev, 82, 0xf2);
1043 +
1044 +               if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1045 +                       rt2800pci_bbp_write(rt2x00dev, 75, 0x46);
1046 +               else
1047 +                       rt2800pci_bbp_write(rt2x00dev, 75, 0x50);
1048 +
1049 +               rt2x00pci_register_read(rt2x00dev, TX_BAND_CFG, &reg);
1050 +               rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_A, 1);
1051 +               rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_BG, 0);
1052 +               rt2x00pci_register_write(rt2x00dev, TX_BAND_CFG, reg);
1053 +       }
1054 +
1055 +       rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
1056 +
1057 +       msleep(1);
1058 +}
1059 +
1060 +static void rt2800pci_config_txpower(struct rt2x00_dev *rt2x00dev,
1061 +                                    const int txpower)
1062 +{
1063 +       u32 reg;
1064 +       u32 value = TXPOWER_G_TO_DEV(txpower);
1065 +       u8 r1;
1066 +
1067 +       rt2800pci_bbp_read(rt2x00dev, 1, &r1);
1068 +       rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
1069 +       rt2800pci_bbp_write(rt2x00dev, 1, r1);
1070 +
1071 +       rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
1072 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
1073 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
1074 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
1075 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
1076 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
1077 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
1078 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
1079 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
1080 +       rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
1081 +
1082 +       rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
1083 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
1084 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
1085 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
1086 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
1087 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
1088 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
1089 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
1090 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
1091 +       rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
1092 +
1093 +       rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
1094 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
1095 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
1096 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
1097 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
1098 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
1099 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
1100 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
1101 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
1102 +       rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
1103 +
1104 +       rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
1105 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
1106 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
1107 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
1108 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
1109 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
1110 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
1111 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
1112 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
1113 +       rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
1114 +
1115 +       rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
1116 +       rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
1117 +       rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
1118 +       rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
1119 +       rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
1120 +       rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
1121 +}
1122 +
1123 +static void rt2800pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
1124 +                                        struct rt2x00lib_conf *libconf)
1125 +{
1126 +       u32 reg;
1127 +
1128 +       rt2x00pci_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1129 +       rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
1130 +                          libconf->conf->short_frame_max_tx_count);
1131 +       rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
1132 +                          libconf->conf->long_frame_max_tx_count);
1133 +       rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
1134 +       rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
1135 +       rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
1136 +       rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
1137 +       rt2x00pci_register_write(rt2x00dev, TX_RTY_CFG, reg);
1138 +}
1139 +
1140 +static void rt2800pci_config_duration(struct rt2x00_dev *rt2x00dev,
1141 +                                     struct rt2x00lib_conf *libconf)
1142 +{
1143 +       u32 reg;
1144 +
1145 +       rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1146 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1147 +                          libconf->conf->beacon_int * 16);
1148 +       rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1149 +}
1150 +
1151 +static void rt2800pci_config(struct rt2x00_dev *rt2x00dev,
1152 +                            struct rt2x00lib_conf *libconf,
1153 +                            const unsigned int flags)
1154 +{
1155 +       /* Always recalculate LNA gain before changing configuration */
1156 +       rt2800pci_config_lna_gain(rt2x00dev, libconf);
1157 +
1158 +       if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1159 +               rt2800pci_config_channel(rt2x00dev, &libconf->rf,
1160 +                                        &libconf->channel);
1161 +       if (flags & IEEE80211_CONF_CHANGE_POWER)
1162 +               rt2800pci_config_txpower(rt2x00dev, libconf->conf->power_level);
1163 +       if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1164 +               rt2800pci_config_retry_limit(rt2x00dev, libconf);
1165 +       if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
1166 +               rt2800pci_config_duration(rt2x00dev, libconf);
1167 +}
1168 +
1169 +/*
1170 + * Link tuning
1171 + */
1172 +static void rt2800pci_link_stats(struct rt2x00_dev *rt2x00dev,
1173 +                                struct link_qual *qual)
1174 +{
1175 +       u32 reg;
1176 +
1177 +       /*
1178 +        * Update FCS error count from register.
1179 +        */
1180 +       rt2x00pci_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1181 +       qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1182 +
1183 +       /*
1184 +        * Update False CCA count from register.
1185 +        */
1186 +       rt2x00pci_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1187 +       qual->false_cca = rt2x00_get_field32(reg, RX_STA_CNT1_FALSE_CCA);
1188 +}
1189 +
1190 +static void rt2800pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
1191 +{
1192 +       u8 r66;
1193 +
1194 +       if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ)
1195 +               r66 = 0x2e + rt2x00dev->lna_gain;
1196 +       else {
1197 +               if (1 /* FIXME: pAd->CommonCfg.BBPCurrentBW == BW_20 */)
1198 +                       r66 = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1199 +               else
1200 +                       r66 = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1201 +       }
1202 +
1203 +       rt2800pci_bbp_write(rt2x00dev, 66, r66);
1204 +}
1205 +
1206 +static void rt2800pci_link_tuner(struct rt2x00_dev *rt2x00dev)
1207 +{
1208 +       int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
1209 +       u8 r66_orig;
1210 +       u8 r66;
1211 +
1212 +       if (rt2x00_rev(&rt2x00dev->chip) == RT2860_VERSION_C)
1213 +               return;
1214 +
1215 +       rt2800pci_bbp_read(rt2x00dev, 66, &r66_orig);
1216 +       r66 = r66_orig;
1217 +
1218 +       if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
1219 +               r66 = 0x2e + rt2x00dev->lna_gain;
1220 +       } else {
1221 +               if (1 /* FIXME: pAd->CommonCfg.BBPCurrentBW == BW_20 */)
1222 +                       r66 = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1223 +               else
1224 +                       r66 = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1225 +       }
1226 +
1227 +       if (rssi > -80)
1228 +               r66 += 0x10;
1229 +
1230 +       if (rssi != r66_orig)
1231 +               rt2800pci_bbp_write(rt2x00dev, 66, r66);
1232 +}
1233 +
1234 +/*
1235 + * Firmware functions
1236 + */
1237 +static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1238 +{
1239 +       return FIRMWARE_RT2860;
1240 +}
1241 +
1242 +static u16 rt2800pci_get_firmware_crc(const void *data, const size_t len)
1243 +{
1244 +       u16 crc;
1245 +
1246 +       /*
1247 +        * Use the crc ccitt algorithm.
1248 +        * This will return the same value as the legacy driver which
1249 +        * used bit ordering reversion on the both the firmware bytes
1250 +        * before input input as well as on the final output.
1251 +        * Obviously using crc ccitt directly is much more efficient.
1252 +        * The last 2 bytes in the firmware array are the crc checksum itself,
1253 +        * this means that we should never pass those 2 bytes to the crc
1254 +        * algorithm.
1255 +        */
1256 +       crc = crc_ccitt(~0, data, len - 2);
1257 +
1258 +       /*
1259 +        * There is a small difference between the crc-itu-t + bitrev and
1260 +        * the crc-ccitt crc calculation. In the latter method the 2 bytes
1261 +        * will be swapped, use swab16 to convert the crc to the correct
1262 +        * value.
1263 +        */
1264 +       return swab16(crc);
1265 +}
1266 +
1267 +static int rt2800pci_load_firmware(struct rt2x00_dev *rt2x00dev,
1268 +                                  const void *data, const size_t len)
1269 +{
1270 +       unsigned int i;
1271 +       u32 reg;
1272 +
1273 +       /*
1274 +        * Wait for stable hardware.
1275 +        */
1276 +       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1277 +               rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
1278 +               if (reg && reg != ~0)
1279 +                       break;
1280 +               msleep(1);
1281 +       }
1282 +
1283 +       if (i == REGISTER_BUSY_COUNT) {
1284 +               ERROR(rt2x00dev, "Unstable hardware.\n");
1285 +               return -EBUSY;
1286 +       }
1287 +
1288 +       /*
1289 +        * Disable DMA, will be reenabled later when enabling
1290 +        * the radio.
1291 +        */
1292 +       rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1293 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1294 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1295 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1296 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1297 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1298 +       rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1299 +
1300 +       rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, ~0);
1301 +       rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x0e1f);
1302 +       rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x0e00);
1303 +
1304 +       /*
1305 +        * enable Host program ram write selection
1306 +        */
1307 +       reg = 0;
1308 +       rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
1309 +       rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
1310 +
1311 +       /*
1312 +        * Write firmware to device.
1313 +        */
1314 +       rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
1315 +                                     data, len);
1316 +
1317 +       rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
1318 +       rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
1319 +
1320 +       /*
1321 +        * Wait for device to stabilize.
1322 +        */
1323 +       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1324 +               rt2x00pci_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1325 +               if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
1326 +                       break;
1327 +               msleep(1);
1328 +       }
1329 +
1330 +       if (i == REGISTER_BUSY_COUNT) {
1331 +               ERROR(rt2x00dev, "PBF system register not ready.\n");
1332 +               return -EBUSY;
1333 +       }
1334 +
1335 +       /*
1336 +        * Initialize BBP R/W access agent
1337 +        */
1338 +       rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1339 +       rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1340 +
1341 +       return 0;
1342 +}
1343 +
1344 +/*
1345 + * Initialization functions.
1346 + */
1347 +static void rt2800pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
1348 +                                  struct queue_entry *entry)
1349 +{
1350 +       struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1351 +       struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1352 +       u32 word;
1353 +
1354 +       rt2x00_desc_read(entry_priv->desc, 0, &word);
1355 +       rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
1356 +       rt2x00_desc_write(entry_priv->desc, 0, word);
1357 +
1358 +       rt2x00_desc_read(entry_priv->desc, 1, &word);
1359 +       rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
1360 +       rt2x00_desc_write(entry_priv->desc, 1, word);
1361 +}
1362 +
1363 +static void rt2800pci_init_txentry(struct rt2x00_dev *rt2x00dev,
1364 +                                  struct queue_entry *entry)
1365 +{
1366 +       struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1367 +       u32 word;
1368 +
1369 +       rt2x00_desc_read(entry_priv->desc, 1, &word);
1370 +       rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
1371 +       rt2x00_desc_write(entry_priv->desc, 1, word);
1372 +}
1373 +
1374 +static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
1375 +{
1376 +       struct queue_entry_priv_pci *entry_priv;
1377 +       u32 reg;
1378 +
1379 +       /*
1380 +        * Initialize registers.
1381 +        */
1382 +       entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
1383 +       rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
1384 +       rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT0, rt2x00dev->tx[0].limit);
1385 +       rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX0, 0);
1386 +
1387 +       entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
1388 +       rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
1389 +       rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT1, rt2x00dev->tx[1].limit);
1390 +       rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX1, 0);
1391 +
1392 +       entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
1393 +       rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
1394 +       rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT2, rt2x00dev->tx[2].limit);
1395 +       rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX2, 0);
1396 +
1397 +       entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
1398 +       rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
1399 +       rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT3, rt2x00dev->tx[3].limit);
1400 +       rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX3, 0);
1401 +
1402 +       entry_priv = rt2x00dev->rx->entries[0].priv_data;
1403 +       rt2x00pci_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
1404 +       rt2x00pci_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit);
1405 +       rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX, 0);
1406 +
1407 +       /*
1408 +        * Enable global DMA configuration
1409 +        */
1410 +       rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1411 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1412 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1413 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1414 +       rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1415 +
1416 +       rt2x00pci_register_write(rt2x00dev, DELAY_INT_CFG, 0);
1417 +
1418 +       return 0;
1419 +}
1420 +
1421 +static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
1422 +{
1423 +       u32 reg;
1424 +       unsigned int i;
1425 +
1426 +       rt2x00pci_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
1427 +       rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
1428 +       rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
1429 +       rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
1430 +       rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
1431 +       rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
1432 +       rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
1433 +       rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
1434 +       rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
1435 +
1436 +       rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
1437 +       rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000000);
1438 +
1439 +       rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1440 +       rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1441 +       rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1442 +       rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1443 +
1444 +       rt2x00pci_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1445 +       rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1446 +       rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1447 +       rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1448 +       rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1449 +       rt2x00pci_register_write(rt2x00dev, BCN_OFFSET0, reg);
1450 +
1451 +       rt2x00pci_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1452 +       rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1453 +       rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1454 +       rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1455 +       rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1456 +       rt2x00pci_register_write(rt2x00dev, BCN_OFFSET1, reg);
1457 +
1458 +       rt2x00pci_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1459 +       rt2x00pci_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1460 +
1461 +       rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1462 +
1463 +       rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1464 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1465 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1466 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1467 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1468 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1469 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1470 +       rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1471 +
1472 +       rt2x00pci_register_write(rt2x00dev, TX_SW_CFG0, 0x00040a06);
1473 +       rt2x00pci_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1474 +
1475 +       rt2x00pci_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1476 +       rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1477 +       rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1478 +       rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1479 +       rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1480 +       rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1481 +       rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1482 +       rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1483 +       rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1484 +       rt2x00pci_register_write(rt2x00dev, TX_LINK_CFG, reg);
1485 +
1486 +       rt2x00pci_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1487 +       rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1488 +       rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1489 +       rt2x00pci_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1490 +
1491 +       rt2x00pci_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1492 +       rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1493 +       rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1494 +       rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1495 +       rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1496 +       rt2x00pci_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1497 +
1498 +       rt2x00pci_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1499 +
1500 +       rt2x00pci_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1501 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1502 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1503 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1504 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1505 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1506 +       rt2x00pci_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1507 +
1508 +       rt2x00pci_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1509 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
1510 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1511 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1512 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1513 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1514 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1515 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1516 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1517 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1518 +       rt2x00pci_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1519 +
1520 +       rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1521 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
1522 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1523 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1524 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1525 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1526 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1527 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1528 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1529 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1530 +       rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1531 +
1532 +       rt2x00pci_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1533 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1534 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1535 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1536 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1537 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1538 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1539 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1540 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1541 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1542 +       rt2x00pci_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1543 +
1544 +       rt2x00pci_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1545 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1546 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
1547 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1548 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1549 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1550 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1551 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1552 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1553 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1554 +       rt2x00pci_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1555 +
1556 +       rt2x00pci_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1557 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1558 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1559 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1560 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1561 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1562 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1563 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1564 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1565 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1566 +       rt2x00pci_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1567 +
1568 +       rt2x00pci_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1569 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1570 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1571 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1572 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1573 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1574 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1575 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1576 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1577 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1578 +       rt2x00pci_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1579 +
1580 +       rt2x00pci_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1581 +       rt2x00pci_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1582 +
1583 +       rt2x00pci_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1584 +       rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1585 +       rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1586 +       rt2x00pci_register_write(rt2x00dev, TX_RTS_CFG, reg);
1587 +
1588 +       rt2x00pci_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1589 +       rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1590 +
1591 +       /*
1592 +        * ASIC will keep garbage value after boot, clear encryption keys.
1593 +        */
1594 +       for (i = 0; i < 254; i++) {
1595 +               u32 wcid[2] = { 0xffffffff, 0x0000ffff };
1596 +               rt2x00pci_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1597 +                                             wcid, sizeof(wcid));
1598 +       }
1599 +
1600 +       for (i = 0; i < 4; i++)
1601 +               rt2x00pci_register_write(rt2x00dev,
1602 +                                        SHARED_KEY_MODE_ENTRY(i), 0);
1603 +
1604 +       for (i = 0; i < 256; i++)
1605 +               rt2x00pci_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1606 +
1607 +       /*
1608 +        * Clear all beacons
1609 +        * For the Beacon base registers we only need to clear
1610 +        * the first byte since that byte contains the VALID and OWNER
1611 +        * bits which (when set to 0) will invalidate the entire beacon.
1612 +        */
1613 +       rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1614 +       rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1615 +       rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1616 +       rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1617 +       rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1618 +       rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1619 +       rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1620 +       rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1621 +
1622 +       rt2x00pci_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1623 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1624 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1625 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1626 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1627 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1628 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1629 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1630 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1631 +       rt2x00pci_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1632 +
1633 +       rt2x00pci_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1634 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1635 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1636 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1637 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1638 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1639 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1640 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1641 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1642 +       rt2x00pci_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1643 +
1644 +       rt2x00pci_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1645 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1646 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1647 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 10);
1648 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 11);
1649 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 12);
1650 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 13);
1651 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 14);
1652 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 15);
1653 +       rt2x00pci_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1654 +
1655 +       rt2x00pci_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1656 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1657 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1658 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1659 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1660 +       rt2x00pci_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1661 +
1662 +       /*
1663 +        * We must clear the error counters.
1664 +        * These registers are cleared on read,
1665 +        * so we may pass a useless variable to store the value.
1666 +        */
1667 +       rt2x00pci_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1668 +       rt2x00pci_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1669 +       rt2x00pci_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1670 +       rt2x00pci_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1671 +       rt2x00pci_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1672 +       rt2x00pci_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1673 +
1674 +       return 0;
1675 +}
1676 +
1677 +static int rt2800pci_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1678 +{
1679 +       unsigned int i;
1680 +       u32 reg;
1681 +
1682 +       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1683 +               rt2x00pci_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1684 +               if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1685 +                       return 0;
1686 +
1687 +               udelay(REGISTER_BUSY_DELAY);
1688 +       }
1689 +
1690 +       ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1691 +       return -EACCES;
1692 +}
1693 +
1694 +static int rt2800pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1695 +{
1696 +       unsigned int i;
1697 +       u8 value;
1698 +
1699 +       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1700 +               rt2800pci_bbp_read(rt2x00dev, 0, &value);
1701 +               if ((value != 0xff) && (value != 0x00))
1702 +                       return 0;
1703 +               udelay(REGISTER_BUSY_DELAY);
1704 +       }
1705 +
1706 +       ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1707 +       return -EACCES;
1708 +}
1709 +
1710 +static int rt2800pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1711 +{
1712 +       unsigned int i;
1713 +       u16 eeprom;
1714 +       u8 reg_id;
1715 +       u8 value;
1716 +
1717 +       if (unlikely(rt2800pci_wait_bbp_rf_ready(rt2x00dev) ||
1718 +                    rt2800pci_wait_bbp_ready(rt2x00dev)))
1719 +               return -EACCES;
1720 +
1721 +       rt2800pci_bbp_write(rt2x00dev, 65, 0x2c);
1722 +       rt2800pci_bbp_write(rt2x00dev, 66, 0x38);
1723 +       rt2800pci_bbp_write(rt2x00dev, 69, 0x12);
1724 +       rt2800pci_bbp_write(rt2x00dev, 70, 0x0a);
1725 +       rt2800pci_bbp_write(rt2x00dev, 73, 0x10);
1726 +       rt2800pci_bbp_write(rt2x00dev, 81, 0x37);
1727 +       rt2800pci_bbp_write(rt2x00dev, 82, 0x62);
1728 +       rt2800pci_bbp_write(rt2x00dev, 83, 0x6a);
1729 +       rt2800pci_bbp_write(rt2x00dev, 84, 0x99);
1730 +       rt2800pci_bbp_write(rt2x00dev, 86, 0x00);
1731 +       rt2800pci_bbp_write(rt2x00dev, 91, 0x04);
1732 +       rt2800pci_bbp_write(rt2x00dev, 92, 0x00);
1733 +       rt2800pci_bbp_write(rt2x00dev, 103, 0x00);
1734 +       rt2800pci_bbp_write(rt2x00dev, 105, 0x05);
1735 +
1736 +       if (rt2x00_rev(&rt2x00dev->chip) == RT2860_VERSION_C) {
1737 +               rt2800pci_bbp_write(rt2x00dev, 69, 0x16);
1738 +               rt2800pci_bbp_write(rt2x00dev, 73, 0x12);
1739 +       }
1740 +
1741 +       if (rt2x00_rev(&rt2x00dev->chip) == RT2860_VERSION_D)
1742 +               rt2800pci_bbp_write(rt2x00dev, 84, 0x19);
1743 +
1744 +       for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1745 +               rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1746 +
1747 +               if (eeprom != 0xffff && eeprom != 0x0000) {
1748 +                       reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1749 +                       value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1750 +                       rt2800pci_bbp_write(rt2x00dev, reg_id, value);
1751 +               }
1752 +       }
1753 +
1754 +       return 0;
1755 +}
1756 +
1757 +/*
1758 + * Device state switch handlers.
1759 + */
1760 +static void rt2800pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1761 +                               enum dev_state state)
1762 +{
1763 +       u32 reg;
1764 +
1765 +       rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1766 +       rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
1767 +                          (state == STATE_RADIO_RX_ON) ||
1768 +                          (state == STATE_RADIO_RX_ON_LINK));
1769 +       rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1770 +}
1771 +
1772 +static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1773 +                                enum dev_state state)
1774 +{
1775 +       int mask = (state == STATE_RADIO_IRQ_OFF);
1776 +       u32 reg;
1777 +
1778 +       /*
1779 +        * When interrupts are being enabled, the interrupt registers
1780 +        * should clear the register to assure a clean state.
1781 +        */
1782 +       if (state == STATE_RADIO_IRQ_ON) {
1783 +               rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1784 +               rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1785 +       }
1786 +
1787 +       rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1788 +       rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, mask);
1789 +       rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, mask);
1790 +       rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask);
1791 +       rt2x00_set_field32(&reg, INT_MASK_CSR_AC0_DMA_DONE, mask);
1792 +       rt2x00_set_field32(&reg, INT_MASK_CSR_AC1_DMA_DONE, mask);
1793 +       rt2x00_set_field32(&reg, INT_MASK_CSR_AC2_DMA_DONE, mask);
1794 +       rt2x00_set_field32(&reg, INT_MASK_CSR_AC3_DMA_DONE, mask);
1795 +       rt2x00_set_field32(&reg, INT_MASK_CSR_HCCA_DMA_DONE, mask);
1796 +       rt2x00_set_field32(&reg, INT_MASK_CSR_MGMT_DMA_DONE, mask);
1797 +       rt2x00_set_field32(&reg, INT_MASK_CSR_MCU_COMMAND, mask);
1798 +       rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, mask);
1799 +       rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, mask);
1800 +       rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1801 +}
1802 +
1803 +static int rt2800pci_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
1804 +{
1805 +       unsigned int i;
1806 +       u32 reg;
1807 +
1808 +       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1809 +               rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1810 +               if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
1811 +                   !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
1812 +                       return 0;
1813 +
1814 +               msleep(1);
1815 +       }
1816 +
1817 +       ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
1818 +       return -EACCES;
1819 +}
1820 +
1821 +static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1822 +{
1823 +       u32 reg;
1824 +       u16 word;
1825 +
1826 +       /*
1827 +        * Initialize all registers.
1828 +        */
1829 +       if (unlikely(rt2800pci_wait_wpdma_ready(rt2x00dev) ||
1830 +                    rt2800pci_init_queues(rt2x00dev) ||
1831 +                    rt2800pci_init_registers(rt2x00dev) ||
1832 +                    rt2800pci_init_bbp(rt2x00dev)))
1833 +               return -EIO;
1834 +
1835 +       rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001a80);
1836 +
1837 +       /* Wait for DMA, ignore error */
1838 +       rt2800pci_wait_wpdma_ready(rt2x00dev);
1839 +
1840 +       /*
1841 +        * Enable RX.
1842 +        */
1843 +       rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1844 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
1845 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
1846 +       rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1847 +
1848 +       rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1849 +       rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
1850 +       rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
1851 +       rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1852 +
1853 +       /*
1854 +        * Initialize LED control
1855 +        */
1856 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
1857 +       rt2800pci_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
1858 +                             word & 0xff, (word >> 8) & 0xff);
1859 +
1860 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
1861 +       rt2800pci_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
1862 +                             word & 0xff, (word >> 8) & 0xff);
1863 +
1864 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
1865 +       rt2800pci_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
1866 +                             word & 0xff, (word >> 8) & 0xff);
1867 +
1868 +       rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1869 +       rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1870 +
1871 +       /*
1872 +        * Send signal to firmware during boot time.
1873 +        */
1874 +       rt2800pci_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0);
1875 +
1876 +       return 0;
1877 +}
1878 +
1879 +static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1880 +{
1881 +       u32 reg;
1882 +
1883 +       rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1884 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1885 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1886 +       rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1887 +
1888 +       rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
1889 +       rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0);
1890 +       rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, 0);
1891 +
1892 +       rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001280);
1893 +
1894 +       /* Wait for DMA, ignore error */
1895 +       rt2800pci_wait_wpdma_ready(rt2x00dev);
1896 +}
1897 +
1898 +static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
1899 +                              enum dev_state state)
1900 +{
1901 +       rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1902 +
1903 +       if (state == STATE_AWAKE)
1904 +               rt2800pci_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
1905 +       else
1906 +               rt2800pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
1907 +
1908 +       return 0;
1909 +}
1910 +
1911 +static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1912 +                                     enum dev_state state)
1913 +{
1914 +       int retval = 0;
1915 +
1916 +       switch (state) {
1917 +       case STATE_RADIO_ON:
1918 +               /*
1919 +                * Before the radio can be enabled, the device first has
1920 +                * to be woken up. After that it needs a bit of time
1921 +                * to be fully awake and the radio can be enabled.
1922 +                */
1923 +               rt2800pci_set_state(rt2x00dev, STATE_AWAKE);
1924 +               msleep(1);
1925 +               retval = rt2800pci_enable_radio(rt2x00dev);
1926 +               break;
1927 +       case STATE_RADIO_OFF:
1928 +               /*
1929 +                * After the radio has been disablee, the device should
1930 +                * be put to sleep for powersaving.
1931 +                */
1932 +               rt2800pci_disable_radio(rt2x00dev);
1933 +               rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
1934 +               break;
1935 +       case STATE_RADIO_RX_ON:
1936 +       case STATE_RADIO_RX_ON_LINK:
1937 +       case STATE_RADIO_RX_OFF:
1938 +       case STATE_RADIO_RX_OFF_LINK:
1939 +               rt2800pci_toggle_rx(rt2x00dev, state);
1940 +               break;
1941 +       case STATE_RADIO_IRQ_ON:
1942 +       case STATE_RADIO_IRQ_OFF:
1943 +               rt2800pci_toggle_irq(rt2x00dev, state);
1944 +               break;
1945 +       case STATE_DEEP_SLEEP:
1946 +       case STATE_SLEEP:
1947 +       case STATE_STANDBY:
1948 +       case STATE_AWAKE:
1949 +               retval = rt2800pci_set_state(rt2x00dev, state);
1950 +               break;
1951 +       default:
1952 +               retval = -ENOTSUPP;
1953 +               break;
1954 +       }
1955 +
1956 +       if (unlikely(retval))
1957 +               ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1958 +                     state, retval);
1959 +
1960 +       return retval;
1961 +}
1962 +
1963 +/*
1964 + * TX descriptor initialization
1965 + */
1966 +static void rt2800pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1967 +                                   struct sk_buff *skb,
1968 +                                   struct txentry_desc *txdesc)
1969 +{
1970 +       struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1971 +       __le32 *txd = skbdesc->desc;
1972 +       __le32 *txwi = (__le32 *)(skb->data - rt2x00dev->hw->extra_tx_headroom);
1973 +       u32 word;
1974 +
1975 +       /*
1976 +        * Initialize TX Info descriptor
1977 +        */
1978 +       rt2x00_desc_read(txwi, 0, &word);
1979 +       rt2x00_set_field32(&word, TXWI_W0_FRAG,
1980 +                          test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags) ||
1981 +                          test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1982 +       rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
1983 +       rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
1984 +       rt2x00_set_field32(&word, TXWI_W0_TS,
1985 +                          test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1986 +       rt2x00_set_field32(&word, TXWI_W0_AMPDU,
1987 +                          test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
1988 +       rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
1989 +       rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->ifs);
1990 +       rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
1991 +       rt2x00_set_field32(&word, TXWI_W0_BW,
1992 +                          test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
1993 +       rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
1994 +                          test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
1995 +       rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
1996 +       rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
1997 +       rt2x00_desc_write(txwi, 0, word);
1998 +
1999 +       rt2x00_desc_read(txwi, 1, &word);
2000 +       rt2x00_set_field32(&word, TXWI_W1_ACK,
2001 +                          test_bit(ENTRY_TXD_ACK, &txdesc->flags));
2002 +       rt2x00_set_field32(&word, TXWI_W1_ACK,
2003 +                          test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags));
2004 +       rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
2005 +       rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID, 0xff);
2006 +       rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT, skb->len);
2007 +       rt2x00_set_field32(&word, TXWI_W1_PACKETID,
2008 +                          skbdesc->entry->entry_idx);
2009 +       rt2x00_desc_write(txwi, 1, word);
2010 +
2011 +       if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
2012 +               _rt2x00_desc_write(txwi, 2, skbdesc->iv);
2013 +               _rt2x00_desc_write(txwi, 3, skbdesc->eiv);
2014 +       }
2015 +
2016 +       /*
2017 +        * Initialize TX descriptor
2018 +        */
2019 +       rt2x00_desc_read(txd, 0, &word);
2020 +       rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
2021 +       rt2x00_desc_write(txd, 0, word);
2022 +
2023 +       rt2x00_desc_read(txd, 1, &word);
2024 +       rt2x00_set_field32(&word, TXD_W1_SD_LEN1, skb->len);
2025 +       rt2x00_set_field32(&word, TXD_W1_LAST_SEC1, 1);
2026 +       rt2x00_set_field32(&word, TXD_W1_BURST,
2027 +                          test_bit(ENTRY_TXD_BURST, &txdesc->flags));
2028 +       rt2x00_set_field32(&word, TXD_W1_SD_LEN0,
2029 +                          rt2x00dev->hw->extra_tx_headroom);
2030 +       rt2x00_set_field32(&word, TXD_W1_LAST_SEC0,
2031 +                          !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
2032 +       rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
2033 +       rt2x00_desc_write(txd, 1, word);
2034 +
2035 +       rt2x00_desc_read(txd, 2, &word);
2036 +       rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
2037 +                          skbdesc->skb_dma + rt2x00dev->hw->extra_tx_headroom);
2038 +       rt2x00_desc_write(txd, 2, word);
2039 +
2040 +       rt2x00_desc_read(txd, 3, &word);
2041 +       rt2x00_set_field32(&word, TXD_W3_WIV, 1);
2042 +       rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
2043 +       rt2x00_desc_write(txd, 3, word);
2044 +}
2045 +
2046 +/*
2047 + * TX data initialization
2048 + */
2049 +static void rt2800pci_write_beacon(struct queue_entry *entry)
2050 +{
2051 +       struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2052 +       struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
2053 +       unsigned int beacon_base;
2054 +       u32 reg;
2055 +
2056 +       /*
2057 +        * Disable beaconing while we are reloading the beacon data,
2058 +        * otherwise we might be sending out invalid data.
2059 +        */
2060 +       rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2061 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
2062 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
2063 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
2064 +       rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2065 +
2066 +       /*
2067 +        * Write entire beacon with descriptor to register.
2068 +        */
2069 +       beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
2070 +       rt2x00pci_register_multiwrite(rt2x00dev,
2071 +                                     beacon_base,
2072 +                                     skbdesc->desc, skbdesc->desc_len);
2073 +       rt2x00pci_register_multiwrite(rt2x00dev,
2074 +                                     beacon_base + skbdesc->desc_len,
2075 +                                     entry->skb->data, entry->skb->len);
2076 +
2077 +       /*
2078 +        * Clean up beacon skb.
2079 +        */
2080 +       dev_kfree_skb_any(entry->skb);
2081 +       entry->skb = NULL;
2082 +}
2083 +
2084 +static void rt2800pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
2085 +                                   const enum data_queue_qid queue)
2086 +{
2087 +       u32 reg;
2088 +
2089 +       if (queue == QID_BEACON) {
2090 +               rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2091 +               if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
2092 +                       rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
2093 +                       rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
2094 +                       rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
2095 +                       rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2096 +               }
2097 +               return;
2098 +       }
2099 +
2100 +       /* FIXME: How can be kick normal TX queues? */
2101 +}
2102 +
2103 +/*
2104 + * RX control handlers
2105 + */
2106 +static void rt2800pci_fill_rxdone(struct queue_entry *entry,
2107 +                                 struct rxdone_entry_desc *rxdesc)
2108 +{
2109 +       struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2110 +       struct queue_entry_priv_pci *entry_priv = entry->priv_data;
2111 +       __le32 *rxd = entry_priv->desc;
2112 +       __le32 *rxwi = (__le32 *)entry->skb->data;
2113 +       u32 rxd3;
2114 +       u32 rxwi0;
2115 +       u32 rxwi1;
2116 +       u32 rxwi2;
2117 +       u32 rxwi3;
2118 +       u8 mcs;
2119 +       u8 mode;
2120 +
2121 +       rt2x00_desc_read(rxd, 3, &rxd3);
2122 +       rt2x00_desc_read(rxwi, 0, &rxwi0);
2123 +       rt2x00_desc_read(rxwi, 1, &rxwi1);
2124 +       rt2x00_desc_read(rxwi, 2, &rxwi2);
2125 +       rt2x00_desc_read(rxwi, 3, &rxwi3);
2126 +
2127 +       if (rt2x00_get_field32(rxd3, RXD_W3_CRC_ERROR))
2128 +               rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
2129 +
2130 +       if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
2131 +               /*
2132 +                * FIXME: Set cipher on WEP64 when it has been decrypted,
2133 +                * at the moment we cannot determine the real cipher type yet.
2134 +                */
2135 +               rxdesc->cipher =
2136 +                   rt2x00_get_field32(rxd3, RXD_W3_DECRYPTED);
2137 +               rxdesc->cipher_status =
2138 +                   rt2x00_get_field32(rxd3, RXD_W3_CIPHER_ERROR);
2139 +       }
2140 +
2141 +       if (rxdesc->cipher != CIPHER_NONE) {
2142 +               /*
2143 +                * Hardware has stripped IV/EIV data from 802.11 frame during
2144 +                * decryption. It has provided the data seperately but rt2x00lib
2145 +                * should decide if it should be reinserted.
2146 +                */
2147 +               rxdesc->flags |= RX_FLAG_IV_STRIPPED;
2148 +
2149 +               if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
2150 +                       rxdesc->flags |= RX_FLAG_DECRYPTED;
2151 +               else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
2152 +                       rxdesc->flags |= RX_FLAG_MMIC_ERROR;
2153 +       }
2154 +
2155 +       if (rt2x00_get_field32(rxd3, RXD_W3_MY_BSS))
2156 +               rxdesc->dev_flags |= RXDONE_MY_BSS;
2157 +
2158 +       /*
2159 +        * Create the MCS value, when the mode is CCK, mask of 0x8 bit
2160 +        * to remove the short preamble flag.
2161 +        */
2162 +       mode = rt2x00_get_field32(rxwi1, RXWI_W1_PHYMODE);
2163 +       mcs = rt2x00_get_field32(rxwi1, RXWI_W1_MCS);
2164 +
2165 +       if (mode == RATE_MODE_CCK)
2166 +               mcs &= ~0x8;
2167 +
2168 +       rxdesc->signal = (mode << 8) | mcs;
2169 +
2170 +       rxdesc->rssi =
2171 +           (rt2x00_get_field32(rxwi2, RXWI_W2_RSSI0) +
2172 +            rt2x00_get_field32(rxwi2, RXWI_W2_RSSI1) +
2173 +            rt2x00_get_field32(rxwi2, RXWI_W2_RSSI2)) / 3;
2174 +
2175 +       rxdesc->noise =
2176 +           (rt2x00_get_field32(rxwi3, RXWI_W3_SNR0) +
2177 +            rt2x00_get_field32(rxwi3, RXWI_W3_SNR1)) / 2;
2178 +
2179 +       rxdesc->size = rt2x00_get_field32(rxwi0, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
2180 +
2181 +       /*
2182 +        * Remove TXWI descriptor from start of buffer.
2183 +        */
2184 +       skb_pull(entry->skb, TXWI_DESC_SIZE);
2185 +       skb_trim(entry->skb, rxdesc->size);
2186 +}
2187 +
2188 +/*
2189 + * Interrupt functions.
2190 + */
2191 +static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
2192 +{
2193 +       struct rt2x00_dev *rt2x00dev = dev_instance;
2194 +
2195 +       /* FIXME */
2196 +
2197 +       return IRQ_HANDLED;
2198 +}
2199 +
2200 +/*
2201 + * Device probe functions.
2202 + */
2203 +static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2204 +{
2205 +       struct eeprom_93cx6 eeprom;
2206 +       u32 reg;
2207 +       u16 word;
2208 +       u8 *mac;
2209 +       u8 default_lna_gain;
2210 +
2211 +       rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
2212 +
2213 +       eeprom.data = rt2x00dev;
2214 +       eeprom.register_read = rt2800pci_eepromregister_read;
2215 +       eeprom.register_write = rt2800pci_eepromregister_write;
2216 +       eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
2217 +           PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
2218 +       eeprom.reg_data_in = 0;
2219 +       eeprom.reg_data_out = 0;
2220 +       eeprom.reg_data_clock = 0;
2221 +       eeprom.reg_chip_select = 0;
2222 +
2223 +       eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
2224 +                              EEPROM_SIZE / sizeof(u16));
2225 +
2226 +       /*
2227 +        * Start validation of the data that has been read.
2228 +        */
2229 +       mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2230 +       if (!is_valid_ether_addr(mac)) {
2231 +               DECLARE_MAC_BUF(macbuf);
2232 +
2233 +               random_ether_addr(mac);
2234 +               EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
2235 +       }
2236 +
2237 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2238 +       if (word == 0xffff) {
2239 +               rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2240 +               rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
2241 +               rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
2242 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2243 +               EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2244 +       }
2245 +
2246 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2247 +       if (word != 0) {
2248 +               /* NIC configuration must always be 0. */
2249 +               word = 0;
2250 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2251 +               EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2252 +       }
2253 +
2254 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2255 +       if ((word & 0x00ff) == 0x00ff) {
2256 +               rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2257 +               rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2258 +                                  LED_MODE_TXRX_ACTIVITY);
2259 +               rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2260 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2261 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
2262 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
2263 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
2264 +               EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2265 +       }
2266 +
2267 +       /*
2268 +        * During the LNA validation we are going to use
2269 +        * lna0 as correct value. Note that EEPROM_LNA
2270 +        * is never validated.
2271 +        */
2272 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2273 +       default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2274 +
2275 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2276 +       if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2277 +               rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2278 +       if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2279 +               rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2280 +       rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2281 +
2282 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2283 +       if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2284 +               rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2285 +       if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2286 +           rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2287 +               rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2288 +                                  default_lna_gain);
2289 +       rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2290 +
2291 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2292 +       if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2293 +               rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2294 +       if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2295 +               rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2296 +       rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2297 +
2298 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2299 +       if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2300 +               rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2301 +       if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2302 +           rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2303 +               rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2304 +                                  default_lna_gain);
2305 +       rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2306 +
2307 +       return 0;
2308 +}
2309 +
2310 +static int rt2800pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2311 +{
2312 +       u32 reg;
2313 +       u16 value;
2314 +       u16 eeprom;
2315 +       u16 device;
2316 +
2317 +       /*
2318 +        * Read EEPROM word for configuration.
2319 +        */
2320 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2321 +
2322 +       /*
2323 +        * Identify RF chipset.
2324 +        * To determine the RT chip we have to read the
2325 +        * PCI header of the device.
2326 +        */
2327 +       pci_read_config_word(to_pci_dev(rt2x00dev->dev),
2328 +                            PCI_CONFIG_HEADER_DEVICE, &device);
2329 +       value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2330 +       rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
2331 +       reg = rt2x00_get_field32(reg, MAC_CSR0_ASIC_REV);
2332 +       rt2x00_set_chip(rt2x00dev, device, value, reg);
2333 +
2334 +       if (!rt2x00_rf(&rt2x00dev->chip, RF2820) &&
2335 +           !rt2x00_rf(&rt2x00dev->chip, RF2850) &&
2336 +           !rt2x00_rf(&rt2x00dev->chip, RF2720) &&
2337 +           !rt2x00_rf(&rt2x00dev->chip, RF2750)) {
2338 +               ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2339 +               return -ENODEV;
2340 +       }
2341 +
2342 +       /*
2343 +        * Read frequency offset and RF programming sequence.
2344 +        */
2345 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2346 +       rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2347 +
2348 +       /*
2349 +        * Read external LNA informations.
2350 +        */
2351 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2352 +
2353 +       if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2354 +               __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2355 +       if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2356 +               __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2357 +
2358 +       /*
2359 +        * Detect if this device has an hardware controlled radio.
2360 +        */
2361 +#ifdef CONFIG_RT2X00_LIB_RFKILL
2362 +       if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
2363 +               __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2364 +#endif /* CONFIG_RT2X00_LIB_RFKILL */
2365 +
2366 +       /*
2367 +        * Store led settings, for correct led behaviour.
2368 +        */
2369 +#ifdef CONFIG_RT2X00_LIB_LEDS
2370 +       rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2371 +       rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2372 +       rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2373 +
2374 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
2375 +#endif /* CONFIG_RT2X00_LIB_LEDS */
2376 +
2377 +       return 0;
2378 +}
2379 +
2380 +/*
2381 + * RF value list for rt2860
2382 + * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
2383 + */
2384 +static const struct rf_channel rf_vals[] = {
2385 +       { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
2386 +       { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
2387 +       { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
2388 +       { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
2389 +       { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
2390 +       { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
2391 +       { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
2392 +       { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
2393 +       { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
2394 +       { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
2395 +       { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
2396 +       { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
2397 +       { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
2398 +       { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
2399 +
2400 +       /* 802.11 UNI / HyperLan 2 */
2401 +       { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
2402 +       { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
2403 +       { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
2404 +       { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
2405 +       { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
2406 +       { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
2407 +       { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
2408 +       { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
2409 +       { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
2410 +       { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
2411 +       { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
2412 +       { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
2413 +
2414 +       /* 802.11 HyperLan 2 */
2415 +       { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
2416 +       { 102, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed793 },
2417 +       { 104, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed1a3 },
2418 +       { 108, 0x18402ecc, 0x184c0a32, 0x18178a55, 0x180ed193 },
2419 +       { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
2420 +       { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
2421 +       { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
2422 +       { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
2423 +       { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2424 +       { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2425 +       { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2426 +       { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2427 +       { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2428 +       { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2429 +       { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2430 +       { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2431 +
2432 +       /* 802.11 UNII */
2433 +       { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2434 +       { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2435 +       { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2436 +       { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2437 +       { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2438 +       { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2439 +       { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2440 +
2441 +       /* 802.11 Japan */
2442 +       { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2443 +       { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2444 +       { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2445 +       { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2446 +       { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2447 +       { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2448 +       { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2449 +};
2450 +
2451 +static int rt2800pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2452 +{
2453 +       struct hw_mode_spec *spec = &rt2x00dev->spec;
2454 +       struct channel_info *info;
2455 +       char *tx_power1;
2456 +       char *tx_power2;
2457 +       unsigned int i;
2458 +
2459 +       /*
2460 +        * Initialize all hw fields.
2461 +        */
2462 +       rt2x00dev->hw->flags =
2463 +           IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2464 +           IEEE80211_HW_SIGNAL_DBM;
2465 +       rt2x00dev->hw->extra_tx_headroom = TXWI_DESC_SIZE;
2466 +
2467 +       SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2468 +       SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2469 +                               rt2x00_eeprom_addr(rt2x00dev,
2470 +                                                  EEPROM_MAC_ADDR_0));
2471 +
2472 +       /*
2473 +        * Initialize hw_mode information.
2474 +        */
2475 +       spec->supported_bands = SUPPORT_BAND_2GHZ;
2476 +       spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2477 +
2478 +       if (rt2x00_rf(&rt2x00dev->chip, RF2820) ||
2479 +           rt2x00_rf(&rt2x00dev->chip, RF2720)) {
2480 +               spec->num_channels = 14;
2481 +               spec->channels = rf_vals;
2482 +       } else if (rt2x00_rf(&rt2x00dev->chip, RF2850) ||
2483 +                  rt2x00_rf(&rt2x00dev->chip, RF2750)) {
2484 +               spec->supported_bands |= SUPPORT_BAND_5GHZ;
2485 +               spec->num_channels = ARRAY_SIZE(rf_vals);
2486 +               spec->channels = rf_vals;
2487 +       }
2488 +
2489 +       /*
2490 +        * Create channel information array
2491 +        */
2492 +       info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2493 +       if (!info)
2494 +               return -ENOMEM;
2495 +
2496 +       spec->channels_info = info;
2497 +
2498 +       tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2499 +       tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2500 +
2501 +       for (i = 0; i < 14; i++) {
2502 +               info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
2503 +               info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
2504 +       }
2505 +
2506 +       if (spec->num_channels > 14) {
2507 +               tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
2508 +               tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
2509 +
2510 +               for (i = 14; i < spec->num_channels; i++) {
2511 +                       info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
2512 +                       info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
2513 +               }
2514 +       }
2515 +
2516 +       return 0;
2517 +}
2518 +
2519 +static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2520 +{
2521 +       int retval;
2522 +
2523 +       /*
2524 +        * Allocate eeprom data.
2525 +        */
2526 +       retval = rt2800pci_validate_eeprom(rt2x00dev);
2527 +       if (retval)
2528 +               return retval;
2529 +
2530 +       retval = rt2800pci_init_eeprom(rt2x00dev);
2531 +       if (retval)
2532 +               return retval;
2533 +
2534 +       /*
2535 +        * Initialize hw specifications.
2536 +        */
2537 +       retval = rt2800pci_probe_hw_mode(rt2x00dev);
2538 +       if (retval)
2539 +               return retval;
2540 +
2541 +       /*
2542 +        * This device requires firmware.
2543 +        */
2544 +       __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2545 +       if (!modparam_nohwcrypt)
2546 +               __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2547 +
2548 +       /*
2549 +        * Set the rssi offset.
2550 +        */
2551 +       rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2552 +
2553 +       return 0;
2554 +}
2555 +
2556 +/*
2557 + * IEEE80211 stack callback functions.
2558 + */
2559 +static int rt2800pci_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2560 +{
2561 +       struct rt2x00_dev *rt2x00dev = hw->priv;
2562 +       u32 reg;
2563 +
2564 +       rt2x00pci_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2565 +       rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
2566 +       rt2x00pci_register_write(rt2x00dev, TX_RTS_CFG, reg);
2567 +
2568 +       rt2x00pci_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2569 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
2570 +       rt2x00pci_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2571 +
2572 +       rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2573 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
2574 +       rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2575 +
2576 +       rt2x00pci_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2577 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 1);
2578 +       rt2x00pci_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2579 +
2580 +       rt2x00pci_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2581 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 1);
2582 +       rt2x00pci_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2583 +
2584 +       rt2x00pci_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2585 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 1);
2586 +       rt2x00pci_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2587 +
2588 +       rt2x00pci_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2589 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 1);
2590 +       rt2x00pci_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2591 +
2592 +       return 0;
2593 +}
2594 +
2595 +static int rt2800pci_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2596 +                            const struct ieee80211_tx_queue_params *params)
2597 +{
2598 +       struct rt2x00_dev *rt2x00dev = hw->priv;
2599 +       struct data_queue *queue;
2600 +       struct rt2x00_field32 field;
2601 +       int retval;
2602 +       u32 reg;
2603 +       u32 offset;
2604 +
2605 +       /*
2606 +        * First pass the configuration through rt2x00lib, that will
2607 +        * update the queue settings and validate the input. After that
2608 +        * we are free to update the registers based on the value
2609 +        * in the queue parameter.
2610 +        */
2611 +       retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2612 +       if (retval)
2613 +               return retval;
2614 +
2615 +       queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2616 +
2617 +       /* Update WMM TXOP register */
2618 +       if (queue_idx < 2) {
2619 +               field.bit_offset = queue_idx * 16;
2620 +               field.bit_mask = 0xffff << field.bit_offset;
2621 +
2622 +               rt2x00pci_register_read(rt2x00dev, WMM_TXOP0_CFG, &reg);
2623 +               rt2x00_set_field32(&reg, field, queue->txop);
2624 +               rt2x00pci_register_write(rt2x00dev, WMM_TXOP0_CFG, reg);
2625 +       } else if (queue_idx < 4) {
2626 +               field.bit_offset = (queue_idx - 2) * 16;
2627 +               field.bit_mask = 0xffff << field.bit_offset;
2628 +
2629 +               rt2x00pci_register_read(rt2x00dev, WMM_TXOP1_CFG, &reg);
2630 +               rt2x00_set_field32(&reg, field, queue->txop);
2631 +               rt2x00pci_register_write(rt2x00dev, WMM_TXOP1_CFG, reg);
2632 +       }
2633 +
2634 +       /* Update WMM registers */
2635 +       field.bit_offset = queue_idx * 4;
2636 +       field.bit_mask = 0xf << field.bit_offset;
2637 +
2638 +       rt2x00pci_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
2639 +       rt2x00_set_field32(&reg, field, queue->aifs);
2640 +       rt2x00pci_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
2641 +
2642 +       rt2x00pci_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
2643 +       rt2x00_set_field32(&reg, field, queue->cw_min);
2644 +       rt2x00pci_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
2645 +
2646 +       rt2x00pci_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
2647 +       rt2x00_set_field32(&reg, field, queue->cw_max);
2648 +       rt2x00pci_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
2649 +
2650 +       /* Update EDCA registers */
2651 +       if (queue_idx < 4) {
2652 +               offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
2653 +
2654 +               rt2x00pci_register_read(rt2x00dev, offset, &reg);
2655 +               rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
2656 +               rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
2657 +               rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
2658 +               rt2x00pci_register_write(rt2x00dev, offset, reg);
2659 +       }
2660 +
2661 +       return 0;
2662 +}
2663 +
2664 +static u64 rt2800pci_get_tsf(struct ieee80211_hw *hw)
2665 +{
2666 +       struct rt2x00_dev *rt2x00dev = hw->priv;
2667 +       u64 tsf;
2668 +       u32 reg;
2669 +
2670 +       rt2x00pci_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
2671 +       tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
2672 +       rt2x00pci_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
2673 +       tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
2674 +
2675 +       return tsf;
2676 +}
2677 +
2678 +static const struct ieee80211_ops rt2800pci_mac80211_ops = {
2679 +       .tx                     = rt2x00mac_tx,
2680 +       .start                  = rt2x00mac_start,
2681 +       .stop                   = rt2x00mac_stop,
2682 +       .add_interface          = rt2x00mac_add_interface,
2683 +       .remove_interface       = rt2x00mac_remove_interface,
2684 +       .config                 = rt2x00mac_config,
2685 +       .config_interface       = rt2x00mac_config_interface,
2686 +       .configure_filter       = rt2x00mac_configure_filter,
2687 +       .set_key                = rt2x00mac_set_key,
2688 +       .get_stats              = rt2x00mac_get_stats,
2689 +       .set_rts_threshold      = rt2800pci_set_rts_threshold,
2690 +       .bss_info_changed       = rt2x00mac_bss_info_changed,
2691 +       .conf_tx                = rt2800pci_conf_tx,
2692 +       .get_tx_stats           = rt2x00mac_get_tx_stats,
2693 +       .get_tsf                = rt2800pci_get_tsf,
2694 +};
2695 +
2696 +static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
2697 +       .irq_handler            = rt2800pci_interrupt,
2698 +       .probe_hw               = rt2800pci_probe_hw,
2699 +       .get_firmware_name      = rt2800pci_get_firmware_name,
2700 +       .get_firmware_crc       = rt2800pci_get_firmware_crc,
2701 +       .load_firmware          = rt2800pci_load_firmware,
2702 +       .initialize             = rt2x00pci_initialize,
2703 +       .uninitialize           = rt2x00pci_uninitialize,
2704 +       .init_rxentry           = rt2800pci_init_rxentry,
2705 +       .init_txentry           = rt2800pci_init_txentry,
2706 +       .set_device_state       = rt2800pci_set_device_state,
2707 +       .rfkill_poll            = rt2800pci_rfkill_poll,
2708 +       .link_stats             = rt2800pci_link_stats,
2709 +       .reset_tuner            = rt2800pci_reset_tuner,
2710 +       .link_tuner             = rt2800pci_link_tuner,
2711 +       .write_tx_desc          = rt2800pci_write_tx_desc,
2712 +       .write_tx_data          = rt2x00pci_write_tx_data,
2713 +       .write_beacon           = rt2800pci_write_beacon,
2714 +       .kick_tx_queue          = rt2800pci_kick_tx_queue,
2715 +       .fill_rxdone            = rt2800pci_fill_rxdone,
2716 +       .config_shared_key      = rt2800pci_config_shared_key,
2717 +       .config_pairwise_key    = rt2800pci_config_pairwise_key,
2718 +       .config_filter          = rt2800pci_config_filter,
2719 +       .config_intf            = rt2800pci_config_intf,
2720 +       .config_erp             = rt2800pci_config_erp,
2721 +       .config_ant             = rt2800pci_config_ant,
2722 +       .config                 = rt2800pci_config,
2723 +};
2724 +
2725 +static const struct data_queue_desc rt2800pci_queue_rx = {
2726 +       .entry_num              = RX_ENTRIES,
2727 +       .data_size              = DATA_FRAME_SIZE,
2728 +       .desc_size              = RXD_DESC_SIZE,
2729 +       .priv_size              = sizeof(struct queue_entry_priv_pci),
2730 +};
2731 +
2732 +static const struct data_queue_desc rt2800pci_queue_tx = {
2733 +       .entry_num              = TX_ENTRIES,
2734 +       .data_size              = DATA_FRAME_SIZE,
2735 +       .desc_size              = TXD_DESC_SIZE,
2736 +       .priv_size              = sizeof(struct queue_entry_priv_pci),
2737 +};
2738 +
2739 +static const struct data_queue_desc rt2800pci_queue_bcn = {
2740 +       .entry_num              = 8 * BEACON_ENTRIES,
2741 +       .data_size              = 0, /* No DMA required for beacons */
2742 +       .desc_size              = TXWI_DESC_SIZE,
2743 +       .priv_size              = sizeof(struct queue_entry_priv_pci),
2744 +};
2745 +
2746 +static const struct rt2x00_ops rt2800pci_ops = {
2747 +       .name           = KBUILD_MODNAME,
2748 +       .max_sta_intf   = 1,
2749 +       .max_ap_intf    = 8,
2750 +       .eeprom_size    = EEPROM_SIZE,
2751 +       .rf_size        = RF_SIZE,
2752 +       .tx_queues      = NUM_TX_QUEUES,
2753 +       .rx             = &rt2800pci_queue_rx,
2754 +       .tx             = &rt2800pci_queue_tx,
2755 +       .bcn            = &rt2800pci_queue_bcn,
2756 +       .lib            = &rt2800pci_rt2x00_ops,
2757 +       .hw             = &rt2800pci_mac80211_ops,
2758 +#ifdef CONFIG_RT2X00_LIB_DEBUGFS
2759 +       .debugfs        = &rt2800pci_rt2x00debug,
2760 +#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2761 +};
2762 +
2763 +/*
2764 + * RT2800pci module information.
2765 + */
2766 +static struct pci_device_id rt2800pci_device_table[] = {
2767 +       { PCI_DEVICE(0x1814, 0x0601), PCI_DEVICE_DATA(&rt2800pci_ops) },
2768 +       { PCI_DEVICE(0x1814, 0x0681), PCI_DEVICE_DATA(&rt2800pci_ops) },
2769 +       { PCI_DEVICE(0x1814, 0x0701), PCI_DEVICE_DATA(&rt2800pci_ops) },
2770 +       { PCI_DEVICE(0x1814, 0x0781), PCI_DEVICE_DATA(&rt2800pci_ops) },
2771 +       { PCI_DEVICE(0x1a3b, 0x1059), PCI_DEVICE_DATA(&rt2800pci_ops) },
2772 +       { 0, }
2773 +};
2774 +
2775 +MODULE_AUTHOR(DRV_PROJECT);
2776 +MODULE_VERSION(DRV_VERSION);
2777 +MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
2778 +MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
2779 +MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
2780 +MODULE_FIRMWARE(FIRMWARE_RT2860);
2781 +MODULE_LICENSE("GPL");
2782 +
2783 +static struct pci_driver rt2800pci_driver = {
2784 +       .name           = KBUILD_MODNAME,
2785 +       .id_table       = rt2800pci_device_table,
2786 +       .probe          = rt2x00pci_probe,
2787 +       .remove         = __devexit_p(rt2x00pci_remove),
2788 +       .suspend        = rt2x00pci_suspend,
2789 +       .resume         = rt2x00pci_resume,
2790 +};
2791 +
2792 +static int __init rt2800pci_init(void)
2793 +{
2794 +       return pci_register_driver(&rt2800pci_driver);
2795 +}
2796 +
2797 +static void __exit rt2800pci_exit(void)
2798 +{
2799 +       pci_unregister_driver(&rt2800pci_driver);
2800 +}
2801 +
2802 +module_init(rt2800pci_init);
2803 +module_exit(rt2800pci_exit);
2804 --- /dev/null
2805 +++ b/drivers/net/wireless/rt2x00/rt2800pci.h
2806 @@ -0,0 +1,1862 @@
2807 +/*
2808 +       Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
2809 +       <http://rt2x00.serialmonkey.com>
2810 +
2811 +       This program is free software; you can redistribute it and/or modify
2812 +       it under the terms of the GNU General Public License as published by
2813 +       the Free Software Foundation; either version 2 of the License, or
2814 +       (at your option) any later version.
2815 +
2816 +       This program is distributed in the hope that it will be useful,
2817 +       but WITHOUT ANY WARRANTY; without even the implied warranty of
2818 +       MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2819 +       GNU General Public License for more details.
2820 +
2821 +       You should have received a copy of the GNU General Public License
2822 +       along with this program; if not, write to the
2823 +       Free Software Foundation, Inc.,
2824 +       59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
2825 + */
2826 +
2827 +/*
2828 +       Module: rt2800pci
2829 +       Abstract: Data structures and registers for the rt2800pci module.
2830 +       Supported chipsets: RT2800E & RT2800ED.
2831 + */
2832 +
2833 +#ifndef RT2800PCI_H
2834 +#define RT2800PCI_H
2835 +
2836 +/*
2837 + * RF chip defines.
2838 + *
2839 + * RF2820 2.4G 2T3R
2840 + * RF2850 2.4G/5G 2T3R
2841 + * RF2720 2.4G 1T2R
2842 + * RF2750 2.4G/5G 1T2R
2843 + */
2844 +#define RF2820                         0x0001
2845 +#define RF2850                         0x0002
2846 +#define RF2720                         0x0003
2847 +#define RF2750                         0x0004
2848 +
2849 +/*
2850 + * RT2860 version
2851 + */
2852 +#define RT2860_VERSION_C               0x0100
2853 +#define RT2860_VERSION_D               0x0101
2854 +#define RT2860_VERSION_E               0x0200
2855 +
2856 +/*
2857 + * Signal information.
2858 + * Defaul offset is required for RSSI <-> dBm conversion.
2859 + */
2860 +#define MAX_SIGNAL                     0 /* FIXME */
2861 +#define MAX_RX_SSI                     0 /* FIXME */
2862 +#define DEFAULT_RSSI_OFFSET            120 /* FIXME */
2863 +
2864 +/*
2865 + * Register layout information.
2866 + */
2867 +#define CSR_REG_BASE                   0x1000
2868 +#define CSR_REG_SIZE                   0x0800
2869 +#define EEPROM_BASE                    0x0000
2870 +#define EEPROM_SIZE                    0x0110
2871 +#define BBP_BASE                       0x0000
2872 +#define BBP_SIZE                       0x0080
2873 +#define RF_BASE                                0x0000
2874 +#define RF_SIZE                                0x0014
2875 +
2876 +/*
2877 + * Number of TX queues.
2878 + */
2879 +#define NUM_TX_QUEUES                  4
2880 +
2881 +/*
2882 + * PCI registers.
2883 + */
2884 +
2885 +/*
2886 + * PCI Configuration Header
2887 + */
2888 +#define PCI_CONFIG_HEADER_VENDOR       0x0000
2889 +#define PCI_CONFIG_HEADER_DEVICE       0x0002
2890 +
2891 +/*
2892 + * E2PROM_CSR: EEPROM control register.
2893 + * RELOAD: Write 1 to reload eeprom content.
2894 + * TYPE_93C46: 1: 93c46, 0:93c66.
2895 + * LOAD_STATUS: 1:loading, 0:done.
2896 + */
2897 +#define E2PROM_CSR                     0x0004
2898 +#define E2PROM_CSR_RELOAD              FIELD32(0x00000001)
2899 +#define E2PROM_CSR_DATA_CLOCK          FIELD32(0x00000002)
2900 +#define E2PROM_CSR_CHIP_SELECT         FIELD32(0x00000004)
2901 +#define E2PROM_CSR_DATA_IN             FIELD32(0x00000008)
2902 +#define E2PROM_CSR_DATA_OUT            FIELD32(0x00000010)
2903 +#define E2PROM_CSR_TYPE_93C46          FIELD32(0x00000020)
2904 +#define E2PROM_CSR_LOAD_STATUS         FIELD32(0x00000040)
2905 +
2906 +/*
2907 + * HOST-MCU shared memory
2908 + */
2909 +#define HOST_CMD_CSR                   0x0404
2910 +#define HOST_CMD_CSR_HOST_COMMAND      FIELD32(0x000000ff)
2911 +
2912 +/*
2913 + * INT_SOURCE_CSR: Interrupt source register.
2914 + * Write one to clear corresponding bit.
2915 + * TX_FIFO_STATUS: FIFO Statistics is full, sw should read 0x171c
2916 + */
2917 +#define INT_SOURCE_CSR                 0x0200
2918 +#define INT_SOURCE_CSR_RXDELAYINT      FIELD32(0x00000001)
2919 +#define INT_SOURCE_CSR_TXDELAYINT      FIELD32(0x00000002)
2920 +#define INT_SOURCE_CSR_RX_DONE         FIELD32(0x00000004)
2921 +#define INT_SOURCE_CSR_AC0_DMA_DONE    FIELD32(0x00000008)
2922 +#define INT_SOURCE_CSR_AC1_DMA_DONE    FIELD32(0x00000010)
2923 +#define INT_SOURCE_CSR_AC2_DMA_DONE    FIELD32(0x00000020)
2924 +#define INT_SOURCE_CSR_AC3_DMA_DONE    FIELD32(0x00000040)
2925 +#define INT_SOURCE_CSR_HCCA_DMA_DONE   FIELD32(0x00000080)
2926 +#define INT_SOURCE_CSR_MGMT_DMA_DONE   FIELD32(0x00000100)
2927 +#define INT_SOURCE_CSR_MCU_COMMAND     FIELD32(0x00000200)
2928 +#define INT_SOURCE_CSR_RXTX_COHERENT   FIELD32(0x00000400)
2929 +#define INT_SOURCE_CSR_TBTT            FIELD32(0x00000800)
2930 +#define INT_SOURCE_CSR_PRE_TBTT                FIELD32(0x00001000)
2931 +#define INT_SOURCE_CSR_TX_FIFO_STATUS  FIELD32(0x00002000)
2932 +#define INT_SOURCE_CSR_AUTO_WAKEUP     FIELD32(0x00004000)
2933 +#define INT_SOURCE_CSR_GPTIMER         FIELD32(0x00008000)
2934 +#define INT_SOURCE_CSR_RX_COHERENT     FIELD32(0x00010000)
2935 +#define INT_SOURCE_CSR_TX_COHERENT     FIELD32(0x00020000)
2936 +
2937 +/*
2938 + * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
2939 + */
2940 +#define INT_MASK_CSR                   0x0204
2941 +#define INT_MASK_CSR_RXDELAYINT                FIELD32(0x00000001)
2942 +#define INT_MASK_CSR_TXDELAYINT                FIELD32(0x00000002)
2943 +#define INT_MASK_CSR_RX_DONE           FIELD32(0x00000004)
2944 +#define INT_MASK_CSR_AC0_DMA_DONE      FIELD32(0x00000008)
2945 +#define INT_MASK_CSR_AC1_DMA_DONE      FIELD32(0x00000010)
2946 +#define INT_MASK_CSR_AC2_DMA_DONE      FIELD32(0x00000020)
2947 +#define INT_MASK_CSR_AC3_DMA_DONE      FIELD32(0x00000040)
2948 +#define INT_MASK_CSR_HCCA_DMA_DONE     FIELD32(0x00000080)
2949 +#define INT_MASK_CSR_MGMT_DMA_DONE     FIELD32(0x00000100)
2950 +#define INT_MASK_CSR_MCU_COMMAND       FIELD32(0x00000200)
2951 +#define INT_MASK_CSR_RX_COHERENT       FIELD32(0x40000000)
2952 +#define INT_MASK_CSR_TX_COHERENT       FIELD32(0x80000000)
2953 +
2954 +/*
2955 + * WPDMA_GLO_CFG
2956 + */
2957 +#define WPDMA_GLO_CFG                  0x0208
2958 +#define WPDMA_GLO_CFG_ENABLE_TX_DMA    FIELD32(0x00000001)
2959 +#define WPDMA_GLO_CFG_TX_DMA_BUSY      FIELD32(0x00000002)
2960 +#define WPDMA_GLO_CFG_ENABLE_RX_DMA    FIELD32(0x00000004)
2961 +#define WPDMA_GLO_CFG_RX_DMA_BUSY      FIELD32(0x00000008)
2962 +#define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE        FIELD32(0x00000030)
2963 +#define WPDMA_GLO_CFG_TX_WRITEBACK_DONE        FIELD32(0x00000040)
2964 +#define WPDMA_GLO_CFG_BIG_ENDIAN       FIELD32(0x00000080)
2965 +#define WPDMA_GLO_CFG_RX_HDR_SCATTER   FIELD32(0x0000ff00)
2966 +#define WPDMA_GLO_CFG_HDR_SEG_LEN      FIELD32(0xffff0000)
2967 +
2968 +/*
2969 + * WPDMA_RST_IDX
2970 + */
2971 +#define WPDMA_RST_IDX                  0x020c
2972 +#define WPDMA_RST_IDX_DTX_IDX0         FIELD32(0x00000001)
2973 +#define WPDMA_RST_IDX_DTX_IDX1         FIELD32(0x00000002)
2974 +#define WPDMA_RST_IDX_DTX_IDX2         FIELD32(0x00000004)
2975 +#define WPDMA_RST_IDX_DTX_IDX3         FIELD32(0x00000008)
2976 +#define WPDMA_RST_IDX_DTX_IDX4         FIELD32(0x00000010)
2977 +#define WPDMA_RST_IDX_DTX_IDX5         FIELD32(0x00000020)
2978 +#define WPDMA_RST_IDX_DRX_IDX0         FIELD32(0x00010000)
2979 +
2980 +/*
2981 + * DELAY_INT_CFG
2982 + */
2983 +#define DELAY_INT_CFG                  0x0210
2984 +#define DELAY_INT_CFG_RXMAX_PTIME      FIELD32(0x000000ff)
2985 +#define DELAY_INT_CFG_RXMAX_PINT       FIELD32(0x00007f00)
2986 +#define DELAY_INT_CFG_RXDLY_INT_EN     FIELD32(0x00008000)
2987 +#define DELAY_INT_CFG_TXMAX_PTIME      FIELD32(0x00ff0000)
2988 +#define DELAY_INT_CFG_TXMAX_PINT       FIELD32(0x7f000000)
2989 +#define DELAY_INT_CFG_TXDLY_INT_EN     FIELD32(0x80000000)
2990 +
2991 +/*
2992 + * WMM_AIFSN_CFG: Aifsn for each EDCA AC
2993 + * AIFSN0: AC_BE
2994 + * AIFSN1: AC_BK
2995 + * AIFSN1: AC_VI
2996 + * AIFSN1: AC_VO
2997 + */
2998 +#define WMM_AIFSN_CFG                  0x0214
2999 +#define WMM_AIFSN_CFG_AIFSN0           FIELD32(0x0000000f)
3000 +#define WMM_AIFSN_CFG_AIFSN1           FIELD32(0x000000f0)
3001 +#define WMM_AIFSN_CFG_AIFSN2           FIELD32(0x00000f00)
3002 +#define WMM_AIFSN_CFG_AIFSN3           FIELD32(0x0000f000)
3003 +
3004 +/*
3005 + * WMM_CWMIN_CSR: CWmin for each EDCA AC
3006 + * CWMIN0: AC_BE
3007 + * CWMIN1: AC_BK
3008 + * CWMIN1: AC_VI
3009 + * CWMIN1: AC_VO
3010 + */
3011 +#define WMM_CWMIN_CFG                  0x0218
3012 +#define WMM_CWMIN_CFG_CWMIN0           FIELD32(0x0000000f)
3013 +#define WMM_CWMIN_CFG_CWMIN1           FIELD32(0x000000f0)
3014 +#define WMM_CWMIN_CFG_CWMIN2           FIELD32(0x00000f00)
3015 +#define WMM_CWMIN_CFG_CWMIN3           FIELD32(0x0000f000)
3016 +
3017 +/*
3018 + * WMM_CWMAX_CSR: CWmax for each EDCA AC
3019 + * CWMAX0: AC_BE
3020 + * CWMAX1: AC_BK
3021 + * CWMAX1: AC_VI
3022 + * CWMAX1: AC_VO
3023 + */
3024 +#define WMM_CWMAX_CFG                  0x021c
3025 +#define WMM_CWMAX_CFG_CWMAX0           FIELD32(0x0000000f)
3026 +#define WMM_CWMAX_CFG_CWMAX1           FIELD32(0x000000f0)
3027 +#define WMM_CWMAX_CFG_CWMAX2           FIELD32(0x00000f00)
3028 +#define WMM_CWMAX_CFG_CWMAX3           FIELD32(0x0000f000)
3029 +
3030 +/*
3031 + * AC_TXOP0: AC_BK/AC_BE TXOP register
3032 + * AC0TXOP: AC_BK in unit of 32us
3033 + * AC1TXOP: AC_BE in unit of 32us
3034 + */
3035 +#define WMM_TXOP0_CFG                  0x0220
3036 +#define WMM_TXOP0_CFG_AC0TXOP          FIELD32(0x0000ffff)
3037 +#define WMM_TXOP0_CFG_AC1TXOP          FIELD32(0xffff0000)
3038 +
3039 +/*
3040 + * AC_TXOP1: AC_VO/AC_VI TXOP register
3041 + * AC2TXOP: AC_VI in unit of 32us
3042 + * AC3TXOP: AC_VO in unit of 32us
3043 + */
3044 +#define WMM_TXOP1_CFG                  0x0224
3045 +#define WMM_TXOP1_CFG_AC2TXOP          FIELD32(0x0000ffff)
3046 +#define WMM_TXOP1_CFG_AC3TXOP          FIELD32(0xffff0000)
3047 +
3048 +/*
3049 + * RINGREG_DIFF
3050 + */
3051 +#define RINGREG_DIFF                   0x0010
3052 +
3053 +/*
3054 + * GPIO_CTRL_CFG:
3055 + */
3056 +#define GPIO_CTRL_CFG                  0x0228
3057 +#define GPIO_CTRL_CFG_BIT0             FIELD32(0x00000001)
3058 +#define GPIO_CTRL_CFG_BIT1             FIELD32(0x00000002)
3059 +#define GPIO_CTRL_CFG_BIT2             FIELD32(0x00000004)
3060 +#define GPIO_CTRL_CFG_BIT3             FIELD32(0x00000008)
3061 +#define GPIO_CTRL_CFG_BIT4             FIELD32(0x00000010)
3062 +#define GPIO_CTRL_CFG_BIT5             FIELD32(0x00000020)
3063 +#define GPIO_CTRL_CFG_BIT6             FIELD32(0x00000040)
3064 +#define GPIO_CTRL_CFG_BIT7             FIELD32(0x00000080)
3065 +#define GPIO_CTRL_CFG_BIT8             FIELD32(0x00000100)
3066 +
3067 +/*
3068 + * MCU_CMD_CFG
3069 + */
3070 +#define MCU_CMD_CFG                    0x022c
3071 +
3072 +/*
3073 + * AC_BK register offsets
3074 + */
3075 +#define TX_BASE_PTR0                   0x0230
3076 +#define TX_MAX_CNT0                    0x0234
3077 +#define TX_CTX_IDX0                    0x0238
3078 +#define TX_DTX_IDX0                    0x023c
3079 +
3080 +/*
3081 + * AC_BE register offsets
3082 + */
3083 +#define TX_BASE_PTR1                   0x0240
3084 +#define TX_MAX_CNT1                    0x0244
3085 +#define TX_CTX_IDX1                    0x0248
3086 +#define TX_DTX_IDX1                    0x024c
3087 +
3088 +/*
3089 + * AC_VI register offsets
3090 + */
3091 +#define TX_BASE_PTR2                   0x0250
3092 +#define TX_MAX_CNT2                    0x0254
3093 +#define TX_CTX_IDX2                    0x0258
3094 +#define TX_DTX_IDX2                    0x025c
3095 +
3096 +/*
3097 + * AC_VO register offsets
3098 + */
3099 +#define TX_BASE_PTR3                   0x0260
3100 +#define TX_MAX_CNT3                    0x0264
3101 +#define TX_CTX_IDX3                    0x0268
3102 +#define TX_DTX_IDX3                    0x026c
3103 +
3104 +/*
3105 + * HCCA register offsets
3106 + */
3107 +#define TX_BASE_PTR4                   0x0270
3108 +#define TX_MAX_CNT4                    0x0274
3109 +#define TX_CTX_IDX4                    0x0278
3110 +#define TX_DTX_IDX4                    0x027c
3111 +
3112 +/*
3113 + * MGMT register offsets
3114 + */
3115 +#define TX_BASE_PTR5                   0x0280
3116 +#define TX_MAX_CNT5                    0x0284
3117 +#define TX_CTX_IDX5                    0x0288
3118 +#define TX_DTX_IDX5                    0x028c
3119 +
3120 +/*
3121 + * RX register offsets
3122 + */
3123 +#define RX_BASE_PTR                    0x0290
3124 +#define RX_MAX_CNT                     0x0294
3125 +#define RX_CRX_IDX                     0x0298
3126 +#define RX_DRX_IDX                     0x029c
3127 +
3128 +/*
3129 + * PBF_SYS_CTRL
3130 + * HOST_RAM_WRITE: enable Host program ram write selection
3131 + */
3132 +#define PBF_SYS_CTRL                   0x0400
3133 +#define PBF_SYS_CTRL_READY             FIELD32(0x00000080)
3134 +#define PBF_SYS_CTRL_HOST_RAM_WRITE    FIELD32(0x00010000)
3135 +
3136 +/*
3137 + * PBF  registers
3138 + * Most are for debug. Driver doesn't touch PBF register.
3139 + */
3140 +#define PBF_CFG                                0x0408
3141 +#define PBF_MAX_PCNT                   0x040c
3142 +#define PBF_CTRL                       0x0410
3143 +#define PBF_INT_STA                    0x0414
3144 +#define PBF_INT_ENA                    0x0418
3145 +
3146 +/*
3147 + * BCN_OFFSET0:
3148 + */
3149 +#define BCN_OFFSET0                    0x042c
3150 +#define BCN_OFFSET0_BCN0               FIELD32(0x000000ff)
3151 +#define BCN_OFFSET0_BCN1               FIELD32(0x0000ff00)
3152 +#define BCN_OFFSET0_BCN2               FIELD32(0x00ff0000)
3153 +#define BCN_OFFSET0_BCN3               FIELD32(0xff000000)
3154 +
3155 +/*
3156 + * BCN_OFFSET1:
3157 + */
3158 +#define BCN_OFFSET1                    0x0430
3159 +#define BCN_OFFSET1_BCN4               FIELD32(0x000000ff)
3160 +#define BCN_OFFSET1_BCN5               FIELD32(0x0000ff00)
3161 +#define BCN_OFFSET1_BCN6               FIELD32(0x00ff0000)
3162 +#define BCN_OFFSET1_BCN7               FIELD32(0xff000000)
3163 +
3164 +/*
3165 + * PBF  registers
3166 + * Most are for debug. Driver doesn't touch PBF register.
3167 + */
3168 +#define TXRXQ_PCNT                     0x0438
3169 +#define PBF_DBG                                0x043c
3170 +
3171 +/*
3172 + * MAC Control/Status Registers(CSR).
3173 + * Some values are set in TU, whereas 1 TU == 1024 us.
3174 + */
3175 +
3176 +/*
3177 + * MAC_CSR0: ASIC revision number.
3178 + * ASIC_REV: 0
3179 + * ASIC_VER: 2860
3180 + */
3181 +#define MAC_CSR0                       0x1000
3182 +#define MAC_CSR0_ASIC_REV              FIELD32(0x0000ffff)
3183 +#define MAC_CSR0_ASIC_VER              FIELD32(0xffff0000)
3184 +
3185 +/*
3186 + * MAC_SYS_CTRL:
3187 + */
3188 +#define MAC_SYS_CTRL                   0x1004
3189 +#define MAC_SYS_CTRL_RESET_CSR         FIELD32(0x00000001)
3190 +#define MAC_SYS_CTRL_RESET_BBP         FIELD32(0x00000002)
3191 +#define MAC_SYS_CTRL_ENABLE_TX         FIELD32(0x00000004)
3192 +#define MAC_SYS_CTRL_ENABLE_RX         FIELD32(0x00000008)
3193 +#define MAC_SYS_CTRL_CONTINUOUS_TX     FIELD32(0x00000010)
3194 +#define MAC_SYS_CTRL_LOOPBACK          FIELD32(0x00000020)
3195 +#define MAC_SYS_CTRL_WLAN_HALT         FIELD32(0x00000040)
3196 +#define MAC_SYS_CTRL_RX_TIMESTAMP      FIELD32(0x00000080)
3197 +
3198 +/*
3199 + * MAC_ADDR_DW0: STA MAC register 0
3200 + */
3201 +#define MAC_ADDR_DW0                   0x1008
3202 +#define MAC_ADDR_DW0_BYTE0             FIELD32(0x000000ff)
3203 +#define MAC_ADDR_DW0_BYTE1             FIELD32(0x0000ff00)
3204 +#define MAC_ADDR_DW0_BYTE2             FIELD32(0x00ff0000)
3205 +#define MAC_ADDR_DW0_BYTE3             FIELD32(0xff000000)
3206 +
3207 +/*
3208 + * MAC_ADDR_DW1: STA MAC register 1
3209 + * UNICAST_TO_ME_MASK:
3210 + * Used to mask off bits from byte 5 of the MAC address
3211 + * to determine the UNICAST_TO_ME bit for RX frames.
3212 + * The full mask is complemented by BSS_ID_MASK:
3213 + *    MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
3214 + */
3215 +#define MAC_ADDR_DW1                   0x100c
3216 +#define MAC_ADDR_DW1_BYTE4             FIELD32(0x000000ff)
3217 +#define MAC_ADDR_DW1_BYTE5             FIELD32(0x0000ff00)
3218 +#define MAC_ADDR_DW1_UNICAST_TO_ME_MASK        FIELD32(0x00ff0000)
3219 +
3220 +/*
3221 + * MAC_BSSID_DW0: BSSID register 0
3222 + */
3223 +#define MAC_BSSID_DW0                  0x1010
3224 +#define MAC_BSSID_DW0_BYTE0            FIELD32(0x000000ff)
3225 +#define MAC_BSSID_DW0_BYTE1            FIELD32(0x0000ff00)
3226 +#define MAC_BSSID_DW0_BYTE2            FIELD32(0x00ff0000)
3227 +#define MAC_BSSID_DW0_BYTE3            FIELD32(0xff000000)
3228 +
3229 +/*
3230 + * MAC_BSSID_DW1: BSSID register 1
3231 + * BSS_ID_MASK:
3232 + *     0: 1-BSSID mode (BSS index = 0)
3233 + *     1: 2-BSSID mode (BSS index: Byte5, bit 0)
3234 + *     2: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
3235 + *     3: 8-BSSID mode (BSS index: byte5, bit 0 - 2)
3236 + * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the
3237 + * BSSID. This will make sure that those bits will be ignored
3238 + * when determining the MY_BSS of RX frames.
3239 + */
3240 +#define MAC_BSSID_DW1                  0x1014
3241 +#define MAC_BSSID_DW1_BYTE4            FIELD32(0x000000ff)
3242 +#define MAC_BSSID_DW1_BYTE5            FIELD32(0x0000ff00)
3243 +#define MAC_BSSID_DW1_BSS_ID_MASK      FIELD32(0x00030000)
3244 +#define MAC_BSSID_DW1_BSS_BCN_NUM      FIELD32(0x001c0000)
3245 +
3246 +/*
3247 + * MAX_LEN_CFG: Maximum frame length register.
3248 + * MAX_MPDU: rt2860b max 16k bytes
3249 + * MAX_PSDU: Maximum PSDU length
3250 + *     (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
3251 + */
3252 +#define MAX_LEN_CFG                    0x1018
3253 +#define MAX_LEN_CFG_MAX_MPDU           FIELD32(0x00000fff)
3254 +#define MAX_LEN_CFG_MAX_PSDU           FIELD32(0x00003000)
3255 +#define MAX_LEN_CFG_MIN_PSDU           FIELD32(0x0000c000)
3256 +#define MAX_LEN_CFG_MIN_MPDU           FIELD32(0x000f0000)
3257 +
3258 +/*
3259 + * BBP_CSR_CFG: BBP serial control register
3260 + * VALUE: Register value to program into BBP
3261 + * REG_NUM: Selected BBP register
3262 + * READ_CONTROL: 0 write BBP, 1 read BBP
3263 + * BUSY: ASIC is busy executing BBP commands
3264 + * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks
3265 + * BBP_RW_MODE: 0 serial, 1 paralell
3266 + */
3267 +#define BBP_CSR_CFG                    0x101c
3268 +#define BBP_CSR_CFG_VALUE              FIELD32(0x000000ff)
3269 +#define BBP_CSR_CFG_REGNUM             FIELD32(0x0000ff00)
3270 +#define BBP_CSR_CFG_READ_CONTROL       FIELD32(0x00010000)
3271 +#define BBP_CSR_CFG_BUSY               FIELD32(0x00020000)
3272 +#define BBP_CSR_CFG_BBP_PAR_DUR                FIELD32(0x00040000)
3273 +#define BBP_CSR_CFG_BBP_RW_MODE                FIELD32(0x00080000)
3274 +
3275 +/*
3276 + * RF_CSR_CFG0: RF control register
3277 + * REGID_AND_VALUE: Register value to program into RF
3278 + * BITWIDTH: Selected RF register
3279 + * STANDBYMODE: 0 high when standby, 1 low when standby
3280 + * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate
3281 + * BUSY: ASIC is busy executing RF commands
3282 + */
3283 +#define RF_CSR_CFG0                    0x1020
3284 +#define RF_CSR_CFG0_REGID_AND_VALUE    FIELD32(0x00ffffff)
3285 +#define RF_CSR_CFG0_BITWIDTH           FIELD32(0x1f000000)
3286 +#define RF_CSR_CFG0_REG_VALUE_BW       FIELD32(0x1fffffff)
3287 +#define RF_CSR_CFG0_STANDBYMODE                FIELD32(0x20000000)
3288 +#define RF_CSR_CFG0_SEL                        FIELD32(0x40000000)
3289 +#define RF_CSR_CFG0_BUSY               FIELD32(0x80000000)
3290 +
3291 +/*
3292 + * RF_CSR_CFG1: RF control register
3293 + * REGID_AND_VALUE: Register value to program into RF
3294 + * RFGAP: Gap between BB_CONTROL_RF and RF_LE
3295 + *        0: 3 system clock cycle (37.5usec)
3296 + *        1: 5 system clock cycle (62.5usec)
3297 + */
3298 +#define RF_CSR_CFG1                    0x1024
3299 +#define RF_CSR_CFG1_REGID_AND_VALUE    FIELD32(0x00ffffff)
3300 +#define RF_CSR_CFG1_RFGAP              FIELD32(0x1f000000)
3301 +
3302 +/*
3303 + * RF_CSR_CFG2: RF control register
3304 + * VALUE: Register value to program into RF
3305 + * RFGAP: Gap between BB_CONTROL_RF and RF_LE
3306 + *        0: 3 system clock cycle (37.5usec)
3307 + *        1: 5 system clock cycle (62.5usec)
3308 + */
3309 +#define RF_CSR_CFG2                    0x1028
3310 +#define RF_CSR_CFG2_VALUE              FIELD32(0x00ffffff)
3311 +
3312 +/*
3313 + * LED_CFG: LED control
3314 + * color LED's:
3315 + *   0: off
3316 + *   1: blinking upon TX2
3317 + *   2: periodic slow blinking
3318 + *   3: always on
3319 + * LED polarity:
3320 + *   0: active low
3321 + *   1: active high
3322 + */
3323 +#define LED_CFG                                0x102c
3324 +#define LED_CFG_ON_PERIOD              FIELD32(0x000000ff)
3325 +#define LED_CFG_OFF_PERIOD             FIELD32(0x0000ff00)
3326 +#define LED_CFG_SLOW_BLINK_PERIOD      FIELD32(0x003f0000)
3327 +#define LED_CFG_R_LED_MODE             FIELD32(0x03000000)
3328 +#define LED_CFG_G_LED_MODE             FIELD32(0x0c000000)
3329 +#define LED_CFG_Y_LED_MODE             FIELD32(0x30000000)
3330 +#define LED_CFG_LED_POLAR              FIELD32(0x40000000)
3331 +
3332 +/*
3333 + * XIFS_TIME_CFG: MAC timing
3334 + * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX
3335 + * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX
3336 + * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX
3337 + *     when MAC doesn't reference BBP signal BBRXEND
3338 + * EIFS: unit 1us
3339 + * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer
3340 + *
3341 + */
3342 +#define XIFS_TIME_CFG                  0x1100
3343 +#define XIFS_TIME_CFG_CCKM_SIFS_TIME   FIELD32(0x000000ff)
3344 +#define XIFS_TIME_CFG_OFDM_SIFS_TIME   FIELD32(0x0000ff00)
3345 +#define XIFS_TIME_CFG_OFDM_XIFS_TIME   FIELD32(0x000f0000)
3346 +#define XIFS_TIME_CFG_EIFS             FIELD32(0x1ff00000)
3347 +#define XIFS_TIME_CFG_BB_RXEND_ENABLE  FIELD32(0x20000000)
3348 +
3349 +/*
3350 + * BKOFF_SLOT_CFG:
3351 + */
3352 +#define BKOFF_SLOT_CFG                 0x1104
3353 +#define BKOFF_SLOT_CFG_SLOT_TIME       FIELD32(0x000000ff)
3354 +#define BKOFF_SLOT_CFG_CC_DELAY_TIME   FIELD32(0x0000ff00)
3355 +
3356 +/*
3357 + * NAV_TIME_CFG:
3358 + */
3359 +#define NAV_TIME_CFG                   0x1108
3360 +#define NAV_TIME_CFG_SIFS              FIELD32(0x000000ff)
3361 +#define NAV_TIME_CFG_SLOT_TIME         FIELD32(0x0000ff00)
3362 +#define NAV_TIME_CFG_EIFS              FIELD32(0x01ff0000)
3363 +#define NAV_TIME_ZERO_SIFS             FIELD32(0x02000000)
3364 +
3365 +/*
3366 + * CH_TIME_CFG: count as channel busy
3367 + */
3368 +#define CH_TIME_CFG                    0x110c
3369 +
3370 +/*
3371 + * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us
3372 + */
3373 +#define PBF_LIFE_TIMER                 0x1110
3374 +
3375 +/*
3376 + * BCN_TIME_CFG:
3377 + * BEACON_INTERVAL: in unit of 1/16 TU
3378 + * TSF_TICKING: Enable TSF auto counting
3379 + * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
3380 + * BEACON_GEN: Enable beacon generator
3381 + */
3382 +#define BCN_TIME_CFG                   0x1114
3383 +#define BCN_TIME_CFG_BEACON_INTERVAL   FIELD32(0x0000ffff)
3384 +#define BCN_TIME_CFG_TSF_TICKING       FIELD32(0x00010000)
3385 +#define BCN_TIME_CFG_TSF_SYNC          FIELD32(0x00060000)
3386 +#define BCN_TIME_CFG_TBTT_ENABLE       FIELD32(0x00080000)
3387 +#define BCN_TIME_CFG_BEACON_GEN                FIELD32(0x00100000)
3388 +#define BCN_TIME_CFG_TX_TIME_COMPENSATE        FIELD32(0xf0000000)
3389 +
3390 +/*
3391 + * TBTT_SYNC_CFG:
3392 + */
3393 +#define TBTT_SYNC_CFG                  0x1118
3394 +
3395 +/*
3396 + * TSF_TIMER_DW0: Local lsb TSF timer, read-only
3397 + */
3398 +#define TSF_TIMER_DW0                  0x111c
3399 +#define TSF_TIMER_DW0_LOW_WORD         FIELD32(0xffffffff)
3400 +
3401 +/*
3402 + * TSF_TIMER_DW1: Local msb TSF timer, read-only
3403 + */
3404 +#define TSF_TIMER_DW1                  0x1120
3405 +#define TSF_TIMER_DW1_HIGH_WORD                FIELD32(0xffffffff)
3406 +
3407 +/*
3408 + * TBTT_TIMER: TImer remains till next TBTT, read-only
3409 + */
3410 +#define TBTT_TIMER                     0x1124
3411 +
3412 +/*
3413 + * INT_TIMER_CFG:
3414 + */
3415 +#define INT_TIMER_CFG                  0x1128
3416 +
3417 +/*
3418 + * INT_TIMER_EN: GP-timer and pre-tbtt Int enable
3419 + */
3420 +#define INT_TIMER_EN                   0x112c
3421 +
3422 +/*
3423 + * CH_IDLE_STA: channel idle time
3424 + */
3425 +#define CH_IDLE_STA                    0x1130
3426 +
3427 +/*
3428 + * CH_BUSY_STA: channel busy time
3429 + */
3430 +#define CH_BUSY_STA                    0x1134
3431 +
3432 +/*
3433 + * MAC_STATUS_CFG:
3434 + * BBP_RF_BUSY: When set to 0, BBP and RF are stable.
3435 + *     if 1 or higher one of the 2 registers is busy.
3436 + */
3437 +#define MAC_STATUS_CFG                 0x1200
3438 +#define MAC_STATUS_CFG_BBP_RF_BUSY     FIELD32(0x00000003)
3439 +
3440 +/*
3441 + * PWR_PIN_CFG:
3442 + */
3443 +#define PWR_PIN_CFG                    0x1204
3444 +
3445 +/*
3446 + * AUTOWAKEUP_CFG: Manual power control / status register
3447 + * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set
3448 + * AUTOWAKE: 0:sleep, 1:awake
3449 + */
3450 +#define AUTOWAKEUP_CFG                 0x1208
3451 +#define AUTOWAKEUP_CFG_AUTO_LEAD_TIME  FIELD32(0x000000ff)
3452 +#define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE        FIELD32(0x00007f00)
3453 +#define AUTOWAKEUP_CFG_AUTOWAKE                FIELD32(0x00008000)
3454 +
3455 +/*
3456 + * EDCA_AC0_CFG:
3457 + */
3458 +#define EDCA_AC0_CFG                   0x1300
3459 +#define EDCA_AC0_CFG_AC_TX_OP          FIELD32(0x000000ff)
3460 +#define EDCA_AC0_CFG_AIFSN             FIELD32(0x00000f00)
3461 +#define EDCA_AC0_CFG_CWMIN             FIELD32(0x0000f000)
3462 +#define EDCA_AC0_CFG_CWMAX             FIELD32(0x000f0000)
3463 +
3464 +/*
3465 + * EDCA_AC1_CFG:
3466 + */
3467 +#define EDCA_AC1_CFG                   0x1304
3468 +#define EDCA_AC1_CFG_AC_TX_OP          FIELD32(0x000000ff)
3469 +#define EDCA_AC1_CFG_AIFSN             FIELD32(0x00000f00)
3470 +#define EDCA_AC1_CFG_CWMIN             FIELD32(0x0000f000)
3471 +#define EDCA_AC1_CFG_CWMAX             FIELD32(0x000f0000)
3472 +
3473 +/*
3474 + * EDCA_AC2_CFG:
3475 + */
3476 +#define EDCA_AC2_CFG                   0x1308
3477 +#define EDCA_AC2_CFG_AC_TX_OP          FIELD32(0x000000ff)
3478 +#define EDCA_AC2_CFG_AIFSN             FIELD32(0x00000f00)
3479 +#define EDCA_AC2_CFG_CWMIN             FIELD32(0x0000f000)
3480 +#define EDCA_AC2_CFG_CWMAX             FIELD32(0x000f0000)
3481 +
3482 +/*
3483 + * EDCA_AC3_CFG:
3484 + */
3485 +#define EDCA_AC3_CFG                   0x130c
3486 +#define EDCA_AC3_CFG_AC_TX_OP          FIELD32(0x000000ff)
3487 +#define EDCA_AC3_CFG_AIFSN             FIELD32(0x00000f00)
3488 +#define EDCA_AC3_CFG_CWMIN             FIELD32(0x0000f000)
3489 +#define EDCA_AC3_CFG_CWMAX             FIELD32(0x000f0000)
3490 +
3491 +/*
3492 + * EDCA_TID_AC_MAP:
3493 + */
3494 +#define EDCA_TID_AC_MAP                        0x1310
3495 +
3496 +/*
3497 + * TX_PWR_CFG_0:
3498 + */
3499 +#define TX_PWR_CFG_0                   0x1314
3500 +#define TX_PWR_CFG_0_1MBS              FIELD32(0x0000000f)
3501 +#define TX_PWR_CFG_0_2MBS              FIELD32(0x000000f0)
3502 +#define TX_PWR_CFG_0_55MBS             FIELD32(0x00000f00)
3503 +#define TX_PWR_CFG_0_11MBS             FIELD32(0x0000f000)
3504 +#define TX_PWR_CFG_0_6MBS              FIELD32(0x000f0000)
3505 +#define TX_PWR_CFG_0_9MBS              FIELD32(0x00f00000)
3506 +#define TX_PWR_CFG_0_12MBS             FIELD32(0x0f000000)
3507 +#define TX_PWR_CFG_0_18MBS             FIELD32(0xf0000000)
3508 +
3509 +/*
3510 + * TX_PWR_CFG_1:
3511 + */
3512 +#define TX_PWR_CFG_1                   0x1318
3513 +#define TX_PWR_CFG_1_24MBS             FIELD32(0x0000000f)
3514 +#define TX_PWR_CFG_1_36MBS             FIELD32(0x000000f0)
3515 +#define TX_PWR_CFG_1_48MBS             FIELD32(0x00000f00)
3516 +#define TX_PWR_CFG_1_54MBS             FIELD32(0x0000f000)
3517 +#define TX_PWR_CFG_1_MCS0              FIELD32(0x000f0000)
3518 +#define TX_PWR_CFG_1_MCS1              FIELD32(0x00f00000)
3519 +#define TX_PWR_CFG_1_MCS2              FIELD32(0x0f000000)
3520 +#define TX_PWR_CFG_1_MCS3              FIELD32(0xf0000000)
3521 +
3522 +/*
3523 + * TX_PWR_CFG_2:
3524 + */
3525 +#define TX_PWR_CFG_2                   0x131c
3526 +#define TX_PWR_CFG_2_MCS4              FIELD32(0x0000000f)
3527 +#define TX_PWR_CFG_2_MCS5              FIELD32(0x000000f0)
3528 +#define TX_PWR_CFG_2_MCS6              FIELD32(0x00000f00)
3529 +#define TX_PWR_CFG_2_MCS7              FIELD32(0x0000f000)
3530 +#define TX_PWR_CFG_2_MCS8              FIELD32(0x000f0000)
3531 +#define TX_PWR_CFG_2_MCS9              FIELD32(0x00f00000)
3532 +#define TX_PWR_CFG_2_MCS10             FIELD32(0x0f000000)
3533 +#define TX_PWR_CFG_2_MCS11             FIELD32(0xf0000000)
3534 +
3535 +/*
3536 + * TX_PWR_CFG_3:
3537 + */
3538 +#define TX_PWR_CFG_3                   0x1320
3539 +#define TX_PWR_CFG_3_MCS12             FIELD32(0x0000000f)
3540 +#define TX_PWR_CFG_3_MCS13             FIELD32(0x000000f0)
3541 +#define TX_PWR_CFG_3_MCS14             FIELD32(0x00000f00)
3542 +#define TX_PWR_CFG_3_MCS15             FIELD32(0x0000f000)
3543 +#define TX_PWR_CFG_3_UKNOWN1           FIELD32(0x000f0000)
3544 +#define TX_PWR_CFG_3_UKNOWN2           FIELD32(0x00f00000)
3545 +#define TX_PWR_CFG_3_UKNOWN3           FIELD32(0x0f000000)
3546 +#define TX_PWR_CFG_3_UKNOWN4           FIELD32(0xf0000000)
3547 +
3548 +/*
3549 + * TX_PWR_CFG_4:
3550 + */
3551 +#define TX_PWR_CFG_4                   0x1324
3552 +#define TX_PWR_CFG_4_UKNOWN5           FIELD32(0x0000000f)
3553 +#define TX_PWR_CFG_4_UKNOWN6           FIELD32(0x000000f0)
3554 +#define TX_PWR_CFG_4_UKNOWN7           FIELD32(0x00000f00)
3555 +#define TX_PWR_CFG_4_UKNOWN8           FIELD32(0x0000f000)
3556 +
3557 +/*
3558 + * TX_PIN_CFG:
3559 + */
3560 +#define TX_PIN_CFG                     0x1328
3561 +#define TX_PIN_CFG_PA_PE_A0_EN         FIELD32(0x00000001)
3562 +#define TX_PIN_CFG_PA_PE_G0_EN         FIELD32(0x00000002)
3563 +#define TX_PIN_CFG_PA_PE_A1_EN         FIELD32(0x00000004)
3564 +#define TX_PIN_CFG_PA_PE_G1_EN         FIELD32(0x00000008)
3565 +#define TX_PIN_CFG_PA_PE_A0_POL                FIELD32(0x00000010)
3566 +#define TX_PIN_CFG_PA_PE_G0_POL                FIELD32(0x00000020)
3567 +#define TX_PIN_CFG_PA_PE_A1_POL                FIELD32(0x00000040)
3568 +#define TX_PIN_CFG_PA_PE_G1_POL                FIELD32(0x00000080)
3569 +#define TX_PIN_CFG_LNA_PE_A0_EN                FIELD32(0x00000100)
3570 +#define TX_PIN_CFG_LNA_PE_G0_EN                FIELD32(0x00000200)
3571 +#define TX_PIN_CFG_LNA_PE_A1_EN                FIELD32(0x00000400)
3572 +#define TX_PIN_CFG_LNA_PE_G1_EN                FIELD32(0x00000800)
3573 +#define TX_PIN_CFG_LNA_PE_A0_POL       FIELD32(0x00001000)
3574 +#define TX_PIN_CFG_LNA_PE_G0_POL       FIELD32(0x00002000)
3575 +#define TX_PIN_CFG_LNA_PE_A1_POL       FIELD32(0x00004000)
3576 +#define TX_PIN_CFG_LNA_PE_G1_POL       FIELD32(0x00008000)
3577 +#define TX_PIN_CFG_RFTR_EN             FIELD32(0x00010000)
3578 +#define TX_PIN_CFG_RFTR_POL            FIELD32(0x00020000)
3579 +#define TX_PIN_CFG_TRSW_EN             FIELD32(0x00040000)
3580 +#define TX_PIN_CFG_TRSW_POL            FIELD32(0x00080000)
3581 +
3582 +/*
3583 + * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz
3584 + */
3585 +#define TX_BAND_CFG                    0x132c
3586 +#define TX_BAND_CFG_A                  FIELD32(0x00000002)
3587 +#define TX_BAND_CFG_BG                 FIELD32(0x00000004)
3588 +
3589 +/*
3590 + * TX_SW_CFG0:
3591 + */
3592 +#define TX_SW_CFG0                     0x1330
3593 +
3594 +/*
3595 + * TX_SW_CFG1:
3596 + */
3597 +#define TX_SW_CFG1                     0x1334
3598 +
3599 +/*
3600 + * TX_SW_CFG2:
3601 + */
3602 +#define TX_SW_CFG2                     0x1338
3603 +
3604 +/*
3605 + * TXOP_THRES_CFG:
3606 + */
3607 +#define TXOP_THRES_CFG                 0x133c
3608 +
3609 +/*
3610 + * TXOP_CTRL_CFG:
3611 + */
3612 +#define TXOP_CTRL_CFG                  0x1340
3613 +
3614 +/*
3615 + * TX_RTS_CFG:
3616 + * RTS_THRES: unit:byte
3617 + * RTS_FBK_EN: enable rts rate fallback
3618 + */
3619 +#define TX_RTS_CFG                     0x1344
3620 +#define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT        FIELD32(0x000000ff)
3621 +#define TX_RTS_CFG_RTS_THRES           FIELD32(0x00ffff00)
3622 +#define TX_RTS_CFG_RTS_FBK_EN          FIELD32(0x01000000)
3623 +
3624 +/*
3625 + * TX_TIMEOUT_CFG:
3626 + * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us
3627 + * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure
3628 + * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation.
3629 + *                it is recommended that:
3630 + *                (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
3631 + */
3632 +#define TX_TIMEOUT_CFG                 0x1348
3633 +#define TX_TIMEOUT_CFG_MPDU_LIFETIME   FIELD32(0x000000f0)
3634 +#define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT  FIELD32(0x0000ff00)
3635 +#define TX_TIMEOUT_CFG_TX_OP_TIMEOUT   FIELD32(0x00ff0000)
3636 +
3637 +/*
3638 + * TX_RTY_CFG:
3639 + * SHORT_RTY_LIMIT: short retry limit
3640 + * LONG_RTY_LIMIT: long retry limit
3641 + * LONG_RTY_THRE: Long retry threshoold
3642 + * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode
3643 + *                   0:expired by retry limit, 1: expired by mpdu life timer
3644 + * AGG_RTY_MODE: Aggregate MPDU retry mode
3645 + *               0:expired by retry limit, 1: expired by mpdu life timer
3646 + * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable
3647 + */
3648 +#define TX_RTY_CFG                     0x134c
3649 +#define TX_RTY_CFG_SHORT_RTY_LIMIT     FIELD32(0x000000ff)
3650 +#define TX_RTY_CFG_LONG_RTY_LIMIT      FIELD32(0x0000ff00)
3651 +#define TX_RTY_CFG_LONG_RTY_THRE       FIELD32(0x0fff0000)
3652 +#define TX_RTY_CFG_NON_AGG_RTY_MODE    FIELD32(0x10000000)
3653 +#define TX_RTY_CFG_AGG_RTY_MODE                FIELD32(0x20000000)
3654 +#define TX_RTY_CFG_TX_AUTO_FB_ENABLE   FIELD32(0x40000000)
3655 +
3656 +/*
3657 + * TX_LINK_CFG:
3658 + * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us
3659 + * MFB_ENABLE: TX apply remote MFB 1:enable
3660 + * REMOTE_UMFS_ENABLE: remote unsolicit  MFB enable
3661 + *                     0: not apply remote remote unsolicit (MFS=7)
3662 + * TX_MRQ_EN: MCS request TX enable
3663 + * TX_RDG_EN: RDG TX enable
3664 + * TX_CF_ACK_EN: Piggyback CF-ACK enable
3665 + * REMOTE_MFB: remote MCS feedback
3666 + * REMOTE_MFS: remote MCS feedback sequence number
3667 + */
3668 +#define TX_LINK_CFG                    0x1350
3669 +#define TX_LINK_CFG_REMOTE_MFB_LIFETIME        FIELD32(0x000000ff)
3670 +#define TX_LINK_CFG_MFB_ENABLE         FIELD32(0x00000100)
3671 +#define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200)
3672 +#define TX_LINK_CFG_TX_MRQ_EN          FIELD32(0x00000400)
3673 +#define TX_LINK_CFG_TX_RDG_EN          FIELD32(0x00000800)
3674 +#define TX_LINK_CFG_TX_CF_ACK_EN       FIELD32(0x00001000)
3675 +#define TX_LINK_CFG_REMOTE_MFB         FIELD32(0x00ff0000)
3676 +#define TX_LINK_CFG_REMOTE_MFS         FIELD32(0xff000000)
3677 +
3678 +/*
3679 + * HT_FBK_CFG0:
3680 + */
3681 +#define HT_FBK_CFG0                    0x1354
3682 +#define HT_FBK_CFG0_HTMCS0FBK          FIELD32(0x0000000f)
3683 +#define HT_FBK_CFG0_HTMCS1FBK          FIELD32(0x000000f0)
3684 +#define HT_FBK_CFG0_HTMCS2FBK          FIELD32(0x00000f00)
3685 +#define HT_FBK_CFG0_HTMCS3FBK          FIELD32(0x0000f000)
3686 +#define HT_FBK_CFG0_HTMCS4FBK          FIELD32(0x000f0000)
3687 +#define HT_FBK_CFG0_HTMCS5FBK          FIELD32(0x00f00000)
3688 +#define HT_FBK_CFG0_HTMCS6FBK          FIELD32(0x0f000000)
3689 +#define HT_FBK_CFG0_HTMCS7FBK          FIELD32(0xf0000000)
3690 +
3691 +/*
3692 + * HT_FBK_CFG1:
3693 + */
3694 +#define HT_FBK_CFG1                    0x1358
3695 +#define HT_FBK_CFG1_HTMCS8FBK          FIELD32(0x0000000f)
3696 +#define HT_FBK_CFG1_HTMCS9FBK          FIELD32(0x000000f0)
3697 +#define HT_FBK_CFG1_HTMCS10FBK         FIELD32(0x00000f00)
3698 +#define HT_FBK_CFG1_HTMCS11FBK         FIELD32(0x0000f000)
3699 +#define HT_FBK_CFG1_HTMCS12FBK         FIELD32(0x000f0000)
3700 +#define HT_FBK_CFG1_HTMCS13FBK         FIELD32(0x00f00000)
3701 +#define HT_FBK_CFG1_HTMCS14FBK         FIELD32(0x0f000000)
3702 +#define HT_FBK_CFG1_HTMCS15FBK         FIELD32(0xf0000000)
3703 +
3704 +/*
3705 + * LG_FBK_CFG0:
3706 + */
3707 +#define LG_FBK_CFG0                    0x135c
3708 +#define LG_FBK_CFG0_OFDMMCS0FBK                FIELD32(0x0000000f)
3709 +#define LG_FBK_CFG0_OFDMMCS1FBK                FIELD32(0x000000f0)
3710 +#define LG_FBK_CFG0_OFDMMCS2FBK                FIELD32(0x00000f00)
3711 +#define LG_FBK_CFG0_OFDMMCS3FBK                FIELD32(0x0000f000)
3712 +#define LG_FBK_CFG0_OFDMMCS4FBK                FIELD32(0x000f0000)
3713 +#define LG_FBK_CFG0_OFDMMCS5FBK                FIELD32(0x00f00000)
3714 +#define LG_FBK_CFG0_OFDMMCS6FBK                FIELD32(0x0f000000)
3715 +#define LG_FBK_CFG0_OFDMMCS7FBK                FIELD32(0xf0000000)
3716 +
3717 +/*
3718 + * LG_FBK_CFG1:
3719 + */
3720 +#define LG_FBK_CFG1                    0x1360
3721 +#define LG_FBK_CFG0_CCKMCS0FBK         FIELD32(0x0000000f)
3722 +#define LG_FBK_CFG0_CCKMCS1FBK         FIELD32(0x000000f0)
3723 +#define LG_FBK_CFG0_CCKMCS2FBK         FIELD32(0x00000f00)
3724 +#define LG_FBK_CFG0_CCKMCS3FBK         FIELD32(0x0000f000)
3725 +
3726 +/*
3727 + * CCK_PROT_CFG: CCK Protection
3728 + * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd)
3729 + * PROTECT_CTRL: Protection control frame type for CCK TX
3730 + *               0:none, 1:RTS/CTS, 2:CTS-to-self
3731 + * PROTECT_NAV: TXOP protection type for CCK TX
3732 + *              0:none, 1:ShortNAVprotect, 2:LongNAVProtect
3733 + * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow
3734 + * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow
3735 + * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow
3736 + * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow
3737 + * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow
3738 + * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow
3739 + * RTS_TH_EN: RTS threshold enable on CCK TX
3740 + */
3741 +#define CCK_PROT_CFG                   0x1364
3742 +#define CCK_PROT_CFG_PROTECT_RATE      FIELD32(0x0000ffff)
3743 +#define CCK_PROT_CFG_PROTECT_CTRL      FIELD32(0x00030000)
3744 +#define CCK_PROT_CFG_PROTECT_NAV       FIELD32(0x000c0000)
3745 +#define CCK_PROT_CFG_TX_OP_ALLOW_CCK   FIELD32(0x00100000)
3746 +#define CCK_PROT_CFG_TX_OP_ALLOW_OFDM  FIELD32(0x00200000)
3747 +#define CCK_PROT_CFG_TX_OP_ALLOW_MM20  FIELD32(0x00400000)
3748 +#define CCK_PROT_CFG_TX_OP_ALLOW_MM40  FIELD32(0x00800000)
3749 +#define CCK_PROT_CFG_TX_OP_ALLOW_GF20  FIELD32(0x01000000)
3750 +#define CCK_PROT_CFG_TX_OP_ALLOW_GF40  FIELD32(0x02000000)
3751 +#define CCK_PROT_CFG_RTS_TH_EN         FIELD32(0x04000000)
3752 +
3753 +/*
3754 + * OFDM_PROT_CFG: OFDM Protection
3755 + */
3756 +#define OFDM_PROT_CFG                  0x1368
3757 +#define OFDM_PROT_CFG_PROTECT_RATE     FIELD32(0x0000ffff)
3758 +#define OFDM_PROT_CFG_PROTECT_CTRL     FIELD32(0x00030000)
3759 +#define OFDM_PROT_CFG_PROTECT_NAV      FIELD32(0x000c0000)
3760 +#define OFDM_PROT_CFG_TX_OP_ALLOW_CCK  FIELD32(0x00100000)
3761 +#define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3762 +#define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3763 +#define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3764 +#define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3765 +#define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3766 +#define OFDM_PROT_CFG_RTS_TH_EN                FIELD32(0x04000000)
3767 +
3768 +/*
3769 + * MM20_PROT_CFG: MM20 Protection
3770 + */
3771 +#define MM20_PROT_CFG                  0x136c
3772 +#define MM20_PROT_CFG_PROTECT_RATE     FIELD32(0x0000ffff)
3773 +#define MM20_PROT_CFG_PROTECT_CTRL     FIELD32(0x00030000)
3774 +#define MM20_PROT_CFG_PROTECT_NAV      FIELD32(0x000c0000)
3775 +#define MM20_PROT_CFG_TX_OP_ALLOW_CCK  FIELD32(0x00100000)
3776 +#define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3777 +#define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3778 +#define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3779 +#define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3780 +#define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3781 +#define MM20_PROT_CFG_RTS_TH_EN                FIELD32(0x04000000)
3782 +
3783 +/*
3784 + * MM40_PROT_CFG: MM40 Protection
3785 + */
3786 +#define MM40_PROT_CFG                  0x1370
3787 +#define MM40_PROT_CFG_PROTECT_RATE     FIELD32(0x0000ffff)
3788 +#define MM40_PROT_CFG_PROTECT_CTRL     FIELD32(0x00030000)
3789 +#define MM40_PROT_CFG_PROTECT_NAV      FIELD32(0x000c0000)
3790 +#define MM40_PROT_CFG_TX_OP_ALLOW_CCK  FIELD32(0x00100000)
3791 +#define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3792 +#define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3793 +#define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3794 +#define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3795 +#define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3796 +#define MM40_PROT_CFG_RTS_TH_EN                FIELD32(0x04000000)
3797 +
3798 +/*
3799 + * GF20_PROT_CFG: GF20 Protection
3800 + */
3801 +#define GF20_PROT_CFG                  0x1374
3802 +#define GF20_PROT_CFG_PROTECT_RATE     FIELD32(0x0000ffff)
3803 +#define GF20_PROT_CFG_PROTECT_CTRL     FIELD32(0x00030000)
3804 +#define GF20_PROT_CFG_PROTECT_NAV      FIELD32(0x000c0000)
3805 +#define GF20_PROT_CFG_TX_OP_ALLOW_CCK  FIELD32(0x00100000)
3806 +#define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3807 +#define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3808 +#define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3809 +#define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3810 +#define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3811 +#define GF20_PROT_CFG_RTS_TH_EN                FIELD32(0x04000000)
3812 +
3813 +/*
3814 + * GF40_PROT_CFG: GF40 Protection
3815 + */
3816 +#define GF40_PROT_CFG                  0x1378
3817 +#define GF40_PROT_CFG_PROTECT_RATE     FIELD32(0x0000ffff)
3818 +#define GF40_PROT_CFG_PROTECT_CTRL     FIELD32(0x00030000)
3819 +#define GF40_PROT_CFG_PROTECT_NAV      FIELD32(0x000c0000)
3820 +#define GF40_PROT_CFG_TX_OP_ALLOW_CCK  FIELD32(0x00100000)
3821 +#define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3822 +#define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3823 +#define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3824 +#define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3825 +#define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3826 +#define GF40_PROT_CFG_RTS_TH_EN                FIELD32(0x04000000)
3827 +
3828 +/*
3829 + * EXP_CTS_TIME:
3830 + */
3831 +#define EXP_CTS_TIME                   0x137c
3832 +
3833 +/*
3834 + * EXP_ACK_TIME:
3835 + */
3836 +#define EXP_ACK_TIME                   0x1380
3837 +
3838 +/*
3839 + * RX_FILTER_CFG: RX configuration register.
3840 + */
3841 +#define RX_FILTER_CFG                  0x1400
3842 +#define RX_FILTER_CFG_DROP_CRC_ERROR   FIELD32(0x00000001)
3843 +#define RX_FILTER_CFG_DROP_PHY_ERROR   FIELD32(0x00000002)
3844 +#define RX_FILTER_CFG_DROP_NOT_TO_ME   FIELD32(0x00000004)
3845 +#define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008)
3846 +#define RX_FILTER_CFG_DROP_VER_ERROR   FIELD32(0x00000010)
3847 +#define RX_FILTER_CFG_DROP_MULTICAST   FIELD32(0x00000020)
3848 +#define RX_FILTER_CFG_DROP_BROADCAST   FIELD32(0x00000040)
3849 +#define RX_FILTER_CFG_DROP_DUPLICATE   FIELD32(0x00000080)
3850 +#define RX_FILTER_CFG_DROP_CF_END_ACK  FIELD32(0x00000100)
3851 +#define RX_FILTER_CFG_DROP_CF_END      FIELD32(0x00000200)
3852 +#define RX_FILTER_CFG_DROP_ACK         FIELD32(0x00000400)
3853 +#define RX_FILTER_CFG_DROP_CTS         FIELD32(0x00000800)
3854 +#define RX_FILTER_CFG_DROP_RTS         FIELD32(0x00001000)
3855 +#define RX_FILTER_CFG_DROP_PSPOLL      FIELD32(0x00002000)
3856 +#define RX_FILTER_CFG_DROP_BA          FIELD32(0x00004000)
3857 +#define RX_FILTER_CFG_DROP_BAR         FIELD32(0x00008000)
3858 +#define RX_FILTER_CFG_DROP_CNTL                FIELD32(0x00010000)
3859 +
3860 +/*
3861 + * AUTO_RSP_CFG:
3862 + * AUTORESPONDER: 0: disable, 1: enable
3863 + * BAC_ACK_POLICY: 0:long, 1:short preamble
3864 + * CTS_40_MMODE: Response CTS 40MHz duplicate mode
3865 + * CTS_40_MREF: Response CTS 40MHz duplicate mode
3866 + * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble
3867 + * DUAL_CTS_EN: Power bit value in control frame
3868 + * ACK_CTS_PSM_BIT:Power bit value in control frame
3869 + */
3870 +#define AUTO_RSP_CFG                   0x1404
3871 +#define AUTO_RSP_CFG_AUTORESPONDER     FIELD32(0x00000001)
3872 +#define AUTO_RSP_CFG_BAC_ACK_POLICY    FIELD32(0x00000002)
3873 +#define AUTO_RSP_CFG_CTS_40_MMODE      FIELD32(0x00000004)
3874 +#define AUTO_RSP_CFG_CTS_40_MREF       FIELD32(0x00000008)
3875 +#define AUTO_RSP_CFG_AR_PREAMBLE       FIELD32(0x00000010)
3876 +#define AUTO_RSP_CFG_DUAL_CTS_EN       FIELD32(0x00000040)
3877 +#define AUTO_RSP_CFG_ACK_CTS_PSM_BIT   FIELD32(0x00000080)
3878 +
3879 +/*
3880 + * LEGACY_BASIC_RATE:
3881 + */
3882 +#define LEGACY_BASIC_RATE              0x1408
3883 +
3884 +/*
3885 + * HT_BASIC_RATE:
3886 + */
3887 +#define HT_BASIC_RATE                  0x140c
3888 +
3889 +/*
3890 + * HT_CTRL_CFG:
3891 + */
3892 +#define HT_CTRL_CFG                    0x1410
3893 +
3894 +/*
3895 + * SIFS_COST_CFG:
3896 + */
3897 +#define SIFS_COST_CFG                  0x1414
3898 +
3899 +/*
3900 + * RX_PARSER_CFG:
3901 + * Set NAV for all received frames
3902 + */
3903 +#define RX_PARSER_CFG                  0x1418
3904 +
3905 +/*
3906 + * TX_SEC_CNT0:
3907 + */
3908 +#define TX_SEC_CNT0                    0x1500
3909 +
3910 +/*
3911 + * RX_SEC_CNT0:
3912 + */
3913 +#define RX_SEC_CNT0                    0x1504
3914 +
3915 +/*
3916 + * CCMP_FC_MUTE:
3917 + */
3918 +#define CCMP_FC_MUTE                   0x1508
3919 +
3920 +/*
3921 + * TXOP_HLDR_ADDR0:
3922 + */
3923 +#define TXOP_HLDR_ADDR0                        0x1600
3924 +
3925 +/*
3926 + * TXOP_HLDR_ADDR1:
3927 + */
3928 +#define TXOP_HLDR_ADDR1                        0x1604
3929 +
3930 +/*
3931 + * TXOP_HLDR_ET:
3932 + */
3933 +#define TXOP_HLDR_ET                   0x1608
3934 +
3935 +/*
3936 + * QOS_CFPOLL_RA_DW0:
3937 + */
3938 +#define QOS_CFPOLL_RA_DW0              0x160c
3939 +
3940 +/*
3941 + * QOS_CFPOLL_RA_DW1:
3942 + */
3943 +#define QOS_CFPOLL_RA_DW1              0x1610
3944 +
3945 +/*
3946 + * QOS_CFPOLL_QC:
3947 + */
3948 +#define QOS_CFPOLL_QC                  0x1614
3949 +
3950 +/*
3951 + * RX_STA_CNT0: RX PLCP error count & RX CRC error count
3952 + */
3953 +#define RX_STA_CNT0                    0x1700
3954 +#define RX_STA_CNT0_CRC_ERR            FIELD32(0x0000ffff)
3955 +#define RX_STA_CNT0_PHY_ERR            FIELD32(0xffff0000)
3956 +
3957 +/*
3958 + * RX_STA_CNT1: RX False CCA count & RX LONG frame count
3959 + */
3960 +#define RX_STA_CNT1                    0x1704
3961 +#define RX_STA_CNT1_FALSE_CCA          FIELD32(0x0000ffff)
3962 +#define RX_STA_CNT1_PLCP_ERR           FIELD32(0xffff0000)
3963 +
3964 +/*
3965 + * RX_STA_CNT2:
3966 + */
3967 +#define RX_STA_CNT2                    0x1708
3968 +#define RX_STA_CNT2_RX_DUPLI_COUNT     FIELD32(0x0000ffff)
3969 +#define RX_STA_CNT2_RX_FIFO_OVERFLOW   FIELD32(0xffff0000)
3970 +
3971 +/*
3972 + * TX_STA_CNT0: TX Beacon count
3973 + */
3974 +#define TX_STA_CNT0                    0x170c
3975 +#define TX_STA_CNT0_TX_FAIL_COUNT      FIELD32(0x0000ffff)
3976 +#define TX_STA_CNT0_TX_BEACON_COUNT    FIELD32(0xffff0000)
3977 +
3978 +/*
3979 + * TX_STA_CNT1: TX tx count
3980 + */
3981 +#define TX_STA_CNT1                    0x1710
3982 +#define TX_STA_CNT1_TX_SUCCESS         FIELD32(0x0000ffff)
3983 +#define TX_STA_CNT1_TX_RETRANSMIT      FIELD32(0xffff0000)
3984 +
3985 +/*
3986 + * TX_STA_CNT2: TX tx count
3987 + */
3988 +#define TX_STA_CNT2                    0x1714
3989 +#define TX_STA_CNT2_TX_ZERO_LEN_COUNT  FIELD32(0x0000ffff)
3990 +#define TX_STA_CNT2_TX_UNDER_FLOW_COUNT        FIELD32(0xffff0000)
3991 +
3992 +/*
3993 + * TX_STA_FIFO: TX Result for specific PID status fifo register
3994 + */
3995 +#define TX_STA_FIFO                    0x1718
3996 +#define TX_STA_FIFO_B_VALID            FIELD32(0x00000001)
3997 +#define TX_STA_FIFO_PID_TYPE           FIELD32(0x0000001e)
3998 +#define TX_STA_FIFO_TX_SUCCESS         FIELD32(0x00000020)
3999 +#define TX_STA_FIFO_TX_AGGRE           FIELD32(0x00000040)
4000 +#define TX_STA_FIFO_TX_ACK_REQUIRED    FIELD32(0x00000080)
4001 +#define TX_STA_FIFO_WCID               FIELD32(0x0000ff00)
4002 +#define TX_STA_FIFO_SUCCESS_RATE       FIELD32(0xffff0000)
4003 +
4004 +/*
4005 + * TX_AGG_CNT: Debug counter
4006 + */
4007 +#define TX_AGG_CNT                     0x171c
4008 +#define TX_AGG_CNT_NON_AGG_TX_COUNT    FIELD32(0x0000ffff)
4009 +#define TX_AGG_CNT_AGG_TX_COUNT                FIELD32(0xffff0000)
4010 +
4011 +/*
4012 + * TX_AGG_CNT0:
4013 + */
4014 +#define TX_AGG_CNT0                    0x1720
4015 +#define TX_AGG_CNT0_AGG_SIZE_1_COUNT   FIELD32(0x0000ffff)
4016 +#define TX_AGG_CNT0_AGG_SIZE_2_COUNT   FIELD32(0xffff0000)
4017 +
4018 +/*
4019 + * TX_AGG_CNT1:
4020 + */
4021 +#define TX_AGG_CNT1                    0x1724
4022 +#define TX_AGG_CNT1_AGG_SIZE_3_COUNT   FIELD32(0x0000ffff)
4023 +#define TX_AGG_CNT1_AGG_SIZE_4_COUNT   FIELD32(0xffff0000)
4024 +
4025 +/*
4026 + * TX_AGG_CNT2:
4027 + */
4028 +#define TX_AGG_CNT2                    0x1728
4029 +#define TX_AGG_CNT2_AGG_SIZE_5_COUNT   FIELD32(0x0000ffff)
4030 +#define TX_AGG_CNT2_AGG_SIZE_6_COUNT   FIELD32(0xffff0000)
4031 +
4032 +/*
4033 + * TX_AGG_CNT3:
4034 + */
4035 +#define TX_AGG_CNT3                    0x172c
4036 +#define TX_AGG_CNT3_AGG_SIZE_7_COUNT   FIELD32(0x0000ffff)
4037 +#define TX_AGG_CNT3_AGG_SIZE_8_COUNT   FIELD32(0xffff0000)
4038 +
4039 +/*
4040 + * TX_AGG_CNT4:
4041 + */
4042 +#define TX_AGG_CNT4                    0x1730
4043 +#define TX_AGG_CNT4_AGG_SIZE_9_COUNT   FIELD32(0x0000ffff)
4044 +#define TX_AGG_CNT4_AGG_SIZE_10_COUNT  FIELD32(0xffff0000)
4045 +
4046 +/*
4047 + * TX_AGG_CNT5:
4048 + */
4049 +#define TX_AGG_CNT5                    0x1734
4050 +#define TX_AGG_CNT5_AGG_SIZE_11_COUNT  FIELD32(0x0000ffff)
4051 +#define TX_AGG_CNT5_AGG_SIZE_12_COUNT  FIELD32(0xffff0000)
4052 +
4053 +/*
4054 + * TX_AGG_CNT6:
4055 + */
4056 +#define TX_AGG_CNT6                    0x1738
4057 +#define TX_AGG_CNT6_AGG_SIZE_13_COUNT  FIELD32(0x0000ffff)
4058 +#define TX_AGG_CNT6_AGG_SIZE_14_COUNT  FIELD32(0xffff0000)
4059 +
4060 +/*
4061 + * TX_AGG_CNT7:
4062 + */
4063 +#define TX_AGG_CNT7                    0x173c
4064 +#define TX_AGG_CNT7_AGG_SIZE_15_COUNT  FIELD32(0x0000ffff)
4065 +#define TX_AGG_CNT7_AGG_SIZE_16_COUNT  FIELD32(0xffff0000)
4066 +
4067 +/*
4068 + * MPDU_DENSITY_CNT:
4069 + * TX_ZERO_DEL: TX zero length delimiter count
4070 + * RX_ZERO_DEL: RX zero length delimiter count
4071 + */
4072 +#define MPDU_DENSITY_CNT               0x1740
4073 +#define MPDU_DENSITY_CNT_TX_ZERO_DEL   FIELD32(0x0000ffff)
4074 +#define MPDU_DENSITY_CNT_RX_ZERO_DEL   FIELD32(0xffff0000)
4075 +
4076 +/*
4077 + * Security key table memory, base address = 0x1800
4078 + */
4079 +struct hw_pairwise_ta_entry {
4080 +       u8 address[6];
4081 +       u8 reserved[2];
4082 +} __attribute__ ((packed));
4083 +
4084 +struct wcid_entry {
4085 +       u8 rx_ba_bitmat7;
4086 +       u8 rx_ba_bitmat0;
4087 +       u8 mac[6];
4088 +} __attribute__ ((packed));
4089 +
4090 +struct hw_key_entry {
4091 +       u8 key[16];
4092 +       u8 tx_mic[8];
4093 +       u8 rx_mic[8];
4094 +} __attribute__ ((packed));
4095 +
4096 +/*
4097 + * Security key table memory.
4098 + * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry
4099 + * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry
4100 + * PAIRWISE_IVEIV_TABLE_BASE: 8-byte * 256-entry
4101 + * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry
4102 + * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry
4103 + * SHARED_KEY_TABLE_BASE: 32-byte * 16-entry
4104 + * SHARED_KEY_MODE_BASE: 32-byte * 16-entry
4105 + */
4106 +#define MAC_WCID_BASE                  0x1800
4107 +#define PAIRWISE_KEY_TABLE_BASE                0x4000
4108 +#define PAIRWISE_IVEIV_TABLE_BASE      0x6000
4109 +#define MAC_IVEIV_TABLE_BASE           0x6000
4110 +#define MAC_WCID_ATTRIBUTE_BASE                0x6800
4111 +#define SHARED_KEY_TABLE_BASE          0x6c00
4112 +#define SHARED_KEY_MODE_BASE           0x7000
4113 +
4114 +#define SHARED_KEY_ENTRY(__idx) \
4115 +       ( SHARED_KEY_TABLE_BASE + \
4116 +               ((__idx) * sizeof(struct hw_key_entry)) )
4117 +#define SHARED_KEY_MODE_ENTRY(__idx) \
4118 +       ( SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)) )
4119 +#define PAIRWISE_KEY_ENTRY(__idx) \
4120 +       ( PAIRWISE_KEY_TABLE_BASE + \
4121 +               ((__idx) * sizeof(struct hw_key_entry)) )
4122 +
4123 +#define MAC_WCID_ENTRY(__idx) \
4124 +       ( MAC_WCID_BASE + (2 * sizeof(u32) * (__idx)) )
4125 +#define MAC_WCID_ATTR_ENTRY(__idx) \
4126 +       ( MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)) )
4127 +
4128 +/*
4129 + * MAC_WCID_ATTRIBUTE:
4130 + * KEYTAB: 0: shared key table, 1: pairwise key table
4131 + * BSS_IDX: multipleBSS index for the WCID
4132 + */
4133 +#define MAC_WCID_ATTRIBUTE_KEYTAB      FIELD32(0x00000001)
4134 +#define MAC_WCID_ATTRIBUTE_PAIRKEY_MODE        FIELD32(0x0000000e)
4135 +#define MAC_WCID_ATTRIBUTE_BSS_IDX     FIELD32(0x00000070)
4136 +#define MAC_WCID_ATTRIBUTE_RX_WIUDF    FIELD32(0x00000380)
4137 +
4138 +/*
4139 + * SHARED_KEY_MODE:
4140 + */
4141 +#define SHARED_KEY_MODE_BSS0_KEY0      FIELD32(0x00000007)
4142 +#define SHARED_KEY_MODE_BSS0_KEY1      FIELD32(0x00000070)
4143 +#define SHARED_KEY_MODE_BSS0_KEY2      FIELD32(0x00000700)
4144 +#define SHARED_KEY_MODE_BSS0_KEY3      FIELD32(0x00007000)
4145 +#define SHARED_KEY_MODE_BSS1_KEY0      FIELD32(0x00070000)
4146 +#define SHARED_KEY_MODE_BSS1_KEY1      FIELD32(0x00700000)
4147 +#define SHARED_KEY_MODE_BSS1_KEY2      FIELD32(0x07000000)
4148 +#define SHARED_KEY_MODE_BSS1_KEY3      FIELD32(0x70000000)
4149 +
4150 +/*
4151 + * HOST-MCU communication
4152 + */
4153 +
4154 +/*
4155 + * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
4156 + */
4157 +#define H2M_MAILBOX_CSR                        0x7010
4158 +#define H2M_MAILBOX_CSR_ARG0           FIELD32(0x000000ff)
4159 +#define H2M_MAILBOX_CSR_ARG1           FIELD32(0x0000ff00)
4160 +#define H2M_MAILBOX_CSR_CMD_TOKEN      FIELD32(0x00ff0000)
4161 +#define H2M_MAILBOX_CSR_OWNER          FIELD32(0xff000000)
4162 +
4163 +/*
4164 + * H2M_MAILBOX_CID:
4165 + */
4166 +#define H2M_MAILBOX_CID                        0x7014
4167 +
4168 +/*
4169 + * H2M_MAILBOX_STATUS:
4170 + */
4171 +#define H2M_MAILBOX_STATUS             0x701c
4172 +
4173 +/*
4174 + * H2M_INT_SRC:
4175 + */
4176 +#define H2M_INT_SRC                    0x7024
4177 +
4178 +/*
4179 + * H2M_BBP_AGENT:
4180 + */
4181 +#define H2M_BBP_AGENT                  0x7028
4182 +
4183 +/*
4184 + * MCU_LEDCS: LED control for MCU Mailbox.
4185 + */
4186 +#define MCU_LEDCS_LED_MODE             FIELD8(0x1f)
4187 +#define MCU_LEDCS_POLARITY             FIELD8(0x01)
4188 +
4189 +/*
4190 + * HW_CS_CTS_BASE:
4191 + * Carrier-sense CTS frame base address.
4192 + * It's where mac stores carrier-sense frame for carrier-sense function.
4193 + */
4194 +#define HW_CS_CTS_BASE                 0x7700
4195 +
4196 +/*
4197 + * HW_DFS_CTS_BASE:
4198 + * FS CTS frame base address. It's where mac stores CTS frame for DFS.
4199 + */
4200 +#define HW_DFS_CTS_BASE                        0x7780
4201 +
4202 +/*
4203 + * TXRX control registers - base address 0x3000
4204 + */
4205 +
4206 +/*
4207 + * TXRX_CSR1:
4208 + * rt2860b  UNKNOWN reg use R/O Reg Addr 0x77d0 first..
4209 + */
4210 +#define TXRX_CSR1                      0x77d0
4211 +
4212 +/*
4213 + * HW_DEBUG_SETTING_BASE:
4214 + * since NULL frame won't be that long (256 byte)
4215 + * We steal 16 tail bytes to save debugging settings
4216 + */
4217 +#define HW_DEBUG_SETTING_BASE          0x77f0
4218 +#define HW_DEBUG_SETTING_BASE2         0x7770
4219 +
4220 +/*
4221 + * HW_BEACON_BASE
4222 + * In order to support maximum 8 MBSS and its maximum length
4223 + * is 512 bytes for each beacon
4224 + * Three section discontinue memory segments will be used.
4225 + * 1. The original region for BCN 0~3
4226 + * 2. Extract memory from FCE table for BCN 4~5
4227 + * 3. Extract memory from Pair-wise key table for BCN 6~7
4228 + *    It occupied those memory of wcid 238~253 for BCN 6
4229 + *    and wcid 222~237 for BCN 7
4230 + *
4231 + * IMPORTANT NOTE: Not sure why legacy driver does this,
4232 + * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6.
4233 + */
4234 +#define HW_BEACON_BASE0                        0x7800
4235 +#define HW_BEACON_BASE1                        0x7a00
4236 +#define HW_BEACON_BASE2                        0x7c00
4237 +#define HW_BEACON_BASE3                        0x7e00
4238 +#define HW_BEACON_BASE4                        0x7200
4239 +#define HW_BEACON_BASE5                        0x7400
4240 +#define HW_BEACON_BASE6                        0x5dc0
4241 +#define HW_BEACON_BASE7                        0x5bc0
4242 +
4243 +#define HW_BEACON_OFFSET(__index) \
4244 +       ( ((__index) < 4) ? ( HW_BEACON_BASE0 + (__index * 0x0200) ) : \
4245 +         (((__index) < 6) ? ( HW_BEACON_BASE4 + ((__index - 4) * 0x0200) ) : \
4246 +         (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))) )
4247 +
4248 +/*
4249 + * 8051 firmware image.
4250 + */
4251 +#define FIRMWARE_RT2860                        "rt2860.bin"
4252 +#define FIRMWARE_IMAGE_BASE            0x2000
4253 +
4254 +/*
4255 + * BBP registers.
4256 + * The wordsize of the BBP is 8 bits.
4257 + */
4258 +
4259 +/*
4260 + * BBP 1: TX Antenna
4261 + */
4262 +#define BBP1_TX_POWER                  FIELD8(0x07)
4263 +#define BBP1_TX_ANTENNA                        FIELD8(0x18)
4264 +
4265 +/*
4266 + * BBP 3: RX Antenna
4267 + */
4268 +#define BBP3_RX_ANTENNA                        FIELD8(0x18)
4269 +
4270 +/*
4271 + * RF registers
4272 + */
4273 +
4274 +/*
4275 + * RF 2
4276 + */
4277 +#define RF2_ANTENNA_RX2                        FIELD32(0x00000040)
4278 +#define RF2_ANTENNA_TX1                        FIELD32(0x00004000)
4279 +#define RF2_ANTENNA_RX1                        FIELD32(0x00020000)
4280 +
4281 +/*
4282 + * RF 3
4283 + */
4284 +#define RF3_TXPOWER_G                  FIELD32(0x00003e00)
4285 +#define RF3_TXPOWER_A_7DBM_BOOST       FIELD32(0x00000200)
4286 +#define RF3_TXPOWER_A                  FIELD32(0x00003c00)
4287 +
4288 +/*
4289 + * RF 4
4290 + */
4291 +#define RF4_TXPOWER_G                  FIELD32(0x000007c0)
4292 +#define RF4_TXPOWER_A_7DBM_BOOST       FIELD32(0x00000040)
4293 +#define RF4_TXPOWER_A                  FIELD32(0x00000780)
4294 +#define RF4_FREQ_OFFSET                        FIELD32(0x001f8000)
4295 +#define RF4_BW40                       FIELD32(0x00200000)
4296 +
4297 +/*
4298 + * EEPROM content.
4299 + * The wordsize of the EEPROM is 16 bits.
4300 + */
4301 +
4302 +/*
4303 + * EEPROM Version
4304 + */
4305 +#define EEPROM_VERSION                 0x0001
4306 +#define EEPROM_VERSION_FAE             FIELD16(0x00ff)
4307 +#define EEPROM_VERSION_VERSION         FIELD16(0xff00)
4308 +
4309 +/*
4310 + * HW MAC address.
4311 + */
4312 +#define EEPROM_MAC_ADDR_0              0x0002
4313 +#define EEPROM_MAC_ADDR_BYTE0          FIELD16(0x00ff)
4314 +#define EEPROM_MAC_ADDR_BYTE1          FIELD16(0xff00)
4315 +#define EEPROM_MAC_ADDR1               0x0003
4316 +#define EEPROM_MAC_ADDR_BYTE2          FIELD16(0x00ff)
4317 +#define EEPROM_MAC_ADDR_BYTE3          FIELD16(0xff00)
4318 +#define EEPROM_MAC_ADDR_2              0x0004
4319 +#define EEPROM_MAC_ADDR_BYTE4          FIELD16(0x00ff)
4320 +#define EEPROM_MAC_ADDR_BYTE5          FIELD16(0xff00)
4321 +
4322 +/*
4323 + * EEPROM ANTENNA config
4324 + * RXPATH: 1: 1R, 2: 2R, 3: 3R
4325 + * TXPATH: 1: 1T, 2: 2T
4326 + */
4327 +#define        EEPROM_ANTENNA                  0x001a
4328 +#define EEPROM_ANTENNA_RXPATH          FIELD16(0x000f)
4329 +#define EEPROM_ANTENNA_TXPATH          FIELD16(0x00f0)
4330 +#define EEPROM_ANTENNA_RF_TYPE         FIELD16(0x0f00)
4331 +
4332 +/*
4333 + * EEPROM NIC config
4334 + * CARDBUS_ACCEL: 0 - enable, 1 - disable
4335 + */
4336 +#define        EEPROM_NIC                      0x001b
4337 +#define EEPROM_NIC_HW_RADIO            FIELD16(0x0001)
4338 +#define EEPROM_NIC_DYNAMIC_TX_AGC      FIELD16(0x0002)
4339 +#define EEPROM_NIC_EXTERNAL_LNA_BG     FIELD16(0x0004)
4340 +#define EEPROM_NIC_EXTERNAL_LNA_A      FIELD16(0x0008)
4341 +#define EEPROM_NIC_CARDBUS_ACCEL       FIELD16(0x0010)
4342 +#define EEPROM_NIC_BW40M_SB_BG         FIELD16(0x0020)
4343 +#define EEPROM_NIC_BW40M_SB_A          FIELD16(0x0040)
4344 +#define EEPROM_NIC_WPS_PBC             FIELD16(0x0080)
4345 +#define EEPROM_NIC_BW40M_BG            FIELD16(0x0100)
4346 +#define EEPROM_NIC_BW40M_A             FIELD16(0x0200)
4347 +
4348 +/*
4349 + * EEPROM frequency
4350 + */
4351 +#define        EEPROM_FREQ                     0x001d
4352 +#define EEPROM_FREQ_OFFSET             FIELD16(0x00ff)
4353 +#define EEPROM_FREQ_LED_MODE           FIELD16(0x7f00)
4354 +#define EEPROM_FREQ_LED_POLARITY       FIELD16(0x1000)
4355 +
4356 +/*
4357 + * EEPROM LED
4358 + * POLARITY_RDY_G: Polarity RDY_G setting.
4359 + * POLARITY_RDY_A: Polarity RDY_A setting.
4360 + * POLARITY_ACT: Polarity ACT setting.
4361 + * POLARITY_GPIO_0: Polarity GPIO0 setting.
4362 + * POLARITY_GPIO_1: Polarity GPIO1 setting.
4363 + * POLARITY_GPIO_2: Polarity GPIO2 setting.
4364 + * POLARITY_GPIO_3: Polarity GPIO3 setting.
4365 + * POLARITY_GPIO_4: Polarity GPIO4 setting.
4366 + * LED_MODE: Led mode.
4367 + */
4368 +#define EEPROM_LED1                    0x001e
4369 +#define EEPROM_LED2                    0x001f
4370 +#define EEPROM_LED3                    0x0020
4371 +#define EEPROM_LED_POLARITY_RDY_BG     FIELD16(0x0001)
4372 +#define EEPROM_LED_POLARITY_RDY_A      FIELD16(0x0002)
4373 +#define EEPROM_LED_POLARITY_ACT                FIELD16(0x0004)
4374 +#define EEPROM_LED_POLARITY_GPIO_0     FIELD16(0x0008)
4375 +#define EEPROM_LED_POLARITY_GPIO_1     FIELD16(0x0010)
4376 +#define EEPROM_LED_POLARITY_GPIO_2     FIELD16(0x0020)
4377 +#define EEPROM_LED_POLARITY_GPIO_3     FIELD16(0x0040)
4378 +#define EEPROM_LED_POLARITY_GPIO_4     FIELD16(0x0080)
4379 +#define EEPROM_LED_LED_MODE            FIELD16(0x1f00)
4380 +
4381 +/*
4382 + * EEPROM LNA
4383 + */
4384 +#define EEPROM_LNA                     0x0022
4385 +#define EEPROM_LNA_BG                  FIELD16(0x00ff)
4386 +#define EEPROM_LNA_A0                  FIELD16(0xff00)
4387 +
4388 +/*
4389 + * EEPROM RSSI BG offset
4390 + */
4391 +#define EEPROM_RSSI_BG                 0x0023
4392 +#define EEPROM_RSSI_BG_OFFSET0         FIELD16(0x00ff)
4393 +#define EEPROM_RSSI_BG_OFFSET1         FIELD16(0xff00)
4394 +
4395 +/*
4396 + * EEPROM RSSI BG2 offset
4397 + */
4398 +#define EEPROM_RSSI_BG2                        0x0024
4399 +#define EEPROM_RSSI_BG2_OFFSET2                FIELD16(0x00ff)
4400 +#define EEPROM_RSSI_BG2_LNA_A1         FIELD16(0xff00)
4401 +
4402 +/*
4403 + * EEPROM RSSI A offset
4404 + */
4405 +#define EEPROM_RSSI_A                  0x0025
4406 +#define EEPROM_RSSI_A_OFFSET0          FIELD16(0x00ff)
4407 +#define EEPROM_RSSI_A_OFFSET1          FIELD16(0xff00)
4408 +
4409 +/*
4410 + * EEPROM RSSI A2 offset
4411 + */
4412 +#define EEPROM_RSSI_A2                 0x0026
4413 +#define EEPROM_RSSI_A2_OFFSET2         FIELD16(0x00ff)
4414 +#define EEPROM_RSSI_A2_LNA_A2          FIELD16(0xff00)
4415 +
4416 +/*
4417 + * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power.
4418 + *     This is delta in 40MHZ.
4419 + * VALUE: Tx Power dalta value (MAX=4)
4420 + * TYPE: 1: Plus the delta value, 0: minus the delta value
4421 + * TXPOWER: Enable:
4422 + */
4423 +#define EEPROM_TXPOWER_DELTA           0x0028
4424 +#define EEPROM_TXPOWER_DELTA_VALUE     FIELD16(0x003f)
4425 +#define EEPROM_TXPOWER_DELTA_TYPE      FIELD16(0x0040)
4426 +#define EEPROM_TXPOWER_DELTA_TXPOWER   FIELD16(0x0080)
4427 +
4428 +/*
4429 + * EEPROM TXPOWER 802.11G
4430 + */
4431 +#define        EEPROM_TXPOWER_BG1              0x0029
4432 +#define        EEPROM_TXPOWER_BG2              0x0030
4433 +#define EEPROM_TXPOWER_BG_SIZE         7
4434 +#define EEPROM_TXPOWER_BG_1            FIELD16(0x00ff)
4435 +#define EEPROM_TXPOWER_BG_2            FIELD16(0xff00)
4436 +
4437 +/*
4438 + * EEPROM TXPOWER 802.11A
4439 + */
4440 +#define EEPROM_TXPOWER_A1              0x003c
4441 +#define EEPROM_TXPOWER_A2              0x0053
4442 +#define EEPROM_TXPOWER_A_SIZE          6
4443 +#define EEPROM_TXPOWER_A_1             FIELD16(0x00ff)
4444 +#define EEPROM_TXPOWER_A_2             FIELD16(0xff00)
4445 +
4446 +/*
4447 + * EEPROM TXpower byrate: 20MHZ power
4448 + */
4449 +#define EEPROM_TXPOWER_BYRATE          0x006f
4450 +
4451 +/*
4452 + * EEPROM BBP.
4453 + */
4454 +#define        EEPROM_BBP_START                0x0078
4455 +#define EEPROM_BBP_SIZE                        16
4456 +#define EEPROM_BBP_VALUE               FIELD16(0x00ff)
4457 +#define EEPROM_BBP_REG_ID              FIELD16(0xff00)
4458 +
4459 +/*
4460 + * MCU mailbox commands.
4461 + */
4462 +#define MCU_SLEEP                      0x30
4463 +#define MCU_WAKEUP                     0x31
4464 +#define MCU_LED                                0x50
4465 +#define MCU_LED_STRENGTH               0x51
4466 +#define MCU_LED_1                      0x52
4467 +#define MCU_LED_2                      0x53
4468 +#define MCU_LED_3                      0x54
4469 +#define MCU_RADAR                      0x60
4470 +#define MCU_BOOT_SIGNAL                        0x72
4471 +
4472 +/*
4473 + * DMA descriptor defines.
4474 + */
4475 +#define TXD_DESC_SIZE                  ( 4 * sizeof(__le32) )
4476 +#define TXWI_DESC_SIZE                 ( 4 * sizeof(__le32) )
4477 +#define RXD_DESC_SIZE                  ( 4 * sizeof(__le32) )
4478 +#define RXWI_DESC_SIZE                 ( 4 * sizeof(__le32) )
4479 +
4480 +/*
4481 + * TX descriptor format for TX, PRIO and Beacon Ring.
4482 + */
4483 +
4484 +/*
4485 + * Word0
4486 + */
4487 +#define TXD_W0_SD_PTR0                 FIELD32(0xffffffff)
4488 +
4489 +/*
4490 + * Word1
4491 + */
4492 +#define TXD_W1_SD_LEN1                 FIELD32(0x00003fff)
4493 +#define TXD_W1_LAST_SEC1               FIELD32(0x00004000)
4494 +#define TXD_W1_BURST                   FIELD32(0x00008000)
4495 +#define TXD_W1_SD_LEN0                 FIELD32(0x3fff0000)
4496 +#define TXD_W1_LAST_SEC0               FIELD32(0x40000000)
4497 +#define TXD_W1_DMA_DONE                        FIELD32(0x80000000)
4498 +
4499 +/*
4500 + * Word2
4501 + */
4502 +#define TXD_W2_SD_PTR1                 FIELD32(0xffffffff)
4503 +
4504 +/*
4505 + * Word3
4506 + * WIV: Wireless Info Valid. 1: Driver filled WI,  0: DMA needs to copy WI
4507 + * QSEL: Select on-chip FIFO ID for 2nd-stage output scheduler.
4508 + *       0:MGMT, 1:HCCA 2:EDCA
4509 + */
4510 +#define TXD_W3_WIV                     FIELD32(0x01000000)
4511 +#define TXD_W3_QSEL                    FIELD32(0x06000000)
4512 +#define TXD_W3_TCO                     FIELD32(0x20000000)
4513 +#define TXD_W3_UCO                     FIELD32(0x40000000)
4514 +#define TXD_W3_ICO                     FIELD32(0x80000000)
4515 +
4516 +/*
4517 + * TX WI structure
4518 + */
4519 +
4520 +/*
4521 + * Word0
4522 + * FRAG: 1 To inform TKIP engine this is a fragment.
4523 + * MIMO_PS: The remote peer is in dynamic MIMO-PS mode
4524 + * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs
4525 + * BW: Channel bandwidth 20MHz or 40 MHz
4526 + * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED
4527 + */
4528 +#define TXWI_W0_FRAG                   FIELD32(0x00000001)
4529 +#define TXWI_W0_MIMO_PS                        FIELD32(0x00000002)
4530 +#define TXWI_W0_CF_ACK                 FIELD32(0x00000004)
4531 +#define TXWI_W0_TS                     FIELD32(0x00000008)
4532 +#define TXWI_W0_AMPDU                  FIELD32(0x00000010)
4533 +#define TXWI_W0_MPDU_DENSITY           FIELD32(0x000000e0)
4534 +#define TXWI_W0_TX_OP                  FIELD32(0x00000300)
4535 +#define TXWI_W0_MCS                    FIELD32(0x007f0000)
4536 +#define TXWI_W0_BW                     FIELD32(0x00800000)
4537 +#define TXWI_W0_SHORT_GI               FIELD32(0x01000000)
4538 +#define TXWI_W0_STBC                   FIELD32(0x06000000)
4539 +#define TXWI_W0_IFS                    FIELD32(0x08000000)
4540 +#define TXWI_W0_PHYMODE                        FIELD32(0xc0000000)
4541 +
4542 +/*
4543 + * Word1
4544 + */
4545 +#define TXWI_W1_ACK                    FIELD32(0x00000001)
4546 +#define TXWI_W1_NSEQ                   FIELD32(0x00000002)
4547 +#define TXWI_W1_BW_WIN_SIZE            FIELD32(0x000000fc)
4548 +#define TXWI_W1_WIRELESS_CLI_ID                FIELD32(0x0000ff00)
4549 +#define TXWI_W1_MPDU_TOTAL_BYTE_COUNT  FIELD32(0x0fff0000)
4550 +#define TXWI_W1_PACKETID               FIELD32(0xf0000000)
4551 +
4552 +/*
4553 + * Word2
4554 + */
4555 +#define TXWI_W2_IV                     FIELD32(0xffffffff)
4556 +
4557 +/*
4558 + * Word3
4559 + */
4560 +#define TXWI_W3_EIV                    FIELD32(0xffffffff)
4561 +
4562 +/*
4563 + * RX descriptor format for RX Ring.
4564 + */
4565 +
4566 +/*
4567 + * Word0
4568 + */
4569 +#define RXD_W0_SDP0                    FIELD32(0xffffffff)
4570 +
4571 +/*
4572 + * Word1
4573 + */
4574 +#define RXD_W1_SDL1                    FIELD32(0x00003fff)
4575 +#define RXD_W1_SDL0                    FIELD32(0x3fff0000)
4576 +#define RXD_W1_LS0                     FIELD32(0x40000000)
4577 +#define RXD_W1_DMA_DONE                        FIELD32(0x80000000)
4578 +
4579 +/*
4580 + * Word2
4581 + */
4582 +#define RXD_W2_SDP1                    FIELD32(0xffffffff)
4583 +
4584 +/*
4585 + * Word3
4586 + * AMSDU: RX with 802.3 header, not 802.11 header.
4587 + * DECRYPTED: This frame is being decrypted.
4588 + */
4589 +#define RXD_W3_BA                      FIELD32(0x00000001)
4590 +#define RXD_W3_DATA                    FIELD32(0x00000002)
4591 +#define RXD_W3_NULLDATA                        FIELD32(0x00000004)
4592 +#define RXD_W3_FRAG                    FIELD32(0x00000008)
4593 +#define RXD_W3_UNICAST_TO_ME           FIELD32(0x00000010)
4594 +#define RXD_W3_MULTICAST               FIELD32(0x00000020)
4595 +#define RXD_W3_BROADCAST               FIELD32(0x00000040)
4596 +#define RXD_W3_MY_BSS                  FIELD32(0x00000080)
4597 +#define RXD_W3_CRC_ERROR               FIELD32(0x00000100)
4598 +#define RXD_W3_CIPHER_ERROR            FIELD32(0x00000600)
4599 +#define RXD_W3_AMSDU                   FIELD32(0x00000800)
4600 +#define RXD_W3_HTC                     FIELD32(0x00001000)
4601 +#define RXD_W3_RSSI                    FIELD32(0x00002000)
4602 +#define RXD_W3_L2PAD                   FIELD32(0x00004000)
4603 +#define RXD_W3_AMPDU                   FIELD32(0x00008000)
4604 +#define RXD_W3_DECRYPTED               FIELD32(0x00010000)
4605 +#define RXD_W3_PLCP_SIGNAL             FIELD32(0x00020000)
4606 +#define RXD_W3_PLCP_RSSI               FIELD32(0x00040000)
4607 +
4608 +/*
4609 + * RX WI structure
4610 + */
4611 +
4612 +/*
4613 + * Word0
4614 + */
4615 +#define RXWI_W0_WIRELESS_CLI_ID                FIELD32(0x000000ff)
4616 +#define RXWI_W0_KEY_INDEX              FIELD32(0x00000300)
4617 +#define RXWI_W0_BSSID                  FIELD32(0x00001c00)
4618 +#define RXWI_W0_UDF                    FIELD32(0x0000e000)
4619 +#define RXWI_W0_MPDU_TOTAL_BYTE_COUNT  FIELD32(0x0fff0000)
4620 +#define RXWI_W0_TID                    FIELD32(0xf0000000)
4621 +
4622 +/*
4623 + * Word1
4624 + */
4625 +#define RXWI_W1_FRAG                   FIELD32(0x0000000f)
4626 +#define RXWI_W1_SEQUENCE               FIELD32(0x0000fff0)
4627 +#define RXWI_W1_MCS                    FIELD32(0x007f0000)
4628 +#define RXWI_W1_BW                     FIELD32(0x00800000)
4629 +#define RXWI_W1_SHORT_GI               FIELD32(0x01000000)
4630 +#define RXWI_W1_STBC                   FIELD32(0x06000000)
4631 +#define RXWI_W1_PHYMODE                        FIELD32(0xc0000000)
4632 +
4633 +/*
4634 + * Word2
4635 + */
4636 +#define RXWI_W2_RSSI0                  FIELD32(0x000000ff)
4637 +#define RXWI_W2_RSSI1                  FIELD32(0x0000ff00)
4638 +#define RXWI_W2_RSSI2                  FIELD32(0x00ff0000)
4639 +
4640 +/*
4641 + * Word3
4642 + */
4643 +#define RXWI_W3_SNR0                   FIELD32(0x000000ff)
4644 +#define RXWI_W3_SNR1                   FIELD32(0x0000ff00)
4645 +
4646 +/*
4647 + * Macro's for converting txpower from EEPROM to mac80211 value
4648 + * and from mac80211 value to register value.
4649 + */
4650 +#define MIN_G_TXPOWER  0
4651 +#define MIN_A_TXPOWER  -7
4652 +#define MAX_G_TXPOWER  31
4653 +#define MAX_A_TXPOWER  15
4654 +#define DEFAULT_TXPOWER        5
4655 +
4656 +#define TXPOWER_G_FROM_DEV(__txpower) \
4657 +       ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
4658 +
4659 +#define TXPOWER_G_TO_DEV(__txpower) \
4660 +       clamp_t(char, __txpower, MIN_G_TXPOWER, MAX_G_TXPOWER)
4661 +
4662 +#define TXPOWER_A_FROM_DEV(__txpower) \
4663 +       ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
4664 +
4665 +#define TXPOWER_A_TO_DEV(__txpower) \
4666 +       clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER)
4667 +
4668 +#endif /* RT2800PCI_H */
4669 --- /dev/null
4670 +++ b/drivers/net/wireless/rt2x00/rt2800usb.c
4671 @@ -0,0 +1,2594 @@
4672 +/*
4673 +       Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
4674 +       <http://rt2x00.serialmonkey.com>
4675 +
4676 +       This program is free software; you can redistribute it and/or modify
4677 +       it under the terms of the GNU General Public License as published by
4678 +       the Free Software Foundation; either version 2 of the License, or
4679 +       (at your option) any later version.
4680 +
4681 +       This program is distributed in the hope that it will be useful,
4682 +       but WITHOUT ANY WARRANTY; without even the implied warranty of
4683 +       MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4684 +       GNU General Public License for more details.
4685 +
4686 +       You should have received a copy of the GNU General Public License
4687 +       along with this program; if not, write to the
4688 +       Free Software Foundation, Inc.,
4689 +       59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
4690 + */
4691 +
4692 +/*
4693 +       Module: rt2800usb
4694 +       Abstract: rt2800usb device specific routines.
4695 +       Supported chipsets: RT2800U.
4696 + */
4697 +
4698 +#include <linux/crc-ccitt.h>
4699 +#include <linux/delay.h>
4700 +#include <linux/etherdevice.h>
4701 +#include <linux/init.h>
4702 +#include <linux/kernel.h>
4703 +#include <linux/module.h>
4704 +#include <linux/usb.h>
4705 +
4706 +#include "rt2x00.h"
4707 +#include "rt2x00usb.h"
4708 +#include "rt2800usb.h"
4709 +
4710 +/*
4711 + * Allow hardware encryption to be disabled.
4712 + */
4713 +static int modparam_nohwcrypt = 0;
4714 +module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
4715 +MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
4716 +
4717 +/*
4718 + * Register access.
4719 + * All access to the CSR registers will go through the methods
4720 + * rt2800usb_register_read and rt2800usb_register_write.
4721 + * BBP and RF register require indirect register access,
4722 + * and use the CSR registers BBPCSR and RFCSR to achieve this.
4723 + * These indirect registers work with busy bits,
4724 + * and we will try maximal REGISTER_BUSY_COUNT times to access
4725 + * the register while taking a REGISTER_BUSY_DELAY us delay
4726 + * between each attampt. When the busy bit is still set at that time,
4727 + * the access attempt is considered to have failed,
4728 + * and we will print an error.
4729 + * The _lock versions must be used if you already hold the usb_cache_mutex
4730 + */
4731 +static inline void rt2800usb_register_read(struct rt2x00_dev *rt2x00dev,
4732 +                                          const unsigned int offset,
4733 +                                          u32 *value)
4734 +{
4735 +       __le32 reg;
4736 +       rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
4737 +                                     USB_VENDOR_REQUEST_IN, offset,
4738 +                                     &reg, sizeof(u32), REGISTER_TIMEOUT);
4739 +       *value = le32_to_cpu(reg);
4740 +}
4741 +
4742 +static inline void rt2800usb_register_read_lock(struct rt2x00_dev *rt2x00dev,
4743 +                                               const unsigned int offset,
4744 +                                               u32 *value)
4745 +{
4746 +       __le32 reg;
4747 +       rt2x00usb_vendor_req_buff_lock(rt2x00dev, USB_MULTI_READ,
4748 +                                      USB_VENDOR_REQUEST_IN, offset,
4749 +                                      &reg, sizeof(u32), REGISTER_TIMEOUT);
4750 +       *value = le32_to_cpu(reg);
4751 +}
4752 +
4753 +static inline void rt2800usb_register_multiread(struct rt2x00_dev *rt2x00dev,
4754 +                                               const unsigned int offset,
4755 +                                               void *value, const u32 length)
4756 +{
4757 +       int timeout = REGISTER_TIMEOUT * (length / sizeof(u32));
4758 +       rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
4759 +                                     USB_VENDOR_REQUEST_IN, offset,
4760 +                                     value, length, timeout);
4761 +}
4762 +
4763 +static inline void rt2800usb_register_write(struct rt2x00_dev *rt2x00dev,
4764 +                                           const unsigned int offset,
4765 +                                           u32 value)
4766 +{
4767 +       __le32 reg = cpu_to_le32(value);
4768 +       rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
4769 +                                     USB_VENDOR_REQUEST_OUT, offset,
4770 +                                     &reg, sizeof(u32), REGISTER_TIMEOUT);
4771 +}
4772 +
4773 +static inline void rt2800usb_register_write_lock(struct rt2x00_dev *rt2x00dev,
4774 +                                                const unsigned int offset,
4775 +                                                u32 value)
4776 +{
4777 +       __le32 reg = cpu_to_le32(value);
4778 +       rt2x00usb_vendor_req_buff_lock(rt2x00dev, USB_MULTI_WRITE,
4779 +                                      USB_VENDOR_REQUEST_OUT, offset,
4780 +                                     &reg, sizeof(u32), REGISTER_TIMEOUT);
4781 +}
4782 +
4783 +static inline void rt2800usb_register_multiwrite(struct rt2x00_dev *rt2x00dev,
4784 +                                                const unsigned int offset,
4785 +                                                void *value, const u32 length)
4786 +{
4787 +       int timeout = REGISTER_TIMEOUT * (length / sizeof(u32));
4788 +       rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
4789 +                                     USB_VENDOR_REQUEST_OUT, offset,
4790 +                                     value, length, timeout);
4791 +}
4792 +
4793 +static u32 rt2800usb_bbp_check(struct rt2x00_dev *rt2x00dev)
4794 +{
4795 +       u32 reg;
4796 +       unsigned int i;
4797 +
4798 +       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
4799 +               rt2800usb_register_read_lock(rt2x00dev, BBP_CSR_CFG, &reg);
4800 +               if (!rt2x00_get_field32(reg, BBP_CSR_CFG_BUSY))
4801 +                       break;
4802 +               udelay(REGISTER_BUSY_DELAY);
4803 +       }
4804 +
4805 +       return reg;
4806 +}
4807 +
4808 +static void rt2800usb_bbp_write(struct rt2x00_dev *rt2x00dev,
4809 +                               const unsigned int word, const u8 value)
4810 +{
4811 +       u32 reg;
4812 +
4813 +       mutex_lock(&rt2x00dev->usb_cache_mutex);
4814 +
4815 +       /*
4816 +        * Wait until the BBP becomes ready.
4817 +        */
4818 +       reg = rt2800usb_bbp_check(rt2x00dev);
4819 +       if (rt2x00_get_field32(reg, BBP_CSR_CFG_BUSY)) {
4820 +               ERROR(rt2x00dev, "BBP_CSR_CFG register busy. Write failed.\n");
4821 +               mutex_unlock(&rt2x00dev->usb_cache_mutex);
4822 +               return;
4823 +       }
4824 +
4825 +       /*
4826 +        * Write the data into the BBP.
4827 +        */
4828 +       reg = 0;
4829 +       rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
4830 +       rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
4831 +       rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
4832 +       rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
4833 +
4834 +       rt2800usb_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
4835 +       mutex_unlock(&rt2x00dev->usb_cache_mutex);
4836 +}
4837 +
4838 +static void rt2800usb_bbp_read(struct rt2x00_dev *rt2x00dev,
4839 +                              const unsigned int word, u8 *value)
4840 +{
4841 +       u32 reg;
4842 +
4843 +       mutex_lock(&rt2x00dev->usb_cache_mutex);
4844 +
4845 +       /*
4846 +        * Wait until the BBP becomes ready.
4847 +        */
4848 +       reg = rt2800usb_bbp_check(rt2x00dev);
4849 +       if (rt2x00_get_field32(reg, BBP_CSR_CFG_BUSY)) {
4850 +               ERROR(rt2x00dev, "BBP_CSR_CFG register busy. Read failed.\n");
4851 +               mutex_unlock(&rt2x00dev->usb_cache_mutex);
4852 +               return;
4853 +       }
4854 +
4855 +       /*
4856 +        * Write the request into the BBP.
4857 +        */
4858 +       reg = 0;
4859 +       rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
4860 +       rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
4861 +       rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
4862 +
4863 +       rt2800usb_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
4864 +
4865 +       /*
4866 +        * Wait until the BBP becomes ready.
4867 +        */
4868 +       reg = rt2800usb_bbp_check(rt2x00dev);
4869 +       if (rt2x00_get_field32(reg, BBP_CSR_CFG_BUSY)) {
4870 +               ERROR(rt2x00dev, "BBP_CSR_CFG register busy. Read failed.\n");
4871 +               *value = 0xff;
4872 +               return;
4873 +       }
4874 +
4875 +       *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
4876 +       mutex_unlock(&rt2x00dev->usb_cache_mutex);
4877 +}
4878 +
4879 +static void rt2800usb_rf_write(struct rt2x00_dev *rt2x00dev,
4880 +                              const unsigned int word, const u32 value)
4881 +{
4882 +       u32 reg;
4883 +       unsigned int i;
4884 +
4885 +       if (!word)
4886 +               return;
4887 +
4888 +       mutex_lock(&rt2x00dev->usb_cache_mutex);
4889 +
4890 +       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
4891 +               rt2800usb_register_read_lock(rt2x00dev, RF_CSR_CFG0, &reg);
4892 +               if (!rt2x00_get_field32(reg, RF_CSR_CFG0_BUSY))
4893 +                       goto rf_write;
4894 +               udelay(REGISTER_BUSY_DELAY);
4895 +       }
4896 +
4897 +       mutex_unlock(&rt2x00dev->usb_cache_mutex);
4898 +       ERROR(rt2x00dev, "RF_CSR_CFG0 register busy. Write failed.\n");
4899 +       return;
4900 +
4901 +rf_write:
4902 +       reg = 0;
4903 +       rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
4904 +       rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
4905 +       rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
4906 +       rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
4907 +
4908 +       rt2800usb_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
4909 +       rt2x00_rf_write(rt2x00dev, word, value);
4910 +       mutex_unlock(&rt2x00dev->usb_cache_mutex);
4911 +}
4912 +
4913 +static void rt2800usb_mcu_request(struct rt2x00_dev *rt2x00dev,
4914 +                                 const u8 command, const u8 token,
4915 +                                 const u8 arg0, const u8 arg1)
4916 +{
4917 +       unsigned int i;
4918 +       u32 reg;
4919 +
4920 +       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
4921 +               rt2800usb_register_read(rt2x00dev, H2M_MAILBOX_CSR, &reg);
4922 +               if (!rt2x00_get_field32(reg, H2M_MAILBOX_CSR_OWNER))
4923 +                       goto mcu_write;
4924 +               udelay(REGISTER_BUSY_DELAY);
4925 +       }
4926 +
4927 +       ERROR(rt2x00dev, "mcu request error. "
4928 +             "Request 0x%02x failed for token 0x%02x.\n",
4929 +             command, token);
4930 +       return;
4931 +
4932 +mcu_write:
4933 +       rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
4934 +       rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
4935 +       rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
4936 +       rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
4937 +       rt2800usb_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
4938 +
4939 +       reg = 0;
4940 +       rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
4941 +       rt2800usb_register_write(rt2x00dev, HOST_CMD_CSR, reg);
4942 +}
4943 +
4944 +#ifdef CONFIG_RT2X00_LIB_DEBUGFS
4945 +static const struct rt2x00debug rt2800usb_rt2x00debug = {
4946 +       .owner  = THIS_MODULE,
4947 +       .csr    = {
4948 +               .read           = rt2800usb_register_read,
4949 +               .write          = rt2800usb_register_write,
4950 +               .flags          = RT2X00DEBUGFS_OFFSET,
4951 +               .word_base      = CSR_REG_BASE,
4952 +               .word_size      = sizeof(u32),
4953 +               .word_count     = CSR_REG_SIZE / sizeof(u32),
4954 +       },
4955 +       .eeprom = {
4956 +               .read           = rt2x00_eeprom_read,
4957 +               .write          = rt2x00_eeprom_write,
4958 +               .word_base      = EEPROM_BASE,
4959 +               .word_size      = sizeof(u16),
4960 +               .word_count     = EEPROM_SIZE / sizeof(u16),
4961 +       },
4962 +       .bbp    = {
4963 +               .read           = rt2800usb_bbp_read,
4964 +               .write          = rt2800usb_bbp_write,
4965 +               .word_base      = BBP_BASE,
4966 +               .word_size      = sizeof(u8),
4967 +               .word_count     = BBP_SIZE / sizeof(u8),
4968 +       },
4969 +       .rf     = {
4970 +               .read           = rt2x00_rf_read,
4971 +               .write          = rt2800usb_rf_write,
4972 +               .word_base      = RF_BASE,
4973 +               .word_size      = sizeof(u32),
4974 +               .word_count     = RF_SIZE / sizeof(u32),
4975 +       },
4976 +};
4977 +#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
4978 +
4979 +#ifdef CONFIG_RT2X00_LIB_LEDS
4980 +static void rt2800usb_brightness_set(struct led_classdev *led_cdev,
4981 +                                    enum led_brightness brightness)
4982 +{
4983 +       struct rt2x00_led *led =
4984 +           container_of(led_cdev, struct rt2x00_led, led_dev);
4985 +       unsigned int enabled = brightness != LED_OFF;
4986 +       unsigned int bg_mode =
4987 +           (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
4988 +       unsigned int polarity =
4989 +               rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
4990 +                                  EEPROM_FREQ_LED_POLARITY);
4991 +       unsigned int ledmode =
4992 +               rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
4993 +                                  EEPROM_FREQ_LED_MODE);
4994 +
4995 +       if (led->type == LED_TYPE_RADIO) {
4996 +               rt2800usb_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
4997 +                                     enabled ? 0x20 : 0);
4998 +       } else if (led->type == LED_TYPE_ASSOC) {
4999 +               rt2800usb_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
5000 +                                     enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
5001 +       } else if (led->type == LED_TYPE_QUALITY) {
5002 +               /*
5003 +                * The brightness is divided into 6 levels (0 - 5),
5004 +                * The specs tell us the following levels:
5005 +                *      0, 1 ,3, 7, 15, 31
5006 +                * to determine the level in a simple way we can simply
5007 +                * work with bitshifting:
5008 +                *      (1 << level) - 1
5009 +                */
5010 +               rt2800usb_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
5011 +                                     (1 << brightness / (LED_FULL / 6)) - 1,
5012 +                                     polarity);
5013 +       }
5014 +}
5015 +
5016 +static int rt2800usb_blink_set(struct led_classdev *led_cdev,
5017 +                              unsigned long *delay_on,
5018 +                              unsigned long *delay_off)
5019 +{
5020 +       struct rt2x00_led *led =
5021 +           container_of(led_cdev, struct rt2x00_led, led_dev);
5022 +       u32 reg;
5023 +
5024 +       rt2800usb_register_read(led->rt2x00dev, LED_CFG, &reg);
5025 +       rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
5026 +       rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
5027 +       rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
5028 +       rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
5029 +       rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 12);
5030 +       rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
5031 +       rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
5032 +       rt2800usb_register_write(led->rt2x00dev, LED_CFG, reg);
5033 +
5034 +       return 0;
5035 +}
5036 +
5037 +static void rt2800usb_init_led(struct rt2x00_dev *rt2x00dev,
5038 +                              struct rt2x00_led *led,
5039 +                              enum led_type type)
5040 +{
5041 +       led->rt2x00dev = rt2x00dev;
5042 +       led->type = type;
5043 +       led->led_dev.brightness_set = rt2800usb_brightness_set;
5044 +       led->led_dev.blink_set = rt2800usb_blink_set;
5045 +       led->flags = LED_INITIALIZED;
5046 +}
5047 +#endif /* CONFIG_RT2X00_LIB_LEDS */
5048 +
5049 +/*
5050 + * Configuration handlers.
5051 + */
5052 +static void rt2800usb_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
5053 +                                      struct rt2x00lib_crypto *crypto,
5054 +                                      struct ieee80211_key_conf *key)
5055 +{
5056 +       u32 offset;
5057 +       u32 reg;
5058 +
5059 +       offset = MAC_WCID_ATTR_ENTRY(crypto->aid);
5060 +
5061 +       reg = 0;
5062 +       rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
5063 +                          !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
5064 +       rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_PAIRKEY_MODE,
5065 +                          crypto->cipher);
5066 +       rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
5067 +                          (crypto->cmd == SET_KEY) ? crypto->bssidx : 0);
5068 +       rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
5069 +       rt2800usb_register_write(rt2x00dev, offset, reg);
5070 +}
5071 +
5072 +static int rt2800usb_config_shared_key(struct rt2x00_dev *rt2x00dev,
5073 +                                      struct rt2x00lib_crypto *crypto,
5074 +                                      struct ieee80211_key_conf *key)
5075 +{
5076 +       struct hw_key_entry key_entry;
5077 +       struct rt2x00_field32 field;
5078 +       int timeout;
5079 +       u32 offset;
5080 +       u32 mask;
5081 +       u32 reg;
5082 +
5083 +       if (crypto->cmd == SET_KEY) {
5084 +               memcpy(key_entry.key, crypto->key,
5085 +                      sizeof(key_entry.key));
5086 +               memcpy(key_entry.tx_mic, crypto->tx_mic,
5087 +                      sizeof(key_entry.tx_mic));
5088 +               memcpy(key_entry.rx_mic, crypto->rx_mic,
5089 +                      sizeof(key_entry.rx_mic));
5090 +
5091 +               offset = SHARED_KEY_ENTRY(key->hw_key_idx);
5092 +               timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
5093 +               rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
5094 +                                                   USB_VENDOR_REQUEST_OUT,
5095 +                                                   offset, &key_entry,
5096 +                                                   sizeof(key_entry),
5097 +                                                   timeout);
5098 +
5099 +               /*
5100 +                * The driver does not support the IV/EIV generation
5101 +                * in hardware. However it doesn't support the IV/EIV
5102 +                * inside the ieee80211 frame either, but requires it
5103 +                * to be provided seperately for the descriptor.
5104 +                * rt2x00lib will cut the IV/EIV data out of all frames
5105 +                * given to us by mac80211, but we must tell mac80211
5106 +                * to generate the IV/EIV data.
5107 +                */
5108 +               key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
5109 +       }
5110 +
5111 +       /*
5112 +        * The cipher types are stored over multiple registers
5113 +        * starting with SHARED_KEY_MODE_BASE each word will have
5114 +        * 32 bits and contains the cipher types for 2 modes each.
5115 +        * Using the correct defines correctly will cause overhead,
5116 +        * so just calculate the correct offset.
5117 +        */
5118 +       mask = key->hw_key_idx % 8;
5119 +       field.bit_offset = (3 * mask);
5120 +       field.bit_mask = 0x7 << field.bit_offset;
5121 +
5122 +       offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
5123 +       rt2800usb_register_read(rt2x00dev, offset, &reg);
5124 +       rt2x00_set_field32(&reg, field,
5125 +                          (crypto->cmd == SET_KEY) ? crypto->cipher : 0);
5126 +       rt2800usb_register_write(rt2x00dev, offset, reg);
5127 +
5128 +       /*
5129 +        * Update WCID information
5130 +        */
5131 +       rt2800usb_config_wcid_attr(rt2x00dev, crypto, key);
5132 +
5133 +       return 0;
5134 +}
5135 +
5136 +static int rt2800usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
5137 +                                        struct rt2x00lib_crypto *crypto,
5138 +                                        struct ieee80211_key_conf *key)
5139 +{
5140 +       struct hw_key_entry key_entry;
5141 +       int timeout;
5142 +       u32 offset;
5143 +
5144 +       /*
5145 +        * 1 pairwise key is possible per AID, this means that the AID
5146 +        * equals our hw_key_idx.
5147 +        */
5148 +       key->hw_key_idx = crypto->aid;
5149 +
5150 +       if (crypto->cmd == SET_KEY) {
5151 +               memcpy(key_entry.key, crypto->key,
5152 +                      sizeof(key_entry.key));
5153 +               memcpy(key_entry.tx_mic, crypto->tx_mic,
5154 +                      sizeof(key_entry.tx_mic));
5155 +               memcpy(key_entry.rx_mic, crypto->rx_mic,
5156 +                      sizeof(key_entry.rx_mic));
5157 +
5158 +               offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
5159 +               timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
5160 +               rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
5161 +                                                   USB_VENDOR_REQUEST_OUT,
5162 +                                                   offset, &key_entry,
5163 +                                                   sizeof(key_entry),
5164 +                                                   timeout);
5165 +
5166 +               /*
5167 +                * The driver does not support the IV/EIV generation
5168 +                * in hardware. However it doesn't support the IV/EIV
5169 +                * inside the ieee80211 frame either, but requires it
5170 +                * to be provided seperately for the descriptor.
5171 +                * rt2x00lib will cut the IV/EIV data out of all frames
5172 +                * given to us by mac80211, but we must tell mac80211
5173 +                * to generate the IV/EIV data.
5174 +                */
5175 +               key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
5176 +       }
5177 +
5178 +       /*
5179 +        * Update WCID information
5180 +        */
5181 +       rt2800usb_config_wcid_attr(rt2x00dev, crypto, key);
5182 +
5183 +       return 0;
5184 +}
5185 +
5186 +static void rt2800usb_config_filter(struct rt2x00_dev *rt2x00dev,
5187 +                                   const unsigned int filter_flags)
5188 +{
5189 +       u32 reg;
5190 +
5191 +       /*
5192 +        * Start configuration steps.
5193 +        * Note that the version error will always be dropped
5194 +        * and broadcast frames will always be accepted since
5195 +        * there is no filter for it at this time.
5196 +        */
5197 +       rt2800usb_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
5198 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
5199 +                          !(filter_flags & FIF_FCSFAIL));
5200 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
5201 +                          !(filter_flags & FIF_PLCPFAIL));
5202 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
5203 +                          !(filter_flags & FIF_PROMISC_IN_BSS));
5204 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
5205 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
5206 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
5207 +                          !(filter_flags & FIF_ALLMULTI));
5208 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
5209 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
5210 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
5211 +                          !(filter_flags & FIF_CONTROL));
5212 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
5213 +                          !(filter_flags & FIF_CONTROL));
5214 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
5215 +                          !(filter_flags & FIF_CONTROL));
5216 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
5217 +                          !(filter_flags & FIF_CONTROL));
5218 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
5219 +                          !(filter_flags & FIF_CONTROL));
5220 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
5221 +                          !(filter_flags & FIF_CONTROL));
5222 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
5223 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 1);
5224 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
5225 +                          !(filter_flags & FIF_CONTROL));
5226 +       rt2800usb_register_write(rt2x00dev, RX_FILTER_CFG, reg);
5227 +}
5228 +
5229 +static void rt2800usb_config_intf(struct rt2x00_dev *rt2x00dev,
5230 +                                 struct rt2x00_intf *intf,
5231 +                                 struct rt2x00intf_conf *conf,
5232 +                                 const unsigned int flags)
5233 +{
5234 +       unsigned int beacon_base;
5235 +       u32 reg;
5236 +
5237 +       if (flags & CONFIG_UPDATE_TYPE) {
5238 +               /*
5239 +                * Clear current synchronisation setup.
5240 +                * For the Beacon base registers we only need to clear
5241 +                * the first byte since that byte contains the VALID and OWNER
5242 +                * bits which (when set to 0) will invalidate the entire beacon.
5243 +                */
5244 +               beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
5245 +               rt2800usb_register_write(rt2x00dev, beacon_base, 0);
5246 +
5247 +               /*
5248 +                * Enable synchronisation.
5249 +                */
5250 +               rt2800usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
5251 +               rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
5252 +               rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
5253 +               rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
5254 +               rt2800usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
5255 +       }
5256 +
5257 +       if (flags & CONFIG_UPDATE_MAC) {
5258 +               reg = le32_to_cpu(conf->mac[1]);
5259 +               rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
5260 +               conf->mac[1] = cpu_to_le32(reg);
5261 +
5262 +               rt2800usb_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
5263 +                                             conf->mac, sizeof(conf->mac));
5264 +       }
5265 +
5266 +       if (flags & CONFIG_UPDATE_BSSID) {
5267 +               reg = le32_to_cpu(conf->bssid[1]);
5268 +               rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
5269 +               rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
5270 +               conf->bssid[1] = cpu_to_le32(reg);
5271 +
5272 +               rt2800usb_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
5273 +                                             conf->bssid, sizeof(conf->bssid));
5274 +       }
5275 +}
5276 +
5277 +static void rt2800usb_config_erp(struct rt2x00_dev *rt2x00dev,
5278 +                                struct rt2x00lib_erp *erp)
5279 +{
5280 +       u32 reg;
5281 +
5282 +       rt2800usb_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
5283 +       rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT,
5284 +                          erp->ack_timeout);
5285 +       rt2800usb_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
5286 +
5287 +       rt2800usb_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
5288 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
5289 +                          !!erp->short_preamble);
5290 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
5291 +                          !!erp->short_preamble);
5292 +       rt2800usb_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
5293 +
5294 +       rt2800usb_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
5295 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
5296 +                          erp->cts_protection ? 2 : 0);
5297 +       rt2800usb_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
5298 +
5299 +       rt2800usb_register_write(rt2x00dev, LEGACY_BASIC_RATE,
5300 +                                erp->basic_rates);
5301 +       rt2800usb_register_write(rt2x00dev, HT_BASIC_RATE,
5302 +                                erp->basic_rates >> 32);
5303 +
5304 +       rt2800usb_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
5305 +       rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
5306 +       rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
5307 +       rt2800usb_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
5308 +
5309 +       rt2800usb_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
5310 +       rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
5311 +       rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
5312 +       rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
5313 +       rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
5314 +       rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
5315 +       rt2800usb_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
5316 +}
5317 +
5318 +static void rt2800usb_config_ant(struct rt2x00_dev *rt2x00dev,
5319 +                                struct antenna_setup *ant)
5320 +{
5321 +       u16 eeprom;
5322 +       u8 r1;
5323 +       u8 r3;
5324 +
5325 +       /*
5326 +        * FIXME: Use requested antenna configuration.
5327 +        */
5328 +
5329 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
5330 +
5331 +       rt2800usb_bbp_read(rt2x00dev, 1, &r1);
5332 +       rt2800usb_bbp_read(rt2x00dev, 3, &r3);
5333 +
5334 +       /*
5335 +        * Configure the TX antenna.
5336 +        */
5337 +       switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH)) {
5338 +       case 1:
5339 +               rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
5340 +               break;
5341 +       case 2:
5342 +       case 3:
5343 +               /* Do nothing */
5344 +               break;
5345 +       }
5346 +
5347 +       /*
5348 +        * Configure the RX antenna.
5349 +        */
5350 +       switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
5351 +       case 1:
5352 +               rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
5353 +               break;
5354 +       case 2:
5355 +               rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
5356 +               break;
5357 +       case 3:
5358 +               rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
5359 +               break;
5360 +       }
5361 +
5362 +       rt2800usb_bbp_write(rt2x00dev, 3, r3);
5363 +       rt2800usb_bbp_write(rt2x00dev, 1, r1);
5364 +}
5365 +
5366 +static void rt2800usb_config_lna_gain(struct rt2x00_dev *rt2x00dev,
5367 +                                     struct rt2x00lib_conf *libconf)
5368 +{
5369 +       u16 eeprom;
5370 +       short lna_gain;
5371 +
5372 +       if (libconf->rf.channel <= 14) {
5373 +               rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
5374 +               lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
5375 +       } else if (libconf->rf.channel <= 64) {
5376 +               rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
5377 +               lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
5378 +       } else if (libconf->rf.channel <= 128) {
5379 +               rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
5380 +               lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
5381 +       } else {
5382 +               rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
5383 +               lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
5384 +       }
5385 +
5386 +       rt2x00dev->lna_gain = lna_gain;
5387 +}
5388 +
5389 +static void rt2800usb_config_channel(struct rt2x00_dev *rt2x00dev,
5390 +                                    struct rf_channel *rf,
5391 +                                    struct channel_info *info)
5392 +{
5393 +       u32 reg;
5394 +       unsigned int tx_pin;
5395 +       u16 eeprom;
5396 +
5397 +       tx_pin = 0;
5398 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
5399 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
5400 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
5401 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
5402 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
5403 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
5404 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
5405 +
5406 +       rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
5407 +
5408 +       /*
5409 +        * Determine antenna settings from EEPROM
5410 +        */
5411 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
5412 +       if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1) {
5413 +               rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
5414 +               /* Turn off unused PA or LNA when only 1T or 1R */
5415 +               rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 0);
5416 +               rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 0);
5417 +       }
5418 +
5419 +       if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1) {
5420 +               rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
5421 +               rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
5422 +               /* Turn off unused PA or LNA when only 1T or 1R */
5423 +               rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 0);
5424 +               rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 0);
5425 +       } else if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 2)
5426 +               rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
5427 +
5428 +       if (rf->channel > 14) {
5429 +               /*
5430 +                * When TX power is below 0, we should increase it by 7 to
5431 +                * make it a positive value (Minumum value is -7).
5432 +                * However this means that values between 0 and 7 have
5433 +                * double meaning, and we should set a 7DBm boost flag.
5434 +                */
5435 +               rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
5436 +                                  (info->tx_power1 >= 0));
5437 +
5438 +               if (info->tx_power1 < 0)
5439 +                       info->tx_power1 += 7;
5440 +
5441 +               rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
5442 +                                  TXPOWER_A_TO_DEV(info->tx_power1));
5443 +
5444 +               rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
5445 +                                  (info->tx_power2 >= 0));
5446 +
5447 +               if (info->tx_power2 < 0)
5448 +                       info->tx_power2 += 7;
5449 +
5450 +               rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
5451 +                                  TXPOWER_A_TO_DEV(info->tx_power2));
5452 +
5453 +               rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
5454 +       } else {
5455 +               rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
5456 +                                  TXPOWER_G_TO_DEV(info->tx_power1));
5457 +               rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
5458 +                                  TXPOWER_G_TO_DEV(info->tx_power2));
5459 +
5460 +               rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
5461 +       }
5462 +
5463 +
5464 +       /* FIXME: How to determine bandwidth
5465 +       rt2x00_set_field32(&rf->rf4, RF4_BW40, !!(BBPCurrentBW == BW_40));
5466 +       */
5467 +
5468 +       rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
5469 +       rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
5470 +       rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
5471 +       rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
5472 +
5473 +       udelay(200);
5474 +
5475 +       rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
5476 +       rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
5477 +       rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
5478 +       rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
5479 +
5480 +       udelay(200);
5481 +
5482 +       rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
5483 +       rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
5484 +       rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
5485 +       rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
5486 +
5487 +       /*
5488 +        * Change BBP settings
5489 +        */
5490 +       rt2800usb_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
5491 +       rt2800usb_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
5492 +       rt2800usb_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
5493 +       rt2800usb_bbp_write(rt2x00dev, 86, 0);
5494 +
5495 +       if (rf->channel <= 14) {
5496 +               if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
5497 +                       rt2800usb_bbp_write(rt2x00dev, 82, 0x62);
5498 +                       rt2800usb_bbp_write(rt2x00dev, 75, 0x46);
5499 +               } else {
5500 +                       rt2800usb_bbp_write(rt2x00dev, 82, 0x84);
5501 +                       rt2800usb_bbp_write(rt2x00dev, 75, 0x50);
5502 +               }
5503 +
5504 +               rt2800usb_register_read(rt2x00dev, TX_BAND_CFG, &reg);
5505 +               rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_A, 0);
5506 +               rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_BG, 1);
5507 +               rt2800usb_register_write(rt2x00dev, TX_BAND_CFG, reg);
5508 +       } else {
5509 +               rt2800usb_bbp_write(rt2x00dev, 82, 0xf2);
5510 +
5511 +               if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
5512 +                       rt2800usb_bbp_write(rt2x00dev, 75, 0x46);
5513 +               else
5514 +                       rt2800usb_bbp_write(rt2x00dev, 75, 0x50);
5515 +
5516 +               rt2800usb_register_read(rt2x00dev, TX_BAND_CFG, &reg);
5517 +               rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_A, 1);
5518 +               rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_BG, 0);
5519 +               rt2800usb_register_write(rt2x00dev, TX_BAND_CFG, reg);
5520 +       }
5521 +
5522 +       rt2800usb_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
5523 +
5524 +       msleep(1);
5525 +}
5526 +
5527 +static void rt2800usb_config_txpower(struct rt2x00_dev *rt2x00dev,
5528 +                                    const int txpower)
5529 +{
5530 +       u32 reg;
5531 +       u32 value = TXPOWER_G_TO_DEV(txpower);
5532 +       u8 r1;
5533 +
5534 +       rt2800usb_bbp_read(rt2x00dev, 1, &r1);
5535 +       rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
5536 +       rt2800usb_bbp_write(rt2x00dev, 1, r1);
5537 +
5538 +       rt2800usb_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
5539 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
5540 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
5541 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
5542 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
5543 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
5544 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
5545 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
5546 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
5547 +       rt2800usb_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
5548 +
5549 +       rt2800usb_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
5550 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
5551 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
5552 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
5553 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
5554 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
5555 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
5556 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
5557 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
5558 +       rt2800usb_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
5559 +
5560 +       rt2800usb_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
5561 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
5562 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
5563 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
5564 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
5565 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
5566 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
5567 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
5568 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
5569 +       rt2800usb_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
5570 +
5571 +       rt2800usb_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
5572 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
5573 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
5574 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
5575 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
5576 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
5577 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
5578 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
5579 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
5580 +       rt2800usb_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
5581 +
5582 +       rt2800usb_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
5583 +       rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
5584 +       rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
5585 +       rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
5586 +       rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
5587 +       rt2800usb_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
5588 +}
5589 +
5590 +static void rt2800usb_config_retry_limit(struct rt2x00_dev *rt2x00dev,
5591 +                                        struct rt2x00lib_conf *libconf)
5592 +{
5593 +       u32 reg;
5594 +
5595 +       rt2800usb_register_read(rt2x00dev, TX_RTY_CFG, &reg);
5596 +       rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
5597 +                          libconf->conf->short_frame_max_tx_count);
5598 +       rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
5599 +                          libconf->conf->long_frame_max_tx_count);
5600 +       rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
5601 +       rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
5602 +       rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
5603 +       rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
5604 +       rt2800usb_register_write(rt2x00dev, TX_RTY_CFG, reg);
5605 +}
5606 +
5607 +static void rt2800usb_config_duration(struct rt2x00_dev *rt2x00dev,
5608 +                                     struct rt2x00lib_conf *libconf)
5609 +{
5610 +       u32 reg;
5611 +
5612 +       rt2800usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
5613 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
5614 +                          libconf->conf->beacon_int * 16);
5615 +       rt2800usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
5616 +}
5617 +
5618 +static void rt2800usb_config(struct rt2x00_dev *rt2x00dev,
5619 +                            struct rt2x00lib_conf *libconf,
5620 +                            const unsigned int flags)
5621 +{
5622 +       /* Always recalculate LNA gain before changing configuration */
5623 +       rt2800usb_config_lna_gain(rt2x00dev, libconf);
5624 +
5625 +       if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
5626 +               rt2800usb_config_channel(rt2x00dev, &libconf->rf,
5627 +                                        &libconf->channel);
5628 +       if (flags & IEEE80211_CONF_CHANGE_POWER)
5629 +               rt2800usb_config_txpower(rt2x00dev, libconf->conf->power_level);
5630 +       if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
5631 +               rt2800usb_config_retry_limit(rt2x00dev, libconf);
5632 +       if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
5633 +               rt2800usb_config_duration(rt2x00dev, libconf);
5634 +}
5635 +
5636 +/*
5637 + * Link tuning
5638 + */
5639 +static void rt2800usb_link_stats(struct rt2x00_dev *rt2x00dev,
5640 +                                struct link_qual *qual)
5641 +{
5642 +       u32 reg;
5643 +
5644 +       /*
5645 +        * Update FCS error count from register.
5646 +        */
5647 +       rt2800usb_register_read(rt2x00dev, RX_STA_CNT0, &reg);
5648 +       qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
5649 +
5650 +       /*
5651 +        * Update False CCA count from register.
5652 +        */
5653 +       rt2800usb_register_read(rt2x00dev, RX_STA_CNT1, &reg);
5654 +       qual->false_cca = rt2x00_get_field32(reg, RX_STA_CNT1_FALSE_CCA);
5655 +}
5656 +
5657 +static void rt2800usb_reset_tuner(struct rt2x00_dev *rt2x00dev)
5658 +{
5659 +       u8 r66;
5660 +
5661 +       if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ)
5662 +               r66 = 0x2e + rt2x00dev->lna_gain;
5663 +       else {
5664 +               if (1 /* FIXME:  pAd->CommonCfg.BBPCurrentBW == BW_20 */)
5665 +                       r66 = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
5666 +               else
5667 +                       r66 = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
5668 +       }
5669 +
5670 +       rt2800usb_bbp_write(rt2x00dev, 66, r66);
5671 +}
5672 +
5673 +static void rt2800usb_link_tuner(struct rt2x00_dev *rt2x00dev)
5674 +{
5675 +       int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
5676 +       u8 r66_orig;
5677 +       u8 r66;
5678 +
5679 +       if (rt2x00_rev(&rt2x00dev->chip) == RT2870_VERSION_C)
5680 +               return;
5681 +
5682 +       rt2800usb_bbp_read(rt2x00dev, 66, &r66_orig);
5683 +       r66 = r66_orig;
5684 +
5685 +       if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
5686 +               r66 = 0x2e + rt2x00dev->lna_gain;
5687 +       } else {
5688 +               if (1 /* FIXME: pAd->CommonCfg.BBPCurrentBW == BW_20 */)
5689 +                       r66 = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
5690 +               else
5691 +                       r66 = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
5692 +       }
5693 +
5694 +       if (rssi > -80)
5695 +               r66 += 0x10;
5696 +
5697 +       if (rssi != r66_orig)
5698 +               rt2800usb_bbp_write(rt2x00dev, 66, r66);
5699 +}
5700 +
5701 +/*
5702 + * Firmware functions
5703 + */
5704 +static char *rt2800usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
5705 +{
5706 +       return FIRMWARE_RT2870;
5707 +}
5708 +
5709 +static u16 rt2800usb_get_firmware_crc(const void *data, const size_t len)
5710 +{
5711 +       u16 crc;
5712 +
5713 +       /*
5714 +        * Use the crc ccitt algorithm.
5715 +        * This will return the same value as the legacy driver which
5716 +        * used bit ordering reversion on the both the firmware bytes
5717 +        * before input input as well as on the final output.
5718 +        * Obviously using crc ccitt directly is much more efficient.
5719 +        * The last 2 bytes in the firmware array are the crc checksum itself,
5720 +        * this means that we should never pass those 2 bytes to the crc
5721 +        * algorithm.
5722 +        */
5723 +       crc = crc_ccitt(~0, data, len - 2);
5724 +
5725 +       /*
5726 +        * There is a small difference between the crc-itu-t + bitrev and
5727 +        * the crc-ccitt crc calculation. In the latter method the 2 bytes
5728 +        * will be swapped, use swab16 to convert the crc to the correct
5729 +        * value.
5730 +        */
5731 +       return swab16(crc);
5732 +}
5733 +
5734 +static int rt2800usb_load_firmware(struct rt2x00_dev *rt2x00dev,
5735 +                                  const void *data, const size_t len)
5736 +{
5737 +       unsigned int i;
5738 +       int status;
5739 +       u32 reg;
5740 +
5741 +       /*
5742 +        * Wait for stable hardware.
5743 +        */
5744 +       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
5745 +               rt2800usb_register_read(rt2x00dev, MAC_CSR0, &reg);
5746 +               if (reg && reg != ~0)
5747 +                       break;
5748 +               msleep(1);
5749 +       }
5750 +
5751 +       if (i == REGISTER_BUSY_COUNT) {
5752 +               ERROR(rt2x00dev, "Unstable hardware.\n");
5753 +               return -EBUSY;
5754 +       }
5755 +
5756 +       /*
5757 +        * Write firmware to device.
5758 +        */
5759 +       rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
5760 +                                           USB_VENDOR_REQUEST_OUT,
5761 +                                           FIRMWARE_IMAGE_BASE,
5762 +                                           data, len,
5763 +                                           REGISTER_TIMEOUT32(len));
5764 +
5765 +       rt2800usb_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
5766 +       rt2800usb_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
5767 +
5768 +       /*
5769 +        * Send firmware request to device to load firmware,
5770 +        * we need to specify a long timeout time.
5771 +        */
5772 +       status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
5773 +                                            0, USB_MODE_FIRMWARE,
5774 +                                            REGISTER_TIMEOUT_FIRMWARE);
5775 +       if (status < 0) {
5776 +               ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
5777 +               return status;
5778 +       }
5779 +
5780 +       /*
5781 +        * Wait for device to stabilize.
5782 +        */
5783 +       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
5784 +               rt2800usb_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
5785 +               if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
5786 +                       break;
5787 +               msleep(1);
5788 +       }
5789 +
5790 +       if (i == REGISTER_BUSY_COUNT) {
5791 +               ERROR(rt2x00dev, "PBF system register not ready.\n");
5792 +               return -EBUSY;
5793 +       }
5794 +
5795 +       /*
5796 +        * Initialize firmware.
5797 +        */
5798 +       rt2800usb_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
5799 +       rt2800usb_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
5800 +       msleep(1);
5801 +
5802 +       return 0;
5803 +}
5804 +
5805 +/*
5806 + * Initialization functions.
5807 + */
5808 +static int rt2800usb_init_registers(struct rt2x00_dev *rt2x00dev)
5809 +{
5810 +       u32 reg;
5811 +       unsigned int i;
5812 +
5813 +       /*
5814 +        * Wait untill BBP and RF are ready.
5815 +        */
5816 +       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
5817 +               rt2800usb_register_read(rt2x00dev, MAC_CSR0, &reg);
5818 +               if (reg && reg != ~0)
5819 +                       break;
5820 +               msleep(1);
5821 +       }
5822 +
5823 +       if (i == REGISTER_BUSY_COUNT) {
5824 +               ERROR(rt2x00dev, "Unstable hardware.\n");
5825 +               return -EBUSY;
5826 +       }
5827 +
5828 +       rt2800usb_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
5829 +       rt2800usb_register_write(rt2x00dev, PBF_SYS_CTRL, reg & ~0x00002000);
5830 +
5831 +       rt2800usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
5832 +       rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
5833 +       rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
5834 +       rt2800usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
5835 +
5836 +       rt2800usb_register_write(rt2x00dev, USB_DMA_CFG, 0x00000000);
5837 +
5838 +       rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
5839 +                                   USB_MODE_RESET, REGISTER_TIMEOUT);
5840 +
5841 +       rt2800usb_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
5842 +
5843 +       rt2800usb_register_read(rt2x00dev, BCN_OFFSET0, &reg);
5844 +       rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
5845 +       rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
5846 +       rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
5847 +       rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
5848 +       rt2800usb_register_write(rt2x00dev, BCN_OFFSET0, reg);
5849 +
5850 +       rt2800usb_register_read(rt2x00dev, BCN_OFFSET1, &reg);
5851 +       rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
5852 +       rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
5853 +       rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
5854 +       rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
5855 +       rt2800usb_register_write(rt2x00dev, BCN_OFFSET1, reg);
5856 +
5857 +       rt2800usb_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
5858 +       rt2800usb_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
5859 +
5860 +       rt2800usb_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
5861 +
5862 +       rt2800usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
5863 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
5864 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
5865 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
5866 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
5867 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
5868 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
5869 +       rt2800usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
5870 +
5871 +       rt2800usb_register_write(rt2x00dev, TX_SW_CFG0, 0x00040a06);
5872 +       rt2800usb_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5873 +
5874 +       rt2800usb_register_read(rt2x00dev, TX_LINK_CFG, &reg);
5875 +       rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
5876 +       rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
5877 +       rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
5878 +       rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
5879 +       rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
5880 +       rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
5881 +       rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
5882 +       rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
5883 +       rt2800usb_register_write(rt2x00dev, TX_LINK_CFG, reg);
5884 +
5885 +       rt2800usb_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
5886 +       rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
5887 +       rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
5888 +       rt2800usb_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
5889 +
5890 +       rt2800usb_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
5891 +       rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
5892 +       rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
5893 +       rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
5894 +       rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
5895 +       rt2800usb_register_write(rt2x00dev, MAX_LEN_CFG, reg);
5896 +
5897 +       rt2800usb_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
5898 +
5899 +       rt2800usb_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
5900 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
5901 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
5902 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
5903 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
5904 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
5905 +       rt2800usb_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
5906 +
5907 +       rt2800usb_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
5908 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
5909 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
5910 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
5911 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
5912 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5913 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5914 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
5915 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5916 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
5917 +       rt2800usb_register_write(rt2x00dev, CCK_PROT_CFG, reg);
5918 +
5919 +       rt2800usb_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
5920 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
5921 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
5922 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
5923 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
5924 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5925 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5926 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
5927 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5928 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
5929 +       rt2800usb_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
5930 +
5931 +       rt2800usb_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
5932 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
5933 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
5934 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
5935 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
5936 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5937 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5938 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
5939 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5940 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
5941 +       rt2800usb_register_write(rt2x00dev, MM20_PROT_CFG, reg);
5942 +
5943 +       rt2800usb_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
5944 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
5945 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
5946 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
5947 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
5948 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5949 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5950 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
5951 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5952 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
5953 +       rt2800usb_register_write(rt2x00dev, MM40_PROT_CFG, reg);
5954 +
5955 +       rt2800usb_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
5956 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
5957 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
5958 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
5959 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
5960 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5961 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5962 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
5963 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5964 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
5965 +       rt2800usb_register_write(rt2x00dev, GF20_PROT_CFG, reg);
5966 +
5967 +       rt2800usb_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
5968 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
5969 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
5970 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
5971 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
5972 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5973 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5974 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
5975 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5976 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
5977 +       rt2800usb_register_write(rt2x00dev, GF40_PROT_CFG, reg);
5978 +
5979 +       rt2800usb_register_write(rt2x00dev, PBF_CFG, 0xf40006);
5980 +
5981 +       rt2800usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
5982 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
5983 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
5984 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
5985 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
5986 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
5987 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
5988 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
5989 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
5990 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
5991 +       rt2800usb_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
5992 +
5993 +       rt2800usb_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
5994 +       rt2800usb_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
5995 +
5996 +       rt2800usb_register_read(rt2x00dev, TX_RTS_CFG, &reg);
5997 +       rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
5998 +       rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
5999 +       rt2800usb_register_write(rt2x00dev, TX_RTS_CFG, reg);
6000 +
6001 +       rt2800usb_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
6002 +       rt2800usb_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
6003 +
6004 +       /*
6005 +        * ASIC will keep garbage value after boot, clear encryption keys.
6006 +        */
6007 +       for (i = 0; i < 254; i++) {
6008 +               u32 wcid[2] = { 0xffffffff, 0x0000ffff };
6009 +               rt2800usb_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
6010 +                                             wcid, sizeof(wcid));
6011 +       }
6012 +
6013 +       for (i = 0; i < 4; i++)
6014 +               rt2800usb_register_write(rt2x00dev,
6015 +                                        SHARED_KEY_MODE_ENTRY(i), 0);
6016 +
6017 +       for (i = 0; i < 256; i++)
6018 +               rt2800usb_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
6019 +
6020 +       /*
6021 +        * Clear all beacons
6022 +        * For the Beacon base registers we only need to clear
6023 +        * the first byte since that byte contains the VALID and OWNER
6024 +        * bits which (when set to 0) will invalidate the entire beacon.
6025 +        */
6026 +       rt2800usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
6027 +       rt2800usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
6028 +       rt2800usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
6029 +       rt2800usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
6030 +       rt2800usb_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
6031 +       rt2800usb_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
6032 +       rt2800usb_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
6033 +       rt2800usb_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
6034 +
6035 +       rt2800usb_register_read(rt2x00dev, USB_CYC_CFG, &reg);
6036 +       rt2x00_set_field32(&reg, USB_CYC_CFG_CLOCK_CYCLE, 30);
6037 +       rt2800usb_register_write(rt2x00dev, USB_CYC_CFG, reg);
6038 +
6039 +       rt2800usb_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
6040 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
6041 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
6042 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
6043 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
6044 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
6045 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
6046 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
6047 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
6048 +       rt2800usb_register_write(rt2x00dev, HT_FBK_CFG0, reg);
6049 +
6050 +       rt2800usb_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
6051 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
6052 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
6053 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
6054 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
6055 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
6056 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
6057 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
6058 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
6059 +       rt2800usb_register_write(rt2x00dev, HT_FBK_CFG1, reg);
6060 +
6061 +       rt2800usb_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
6062 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
6063 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
6064 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 10);
6065 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 11);
6066 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 12);
6067 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 13);
6068 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 14);
6069 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 15);
6070 +       rt2800usb_register_write(rt2x00dev, LG_FBK_CFG0, reg);
6071 +
6072 +       rt2800usb_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
6073 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
6074 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
6075 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
6076 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
6077 +       rt2800usb_register_write(rt2x00dev, LG_FBK_CFG1, reg);
6078 +
6079 +       /*
6080 +        * We must clear the error counters.
6081 +        * These registers are cleared on read,
6082 +        * so we may pass a useless variable to store the value.
6083 +        */
6084 +       rt2800usb_register_read(rt2x00dev, RX_STA_CNT0, &reg);
6085 +       rt2800usb_register_read(rt2x00dev, RX_STA_CNT1, &reg);
6086 +       rt2800usb_register_read(rt2x00dev, RX_STA_CNT2, &reg);
6087 +       rt2800usb_register_read(rt2x00dev, TX_STA_CNT0, &reg);
6088 +       rt2800usb_register_read(rt2x00dev, TX_STA_CNT1, &reg);
6089 +       rt2800usb_register_read(rt2x00dev, TX_STA_CNT2, &reg);
6090 +
6091 +       return 0;
6092 +}
6093 +
6094 +static int rt2800usb_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
6095 +{
6096 +       unsigned int i;
6097 +       u32 reg;
6098 +
6099 +       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
6100 +               rt2800usb_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
6101 +               if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
6102 +                       return 0;
6103 +
6104 +               udelay(REGISTER_BUSY_DELAY);
6105 +       }
6106 +
6107 +       ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
6108 +       return -EACCES;
6109 +}
6110 +
6111 +static int rt2800usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
6112 +{
6113 +       unsigned int i;
6114 +       u8 value;
6115 +
6116 +       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
6117 +               rt2800usb_bbp_read(rt2x00dev, 0, &value);
6118 +               if ((value != 0xff) && (value != 0x00))
6119 +                       return 0;
6120 +               udelay(REGISTER_BUSY_DELAY);
6121 +       }
6122 +
6123 +       ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
6124 +       return -EACCES;
6125 +}
6126 +
6127 +static int rt2800usb_init_bbp(struct rt2x00_dev *rt2x00dev)
6128 +{
6129 +       unsigned int i;
6130 +       u16 eeprom;
6131 +       u8 reg_id;
6132 +       u8 value;
6133 +
6134 +       if (unlikely(rt2800usb_wait_bbp_rf_ready(rt2x00dev) ||
6135 +                    rt2800usb_wait_bbp_ready(rt2x00dev)))
6136 +               return -EACCES;
6137 +
6138 +       rt2800usb_bbp_write(rt2x00dev, 65, 0x2c);
6139 +       rt2800usb_bbp_write(rt2x00dev, 66, 0x38);
6140 +       rt2800usb_bbp_write(rt2x00dev, 69, 0x12);
6141 +       rt2800usb_bbp_write(rt2x00dev, 70, 0x0a);
6142 +       rt2800usb_bbp_write(rt2x00dev, 73, 0x10);
6143 +       rt2800usb_bbp_write(rt2x00dev, 81, 0x37);
6144 +       rt2800usb_bbp_write(rt2x00dev, 82, 0x62);
6145 +       rt2800usb_bbp_write(rt2x00dev, 83, 0x6a);
6146 +       rt2800usb_bbp_write(rt2x00dev, 84, 0x99);
6147 +       rt2800usb_bbp_write(rt2x00dev, 86, 0x00);
6148 +       rt2800usb_bbp_write(rt2x00dev, 91, 0x04);
6149 +       rt2800usb_bbp_write(rt2x00dev, 92, 0x00);
6150 +       rt2800usb_bbp_write(rt2x00dev, 105, 0x05);
6151 +
6152 +       if (rt2x00_rev(&rt2x00dev->chip) == RT2870_VERSION_C) {
6153 +               rt2800usb_bbp_write(rt2x00dev, 69, 0x16);
6154 +               rt2800usb_bbp_write(rt2x00dev, 73, 0x12);
6155 +       }
6156 +
6157 +       if (rt2x00_rev(&rt2x00dev->chip) != RT2870_VERSION_D)
6158 +               rt2800usb_bbp_write(rt2x00dev, 84, 0x19);
6159 +
6160 +       for (i = 0; i < EEPROM_BBP_SIZE; i++) {
6161 +               rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
6162 +
6163 +               if (eeprom != 0xffff && eeprom != 0x0000) {
6164 +                       reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
6165 +                       value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
6166 +                       rt2800usb_bbp_write(rt2x00dev, reg_id, value);
6167 +               }
6168 +       }
6169 +
6170 +       return 0;
6171 +}
6172 +
6173 +/*
6174 + * Device state switch handlers.
6175 + */
6176 +static void rt2800usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
6177 +                               enum dev_state state)
6178 +{
6179 +       u32 reg;
6180 +
6181 +       rt2800usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
6182 +       rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
6183 +                          (state == STATE_RADIO_RX_ON) ||
6184 +                          (state == STATE_RADIO_RX_ON_LINK));
6185 +       rt2800usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
6186 +}
6187 +
6188 +static int rt2800usb_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
6189 +{
6190 +       unsigned int i;
6191 +       u32 reg;
6192 +
6193 +       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
6194 +               rt2800usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
6195 +               if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
6196 +                   !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
6197 +                       return 0;
6198 +
6199 +               msleep(1);
6200 +       }
6201 +
6202 +       ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
6203 +       return -EACCES;
6204 +}
6205 +
6206 +static int rt2800usb_enable_radio(struct rt2x00_dev *rt2x00dev)
6207 +{
6208 +       u32 reg;
6209 +       u16 word;
6210 +
6211 +       /*
6212 +        * Initialize all registers.
6213 +        */
6214 +       if (unlikely(rt2800usb_wait_wpdma_ready(rt2x00dev) ||
6215 +                    rt2800usb_init_registers(rt2x00dev) ||
6216 +                    rt2800usb_init_bbp(rt2x00dev)))
6217 +               return -EIO;
6218 +
6219 +       rt2800usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
6220 +       rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
6221 +       rt2800usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
6222 +
6223 +       udelay(50);
6224 +
6225 +       rt2800usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
6226 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
6227 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
6228 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
6229 +       rt2800usb_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
6230 +
6231 +
6232 +       rt2800usb_register_read(rt2x00dev, USB_DMA_CFG, &reg);
6233 +       rt2x00_set_field32(&reg, USB_DMA_CFG_PHY_CLEAR, 0);
6234 +       /* Don't use bulk in aggregation when working with USB 1.1 */
6235 +       rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_EN,
6236 +                          (rt2x00dev->usb_maxpacket == 512));
6237 +       rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_TIMEOUT, 128);
6238 +       /* FIXME: Calculate this value based on Aggregation defines */
6239 +       rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_LIMIT, 21);
6240 +       rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_EN, 1);
6241 +       rt2x00_set_field32(&reg, USB_DMA_CFG_TX_BULK_EN, 1);
6242 +       rt2800usb_register_write(rt2x00dev, USB_DMA_CFG, reg);
6243 +
6244 +       rt2800usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
6245 +       rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
6246 +       rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
6247 +       rt2800usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
6248 +
6249 +       /*
6250 +        * Initialize LED control
6251 +        */
6252 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
6253 +       rt2800usb_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
6254 +                             word & 0xff, (word >> 8) & 0xff);
6255 +
6256 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
6257 +       rt2800usb_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
6258 +                             word & 0xff, (word >> 8) & 0xff);
6259 +
6260 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
6261 +       rt2800usb_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
6262 +                             word & 0xff, (word >> 8) & 0xff);
6263 +
6264 +       /*
6265 +        * Send signal to firmware during boot time.
6266 +        */
6267 +       rt2800usb_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0);
6268 +
6269 +       return 0;
6270 +}
6271 +
6272 +static void rt2800usb_disable_radio(struct rt2x00_dev *rt2x00dev)
6273 +{
6274 +       u32 reg;
6275 +
6276 +       rt2800usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
6277 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
6278 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
6279 +       rt2800usb_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
6280 +
6281 +       rt2800usb_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
6282 +       rt2800usb_register_write(rt2x00dev, PWR_PIN_CFG, 0);
6283 +       rt2800usb_register_write(rt2x00dev, TX_PIN_CFG, 0);
6284 +
6285 +       /* Wait for DMA, ignore error */
6286 +       rt2800usb_wait_wpdma_ready(rt2x00dev);
6287 +
6288 +       rt2x00usb_disable_radio(rt2x00dev);
6289 +}
6290 +
6291 +static int rt2800usb_set_state(struct rt2x00_dev *rt2x00dev,
6292 +                              enum dev_state state)
6293 +{
6294 +       rt2800usb_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
6295 +
6296 +       if (state == STATE_AWAKE)
6297 +               rt2800usb_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
6298 +       else
6299 +               rt2800usb_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
6300 +
6301 +       return 0;
6302 +}
6303 +
6304 +static int rt2800usb_set_device_state(struct rt2x00_dev *rt2x00dev,
6305 +                                     enum dev_state state)
6306 +{
6307 +       int retval = 0;
6308 +
6309 +       switch (state) {
6310 +       case STATE_RADIO_ON:
6311 +               /*
6312 +                * Before the radio can be enabled, the device first has
6313 +                * to be woken up. After that it needs a bit of time
6314 +                * to be fully awake and the radio can be enabled.
6315 +                */
6316 +               rt2800usb_set_state(rt2x00dev, STATE_AWAKE);
6317 +               msleep(1);
6318 +               retval = rt2800usb_enable_radio(rt2x00dev);
6319 +               break;
6320 +       case STATE_RADIO_OFF:
6321 +               /*
6322 +                * After the radio has been disablee, the device should
6323 +                * be put to sleep for powersaving.
6324 +                */
6325 +               rt2800usb_disable_radio(rt2x00dev);
6326 +               rt2800usb_set_state(rt2x00dev, STATE_SLEEP);
6327 +               break;
6328 +       case STATE_RADIO_RX_ON:
6329 +       case STATE_RADIO_RX_ON_LINK:
6330 +       case STATE_RADIO_RX_OFF:
6331 +       case STATE_RADIO_RX_OFF_LINK:
6332 +               rt2800usb_toggle_rx(rt2x00dev, state);
6333 +               break;
6334 +       case STATE_RADIO_IRQ_ON:
6335 +       case STATE_RADIO_IRQ_OFF:
6336 +               /* No support, but no error either */
6337 +               break;
6338 +       case STATE_DEEP_SLEEP:
6339 +       case STATE_SLEEP:
6340 +       case STATE_STANDBY:
6341 +       case STATE_AWAKE:
6342 +               retval = rt2800usb_set_state(rt2x00dev, state);
6343 +               break;
6344 +       default:
6345 +               retval = -ENOTSUPP;
6346 +               break;
6347 +       }
6348 +
6349 +       if (unlikely(retval))
6350 +               ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
6351 +                     state, retval);
6352 +
6353 +       return retval;
6354 +}
6355 +
6356 +/*
6357 + * TX descriptor initialization
6358 + */
6359 +static void rt2800usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
6360 +                                   struct sk_buff *skb,
6361 +                                   struct txentry_desc *txdesc)
6362 +{
6363 +       struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
6364 +       __le32 *txd = skbdesc->desc;
6365 +       __le32 *txwi = txd + TXD_DESC_SIZE;
6366 +       u32 word;
6367 +
6368 +       /*
6369 +        * Initialize TX Info descriptor
6370 +        */
6371 +       rt2x00_desc_read(txwi, 0, &word);
6372 +       rt2x00_set_field32(&word, TXWI_W0_FRAG,
6373 +                          test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags) ||
6374 +                          test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
6375 +       rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
6376 +       rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
6377 +       rt2x00_set_field32(&word, TXWI_W0_TS,
6378 +                          test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
6379 +       rt2x00_set_field32(&word, TXWI_W0_AMPDU,
6380 +                          test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
6381 +       rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
6382 +       rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->ifs);
6383 +       rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
6384 +       rt2x00_set_field32(&word, TXWI_W0_BW,
6385 +                          test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
6386 +       rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
6387 +                          test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
6388 +       rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
6389 +       rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
6390 +       rt2x00_desc_write(txwi, 0, word);
6391 +
6392 +       rt2x00_desc_read(txwi, 1, &word);
6393 +       rt2x00_set_field32(&word, TXWI_W1_ACK,
6394 +                          test_bit(ENTRY_TXD_ACK, &txdesc->flags));
6395 +       rt2x00_set_field32(&word, TXWI_W1_ACK,
6396 +                          test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags));
6397 +       rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
6398 +       rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID, 0xff);
6399 +       rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT, skb->len);
6400 +       rt2x00_set_field32(&word, TXWI_W1_PACKETID,
6401 +                          skbdesc->entry->entry_idx);
6402 +       rt2x00_desc_write(txwi, 1, word);
6403 +
6404 +       if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
6405 +               _rt2x00_desc_write(txwi, 2, skbdesc->iv);
6406 +               _rt2x00_desc_write(txwi, 3, skbdesc->eiv);
6407 +       }
6408 +
6409 +       /*
6410 +        * Initialize TX descriptor
6411 +        */
6412 +       rt2x00_desc_read(txd, 0, &word);
6413 +       rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
6414 +       rt2x00_desc_write(txd, 0, word);
6415 +
6416 +       rt2x00_desc_read(txd, 1, &word);
6417 +       rt2x00_set_field32(&word, TXD_W1_SD_LEN1, skb->len);
6418 +       rt2x00_set_field32(&word, TXD_W1_LAST_SEC1, 1);
6419 +       rt2x00_set_field32(&word, TXD_W1_BURST,
6420 +                          test_bit(ENTRY_TXD_BURST, &txdesc->flags));
6421 +       rt2x00_set_field32(&word, TXD_W1_SD_LEN0,
6422 +                          rt2x00dev->hw->extra_tx_headroom);
6423 +       rt2x00_set_field32(&word, TXD_W1_LAST_SEC0,
6424 +                          !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
6425 +       rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
6426 +       rt2x00_desc_write(txd, 1, word);
6427 +
6428 +       rt2x00_desc_read(txd, 2, &word);
6429 +       rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
6430 +                          skbdesc->skb_dma + rt2x00dev->hw->extra_tx_headroom);
6431 +       rt2x00_desc_write(txd, 2, word);
6432 +
6433 +       rt2x00_desc_read(txd, 3, &word);
6434 +       rt2x00_set_field32(&word, TXD_W3_WIV, 1);
6435 +       rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
6436 +       rt2x00_desc_write(txd, 3, word);
6437 +}
6438 +
6439 +/*
6440 + * TX data initialization
6441 + */
6442 +static void rt2800usb_write_beacon(struct queue_entry *entry)
6443 +{
6444 +       struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
6445 +       struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
6446 +       unsigned int beacon_base;
6447 +       u32 reg;
6448 +
6449 +       /*
6450 +        * Add the descriptor in front of the skb.
6451 +        */
6452 +       skb_push(entry->skb, entry->queue->desc_size);
6453 +       memcpy(entry->skb->data, skbdesc->desc, skbdesc->desc_len);
6454 +       skbdesc->desc = entry->skb->data;
6455 +
6456 +       /*
6457 +        * Disable beaconing while we are reloading the beacon data,
6458 +        * otherwise we might be sending out invalid data.
6459 +        */
6460 +       rt2800usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
6461 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
6462 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
6463 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
6464 +       rt2800usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
6465 +
6466 +       /*
6467 +        * Write entire beacon with descriptor to register.
6468 +        */
6469 +       beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
6470 +       rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
6471 +                                           USB_VENDOR_REQUEST_OUT, beacon_base,
6472 +                                           entry->skb->data, entry->skb->len,
6473 +                                           REGISTER_TIMEOUT32(entry->skb->len));
6474 +
6475 +       /*
6476 +        * Clean up the beacon skb.
6477 +        */
6478 +       dev_kfree_skb(entry->skb);
6479 +       entry->skb = NULL;
6480 +}
6481 +
6482 +static int rt2800usb_get_tx_data_len(struct rt2x00_dev *rt2x00dev,
6483 +                                    struct sk_buff *skb)
6484 +{
6485 +       int length;
6486 +
6487 +       /*
6488 +        * The length _must_ be a multiple of 4,
6489 +        * but it must _not_ be a multiple of the USB packet size.
6490 +        */
6491 +       length = roundup(skb->len, 4);
6492 +       length += (4 * !(length % rt2x00dev->usb_maxpacket));
6493 +
6494 +       return length;
6495 +}
6496 +
6497 +static void rt2800usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
6498 +                                   const enum data_queue_qid queue)
6499 +{
6500 +       u32 reg;
6501 +
6502 +       if (queue != QID_BEACON) {
6503 +               rt2x00usb_kick_tx_queue(rt2x00dev, queue);
6504 +               return;
6505 +       }
6506 +
6507 +       rt2800usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
6508 +       if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
6509 +               rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
6510 +               rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
6511 +               rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
6512 +               rt2800usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
6513 +       }
6514 +}
6515 +
6516 +/*
6517 + * RX control handlers
6518 + */
6519 +static void rt2800usb_fill_rxdone(struct queue_entry *entry,
6520 +                                 struct rxdone_entry_desc *rxdesc)
6521 +{
6522 +       struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
6523 +       struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
6524 +       __le32 *rxd = (__le32 *)entry->skb->data;
6525 +       __le32 *rxwi = (__le32 *)(entry->skb->data + skbdesc->desc_len);
6526 +       u32 rxd0;
6527 +       u32 rxwi0;
6528 +       u32 rxwi1;
6529 +       u32 rxwi2;
6530 +       u32 rxwi3;
6531 +       u8 mcs;
6532 +       u8 mode;
6533 +
6534 +       /*
6535 +        * Copy descriptor to the skbdesc->desc buffer, making it safe from
6536 +        * moving of frame data in rt2x00usb.
6537 +        */
6538 +       memcpy(skbdesc->desc, rxd, skbdesc->desc_len);
6539 +       rxd = (__le32 *)skbdesc->desc;
6540 +
6541 +       /*
6542 +        * It is now safe to read the descriptor on all architectures.
6543 +        */
6544 +       rt2x00_desc_read(rxd, 0, &rxd0);
6545 +       rt2x00_desc_read(rxwi, 0, &rxwi0);
6546 +       rt2x00_desc_read(rxwi, 1, &rxwi1);
6547 +       rt2x00_desc_read(rxwi, 2, &rxwi2);
6548 +       rt2x00_desc_read(rxwi, 3, &rxwi3);
6549 +
6550 +       if (rt2x00_get_field32(rxd0, RXD_W0_CRC_ERROR))
6551 +               rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
6552 +
6553 +       if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
6554 +               /*
6555 +                * FIXME: Set cipher on WEP64 when it has been decrypted,
6556 +                * at the moment we cannot determine the real cipher type yet.
6557 +                */
6558 +               rxdesc->cipher =
6559 +                   rt2x00_get_field32(rxd0, RXD_W0_DECRYPTED);
6560 +               rxdesc->cipher_status =
6561 +                   rt2x00_get_field32(rxd0, RXD_W0_CIPHER_ERROR);
6562 +       }
6563 +
6564 +       if (rxdesc->cipher != CIPHER_NONE) {
6565 +               /*
6566 +                * Hardware has stripped IV/EIV data from 802.11 frame during
6567 +                * decryption. It has provided the data seperately but rt2x00lib
6568 +                * should decide if it should be reinserted.
6569 +                */
6570 +               rxdesc->flags |= RX_FLAG_IV_STRIPPED;
6571 +
6572 +               if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
6573 +                       rxdesc->flags |= RX_FLAG_DECRYPTED;
6574 +               else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
6575 +                       rxdesc->flags |= RX_FLAG_MMIC_ERROR;
6576 +       }
6577 +
6578 +       if (rt2x00_get_field32(rxd0, RXD_W0_MY_BSS))
6579 +               rxdesc->dev_flags |= RXDONE_MY_BSS;
6580 +
6581 +       /*
6582 +        * Create the MCS value, when the mode is CCK, mask of 0x8 bit
6583 +        * to remove the short preamble flag.
6584 +        */
6585 +       mode = rt2x00_get_field32(rxwi1, RXWI_W1_PHYMODE);
6586 +       mcs = rt2x00_get_field32(rxwi1, RXWI_W1_MCS);
6587 +
6588 +       if (mode == RATE_MODE_CCK)
6589 +               mcs &= ~0x8;
6590 +
6591 +       rxdesc->signal = (mode << 8) | mcs;
6592 +
6593 +       rxdesc->rssi =
6594 +           (rt2x00_get_field32(rxwi2, RXWI_W2_RSSI0) +
6595 +            rt2x00_get_field32(rxwi2, RXWI_W2_RSSI1) +
6596 +            rt2x00_get_field32(rxwi2, RXWI_W2_RSSI2)) / 3;
6597 +
6598 +       rxdesc->noise =
6599 +           (rt2x00_get_field32(rxwi3, RXWI_W3_SNR0) +
6600 +            rt2x00_get_field32(rxwi3, RXWI_W3_SNR1)) / 2;
6601 +
6602 +       rxdesc->size = rt2x00_get_field32(rxwi0, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
6603 +
6604 +       /*
6605 +        * Remove TXWI descriptor from start of buffer.
6606 +        */
6607 +       skb_pull(entry->skb, TXWI_DESC_SIZE + skbdesc->desc_len);
6608 +       skb_trim(entry->skb, rxdesc->size);
6609 +}
6610 +
6611 +/*
6612 + * Device probe functions.
6613 + */
6614 +static int rt2800usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
6615 +{
6616 +       u16 word;
6617 +       u8 *mac;
6618 +       u8 default_lna_gain;
6619 +
6620 +       rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
6621 +
6622 +       /*
6623 +        * Start validation of the data that has been read.
6624 +        */
6625 +       mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
6626 +       if (!is_valid_ether_addr(mac)) {
6627 +               DECLARE_MAC_BUF(macbuf);
6628 +
6629 +               random_ether_addr(mac);
6630 +               EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
6631 +       }
6632 +
6633 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
6634 +       if (word == 0xffff) {
6635 +               rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
6636 +               rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
6637 +               rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
6638 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
6639 +               EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
6640 +       }
6641 +
6642 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
6643 +       if (word != 0) {
6644 +               /* NIC configuration must always be 0. */
6645 +               word = 0;
6646 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
6647 +               EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
6648 +       }
6649 +
6650 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
6651 +       if ((word & 0x00ff) == 0x00ff) {
6652 +               rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
6653 +               rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
6654 +                                  LED_MODE_TXRX_ACTIVITY);
6655 +               rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
6656 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
6657 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
6658 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
6659 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
6660 +               EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
6661 +       }
6662 +
6663 +       /*
6664 +        * During the LNA validation we are going to use
6665 +        * lna0 as correct value. Note that EEPROM_LNA
6666 +        * is never validated.
6667 +        */
6668 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
6669 +       default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
6670 +
6671 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
6672 +       if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
6673 +               rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
6674 +       if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
6675 +               rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
6676 +       rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
6677 +
6678 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
6679 +       if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
6680 +               rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
6681 +       if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
6682 +           rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
6683 +               rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
6684 +                                  default_lna_gain);
6685 +       rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
6686 +
6687 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
6688 +       if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
6689 +               rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
6690 +       if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
6691 +               rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
6692 +       rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
6693 +
6694 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
6695 +       if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
6696 +               rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
6697 +       if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
6698 +           rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
6699 +               rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
6700 +                                  default_lna_gain);
6701 +       rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
6702 +
6703 +       return 0;
6704 +}
6705 +
6706 +static int rt2800usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
6707 +{
6708 +       u32 reg;
6709 +       u16 rev;
6710 +       u16 value;
6711 +       u16 eeprom;
6712 +
6713 +       /*
6714 +        * Read EEPROM word for configuration.
6715 +        */
6716 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
6717 +
6718 +       /*
6719 +        * Identify RF chipset.
6720 +        */
6721 +       value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
6722 +       rt2800usb_register_read(rt2x00dev, MAC_CSR0, &reg);
6723 +       rev = rt2x00_get_field32(reg, MAC_CSR0_ASIC_REV);
6724 +       rt2x00_set_chip(rt2x00dev, RT2870, value, rev);
6725 +
6726 +       /*
6727 +        * The check for rt2860 is not a typo, some rt2870 hardware
6728 +        * identifies itself as rt2860 in the CSR register.
6729 +        */
6730 +       if ((rt2x00_get_field32(reg, MAC_CSR0_ASIC_VER) != 0x2860) &&
6731 +           (rt2x00_get_field32(reg, MAC_CSR0_ASIC_VER) != 0x2870)) {
6732 +               ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
6733 +               return -ENODEV;
6734 +       }
6735 +
6736 +       if (!rt2x00_rf(&rt2x00dev->chip, RF2820) &&
6737 +           !rt2x00_rf(&rt2x00dev->chip, RF2850) &&
6738 +           !rt2x00_rf(&rt2x00dev->chip, RF2720) &&
6739 +           !rt2x00_rf(&rt2x00dev->chip, RF2750)) {
6740 +               ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
6741 +               return -ENODEV;
6742 +       }
6743 +
6744 +       /*
6745 +        * Read frequency offset and RF programming sequence.
6746 +        */
6747 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
6748 +       rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
6749 +
6750 +       /*
6751 +        * Read external LNA informations.
6752 +        */
6753 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
6754 +
6755 +       if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
6756 +               __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
6757 +       if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
6758 +               __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
6759 +
6760 +       /*
6761 +        * Store led settings, for correct led behaviour.
6762 +        */
6763 +#ifdef CONFIG_RT2X00_LIB_LEDS
6764 +       rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
6765 +       rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
6766 +       rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
6767 +
6768 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ,
6769 +                          &rt2x00dev->led_mcu_reg);
6770 +#endif /* CONFIG_RT2X00_LIB_LEDS */
6771 +
6772 +       return 0;
6773 +}
6774 +
6775 +/*
6776 + * RF value list for rt2870
6777 + * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
6778 + */
6779 +static const struct rf_channel rf_vals[] = {
6780 +       { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
6781 +       { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
6782 +       { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
6783 +       { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
6784 +       { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
6785 +       { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
6786 +       { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
6787 +       { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
6788 +       { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
6789 +       { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
6790 +       { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
6791 +       { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
6792 +       { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
6793 +       { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
6794 +
6795 +       /* 802.11 UNI / HyperLan 2 */
6796 +       { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
6797 +       { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
6798 +       { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
6799 +       { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
6800 +       { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
6801 +       { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
6802 +       { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
6803 +       { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
6804 +       { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
6805 +       { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
6806 +       { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
6807 +       { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
6808 +
6809 +       /* 802.11 HyperLan 2 */
6810 +       { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
6811 +       { 102, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed793 },
6812 +       { 104, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed1a3 },
6813 +       { 108, 0x18402ecc, 0x184c0a32, 0x18178a55, 0x180ed193 },
6814 +       { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
6815 +       { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
6816 +       { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
6817 +       { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
6818 +       { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
6819 +       { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
6820 +       { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
6821 +       { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
6822 +       { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
6823 +       { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
6824 +       { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
6825 +       { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
6826 +
6827 +       /* 802.11 UNII */
6828 +       { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
6829 +       { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
6830 +       { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
6831 +       { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
6832 +       { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
6833 +       { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
6834 +       { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
6835 +
6836 +       /* 802.11 Japan */
6837 +       { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
6838 +       { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
6839 +       { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
6840 +       { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
6841 +       { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
6842 +       { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
6843 +       { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
6844 +};
6845 +
6846 +static int rt2800usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
6847 +{
6848 +       struct hw_mode_spec *spec = &rt2x00dev->spec;
6849 +       struct channel_info *info;
6850 +       char *tx_power1;
6851 +       char *tx_power2;
6852 +       unsigned int i;
6853 +
6854 +       /*
6855 +        * Initialize all hw fields.
6856 +        */
6857 +       rt2x00dev->hw->flags =
6858 +           IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
6859 +           IEEE80211_HW_SIGNAL_DBM;
6860 +       rt2x00dev->hw->extra_tx_headroom = TXD_DESC_SIZE + TXINFO_DESC_SIZE;
6861 +
6862 +       SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
6863 +       SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
6864 +                               rt2x00_eeprom_addr(rt2x00dev,
6865 +                                                  EEPROM_MAC_ADDR_0));
6866 +
6867 +       /*
6868 +        * Initialize hw_mode information.
6869 +        */
6870 +       spec->supported_bands = SUPPORT_BAND_2GHZ;
6871 +       spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
6872 +
6873 +       if (rt2x00_rf(&rt2x00dev->chip, RF2820) ||
6874 +           rt2x00_rf(&rt2x00dev->chip, RF2720)) {
6875 +               spec->num_channels = 14;
6876 +               spec->channels = rf_vals;
6877 +       } else if (rt2x00_rf(&rt2x00dev->chip, RF2850) ||
6878 +                  rt2x00_rf(&rt2x00dev->chip, RF2750)) {
6879 +               spec->supported_bands |= SUPPORT_BAND_5GHZ;
6880 +               spec->num_channels = ARRAY_SIZE(rf_vals);
6881 +               spec->channels = rf_vals;
6882 +       }
6883 +
6884 +       /*
6885 +        * Create channel information array
6886 +        */
6887 +       info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
6888 +       if (!info)
6889 +               return -ENOMEM;
6890 +
6891 +       spec->channels_info = info;
6892 +
6893 +       tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
6894 +       tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
6895 +
6896 +       for (i = 0; i < 14; i++) {
6897 +               info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
6898 +               info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
6899 +       }
6900 +
6901 +       if (spec->num_channels > 14) {
6902 +               tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
6903 +               tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
6904 +
6905 +               for (i = 14; i < spec->num_channels; i++) {
6906 +                       info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
6907 +                       info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
6908 +               }
6909 +       }
6910 +
6911 +       return 0;
6912 +}
6913 +
6914 +static int rt2800usb_probe_hw(struct rt2x00_dev *rt2x00dev)
6915 +{
6916 +       int retval;
6917 +
6918 +       /*
6919 +        * Allocate eeprom data.
6920 +        */
6921 +       retval = rt2800usb_validate_eeprom(rt2x00dev);
6922 +       if (retval)
6923 +               return retval;
6924 +
6925 +       retval = rt2800usb_init_eeprom(rt2x00dev);
6926 +       if (retval)
6927 +               return retval;
6928 +
6929 +       /*
6930 +        * Initialize hw specifications.
6931 +        */
6932 +       retval = rt2800usb_probe_hw_mode(rt2x00dev);
6933 +       if (retval)
6934 +               return retval;
6935 +
6936 +       /*
6937 +        * This device requires firmware.
6938 +        */
6939 +       __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
6940 +       __set_bit(DRIVER_REQUIRE_SCHEDULED, &rt2x00dev->flags);
6941 +       if (!modparam_nohwcrypt)
6942 +               __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
6943 +
6944 +       /*
6945 +        * Set the rssi offset.
6946 +        */
6947 +       rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
6948 +
6949 +       return 0;
6950 +}
6951 +
6952 +/*
6953 + * IEEE80211 stack callback functions.
6954 + */
6955 +static int rt2800usb_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
6956 +{
6957 +       struct rt2x00_dev *rt2x00dev = hw->priv;
6958 +       u32 reg;
6959 +
6960 +       rt2800usb_register_read(rt2x00dev, TX_RTS_CFG, &reg);
6961 +       rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
6962 +       rt2800usb_register_write(rt2x00dev, TX_RTS_CFG, reg);
6963 +
6964 +       rt2800usb_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
6965 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
6966 +       rt2800usb_register_write(rt2x00dev, CCK_PROT_CFG, reg);
6967 +
6968 +       rt2800usb_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
6969 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
6970 +       rt2800usb_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
6971 +
6972 +       rt2800usb_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
6973 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 1);
6974 +       rt2800usb_register_write(rt2x00dev, MM20_PROT_CFG, reg);
6975 +
6976 +       rt2800usb_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
6977 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 1);
6978 +       rt2800usb_register_write(rt2x00dev, MM40_PROT_CFG, reg);
6979 +
6980 +       rt2800usb_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
6981 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 1);
6982 +       rt2800usb_register_write(rt2x00dev, GF20_PROT_CFG, reg);
6983 +
6984 +       rt2800usb_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
6985 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 1);
6986 +       rt2800usb_register_write(rt2x00dev, GF40_PROT_CFG, reg);
6987 +
6988 +       return 0;
6989 +}
6990 +
6991 +static int rt2800usb_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
6992 +                            const struct ieee80211_tx_queue_params *params)
6993 +{
6994 +       struct rt2x00_dev *rt2x00dev = hw->priv;
6995 +       struct data_queue *queue;
6996 +       struct rt2x00_field32 field;
6997 +       int retval;
6998 +       u32 reg;
6999 +       u32 offset;
7000 +
7001 +       /*
7002 +        * First pass the configuration through rt2x00lib, that will
7003 +        * update the queue settings and validate the input. After that
7004 +        * we are free to update the registers based on the value
7005 +        * in the queue parameter.
7006 +        */
7007 +       retval = rt2x00mac_conf_tx(hw, queue_idx, params);
7008 +       if (retval)
7009 +               return retval;
7010 +
7011 +       queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
7012 +
7013 +       /* Update WMM TXOP register */
7014 +       if (queue_idx < 2) {
7015 +               field.bit_offset = queue_idx * 16;
7016 +               field.bit_mask = 0xffff << field.bit_offset;
7017 +
7018 +               rt2800usb_register_read(rt2x00dev, WMM_TXOP0_CFG, &reg);
7019 +               rt2x00_set_field32(&reg, field, queue->txop);
7020 +               rt2800usb_register_write(rt2x00dev, WMM_TXOP0_CFG, reg);
7021 +       } else if (queue_idx < 4) {
7022 +               field.bit_offset = (queue_idx - 2) * 16;
7023 +               field.bit_mask = 0xffff << field.bit_offset;
7024 +
7025 +               rt2800usb_register_read(rt2x00dev, WMM_TXOP1_CFG, &reg);
7026 +               rt2x00_set_field32(&reg, field, queue->txop);
7027 +               rt2800usb_register_write(rt2x00dev, WMM_TXOP1_CFG, reg);
7028 +       }
7029 +
7030 +       /* Update WMM registers */
7031 +       field.bit_offset = queue_idx * 4;
7032 +       field.bit_mask = 0xf << field.bit_offset;
7033 +
7034 +       rt2800usb_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
7035 +       rt2x00_set_field32(&reg, field, queue->aifs);
7036 +       rt2800usb_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
7037 +
7038 +       rt2800usb_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
7039 +       rt2x00_set_field32(&reg, field, queue->cw_min);
7040 +       rt2800usb_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
7041 +
7042 +       rt2800usb_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
7043 +       rt2x00_set_field32(&reg, field, queue->cw_max);
7044 +       rt2800usb_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
7045 +
7046 +       /* Update EDCA registers */
7047 +       if (queue_idx < 4) {
7048 +               offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
7049 +
7050 +               rt2800usb_register_read(rt2x00dev, offset, &reg);
7051 +               rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
7052 +               rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
7053 +               rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
7054 +               rt2800usb_register_write(rt2x00dev, offset, reg);
7055 +       }
7056 +
7057 +       return 0;
7058 +}
7059 +
7060 +#if 0
7061 +/*
7062 + * Mac80211 demands get_tsf must be atomic.
7063 + * This is not possible for rt2800usb since all register access
7064 + * functions require sleeping. Untill mac80211 no longer needs
7065 + * get_tsf to be atomic, this function should be disabled.
7066 + */
7067 +static u64 rt2800usb_get_tsf(struct ieee80211_hw *hw)
7068 +{
7069 +       struct rt2x00_dev *rt2x00dev = hw->priv;
7070 +       u64 tsf;
7071 +       u32 reg;
7072 +
7073 +       rt2800usb_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
7074 +       tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
7075 +       rt2800usb_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
7076 +       tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
7077 +
7078 +       return tsf;
7079 +}
7080 +#else
7081 +#define rt2800usb_get_tsf      NULL
7082 +#endif
7083 +
7084 +static const struct ieee80211_ops rt2800usb_mac80211_ops = {
7085 +       .tx                     = rt2x00mac_tx,
7086 +       .start                  = rt2x00mac_start,
7087 +       .stop                   = rt2x00mac_stop,
7088 +       .add_interface          = rt2x00mac_add_interface,
7089 +       .remove_interface       = rt2x00mac_remove_interface,
7090 +       .config                 = rt2x00mac_config,
7091 +       .config_interface       = rt2x00mac_config_interface,
7092 +       .configure_filter       = rt2x00mac_configure_filter,
7093 +       .set_key                = rt2x00mac_set_key,
7094 +       .get_stats              = rt2x00mac_get_stats,
7095 +       .set_rts_threshold      = rt2800usb_set_rts_threshold,
7096 +       .bss_info_changed       = rt2x00mac_bss_info_changed,
7097 +       .conf_tx                = rt2800usb_conf_tx,
7098 +       .get_tx_stats           = rt2x00mac_get_tx_stats,
7099 +       .get_tsf                = rt2800usb_get_tsf,
7100 +};
7101 +
7102 +static const struct rt2x00lib_ops rt2800usb_rt2x00_ops = {
7103 +       .probe_hw               = rt2800usb_probe_hw,
7104 +       .get_firmware_name      = rt2800usb_get_firmware_name,
7105 +       .get_firmware_crc       = rt2800usb_get_firmware_crc,
7106 +       .load_firmware          = rt2800usb_load_firmware,
7107 +       .initialize             = rt2x00usb_initialize,
7108 +       .uninitialize           = rt2x00usb_uninitialize,
7109 +       .init_rxentry           = rt2x00usb_init_rxentry,
7110 +       .init_txentry           = rt2x00usb_init_txentry,
7111 +       .set_device_state       = rt2800usb_set_device_state,
7112 +       .link_stats             = rt2800usb_link_stats,
7113 +       .reset_tuner            = rt2800usb_reset_tuner,
7114 +       .link_tuner             = rt2800usb_link_tuner,
7115 +       .write_tx_desc          = rt2800usb_write_tx_desc,
7116 +       .write_tx_data          = rt2x00usb_write_tx_data,
7117 +       .write_beacon           = rt2800usb_write_beacon,
7118 +       .get_tx_data_len        = rt2800usb_get_tx_data_len,
7119 +       .kick_tx_queue          = rt2800usb_kick_tx_queue,
7120 +       .fill_rxdone            = rt2800usb_fill_rxdone,
7121 +       .config_shared_key      = rt2800usb_config_shared_key,
7122 +       .config_pairwise_key    = rt2800usb_config_pairwise_key,
7123 +       .config_filter          = rt2800usb_config_filter,
7124 +       .config_intf            = rt2800usb_config_intf,
7125 +       .config_erp             = rt2800usb_config_erp,
7126 +       .config_ant             = rt2800usb_config_ant,
7127 +       .config                 = rt2800usb_config,
7128 +};
7129 +
7130 +static const struct data_queue_desc rt2800usb_queue_rx = {
7131 +       .entry_num              = RX_ENTRIES,
7132 +       .data_size              = DATA_FRAME_SIZE,
7133 +       .desc_size              = RXD_DESC_SIZE,
7134 +       .priv_size              = sizeof(struct queue_entry_priv_usb),
7135 +};
7136 +
7137 +static const struct data_queue_desc rt2800usb_queue_tx = {
7138 +       .entry_num              = TX_ENTRIES,
7139 +       .data_size              = DATA_FRAME_SIZE,
7140 +       .desc_size              = TXD_DESC_SIZE,
7141 +       .priv_size              = sizeof(struct queue_entry_priv_usb),
7142 +};
7143 +
7144 +static const struct data_queue_desc rt2800usb_queue_bcn = {
7145 +       .entry_num              = 8 * BEACON_ENTRIES,
7146 +       .data_size              = MGMT_FRAME_SIZE,
7147 +       .desc_size              = TXWI_DESC_SIZE,
7148 +       .priv_size              = sizeof(struct queue_entry_priv_usb),
7149 +};
7150 +
7151 +static const struct rt2x00_ops rt2800usb_ops = {
7152 +       .name           = KBUILD_MODNAME,
7153 +       .max_sta_intf   = 1,
7154 +       .max_ap_intf    = 8,
7155 +       .eeprom_size    = EEPROM_SIZE,
7156 +       .rf_size        = RF_SIZE,
7157 +       .tx_queues      = NUM_TX_QUEUES,
7158 +       .rx             = &rt2800usb_queue_rx,
7159 +       .tx             = &rt2800usb_queue_tx,
7160 +       .bcn            = &rt2800usb_queue_bcn,
7161 +       .lib            = &rt2800usb_rt2x00_ops,
7162 +       .hw             = &rt2800usb_mac80211_ops,
7163 +#ifdef CONFIG_RT2X00_LIB_DEBUGFS
7164 +       .debugfs        = &rt2800usb_rt2x00debug,
7165 +#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
7166 +};
7167 +
7168 +/*
7169 + * rt2800usb module information.
7170 + */
7171 +static struct usb_device_id rt2800usb_device_table[] = {
7172 +       /* Amit */
7173 +       { USB_DEVICE(0x15c5, 0x0008), USB_DEVICE_DATA(&rt2800usb_ops) },
7174 +       /* ASUS */
7175 +       { USB_DEVICE(0x0b05, 0x1731), USB_DEVICE_DATA(&rt2800usb_ops) },
7176 +       { USB_DEVICE(0x0b05, 0x1732), USB_DEVICE_DATA(&rt2800usb_ops) },
7177 +       { USB_DEVICE(0x0b05, 0x1742), USB_DEVICE_DATA(&rt2800usb_ops) },
7178 +       /* AzureWave */
7179 +       { USB_DEVICE(0x13d3, 0x3247), USB_DEVICE_DATA(&rt2800usb_ops) },
7180 +       /* Belkin */
7181 +       { USB_DEVICE(0x050d, 0x8053), USB_DEVICE_DATA(&rt2800usb_ops) },
7182 +       /* Conceptronic */
7183 +       { USB_DEVICE(0x14b2, 0x3c06), USB_DEVICE_DATA(&rt2800usb_ops) },
7184 +       { USB_DEVICE(0x14b2, 0x3c07), USB_DEVICE_DATA(&rt2800usb_ops) },
7185 +       { USB_DEVICE(0x14b2, 0x3c23), USB_DEVICE_DATA(&rt2800usb_ops) },
7186 +       { USB_DEVICE(0x14b2, 0x3c25), USB_DEVICE_DATA(&rt2800usb_ops) },
7187 +       { USB_DEVICE(0x14b2, 0x3c27), USB_DEVICE_DATA(&rt2800usb_ops) },
7188 +       { USB_DEVICE(0x14b2, 0x3c28), USB_DEVICE_DATA(&rt2800usb_ops) },
7189 +       /* Corega */
7190 +       { USB_DEVICE(0x07aa, 0x002f), USB_DEVICE_DATA(&rt2800usb_ops) },
7191 +       { USB_DEVICE(0x07aa, 0x003c), USB_DEVICE_DATA(&rt2800usb_ops) },
7192 +       { USB_DEVICE(0x07aa, 0x003f), USB_DEVICE_DATA(&rt2800usb_ops) },
7193 +       /* D-Link */
7194 +       { USB_DEVICE(0x07d1, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
7195 +       { USB_DEVICE(0x07d1, 0x3c11), USB_DEVICE_DATA(&rt2800usb_ops) },
7196 +       /* EnGenius */
7197 +       { USB_DEVICE(0X1740, 0x9701), USB_DEVICE_DATA(&rt2800usb_ops) },
7198 +       { USB_DEVICE(0x1740, 0x9702), USB_DEVICE_DATA(&rt2800usb_ops) },
7199 +       /* Gigabyte */
7200 +       { USB_DEVICE(0x1044, 0x800b), USB_DEVICE_DATA(&rt2800usb_ops) },
7201 +       /* Hawking */
7202 +       { USB_DEVICE(0x0e66, 0x0001), USB_DEVICE_DATA(&rt2800usb_ops) },
7203 +       { USB_DEVICE(0x0e66, 0x0003), USB_DEVICE_DATA(&rt2800usb_ops) },
7204 +       /* Linksys */
7205 +       { USB_DEVICE(0x1737, 0x0071), USB_DEVICE_DATA(&rt2800usb_ops) },
7206 +       /* Philips */
7207 +       { USB_DEVICE(0x0471, 0x200f), USB_DEVICE_DATA(&rt2800usb_ops) },
7208 +       /* Planex */
7209 +       { USB_DEVICE(0x2019, 0xed06), USB_DEVICE_DATA(&rt2800usb_ops) },
7210 +       /* Ralink */
7211 +       { USB_DEVICE(0x148f, 0x2770), USB_DEVICE_DATA(&rt2800usb_ops) },
7212 +       { USB_DEVICE(0x148f, 0x2870), USB_DEVICE_DATA(&rt2800usb_ops) },
7213 +       /* Siemens */
7214 +       { USB_DEVICE(0x129b, 0x1828), USB_DEVICE_DATA(&rt2800usb_ops) },
7215 +       /* Sitecom */
7216 +       { USB_DEVICE(0x0df6, 0x0017), USB_DEVICE_DATA(&rt2800usb_ops) },
7217 +       { USB_DEVICE(0x0df6, 0x002b), USB_DEVICE_DATA(&rt2800usb_ops) },
7218 +       { USB_DEVICE(0x0df6, 0x002c), USB_DEVICE_DATA(&rt2800usb_ops) },
7219 +       { USB_DEVICE(0x0df6, 0x002d), USB_DEVICE_DATA(&rt2800usb_ops) },
7220 +       /* SMC */
7221 +       { USB_DEVICE(0x083a, 0x6618), USB_DEVICE_DATA(&rt2800usb_ops) },
7222 +       { USB_DEVICE(0x083a, 0x7522), USB_DEVICE_DATA(&rt2800usb_ops) },
7223 +       { USB_DEVICE(0x083a, 0xb522), USB_DEVICE_DATA(&rt2800usb_ops) },
7224 +       { USB_DEVICE(0x083a, 0xa618), USB_DEVICE_DATA(&rt2800usb_ops) },
7225 +       /* Sparklan */
7226 +       { USB_DEVICE(0x15a9, 0x0006), USB_DEVICE_DATA(&rt2800usb_ops) },
7227 +       /* U-Media*/
7228 +       { USB_DEVICE(0x157e, 0x300e), USB_DEVICE_DATA(&rt2800usb_ops) },
7229 +       /* ZCOM */
7230 +       { USB_DEVICE(0x0cde, 0x0022), USB_DEVICE_DATA(&rt2800usb_ops) },
7231 +       { USB_DEVICE(0x0cde, 0x0025), USB_DEVICE_DATA(&rt2800usb_ops) },
7232 +       /* Zyxel */
7233 +       { USB_DEVICE(0x0586, 0x3416), USB_DEVICE_DATA(&rt2800usb_ops) },
7234 +       { 0, }
7235 +};
7236 +
7237 +MODULE_AUTHOR(DRV_PROJECT);
7238 +MODULE_VERSION(DRV_VERSION);
7239 +MODULE_DESCRIPTION("Ralink RT2800 USB Wireless LAN driver.");
7240 +MODULE_SUPPORTED_DEVICE("Ralink RT2870 USB chipset based cards");
7241 +MODULE_DEVICE_TABLE(usb, rt2800usb_device_table);
7242 +MODULE_FIRMWARE(FIRMWARE_RT2870);
7243 +MODULE_LICENSE("GPL");
7244 +
7245 +static struct usb_driver rt2800usb_driver = {
7246 +       .name           = KBUILD_MODNAME,
7247 +       .id_table       = rt2800usb_device_table,
7248 +       .probe          = rt2x00usb_probe,
7249 +       .disconnect     = rt2x00usb_disconnect,
7250 +       .suspend        = rt2x00usb_suspend,
7251 +       .resume         = rt2x00usb_resume,
7252 +};
7253 +
7254 +static int __init rt2800usb_init(void)
7255 +{
7256 +       return usb_register(&rt2800usb_driver);
7257 +}
7258 +
7259 +static void __exit rt2800usb_exit(void)
7260 +{
7261 +       usb_deregister(&rt2800usb_driver);
7262 +}
7263 +
7264 +module_init(rt2800usb_init);
7265 +module_exit(rt2800usb_exit);
7266 --- /dev/null
7267 +++ b/drivers/net/wireless/rt2x00/rt2800usb.h
7268 @@ -0,0 +1,1884 @@
7269 +/*
7270 +       Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
7271 +       <http://rt2x00.serialmonkey.com>
7272 +
7273 +       This program is free software; you can redistribute it and/or modify
7274 +       it under the terms of the GNU General Public License as published by
7275 +       the Free Software Foundation; either version 2 of the License, or
7276 +       (at your option) any later version.
7277 +
7278 +       This program is distributed in the hope that it will be useful,
7279 +       but WITHOUT ANY WARRANTY; without even the implied warranty of
7280 +       MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7281 +       GNU General Public License for more details.
7282 +
7283 +       You should have received a copy of the GNU General Public License
7284 +       along with this program; if not, write to the
7285 +       Free Software Foundation, Inc.,
7286 +       59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
7287 + */
7288 +
7289 +/*
7290 +       Module: rt2800usb
7291 +       Abstract: Data structures and registers for the rt2800usb module.
7292 +       Supported chipsets: RT2800U.
7293 + */
7294 +
7295 +#ifndef RT2800USB_H
7296 +#define RT2800USB_H
7297 +
7298 +/*
7299 + * RF chip defines.
7300 + *
7301 + * RF2820 2.4G 2T3R
7302 + * RF2850 2.4G/5G 2T3R
7303 + * RF2720 2.4G 1T2R
7304 + * RF2750 2.4G/5G 1T2R
7305 + */
7306 +#define RF2820                         0x0001
7307 +#define RF2850                         0x0002
7308 +#define RF2720                         0x0003
7309 +#define RF2750                         0x0004
7310 +
7311 +/*
7312 + * RT2870 version
7313 + */
7314 +#define RT2870_VERSION_C               0x0100
7315 +#define RT2870_VERSION_D               0x0101
7316 +#define RT2870_VERSION_E               0x0200
7317 +
7318 +/*
7319 + * Signal information.
7320 + * Defaul offset is required for RSSI <-> dBm conversion.
7321 + */
7322 +#define MAX_SIGNAL                     0 /* FIXME */
7323 +#define MAX_RX_SSI                     0 /* FIXME */
7324 +#define DEFAULT_RSSI_OFFSET            120 /* FIXME */
7325 +
7326 +/*
7327 + * Register layout information.
7328 + */
7329 +#define CSR_REG_BASE                   0x1000
7330 +#define CSR_REG_SIZE                   0x0800
7331 +#define EEPROM_BASE                    0x0000
7332 +#define EEPROM_SIZE                    0x0110
7333 +#define BBP_BASE                       0x0000
7334 +#define BBP_SIZE                       0x0080
7335 +#define RF_BASE                                0x0000
7336 +#define RF_SIZE                                0x0014
7337 +
7338 +/*
7339 + * Number of TX queues.
7340 + */
7341 +#define NUM_TX_QUEUES                  4
7342 +
7343 +/*
7344 + * USB registers.
7345 + */
7346 +
7347 +/*
7348 + * HOST-MCU shared memory
7349 + */
7350 +#define HOST_CMD_CSR                   0x0404
7351 +#define HOST_CMD_CSR_HOST_COMMAND      FIELD32(0x000000ff)
7352 +
7353 +/*
7354 + * INT_SOURCE_CSR: Interrupt source register.
7355 + * Write one to clear corresponding bit.
7356 + * TX_FIFO_STATUS: FIFO Statistics is full, sw should read 0x171c
7357 + */
7358 +#define INT_SOURCE_CSR                 0x0200
7359 +#define INT_SOURCE_CSR_RXDELAYINT      FIELD32(0x00000001)
7360 +#define INT_SOURCE_CSR_TXDELAYINT      FIELD32(0x00000002)
7361 +#define INT_SOURCE_CSR_RX_DONE         FIELD32(0x00000004)
7362 +#define INT_SOURCE_CSR_AC0_DMA_DONE    FIELD32(0x00000008)
7363 +#define INT_SOURCE_CSR_AC1_DMA_DONE    FIELD32(0x00000010)
7364 +#define INT_SOURCE_CSR_AC2_DMA_DONE    FIELD32(0x00000020)
7365 +#define INT_SOURCE_CSR_AC3_DMA_DONE    FIELD32(0x00000040)
7366 +#define INT_SOURCE_CSR_HCCA_DMA_DONE   FIELD32(0x00000080)
7367 +#define INT_SOURCE_CSR_MGMT_DMA_DONE   FIELD32(0x00000100)
7368 +#define INT_SOURCE_CSR_MCU_COMMAND     FIELD32(0x00000200)
7369 +#define INT_SOURCE_CSR_RXTX_COHERENT   FIELD32(0x00000400)
7370 +#define INT_SOURCE_CSR_TBTT            FIELD32(0x00000800)
7371 +#define INT_SOURCE_CSR_PRE_TBTT                FIELD32(0x00001000)
7372 +#define INT_SOURCE_CSR_TX_FIFO_STATUS  FIELD32(0x00002000)
7373 +#define INT_SOURCE_CSR_AUTO_WAKEUP     FIELD32(0x00004000)
7374 +#define INT_SOURCE_CSR_GPTIMER         FIELD32(0x00008000)
7375 +#define INT_SOURCE_CSR_RX_COHERENT     FIELD32(0x00010000)
7376 +#define INT_SOURCE_CSR_TX_COHERENT     FIELD32(0x00020000)
7377 +
7378 +/*
7379 + * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
7380 + */
7381 +#define INT_MASK_CSR                   0x0204
7382 +#define INT_MASK_CSR_RXDELAYINT                FIELD32(0x00000001)
7383 +#define INT_MASK_CSR_TXDELAYINT                FIELD32(0x00000002)
7384 +#define INT_MASK_CSR_RX_DONE           FIELD32(0x00000004)
7385 +#define INT_MASK_CSR_AC0_DMA_DONE      FIELD32(0x00000008)
7386 +#define INT_MASK_CSR_AC1_DMA_DONE      FIELD32(0x00000010)
7387 +#define INT_MASK_CSR_AC2_DMA_DONE      FIELD32(0x00000020)
7388 +#define INT_MASK_CSR_AC3_DMA_DONE      FIELD32(0x00000040)
7389 +#define INT_MASK_CSR_HCCA_DMA_DONE     FIELD32(0x00000080)
7390 +#define INT_MASK_CSR_MGMT_DMA_DONE     FIELD32(0x00000100)
7391 +#define INT_MASK_CSR_MCU_COMMAND       FIELD32(0x00000200)
7392 +#define INT_MASK_CSR_RX_COHERENT       FIELD32(0x40000000)
7393 +#define INT_MASK_CSR_TX_COHERENT       FIELD32(0x80000000)
7394 +
7395 +/*
7396 + * WPDMA_GLO_CFG
7397 + */
7398 +#define WPDMA_GLO_CFG                  0x0208
7399 +#define WPDMA_GLO_CFG_ENABLE_TX_DMA    FIELD32(0x00000001)
7400 +#define WPDMA_GLO_CFG_TX_DMA_BUSY      FIELD32(0x00000002)
7401 +#define WPDMA_GLO_CFG_ENABLE_RX_DMA    FIELD32(0x00000004)
7402 +#define WPDMA_GLO_CFG_RX_DMA_BUSY      FIELD32(0x00000008)
7403 +#define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE        FIELD32(0x00000030)
7404 +#define WPDMA_GLO_CFG_TX_WRITEBACK_DONE        FIELD32(0x00000040)
7405 +#define WPDMA_GLO_CFG_BIG_ENDIAN       FIELD32(0x00000080)
7406 +#define WPDMA_GLO_CFG_RX_HDR_SCATTER   FIELD32(0x0000ff00)
7407 +#define WPDMA_GLO_CFG_HDR_SEG_LEN      FIELD32(0xffff0000)
7408 +
7409 +/*
7410 + * WPDMA_RST_IDX
7411 + */
7412 +#define WPDMA_RST_IDX                  0x020c
7413 +#define WPDMA_RST_IDX_DTX_IDX0         FIELD32(0x00000001)
7414 +#define WPDMA_RST_IDX_DTX_IDX1         FIELD32(0x00000002)
7415 +#define WPDMA_RST_IDX_DTX_IDX2         FIELD32(0x00000004)
7416 +#define WPDMA_RST_IDX_DTX_IDX3         FIELD32(0x00000008)
7417 +#define WPDMA_RST_IDX_DTX_IDX4         FIELD32(0x00000010)
7418 +#define WPDMA_RST_IDX_DTX_IDX5         FIELD32(0x00000020)
7419 +#define WPDMA_RST_IDX_DRX_IDX0         FIELD32(0x00010000)
7420 +
7421 +/*
7422 + * DELAY_INT_CFG
7423 + */
7424 +#define DELAY_INT_CFG                  0x0210
7425 +#define DELAY_INT_CFG_RXMAX_PTIME      FIELD32(0x000000ff)
7426 +#define DELAY_INT_CFG_RXMAX_PINT       FIELD32(0x00007f00)
7427 +#define DELAY_INT_CFG_RXDLY_INT_EN     FIELD32(0x00008000)
7428 +#define DELAY_INT_CFG_TXMAX_PTIME      FIELD32(0x00ff0000)
7429 +#define DELAY_INT_CFG_TXMAX_PINT       FIELD32(0x7f000000)
7430 +#define DELAY_INT_CFG_TXDLY_INT_EN     FIELD32(0x80000000)
7431 +
7432 +/*
7433 + * WMM_AIFSN_CFG: Aifsn for each EDCA AC
7434 + * AIFSN0: AC_BE
7435 + * AIFSN1: AC_BK
7436 + * AIFSN1: AC_VI
7437 + * AIFSN1: AC_VO
7438 + */
7439 +#define WMM_AIFSN_CFG                  0x0214
7440 +#define WMM_AIFSN_CFG_AIFSN0           FIELD32(0x0000000f)
7441 +#define WMM_AIFSN_CFG_AIFSN1           FIELD32(0x000000f0)
7442 +#define WMM_AIFSN_CFG_AIFSN2           FIELD32(0x00000f00)
7443 +#define WMM_AIFSN_CFG_AIFSN3           FIELD32(0x0000f000)
7444 +
7445 +/*
7446 + * WMM_CWMIN_CSR: CWmin for each EDCA AC
7447 + * CWMIN0: AC_BE
7448 + * CWMIN1: AC_BK
7449 + * CWMIN1: AC_VI
7450 + * CWMIN1: AC_VO
7451 + */
7452 +#define WMM_CWMIN_CFG                  0x0218
7453 +#define WMM_CWMIN_CFG_CWMIN0           FIELD32(0x0000000f)
7454 +#define WMM_CWMIN_CFG_CWMIN1           FIELD32(0x000000f0)
7455 +#define WMM_CWMIN_CFG_CWMIN2           FIELD32(0x00000f00)
7456 +#define WMM_CWMIN_CFG_CWMIN3           FIELD32(0x0000f000)
7457 +
7458 +/*
7459 + * WMM_CWMAX_CSR: CWmax for each EDCA AC
7460 + * CWMAX0: AC_BE
7461 + * CWMAX1: AC_BK
7462 + * CWMAX1: AC_VI
7463 + * CWMAX1: AC_VO
7464 + */
7465 +#define WMM_CWMAX_CFG                  0x021c
7466 +#define WMM_CWMAX_CFG_CWMAX0           FIELD32(0x0000000f)
7467 +#define WMM_CWMAX_CFG_CWMAX1           FIELD32(0x000000f0)
7468 +#define WMM_CWMAX_CFG_CWMAX2           FIELD32(0x00000f00)
7469 +#define WMM_CWMAX_CFG_CWMAX3           FIELD32(0x0000f000)
7470 +
7471 +/*
7472 + * AC_TXOP0: AC_BK/AC_BE TXOP register
7473 + * AC0TXOP: AC_BK in unit of 32us
7474 + * AC1TXOP: AC_BE in unit of 32us
7475 + */
7476 +#define WMM_TXOP0_CFG                  0x0220
7477 +#define WMM_TXOP0_CFG_AC0TXOP          FIELD32(0x0000ffff)
7478 +#define WMM_TXOP0_CFG_AC1TXOP          FIELD32(0xffff0000)
7479 +
7480 +/*
7481 + * AC_TXOP1: AC_VO/AC_VI TXOP register
7482 + * AC2TXOP: AC_VI in unit of 32us
7483 + * AC3TXOP: AC_VO in unit of 32us
7484 + */
7485 +#define WMM_TXOP1_CFG                  0x0224
7486 +#define WMM_TXOP1_CFG_AC2TXOP          FIELD32(0x0000ffff)
7487 +#define WMM_TXOP1_CFG_AC3TXOP          FIELD32(0xffff0000)
7488 +
7489 +/*
7490 + * RINGREG_DIFF
7491 + */
7492 +#define RINGREG_DIFF                   0x0010
7493 +
7494 +/*
7495 + * GPIO_CTRL_CFG:
7496 + */
7497 +#define GPIO_CTRL_CFG                  0x0228
7498 +#define GPIO_CTRL_CFG_BIT0             FIELD32(0x00000001)
7499 +#define GPIO_CTRL_CFG_BIT1             FIELD32(0x00000002)
7500 +#define GPIO_CTRL_CFG_BIT2             FIELD32(0x00000004)
7501 +#define GPIO_CTRL_CFG_BIT3             FIELD32(0x00000008)
7502 +#define GPIO_CTRL_CFG_BIT4             FIELD32(0x00000010)
7503 +#define GPIO_CTRL_CFG_BIT5             FIELD32(0x00000020)
7504 +#define GPIO_CTRL_CFG_BIT6             FIELD32(0x00000040)
7505 +#define GPIO_CTRL_CFG_BIT7             FIELD32(0x00000080)
7506 +#define GPIO_CTRL_CFG_BIT8             FIELD32(0x00000100)
7507 +
7508 +/*
7509 + * MCU_CMD_CFG
7510 + */
7511 +#define MCU_CMD_CFG                    0x022c
7512 +
7513 +/*
7514 + * AC_BK register offsets
7515 + */
7516 +#define TX_BASE_PTR0                   0x0230
7517 +#define TX_MAX_CNT0                    0x0234
7518 +#define TX_CTX_IDX0                    0x0238
7519 +#define TX_DTX_IDX0                    0x023c
7520 +
7521 +/*
7522 + * AC_BE register offsets
7523 + */
7524 +#define TX_BASE_PTR1                   0x0240
7525 +#define TX_MAX_CNT1                    0x0244
7526 +#define TX_CTX_IDX1                    0x0248
7527 +#define TX_DTX_IDX1                    0x024c
7528 +
7529 +/*
7530 + * AC_VI register offsets
7531 + */
7532 +#define TX_BASE_PTR2                   0x0250
7533 +#define TX_MAX_CNT2                    0x0254
7534 +#define TX_CTX_IDX2                    0x0258
7535 +#define TX_DTX_IDX2                    0x025c
7536 +
7537 +/*
7538 + * AC_VO register offsets
7539 + */
7540 +#define TX_BASE_PTR3                   0x0260
7541 +#define TX_MAX_CNT3                    0x0264
7542 +#define TX_CTX_IDX3                    0x0268
7543 +#define TX_DTX_IDX3                    0x026c
7544 +
7545 +/*
7546 + * HCCA register offsets
7547 + */
7548 +#define TX_BASE_PTR4                   0x0270
7549 +#define TX_MAX_CNT4                    0x0274
7550 +#define TX_CTX_IDX4                    0x0278
7551 +#define TX_DTX_IDX4                    0x027c
7552 +
7553 +/*
7554 + * MGMT register offsets
7555 + */
7556 +#define TX_BASE_PTR5                   0x0280
7557 +#define TX_MAX_CNT5                    0x0284
7558 +#define TX_CTX_IDX5                    0x0288
7559 +#define TX_DTX_IDX5                    0x028c
7560 +
7561 +/*
7562 + * RX register offsets
7563 + */
7564 +#define RX_BASE_PTR                    0x0290
7565 +#define RX_MAX_CNT                     0x0294
7566 +#define RX_CRX_IDX                     0x0298
7567 +#define RX_DRX_IDX                     0x029c
7568 +
7569 +/*
7570 + * USB_DMA_CFG
7571 + * RX_BULK_AGG_TIMEOUT: Rx Bulk Aggregation TimeOut in unit of 33ns.
7572 + * RX_BULK_AGG_LIMIT: Rx Bulk Aggregation Limit in unit of 256 bytes.
7573 + * PHY_CLEAR: phy watch dog enable.
7574 + * TX_CLEAR: Clear USB DMA TX path.
7575 + * TXOP_HALT: Halt TXOP count down when TX buffer is full.
7576 + * RX_BULK_AGG_EN: Enable Rx Bulk Aggregation.
7577 + * RX_BULK_EN: Enable USB DMA Rx.
7578 + * TX_BULK_EN: Enable USB DMA Tx.
7579 + * EP_OUT_VALID: OUT endpoint data valid.
7580 + * RX_BUSY: USB DMA RX FSM busy.
7581 + * TX_BUSY: USB DMA TX FSM busy.
7582 + */
7583 +#define USB_DMA_CFG                    0x02a0
7584 +#define USB_DMA_CFG_RX_BULK_AGG_TIMEOUT        FIELD32(0x000000ff)
7585 +#define USB_DMA_CFG_RX_BULK_AGG_LIMIT  FIELD32(0x0000ff00)
7586 +#define USB_DMA_CFG_PHY_CLEAR          FIELD32(0x00010000)
7587 +#define USB_DMA_CFG_TX_CLEAR           FIELD32(0x00080000)
7588 +#define USB_DMA_CFG_TXOP_HALT          FIELD32(0x00100000)
7589 +#define USB_DMA_CFG_RX_BULK_AGG_EN     FIELD32(0x00200000)
7590 +#define USB_DMA_CFG_RX_BULK_EN         FIELD32(0x00400000)
7591 +#define USB_DMA_CFG_TX_BULK_EN         FIELD32(0x00800000)
7592 +#define USB_DMA_CFG_EP_OUT_VALID       FIELD32(0x3f000000)
7593 +#define USB_DMA_CFG_RX_BUSY            FIELD32(0x40000000)
7594 +#define USB_DMA_CFG_TX_BUSY            FIELD32(0x80000000)
7595 +
7596 +/*
7597 + * USB_CYC_CFG
7598 + */
7599 +#define USB_CYC_CFG                    0x02a4
7600 +#define USB_CYC_CFG_CLOCK_CYCLE                FIELD32(0x000000ff)
7601 +
7602 +/*
7603 + * PBF_SYS_CTRL
7604 + * HOST_RAM_WRITE: enable Host program ram write selection
7605 + */
7606 +#define PBF_SYS_CTRL                   0x0400
7607 +#define PBF_SYS_CTRL_READY             FIELD32(0x00000080)
7608 +#define PBF_SYS_CTRL_HOST_RAM_WRITE    FIELD32(0x00010000)
7609 +
7610 +/*
7611 + * PBF registers
7612 + * Most are for debug. Driver doesn't touch PBF register.
7613 + */
7614 +#define PBF_CFG                                0x0408
7615 +#define PBF_MAX_PCNT                   0x040c
7616 +#define PBF_CTRL                       0x0410
7617 +#define PBF_INT_STA                    0x0414
7618 +#define PBF_INT_ENA                    0x0418
7619 +
7620 +/*
7621 + * BCN_OFFSET0:
7622 + */
7623 +#define BCN_OFFSET0                    0x042c
7624 +#define BCN_OFFSET0_BCN0               FIELD32(0x000000ff)
7625 +#define BCN_OFFSET0_BCN1               FIELD32(0x0000ff00)
7626 +#define BCN_OFFSET0_BCN2               FIELD32(0x00ff0000)
7627 +#define BCN_OFFSET0_BCN3               FIELD32(0xff000000)
7628 +
7629 +/*
7630 + * BCN_OFFSET1:
7631 + */
7632 +#define BCN_OFFSET1                    0x0430
7633 +#define BCN_OFFSET1_BCN4               FIELD32(0x000000ff)
7634 +#define BCN_OFFSET1_BCN5               FIELD32(0x0000ff00)
7635 +#define BCN_OFFSET1_BCN6               FIELD32(0x00ff0000)
7636 +#define BCN_OFFSET1_BCN7               FIELD32(0xff000000)
7637 +
7638 +/*
7639 + * PBF registers
7640 + * Most are for debug. Driver doesn't touch PBF register.
7641 + */
7642 +#define TXRXQ_PCNT                     0x0438
7643 +#define PBF_DBG                                0x043c
7644 +
7645 +/*
7646 + * MAC Control/Status Registers(CSR).
7647 + * Some values are set in TU, whereas 1 TU == 1024 us.
7648 + */
7649 +
7650 +/*
7651 + * MAC_CSR0: ASIC revision number.
7652 + * ASIC_REV: 0
7653 + * ASIC_VER: 2870
7654 + */
7655 +#define MAC_CSR0                       0x1000
7656 +#define MAC_CSR0_ASIC_REV              FIELD32(0x0000ffff)
7657 +#define MAC_CSR0_ASIC_VER              FIELD32(0xffff0000)
7658 +
7659 +/*
7660 + * MAC_SYS_CTRL:
7661 + */
7662 +#define MAC_SYS_CTRL                   0x1004
7663 +#define MAC_SYS_CTRL_RESET_CSR         FIELD32(0x00000001)
7664 +#define MAC_SYS_CTRL_RESET_BBP         FIELD32(0x00000002)
7665 +#define MAC_SYS_CTRL_ENABLE_TX         FIELD32(0x00000004)
7666 +#define MAC_SYS_CTRL_ENABLE_RX         FIELD32(0x00000008)
7667 +#define MAC_SYS_CTRL_CONTINUOUS_TX     FIELD32(0x00000010)
7668 +#define MAC_SYS_CTRL_LOOPBACK          FIELD32(0x00000020)
7669 +#define MAC_SYS_CTRL_WLAN_HALT         FIELD32(0x00000040)
7670 +#define MAC_SYS_CTRL_RX_TIMESTAMP      FIELD32(0x00000080)
7671 +
7672 +/*
7673 + * MAC_ADDR_DW0: STA MAC register 0
7674 + */
7675 +#define MAC_ADDR_DW0                   0x1008
7676 +#define MAC_ADDR_DW0_BYTE0             FIELD32(0x000000ff)
7677 +#define MAC_ADDR_DW0_BYTE1             FIELD32(0x0000ff00)
7678 +#define MAC_ADDR_DW0_BYTE2             FIELD32(0x00ff0000)
7679 +#define MAC_ADDR_DW0_BYTE3             FIELD32(0xff000000)
7680 +
7681 +/*
7682 + * MAC_ADDR_DW1: STA MAC register 1
7683 + * UNICAST_TO_ME_MASK:
7684 + * Used to mask off bits from byte 5 of the MAC address
7685 + * to determine the UNICAST_TO_ME bit for RX frames.
7686 + * The full mask is complemented by BSS_ID_MASK:
7687 + *    MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
7688 + */
7689 +#define MAC_ADDR_DW1                   0x100c
7690 +#define MAC_ADDR_DW1_BYTE4             FIELD32(0x000000ff)
7691 +#define MAC_ADDR_DW1_BYTE5             FIELD32(0x0000ff00)
7692 +#define MAC_ADDR_DW1_UNICAST_TO_ME_MASK        FIELD32(0x00ff0000)
7693 +
7694 +/*
7695 + * MAC_BSSID_DW0: BSSID register 0
7696 + */
7697 +#define MAC_BSSID_DW0                  0x1010
7698 +#define MAC_BSSID_DW0_BYTE0            FIELD32(0x000000ff)
7699 +#define MAC_BSSID_DW0_BYTE1            FIELD32(0x0000ff00)
7700 +#define MAC_BSSID_DW0_BYTE2            FIELD32(0x00ff0000)
7701 +#define MAC_BSSID_DW0_BYTE3            FIELD32(0xff000000)
7702 +
7703 +/*
7704 + * MAC_BSSID_DW1: BSSID register 1
7705 + * BSS_ID_MASK:
7706 + *     0: 1-BSSID mode (BSS index = 0)
7707 + *     1: 2-BSSID mode (BSS index: Byte5, bit 0)
7708 + *     2: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
7709 + *     3: 8-BSSID mode (BSS index: byte5, bit 0 - 2)
7710 + * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the
7711 + * BSSID. This will make sure that those bits will be ignored
7712 + * when determining the MY_BSS of RX frames.
7713 + */
7714 +#define MAC_BSSID_DW1                  0x1014
7715 +#define MAC_BSSID_DW1_BYTE4            FIELD32(0x000000ff)
7716 +#define MAC_BSSID_DW1_BYTE5            FIELD32(0x0000ff00)
7717 +#define MAC_BSSID_DW1_BSS_ID_MASK      FIELD32(0x00030000)
7718 +#define MAC_BSSID_DW1_BSS_BCN_NUM      FIELD32(0x001c0000)
7719 +
7720 +/*
7721 + * MAX_LEN_CFG: Maximum frame length register.
7722 + * MAX_MPDU: rt2860b max 16k bytes
7723 + * MAX_PSDU: Maximum PSDU length
7724 + *     (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
7725 + */
7726 +#define MAX_LEN_CFG                    0x1018
7727 +#define MAX_LEN_CFG_MAX_MPDU           FIELD32(0x00000fff)
7728 +#define MAX_LEN_CFG_MAX_PSDU           FIELD32(0x00003000)
7729 +#define MAX_LEN_CFG_MIN_PSDU           FIELD32(0x0000c000)
7730 +#define MAX_LEN_CFG_MIN_MPDU           FIELD32(0x000f0000)
7731 +
7732 +/*
7733 + * BBP_CSR_CFG: BBP serial control register
7734 + * VALUE: Register value to program into BBP
7735 + * REG_NUM: Selected BBP register
7736 + * READ_CONTROL: 0 write BBP, 1 read BBP
7737 + * BUSY: ASIC is busy executing BBP commands
7738 + * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks
7739 + * BBP_RW_MODE: 0 serial, 1 paralell
7740 + */
7741 +#define BBP_CSR_CFG                    0x101c
7742 +#define BBP_CSR_CFG_VALUE              FIELD32(0x000000ff)
7743 +#define BBP_CSR_CFG_REGNUM             FIELD32(0x0000ff00)
7744 +#define BBP_CSR_CFG_READ_CONTROL       FIELD32(0x00010000)
7745 +#define BBP_CSR_CFG_BUSY               FIELD32(0x00020000)
7746 +#define BBP_CSR_CFG_BBP_PAR_DUR                FIELD32(0x00040000)
7747 +#define BBP_CSR_CFG_BBP_RW_MODE                FIELD32(0x00080000)
7748 +
7749 +/*
7750 + * RF_CSR_CFG0: RF control register
7751 + * REGID_AND_VALUE: Register value to program into RF
7752 + * BITWIDTH: Selected RF register
7753 + * STANDBYMODE: 0 high when standby, 1 low when standby
7754 + * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate
7755 + * BUSY: ASIC is busy executing RF commands
7756 + */
7757 +#define RF_CSR_CFG0                    0x1020
7758 +#define RF_CSR_CFG0_REGID_AND_VALUE    FIELD32(0x00ffffff)
7759 +#define RF_CSR_CFG0_BITWIDTH           FIELD32(0x1f000000)
7760 +#define RF_CSR_CFG0_REG_VALUE_BW       FIELD32(0x1fffffff)
7761 +#define RF_CSR_CFG0_STANDBYMODE                FIELD32(0x20000000)
7762 +#define RF_CSR_CFG0_SEL                        FIELD32(0x40000000)
7763 +#define RF_CSR_CFG0_BUSY               FIELD32(0x80000000)
7764 +
7765 +/*
7766 + * RF_CSR_CFG1: RF control register
7767 + * REGID_AND_VALUE: Register value to program into RF
7768 + * RFGAP: Gap between BB_CONTROL_RF and RF_LE
7769 + *        0: 3 system clock cycle (37.5usec)
7770 + *        1: 5 system clock cycle (62.5usec)
7771 + */
7772 +#define RF_CSR_CFG1                    0x1024
7773 +#define RF_CSR_CFG1_REGID_AND_VALUE    FIELD32(0x00ffffff)
7774 +#define RF_CSR_CFG1_RFGAP              FIELD32(0x1f000000)
7775 +
7776 +/*
7777 + * RF_CSR_CFG2: RF control register
7778 + * VALUE: Register value to program into RF
7779 + * RFGAP: Gap between BB_CONTROL_RF and RF_LE
7780 + *        0: 3 system clock cycle (37.5usec)
7781 + *        1: 5 system clock cycle (62.5usec)
7782 + */
7783 +#define RF_CSR_CFG2                    0x1028
7784 +#define RF_CSR_CFG2_VALUE              FIELD32(0x00ffffff)
7785 +
7786 +/*
7787 + * LED_CFG: LED control
7788 + * color LED's:
7789 + *   0: off
7790 + *   1: blinking upon TX2
7791 + *   2: periodic slow blinking
7792 + *   3: always on
7793 + * LED polarity:
7794 + *   0: active low
7795 + *   1: active high
7796 + */
7797 +#define LED_CFG                                0x102c
7798 +#define LED_CFG_ON_PERIOD              FIELD32(0x000000ff)
7799 +#define LED_CFG_OFF_PERIOD             FIELD32(0x0000ff00)
7800 +#define LED_CFG_SLOW_BLINK_PERIOD      FIELD32(0x003f0000)
7801 +#define LED_CFG_R_LED_MODE             FIELD32(0x03000000)
7802 +#define LED_CFG_G_LED_MODE             FIELD32(0x0c000000)
7803 +#define LED_CFG_Y_LED_MODE             FIELD32(0x30000000)
7804 +#define LED_CFG_LED_POLAR              FIELD32(0x40000000)
7805 +
7806 +/*
7807 + * XIFS_TIME_CFG: MAC timing
7808 + * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX
7809 + * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX
7810 + * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX
7811 + *     when MAC doesn't reference BBP signal BBRXEND
7812 + * EIFS: unit 1us
7813 + * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer
7814 + *
7815 + */
7816 +#define XIFS_TIME_CFG                  0x1100
7817 +#define XIFS_TIME_CFG_CCKM_SIFS_TIME   FIELD32(0x000000ff)
7818 +#define XIFS_TIME_CFG_OFDM_SIFS_TIME   FIELD32(0x0000ff00)
7819 +#define XIFS_TIME_CFG_OFDM_XIFS_TIME   FIELD32(0x000f0000)
7820 +#define XIFS_TIME_CFG_EIFS             FIELD32(0x1ff00000)
7821 +#define XIFS_TIME_CFG_BB_RXEND_ENABLE  FIELD32(0x20000000)
7822 +
7823 +/*
7824 + * BKOFF_SLOT_CFG:
7825 + */
7826 +#define BKOFF_SLOT_CFG                 0x1104
7827 +#define BKOFF_SLOT_CFG_SLOT_TIME       FIELD32(0x000000ff)
7828 +#define BKOFF_SLOT_CFG_CC_DELAY_TIME   FIELD32(0x0000ff00)
7829 +
7830 +/*
7831 + * NAV_TIME_CFG:
7832 + */
7833 +#define NAV_TIME_CFG                   0x1108
7834 +#define NAV_TIME_CFG_SIFS              FIELD32(0x000000ff)
7835 +#define NAV_TIME_CFG_SLOT_TIME         FIELD32(0x0000ff00)
7836 +#define NAV_TIME_CFG_EIFS              FIELD32(0x01ff0000)
7837 +#define NAV_TIME_ZERO_SIFS             FIELD32(0x02000000)
7838 +
7839 +/*
7840 + * CH_TIME_CFG: count as channel busy
7841 + */
7842 +#define CH_TIME_CFG                    0x110c
7843 +
7844 +/*
7845 + * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us
7846 + */
7847 +#define PBF_LIFE_TIMER                 0x1110
7848 +
7849 +/*
7850 + * BCN_TIME_CFG:
7851 + * BEACON_INTERVAL: in unit of 1/16 TU
7852 + * TSF_TICKING: Enable TSF auto counting
7853 + * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
7854 + * BEACON_GEN: Enable beacon generator
7855 + */
7856 +#define BCN_TIME_CFG                   0x1114
7857 +#define BCN_TIME_CFG_BEACON_INTERVAL   FIELD32(0x0000ffff)
7858 +#define BCN_TIME_CFG_TSF_TICKING       FIELD32(0x00010000)
7859 +#define BCN_TIME_CFG_TSF_SYNC          FIELD32(0x00060000)
7860 +#define BCN_TIME_CFG_TBTT_ENABLE       FIELD32(0x00080000)
7861 +#define BCN_TIME_CFG_BEACON_GEN                FIELD32(0x00100000)
7862 +#define BCN_TIME_CFG_TX_TIME_COMPENSATE        FIELD32(0xf0000000)
7863 +
7864 +/*
7865 + * TBTT_SYNC_CFG:
7866 + */
7867 +#define TBTT_SYNC_CFG                  0x1118
7868 +
7869 +/*
7870 + * TSF_TIMER_DW0: Local lsb TSF timer, read-only
7871 + */
7872 +#define TSF_TIMER_DW0                  0x111c
7873 +#define TSF_TIMER_DW0_LOW_WORD         FIELD32(0xffffffff)
7874 +
7875 +/*
7876 + * TSF_TIMER_DW1: Local msb TSF timer, read-only
7877 + */
7878 +#define TSF_TIMER_DW1                  0x1120
7879 +#define TSF_TIMER_DW1_HIGH_WORD                FIELD32(0xffffffff)
7880 +
7881 +/*
7882 + * TBTT_TIMER: TImer remains till next TBTT, read-only
7883 + */
7884 +#define TBTT_TIMER                     0x1124
7885 +
7886 +/*
7887 + * INT_TIMER_CFG:
7888 + */
7889 +#define INT_TIMER_CFG                  0x1128
7890 +
7891 +/*
7892 + * INT_TIMER_EN: GP-timer and pre-tbtt Int enable
7893 + */
7894 +#define INT_TIMER_EN                   0x112c
7895 +
7896 +/*
7897 + * CH_IDLE_STA: channel idle time
7898 + */
7899 +#define CH_IDLE_STA                    0x1130
7900 +
7901 +/*
7902 + * CH_BUSY_STA: channel busy time
7903 + */
7904 +#define CH_BUSY_STA                    0x1134
7905 +
7906 +/*
7907 + * MAC_STATUS_CFG:
7908 + * BBP_RF_BUSY: When set to 0, BBP and RF are stable.
7909 + *     if 1 or higher one of the 2 registers is busy.
7910 + */
7911 +#define MAC_STATUS_CFG                 0x1200
7912 +#define MAC_STATUS_CFG_BBP_RF_BUSY     FIELD32(0x00000003)
7913 +
7914 +/*
7915 + * PWR_PIN_CFG:
7916 + */
7917 +#define PWR_PIN_CFG                    0x1204
7918 +
7919 +/*
7920 + * AUTOWAKEUP_CFG: Manual power control / status register
7921 + * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set
7922 + * AUTOWAKE: 0:sleep, 1:awake
7923 + */
7924 +#define AUTOWAKEUP_CFG                 0x1208
7925 +#define AUTOWAKEUP_CFG_AUTO_LEAD_TIME  FIELD32(0x000000ff)
7926 +#define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE        FIELD32(0x00007f00)
7927 +#define AUTOWAKEUP_CFG_AUTOWAKE                FIELD32(0x00008000)
7928 +
7929 +/*
7930 + * EDCA_AC0_CFG:
7931 + */
7932 +#define EDCA_AC0_CFG                   0x1300
7933 +#define EDCA_AC0_CFG_AC_TX_OP          FIELD32(0x000000ff)
7934 +#define EDCA_AC0_CFG_AIFSN             FIELD32(0x00000f00)
7935 +#define EDCA_AC0_CFG_CWMIN             FIELD32(0x0000f000)
7936 +#define EDCA_AC0_CFG_CWMAX             FIELD32(0x000f0000)
7937 +
7938 +/*
7939 + * EDCA_AC1_CFG:
7940 + */
7941 +#define EDCA_AC1_CFG                   0x1304
7942 +#define EDCA_AC1_CFG_AC_TX_OP          FIELD32(0x000000ff)
7943 +#define EDCA_AC1_CFG_AIFSN             FIELD32(0x00000f00)
7944 +#define EDCA_AC1_CFG_CWMIN             FIELD32(0x0000f000)
7945 +#define EDCA_AC1_CFG_CWMAX             FIELD32(0x000f0000)
7946 +
7947 +/*
7948 + * EDCA_AC2_CFG:
7949 + */
7950 +#define EDCA_AC2_CFG                   0x1308
7951 +#define EDCA_AC2_CFG_AC_TX_OP          FIELD32(0x000000ff)
7952 +#define EDCA_AC2_CFG_AIFSN             FIELD32(0x00000f00)
7953 +#define EDCA_AC2_CFG_CWMIN             FIELD32(0x0000f000)
7954 +#define EDCA_AC2_CFG_CWMAX             FIELD32(0x000f0000)
7955 +
7956 +/*
7957 + * EDCA_AC3_CFG:
7958 + */
7959 +#define EDCA_AC3_CFG                   0x130c
7960 +#define EDCA_AC3_CFG_AC_TX_OP          FIELD32(0x000000ff)
7961 +#define EDCA_AC3_CFG_AIFSN             FIELD32(0x00000f00)
7962 +#define EDCA_AC3_CFG_CWMIN             FIELD32(0x0000f000)
7963 +#define EDCA_AC3_CFG_CWMAX             FIELD32(0x000f0000)
7964 +
7965 +/*
7966 + * EDCA_TID_AC_MAP:
7967 + */
7968 +#define EDCA_TID_AC_MAP                        0x1310
7969 +
7970 +/*
7971 + * TX_PWR_CFG_0:
7972 + */
7973 +#define TX_PWR_CFG_0                   0x1314
7974 +#define TX_PWR_CFG_0_1MBS              FIELD32(0x0000000f)
7975 +#define TX_PWR_CFG_0_2MBS              FIELD32(0x000000f0)
7976 +#define TX_PWR_CFG_0_55MBS             FIELD32(0x00000f00)
7977 +#define TX_PWR_CFG_0_11MBS             FIELD32(0x0000f000)
7978 +#define TX_PWR_CFG_0_6MBS              FIELD32(0x000f0000)
7979 +#define TX_PWR_CFG_0_9MBS              FIELD32(0x00f00000)
7980 +#define TX_PWR_CFG_0_12MBS             FIELD32(0x0f000000)
7981 +#define TX_PWR_CFG_0_18MBS             FIELD32(0xf0000000)
7982 +
7983 +/*
7984 + * TX_PWR_CFG_1:
7985 + */
7986 +#define TX_PWR_CFG_1                   0x1318
7987 +#define TX_PWR_CFG_1_24MBS             FIELD32(0x0000000f)
7988 +#define TX_PWR_CFG_1_36MBS             FIELD32(0x000000f0)
7989 +#define TX_PWR_CFG_1_48MBS             FIELD32(0x00000f00)
7990 +#define TX_PWR_CFG_1_54MBS             FIELD32(0x0000f000)
7991 +#define TX_PWR_CFG_1_MCS0              FIELD32(0x000f0000)
7992 +#define TX_PWR_CFG_1_MCS1              FIELD32(0x00f00000)
7993 +#define TX_PWR_CFG_1_MCS2              FIELD32(0x0f000000)
7994 +#define TX_PWR_CFG_1_MCS3              FIELD32(0xf0000000)
7995 +
7996 +/*
7997 + * TX_PWR_CFG_2:
7998 + */
7999 +#define TX_PWR_CFG_2                   0x131c
8000 +#define TX_PWR_CFG_2_MCS4              FIELD32(0x0000000f)
8001 +#define TX_PWR_CFG_2_MCS5              FIELD32(0x000000f0)
8002 +#define TX_PWR_CFG_2_MCS6              FIELD32(0x00000f00)
8003 +#define TX_PWR_CFG_2_MCS7              FIELD32(0x0000f000)
8004 +#define TX_PWR_CFG_2_MCS8              FIELD32(0x000f0000)
8005 +#define TX_PWR_CFG_2_MCS9              FIELD32(0x00f00000)
8006 +#define TX_PWR_CFG_2_MCS10             FIELD32(0x0f000000)
8007 +#define TX_PWR_CFG_2_MCS11             FIELD32(0xf0000000)
8008 +
8009 +/*
8010 + * TX_PWR_CFG_3:
8011 + */
8012 +#define TX_PWR_CFG_3                   0x1320
8013 +#define TX_PWR_CFG_3_MCS12             FIELD32(0x0000000f)
8014 +#define TX_PWR_CFG_3_MCS13             FIELD32(0x000000f0)
8015 +#define TX_PWR_CFG_3_MCS14             FIELD32(0x00000f00)
8016 +#define TX_PWR_CFG_3_MCS15             FIELD32(0x0000f000)
8017 +#define TX_PWR_CFG_3_UKNOWN1           FIELD32(0x000f0000)
8018 +#define TX_PWR_CFG_3_UKNOWN2           FIELD32(0x00f00000)
8019 +#define TX_PWR_CFG_3_UKNOWN3           FIELD32(0x0f000000)
8020 +#define TX_PWR_CFG_3_UKNOWN4           FIELD32(0xf0000000)
8021 +
8022 +/*
8023 + * TX_PWR_CFG_4:
8024 + */
8025 +#define TX_PWR_CFG_4                   0x1324
8026 +#define TX_PWR_CFG_4_UKNOWN5           FIELD32(0x0000000f)
8027 +#define TX_PWR_CFG_4_UKNOWN6           FIELD32(0x000000f0)
8028 +#define TX_PWR_CFG_4_UKNOWN7           FIELD32(0x00000f00)
8029 +#define TX_PWR_CFG_4_UKNOWN8           FIELD32(0x0000f000)
8030 +
8031 +/*
8032 + * TX_PIN_CFG:
8033 + */
8034 +#define TX_PIN_CFG                     0x1328
8035 +#define TX_PIN_CFG_PA_PE_A0_EN         FIELD32(0x00000001)
8036 +#define TX_PIN_CFG_PA_PE_G0_EN         FIELD32(0x00000002)
8037 +#define TX_PIN_CFG_PA_PE_A1_EN         FIELD32(0x00000004)
8038 +#define TX_PIN_CFG_PA_PE_G1_EN         FIELD32(0x00000008)
8039 +#define TX_PIN_CFG_PA_PE_A0_POL                FIELD32(0x00000010)
8040 +#define TX_PIN_CFG_PA_PE_G0_POL                FIELD32(0x00000020)
8041 +#define TX_PIN_CFG_PA_PE_A1_POL                FIELD32(0x00000040)
8042 +#define TX_PIN_CFG_PA_PE_G1_POL                FIELD32(0x00000080)
8043 +#define TX_PIN_CFG_LNA_PE_A0_EN                FIELD32(0x00000100)
8044 +#define TX_PIN_CFG_LNA_PE_G0_EN                FIELD32(0x00000200)
8045 +#define TX_PIN_CFG_LNA_PE_A1_EN                FIELD32(0x00000400)
8046 +#define TX_PIN_CFG_LNA_PE_G1_EN                FIELD32(0x00000800)
8047 +#define TX_PIN_CFG_LNA_PE_A0_POL       FIELD32(0x00001000)
8048 +#define TX_PIN_CFG_LNA_PE_G0_POL       FIELD32(0x00002000)
8049 +#define TX_PIN_CFG_LNA_PE_A1_POL       FIELD32(0x00004000)
8050 +#define TX_PIN_CFG_LNA_PE_G1_POL       FIELD32(0x00008000)
8051 +#define TX_PIN_CFG_RFTR_EN             FIELD32(0x00010000)
8052 +#define TX_PIN_CFG_RFTR_POL            FIELD32(0x00020000)
8053 +#define TX_PIN_CFG_TRSW_EN             FIELD32(0x00040000)
8054 +#define TX_PIN_CFG_TRSW_POL            FIELD32(0x00080000)
8055 +
8056 +/*
8057 + * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz
8058 + */
8059 +#define TX_BAND_CFG                    0x132c
8060 +#define TX_BAND_CFG_A                  FIELD32(0x00000002)
8061 +#define TX_BAND_CFG_BG                 FIELD32(0x00000004)
8062 +
8063 +/*
8064 + * TX_SW_CFG0:
8065 + */
8066 +#define TX_SW_CFG0                     0x1330
8067 +
8068 +/*
8069 + * TX_SW_CFG1:
8070 + */
8071 +#define TX_SW_CFG1                     0x1334
8072 +
8073 +/*
8074 + * TX_SW_CFG2:
8075 + */
8076 +#define TX_SW_CFG2                     0x1338
8077 +
8078 +/*
8079 + * TXOP_THRES_CFG:
8080 + */
8081 +#define TXOP_THRES_CFG                 0x133c
8082 +
8083 +/*
8084 + * TXOP_CTRL_CFG:
8085 + */
8086 +#define TXOP_CTRL_CFG                  0x1340
8087 +
8088 +/*
8089 + * TX_RTS_CFG:
8090 + * RTS_THRES: unit:byte
8091 + * RTS_FBK_EN: enable rts rate fallback
8092 + */
8093 +#define TX_RTS_CFG                     0x1344
8094 +#define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT        FIELD32(0x000000ff)
8095 +#define TX_RTS_CFG_RTS_THRES           FIELD32(0x00ffff00)
8096 +#define TX_RTS_CFG_RTS_FBK_EN          FIELD32(0x01000000)
8097 +
8098 +/*
8099 + * TX_TIMEOUT_CFG:
8100 + * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us
8101 + * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure
8102 + * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation.
8103 + *                it is recommended that:
8104 + *                (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
8105 + */
8106 +#define TX_TIMEOUT_CFG                 0x1348
8107 +#define TX_TIMEOUT_CFG_MPDU_LIFETIME   FIELD32(0x000000f0)
8108 +#define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT  FIELD32(0x0000ff00)
8109 +#define TX_TIMEOUT_CFG_TX_OP_TIMEOUT   FIELD32(0x00ff0000)
8110 +
8111 +/*
8112 + * TX_RTY_CFG:
8113 + * SHORT_RTY_LIMIT: short retry limit
8114 + * LONG_RTY_LIMIT: long retry limit
8115 + * LONG_RTY_THRE: Long retry threshoold
8116 + * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode
8117 + *                   0:expired by retry limit, 1: expired by mpdu life timer
8118 + * AGG_RTY_MODE: Aggregate MPDU retry mode
8119 + *               0:expired by retry limit, 1: expired by mpdu life timer
8120 + * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable
8121 + */
8122 +#define TX_RTY_CFG                     0x134c
8123 +#define TX_RTY_CFG_SHORT_RTY_LIMIT     FIELD32(0x000000ff)
8124 +#define TX_RTY_CFG_LONG_RTY_LIMIT      FIELD32(0x0000ff00)
8125 +#define TX_RTY_CFG_LONG_RTY_THRE       FIELD32(0x0fff0000)
8126 +#define TX_RTY_CFG_NON_AGG_RTY_MODE    FIELD32(0x10000000)
8127 +#define TX_RTY_CFG_AGG_RTY_MODE                FIELD32(0x20000000)
8128 +#define TX_RTY_CFG_TX_AUTO_FB_ENABLE   FIELD32(0x40000000)
8129 +
8130 +/*
8131 + * TX_LINK_CFG:
8132 + * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us
8133 + * MFB_ENABLE: TX apply remote MFB 1:enable
8134 + * REMOTE_UMFS_ENABLE: remote unsolicit  MFB enable
8135 + *                     0: not apply remote remote unsolicit (MFS=7)
8136 + * TX_MRQ_EN: MCS request TX enable
8137 + * TX_RDG_EN: RDG TX enable
8138 + * TX_CF_ACK_EN: Piggyback CF-ACK enable
8139 + * REMOTE_MFB: remote MCS feedback
8140 + * REMOTE_MFS: remote MCS feedback sequence number
8141 + */
8142 +#define TX_LINK_CFG                    0x1350
8143 +#define TX_LINK_CFG_REMOTE_MFB_LIFETIME        FIELD32(0x000000ff)
8144 +#define TX_LINK_CFG_MFB_ENABLE         FIELD32(0x00000100)
8145 +#define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200)
8146 +#define TX_LINK_CFG_TX_MRQ_EN          FIELD32(0x00000400)
8147 +#define TX_LINK_CFG_TX_RDG_EN          FIELD32(0x00000800)
8148 +#define TX_LINK_CFG_TX_CF_ACK_EN       FIELD32(0x00001000)
8149 +#define TX_LINK_CFG_REMOTE_MFB         FIELD32(0x00ff0000)
8150 +#define TX_LINK_CFG_REMOTE_MFS         FIELD32(0xff000000)
8151 +
8152 +/*
8153 + * HT_FBK_CFG0:
8154 + */
8155 +#define HT_FBK_CFG0                    0x1354
8156 +#define HT_FBK_CFG0_HTMCS0FBK          FIELD32(0x0000000f)
8157 +#define HT_FBK_CFG0_HTMCS1FBK          FIELD32(0x000000f0)
8158 +#define HT_FBK_CFG0_HTMCS2FBK          FIELD32(0x00000f00)
8159 +#define HT_FBK_CFG0_HTMCS3FBK          FIELD32(0x0000f000)
8160 +#define HT_FBK_CFG0_HTMCS4FBK          FIELD32(0x000f0000)
8161 +#define HT_FBK_CFG0_HTMCS5FBK          FIELD32(0x00f00000)
8162 +#define HT_FBK_CFG0_HTMCS6FBK          FIELD32(0x0f000000)
8163 +#define HT_FBK_CFG0_HTMCS7FBK          FIELD32(0xf0000000)
8164 +
8165 +/*
8166 + * HT_FBK_CFG1:
8167 + */
8168 +#define HT_FBK_CFG1                    0x1358
8169 +#define HT_FBK_CFG1_HTMCS8FBK          FIELD32(0x0000000f)
8170 +#define HT_FBK_CFG1_HTMCS9FBK          FIELD32(0x000000f0)
8171 +#define HT_FBK_CFG1_HTMCS10FBK         FIELD32(0x00000f00)
8172 +#define HT_FBK_CFG1_HTMCS11FBK         FIELD32(0x0000f000)
8173 +#define HT_FBK_CFG1_HTMCS12FBK         FIELD32(0x000f0000)
8174 +#define HT_FBK_CFG1_HTMCS13FBK         FIELD32(0x00f00000)
8175 +#define HT_FBK_CFG1_HTMCS14FBK         FIELD32(0x0f000000)
8176 +#define HT_FBK_CFG1_HTMCS15FBK         FIELD32(0xf0000000)
8177 +
8178 +/*
8179 + * LG_FBK_CFG0:
8180 + */
8181 +#define LG_FBK_CFG0                    0x135c
8182 +#define LG_FBK_CFG0_OFDMMCS0FBK                FIELD32(0x0000000f)
8183 +#define LG_FBK_CFG0_OFDMMCS1FBK                FIELD32(0x000000f0)
8184 +#define LG_FBK_CFG0_OFDMMCS2FBK                FIELD32(0x00000f00)
8185 +#define LG_FBK_CFG0_OFDMMCS3FBK                FIELD32(0x0000f000)
8186 +#define LG_FBK_CFG0_OFDMMCS4FBK                FIELD32(0x000f0000)
8187 +#define LG_FBK_CFG0_OFDMMCS5FBK                FIELD32(0x00f00000)
8188 +#define LG_FBK_CFG0_OFDMMCS6FBK                FIELD32(0x0f000000)
8189 +#define LG_FBK_CFG0_OFDMMCS7FBK                FIELD32(0xf0000000)
8190 +
8191 +/*
8192 + * LG_FBK_CFG1:
8193 + */
8194 +#define LG_FBK_CFG1                    0x1360
8195 +#define LG_FBK_CFG0_CCKMCS0FBK         FIELD32(0x0000000f)
8196 +#define LG_FBK_CFG0_CCKMCS1FBK         FIELD32(0x000000f0)
8197 +#define LG_FBK_CFG0_CCKMCS2FBK         FIELD32(0x00000f00)
8198 +#define LG_FBK_CFG0_CCKMCS3FBK         FIELD32(0x0000f000)
8199 +
8200 +/*
8201 + * CCK_PROT_CFG: CCK Protection
8202 + * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd)
8203 + * PROTECT_CTRL: Protection control frame type for CCK TX
8204 + *               0:none, 1:RTS/CTS, 2:CTS-to-self
8205 + * PROTECT_NAV: TXOP protection type for CCK TX
8206 + *              0:none, 1:ShortNAVprotect, 2:LongNAVProtect
8207 + * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow
8208 + * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow
8209 + * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow
8210 + * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow
8211 + * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow
8212 + * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow
8213 + * RTS_TH_EN: RTS threshold enable on CCK TX
8214 + */
8215 +#define CCK_PROT_CFG                   0x1364
8216 +#define CCK_PROT_CFG_PROTECT_RATE      FIELD32(0x0000ffff)
8217 +#define CCK_PROT_CFG_PROTECT_CTRL      FIELD32(0x00030000)
8218 +#define CCK_PROT_CFG_PROTECT_NAV       FIELD32(0x000c0000)
8219 +#define CCK_PROT_CFG_TX_OP_ALLOW_CCK   FIELD32(0x00100000)
8220 +#define CCK_PROT_CFG_TX_OP_ALLOW_OFDM  FIELD32(0x00200000)
8221 +#define CCK_PROT_CFG_TX_OP_ALLOW_MM20  FIELD32(0x00400000)
8222 +#define CCK_PROT_CFG_TX_OP_ALLOW_MM40  FIELD32(0x00800000)
8223 +#define CCK_PROT_CFG_TX_OP_ALLOW_GF20  FIELD32(0x01000000)
8224 +#define CCK_PROT_CFG_TX_OP_ALLOW_GF40  FIELD32(0x02000000)
8225 +#define CCK_PROT_CFG_RTS_TH_EN         FIELD32(0x04000000)
8226 +
8227 +/*
8228 + * OFDM_PROT_CFG: OFDM Protection
8229 + */
8230 +#define OFDM_PROT_CFG                  0x1368
8231 +#define OFDM_PROT_CFG_PROTECT_RATE     FIELD32(0x0000ffff)
8232 +#define OFDM_PROT_CFG_PROTECT_CTRL     FIELD32(0x00030000)
8233 +#define OFDM_PROT_CFG_PROTECT_NAV      FIELD32(0x000c0000)
8234 +#define OFDM_PROT_CFG_TX_OP_ALLOW_CCK  FIELD32(0x00100000)
8235 +#define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
8236 +#define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
8237 +#define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
8238 +#define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
8239 +#define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
8240 +#define OFDM_PROT_CFG_RTS_TH_EN                FIELD32(0x04000000)
8241 +
8242 +/*
8243 + * MM20_PROT_CFG: MM20 Protection
8244 + */
8245 +#define MM20_PROT_CFG                  0x136c
8246 +#define MM20_PROT_CFG_PROTECT_RATE     FIELD32(0x0000ffff)
8247 +#define MM20_PROT_CFG_PROTECT_CTRL     FIELD32(0x00030000)
8248 +#define MM20_PROT_CFG_PROTECT_NAV      FIELD32(0x000c0000)
8249 +#define MM20_PROT_CFG_TX_OP_ALLOW_CCK  FIELD32(0x00100000)
8250 +#define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
8251 +#define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
8252 +#define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
8253 +#define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
8254 +#define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
8255 +#define MM20_PROT_CFG_RTS_TH_EN                FIELD32(0x04000000)
8256 +
8257 +/*
8258 + * MM40_PROT_CFG: MM40 Protection
8259 + */
8260 +#define MM40_PROT_CFG                  0x1370
8261 +#define MM40_PROT_CFG_PROTECT_RATE     FIELD32(0x0000ffff)
8262 +#define MM40_PROT_CFG_PROTECT_CTRL     FIELD32(0x00030000)
8263 +#define MM40_PROT_CFG_PROTECT_NAV      FIELD32(0x000c0000)
8264 +#define MM40_PROT_CFG_TX_OP_ALLOW_CCK  FIELD32(0x00100000)
8265 +#define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
8266 +#define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
8267 +#define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
8268 +#define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
8269 +#define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
8270 +#define MM40_PROT_CFG_RTS_TH_EN                FIELD32(0x04000000)
8271 +
8272 +/*
8273 + * GF20_PROT_CFG: GF20 Protection
8274 + */
8275 +#define GF20_PROT_CFG                  0x1374
8276 +#define GF20_PROT_CFG_PROTECT_RATE     FIELD32(0x0000ffff)
8277 +#define GF20_PROT_CFG_PROTECT_CTRL     FIELD32(0x00030000)
8278 +#define GF20_PROT_CFG_PROTECT_NAV      FIELD32(0x000c0000)
8279 +#define GF20_PROT_CFG_TX_OP_ALLOW_CCK  FIELD32(0x00100000)
8280 +#define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
8281 +#define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
8282 +#define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
8283 +#define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
8284 +#define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
8285 +#define GF20_PROT_CFG_RTS_TH_EN                FIELD32(0x04000000)
8286 +
8287 +/*
8288 + * GF40_PROT_CFG: GF40 Protection
8289 + */
8290 +#define GF40_PROT_CFG                  0x1378
8291 +#define GF40_PROT_CFG_PROTECT_RATE     FIELD32(0x0000ffff)
8292 +#define GF40_PROT_CFG_PROTECT_CTRL     FIELD32(0x00030000)
8293 +#define GF40_PROT_CFG_PROTECT_NAV      FIELD32(0x000c0000)
8294 +#define GF40_PROT_CFG_TX_OP_ALLOW_CCK  FIELD32(0x00100000)
8295 +#define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
8296 +#define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
8297 +#define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
8298 +#define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
8299 +#define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
8300 +#define GF40_PROT_CFG_RTS_TH_EN                FIELD32(0x04000000)
8301 +
8302 +/*
8303 + * EXP_CTS_TIME:
8304 + */
8305 +#define EXP_CTS_TIME                   0x137c
8306 +
8307 +/*
8308 + * EXP_ACK_TIME:
8309 + */
8310 +#define EXP_ACK_TIME                   0x1380
8311 +
8312 +/*
8313 + * RX_FILTER_CFG: RX configuration register.
8314 + */
8315 +#define RX_FILTER_CFG                  0x1400
8316 +#define RX_FILTER_CFG_DROP_CRC_ERROR   FIELD32(0x00000001)
8317 +#define RX_FILTER_CFG_DROP_PHY_ERROR   FIELD32(0x00000002)
8318 +#define RX_FILTER_CFG_DROP_NOT_TO_ME   FIELD32(0x00000004)
8319 +#define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008)
8320 +#define RX_FILTER_CFG_DROP_VER_ERROR   FIELD32(0x00000010)
8321 +#define RX_FILTER_CFG_DROP_MULTICAST   FIELD32(0x00000020)
8322 +#define RX_FILTER_CFG_DROP_BROADCAST   FIELD32(0x00000040)
8323 +#define RX_FILTER_CFG_DROP_DUPLICATE   FIELD32(0x00000080)
8324 +#define RX_FILTER_CFG_DROP_CF_END_ACK  FIELD32(0x00000100)
8325 +#define RX_FILTER_CFG_DROP_CF_END      FIELD32(0x00000200)
8326 +#define RX_FILTER_CFG_DROP_ACK         FIELD32(0x00000400)
8327 +#define RX_FILTER_CFG_DROP_CTS         FIELD32(0x00000800)
8328 +#define RX_FILTER_CFG_DROP_RTS         FIELD32(0x00001000)
8329 +#define RX_FILTER_CFG_DROP_PSPOLL      FIELD32(0x00002000)
8330 +#define RX_FILTER_CFG_DROP_BA          FIELD32(0x00004000)
8331 +#define RX_FILTER_CFG_DROP_BAR         FIELD32(0x00008000)
8332 +#define RX_FILTER_CFG_DROP_CNTL                FIELD32(0x00010000)
8333 +
8334 +/*
8335 + * AUTO_RSP_CFG:
8336 + * AUTORESPONDER: 0: disable, 1: enable
8337 + * BAC_ACK_POLICY: 0:long, 1:short preamble
8338 + * CTS_40_MMODE: Response CTS 40MHz duplicate mode
8339 + * CTS_40_MREF: Response CTS 40MHz duplicate mode
8340 + * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble
8341 + * DUAL_CTS_EN: Power bit value in control frame
8342 + * ACK_CTS_PSM_BIT:Power bit value in control frame
8343 + */
8344 +#define AUTO_RSP_CFG                   0x1404
8345 +#define AUTO_RSP_CFG_AUTORESPONDER     FIELD32(0x00000001)
8346 +#define AUTO_RSP_CFG_BAC_ACK_POLICY    FIELD32(0x00000002)
8347 +#define AUTO_RSP_CFG_CTS_40_MMODE      FIELD32(0x00000004)
8348 +#define AUTO_RSP_CFG_CTS_40_MREF       FIELD32(0x00000008)
8349 +#define AUTO_RSP_CFG_AR_PREAMBLE       FIELD32(0x00000010)
8350 +#define AUTO_RSP_CFG_DUAL_CTS_EN       FIELD32(0x00000040)
8351 +#define AUTO_RSP_CFG_ACK_CTS_PSM_BIT   FIELD32(0x00000080)
8352 +
8353 +/*
8354 + * LEGACY_BASIC_RATE:
8355 + */
8356 +#define LEGACY_BASIC_RATE              0x1408
8357 +
8358 +/*
8359 + * HT_BASIC_RATE:
8360 + */
8361 +#define HT_BASIC_RATE                  0x140c
8362 +
8363 +/*
8364 + * HT_CTRL_CFG:
8365 + */
8366 +#define HT_CTRL_CFG                    0x1410
8367 +
8368 +/*
8369 + * SIFS_COST_CFG:
8370 + */
8371 +#define SIFS_COST_CFG                  0x1414
8372 +
8373 +/*
8374 + * RX_PARSER_CFG:
8375 + * Set NAV for all received frames
8376 + */
8377 +#define RX_PARSER_CFG                  0x1418
8378 +
8379 +/*
8380 + * TX_SEC_CNT0:
8381 + */
8382 +#define TX_SEC_CNT0                    0x1500
8383 +
8384 +/*
8385 + * RX_SEC_CNT0:
8386 + */
8387 +#define RX_SEC_CNT0                    0x1504
8388 +
8389 +/*
8390 + * CCMP_FC_MUTE:
8391 + */
8392 +#define CCMP_FC_MUTE                   0x1508
8393 +
8394 +/*
8395 + * TXOP_HLDR_ADDR0:
8396 + */
8397 +#define TXOP_HLDR_ADDR0                        0x1600
8398 +
8399 +/*
8400 + * TXOP_HLDR_ADDR1:
8401 + */
8402 +#define TXOP_HLDR_ADDR1                        0x1604
8403 +
8404 +/*
8405 + * TXOP_HLDR_ET:
8406 + */
8407 +#define TXOP_HLDR_ET                   0x1608
8408 +
8409 +/*
8410 + * QOS_CFPOLL_RA_DW0:
8411 + */
8412 +#define QOS_CFPOLL_RA_DW0              0x160c
8413 +
8414 +/*
8415 + * QOS_CFPOLL_RA_DW1:
8416 + */
8417 +#define QOS_CFPOLL_RA_DW1              0x1610
8418 +
8419 +/*
8420 + * QOS_CFPOLL_QC:
8421 + */
8422 +#define QOS_CFPOLL_QC                  0x1614
8423 +
8424 +/*
8425 + * RX_STA_CNT0: RX PLCP error count & RX CRC error count
8426 + */
8427 +#define RX_STA_CNT0                    0x1700
8428 +#define RX_STA_CNT0_CRC_ERR            FIELD32(0x0000ffff)
8429 +#define RX_STA_CNT0_PHY_ERR            FIELD32(0xffff0000)
8430 +
8431 +/*
8432 + * RX_STA_CNT1: RX False CCA count & RX LONG frame count
8433 + */
8434 +#define RX_STA_CNT1                    0x1704
8435 +#define RX_STA_CNT1_FALSE_CCA          FIELD32(0x0000ffff)
8436 +#define RX_STA_CNT1_PLCP_ERR           FIELD32(0xffff0000)
8437 +
8438 +/*
8439 + * RX_STA_CNT2:
8440 + */
8441 +#define RX_STA_CNT2                    0x1708
8442 +#define RX_STA_CNT2_RX_DUPLI_COUNT     FIELD32(0x0000ffff)
8443 +#define RX_STA_CNT2_RX_FIFO_OVERFLOW   FIELD32(0xffff0000)
8444 +
8445 +/*
8446 + * TX_STA_CNT0: TX Beacon count
8447 + */
8448 +#define TX_STA_CNT0                    0x170c
8449 +#define TX_STA_CNT0_TX_FAIL_COUNT      FIELD32(0x0000ffff)
8450 +#define TX_STA_CNT0_TX_BEACON_COUNT    FIELD32(0xffff0000)
8451 +
8452 +/*
8453 + * TX_STA_CNT1: TX tx count
8454 + */
8455 +#define TX_STA_CNT1                    0x1710
8456 +#define TX_STA_CNT1_TX_SUCCESS         FIELD32(0x0000ffff)
8457 +#define TX_STA_CNT1_TX_RETRANSMIT      FIELD32(0xffff0000)
8458 +
8459 +/*
8460 + * TX_STA_CNT2: TX tx count
8461 + */
8462 +#define TX_STA_CNT2                    0x1714
8463 +#define TX_STA_CNT2_TX_ZERO_LEN_COUNT  FIELD32(0x0000ffff)
8464 +#define TX_STA_CNT2_TX_UNDER_FLOW_COUNT        FIELD32(0xffff0000)
8465 +
8466 +/*
8467 + * TX_STA_FIFO: TX Result for specific PID status fifo register
8468 + */
8469 +#define TX_STA_FIFO                    0x1718
8470 +#define TX_STA_FIFO_B_VALID            FIELD32(0x00000001)
8471 +#define TX_STA_FIFO_PID_TYPE           FIELD32(0x0000001e)
8472 +#define TX_STA_FIFO_TX_SUCCESS         FIELD32(0x00000020)
8473 +#define TX_STA_FIFO_TX_AGGRE           FIELD32(0x00000040)
8474 +#define TX_STA_FIFO_TX_ACK_REQUIRED    FIELD32(0x00000080)
8475 +#define TX_STA_FIFO_WCID               FIELD32(0x0000ff00)
8476 +#define TX_STA_FIFO_SUCCESS_RATE       FIELD32(0xffff0000)
8477 +
8478 +/*
8479 + * TX_AGG_CNT: Debug counter
8480 + */
8481 +#define TX_AGG_CNT                     0x171c
8482 +#define TX_AGG_CNT_NON_AGG_TX_COUNT    FIELD32(0x0000ffff)
8483 +#define TX_AGG_CNT_AGG_TX_COUNT                FIELD32(0xffff0000)
8484 +
8485 +/*
8486 + * TX_AGG_CNT0:
8487 + */
8488 +#define TX_AGG_CNT0                    0x1720
8489 +#define TX_AGG_CNT0_AGG_SIZE_1_COUNT   FIELD32(0x0000ffff)
8490 +#define TX_AGG_CNT0_AGG_SIZE_2_COUNT   FIELD32(0xffff0000)
8491 +
8492 +/*
8493 + * TX_AGG_CNT1:
8494 + */
8495 +#define TX_AGG_CNT1                    0x1724
8496 +#define TX_AGG_CNT1_AGG_SIZE_3_COUNT   FIELD32(0x0000ffff)
8497 +#define TX_AGG_CNT1_AGG_SIZE_4_COUNT   FIELD32(0xffff0000)
8498 +
8499 +/*
8500 + * TX_AGG_CNT2:
8501 + */
8502 +#define TX_AGG_CNT2                    0x1728
8503 +#define TX_AGG_CNT2_AGG_SIZE_5_COUNT   FIELD32(0x0000ffff)
8504 +#define TX_AGG_CNT2_AGG_SIZE_6_COUNT   FIELD32(0xffff0000)
8505 +
8506 +/*
8507 + * TX_AGG_CNT3:
8508 + */
8509 +#define TX_AGG_CNT3                    0x172c
8510 +#define TX_AGG_CNT3_AGG_SIZE_7_COUNT   FIELD32(0x0000ffff)
8511 +#define TX_AGG_CNT3_AGG_SIZE_8_COUNT   FIELD32(0xffff0000)
8512 +
8513 +/*
8514 + * TX_AGG_CNT4:
8515 + */
8516 +#define TX_AGG_CNT4                    0x1730
8517 +#define TX_AGG_CNT4_AGG_SIZE_9_COUNT   FIELD32(0x0000ffff)
8518 +#define TX_AGG_CNT4_AGG_SIZE_10_COUNT  FIELD32(0xffff0000)
8519 +
8520 +/*
8521 + * TX_AGG_CNT5:
8522 + */
8523 +#define TX_AGG_CNT5                    0x1734
8524 +#define TX_AGG_CNT5_AGG_SIZE_11_COUNT  FIELD32(0x0000ffff)
8525 +#define TX_AGG_CNT5_AGG_SIZE_12_COUNT  FIELD32(0xffff0000)
8526 +
8527 +/*
8528 + * TX_AGG_CNT6:
8529 + */
8530 +#define TX_AGG_CNT6                    0x1738
8531 +#define TX_AGG_CNT6_AGG_SIZE_13_COUNT  FIELD32(0x0000ffff)
8532 +#define TX_AGG_CNT6_AGG_SIZE_14_COUNT  FIELD32(0xffff0000)
8533 +
8534 +/*
8535 + * TX_AGG_CNT7:
8536 + */
8537 +#define TX_AGG_CNT7                    0x173c
8538 +#define TX_AGG_CNT7_AGG_SIZE_15_COUNT  FIELD32(0x0000ffff)
8539 +#define TX_AGG_CNT7_AGG_SIZE_16_COUNT  FIELD32(0xffff0000)
8540 +
8541 +/*
8542 + * MPDU_DENSITY_CNT:
8543 + * TX_ZERO_DEL: TX zero length delimiter count
8544 + * RX_ZERO_DEL: RX zero length delimiter count
8545 + */
8546 +#define MPDU_DENSITY_CNT               0x1740
8547 +#define MPDU_DENSITY_CNT_TX_ZERO_DEL   FIELD32(0x0000ffff)
8548 +#define MPDU_DENSITY_CNT_RX_ZERO_DEL   FIELD32(0xffff0000)
8549 +
8550 +/*
8551 + * Security key table memory, base address = 0x1800
8552 + */
8553 +struct hw_pairwise_ta_entry {
8554 +       u8 address[6];
8555 +       u8 reserved[2];
8556 +} __attribute__ ((packed));
8557 +
8558 +struct wcid_entry {
8559 +       u8 rx_ba_bitmat7;
8560 +       u8 rx_ba_bitmat0;
8561 +       u8 mac[6];
8562 +} __attribute__ ((packed));
8563 +
8564 +struct hw_key_entry {
8565 +       u8 key[16];
8566 +       u8 tx_mic[8];
8567 +       u8 rx_mic[8];
8568 +} __attribute__ ((packed));
8569 +
8570 +/*
8571 + * Security key table memory.
8572 + * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry
8573 + * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry
8574 + * PAIRWISE_IVEIV_TABLE_BASE: 8-byte * 256-entry
8575 + * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry
8576 + * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry
8577 + * SHARED_KEY_TABLE_BASE: 32-byte * 16-entry
8578 + * SHARED_KEY_MODE_BASE: 32-byte * 16-entry
8579 + */
8580 +#define MAC_WCID_BASE                  0x1800
8581 +#define PAIRWISE_KEY_TABLE_BASE                0x4000
8582 +#define PAIRWISE_IVEIV_TABLE_BASE      0x6000
8583 +#define MAC_IVEIV_TABLE_BASE           0x6000
8584 +#define MAC_WCID_ATTRIBUTE_BASE                0x6800
8585 +#define SHARED_KEY_TABLE_BASE          0x6c00
8586 +#define SHARED_KEY_MODE_BASE           0x7000
8587 +
8588 +#define SHARED_KEY_ENTRY(__idx) \
8589 +       ( SHARED_KEY_TABLE_BASE + \
8590 +               ((__idx) * sizeof(struct hw_key_entry)) )
8591 +#define SHARED_KEY_MODE_ENTRY(__idx) \
8592 +       ( SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)) )
8593 +#define PAIRWISE_KEY_ENTRY(__idx) \
8594 +       ( PAIRWISE_KEY_TABLE_BASE + \
8595 +               ((__idx) * sizeof(struct hw_key_entry)) )
8596 +
8597 +#define MAC_WCID_ENTRY(__idx) \
8598 +       ( MAC_WCID_BASE + (2 * sizeof(u32) * (__idx)) )
8599 +#define MAC_WCID_ATTR_ENTRY(__idx) \
8600 +       ( MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)) )
8601 +
8602 +/*
8603 + * MAC_WCID_ATTRIBUTE:
8604 + * KEYTAB: 0: shared key table, 1: pairwise key table
8605 + * BSS_IDX: multipleBSS index for the WCID
8606 + */
8607 +#define MAC_WCID_ATTRIBUTE_KEYTAB      FIELD32(0x00000001)
8608 +#define MAC_WCID_ATTRIBUTE_PAIRKEY_MODE        FIELD32(0x0000000e)
8609 +#define MAC_WCID_ATTRIBUTE_BSS_IDX     FIELD32(0x00000070)
8610 +#define MAC_WCID_ATTRIBUTE_RX_WIUDF    FIELD32(0x00000380)
8611 +
8612 +/*
8613 + * SHARED_KEY_MODE:
8614 + */
8615 +#define SHARED_KEY_MODE_BSS0_KEY0      FIELD32(0x00000007)
8616 +#define SHARED_KEY_MODE_BSS0_KEY1      FIELD32(0x00000070)
8617 +#define SHARED_KEY_MODE_BSS0_KEY2      FIELD32(0x00000700)
8618 +#define SHARED_KEY_MODE_BSS0_KEY3      FIELD32(0x00007000)
8619 +#define SHARED_KEY_MODE_BSS1_KEY0      FIELD32(0x00070000)
8620 +#define SHARED_KEY_MODE_BSS1_KEY1      FIELD32(0x00700000)
8621 +#define SHARED_KEY_MODE_BSS1_KEY2      FIELD32(0x07000000)
8622 +#define SHARED_KEY_MODE_BSS1_KEY3      FIELD32(0x70000000)
8623 +
8624 +/*
8625 + * HOST-MCU communication
8626 + */
8627 +
8628 +/*
8629 + * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
8630 + */
8631 +#define H2M_MAILBOX_CSR                        0x7010
8632 +#define H2M_MAILBOX_CSR_ARG0           FIELD32(0x000000ff)
8633 +#define H2M_MAILBOX_CSR_ARG1           FIELD32(0x0000ff00)
8634 +#define H2M_MAILBOX_CSR_CMD_TOKEN      FIELD32(0x00ff0000)
8635 +#define H2M_MAILBOX_CSR_OWNER          FIELD32(0xff000000)
8636 +
8637 +/*
8638 + * H2M_MAILBOX_CID:
8639 + */
8640 +#define H2M_MAILBOX_CID                        0x7014
8641 +
8642 +/*
8643 + * H2M_MAILBOX_STATUS:
8644 + */
8645 +#define H2M_MAILBOX_STATUS             0x701c
8646 +
8647 +/*
8648 + * H2M_INT_SRC:
8649 + */
8650 +#define H2M_INT_SRC                    0x7024
8651 +
8652 +/*
8653 + * H2M_BBP_AGENT:
8654 + */
8655 +#define H2M_BBP_AGENT                  0x7028
8656 +
8657 +/*
8658 + * MCU_LEDCS: LED control for MCU Mailbox.
8659 + */
8660 +#define MCU_LEDCS_LED_MODE             FIELD8(0x1f)
8661 +#define MCU_LEDCS_POLARITY             FIELD8(0x01)
8662 +
8663 +/*
8664 + * HW_CS_CTS_BASE:
8665 + * Carrier-sense CTS frame base address.
8666 + * It's where mac stores carrier-sense frame for carrier-sense function.
8667 + */
8668 +#define HW_CS_CTS_BASE                 0x7700
8669 +
8670 +/*
8671 + * HW_DFS_CTS_BASE:
8672 + * FS CTS frame base address. It's where mac stores CTS frame for DFS.
8673 + */
8674 +#define HW_DFS_CTS_BASE                        0x7780
8675 +
8676 +/*
8677 + * TXRX control registers - base address 0x3000
8678 + */
8679 +
8680 +/*
8681 + * TXRX_CSR1:
8682 + * rt2860b  UNKNOWN reg use R/O Reg Addr 0x77d0 first..
8683 + */
8684 +#define TXRX_CSR1                      0x77d0
8685 +
8686 +/*
8687 + * HW_DEBUG_SETTING_BASE:
8688 + * since NULL frame won't be that long (256 byte)
8689 + * We steal 16 tail bytes to save debugging settings
8690 + */
8691 +#define HW_DEBUG_SETTING_BASE          0x77f0
8692 +#define HW_DEBUG_SETTING_BASE2         0x7770
8693 +
8694 +/*
8695 + * HW_BEACON_BASE
8696 + * In order to support maximum 8 MBSS and its maximum length
8697 + *     is 512 bytes for each beacon
8698 + * Three section discontinue memory segments will be used.
8699 + * 1. The original region for BCN 0~3
8700 + * 2. Extract memory from FCE table for BCN 4~5
8701 + * 3. Extract memory from Pair-wise key table for BCN 6~7
8702 + *    It occupied those memory of wcid 238~253 for BCN 6
8703 + *    and wcid 222~237 for BCN 7
8704 + *
8705 + * IMPORTANT NOTE: Not sure why legacy driver does this,
8706 + * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6.
8707 + */
8708 +#define HW_BEACON_BASE0                        0x7800
8709 +#define HW_BEACON_BASE1                        0x7a00
8710 +#define HW_BEACON_BASE2                        0x7c00
8711 +#define HW_BEACON_BASE3                        0x7e00
8712 +#define HW_BEACON_BASE4                        0x7200
8713 +#define HW_BEACON_BASE5                        0x7400
8714 +#define HW_BEACON_BASE6                        0x5dc0
8715 +#define HW_BEACON_BASE7                        0x5bc0
8716 +
8717 +#define HW_BEACON_OFFSET(__index) \
8718 +       ( ((__index) < 4) ? ( HW_BEACON_BASE0 + (__index * 0x0200) ) : \
8719 +         (((__index) < 6) ? ( HW_BEACON_BASE4 + ((__index - 4) * 0x0200) ) : \
8720 +         (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))) )
8721 +
8722 +/*
8723 + * 8051 firmware image.
8724 + */
8725 +#define FIRMWARE_RT2870                        "rt2870.bin"
8726 +#define FIRMWARE_IMAGE_BASE            0x3000
8727 +
8728 +/*
8729 + * BBP registers.
8730 + * The wordsize of the BBP is 8 bits.
8731 + */
8732 +
8733 +/*
8734 + * BBP 1: TX Antenna
8735 + */
8736 +#define BBP1_TX_POWER                  FIELD8(0x07)
8737 +#define BBP1_TX_ANTENNA                        FIELD8(0x18)
8738 +
8739 +/*
8740 + * BBP 3: RX Antenna
8741 + */
8742 +#define BBP3_RX_ANTENNA                        FIELD8(0x18)
8743 +
8744 +/*
8745 + * RF registers
8746 + */
8747 +
8748 +/*
8749 + * RF 2
8750 + */
8751 +#define RF2_ANTENNA_RX2                        FIELD32(0x00000040)
8752 +#define RF2_ANTENNA_TX1                        FIELD32(0x00004000)
8753 +#define RF2_ANTENNA_RX1                        FIELD32(0x00020000)
8754 +
8755 +/*
8756 + * RF 3
8757 + */
8758 +#define RF3_TXPOWER_G                  FIELD32(0x00003e00)
8759 +#define RF3_TXPOWER_A_7DBM_BOOST       FIELD32(0x00000200)
8760 +#define RF3_TXPOWER_A                  FIELD32(0x00003c00)
8761 +
8762 +/*
8763 + * RF 4
8764 + */
8765 +#define RF4_TXPOWER_G                  FIELD32(0x000007c0)
8766 +#define RF4_TXPOWER_A_7DBM_BOOST       FIELD32(0x00000040)
8767 +#define RF4_TXPOWER_A                  FIELD32(0x00000780)
8768 +#define RF4_FREQ_OFFSET                        FIELD32(0x001f8000)
8769 +#define RF4_BW40                       FIELD32(0x00200000)
8770 +
8771 +/*
8772 + * EEPROM content.
8773 + * The wordsize of the EEPROM is 16 bits.
8774 + */
8775 +
8776 +/*
8777 + * EEPROM Version
8778 + */
8779 +#define EEPROM_VERSION                 0x0001
8780 +#define EEPROM_VERSION_FAE             FIELD16(0x00ff)
8781 +#define EEPROM_VERSION_VERSION         FIELD16(0xff00)
8782 +
8783 +/*
8784 + * HW MAC address.
8785 + */
8786 +#define EEPROM_MAC_ADDR_0              0x0002
8787 +#define EEPROM_MAC_ADDR_BYTE0          FIELD16(0x00ff)
8788 +#define EEPROM_MAC_ADDR_BYTE1          FIELD16(0xff00)
8789 +#define EEPROM_MAC_ADDR1               0x0003
8790 +#define EEPROM_MAC_ADDR_BYTE2          FIELD16(0x00ff)
8791 +#define EEPROM_MAC_ADDR_BYTE3          FIELD16(0xff00)
8792 +#define EEPROM_MAC_ADDR_2              0x0004
8793 +#define EEPROM_MAC_ADDR_BYTE4          FIELD16(0x00ff)
8794 +#define EEPROM_MAC_ADDR_BYTE5          FIELD16(0xff00)
8795 +
8796 +/*
8797 + * EEPROM ANTENNA config
8798 + * RXPATH: 1: 1R, 2: 2R, 3: 3R
8799 + * TXPATH: 1: 1T, 2: 2T
8800 + */
8801 +#define        EEPROM_ANTENNA                  0x001a
8802 +#define EEPROM_ANTENNA_RXPATH          FIELD16(0x000f)
8803 +#define EEPROM_ANTENNA_TXPATH          FIELD16(0x00f0)
8804 +#define EEPROM_ANTENNA_RF_TYPE         FIELD16(0x0f00)
8805 +
8806 +/*
8807 + * EEPROM NIC config
8808 + * CARDBUS_ACCEL: 0 - enable, 1 - disable
8809 + */
8810 +#define        EEPROM_NIC                      0x001b
8811 +#define EEPROM_NIC_HW_RADIO            FIELD16(0x0001)
8812 +#define EEPROM_NIC_DYNAMIC_TX_AGC      FIELD16(0x0002)
8813 +#define EEPROM_NIC_EXTERNAL_LNA_BG     FIELD16(0x0004)
8814 +#define EEPROM_NIC_EXTERNAL_LNA_A      FIELD16(0x0008)
8815 +#define EEPROM_NIC_CARDBUS_ACCEL       FIELD16(0x0010)
8816 +#define EEPROM_NIC_BW40M_SB_BG         FIELD16(0x0020)
8817 +#define EEPROM_NIC_BW40M_SB_A          FIELD16(0x0040)
8818 +#define EEPROM_NIC_WPS_PBC             FIELD16(0x0080)
8819 +#define EEPROM_NIC_BW40M_BG            FIELD16(0x0100)
8820 +#define EEPROM_NIC_BW40M_A             FIELD16(0x0200)
8821 +
8822 +/*
8823 + * EEPROM frequency
8824 + */
8825 +#define        EEPROM_FREQ                     0x001d
8826 +#define EEPROM_FREQ_OFFSET             FIELD16(0x00ff)
8827 +#define EEPROM_FREQ_LED_MODE           FIELD16(0x7f00)
8828 +#define EEPROM_FREQ_LED_POLARITY       FIELD16(0x1000)
8829 +
8830 +/*
8831 + * EEPROM LED
8832 + * POLARITY_RDY_G: Polarity RDY_G setting.
8833 + * POLARITY_RDY_A: Polarity RDY_A setting.
8834 + * POLARITY_ACT: Polarity ACT setting.
8835 + * POLARITY_GPIO_0: Polarity GPIO0 setting.
8836 + * POLARITY_GPIO_1: Polarity GPIO1 setting.
8837 + * POLARITY_GPIO_2: Polarity GPIO2 setting.
8838 + * POLARITY_GPIO_3: Polarity GPIO3 setting.
8839 + * POLARITY_GPIO_4: Polarity GPIO4 setting.
8840 + * LED_MODE: Led mode.
8841 + */
8842 +#define EEPROM_LED1                    0x001e
8843 +#define EEPROM_LED2                    0x001f
8844 +#define EEPROM_LED3                    0x0020
8845 +#define EEPROM_LED_POLARITY_RDY_BG     FIELD16(0x0001)
8846 +#define EEPROM_LED_POLARITY_RDY_A      FIELD16(0x0002)
8847 +#define EEPROM_LED_POLARITY_ACT                FIELD16(0x0004)
8848 +#define EEPROM_LED_POLARITY_GPIO_0     FIELD16(0x0008)
8849 +#define EEPROM_LED_POLARITY_GPIO_1     FIELD16(0x0010)
8850 +#define EEPROM_LED_POLARITY_GPIO_2     FIELD16(0x0020)
8851 +#define EEPROM_LED_POLARITY_GPIO_3     FIELD16(0x0040)
8852 +#define EEPROM_LED_POLARITY_GPIO_4     FIELD16(0x0080)
8853 +#define EEPROM_LED_LED_MODE            FIELD16(0x1f00)
8854 +
8855 +/*
8856 + * EEPROM LNA
8857 + */
8858 +#define EEPROM_LNA                     0x0022
8859 +#define EEPROM_LNA_BG                  FIELD16(0x00ff)
8860 +#define EEPROM_LNA_A0                  FIELD16(0xff00)
8861 +
8862 +/*
8863 + * EEPROM RSSI BG offset
8864 + */
8865 +#define EEPROM_RSSI_BG                 0x0023
8866 +#define EEPROM_RSSI_BG_OFFSET0         FIELD16(0x00ff)
8867 +#define EEPROM_RSSI_BG_OFFSET1         FIELD16(0xff00)
8868 +
8869 +/*
8870 + * EEPROM RSSI BG2 offset
8871 + */
8872 +#define EEPROM_RSSI_BG2                        0x0024
8873 +#define EEPROM_RSSI_BG2_OFFSET2                FIELD16(0x00ff)
8874 +#define EEPROM_RSSI_BG2_LNA_A1         FIELD16(0xff00)
8875 +
8876 +/*
8877 + * EEPROM RSSI A offset
8878 + */
8879 +#define EEPROM_RSSI_A                  0x0025
8880 +#define EEPROM_RSSI_A_OFFSET0          FIELD16(0x00ff)
8881 +#define EEPROM_RSSI_A_OFFSET1          FIELD16(0xff00)
8882 +
8883 +/*
8884 + * EEPROM RSSI A2 offset
8885 + */
8886 +#define EEPROM_RSSI_A2                 0x0026
8887 +#define EEPROM_RSSI_A2_OFFSET2         FIELD16(0x00ff)
8888 +#define EEPROM_RSSI_A2_LNA_A2          FIELD16(0xff00)
8889 +
8890 +/*
8891 + * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power.
8892 + *     This is delta in 40MHZ.
8893 + * VALUE: Tx Power dalta value (MAX=4)
8894 + * TYPE: 1: Plus the delta value, 0: minus the delta value
8895 + * TXPOWER: Enable:
8896 + */
8897 +#define EEPROM_TXPOWER_DELTA           0x0028
8898 +#define EEPROM_TXPOWER_DELTA_VALUE     FIELD16(0x003f)
8899 +#define EEPROM_TXPOWER_DELTA_TYPE      FIELD16(0x0040)
8900 +#define EEPROM_TXPOWER_DELTA_TXPOWER   FIELD16(0x0080)
8901 +
8902 +/*
8903 + * EEPROM TXPOWER 802.11BG
8904 + */
8905 +#define        EEPROM_TXPOWER_BG1              0x0029
8906 +#define        EEPROM_TXPOWER_BG2              0x0030
8907 +#define EEPROM_TXPOWER_BG_SIZE         7
8908 +#define EEPROM_TXPOWER_BG_1            FIELD16(0x00ff)
8909 +#define EEPROM_TXPOWER_BG_2            FIELD16(0xff00)
8910 +
8911 +/*
8912 + * EEPROM TXPOWER 802.11A
8913 + */
8914 +#define EEPROM_TXPOWER_A1              0x003c
8915 +#define EEPROM_TXPOWER_A2              0x0053
8916 +#define EEPROM_TXPOWER_A_SIZE          6
8917 +#define EEPROM_TXPOWER_A_1             FIELD16(0x00ff)
8918 +#define EEPROM_TXPOWER_A_2             FIELD16(0xff00)
8919 +
8920 +/*
8921 + * EEPROM TXpower byrate: 20MHZ power
8922 + */
8923 +#define EEPROM_TXPOWER_BYRATE          0x006f
8924 +
8925 +/*
8926 + * EEPROM BBP.
8927 + */
8928 +#define        EEPROM_BBP_START                0x0078
8929 +#define EEPROM_BBP_SIZE                        16
8930 +#define EEPROM_BBP_VALUE               FIELD16(0x00ff)
8931 +#define EEPROM_BBP_REG_ID              FIELD16(0xff00)
8932 +
8933 +/*
8934 + * MCU mailbox commands.
8935 + */
8936 +#define MCU_SLEEP                      0x30
8937 +#define MCU_WAKEUP                     0x31
8938 +#define MCU_LED                                0x50
8939 +#define MCU_LED_STRENGTH               0x51
8940 +#define MCU_LED_1                      0x52
8941 +#define MCU_LED_2                      0x53
8942 +#define MCU_LED_3                      0x54
8943 +#define MCU_RADAR                      0x60
8944 +#define MCU_BOOT_SIGNAL                        0x72
8945 +
8946 +/*
8947 + * DMA descriptor defines.
8948 + */
8949 +#define TXD_DESC_SIZE                  ( 4 * sizeof(__le32) )
8950 +#define TXINFO_DESC_SIZE               ( 1 * sizeof(__le32) )
8951 +#define TXWI_DESC_SIZE                 ( 4 * sizeof(__le32) )
8952 +#define RXD_DESC_SIZE                  ( 1 * sizeof(__le32) )
8953 +#define RXWI_DESC_SIZE                 ( 4 * sizeof(__le32) )
8954 +
8955 +/*
8956 + * TX descriptor format for TX, PRIO and Beacon Ring.
8957 + */
8958 +
8959 +/*
8960 + * Word0
8961 + */
8962 +#define TXD_W0_SD_PTR0                 FIELD32(0xffffffff)
8963 +
8964 +/*
8965 + * Word1
8966 + */
8967 +#define TXD_W1_SD_LEN1                 FIELD32(0x00003fff)
8968 +#define TXD_W1_LAST_SEC1               FIELD32(0x00004000)
8969 +#define TXD_W1_BURST                   FIELD32(0x00008000)
8970 +#define TXD_W1_SD_LEN0                 FIELD32(0x3fff0000)
8971 +#define TXD_W1_LAST_SEC0               FIELD32(0x40000000)
8972 +#define TXD_W1_DMA_DONE                        FIELD32(0x80000000)
8973 +
8974 +/*
8975 + * Word2
8976 + */
8977 +#define TXD_W2_SD_PTR1                 FIELD32(0xffffffff)
8978 +
8979 +/*
8980 + * Word3
8981 + * WIV: Wireless Info Valid. 1: Driver filled WI,  0: DMA needs to copy WI
8982 + * QSEL: Select on-chip FIFO ID for 2nd-stage output scheduler.
8983 + *       0:MGMT, 1:HCCA 2:EDCA
8984 + */
8985 +#define TXD_W3_WIV                     FIELD32(0x01000000)
8986 +#define TXD_W3_QSEL                    FIELD32(0x06000000)
8987 +#define TXD_W3_TCO                     FIELD32(0x20000000)
8988 +#define TXD_W3_UCO                     FIELD32(0x40000000)
8989 +#define TXD_W3_ICO                     FIELD32(0x80000000)
8990 +
8991 +/*
8992 + * TX Info structure
8993 + */
8994 +
8995 +/*
8996 + * Word0
8997 + * WIV: Wireless Info Valid. 1: Driver filled WI,  0: DMA needs to copy WI
8998 + * QSEL: Select on-chip FIFO ID for 2nd-stage output scheduler.
8999 + *       0:MGMT, 1:HCCA 2:EDCA
9000 + * USB_DMA_NEXT_VALID: Used ONLY in USB bulk Aggregation, NextValid
9001 + * DMA_TX_BURST: used ONLY in USB bulk Aggregation.
9002 + *               Force USB DMA transmit frame from current selected endpoint
9003 + */
9004 +#define TXINFO_W0_USB_DMA_TX_PKT_LEN   FIELD32(0x0000ffff)
9005 +#define TXINFO_W0_WIV                  FIELD32(0x01000000)
9006 +#define TXINFO_W0_QSEL                 FIELD32(0x06000000)
9007 +#define TXINFO_W0_USB_DMA_NEXT_VALID   FIELD32(0x40000000)
9008 +#define TXINFO_W0_USB_DMA_TX_BURST     FIELD32(0x80000000)
9009 +
9010 +/*
9011 + * TX WI structure
9012 + */
9013 +
9014 +/*
9015 + * Word0
9016 + * FRAG: 1 To inform TKIP engine this is a fragment.
9017 + * MIMO_PS: The remote peer is in dynamic MIMO-PS mode
9018 + * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs
9019 + * BW: Channel bandwidth 20MHz or 40 MHz
9020 + * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED
9021 + */
9022 +#define TXWI_W0_FRAG                   FIELD32(0x00000001)
9023 +#define TXWI_W0_MIMO_PS                        FIELD32(0x00000002)
9024 +#define TXWI_W0_CF_ACK                 FIELD32(0x00000004)
9025 +#define TXWI_W0_TS                     FIELD32(0x00000008)
9026 +#define TXWI_W0_AMPDU                  FIELD32(0x00000010)
9027 +#define TXWI_W0_MPDU_DENSITY           FIELD32(0x000000e0)
9028 +#define TXWI_W0_TX_OP                  FIELD32(0x00000300)
9029 +#define TXWI_W0_MCS                    FIELD32(0x007f0000)
9030 +#define TXWI_W0_BW                     FIELD32(0x00800000)
9031 +#define TXWI_W0_SHORT_GI               FIELD32(0x01000000)
9032 +#define TXWI_W0_STBC                   FIELD32(0x06000000)
9033 +#define TXWI_W0_IFS                    FIELD32(0x08000000)
9034 +#define TXWI_W0_PHYMODE                        FIELD32(0xc0000000)
9035 +
9036 +/*
9037 + * Word1
9038 + */
9039 +#define TXWI_W1_ACK                    FIELD32(0x00000001)
9040 +#define TXWI_W1_NSEQ                   FIELD32(0x00000002)
9041 +#define TXWI_W1_BW_WIN_SIZE            FIELD32(0x000000fc)
9042 +#define TXWI_W1_WIRELESS_CLI_ID                FIELD32(0x0000ff00)
9043 +#define TXWI_W1_MPDU_TOTAL_BYTE_COUNT  FIELD32(0x0fff0000)
9044 +#define TXWI_W1_PACKETID               FIELD32(0xf0000000)
9045 +
9046 +/*
9047 + * Word2
9048 + */
9049 +#define TXWI_W2_IV                     FIELD32(0xffffffff)
9050 +
9051 +/*
9052 + * Word3
9053 + */
9054 +#define TXWI_W3_EIV                    FIELD32(0xffffffff)
9055 +
9056 +/*
9057 + * RX descriptor format for RX Ring.
9058 + */
9059 +
9060 +/*
9061 + * Word0
9062 + * UNICAST_TO_ME: This RX frame is unicast to me.
9063 + * MULTICAST: This is a multicast frame.
9064 + * BROADCAST: This is a broadcast frame.
9065 + * MY_BSS: this frame belongs to the same BSSID.
9066 + * CRC_ERROR: CRC error.
9067 + * CIPHER_ERROR: 0: decryption okay, 1:ICV error, 2:MIC error, 3:KEY not valid.
9068 + * AMSDU: rx with 802.3 header, not 802.11 header.
9069 + */
9070 +
9071 +#define RXD_W0_BA                      FIELD32(0x00000001)
9072 +#define RXD_W0_DATA                    FIELD32(0x00000002)
9073 +#define RXD_W0_NULLDATA                        FIELD32(0x00000004)
9074 +#define RXD_W0_FRAG                    FIELD32(0x00000008)
9075 +#define RXD_W0_UNICAST_TO_ME           FIELD32(0x00000010)
9076 +#define RXD_W0_MULTICAST               FIELD32(0x00000020)
9077 +#define RXD_W0_BROADCAST               FIELD32(0x00000040)
9078 +#define RXD_W0_MY_BSS                  FIELD32(0x00000080)
9079 +#define RXD_W0_CRC_ERROR               FIELD32(0x00000100)
9080 +#define RXD_W0_CIPHER_ERROR            FIELD32(0x00000600)
9081 +#define RXD_W0_AMSDU                   FIELD32(0x00000800)
9082 +#define RXD_W0_HTC                     FIELD32(0x00001000)
9083 +#define RXD_W0_RSSI                    FIELD32(0x00002000)
9084 +#define RXD_W0_L2PAD                   FIELD32(0x00004000)
9085 +#define RXD_W0_AMPDU                   FIELD32(0x00008000)
9086 +#define RXD_W0_DECRYPTED               FIELD32(0x00010000)
9087 +#define RXD_W0_PLCP_RSSI               FIELD32(0x00020000)
9088 +#define RXD_W0_CIPHER_ALG              FIELD32(0x00040000)
9089 +#define RXD_W0_LAST_AMSDU              FIELD32(0x00080000)
9090 +#define RXD_W0_PLCP_SIGNAL             FIELD32(0xfff00000)
9091 +
9092 +/*
9093 + * RX WI structure
9094 + */
9095 +
9096 +/*
9097 + * Word0
9098 + */
9099 +#define RXWI_W0_WIRELESS_CLI_ID                FIELD32(0x000000ff)
9100 +#define RXWI_W0_KEY_INDEX              FIELD32(0x00000300)
9101 +#define RXWI_W0_BSSID                  FIELD32(0x00001c00)
9102 +#define RXWI_W0_UDF                    FIELD32(0x0000e000)
9103 +#define RXWI_W0_MPDU_TOTAL_BYTE_COUNT  FIELD32(0x0fff0000)
9104 +#define RXWI_W0_TID                    FIELD32(0xf0000000)
9105 +
9106 +/*
9107 + * Word1
9108 + */
9109 +#define RXWI_W1_FRAG                   FIELD32(0x0000000f)
9110 +#define RXWI_W1_SEQUENCE               FIELD32(0x0000fff0)
9111 +#define RXWI_W1_MCS                    FIELD32(0x007f0000)
9112 +#define RXWI_W1_BW                     FIELD32(0x00800000)
9113 +#define RXWI_W1_SHORT_GI               FIELD32(0x01000000)
9114 +#define RXWI_W1_STBC                   FIELD32(0x06000000)
9115 +#define RXWI_W1_PHYMODE                        FIELD32(0xc0000000)
9116 +
9117 +/*
9118 + * Word2
9119 + */
9120 +#define RXWI_W2_RSSI0                  FIELD32(0x000000ff)
9121 +#define RXWI_W2_RSSI1                  FIELD32(0x0000ff00)
9122 +#define RXWI_W2_RSSI2                  FIELD32(0x00ff0000)
9123 +
9124 +/*
9125 + * Word3
9126 + */
9127 +#define RXWI_W3_SNR0                   FIELD32(0x000000ff)
9128 +#define RXWI_W3_SNR1                   FIELD32(0x0000ff00)
9129 +
9130 +/*
9131 + * Macro's for converting txpower from EEPROM to mac80211 value
9132 + * and from mac80211 value to register value.
9133 + */
9134 +#define MIN_G_TXPOWER  0
9135 +#define MIN_A_TXPOWER  -7
9136 +#define MAX_G_TXPOWER  31
9137 +#define MAX_A_TXPOWER  15
9138 +#define DEFAULT_TXPOWER        5
9139 +
9140 +#define TXPOWER_G_FROM_DEV(__txpower) \
9141 +       ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
9142 +
9143 +#define TXPOWER_G_TO_DEV(__txpower) \
9144 +       clamp_t(char, __txpower, MIN_G_TXPOWER, MAX_G_TXPOWER)
9145 +
9146 +#define TXPOWER_A_FROM_DEV(__txpower) \
9147 +       ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
9148 +
9149 +#define TXPOWER_A_TO_DEV(__txpower) \
9150 +       clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER)
9151 +
9152 +#endif /* RT2800USB_H */
9153 --- a/drivers/net/wireless/rt2x00/rt2x00.h
9154 +++ b/drivers/net/wireless/rt2x00/rt2x00.h
9155 @@ -97,6 +97,7 @@
9156   */
9157  #define ACK_SIZE               14
9158  #define IEEE80211_HEADER       24
9159 +#define AGGREGATION_SIZE       3840
9160  #define PLCP                   48
9161  #define BEACON                 100
9162  #define PREAMBLE               144
9163 @@ -127,6 +128,11 @@ struct rt2x00_chip {
9164  #define RT2561         0x0302
9165  #define RT2661         0x0401
9166  #define RT2571         0x1300
9167 +#define RT2860         0x0601  /* 2.4GHz PCI/CB */
9168 +#define RT2860D                0x0681  /* 2.4GHz, 5GHz PCI/CB */
9169 +#define RT2890         0x0701  /* 2.4GHz PCIe */
9170 +#define RT2890D                0x0781  /* 2.4GHz, 5GHz PCIe */
9171 +#define RT2870         0x1600
9172
9173         u16 rf;
9174         u32 rev;
9175 --- a/drivers/net/wireless/rt2x00/rt2x00dev.c
9176 +++ b/drivers/net/wireless/rt2x00/rt2x00dev.c
9177 @@ -658,7 +658,9 @@ void rt2x00lib_rxdone(struct rt2x00_dev
9178                 if (((rxdesc.dev_flags & RXDONE_SIGNAL_PLCP) &&
9179                      (rate->plcp == rxdesc.signal)) ||
9180                     ((rxdesc.dev_flags & RXDONE_SIGNAL_BITRATE) &&
9181 -                     (rate->bitrate == rxdesc.signal))) {
9182 +                     (rate->bitrate == rxdesc.signal)) ||
9183 +                   ((rxdesc.dev_flags & RXDONE_SIGNAL_MCS) &&
9184 +                     (rate->mcs == rxdesc.signal))) {
9185                         idx = i;
9186                         break;
9187                 }
9188 @@ -690,6 +692,7 @@ void rt2x00lib_rxdone(struct rt2x00_dev
9189         rx_status->qual =
9190             rt2x00lib_calculate_link_signal(rt2x00dev, rxdesc.rssi);
9191         rx_status->signal = rxdesc.rssi;
9192 +       rx_status->noise = rxdesc.noise;
9193         rx_status->flag = rxdesc.flags;
9194         rx_status->antenna = rt2x00dev->link.ant.active.rx;
9195
9196 @@ -721,72 +724,84 @@ const struct rt2x00_rate rt2x00_supporte
9197                 .bitrate = 10,
9198                 .ratemask = BIT(0),
9199                 .plcp = 0x00,
9200 +               .mcs = RATE_MCS(RATE_MODE_CCK, 0),
9201         },
9202         {
9203                 .flags = DEV_RATE_CCK | DEV_RATE_SHORT_PREAMBLE | DEV_RATE_BASIC,
9204                 .bitrate = 20,
9205                 .ratemask = BIT(1),
9206                 .plcp = 0x01,
9207 +               .mcs = RATE_MCS(RATE_MODE_CCK, 1),
9208         },
9209         {
9210                 .flags = DEV_RATE_CCK | DEV_RATE_SHORT_PREAMBLE | DEV_RATE_BASIC,
9211                 .bitrate = 55,
9212                 .ratemask = BIT(2),
9213                 .plcp = 0x02,
9214 +               .mcs = RATE_MCS(RATE_MODE_CCK, 2),
9215         },
9216         {
9217                 .flags = DEV_RATE_CCK | DEV_RATE_SHORT_PREAMBLE | DEV_RATE_BASIC,
9218                 .bitrate = 110,
9219                 .ratemask = BIT(3),
9220                 .plcp = 0x03,
9221 +               .mcs = RATE_MCS(RATE_MODE_CCK, 3),
9222         },
9223         {
9224                 .flags = DEV_RATE_OFDM | DEV_RATE_BASIC,
9225                 .bitrate = 60,
9226                 .ratemask = BIT(4),
9227                 .plcp = 0x0b,
9228 +               .mcs = RATE_MCS(RATE_MODE_OFDM, 0),
9229         },
9230         {
9231                 .flags = DEV_RATE_OFDM,
9232                 .bitrate = 90,
9233                 .ratemask = BIT(5),
9234                 .plcp = 0x0f,
9235 +               .mcs = RATE_MCS(RATE_MODE_OFDM, 1),
9236         },
9237         {
9238                 .flags = DEV_RATE_OFDM | DEV_RATE_BASIC,
9239                 .bitrate = 120,
9240                 .ratemask = BIT(6),
9241                 .plcp = 0x0a,
9242 +               .mcs = RATE_MCS(RATE_MODE_OFDM, 2),
9243         },
9244         {
9245                 .flags = DEV_RATE_OFDM,
9246                 .bitrate = 180,
9247                 .ratemask = BIT(7),
9248                 .plcp = 0x0e,
9249 +               .mcs = RATE_MCS(RATE_MODE_OFDM, 3),
9250         },
9251         {
9252                 .flags = DEV_RATE_OFDM | DEV_RATE_BASIC,
9253                 .bitrate = 240,
9254                 .ratemask = BIT(8),
9255                 .plcp = 0x09,
9256 +               .mcs = RATE_MCS(RATE_MODE_OFDM, 4),
9257         },
9258         {
9259                 .flags = DEV_RATE_OFDM,
9260                 .bitrate = 360,
9261                 .ratemask = BIT(9),
9262                 .plcp = 0x0d,
9263 +               .mcs = RATE_MCS(RATE_MODE_OFDM, 5),
9264         },
9265         {
9266                 .flags = DEV_RATE_OFDM,
9267                 .bitrate = 480,
9268                 .ratemask = BIT(10),
9269                 .plcp = 0x08,
9270 +               .mcs = RATE_MCS(RATE_MODE_OFDM, 6),
9271         },
9272         {
9273                 .flags = DEV_RATE_OFDM,
9274                 .bitrate = 540,
9275                 .ratemask = BIT(11),
9276                 .plcp = 0x0c,
9277 +               .mcs = RATE_MCS(RATE_MODE_OFDM, 7),
9278         },
9279  };
9280
9281 --- a/drivers/net/wireless/rt2x00/rt2x00lib.h
9282 +++ b/drivers/net/wireless/rt2x00/rt2x00lib.h
9283 @@ -49,6 +49,7 @@ struct rt2x00_rate {
9284         unsigned short ratemask;
9285
9286         unsigned short plcp;
9287 +       unsigned short mcs;
9288  };
9289
9290  extern const struct rt2x00_rate rt2x00_supported_rates[12];
9291 @@ -69,6 +70,9 @@ static inline int rt2x00_get_rate_preamb
9292         return (hw_value & 0xff00);
9293  }
9294
9295 +#define RATE_MCS(__mode, __mcs) \
9296 +       ( (((__mode) & 0x00ff) << 8) | ((__mcs) & 0x00ff) )
9297 +
9298  /*
9299   * Radio control handlers.
9300   */
9301 --- a/drivers/net/wireless/rt2x00/rt2x00queue.c
9302 +++ b/drivers/net/wireless/rt2x00/rt2x00queue.c
9303 @@ -303,6 +303,19 @@ static void rt2x00queue_create_tx_descri
9304         }
9305
9306         /*
9307 +        * Check HT properties for this frame.
9308 +        */
9309 +       if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
9310 +               __set_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags);
9311 +       if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ)
9312 +               __set_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags);
9313 +
9314 +       txdesc->ba_size = 0; /* FIXME: What value is needed? */
9315 +       txdesc->mpdu_density = 0; /* FIXME: What value is needed? */
9316 +       txdesc->stbc = 0;
9317 +       txdesc->mcs = 33; /* Let hardware handle this */
9318 +
9319 +       /*
9320          * PLCP setup
9321          * Length calculation depends on OFDM/CCK rate.
9322          */
9323 @@ -342,6 +355,20 @@ static void rt2x00queue_create_tx_descri
9324                 if (rt2x00_get_rate_preamble(rate->hw_value))
9325                         txdesc->signal |= 0x08;
9326         }
9327 +
9328 +       /*
9329 +        * Determine CCK/OFDM/HT rate mode
9330 +        */
9331 +       txdesc->rate_mode = TXRATE_MODE_CCK;
9332 +       if (hwrate->flags & DEV_RATE_OFDM)
9333 +               txdesc->rate_mode = TXRATE_MODE_OFDM;
9334 +       if (tx_info->control.rates[0].flags & IEEE80211_TX_RC_MCS)
9335 +               txdesc->rate_mode = TXRATE_MODE_HTMIX;
9336 +       if (tx_info->control.rates[0].flags & IEEE80211_TX_RC_GREEN_FIELD)
9337 +               txdesc->rate_mode = TXRATE_MODE_GREENFIELD;
9338 +
9339 +       if (tx_info->control.rates[0].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
9340 +               __set_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags);
9341  }
9342
9343  static void rt2x00queue_write_tx_descriptor(struct queue_entry *entry,
9344 --- a/drivers/net/wireless/rt2x00/rt2x00queue.h
9345 +++ b/drivers/net/wireless/rt2x00/rt2x00queue.h
9346 @@ -147,12 +147,14 @@ static inline struct skb_frame_desc* get
9347   *
9348   * @RXDONE_SIGNAL_PLCP: Signal field contains the plcp value.
9349   * @RXDONE_SIGNAL_BITRATE: Signal field contains the bitrate value.
9350 + * @RXDONE_SIGNAL_MCS: Signal field contains the mcs value.
9351   * @RXDONE_MY_BSS: Does this frame originate from device's BSS.
9352   */
9353  enum rxdone_entry_desc_flags {
9354         RXDONE_SIGNAL_PLCP = 1 << 0,
9355         RXDONE_SIGNAL_BITRATE = 1 << 1,
9356 -       RXDONE_MY_BSS = 1 << 2,
9357 +       RXDONE_SIGNAL_MCS = 1 << 2,
9358 +       RXDONE_MY_BSS = 1 << 3,
9359  };
9360
9361  /**
9362 @@ -163,6 +165,7 @@ enum rxdone_entry_desc_flags {
9363   * @timestamp: RX Timestamp
9364   * @signal: Signal of the received frame.
9365   * @rssi: RSSI of the received frame.
9366 + * @noise: Measured noise during frame reception.
9367   * @size: Data size of the received frame.
9368   * @flags: MAC80211 receive flags (See &enum mac80211_rx_flags).
9369   * @dev_flags: Ralink receive flags (See &enum rxdone_entry_desc_flags).
9370 @@ -176,6 +179,7 @@ struct rxdone_entry_desc {
9371         u64 timestamp;
9372         int signal;
9373         int rssi;
9374 +       int noise;
9375         int size;
9376         int flags;
9377         int dev_flags;
9378 @@ -234,6 +238,9 @@ struct txdone_entry_desc {
9379   * @ENTRY_TXD_ENCRYPT_PAIRWISE: Use pairwise key table (instead of shared).
9380   * @ENTRY_TXD_ENCRYPT_IV: Generate IV/EIV in hardware.
9381   * @ENTRY_TXD_ENCRYPT_MMIC: Generate MIC in hardware.
9382 + * @ENTRY_TXD_HT_AMPDU: This frame is part of an AMPDU.
9383 + * @ENTRY_TXD_HT_BW_40: Use 40MHz Bandwidth.
9384 + * @ENTRY_TXD_HT_SHORT_GI: Use short GI.
9385   */
9386  enum txentry_desc_flags {
9387         ENTRY_TXD_RTS_FRAME,
9388 @@ -250,6 +257,9 @@ enum txentry_desc_flags {
9389         ENTRY_TXD_ENCRYPT_PAIRWISE,
9390         ENTRY_TXD_ENCRYPT_IV,
9391         ENTRY_TXD_ENCRYPT_MMIC,
9392 +       ENTRY_TXD_HT_AMPDU,
9393 +       ENTRY_TXD_HT_BW_40,
9394 +       ENTRY_TXD_HT_SHORT_GI,
9395  };
9396
9397  /**
9398 @@ -263,6 +273,11 @@ enum txentry_desc_flags {
9399   * @length_low: PLCP length low word.
9400   * @signal: PLCP signal.
9401   * @service: PLCP service.
9402 + * @msc: MCS.
9403 + * @stbc: STBC.
9404 + * @ba_size: BA size.
9405 + * @rate_mode: Rate mode (CCK, OFDM, HT).
9406 + * @mpdu_density: MDPU density.
9407   * @retry_limit: Max number of retries.
9408   * @aifs: AIFS value.
9409   * @ifs: IFS value.
9410 @@ -282,6 +297,12 @@ struct txentry_desc {
9411         u16 signal;
9412         u16 service;
9413
9414 +       u16 mcs;
9415 +       u16 stbc;
9416 +       u16 ba_size;
9417 +       u16 rate_mode;
9418 +       u16 mpdu_density;
9419 +
9420         short retry_limit;
9421         short aifs;
9422         short ifs;
9423 --- a/drivers/net/wireless/rt2x00/rt2x00reg.h
9424 +++ b/drivers/net/wireless/rt2x00/rt2x00reg.h
9425 @@ -67,6 +67,16 @@ enum tsf_sync {
9426  };
9427
9428  /*
9429 + * TX frame rate mode
9430 + */
9431 +enum txrate_mode {
9432 +       TXRATE_MODE_CCK = 0,
9433 +       TXRATE_MODE_OFDM = 1,
9434 +       TXRATE_MODE_HTMIX = 2,
9435 +       TXRATE_MODE_GREENFIELD = 3,
9436 +};
9437 +
9438 +/*
9439   * Device states
9440   */
9441  enum dev_state {
9442 @@ -125,6 +135,16 @@ enum cipher {
9443  };
9444
9445  /*
9446 + * Rate modulations for 802.11n
9447 + */
9448 +enum rate_modulation {
9449 +       RATE_MODE_CCK = 0,
9450 +       RATE_MODE_OFDM = 1,
9451 +       RATE_MODE_HT_MIX = 2,
9452 +       RATE_MODE_HT_GREENFIELD = 3,
9453 +};
9454 +
9455 +/*
9456   * Register handlers.
9457   * We store the position of a register field inside a field structure,
9458   * This will simplify the process of setting and reading a certain field