package/mac80211/patches/310-rt2800_experimental.patch

   1 From: Ivo van Doorn <IvDoorn@gmail.com>
   2 Date: Thu, 20 Nov 2008 22:42:04 +0000 (+0100)
   3 Subject: rt2x00: Add rt2800pci and rt2800usb (BROKEN)
   4 X-Git-Url: http://git.kernel.org/?p=linux%2Fkernel%2Fgit%2Fivd%2Frt2x00.git;a=commitdiff_plain;h=760e9f904b54ab91cd78aac6188851cfaac5c795
   5
   6 rt2x00: Add rt2800pci and rt2800usb (BROKEN)
   7
   8 incomplete code...
   9
  10 Signed-off-by: Mattias Nissler <mattias.nissler@gmx.de>
  11 Signed-off-by: Felix Fietkau <nbd@openwrt.org>
  12 Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
  13 ---
  14
  15 diff --git a/drivers/net/wireless/rt2x00/Makefile b/drivers/net/wireless/rt2x00/Makefile
  16 index 917cb4f..99cec67 100644
  17 --- a/drivers/net/wireless/rt2x00/Makefile
  18 +++ b/drivers/net/wireless/rt2x00/Makefile
  19 @@ -14,5 +14,7 @@ obj-$(CONFIG_RT2X00_LIB_USB)          += rt2x00usb.o
  20  obj-$(CONFIG_RT2400PCI)                        += rt2400pci.o
  21  obj-$(CONFIG_RT2500PCI)                        += rt2500pci.o
  22  obj-$(CONFIG_RT61PCI)                  += rt61pci.o
  23 +obj-$(CONFIG_RT2800PCI)                        += rt2800pci.o
  24  obj-$(CONFIG_RT2500USB)                        += rt2500usb.o
  25  obj-$(CONFIG_RT73USB)                  += rt73usb.o
  26 +obj-$(CONFIG_RT2800USB)                        += rt2800usb.o
  27 diff --git a/drivers/net/wireless/rt2x00/rt2800pci.c b/drivers/net/wireless/rt2x00/rt2800pci.c
  28 new file mode 100644
  29 index 0000000..65e9915
  30 --- /dev/null
  31 +++ b/drivers/net/wireless/rt2x00/rt2800pci.c
  32 @@ -0,0 +1,2576 @@
  33 +/*
  34 +       Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
  35 +       <http://rt2x00.serialmonkey.com>
  36 +
  37 +       This program is free software; you can redistribute it and/or modify
  38 +       it under the terms of the GNU General Public License as published by
  39 +       the Free Software Foundation; either version 2 of the License, or
  40 +       (at your option) any later version.
  41 +
  42 +       This program is distributed in the hope that it will be useful,
  43 +       but WITHOUT ANY WARRANTY; without even the implied warranty of
  44 +       MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  45 +       GNU General Public License for more details.
  46 +
  47 +       You should have received a copy of the GNU General Public License
  48 +       along with this program; if not, write to the
  49 +       Free Software Foundation, Inc.,
  50 +       59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  51 + */
  52 +
  53 +/*
  54 +       Module: rt2800pci
  55 +       Abstract: rt2800pci device specific routines.
  56 +       Supported chipsets: RT2800E & RT2800ED.
  57 + */
  58 +
  59 +#include <linux/crc-ccitt.h>
  60 +#include <linux/delay.h>
  61 +#include <linux/etherdevice.h>
  62 +#include <linux/init.h>
  63 +#include <linux/kernel.h>
  64 +#include <linux/module.h>
  65 +#include <linux/pci.h>
  66 +#include <linux/eeprom_93cx6.h>
  67 +
  68 +#include "rt2x00.h"
  69 +#include "rt2x00pci.h"
  70 +#include "rt2800pci.h"
  71 +
  72 +/*
  73 + * Allow hardware encryption to be disabled.
  74 + */
  75 +static int modparam_nohwcrypt = 0;
  76 +module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
  77 +MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  78 +
  79 +/*
  80 + * Register access.
  81 + * BBP and RF register require indirect register access,
  82 + * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
  83 + * These indirect registers work with busy bits,
  84 + * and we will try maximal REGISTER_BUSY_COUNT times to access
  85 + * the register while taking a REGISTER_BUSY_DELAY us delay
  86 + * between each attampt. When the busy bit is still set at that time,
  87 + * the access attempt is considered to have failed,
  88 + * and we will print an error.
  89 + */
  90 +#define WAIT_FOR_BBP(__dev, __reg) \
  91 +       rt2x00pci_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
  92 +#define WAIT_FOR_RF(__dev, __reg) \
  93 +       rt2x00pci_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
  94 +#define WAIT_FOR_MCU(__dev, __reg) \
  95 +       rt2x00pci_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  96 +                              H2M_MAILBOX_CSR_OWNER, (__reg))
  97 +
  98 +static void rt2800pci_bbp_write(struct rt2x00_dev *rt2x00dev,
  99 +                               const unsigned int word, const u8 value)
 100 +{
 101 +       u32 reg;
 102 +
 103 +       mutex_lock(&rt2x00dev->csr_mutex);
 104 +
 105 +       /*
 106 +        * Wait until the BBP becomes available, afterwards we
 107 +        * can safely write the new data into the register.
 108 +        */
 109 +       if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 110 +               reg = 0;
 111 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
 112 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 113 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 114 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
 115 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 116 +
 117 +               rt2x00pci_register_write(rt2x00dev, BBP_CSR_CFG, reg);
 118 +       }
 119 +
 120 +       mutex_unlock(&rt2x00dev->csr_mutex);
 121 +}
 122 +
 123 +static void rt2800pci_bbp_read(struct rt2x00_dev *rt2x00dev,
 124 +                              const unsigned int word, u8 *value)
 125 +{
 126 +       u32 reg;
 127 +
 128 +       mutex_lock(&rt2x00dev->csr_mutex);
 129 +
 130 +       /*
 131 +        * Wait until the BBP becomes available, afterwards we
 132 +        * can safely write the read request into the register.
 133 +        * After the data has been written, we wait until hardware
 134 +        * returns the correct value, if at any time the register
 135 +        * doesn't become available in time, reg will be 0xffffffff
 136 +        * which means we return 0xff to the caller.
 137 +        */
 138 +       if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 139 +               reg = 0;
 140 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 141 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 142 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
 143 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 144 +
 145 +               rt2x00pci_register_write(rt2x00dev, BBP_CSR_CFG, reg);
 146 +
 147 +               WAIT_FOR_BBP(rt2x00dev, &reg);
 148 +       }
 149 +
 150 +       *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
 151 +
 152 +       mutex_unlock(&rt2x00dev->csr_mutex);
 153 +}
 154 +
 155 +static void rt2800pci_rf_write(struct rt2x00_dev *rt2x00dev,
 156 +                              const unsigned int word, const u32 value)
 157 +{
 158 +       u32 reg;
 159 +
 160 +       if (!word)
 161 +               return;
 162 +
 163 +       mutex_lock(&rt2x00dev->csr_mutex);
 164 +
 165 +       /*
 166 +        * Wait until the RF becomes available, afterwards we
 167 +        * can safely write the new data into the register.
 168 +        */
 169 +       if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 170 +               reg = 0;
 171 +               rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
 172 +               rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
 173 +               rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
 174 +               rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
 175 +
 176 +               rt2x00pci_register_write(rt2x00dev, RF_CSR_CFG0, reg);
 177 +               rt2x00_rf_write(rt2x00dev, word, value);
 178 +       }
 179 +
 180 +       mutex_unlock(&rt2x00dev->csr_mutex);
 181 +}
 182 +
 183 +static void rt2800pci_mcu_request(struct rt2x00_dev *rt2x00dev,
 184 +                                 const u8 command, const u8 token,
 185 +                                 const u8 arg0, const u8 arg1)
 186 +{
 187 +       u32 reg;
 188 +
 189 +       mutex_lock(&rt2x00dev->csr_mutex);
 190 +
 191 +       /*
 192 +        * Wait until the MCU becomes available, afterwards we
 193 +        * can safely write the new data into the register.
 194 +        */
 195 +       if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
 196 +               rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 197 +               rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 198 +               rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 199 +               rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 200 +               rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
 201 +
 202 +               reg = 0;
 203 +               rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 204 +               rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
 205 +       }
 206 +
 207 +       mutex_unlock(&rt2x00dev->csr_mutex);
 208 +}
 209 +
 210 +static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 211 +{
 212 +       struct rt2x00_dev *rt2x00dev = eeprom->data;
 213 +       u32 reg;
 214 +
 215 +       rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
 216 +
 217 +       eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
 218 +       eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
 219 +       eeprom->reg_data_clock =
 220 +           !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
 221 +       eeprom->reg_chip_select =
 222 +           !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
 223 +}
 224 +
 225 +static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 226 +{
 227 +       struct rt2x00_dev *rt2x00dev = eeprom->data;
 228 +       u32 reg = 0;
 229 +
 230 +       rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
 231 +       rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
 232 +       rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
 233 +                          !!eeprom->reg_data_clock);
 234 +       rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
 235 +                          !!eeprom->reg_chip_select);
 236 +
 237 +       rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
 238 +}
 239 +
 240 +#ifdef CONFIG_RT2X00_LIB_DEBUGFS
 241 +static const struct rt2x00debug rt2800pci_rt2x00debug = {
 242 +       .owner  = THIS_MODULE,
 243 +       .csr    = {
 244 +               .read           = rt2x00pci_register_read,
 245 +               .write          = rt2x00pci_register_write,
 246 +               .flags          = RT2X00DEBUGFS_OFFSET,
 247 +               .word_base      = CSR_REG_BASE,
 248 +               .word_size      = sizeof(u32),
 249 +               .word_count     = CSR_REG_SIZE / sizeof(u32),
 250 +       },
 251 +       .eeprom = {
 252 +               .read           = rt2x00_eeprom_read,
 253 +               .write          = rt2x00_eeprom_write,
 254 +               .word_base      = EEPROM_BASE,
 255 +               .word_size      = sizeof(u16),
 256 +               .word_count     = EEPROM_SIZE / sizeof(u16),
 257 +       },
 258 +       .bbp    = {
 259 +               .read           = rt2800pci_bbp_read,
 260 +               .write          = rt2800pci_bbp_write,
 261 +               .word_base      = BBP_BASE,
 262 +               .word_size      = sizeof(u8),
 263 +               .word_count     = BBP_SIZE / sizeof(u8),
 264 +       },
 265 +       .rf     = {
 266 +               .read           = rt2x00_rf_read,
 267 +               .write          = rt2800pci_rf_write,
 268 +               .word_base      = RF_BASE,
 269 +               .word_size      = sizeof(u32),
 270 +               .word_count     = RF_SIZE / sizeof(u32),
 271 +       },
 272 +};
 273 +#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 274 +
 275 +#ifdef CONFIG_RT2X00_LIB_RFKILL
 276 +static int rt2800pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 277 +{
 278 +       u32 reg;
 279 +
 280 +       rt2x00pci_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
 281 +       return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
 282 +}
 283 +#else
 284 +#define rt2800pci_rfkill_poll  NULL
 285 +#endif /* CONFIG_RT2X00_LIB_RFKILL */
 286 +
 287 +#ifdef CONFIG_RT2X00_LIB_LEDS
 288 +static void rt2800pci_brightness_set(struct led_classdev *led_cdev,
 289 +                                    enum led_brightness brightness)
 290 +{
 291 +       struct rt2x00_led *led =
 292 +           container_of(led_cdev, struct rt2x00_led, led_dev);
 293 +       unsigned int enabled = brightness != LED_OFF;
 294 +       unsigned int bg_mode =
 295 +           (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 296 +       unsigned int polarity =
 297 +               rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 298 +                                  EEPROM_FREQ_LED_POLARITY);
 299 +       unsigned int ledmode =
 300 +               rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 301 +                                  EEPROM_FREQ_LED_MODE);
 302 +
 303 +       if (led->type == LED_TYPE_RADIO) {
 304 +               rt2800pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 305 +                                     enabled ? 0x20 : 0);
 306 +       } else if (led->type == LED_TYPE_ASSOC) {
 307 +               rt2800pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 308 +                                     enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
 309 +       } else if (led->type == LED_TYPE_QUALITY) {
 310 +               /*
 311 +                * The brightness is divided into 6 levels (0 - 5),
 312 +                * The specs tell us the following levels:
 313 +                *      0, 1 ,3, 7, 15, 31
 314 +                * to determine the level in a simple way we can simply
 315 +                * work with bitshifting:
 316 +                *      (1 << level) - 1
 317 +                */
 318 +               rt2800pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
 319 +                                     (1 << brightness / (LED_FULL / 6)) - 1,
 320 +                                     polarity);
 321 +       }
 322 +}
 323 +
 324 +static int rt2800pci_blink_set(struct led_classdev *led_cdev,
 325 +                              unsigned long *delay_on,
 326 +                              unsigned long *delay_off)
 327 +{
 328 +       struct rt2x00_led *led =
 329 +           container_of(led_cdev, struct rt2x00_led, led_dev);
 330 +       u32 reg;
 331 +
 332 +       rt2x00pci_register_read(led->rt2x00dev, LED_CFG, &reg);
 333 +       rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
 334 +       rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
 335 +       rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
 336 +       rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
 337 +       rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 12);
 338 +       rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
 339 +       rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
 340 +       rt2x00pci_register_write(led->rt2x00dev, LED_CFG, reg);
 341 +
 342 +       return 0;
 343 +}
 344 +
 345 +static void rt2800pci_init_led(struct rt2x00_dev *rt2x00dev,
 346 +                              struct rt2x00_led *led,
 347 +                              enum led_type type)
 348 +{
 349 +       led->rt2x00dev = rt2x00dev;
 350 +       led->type = type;
 351 +       led->led_dev.brightness_set = rt2800pci_brightness_set;
 352 +       led->led_dev.blink_set = rt2800pci_blink_set;
 353 +       led->flags = LED_INITIALIZED;
 354 +}
 355 +#endif /* CONFIG_RT2X00_LIB_LEDS */
 356 +
 357 +/*
 358 + * Configuration handlers.
 359 + */
 360 +static void rt2800pci_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
 361 +                                      struct rt2x00lib_crypto *crypto,
 362 +                                      struct ieee80211_key_conf *key)
 363 +{
 364 +       u32 offset;
 365 +       u32 reg;
 366 +
 367 +       offset = MAC_WCID_ATTR_ENTRY(crypto->aid);
 368 +
 369 +       reg = 0;
 370 +       rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
 371 +                          !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
 372 +       rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_PAIRKEY_MODE,
 373 +                          crypto->cipher);
 374 +       rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
 375 +                          (crypto->cmd == SET_KEY) ? crypto->bssidx : 0);
 376 +       rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
 377 +       rt2x00pci_register_write(rt2x00dev, offset, reg);
 378 +}
 379 +
 380 +static int rt2800pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
 381 +                                      struct rt2x00lib_crypto *crypto,
 382 +                                      struct ieee80211_key_conf *key)
 383 +{
 384 +       struct hw_key_entry key_entry;
 385 +       struct rt2x00_field32 field;
 386 +       u32 offset;
 387 +       u32 mask;
 388 +       u32 reg;
 389 +
 390 +       if (crypto->cmd == SET_KEY) {
 391 +               memcpy(key_entry.key, crypto->key,
 392 +                      sizeof(key_entry.key));
 393 +               memcpy(key_entry.tx_mic, crypto->tx_mic,
 394 +                      sizeof(key_entry.tx_mic));
 395 +               memcpy(key_entry.rx_mic, crypto->rx_mic,
 396 +                      sizeof(key_entry.rx_mic));
 397 +
 398 +               offset = SHARED_KEY_ENTRY(key->hw_key_idx);
 399 +               rt2x00pci_register_multiwrite(rt2x00dev, offset,
 400 +                                             &key_entry, sizeof(key_entry));
 401 +
 402 +               /*
 403 +                * The driver does not support the IV/EIV generation
 404 +                * in hardware. However it doesn't support the IV/EIV
 405 +                * inside the ieee80211 frame either, but requires it
 406 +                * to be provided seperately for the descriptor.
 407 +                * rt2x00lib will cut the IV/EIV data out of all frames
 408 +                * given to us by mac80211, but we must tell mac80211
 409 +                * to generate the IV/EIV data.
 410 +                */
 411 +               key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
 412 +       }
 413 +
 414 +       /*
 415 +        * The cipher types are stored over multiple registers
 416 +        * starting with SHARED_KEY_MODE_BASE each word will have
 417 +        * 32 bits and contains the cipher types for 2 modes each.
 418 +        * Using the correct defines correctly will cause overhead,
 419 +        * so just calculate the correct offset.
 420 +        */
 421 +       mask = key->hw_key_idx % 8;
 422 +       field.bit_offset = (3 * mask);
 423 +       field.bit_mask = 0x7 << field.bit_offset;
 424 +
 425 +       offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
 426 +       rt2x00pci_register_read(rt2x00dev, offset, &reg);
 427 +       rt2x00_set_field32(&reg, field,
 428 +                          (crypto->cmd == SET_KEY) ? crypto->cipher : 0);
 429 +       rt2x00pci_register_write(rt2x00dev, offset, reg);
 430 +
 431 +       /*
 432 +        * Update WCID information
 433 +        */
 434 +       rt2800pci_config_wcid_attr(rt2x00dev, crypto, key);
 435 +
 436 +       return 0;
 437 +}
 438 +
 439 +static int rt2800pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
 440 +                                        struct rt2x00lib_crypto *crypto,
 441 +                                        struct ieee80211_key_conf *key)
 442 +{
 443 +       struct hw_key_entry key_entry;
 444 +       u32 offset;
 445 +
 446 +       /*
 447 +        * 1 pairwise key is possible per AID, this means that the AID
 448 +        * equals our hw_key_idx.
 449 +        */
 450 +       key->hw_key_idx = crypto->aid;
 451 +
 452 +       if (crypto->cmd == SET_KEY) {
 453 +               memcpy(key_entry.key, crypto->key,
 454 +                      sizeof(key_entry.key));
 455 +               memcpy(key_entry.tx_mic, crypto->tx_mic,
 456 +                      sizeof(key_entry.tx_mic));
 457 +               memcpy(key_entry.rx_mic, crypto->rx_mic,
 458 +                      sizeof(key_entry.rx_mic));
 459 +
 460 +               offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
 461 +               rt2x00pci_register_multiwrite(rt2x00dev, offset,
 462 +                                             &key_entry, sizeof(key_entry));
 463 +
 464 +               /*
 465 +                * The driver does not support the IV/EIV generation
 466 +                * in hardware. However it doesn't support the IV/EIV
 467 +                * inside the ieee80211 frame either, but requires it
 468 +                * to be provided seperately for the descriptor.
 469 +                * rt2x00lib will cut the IV/EIV data out of all frames
 470 +                * given to us by mac80211, but we must tell mac80211
 471 +                * to generate the IV/EIV data.
 472 +                */
 473 +               key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
 474 +       }
 475 +
 476 +       /*
 477 +        * Update WCID information
 478 +        */
 479 +       rt2800pci_config_wcid_attr(rt2x00dev, crypto, key);
 480 +
 481 +       return 0;
 482 +}
 483 +
 484 +static void rt2800pci_config_filter(struct rt2x00_dev *rt2x00dev,
 485 +                                   const unsigned int filter_flags)
 486 +{
 487 +       u32 reg;
 488 +
 489 +       /*
 490 +        * Start configuration steps.
 491 +        * Note that the version error will always be dropped
 492 +        * and broadcast frames will always be accepted since
 493 +        * there is no filter for it at this time.
 494 +        */
 495 +       rt2x00pci_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
 496 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
 497 +                          !(filter_flags & FIF_FCSFAIL));
 498 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
 499 +                          !(filter_flags & FIF_PLCPFAIL));
 500 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
 501 +                          !(filter_flags & FIF_PROMISC_IN_BSS));
 502 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD,
 503 +                          !(filter_flags & FIF_OTHER_BSS));
 504 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
 505 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
 506 +                          !(filter_flags & FIF_ALLMULTI));
 507 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
 508 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
 509 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
 510 +                          !(filter_flags & FIF_CONTROL));
 511 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
 512 +                          !(filter_flags & FIF_CONTROL));
 513 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
 514 +                          !(filter_flags & FIF_CONTROL));
 515 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
 516 +                          !(filter_flags & FIF_CONTROL));
 517 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
 518 +                          !(filter_flags & FIF_CONTROL));
 519 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
 520 +                          !(filter_flags & FIF_CONTROL));
 521 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
 522 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 1);
 523 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
 524 +                          !(filter_flags & FIF_CONTROL));
 525 +       rt2x00pci_register_write(rt2x00dev, RX_FILTER_CFG, reg);
 526 +}
 527 +
 528 +static void rt2800pci_config_intf(struct rt2x00_dev *rt2x00dev,
 529 +                                 struct rt2x00_intf *intf,
 530 +                                 struct rt2x00intf_conf *conf,
 531 +                                 const unsigned int flags)
 532 +{
 533 +       unsigned int beacon_base;
 534 +       u32 reg;
 535 +
 536 +       if (flags & CONFIG_UPDATE_TYPE) {
 537 +               /*
 538 +                * Clear current synchronisation setup.
 539 +                * For the Beacon base registers we only need to clear
 540 +                * the first byte since that byte contains the VALID and OWNER
 541 +                * bits which (when set to 0) will invalidate the entire beacon.
 542 +                */
 543 +               beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
 544 +               rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
 545 +
 546 +               /*
 547 +                * Enable synchronisation.
 548 +                */
 549 +               rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 550 +               rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
 551 +               rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
 552 +               rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
 553 +               rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 554 +       }
 555 +
 556 +       if (flags & CONFIG_UPDATE_MAC) {
 557 +               reg = le32_to_cpu(conf->mac[1]);
 558 +               rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
 559 +               conf->mac[1] = cpu_to_le32(reg);
 560 +
 561 +               rt2x00pci_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
 562 +                                             conf->mac, sizeof(conf->mac));
 563 +       }
 564 +
 565 +       if (flags & CONFIG_UPDATE_BSSID) {
 566 +               reg = le32_to_cpu(conf->bssid[1]);
 567 +               rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
 568 +               rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
 569 +               conf->bssid[1] = cpu_to_le32(reg);
 570 +
 571 +               rt2x00pci_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
 572 +                                             conf->bssid, sizeof(conf->bssid));
 573 +       }
 574 +}
 575 +
 576 +static void rt2800pci_config_erp(struct rt2x00_dev *rt2x00dev,
 577 +                                struct rt2x00lib_erp *erp)
 578 +{
 579 +       u32 reg;
 580 +
 581 +       rt2x00pci_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
 582 +       rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT,
 583 +                          erp->ack_timeout);
 584 +       rt2x00pci_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
 585 +
 586 +       rt2x00pci_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
 587 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
 588 +                          !!erp->short_preamble);
 589 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
 590 +                          !!erp->short_preamble);
 591 +       rt2x00pci_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
 592 +
 593 +       rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
 594 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
 595 +                          erp->cts_protection ? 2 : 0);
 596 +       rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
 597 +
 598 +       rt2x00pci_register_write(rt2x00dev, LEGACY_BASIC_RATE,
 599 +                                erp->basic_rates);
 600 +       rt2x00pci_register_write(rt2x00dev, HT_BASIC_RATE,
 601 +                                erp->basic_rates >> 32);
 602 +
 603 +       rt2x00pci_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
 604 +       rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
 605 +       rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
 606 +       rt2x00pci_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
 607 +
 608 +       rt2x00pci_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
 609 +       rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
 610 +       rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
 611 +       rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
 612 +       rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
 613 +       rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
 614 +       rt2x00pci_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
 615 +}
 616 +
 617 +static void rt2800pci_config_ant(struct rt2x00_dev *rt2x00dev,
 618 +                                struct antenna_setup *ant)
 619 +{
 620 +       u16 eeprom;
 621 +       u8 r1;
 622 +       u8 r3;
 623 +
 624 +       /*
 625 +        * FIXME: Use requested antenna configuration.
 626 +        */
 627 +
 628 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
 629 +
 630 +       rt2800pci_bbp_read(rt2x00dev, 1, &r1);
 631 +       rt2800pci_bbp_read(rt2x00dev, 3, &r3);
 632 +
 633 +       /*
 634 +        * Configure the TX antenna.
 635 +        */
 636 +       switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH)) {
 637 +       case 1:
 638 +               rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
 639 +               break;
 640 +       case 2:
 641 +       case 3:
 642 +               /* Do nothing */
 643 +               break;
 644 +       }
 645 +
 646 +       /*
 647 +        * Configure the RX antenna.
 648 +        */
 649 +       switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
 650 +       case 1:
 651 +               rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
 652 +               break;
 653 +       case 2:
 654 +               rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
 655 +               break;
 656 +       case 3:
 657 +               rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
 658 +               break;
 659 +       }
 660 +
 661 +       rt2800pci_bbp_write(rt2x00dev, 3, r3);
 662 +       rt2800pci_bbp_write(rt2x00dev, 1, r1);
 663 +}
 664 +
 665 +static void rt2800pci_config_lna_gain(struct rt2x00_dev *rt2x00dev,
 666 +                                     struct rt2x00lib_conf *libconf)
 667 +{
 668 +       u16 eeprom;
 669 +       short lna_gain;
 670 +
 671 +       if (libconf->rf.channel <= 14) {
 672 +               rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
 673 +               lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
 674 +       } else if (libconf->rf.channel <= 64) {
 675 +               rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
 676 +               lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
 677 +       } else if (libconf->rf.channel <= 128) {
 678 +               rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
 679 +               lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
 680 +       } else {
 681 +               rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
 682 +               lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
 683 +       }
 684 +
 685 +       rt2x00dev->lna_gain = lna_gain;
 686 +}
 687 +
 688 +static void rt2800pci_config_channel(struct rt2x00_dev *rt2x00dev,
 689 +                                    struct rf_channel *rf,
 690 +                                    struct channel_info *info)
 691 +{
 692 +       u32 reg;
 693 +       unsigned int tx_pin;
 694 +       u16 eeprom;
 695 +
 696 +       tx_pin = 0;
 697 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
 698 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
 699 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
 700 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
 701 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
 702 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
 703 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
 704 +
 705 +       rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
 706 +
 707 +       /*
 708 +        * Determine antenna settings from EEPROM
 709 +        */
 710 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
 711 +       if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1) {
 712 +               rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
 713 +               /* Turn off unused PA or LNA when only 1T or 1R */
 714 +               rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 0);
 715 +               rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 0);
 716 +       }
 717 +
 718 +       if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1) {
 719 +               rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
 720 +               rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
 721 +               /* Turn off unused PA or LNA when only 1T or 1R */
 722 +               rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 0);
 723 +               rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 0);
 724 +       } else if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 2)
 725 +               rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
 726 +
 727 +       if (rf->channel > 14) {
 728 +               /*
 729 +                * When TX power is below 0, we should increase it by 7 to
 730 +                * make it a positive value (Minumum value is -7).
 731 +                * However this means that values between 0 and 7 have
 732 +                * double meaning, and we should set a 7DBm boost flag.
 733 +                */
 734 +               rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
 735 +                                  (info->tx_power1 >= 0));
 736 +
 737 +               if (info->tx_power1 < 0)
 738 +                       info->tx_power1 += 7;
 739 +
 740 +               rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
 741 +                                  TXPOWER_A_TO_DEV(info->tx_power1));
 742 +
 743 +               rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
 744 +                                  (info->tx_power2 >= 0));
 745 +
 746 +               if (info->tx_power2 < 0)
 747 +                       info->tx_power2 += 7;
 748 +
 749 +               rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
 750 +                                  TXPOWER_A_TO_DEV(info->tx_power2));
 751 +
 752 +               rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
 753 +       } else {
 754 +               rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
 755 +                                  TXPOWER_G_TO_DEV(info->tx_power1));
 756 +               rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
 757 +                                  TXPOWER_G_TO_DEV(info->tx_power2));
 758 +
 759 +               rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
 760 +       }
 761 +
 762 +       /* FIXME: How to determine bandwidth
 763 +       rt2x00_set_field32(&rf->rf4, RF4_BW40, !!(BBPCurrentBW == BW_40));
 764 +       */
 765 +
 766 +       rt2800pci_rf_write(rt2x00dev, 1, rf->rf1);
 767 +       rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
 768 +       rt2800pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 769 +       rt2800pci_rf_write(rt2x00dev, 4, rf->rf4);
 770 +
 771 +       udelay(200);
 772 +
 773 +       rt2800pci_rf_write(rt2x00dev, 1, rf->rf1);
 774 +       rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
 775 +       rt2800pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
 776 +       rt2800pci_rf_write(rt2x00dev, 4, rf->rf4);
 777 +
 778 +       udelay(200);
 779 +
 780 +       rt2800pci_rf_write(rt2x00dev, 1, rf->rf1);
 781 +       rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
 782 +       rt2800pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 783 +       rt2800pci_rf_write(rt2x00dev, 4, rf->rf4);
 784 +
 785 +       /*
 786 +        * Change BBP settings
 787 +        */
 788 +       rt2800pci_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
 789 +       rt2800pci_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
 790 +       rt2800pci_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
 791 +       rt2800pci_bbp_write(rt2x00dev, 86, 0);
 792 +
 793 +       if (rf->channel <= 14) {
 794 +               if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
 795 +                       rt2800pci_bbp_write(rt2x00dev, 82, 0x62);
 796 +                       rt2800pci_bbp_write(rt2x00dev, 75, 0x46);
 797 +               } else {
 798 +                       rt2800pci_bbp_write(rt2x00dev, 82, 0x84);
 799 +                       rt2800pci_bbp_write(rt2x00dev, 75, 0x50);
 800 +               }
 801 +
 802 +               rt2x00pci_register_read(rt2x00dev, TX_BAND_CFG, &reg);
 803 +               rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_A, 0);
 804 +               rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_BG, 1);
 805 +               rt2x00pci_register_write(rt2x00dev, TX_BAND_CFG, reg);
 806 +       } else {
 807 +               rt2800pci_bbp_write(rt2x00dev, 82, 0xf2);
 808 +
 809 +               if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
 810 +                       rt2800pci_bbp_write(rt2x00dev, 75, 0x46);
 811 +               else
 812 +                       rt2800pci_bbp_write(rt2x00dev, 75, 0x50);
 813 +
 814 +               rt2x00pci_register_read(rt2x00dev, TX_BAND_CFG, &reg);
 815 +               rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_A, 1);
 816 +               rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_BG, 0);
 817 +               rt2x00pci_register_write(rt2x00dev, TX_BAND_CFG, reg);
 818 +       }
 819 +
 820 +       rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
 821 +
 822 +       msleep(1);
 823 +}
 824 +
 825 +static void rt2800pci_config_txpower(struct rt2x00_dev *rt2x00dev,
 826 +                                    const int txpower)
 827 +{
 828 +       u32 reg;
 829 +       u32 value = TXPOWER_G_TO_DEV(txpower);
 830 +       u8 r1;
 831 +
 832 +       rt2800pci_bbp_read(rt2x00dev, 1, &r1);
 833 +       rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
 834 +       rt2800pci_bbp_write(rt2x00dev, 1, r1);
 835 +
 836 +       rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
 837 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
 838 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
 839 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
 840 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
 841 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
 842 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
 843 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
 844 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
 845 +       rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
 846 +
 847 +       rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
 848 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
 849 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
 850 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
 851 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
 852 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
 853 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
 854 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
 855 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
 856 +       rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
 857 +
 858 +       rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
 859 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
 860 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
 861 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
 862 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
 863 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
 864 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
 865 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
 866 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
 867 +       rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
 868 +
 869 +       rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
 870 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
 871 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
 872 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
 873 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
 874 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
 875 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
 876 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
 877 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
 878 +       rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
 879 +
 880 +       rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
 881 +       rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
 882 +       rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
 883 +       rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
 884 +       rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
 885 +       rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
 886 +}
 887 +
 888 +static void rt2800pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
 889 +                                        struct rt2x00lib_conf *libconf)
 890 +{
 891 +       u32 reg;
 892 +
 893 +       rt2x00pci_register_read(rt2x00dev, TX_RTY_CFG, &reg);
 894 +       rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
 895 +                          libconf->conf->short_frame_max_tx_count);
 896 +       rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
 897 +                          libconf->conf->long_frame_max_tx_count);
 898 +       rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
 899 +       rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
 900 +       rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
 901 +       rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
 902 +       rt2x00pci_register_write(rt2x00dev, TX_RTY_CFG, reg);
 903 +}
 904 +
 905 +static void rt2800pci_config_duration(struct rt2x00_dev *rt2x00dev,
 906 +                                     struct rt2x00lib_conf *libconf)
 907 +{
 908 +       u32 reg;
 909 +
 910 +       rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 911 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
 912 +                          libconf->conf->beacon_int * 16);
 913 +       rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 914 +}
 915 +
 916 +static void rt2800pci_config(struct rt2x00_dev *rt2x00dev,
 917 +                            struct rt2x00lib_conf *libconf,
 918 +                            const unsigned int flags)
 919 +{
 920 +       /* Always recalculate LNA gain before changing configuration */
 921 +       rt2800pci_config_lna_gain(rt2x00dev, libconf);
 922 +
 923 +       if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
 924 +               rt2800pci_config_channel(rt2x00dev, &libconf->rf,
 925 +                                        &libconf->channel);
 926 +       if (flags & IEEE80211_CONF_CHANGE_POWER)
 927 +               rt2800pci_config_txpower(rt2x00dev, libconf->conf->power_level);
 928 +       if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
 929 +               rt2800pci_config_retry_limit(rt2x00dev, libconf);
 930 +       if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
 931 +               rt2800pci_config_duration(rt2x00dev, libconf);
 932 +}
 933 +
 934 +/*
 935 + * Link tuning
 936 + */
 937 +static void rt2800pci_link_stats(struct rt2x00_dev *rt2x00dev,
 938 +                                struct link_qual *qual)
 939 +{
 940 +       u32 reg;
 941 +
 942 +       /*
 943 +        * Update FCS error count from register.
 944 +        */
 945 +       rt2x00pci_register_read(rt2x00dev, RX_STA_CNT0, &reg);
 946 +       qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
 947 +
 948 +       /*
 949 +        * Update False CCA count from register.
 950 +        */
 951 +       rt2x00pci_register_read(rt2x00dev, RX_STA_CNT1, &reg);
 952 +       qual->false_cca = rt2x00_get_field32(reg, RX_STA_CNT1_FALSE_CCA);
 953 +}
 954 +
 955 +static void rt2800pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
 956 +{
 957 +       u8 r66;
 958 +
 959 +       if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ)
 960 +               r66 = 0x2e + rt2x00dev->lna_gain;
 961 +       else {
 962 +               if (1 /* FIXME: pAd->CommonCfg.BBPCurrentBW == BW_20 */)
 963 +                       r66 = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
 964 +               else
 965 +                       r66 = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
 966 +       }
 967 +
 968 +       rt2800pci_bbp_write(rt2x00dev, 66, r66);
 969 +}
 970 +
 971 +static void rt2800pci_link_tuner(struct rt2x00_dev *rt2x00dev)
 972 +{
 973 +       int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
 974 +       u8 r66_orig;
 975 +       u8 r66;
 976 +
 977 +       if (rt2x00_rev(&rt2x00dev->chip) == RT2860_VERSION_C)
 978 +               return;
 979 +
 980 +       rt2800pci_bbp_read(rt2x00dev, 66, &r66_orig);
 981 +       r66 = r66_orig;
 982 +
 983 +       if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
 984 +               r66 = 0x2e + rt2x00dev->lna_gain;
 985 +       } else {
 986 +               if (1 /* FIXME: pAd->CommonCfg.BBPCurrentBW == BW_20 */)
 987 +                       r66 = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
 988 +               else
 989 +                       r66 = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
 990 +       }
 991 +
 992 +       if (rssi > -80)
 993 +               r66 += 0x10;
 994 +
 995 +       if (rssi != r66_orig)
 996 +               rt2800pci_bbp_write(rt2x00dev, 66, r66);
 997 +}
 998 +
 999 +/*
1000 + * Firmware functions
1001 + */
1002 +static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1003 +{
1004 +       return FIRMWARE_RT2860;
1005 +}
1006 +
1007 +static u16 rt2800pci_get_firmware_crc(const void *data, const size_t len)
1008 +{
1009 +       u16 crc;
1010 +
1011 +       /*
1012 +        * Use the crc ccitt algorithm.
1013 +        * This will return the same value as the legacy driver which
1014 +        * used bit ordering reversion on the both the firmware bytes
1015 +        * before input input as well as on the final output.
1016 +        * Obviously using crc ccitt directly is much more efficient.
1017 +        * The last 2 bytes in the firmware array are the crc checksum itself,
1018 +        * this means that we should never pass those 2 bytes to the crc
1019 +        * algorithm.
1020 +        */
1021 +       crc = crc_ccitt(~0, data, len - 2);
1022 +
1023 +       /*
1024 +        * There is a small difference between the crc-itu-t + bitrev and
1025 +        * the crc-ccitt crc calculation. In the latter method the 2 bytes
1026 +        * will be swapped, use swab16 to convert the crc to the correct
1027 +        * value.
1028 +        */
1029 +       return swab16(crc);
1030 +}
1031 +
1032 +static int rt2800pci_load_firmware(struct rt2x00_dev *rt2x00dev,
1033 +                                  const void *data, const size_t len)
1034 +{
1035 +       unsigned int i;
1036 +       u32 reg;
1037 +
1038 +       /*
1039 +        * Wait for stable hardware.
1040 +        */
1041 +       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1042 +               rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
1043 +               if (reg && reg != ~0)
1044 +                       break;
1045 +               msleep(1);
1046 +       }
1047 +
1048 +       if (i == REGISTER_BUSY_COUNT) {
1049 +               ERROR(rt2x00dev, "Unstable hardware.\n");
1050 +               return -EBUSY;
1051 +       }
1052 +
1053 +       /*
1054 +        * Disable DMA, will be reenabled later when enabling
1055 +        * the radio.
1056 +        */
1057 +       rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1058 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1059 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1060 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1061 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1062 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1063 +       rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1064 +
1065 +       rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, ~0);
1066 +       rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x0e1f);
1067 +       rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x0e00);
1068 +
1069 +       /*
1070 +        * enable Host program ram write selection
1071 +        */
1072 +       reg = 0;
1073 +       rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
1074 +       rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
1075 +
1076 +       /*
1077 +        * Write firmware to device.
1078 +        */
1079 +       rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
1080 +                                     data, len);
1081 +
1082 +       rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
1083 +       rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
1084 +
1085 +       /*
1086 +        * Wait for device to stabilize.
1087 +        */
1088 +       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1089 +               rt2x00pci_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1090 +               if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
1091 +                       break;
1092 +               msleep(1);
1093 +       }
1094 +
1095 +       if (i == REGISTER_BUSY_COUNT) {
1096 +               ERROR(rt2x00dev, "PBF system register not ready.\n");
1097 +               return -EBUSY;
1098 +       }
1099 +
1100 +       /*
1101 +        * Initialize BBP R/W access agent
1102 +        */
1103 +       rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1104 +       rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1105 +
1106 +       return 0;
1107 +}
1108 +
1109 +/*
1110 + * Initialization functions.
1111 + */
1112 +static bool rt2800pci_get_entry_state(struct queue_entry *entry)
1113 +{
1114 +       struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1115 +       u32 word;
1116 +
1117 +       if (entry->queue->qid == QID_RX) {
1118 +               rt2x00_desc_read(entry_priv->desc, 1, &word);
1119 +
1120 +               return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
1121 +       } else {
1122 +               rt2x00_desc_read(entry_priv->desc, 0, &word);
1123 +
1124 +               return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
1125 +       }
1126 +}
1127 +
1128 +static void rt2800pci_clear_entry(struct queue_entry *entry)
1129 +{
1130 +       struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1131 +       struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1132 +       u32 word;
1133 +
1134 +       if (entry->queue->qid == QID_RX) {
1135 +               rt2x00_desc_read(entry_priv->desc, 0, &word);
1136 +               rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
1137 +               rt2x00_desc_write(entry_priv->desc, 0, word);
1138 +
1139 +               rt2x00_desc_read(entry_priv->desc, 1, &word);
1140 +               rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
1141 +               rt2x00_desc_write(entry_priv->desc, 1, word);
1142 +       } else {
1143 +               rt2x00_desc_read(entry_priv->desc, 1, &word);
1144 +               rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
1145 +               rt2x00_desc_write(entry_priv->desc, 1, word);
1146 +       }
1147 +}
1148 +
1149 +static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
1150 +{
1151 +       struct queue_entry_priv_pci *entry_priv;
1152 +       u32 reg;
1153 +
1154 +       /*
1155 +        * Initialize registers.
1156 +        */
1157 +       entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
1158 +       rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
1159 +       rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT0, rt2x00dev->tx[0].limit);
1160 +       rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX0, 0);
1161 +
1162 +       entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
1163 +       rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
1164 +       rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT1, rt2x00dev->tx[1].limit);
1165 +       rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX1, 0);
1166 +
1167 +       entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
1168 +       rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
1169 +       rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT2, rt2x00dev->tx[2].limit);
1170 +       rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX2, 0);
1171 +
1172 +       entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
1173 +       rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
1174 +       rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT3, rt2x00dev->tx[3].limit);
1175 +       rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX3, 0);
1176 +
1177 +       entry_priv = rt2x00dev->rx->entries[0].priv_data;
1178 +       rt2x00pci_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
1179 +       rt2x00pci_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit);
1180 +       rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX, 0);
1181 +
1182 +       /*
1183 +        * Enable global DMA configuration
1184 +        */
1185 +       rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1186 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1187 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1188 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1189 +       rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1190 +
1191 +       rt2x00pci_register_write(rt2x00dev, DELAY_INT_CFG, 0);
1192 +
1193 +       return 0;
1194 +}
1195 +
1196 +static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
1197 +{
1198 +       u32 reg;
1199 +       unsigned int i;
1200 +
1201 +       rt2x00pci_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
1202 +       rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
1203 +       rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
1204 +       rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
1205 +       rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
1206 +       rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
1207 +       rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
1208 +       rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
1209 +       rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
1210 +
1211 +       rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
1212 +       rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000000);
1213 +
1214 +       rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1215 +       rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1216 +       rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1217 +       rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1218 +
1219 +       rt2x00pci_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1220 +       rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1221 +       rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1222 +       rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1223 +       rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1224 +       rt2x00pci_register_write(rt2x00dev, BCN_OFFSET0, reg);
1225 +
1226 +       rt2x00pci_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1227 +       rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1228 +       rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1229 +       rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1230 +       rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1231 +       rt2x00pci_register_write(rt2x00dev, BCN_OFFSET1, reg);
1232 +
1233 +       rt2x00pci_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1234 +       rt2x00pci_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1235 +
1236 +       rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1237 +
1238 +       rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1239 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1240 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1241 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1242 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1243 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1244 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1245 +       rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1246 +
1247 +       rt2x00pci_register_write(rt2x00dev, TX_SW_CFG0, 0x00040a06);
1248 +       rt2x00pci_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1249 +
1250 +       rt2x00pci_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1251 +       rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1252 +       rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1253 +       rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1254 +       rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1255 +       rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1256 +       rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1257 +       rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1258 +       rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1259 +       rt2x00pci_register_write(rt2x00dev, TX_LINK_CFG, reg);
1260 +
1261 +       rt2x00pci_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1262 +       rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1263 +       rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1264 +       rt2x00pci_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1265 +
1266 +       rt2x00pci_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1267 +       rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1268 +       rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1269 +       rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1270 +       rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1271 +       rt2x00pci_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1272 +
1273 +       rt2x00pci_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1274 +
1275 +       rt2x00pci_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1276 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1277 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1278 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1279 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1280 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1281 +       rt2x00pci_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1282 +
1283 +       rt2x00pci_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1284 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
1285 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1286 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1287 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1288 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1289 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1290 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1291 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1292 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1293 +       rt2x00pci_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1294 +
1295 +       rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1296 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
1297 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1298 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1299 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1300 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1301 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1302 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1303 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1304 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1305 +       rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1306 +
1307 +       rt2x00pci_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1308 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1309 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1310 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1311 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1312 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1313 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1314 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1315 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1316 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1317 +       rt2x00pci_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1318 +
1319 +       rt2x00pci_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1320 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1321 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
1322 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1323 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1324 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1325 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1326 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1327 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1328 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1329 +       rt2x00pci_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1330 +
1331 +       rt2x00pci_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1332 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1333 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1334 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1335 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1336 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1337 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1338 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1339 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1340 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1341 +       rt2x00pci_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1342 +
1343 +       rt2x00pci_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1344 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1345 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1346 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1347 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1348 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1349 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1350 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1351 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1352 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1353 +       rt2x00pci_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1354 +
1355 +       rt2x00pci_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1356 +       rt2x00pci_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1357 +
1358 +       rt2x00pci_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1359 +       rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1360 +       rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1361 +       rt2x00pci_register_write(rt2x00dev, TX_RTS_CFG, reg);
1362 +
1363 +       rt2x00pci_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1364 +       rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1365 +
1366 +       /*
1367 +        * ASIC will keep garbage value after boot, clear encryption keys.
1368 +        */
1369 +       for (i = 0; i < 254; i++) {
1370 +               u32 wcid[2] = { 0xffffffff, 0x0000ffff };
1371 +               rt2x00pci_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1372 +                                             wcid, sizeof(wcid));
1373 +       }
1374 +
1375 +       for (i = 0; i < 4; i++)
1376 +               rt2x00pci_register_write(rt2x00dev,
1377 +                                        SHARED_KEY_MODE_ENTRY(i), 0);
1378 +
1379 +       for (i = 0; i < 256; i++)
1380 +               rt2x00pci_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1381 +
1382 +       /*
1383 +        * Clear all beacons
1384 +        * For the Beacon base registers we only need to clear
1385 +        * the first byte since that byte contains the VALID and OWNER
1386 +        * bits which (when set to 0) will invalidate the entire beacon.
1387 +        */
1388 +       rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1389 +       rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1390 +       rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1391 +       rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1392 +       rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1393 +       rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1394 +       rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1395 +       rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1396 +
1397 +       rt2x00pci_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1398 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1399 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1400 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1401 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1402 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1403 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1404 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1405 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1406 +       rt2x00pci_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1407 +
1408 +       rt2x00pci_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1409 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1410 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1411 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1412 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1413 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1414 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1415 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1416 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1417 +       rt2x00pci_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1418 +
1419 +       rt2x00pci_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1420 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1421 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1422 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 10);
1423 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 11);
1424 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 12);
1425 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 13);
1426 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 14);
1427 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 15);
1428 +       rt2x00pci_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1429 +
1430 +       rt2x00pci_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1431 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1432 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1433 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1434 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1435 +       rt2x00pci_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1436 +
1437 +       /*
1438 +        * We must clear the error counters.
1439 +        * These registers are cleared on read,
1440 +        * so we may pass a useless variable to store the value.
1441 +        */
1442 +       rt2x00pci_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1443 +       rt2x00pci_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1444 +       rt2x00pci_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1445 +       rt2x00pci_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1446 +       rt2x00pci_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1447 +       rt2x00pci_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1448 +
1449 +       return 0;
1450 +}
1451 +
1452 +static int rt2800pci_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1453 +{
1454 +       unsigned int i;
1455 +       u32 reg;
1456 +
1457 +       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1458 +               rt2x00pci_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1459 +               if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1460 +                       return 0;
1461 +
1462 +               udelay(REGISTER_BUSY_DELAY);
1463 +       }
1464 +
1465 +       ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1466 +       return -EACCES;
1467 +}
1468 +
1469 +static int rt2800pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1470 +{
1471 +       unsigned int i;
1472 +       u8 value;
1473 +
1474 +       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1475 +               rt2800pci_bbp_read(rt2x00dev, 0, &value);
1476 +               if ((value != 0xff) && (value != 0x00))
1477 +                       return 0;
1478 +               udelay(REGISTER_BUSY_DELAY);
1479 +       }
1480 +
1481 +       ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1482 +       return -EACCES;
1483 +}
1484 +
1485 +static int rt2800pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1486 +{
1487 +       unsigned int i;
1488 +       u16 eeprom;
1489 +       u8 reg_id;
1490 +       u8 value;
1491 +
1492 +       if (unlikely(rt2800pci_wait_bbp_rf_ready(rt2x00dev) ||
1493 +                    rt2800pci_wait_bbp_ready(rt2x00dev)))
1494 +               return -EACCES;
1495 +
1496 +       rt2800pci_bbp_write(rt2x00dev, 65, 0x2c);
1497 +       rt2800pci_bbp_write(rt2x00dev, 66, 0x38);
1498 +       rt2800pci_bbp_write(rt2x00dev, 69, 0x12);
1499 +       rt2800pci_bbp_write(rt2x00dev, 70, 0x0a);
1500 +       rt2800pci_bbp_write(rt2x00dev, 73, 0x10);
1501 +       rt2800pci_bbp_write(rt2x00dev, 81, 0x37);
1502 +       rt2800pci_bbp_write(rt2x00dev, 82, 0x62);
1503 +       rt2800pci_bbp_write(rt2x00dev, 83, 0x6a);
1504 +       rt2800pci_bbp_write(rt2x00dev, 84, 0x99);
1505 +       rt2800pci_bbp_write(rt2x00dev, 86, 0x00);
1506 +       rt2800pci_bbp_write(rt2x00dev, 91, 0x04);
1507 +       rt2800pci_bbp_write(rt2x00dev, 92, 0x00);
1508 +       rt2800pci_bbp_write(rt2x00dev, 103, 0x00);
1509 +       rt2800pci_bbp_write(rt2x00dev, 105, 0x05);
1510 +
1511 +       if (rt2x00_rev(&rt2x00dev->chip) == RT2860_VERSION_C) {
1512 +               rt2800pci_bbp_write(rt2x00dev, 69, 0x16);
1513 +               rt2800pci_bbp_write(rt2x00dev, 73, 0x12);
1514 +       }
1515 +
1516 +       if (rt2x00_rev(&rt2x00dev->chip) == RT2860_VERSION_D)
1517 +               rt2800pci_bbp_write(rt2x00dev, 84, 0x19);
1518 +
1519 +       for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1520 +               rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1521 +
1522 +               if (eeprom != 0xffff && eeprom != 0x0000) {
1523 +                       reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1524 +                       value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1525 +                       rt2800pci_bbp_write(rt2x00dev, reg_id, value);
1526 +               }
1527 +       }
1528 +
1529 +       return 0;
1530 +}
1531 +
1532 +/*
1533 + * Device state switch handlers.
1534 + */
1535 +static void rt2800pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1536 +                               enum dev_state state)
1537 +{
1538 +       u32 reg;
1539 +
1540 +       rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1541 +       rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
1542 +                          (state == STATE_RADIO_RX_ON) ||
1543 +                          (state == STATE_RADIO_RX_ON_LINK));
1544 +       rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1545 +}
1546 +
1547 +static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1548 +                                enum dev_state state)
1549 +{
1550 +       int mask = (state == STATE_RADIO_IRQ_ON);
1551 +       u32 reg;
1552 +
1553 +       /*
1554 +        * When interrupts are being enabled, the interrupt registers
1555 +        * should clear the register to assure a clean state.
1556 +        */
1557 +       if (state == STATE_RADIO_IRQ_ON) {
1558 +               rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1559 +               rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1560 +       }
1561 +
1562 +       rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1563 +       rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, mask);
1564 +       rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, mask);
1565 +       rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask);
1566 +       rt2x00_set_field32(&reg, INT_MASK_CSR_AC0_DMA_DONE, mask);
1567 +       rt2x00_set_field32(&reg, INT_MASK_CSR_AC1_DMA_DONE, mask);
1568 +       rt2x00_set_field32(&reg, INT_MASK_CSR_AC2_DMA_DONE, mask);
1569 +       rt2x00_set_field32(&reg, INT_MASK_CSR_AC3_DMA_DONE, mask);
1570 +       rt2x00_set_field32(&reg, INT_MASK_CSR_HCCA_DMA_DONE, mask);
1571 +       rt2x00_set_field32(&reg, INT_MASK_CSR_MGMT_DMA_DONE, mask);
1572 +       rt2x00_set_field32(&reg, INT_MASK_CSR_MCU_COMMAND, mask);
1573 +       rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, mask);
1574 +       rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, mask);
1575 +       rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1576 +}
1577 +
1578 +static int rt2800pci_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
1579 +{
1580 +       unsigned int i;
1581 +       u32 reg;
1582 +
1583 +       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1584 +               rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1585 +               if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
1586 +                   !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
1587 +                       return 0;
1588 +
1589 +               msleep(1);
1590 +       }
1591 +
1592 +       ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
1593 +       return -EACCES;
1594 +}
1595 +
1596 +static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1597 +{
1598 +       u32 reg;
1599 +       u16 word;
1600 +
1601 +       /*
1602 +        * Initialize all registers.
1603 +        */
1604 +       if (unlikely(rt2800pci_wait_wpdma_ready(rt2x00dev) ||
1605 +                    rt2800pci_init_queues(rt2x00dev) ||
1606 +                    rt2800pci_init_registers(rt2x00dev) ||
1607 +                    rt2800pci_init_bbp(rt2x00dev)))
1608 +               return -EIO;
1609 +
1610 +       rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001a80);
1611 +
1612 +       /* Wait for DMA, ignore error */
1613 +       rt2800pci_wait_wpdma_ready(rt2x00dev);
1614 +
1615 +       /*
1616 +        * Enable RX.
1617 +        */
1618 +       rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1619 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
1620 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
1621 +       rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1622 +
1623 +       rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1624 +       rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
1625 +       rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
1626 +       rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1627 +
1628 +       /*
1629 +        * Initialize LED control
1630 +        */
1631 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
1632 +       rt2800pci_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
1633 +                             word & 0xff, (word >> 8) & 0xff);
1634 +
1635 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
1636 +       rt2800pci_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
1637 +                             word & 0xff, (word >> 8) & 0xff);
1638 +
1639 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
1640 +       rt2800pci_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
1641 +                             word & 0xff, (word >> 8) & 0xff);
1642 +
1643 +       rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1644 +       rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1645 +
1646 +       /*
1647 +        * Send signal to firmware during boot time.
1648 +        */
1649 +       rt2800pci_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0);
1650 +
1651 +       return 0;
1652 +}
1653 +
1654 +static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1655 +{
1656 +       u32 reg;
1657 +
1658 +       rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1659 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1660 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1661 +       rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1662 +
1663 +       rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
1664 +       rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0);
1665 +       rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, 0);
1666 +
1667 +       rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001280);
1668 +
1669 +       /* Wait for DMA, ignore error */
1670 +       rt2800pci_wait_wpdma_ready(rt2x00dev);
1671 +}
1672 +
1673 +static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
1674 +                              enum dev_state state)
1675 +{
1676 +       rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1677 +
1678 +       if (state == STATE_AWAKE)
1679 +               rt2800pci_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
1680 +       else
1681 +               rt2800pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
1682 +
1683 +       return 0;
1684 +}
1685 +
1686 +static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1687 +                                     enum dev_state state)
1688 +{
1689 +       int retval = 0;
1690 +
1691 +       switch (state) {
1692 +       case STATE_RADIO_ON:
1693 +               /*
1694 +                * Before the radio can be enabled, the device first has
1695 +                * to be woken up. After that it needs a bit of time
1696 +                * to be fully awake and the radio can be enabled.
1697 +                */
1698 +               rt2800pci_set_state(rt2x00dev, STATE_AWAKE);
1699 +               msleep(1);
1700 +               retval = rt2800pci_enable_radio(rt2x00dev);
1701 +               break;
1702 +       case STATE_RADIO_OFF:
1703 +               /*
1704 +                * After the radio has been disablee, the device should
1705 +                * be put to sleep for powersaving.
1706 +                */
1707 +               rt2800pci_disable_radio(rt2x00dev);
1708 +               rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
1709 +               break;
1710 +       case STATE_RADIO_RX_ON:
1711 +       case STATE_RADIO_RX_ON_LINK:
1712 +       case STATE_RADIO_RX_OFF:
1713 +       case STATE_RADIO_RX_OFF_LINK:
1714 +               rt2800pci_toggle_rx(rt2x00dev, state);
1715 +               break;
1716 +       case STATE_RADIO_IRQ_ON:
1717 +       case STATE_RADIO_IRQ_OFF:
1718 +               rt2800pci_toggle_irq(rt2x00dev, state);
1719 +               break;
1720 +       case STATE_DEEP_SLEEP:
1721 +       case STATE_SLEEP:
1722 +       case STATE_STANDBY:
1723 +       case STATE_AWAKE:
1724 +               retval = rt2800pci_set_state(rt2x00dev, state);
1725 +               break;
1726 +       default:
1727 +               retval = -ENOTSUPP;
1728 +               break;
1729 +       }
1730 +
1731 +       if (unlikely(retval))
1732 +               ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1733 +                     state, retval);
1734 +
1735 +       return retval;
1736 +}
1737 +
1738 +/*
1739 + * TX descriptor initialization
1740 + */
1741 +static void rt2800pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1742 +                                   struct sk_buff *skb,
1743 +                                   struct txentry_desc *txdesc)
1744 +{
1745 +       struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1746 +       __le32 *txd = skbdesc->desc;
1747 +       __le32 *txwi = (__le32 *)(skb->data - rt2x00dev->hw->extra_tx_headroom);
1748 +       u32 word;
1749 +
1750 +       /*
1751 +        * Initialize TX Info descriptor
1752 +        */
1753 +       rt2x00_desc_read(txwi, 0, &word);
1754 +       rt2x00_set_field32(&word, TXWI_W0_FRAG,
1755 +                          test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags) ||
1756 +                          test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1757 +       rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
1758 +       rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
1759 +       rt2x00_set_field32(&word, TXWI_W0_TS,
1760 +                          test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1761 +       rt2x00_set_field32(&word, TXWI_W0_AMPDU,
1762 +                          test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
1763 +       rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
1764 +       rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->ifs);
1765 +       rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
1766 +       rt2x00_set_field32(&word, TXWI_W0_BW,
1767 +                          test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
1768 +       rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
1769 +                          test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
1770 +       rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
1771 +       rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
1772 +       rt2x00_desc_write(txwi, 0, word);
1773 +
1774 +       rt2x00_desc_read(txwi, 1, &word);
1775 +       rt2x00_set_field32(&word, TXWI_W1_ACK,
1776 +                          test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1777 +       rt2x00_set_field32(&word, TXWI_W1_ACK,
1778 +                          test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags));
1779 +       rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
1780 +       rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID, 0xff);
1781 +       rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT, skb->len);
1782 +       rt2x00_set_field32(&word, TXWI_W1_PACKETID,
1783 +                          skbdesc->entry->entry_idx);
1784 +       rt2x00_desc_write(txwi, 1, word);
1785 +
1786 +       if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1787 +               _rt2x00_desc_write(txwi, 2, skbdesc->iv);
1788 +               _rt2x00_desc_write(txwi, 3, skbdesc->eiv);
1789 +       }
1790 +
1791 +       /*
1792 +        * Initialize TX descriptor
1793 +        */
1794 +       rt2x00_desc_read(txd, 0, &word);
1795 +       rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
1796 +       rt2x00_desc_write(txd, 0, word);
1797 +
1798 +       rt2x00_desc_read(txd, 1, &word);
1799 +       rt2x00_set_field32(&word, TXD_W1_SD_LEN1, skb->len);
1800 +       rt2x00_set_field32(&word, TXD_W1_LAST_SEC1, 1);
1801 +       rt2x00_set_field32(&word, TXD_W1_BURST,
1802 +                          test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1803 +       rt2x00_set_field32(&word, TXD_W1_SD_LEN0,
1804 +                          rt2x00dev->hw->extra_tx_headroom);
1805 +       rt2x00_set_field32(&word, TXD_W1_LAST_SEC0,
1806 +                          !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1807 +       rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
1808 +       rt2x00_desc_write(txd, 1, word);
1809 +
1810 +       rt2x00_desc_read(txd, 2, &word);
1811 +       rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
1812 +                          skbdesc->skb_dma + rt2x00dev->hw->extra_tx_headroom);
1813 +       rt2x00_desc_write(txd, 2, word);
1814 +
1815 +       rt2x00_desc_read(txd, 3, &word);
1816 +       rt2x00_set_field32(&word, TXD_W3_WIV, 1);
1817 +       rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
1818 +       rt2x00_desc_write(txd, 3, word);
1819 +}
1820 +
1821 +/*
1822 + * TX data initialization
1823 + */
1824 +static void rt2800pci_write_beacon(struct queue_entry *entry)
1825 +{
1826 +       struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1827 +       struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1828 +       unsigned int beacon_base;
1829 +       u32 reg;
1830 +
1831 +       /*
1832 +        * Disable beaconing while we are reloading the beacon data,
1833 +        * otherwise we might be sending out invalid data.
1834 +        */
1835 +       rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1836 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1837 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1838 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1839 +       rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1840 +
1841 +       /*
1842 +        * Write entire beacon with descriptor to register.
1843 +        */
1844 +       beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1845 +       rt2x00pci_register_multiwrite(rt2x00dev,
1846 +                                     beacon_base,
1847 +                                     skbdesc->desc, skbdesc->desc_len);
1848 +       rt2x00pci_register_multiwrite(rt2x00dev,
1849 +                                     beacon_base + skbdesc->desc_len,
1850 +                                     entry->skb->data, entry->skb->len);
1851 +
1852 +       /*
1853 +        * Clean up beacon skb.
1854 +        */
1855 +       dev_kfree_skb_any(entry->skb);
1856 +       entry->skb = NULL;
1857 +}
1858 +
1859 +static void rt2800pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1860 +                                   const enum data_queue_qid queue_idx)
1861 +{
1862 +       struct data_queue *queue;
1863 +       unsigned int idx, qidx = 0;
1864 +       u32 reg;
1865 +
1866 +       if (queue_idx == QID_BEACON) {
1867 +               rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1868 +               if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
1869 +                       rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
1870 +                       rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
1871 +                       rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
1872 +                       rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1873 +               }
1874 +               return;
1875 +       }
1876 +
1877 +       if (queue_idx > QID_HCCA && queue_idx != QID_MGMT)
1878 +               return;
1879 +
1880 +       queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1881 +       idx = queue->index[Q_INDEX];
1882 +
1883 +       if (queue_idx == QID_MGMT)
1884 +               qidx = 5;
1885 +       else
1886 +               qidx = queue_idx;
1887 +
1888 +       rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX(qidx), idx);
1889 +}
1890 +
1891 +/*
1892 + * RX control handlers
1893 + */
1894 +static void rt2800pci_fill_rxdone(struct queue_entry *entry,
1895 +                                 struct rxdone_entry_desc *rxdesc)
1896 +{
1897 +       struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1898 +       struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1899 +       __le32 *rxd = entry_priv->desc;
1900 +       __le32 *rxwi = (__le32 *)entry->skb->data;
1901 +       u32 rxd3;
1902 +       u32 rxwi0;
1903 +       u32 rxwi1;
1904 +       u32 rxwi2;
1905 +       u32 rxwi3;
1906 +       u8 mcs;
1907 +       u8 mode;
1908 +
1909 +       rt2x00_desc_read(rxd, 3, &rxd3);
1910 +       rt2x00_desc_read(rxwi, 0, &rxwi0);
1911 +       rt2x00_desc_read(rxwi, 1, &rxwi1);
1912 +       rt2x00_desc_read(rxwi, 2, &rxwi2);
1913 +       rt2x00_desc_read(rxwi, 3, &rxwi3);
1914 +
1915 +       if (rt2x00_get_field32(rxd3, RXD_W3_CRC_ERROR))
1916 +               rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1917 +
1918 +       if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
1919 +               /*
1920 +                * FIXME: Set cipher on WEP64 when it has been decrypted,
1921 +                * at the moment we cannot determine the real cipher type yet.
1922 +                */
1923 +               rxdesc->cipher =
1924 +                   rt2x00_get_field32(rxd3, RXD_W3_DECRYPTED);
1925 +               rxdesc->cipher_status =
1926 +                   rt2x00_get_field32(rxd3, RXD_W3_CIPHER_ERROR);
1927 +       }
1928 +
1929 +       if (rxdesc->cipher != CIPHER_NONE) {
1930 +               /*
1931 +                * Hardware has stripped IV/EIV data from 802.11 frame during
1932 +                * decryption. It has provided the data seperately but rt2x00lib
1933 +                * should decide if it should be reinserted.
1934 +                */
1935 +               rxdesc->flags |= RX_FLAG_IV_STRIPPED;
1936 +
1937 +               if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
1938 +                       rxdesc->flags |= RX_FLAG_DECRYPTED;
1939 +               else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
1940 +                       rxdesc->flags |= RX_FLAG_MMIC_ERROR;
1941 +       }
1942 +
1943 +       if (rt2x00_get_field32(rxd3, RXD_W3_MY_BSS))
1944 +               rxdesc->dev_flags |= RXDONE_MY_BSS;
1945 +
1946 +       /*
1947 +        * Create the MCS value, when the mode is CCK, mask of 0x8 bit
1948 +        * to remove the short preamble flag.
1949 +        */
1950 +       mode = rt2x00_get_field32(rxwi1, RXWI_W1_PHYMODE);
1951 +       mcs = rt2x00_get_field32(rxwi1, RXWI_W1_MCS);
1952 +
1953 +       if (mode == RATE_MODE_CCK)
1954 +               mcs &= ~0x8;
1955 +
1956 +       rxdesc->signal = (mode << 8) | mcs;
1957 +
1958 +       rxdesc->rssi =
1959 +           (rt2x00_get_field32(rxwi2, RXWI_W2_RSSI0) +
1960 +            rt2x00_get_field32(rxwi2, RXWI_W2_RSSI1) +
1961 +            rt2x00_get_field32(rxwi2, RXWI_W2_RSSI2)) / 3;
1962 +
1963 +       rxdesc->noise =
1964 +           (rt2x00_get_field32(rxwi3, RXWI_W3_SNR0) +
1965 +            rt2x00_get_field32(rxwi3, RXWI_W3_SNR1)) / 2;
1966 +
1967 +       rxdesc->size = rt2x00_get_field32(rxwi0, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
1968 +
1969 +       /*
1970 +        * Remove TXWI descriptor from start of buffer.
1971 +        */
1972 +       skb_pull(entry->skb, TXWI_DESC_SIZE);
1973 +       skb_trim(entry->skb, rxdesc->size);
1974 +}
1975 +
1976 +/*
1977 + * Interrupt functions.
1978 + */
1979 +static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
1980 +{
1981 +       struct rt2x00_dev *rt2x00dev = dev_instance;
1982 +       u32 reg;
1983 +
1984 +       /* Read status and ACK all interrupts */
1985 +       rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1986 +       rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1987 +
1988 +       if (!reg)
1989 +               return IRQ_NONE;
1990 +
1991 +       if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1992 +               return IRQ_HANDLED;
1993 +
1994 +       /*
1995 +        * 1 - Rx ring done interrupt.
1996 +        */
1997 +       if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
1998 +               rt2x00pci_rxdone(rt2x00dev);
1999 +
2000 +       /* TODO: TX DONE */
2001 +
2002 +       return IRQ_HANDLED;
2003 +}
2004 +
2005 +/*
2006 + * Device probe functions.
2007 + */
2008 +static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2009 +{
2010 +       struct eeprom_93cx6 eeprom;
2011 +       u32 reg;
2012 +       u16 word;
2013 +       u8 *mac;
2014 +       u8 default_lna_gain;
2015 +
2016 +       rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
2017 +
2018 +       eeprom.data = rt2x00dev;
2019 +       eeprom.register_read = rt2800pci_eepromregister_read;
2020 +       eeprom.register_write = rt2800pci_eepromregister_write;
2021 +       eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
2022 +           PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
2023 +       eeprom.reg_data_in = 0;
2024 +       eeprom.reg_data_out = 0;
2025 +       eeprom.reg_data_clock = 0;
2026 +       eeprom.reg_chip_select = 0;
2027 +
2028 +       eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
2029 +                              EEPROM_SIZE / sizeof(u16));
2030 +
2031 +       /*
2032 +        * Start validation of the data that has been read.
2033 +        */
2034 +       mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2035 +       if (!is_valid_ether_addr(mac)) {
2036 +               DECLARE_MAC_BUF(macbuf);
2037 +
2038 +               random_ether_addr(mac);
2039 +               EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
2040 +       }
2041 +
2042 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2043 +       if (word == 0xffff) {
2044 +               rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2045 +               rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
2046 +               rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
2047 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2048 +               EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2049 +       }
2050 +
2051 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2052 +       if (word != 0) {
2053 +               /* NIC configuration must always be 0. */
2054 +               word = 0;
2055 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2056 +               EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2057 +       }
2058 +
2059 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2060 +       if ((word & 0x00ff) == 0x00ff) {
2061 +               rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2062 +               rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2063 +                                  LED_MODE_TXRX_ACTIVITY);
2064 +               rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2065 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2066 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
2067 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
2068 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
2069 +               EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2070 +       }
2071 +
2072 +       /*
2073 +        * During the LNA validation we are going to use
2074 +        * lna0 as correct value. Note that EEPROM_LNA
2075 +        * is never validated.
2076 +        */
2077 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2078 +       default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2079 +
2080 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2081 +       if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2082 +               rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2083 +       if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2084 +               rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2085 +       rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2086 +
2087 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2088 +       if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2089 +               rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2090 +       if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2091 +           rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2092 +               rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2093 +                                  default_lna_gain);
2094 +       rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2095 +
2096 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2097 +       if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2098 +               rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2099 +       if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2100 +               rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2101 +       rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2102 +
2103 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2104 +       if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2105 +               rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2106 +       if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2107 +           rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2108 +               rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2109 +                                  default_lna_gain);
2110 +       rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2111 +
2112 +       return 0;
2113 +}
2114 +
2115 +static int rt2800pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2116 +{
2117 +       u32 reg;
2118 +       u16 value;
2119 +       u16 eeprom;
2120 +       u16 device;
2121 +
2122 +       /*
2123 +        * Read EEPROM word for configuration.
2124 +        */
2125 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2126 +
2127 +       /*
2128 +        * Identify RF chipset.
2129 +        * To determine the RT chip we have to read the
2130 +        * PCI header of the device.
2131 +        */
2132 +       pci_read_config_word(to_pci_dev(rt2x00dev->dev),
2133 +                            PCI_CONFIG_HEADER_DEVICE, &device);
2134 +       value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2135 +       rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
2136 +       reg = rt2x00_get_field32(reg, MAC_CSR0_ASIC_REV);
2137 +       rt2x00_set_chip(rt2x00dev, device, value, reg);
2138 +
2139 +       if (!rt2x00_rf(&rt2x00dev->chip, RF2820) &&
2140 +           !rt2x00_rf(&rt2x00dev->chip, RF2850) &&
2141 +           !rt2x00_rf(&rt2x00dev->chip, RF2720) &&
2142 +           !rt2x00_rf(&rt2x00dev->chip, RF2750)) {
2143 +               ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2144 +               return -ENODEV;
2145 +       }
2146 +
2147 +       /*
2148 +        * Read frequency offset and RF programming sequence.
2149 +        */
2150 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2151 +       rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2152 +
2153 +       /*
2154 +        * Read external LNA informations.
2155 +        */
2156 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2157 +
2158 +       if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2159 +               __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2160 +       if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2161 +               __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2162 +
2163 +       /*
2164 +        * Detect if this device has an hardware controlled radio.
2165 +        */
2166 +#ifdef CONFIG_RT2X00_LIB_RFKILL
2167 +       if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
2168 +               __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2169 +#endif /* CONFIG_RT2X00_LIB_RFKILL */
2170 +
2171 +       /*
2172 +        * Store led settings, for correct led behaviour.
2173 +        */
2174 +#ifdef CONFIG_RT2X00_LIB_LEDS
2175 +       rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2176 +       rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2177 +       rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2178 +
2179 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
2180 +#endif /* CONFIG_RT2X00_LIB_LEDS */
2181 +
2182 +       return 0;
2183 +}
2184 +
2185 +/*
2186 + * RF value list for rt2860
2187 + * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
2188 + */
2189 +static const struct rf_channel rf_vals[] = {
2190 +       { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
2191 +       { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
2192 +       { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
2193 +       { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
2194 +       { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
2195 +       { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
2196 +       { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
2197 +       { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
2198 +       { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
2199 +       { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
2200 +       { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
2201 +       { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
2202 +       { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
2203 +       { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
2204 +
2205 +       /* 802.11 UNI / HyperLan 2 */
2206 +       { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
2207 +       { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
2208 +       { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
2209 +       { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
2210 +       { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
2211 +       { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
2212 +       { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
2213 +       { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
2214 +       { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
2215 +       { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
2216 +       { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
2217 +       { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
2218 +
2219 +       /* 802.11 HyperLan 2 */
2220 +       { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
2221 +       { 102, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed793 },
2222 +       { 104, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed1a3 },
2223 +       { 108, 0x18402ecc, 0x184c0a32, 0x18178a55, 0x180ed193 },
2224 +       { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
2225 +       { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
2226 +       { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
2227 +       { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
2228 +       { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2229 +       { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2230 +       { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2231 +       { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2232 +       { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2233 +       { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2234 +       { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2235 +       { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2236 +
2237 +       /* 802.11 UNII */
2238 +       { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2239 +       { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2240 +       { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2241 +       { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2242 +       { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2243 +       { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2244 +       { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2245 +
2246 +       /* 802.11 Japan */
2247 +       { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2248 +       { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2249 +       { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2250 +       { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2251 +       { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2252 +       { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2253 +       { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2254 +};
2255 +
2256 +static int rt2800pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2257 +{
2258 +       struct hw_mode_spec *spec = &rt2x00dev->spec;
2259 +       struct channel_info *info;
2260 +       char *tx_power1;
2261 +       char *tx_power2;
2262 +       unsigned int i;
2263 +
2264 +       /*
2265 +        * Initialize all hw fields.
2266 +        */
2267 +       rt2x00dev->hw->flags =
2268 +           IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2269 +           IEEE80211_HW_SIGNAL_DBM;
2270 +       rt2x00dev->hw->extra_tx_headroom = TXWI_DESC_SIZE;
2271 +
2272 +       SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2273 +       SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2274 +                               rt2x00_eeprom_addr(rt2x00dev,
2275 +                                                  EEPROM_MAC_ADDR_0));
2276 +
2277 +       /*
2278 +        * Initialize hw_mode information.
2279 +        */
2280 +       spec->supported_bands = SUPPORT_BAND_2GHZ;
2281 +       spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2282 +
2283 +       if (rt2x00_rf(&rt2x00dev->chip, RF2820) ||
2284 +           rt2x00_rf(&rt2x00dev->chip, RF2720)) {
2285 +               spec->num_channels = 14;
2286 +               spec->channels = rf_vals;
2287 +       } else if (rt2x00_rf(&rt2x00dev->chip, RF2850) ||
2288 +                  rt2x00_rf(&rt2x00dev->chip, RF2750)) {
2289 +               spec->supported_bands |= SUPPORT_BAND_5GHZ;
2290 +               spec->num_channels = ARRAY_SIZE(rf_vals);
2291 +               spec->channels = rf_vals;
2292 +       }
2293 +
2294 +       /*
2295 +        * Create channel information array
2296 +        */
2297 +       info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2298 +       if (!info)
2299 +               return -ENOMEM;
2300 +
2301 +       spec->channels_info = info;
2302 +
2303 +       tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2304 +       tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2305 +
2306 +       for (i = 0; i < 14; i++) {
2307 +               info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
2308 +               info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
2309 +       }
2310 +
2311 +       if (spec->num_channels > 14) {
2312 +               tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
2313 +               tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
2314 +
2315 +               for (i = 14; i < spec->num_channels; i++) {
2316 +                       info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
2317 +                       info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
2318 +               }
2319 +       }
2320 +
2321 +       return 0;
2322 +}
2323 +
2324 +static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2325 +{
2326 +       int retval;
2327 +
2328 +       /*
2329 +        * Allocate eeprom data.
2330 +        */
2331 +       retval = rt2800pci_validate_eeprom(rt2x00dev);
2332 +       if (retval)
2333 +               return retval;
2334 +
2335 +       retval = rt2800pci_init_eeprom(rt2x00dev);
2336 +       if (retval)
2337 +               return retval;
2338 +
2339 +       /*
2340 +        * Initialize hw specifications.
2341 +        */
2342 +       retval = rt2800pci_probe_hw_mode(rt2x00dev);
2343 +       if (retval)
2344 +               return retval;
2345 +
2346 +       /*
2347 +        * This device requires firmware.
2348 +        */
2349 +       __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2350 +       if (!modparam_nohwcrypt)
2351 +               __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2352 +
2353 +       /*
2354 +        * Set the rssi offset.
2355 +        */
2356 +       rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2357 +
2358 +       return 0;
2359 +}
2360 +
2361 +/*
2362 + * IEEE80211 stack callback functions.
2363 + */
2364 +static int rt2800pci_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2365 +{
2366 +       struct rt2x00_dev *rt2x00dev = hw->priv;
2367 +       u32 reg;
2368 +
2369 +       rt2x00pci_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2370 +       rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
2371 +       rt2x00pci_register_write(rt2x00dev, TX_RTS_CFG, reg);
2372 +
2373 +       rt2x00pci_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2374 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
2375 +       rt2x00pci_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2376 +
2377 +       rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2378 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
2379 +       rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2380 +
2381 +       rt2x00pci_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2382 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 1);
2383 +       rt2x00pci_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2384 +
2385 +       rt2x00pci_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2386 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 1);
2387 +       rt2x00pci_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2388 +
2389 +       rt2x00pci_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2390 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 1);
2391 +       rt2x00pci_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2392 +
2393 +       rt2x00pci_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2394 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 1);
2395 +       rt2x00pci_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2396 +
2397 +       return 0;
2398 +}
2399 +
2400 +static int rt2800pci_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2401 +                            const struct ieee80211_tx_queue_params *params)
2402 +{
2403 +       struct rt2x00_dev *rt2x00dev = hw->priv;
2404 +       struct data_queue *queue;
2405 +       struct rt2x00_field32 field;
2406 +       int retval;
2407 +       u32 reg;
2408 +       u32 offset;
2409 +
2410 +       /*
2411 +        * First pass the configuration through rt2x00lib, that will
2412 +        * update the queue settings and validate the input. After that
2413 +        * we are free to update the registers based on the value
2414 +        * in the queue parameter.
2415 +        */
2416 +       retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2417 +       if (retval)
2418 +               return retval;
2419 +
2420 +       queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2421 +
2422 +       /* Update WMM TXOP register */
2423 +       if (queue_idx < 2) {
2424 +               field.bit_offset = queue_idx * 16;
2425 +               field.bit_mask = 0xffff << field.bit_offset;
2426 +
2427 +               rt2x00pci_register_read(rt2x00dev, WMM_TXOP0_CFG, &reg);
2428 +               rt2x00_set_field32(&reg, field, queue->txop);
2429 +               rt2x00pci_register_write(rt2x00dev, WMM_TXOP0_CFG, reg);
2430 +       } else if (queue_idx < 4) {
2431 +               field.bit_offset = (queue_idx - 2) * 16;
2432 +               field.bit_mask = 0xffff << field.bit_offset;
2433 +
2434 +               rt2x00pci_register_read(rt2x00dev, WMM_TXOP1_CFG, &reg);
2435 +               rt2x00_set_field32(&reg, field, queue->txop);
2436 +               rt2x00pci_register_write(rt2x00dev, WMM_TXOP1_CFG, reg);
2437 +       }
2438 +
2439 +       /* Update WMM registers */
2440 +       field.bit_offset = queue_idx * 4;
2441 +       field.bit_mask = 0xf << field.bit_offset;
2442 +
2443 +       rt2x00pci_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
2444 +       rt2x00_set_field32(&reg, field, queue->aifs);
2445 +       rt2x00pci_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
2446 +
2447 +       rt2x00pci_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
2448 +       rt2x00_set_field32(&reg, field, queue->cw_min);
2449 +       rt2x00pci_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
2450 +
2451 +       rt2x00pci_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
2452 +       rt2x00_set_field32(&reg, field, queue->cw_max);
2453 +       rt2x00pci_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
2454 +
2455 +       /* Update EDCA registers */
2456 +       if (queue_idx < 4) {
2457 +               offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
2458 +
2459 +               rt2x00pci_register_read(rt2x00dev, offset, &reg);
2460 +               rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
2461 +               rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
2462 +               rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
2463 +               rt2x00pci_register_write(rt2x00dev, offset, reg);
2464 +       }
2465 +
2466 +       return 0;
2467 +}
2468 +
2469 +static u64 rt2800pci_get_tsf(struct ieee80211_hw *hw)
2470 +{
2471 +       struct rt2x00_dev *rt2x00dev = hw->priv;
2472 +       u64 tsf;
2473 +       u32 reg;
2474 +
2475 +       rt2x00pci_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
2476 +       tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
2477 +       rt2x00pci_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
2478 +       tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
2479 +
2480 +       return tsf;
2481 +}
2482 +
2483 +static const struct ieee80211_ops rt2800pci_mac80211_ops = {
2484 +       .tx                     = rt2x00mac_tx,
2485 +       .start                  = rt2x00mac_start,
2486 +       .stop                   = rt2x00mac_stop,
2487 +       .add_interface          = rt2x00mac_add_interface,
2488 +       .remove_interface       = rt2x00mac_remove_interface,
2489 +       .config                 = rt2x00mac_config,
2490 +       .config_interface       = rt2x00mac_config_interface,
2491 +       .configure_filter       = rt2x00mac_configure_filter,
2492 +       .set_key                = rt2x00mac_set_key,
2493 +       .get_stats              = rt2x00mac_get_stats,
2494 +       .set_rts_threshold      = rt2800pci_set_rts_threshold,
2495 +       .bss_info_changed       = rt2x00mac_bss_info_changed,
2496 +       .conf_tx                = rt2800pci_conf_tx,
2497 +       .get_tx_stats           = rt2x00mac_get_tx_stats,
2498 +       .get_tsf                = rt2800pci_get_tsf,
2499 +};
2500 +
2501 +static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
2502 +       .irq_handler            = rt2800pci_interrupt,
2503 +       .probe_hw               = rt2800pci_probe_hw,
2504 +       .get_firmware_name      = rt2800pci_get_firmware_name,
2505 +       .get_firmware_crc       = rt2800pci_get_firmware_crc,
2506 +       .load_firmware          = rt2800pci_load_firmware,
2507 +       .initialize             = rt2x00pci_initialize,
2508 +       .uninitialize           = rt2x00pci_uninitialize,
2509 +       .get_entry_state        = rt2800pci_get_entry_state,
2510 +       .clear_entry            = rt2800pci_clear_entry,
2511 +       .set_device_state       = rt2800pci_set_device_state,
2512 +       .rfkill_poll            = rt2800pci_rfkill_poll,
2513 +       .link_stats             = rt2800pci_link_stats,
2514 +       .reset_tuner            = rt2800pci_reset_tuner,
2515 +       .link_tuner             = rt2800pci_link_tuner,
2516 +       .write_tx_desc          = rt2800pci_write_tx_desc,
2517 +       .write_tx_data          = rt2x00pci_write_tx_data,
2518 +       .write_beacon           = rt2800pci_write_beacon,
2519 +       .kick_tx_queue          = rt2800pci_kick_tx_queue,
2520 +       .fill_rxdone            = rt2800pci_fill_rxdone,
2521 +       .config_shared_key      = rt2800pci_config_shared_key,
2522 +       .config_pairwise_key    = rt2800pci_config_pairwise_key,
2523 +       .config_filter          = rt2800pci_config_filter,
2524 +       .config_intf            = rt2800pci_config_intf,
2525 +       .config_erp             = rt2800pci_config_erp,
2526 +       .config_ant             = rt2800pci_config_ant,
2527 +       .config                 = rt2800pci_config,
2528 +};
2529 +
2530 +static const struct data_queue_desc rt2800pci_queue_rx = {
2531 +       .entry_num              = RX_ENTRIES,
2532 +       .data_size              = DATA_FRAME_SIZE,
2533 +       .desc_size              = RXD_DESC_SIZE,
2534 +       .priv_size              = sizeof(struct queue_entry_priv_pci),
2535 +};
2536 +
2537 +static const struct data_queue_desc rt2800pci_queue_tx = {
2538 +       .entry_num              = TX_ENTRIES,
2539 +       .data_size              = DATA_FRAME_SIZE,
2540 +       .desc_size              = TXD_DESC_SIZE,
2541 +       .priv_size              = sizeof(struct queue_entry_priv_pci),
2542 +};
2543 +
2544 +static const struct data_queue_desc rt2800pci_queue_bcn = {
2545 +       .entry_num              = 8 * BEACON_ENTRIES,
2546 +       .data_size              = 0, /* No DMA required for beacons */
2547 +       .desc_size              = TXWI_DESC_SIZE,
2548 +       .priv_size              = sizeof(struct queue_entry_priv_pci),
2549 +};
2550 +
2551 +static const struct rt2x00_ops rt2800pci_ops = {
2552 +       .name           = KBUILD_MODNAME,
2553 +       .max_sta_intf   = 1,
2554 +       .max_ap_intf    = 8,
2555 +       .eeprom_size    = EEPROM_SIZE,
2556 +       .rf_size        = RF_SIZE,
2557 +       .tx_queues      = NUM_TX_QUEUES,
2558 +       .rx             = &rt2800pci_queue_rx,
2559 +       .tx             = &rt2800pci_queue_tx,
2560 +       .bcn            = &rt2800pci_queue_bcn,
2561 +       .lib            = &rt2800pci_rt2x00_ops,
2562 +       .hw             = &rt2800pci_mac80211_ops,
2563 +#ifdef CONFIG_RT2X00_LIB_DEBUGFS
2564 +       .debugfs        = &rt2800pci_rt2x00debug,
2565 +#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2566 +};
2567 +
2568 +/*
2569 + * RT2800pci module information.
2570 + */
2571 +static struct pci_device_id rt2800pci_device_table[] = {
2572 +       { PCI_DEVICE(0x1814, 0x0601), PCI_DEVICE_DATA(&rt2800pci_ops) },
2573 +       { PCI_DEVICE(0x1814, 0x0681), PCI_DEVICE_DATA(&rt2800pci_ops) },
2574 +       { PCI_DEVICE(0x1814, 0x0701), PCI_DEVICE_DATA(&rt2800pci_ops) },
2575 +       { PCI_DEVICE(0x1814, 0x0781), PCI_DEVICE_DATA(&rt2800pci_ops) },
2576 +       { PCI_DEVICE(0x1a3b, 0x1059), PCI_DEVICE_DATA(&rt2800pci_ops) },
2577 +       { 0, }
2578 +};
2579 +
2580 +MODULE_AUTHOR(DRV_PROJECT);
2581 +MODULE_VERSION(DRV_VERSION);
2582 +MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
2583 +MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
2584 +MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
2585 +MODULE_FIRMWARE(FIRMWARE_RT2860);
2586 +MODULE_LICENSE("GPL");
2587 +
2588 +static struct pci_driver rt2800pci_driver = {
2589 +       .name           = KBUILD_MODNAME,
2590 +       .id_table       = rt2800pci_device_table,
2591 +       .probe          = rt2x00pci_probe,
2592 +       .remove         = __devexit_p(rt2x00pci_remove),
2593 +       .suspend        = rt2x00pci_suspend,
2594 +       .resume         = rt2x00pci_resume,
2595 +};
2596 +
2597 +static int __init rt2800pci_init(void)
2598 +{
2599 +       return pci_register_driver(&rt2800pci_driver);
2600 +}
2601 +
2602 +static void __exit rt2800pci_exit(void)
2603 +{
2604 +       pci_unregister_driver(&rt2800pci_driver);
2605 +}
2606 +
2607 +module_init(rt2800pci_init);
2608 +module_exit(rt2800pci_exit);
2609 diff --git a/drivers/net/wireless/rt2x00/rt2800pci.h b/drivers/net/wireless/rt2x00/rt2800pci.h
2610 new file mode 100644
2611 index 0000000..66593ed
2612 --- /dev/null
2613 +++ b/drivers/net/wireless/rt2x00/rt2800pci.h
2614 @@ -0,0 +1,1871 @@
2615 +/*
2616 +       Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
2617 +       <http://rt2x00.serialmonkey.com>
2618 +
2619 +       This program is free software; you can redistribute it and/or modify
2620 +       it under the terms of the GNU General Public License as published by
2621 +       the Free Software Foundation; either version 2 of the License, or
2622 +       (at your option) any later version.
2623 +
2624 +       This program is distributed in the hope that it will be useful,
2625 +       but WITHOUT ANY WARRANTY; without even the implied warranty of
2626 +       MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2627 +       GNU General Public License for more details.
2628 +
2629 +       You should have received a copy of the GNU General Public License
2630 +       along with this program; if not, write to the
2631 +       Free Software Foundation, Inc.,
2632 +       59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
2633 + */
2634 +
2635 +/*
2636 +       Module: rt2800pci
2637 +       Abstract: Data structures and registers for the rt2800pci module.
2638 +       Supported chipsets: RT2800E & RT2800ED.
2639 + */
2640 +
2641 +#ifndef RT2800PCI_H
2642 +#define RT2800PCI_H
2643 +
2644 +/*
2645 + * RF chip defines.
2646 + *
2647 + * RF2820 2.4G 2T3R
2648 + * RF2850 2.4G/5G 2T3R
2649 + * RF2720 2.4G 1T2R
2650 + * RF2750 2.4G/5G 1T2R
2651 + */
2652 +#define RF2820                         0x0001
2653 +#define RF2850                         0x0002
2654 +#define RF2720                         0x0003
2655 +#define RF2750                         0x0004
2656 +
2657 +/*
2658 + * RT2860 version
2659 + */
2660 +#define RT2860_VERSION_C               0x0100
2661 +#define RT2860_VERSION_D               0x0101
2662 +#define RT2860_VERSION_E               0x0200
2663 +
2664 +/*
2665 + * Signal information.
2666 + * Defaul offset is required for RSSI <-> dBm conversion.
2667 + */
2668 +#define MAX_SIGNAL                     0 /* FIXME */
2669 +#define MAX_RX_SSI                     0 /* FIXME */
2670 +#define DEFAULT_RSSI_OFFSET            120 /* FIXME */
2671 +
2672 +/*
2673 + * Register layout information.
2674 + */
2675 +#define CSR_REG_BASE                   0x1000
2676 +#define CSR_REG_SIZE                   0x0800
2677 +#define EEPROM_BASE                    0x0000
2678 +#define EEPROM_SIZE                    0x0110
2679 +#define BBP_BASE                       0x0000
2680 +#define BBP_SIZE                       0x0080
2681 +#define RF_BASE                                0x0000
2682 +#define RF_SIZE                                0x0014
2683 +
2684 +/*
2685 + * Number of TX queues.
2686 + */
2687 +#define NUM_TX_QUEUES                  4
2688 +
2689 +/*
2690 + * PCI registers.
2691 + */
2692 +
2693 +/*
2694 + * PCI Configuration Header
2695 + */
2696 +#define PCI_CONFIG_HEADER_VENDOR       0x0000
2697 +#define PCI_CONFIG_HEADER_DEVICE       0x0002
2698 +
2699 +/*
2700 + * E2PROM_CSR: EEPROM control register.
2701 + * RELOAD: Write 1 to reload eeprom content.
2702 + * TYPE_93C46: 1: 93c46, 0:93c66.
2703 + * LOAD_STATUS: 1:loading, 0:done.
2704 + */
2705 +#define E2PROM_CSR                     0x0004
2706 +#define E2PROM_CSR_RELOAD              FIELD32(0x00000001)
2707 +#define E2PROM_CSR_DATA_CLOCK          FIELD32(0x00000002)
2708 +#define E2PROM_CSR_CHIP_SELECT         FIELD32(0x00000004)
2709 +#define E2PROM_CSR_DATA_IN             FIELD32(0x00000008)
2710 +#define E2PROM_CSR_DATA_OUT            FIELD32(0x00000010)
2711 +#define E2PROM_CSR_TYPE_93C46          FIELD32(0x00000020)
2712 +#define E2PROM_CSR_LOAD_STATUS         FIELD32(0x00000040)
2713 +
2714 +/*
2715 + * HOST-MCU shared memory
2716 + */
2717 +#define HOST_CMD_CSR                   0x0404
2718 +#define HOST_CMD_CSR_HOST_COMMAND      FIELD32(0x000000ff)
2719 +
2720 +/*
2721 + * INT_SOURCE_CSR: Interrupt source register.
2722 + * Write one to clear corresponding bit.
2723 + * TX_FIFO_STATUS: FIFO Statistics is full, sw should read 0x171c
2724 + */
2725 +#define INT_SOURCE_CSR                 0x0200
2726 +#define INT_SOURCE_CSR_RXDELAYINT      FIELD32(0x00000001)
2727 +#define INT_SOURCE_CSR_TXDELAYINT      FIELD32(0x00000002)
2728 +#define INT_SOURCE_CSR_RX_DONE         FIELD32(0x00000004)
2729 +#define INT_SOURCE_CSR_AC0_DMA_DONE    FIELD32(0x00000008)
2730 +#define INT_SOURCE_CSR_AC1_DMA_DONE    FIELD32(0x00000010)
2731 +#define INT_SOURCE_CSR_AC2_DMA_DONE    FIELD32(0x00000020)
2732 +#define INT_SOURCE_CSR_AC3_DMA_DONE    FIELD32(0x00000040)
2733 +#define INT_SOURCE_CSR_HCCA_DMA_DONE   FIELD32(0x00000080)
2734 +#define INT_SOURCE_CSR_MGMT_DMA_DONE   FIELD32(0x00000100)
2735 +#define INT_SOURCE_CSR_MCU_COMMAND     FIELD32(0x00000200)
2736 +#define INT_SOURCE_CSR_RXTX_COHERENT   FIELD32(0x00000400)
2737 +#define INT_SOURCE_CSR_TBTT            FIELD32(0x00000800)
2738 +#define INT_SOURCE_CSR_PRE_TBTT                FIELD32(0x00001000)
2739 +#define INT_SOURCE_CSR_TX_FIFO_STATUS  FIELD32(0x00002000)
2740 +#define INT_SOURCE_CSR_AUTO_WAKEUP     FIELD32(0x00004000)
2741 +#define INT_SOURCE_CSR_GPTIMER         FIELD32(0x00008000)
2742 +#define INT_SOURCE_CSR_RX_COHERENT     FIELD32(0x00010000)
2743 +#define INT_SOURCE_CSR_TX_COHERENT     FIELD32(0x00020000)
2744 +
2745 +/*
2746 + * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
2747 + */
2748 +#define INT_MASK_CSR                   0x0204
2749 +#define INT_MASK_CSR_RXDELAYINT                FIELD32(0x00000001)
2750 +#define INT_MASK_CSR_TXDELAYINT                FIELD32(0x00000002)
2751 +#define INT_MASK_CSR_RX_DONE           FIELD32(0x00000004)
2752 +#define INT_MASK_CSR_AC0_DMA_DONE      FIELD32(0x00000008)
2753 +#define INT_MASK_CSR_AC1_DMA_DONE      FIELD32(0x00000010)
2754 +#define INT_MASK_CSR_AC2_DMA_DONE      FIELD32(0x00000020)
2755 +#define INT_MASK_CSR_AC3_DMA_DONE      FIELD32(0x00000040)
2756 +#define INT_MASK_CSR_HCCA_DMA_DONE     FIELD32(0x00000080)
2757 +#define INT_MASK_CSR_MGMT_DMA_DONE     FIELD32(0x00000100)
2758 +#define INT_MASK_CSR_MCU_COMMAND       FIELD32(0x00000200)
2759 +#define INT_MASK_CSR_RX_COHERENT       FIELD32(0x40000000)
2760 +#define INT_MASK_CSR_TX_COHERENT       FIELD32(0x80000000)
2761 +
2762 +/*
2763 + * WPDMA_GLO_CFG
2764 + */
2765 +#define WPDMA_GLO_CFG                  0x0208
2766 +#define WPDMA_GLO_CFG_ENABLE_TX_DMA    FIELD32(0x00000001)
2767 +#define WPDMA_GLO_CFG_TX_DMA_BUSY      FIELD32(0x00000002)
2768 +#define WPDMA_GLO_CFG_ENABLE_RX_DMA    FIELD32(0x00000004)
2769 +#define WPDMA_GLO_CFG_RX_DMA_BUSY      FIELD32(0x00000008)
2770 +#define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE        FIELD32(0x00000030)
2771 +#define WPDMA_GLO_CFG_TX_WRITEBACK_DONE        FIELD32(0x00000040)
2772 +#define WPDMA_GLO_CFG_BIG_ENDIAN       FIELD32(0x00000080)
2773 +#define WPDMA_GLO_CFG_RX_HDR_SCATTER   FIELD32(0x0000ff00)
2774 +#define WPDMA_GLO_CFG_HDR_SEG_LEN      FIELD32(0xffff0000)
2775 +
2776 +/*
2777 + * WPDMA_RST_IDX
2778 + */
2779 +#define WPDMA_RST_IDX                  0x020c
2780 +#define WPDMA_RST_IDX_DTX_IDX0         FIELD32(0x00000001)
2781 +#define WPDMA_RST_IDX_DTX_IDX1         FIELD32(0x00000002)
2782 +#define WPDMA_RST_IDX_DTX_IDX2         FIELD32(0x00000004)
2783 +#define WPDMA_RST_IDX_DTX_IDX3         FIELD32(0x00000008)
2784 +#define WPDMA_RST_IDX_DTX_IDX4         FIELD32(0x00000010)
2785 +#define WPDMA_RST_IDX_DTX_IDX5         FIELD32(0x00000020)
2786 +#define WPDMA_RST_IDX_DRX_IDX0         FIELD32(0x00010000)
2787 +
2788 +/*
2789 + * DELAY_INT_CFG
2790 + */
2791 +#define DELAY_INT_CFG                  0x0210
2792 +#define DELAY_INT_CFG_RXMAX_PTIME      FIELD32(0x000000ff)
2793 +#define DELAY_INT_CFG_RXMAX_PINT       FIELD32(0x00007f00)
2794 +#define DELAY_INT_CFG_RXDLY_INT_EN     FIELD32(0x00008000)
2795 +#define DELAY_INT_CFG_TXMAX_PTIME      FIELD32(0x00ff0000)
2796 +#define DELAY_INT_CFG_TXMAX_PINT       FIELD32(0x7f000000)
2797 +#define DELAY_INT_CFG_TXDLY_INT_EN     FIELD32(0x80000000)
2798 +
2799 +/*
2800 + * WMM_AIFSN_CFG: Aifsn for each EDCA AC
2801 + * AIFSN0: AC_BE
2802 + * AIFSN1: AC_BK
2803 + * AIFSN1: AC_VI
2804 + * AIFSN1: AC_VO
2805 + */
2806 +#define WMM_AIFSN_CFG                  0x0214
2807 +#define WMM_AIFSN_CFG_AIFSN0           FIELD32(0x0000000f)
2808 +#define WMM_AIFSN_CFG_AIFSN1           FIELD32(0x000000f0)
2809 +#define WMM_AIFSN_CFG_AIFSN2           FIELD32(0x00000f00)
2810 +#define WMM_AIFSN_CFG_AIFSN3           FIELD32(0x0000f000)
2811 +
2812 +/*
2813 + * WMM_CWMIN_CSR: CWmin for each EDCA AC
2814 + * CWMIN0: AC_BE
2815 + * CWMIN1: AC_BK
2816 + * CWMIN1: AC_VI
2817 + * CWMIN1: AC_VO
2818 + */
2819 +#define WMM_CWMIN_CFG                  0x0218
2820 +#define WMM_CWMIN_CFG_CWMIN0           FIELD32(0x0000000f)
2821 +#define WMM_CWMIN_CFG_CWMIN1           FIELD32(0x000000f0)
2822 +#define WMM_CWMIN_CFG_CWMIN2           FIELD32(0x00000f00)
2823 +#define WMM_CWMIN_CFG_CWMIN3           FIELD32(0x0000f000)
2824 +
2825 +/*
2826 + * WMM_CWMAX_CSR: CWmax for each EDCA AC
2827 + * CWMAX0: AC_BE
2828 + * CWMAX1: AC_BK
2829 + * CWMAX1: AC_VI
2830 + * CWMAX1: AC_VO
2831 + */
2832 +#define WMM_CWMAX_CFG                  0x021c
2833 +#define WMM_CWMAX_CFG_CWMAX0           FIELD32(0x0000000f)
2834 +#define WMM_CWMAX_CFG_CWMAX1           FIELD32(0x000000f0)
2835 +#define WMM_CWMAX_CFG_CWMAX2           FIELD32(0x00000f00)
2836 +#define WMM_CWMAX_CFG_CWMAX3           FIELD32(0x0000f000)
2837 +
2838 +/*
2839 + * AC_TXOP0: AC_BK/AC_BE TXOP register
2840 + * AC0TXOP: AC_BK in unit of 32us
2841 + * AC1TXOP: AC_BE in unit of 32us
2842 + */
2843 +#define WMM_TXOP0_CFG                  0x0220
2844 +#define WMM_TXOP0_CFG_AC0TXOP          FIELD32(0x0000ffff)
2845 +#define WMM_TXOP0_CFG_AC1TXOP          FIELD32(0xffff0000)
2846 +
2847 +/*
2848 + * AC_TXOP1: AC_VO/AC_VI TXOP register
2849 + * AC2TXOP: AC_VI in unit of 32us
2850 + * AC3TXOP: AC_VO in unit of 32us
2851 + */
2852 +#define WMM_TXOP1_CFG                  0x0224
2853 +#define WMM_TXOP1_CFG_AC2TXOP          FIELD32(0x0000ffff)
2854 +#define WMM_TXOP1_CFG_AC3TXOP          FIELD32(0xffff0000)
2855 +
2856 +/*
2857 + * RINGREG_DIFF
2858 + */
2859 +#define RINGREG_DIFF                   0x0010
2860 +
2861 +/*
2862 + * GPIO_CTRL_CFG:
2863 + */
2864 +#define GPIO_CTRL_CFG                  0x0228
2865 +#define GPIO_CTRL_CFG_BIT0             FIELD32(0x00000001)
2866 +#define GPIO_CTRL_CFG_BIT1             FIELD32(0x00000002)
2867 +#define GPIO_CTRL_CFG_BIT2             FIELD32(0x00000004)
2868 +#define GPIO_CTRL_CFG_BIT3             FIELD32(0x00000008)
2869 +#define GPIO_CTRL_CFG_BIT4             FIELD32(0x00000010)
2870 +#define GPIO_CTRL_CFG_BIT5             FIELD32(0x00000020)
2871 +#define GPIO_CTRL_CFG_BIT6             FIELD32(0x00000040)
2872 +#define GPIO_CTRL_CFG_BIT7             FIELD32(0x00000080)
2873 +#define GPIO_CTRL_CFG_BIT8             FIELD32(0x00000100)
2874 +
2875 +/*
2876 + * MCU_CMD_CFG
2877 + */
2878 +#define MCU_CMD_CFG                    0x022c
2879 +
2880 +/*
2881 + * AC_BK register offsets
2882 + */
2883 +#define TX_BASE_PTR0                   0x0230
2884 +#define TX_MAX_CNT0                    0x0234
2885 +#define TX_CTX_IDX0                    0x0238
2886 +#define TX_DTX_IDX0                    0x023c
2887 +
2888 +/*
2889 + * AC_BE register offsets
2890 + */
2891 +#define TX_BASE_PTR1                   0x0240
2892 +#define TX_MAX_CNT1                    0x0244
2893 +#define TX_CTX_IDX1                    0x0248
2894 +#define TX_DTX_IDX1                    0x024c
2895 +
2896 +/*
2897 + * AC_VI register offsets
2898 + */
2899 +#define TX_BASE_PTR2                   0x0250
2900 +#define TX_MAX_CNT2                    0x0254
2901 +#define TX_CTX_IDX2                    0x0258
2902 +#define TX_DTX_IDX2                    0x025c
2903 +
2904 +/*
2905 + * AC_VO register offsets
2906 + */
2907 +#define TX_BASE_PTR3                   0x0260
2908 +#define TX_MAX_CNT3                    0x0264
2909 +#define TX_CTX_IDX3                    0x0268
2910 +#define TX_DTX_IDX3                    0x026c
2911 +
2912 +/*
2913 + * HCCA register offsets
2914 + */
2915 +#define TX_BASE_PTR4                   0x0270
2916 +#define TX_MAX_CNT4                    0x0274
2917 +#define TX_CTX_IDX4                    0x0278
2918 +#define TX_DTX_IDX4                    0x027c
2919 +
2920 +/*
2921 + * MGMT register offsets
2922 + */
2923 +#define TX_BASE_PTR5                   0x0280
2924 +#define TX_MAX_CNT5                    0x0284
2925 +#define TX_CTX_IDX5                    0x0288
2926 +#define TX_DTX_IDX5                    0x028c
2927 +
2928 +/*
2929 + * Queue register offset macros
2930 + */
2931 +#define TX_QUEUE_REG_OFFSET            0x10
2932 +#define TX_BASE_PTR(__x)               TX_BASE_PTR0 + ((__x) * TX_QUEUE_REG_OFFSET)
2933 +#define TX_MAX_CNT(__x)                        TX_MAX_CNT0 + ((__x) * TX_QUEUE_REG_OFFSET)
2934 +#define TX_CTX_IDX(__x)                        TX_CTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET)
2935 +#define TX_DTX_IDX(__x)                        TX_DTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET)
2936 +
2937 +/*
2938 + * RX register offsets
2939 + */
2940 +#define RX_BASE_PTR                    0x0290
2941 +#define RX_MAX_CNT                     0x0294
2942 +#define RX_CRX_IDX                     0x0298
2943 +#define RX_DRX_IDX                     0x029c
2944 +
2945 +/*
2946 + * PBF_SYS_CTRL
2947 + * HOST_RAM_WRITE: enable Host program ram write selection
2948 + */
2949 +#define PBF_SYS_CTRL                   0x0400
2950 +#define PBF_SYS_CTRL_READY             FIELD32(0x00000080)
2951 +#define PBF_SYS_CTRL_HOST_RAM_WRITE    FIELD32(0x00010000)
2952 +
2953 +/*
2954 + * PBF  registers
2955 + * Most are for debug. Driver doesn't touch PBF register.
2956 + */
2957 +#define PBF_CFG                                0x0408
2958 +#define PBF_MAX_PCNT                   0x040c
2959 +#define PBF_CTRL                       0x0410
2960 +#define PBF_INT_STA                    0x0414
2961 +#define PBF_INT_ENA                    0x0418
2962 +
2963 +/*
2964 + * BCN_OFFSET0:
2965 + */
2966 +#define BCN_OFFSET0                    0x042c
2967 +#define BCN_OFFSET0_BCN0               FIELD32(0x000000ff)
2968 +#define BCN_OFFSET0_BCN1               FIELD32(0x0000ff00)
2969 +#define BCN_OFFSET0_BCN2               FIELD32(0x00ff0000)
2970 +#define BCN_OFFSET0_BCN3               FIELD32(0xff000000)
2971 +
2972 +/*
2973 + * BCN_OFFSET1:
2974 + */
2975 +#define BCN_OFFSET1                    0x0430
2976 +#define BCN_OFFSET1_BCN4               FIELD32(0x000000ff)
2977 +#define BCN_OFFSET1_BCN5               FIELD32(0x0000ff00)
2978 +#define BCN_OFFSET1_BCN6               FIELD32(0x00ff0000)
2979 +#define BCN_OFFSET1_BCN7               FIELD32(0xff000000)
2980 +
2981 +/*
2982 + * PBF  registers
2983 + * Most are for debug. Driver doesn't touch PBF register.
2984 + */
2985 +#define TXRXQ_PCNT                     0x0438
2986 +#define PBF_DBG                                0x043c
2987 +
2988 +/*
2989 + * MAC Control/Status Registers(CSR).
2990 + * Some values are set in TU, whereas 1 TU == 1024 us.
2991 + */
2992 +
2993 +/*
2994 + * MAC_CSR0: ASIC revision number.
2995 + * ASIC_REV: 0
2996 + * ASIC_VER: 2860
2997 + */
2998 +#define MAC_CSR0                       0x1000
2999 +#define MAC_CSR0_ASIC_REV              FIELD32(0x0000ffff)
3000 +#define MAC_CSR0_ASIC_VER              FIELD32(0xffff0000)
3001 +
3002 +/*
3003 + * MAC_SYS_CTRL:
3004 + */
3005 +#define MAC_SYS_CTRL                   0x1004
3006 +#define MAC_SYS_CTRL_RESET_CSR         FIELD32(0x00000001)
3007 +#define MAC_SYS_CTRL_RESET_BBP         FIELD32(0x00000002)
3008 +#define MAC_SYS_CTRL_ENABLE_TX         FIELD32(0x00000004)
3009 +#define MAC_SYS_CTRL_ENABLE_RX         FIELD32(0x00000008)
3010 +#define MAC_SYS_CTRL_CONTINUOUS_TX     FIELD32(0x00000010)
3011 +#define MAC_SYS_CTRL_LOOPBACK          FIELD32(0x00000020)
3012 +#define MAC_SYS_CTRL_WLAN_HALT         FIELD32(0x00000040)
3013 +#define MAC_SYS_CTRL_RX_TIMESTAMP      FIELD32(0x00000080)
3014 +
3015 +/*
3016 + * MAC_ADDR_DW0: STA MAC register 0
3017 + */
3018 +#define MAC_ADDR_DW0                   0x1008
3019 +#define MAC_ADDR_DW0_BYTE0             FIELD32(0x000000ff)
3020 +#define MAC_ADDR_DW0_BYTE1             FIELD32(0x0000ff00)
3021 +#define MAC_ADDR_DW0_BYTE2             FIELD32(0x00ff0000)
3022 +#define MAC_ADDR_DW0_BYTE3             FIELD32(0xff000000)
3023 +
3024 +/*
3025 + * MAC_ADDR_DW1: STA MAC register 1
3026 + * UNICAST_TO_ME_MASK:
3027 + * Used to mask off bits from byte 5 of the MAC address
3028 + * to determine the UNICAST_TO_ME bit for RX frames.
3029 + * The full mask is complemented by BSS_ID_MASK:
3030 + *    MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
3031 + */
3032 +#define MAC_ADDR_DW1                   0x100c
3033 +#define MAC_ADDR_DW1_BYTE4             FIELD32(0x000000ff)
3034 +#define MAC_ADDR_DW1_BYTE5             FIELD32(0x0000ff00)
3035 +#define MAC_ADDR_DW1_UNICAST_TO_ME_MASK        FIELD32(0x00ff0000)
3036 +
3037 +/*
3038 + * MAC_BSSID_DW0: BSSID register 0
3039 + */
3040 +#define MAC_BSSID_DW0                  0x1010
3041 +#define MAC_BSSID_DW0_BYTE0            FIELD32(0x000000ff)
3042 +#define MAC_BSSID_DW0_BYTE1            FIELD32(0x0000ff00)
3043 +#define MAC_BSSID_DW0_BYTE2            FIELD32(0x00ff0000)
3044 +#define MAC_BSSID_DW0_BYTE3            FIELD32(0xff000000)
3045 +
3046 +/*
3047 + * MAC_BSSID_DW1: BSSID register 1
3048 + * BSS_ID_MASK:
3049 + *     0: 1-BSSID mode (BSS index = 0)
3050 + *     1: 2-BSSID mode (BSS index: Byte5, bit 0)
3051 + *     2: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
3052 + *     3: 8-BSSID mode (BSS index: byte5, bit 0 - 2)
3053 + * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the
3054 + * BSSID. This will make sure that those bits will be ignored
3055 + * when determining the MY_BSS of RX frames.
3056 + */
3057 +#define MAC_BSSID_DW1                  0x1014
3058 +#define MAC_BSSID_DW1_BYTE4            FIELD32(0x000000ff)
3059 +#define MAC_BSSID_DW1_BYTE5            FIELD32(0x0000ff00)
3060 +#define MAC_BSSID_DW1_BSS_ID_MASK      FIELD32(0x00030000)
3061 +#define MAC_BSSID_DW1_BSS_BCN_NUM      FIELD32(0x001c0000)
3062 +
3063 +/*
3064 + * MAX_LEN_CFG: Maximum frame length register.
3065 + * MAX_MPDU: rt2860b max 16k bytes
3066 + * MAX_PSDU: Maximum PSDU length
3067 + *     (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
3068 + */
3069 +#define MAX_LEN_CFG                    0x1018
3070 +#define MAX_LEN_CFG_MAX_MPDU           FIELD32(0x00000fff)
3071 +#define MAX_LEN_CFG_MAX_PSDU           FIELD32(0x00003000)
3072 +#define MAX_LEN_CFG_MIN_PSDU           FIELD32(0x0000c000)
3073 +#define MAX_LEN_CFG_MIN_MPDU           FIELD32(0x000f0000)
3074 +
3075 +/*
3076 + * BBP_CSR_CFG: BBP serial control register
3077 + * VALUE: Register value to program into BBP
3078 + * REG_NUM: Selected BBP register
3079 + * READ_CONTROL: 0 write BBP, 1 read BBP
3080 + * BUSY: ASIC is busy executing BBP commands
3081 + * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks
3082 + * BBP_RW_MODE: 0 serial, 1 paralell
3083 + */
3084 +#define BBP_CSR_CFG                    0x101c
3085 +#define BBP_CSR_CFG_VALUE              FIELD32(0x000000ff)
3086 +#define BBP_CSR_CFG_REGNUM             FIELD32(0x0000ff00)
3087 +#define BBP_CSR_CFG_READ_CONTROL       FIELD32(0x00010000)
3088 +#define BBP_CSR_CFG_BUSY               FIELD32(0x00020000)
3089 +#define BBP_CSR_CFG_BBP_PAR_DUR                FIELD32(0x00040000)
3090 +#define BBP_CSR_CFG_BBP_RW_MODE                FIELD32(0x00080000)
3091 +
3092 +/*
3093 + * RF_CSR_CFG0: RF control register
3094 + * REGID_AND_VALUE: Register value to program into RF
3095 + * BITWIDTH: Selected RF register
3096 + * STANDBYMODE: 0 high when standby, 1 low when standby
3097 + * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate
3098 + * BUSY: ASIC is busy executing RF commands
3099 + */
3100 +#define RF_CSR_CFG0                    0x1020
3101 +#define RF_CSR_CFG0_REGID_AND_VALUE    FIELD32(0x00ffffff)
3102 +#define RF_CSR_CFG0_BITWIDTH           FIELD32(0x1f000000)
3103 +#define RF_CSR_CFG0_REG_VALUE_BW       FIELD32(0x1fffffff)
3104 +#define RF_CSR_CFG0_STANDBYMODE                FIELD32(0x20000000)
3105 +#define RF_CSR_CFG0_SEL                        FIELD32(0x40000000)
3106 +#define RF_CSR_CFG0_BUSY               FIELD32(0x80000000)
3107 +
3108 +/*
3109 + * RF_CSR_CFG1: RF control register
3110 + * REGID_AND_VALUE: Register value to program into RF
3111 + * RFGAP: Gap between BB_CONTROL_RF and RF_LE
3112 + *        0: 3 system clock cycle (37.5usec)
3113 + *        1: 5 system clock cycle (62.5usec)
3114 + */
3115 +#define RF_CSR_CFG1                    0x1024
3116 +#define RF_CSR_CFG1_REGID_AND_VALUE    FIELD32(0x00ffffff)
3117 +#define RF_CSR_CFG1_RFGAP              FIELD32(0x1f000000)
3118 +
3119 +/*
3120 + * RF_CSR_CFG2: RF control register
3121 + * VALUE: Register value to program into RF
3122 + * RFGAP: Gap between BB_CONTROL_RF and RF_LE
3123 + *        0: 3 system clock cycle (37.5usec)
3124 + *        1: 5 system clock cycle (62.5usec)
3125 + */
3126 +#define RF_CSR_CFG2                    0x1028
3127 +#define RF_CSR_CFG2_VALUE              FIELD32(0x00ffffff)
3128 +
3129 +/*
3130 + * LED_CFG: LED control
3131 + * color LED's:
3132 + *   0: off
3133 + *   1: blinking upon TX2
3134 + *   2: periodic slow blinking
3135 + *   3: always on
3136 + * LED polarity:
3137 + *   0: active low
3138 + *   1: active high
3139 + */
3140 +#define LED_CFG                                0x102c
3141 +#define LED_CFG_ON_PERIOD              FIELD32(0x000000ff)
3142 +#define LED_CFG_OFF_PERIOD             FIELD32(0x0000ff00)
3143 +#define LED_CFG_SLOW_BLINK_PERIOD      FIELD32(0x003f0000)
3144 +#define LED_CFG_R_LED_MODE             FIELD32(0x03000000)
3145 +#define LED_CFG_G_LED_MODE             FIELD32(0x0c000000)
3146 +#define LED_CFG_Y_LED_MODE             FIELD32(0x30000000)
3147 +#define LED_CFG_LED_POLAR              FIELD32(0x40000000)
3148 +
3149 +/*
3150 + * XIFS_TIME_CFG: MAC timing
3151 + * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX
3152 + * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX
3153 + * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX
3154 + *     when MAC doesn't reference BBP signal BBRXEND
3155 + * EIFS: unit 1us
3156 + * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer
3157 + *
3158 + */
3159 +#define XIFS_TIME_CFG                  0x1100
3160 +#define XIFS_TIME_CFG_CCKM_SIFS_TIME   FIELD32(0x000000ff)
3161 +#define XIFS_TIME_CFG_OFDM_SIFS_TIME   FIELD32(0x0000ff00)
3162 +#define XIFS_TIME_CFG_OFDM_XIFS_TIME   FIELD32(0x000f0000)
3163 +#define XIFS_TIME_CFG_EIFS             FIELD32(0x1ff00000)
3164 +#define XIFS_TIME_CFG_BB_RXEND_ENABLE  FIELD32(0x20000000)
3165 +
3166 +/*
3167 + * BKOFF_SLOT_CFG:
3168 + */
3169 +#define BKOFF_SLOT_CFG                 0x1104
3170 +#define BKOFF_SLOT_CFG_SLOT_TIME       FIELD32(0x000000ff)
3171 +#define BKOFF_SLOT_CFG_CC_DELAY_TIME   FIELD32(0x0000ff00)
3172 +
3173 +/*
3174 + * NAV_TIME_CFG:
3175 + */
3176 +#define NAV_TIME_CFG                   0x1108
3177 +#define NAV_TIME_CFG_SIFS              FIELD32(0x000000ff)
3178 +#define NAV_TIME_CFG_SLOT_TIME         FIELD32(0x0000ff00)
3179 +#define NAV_TIME_CFG_EIFS              FIELD32(0x01ff0000)
3180 +#define NAV_TIME_ZERO_SIFS             FIELD32(0x02000000)
3181 +
3182 +/*
3183 + * CH_TIME_CFG: count as channel busy
3184 + */
3185 +#define CH_TIME_CFG                    0x110c
3186 +
3187 +/*
3188 + * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us
3189 + */
3190 +#define PBF_LIFE_TIMER                 0x1110
3191 +
3192 +/*
3193 + * BCN_TIME_CFG:
3194 + * BEACON_INTERVAL: in unit of 1/16 TU
3195 + * TSF_TICKING: Enable TSF auto counting
3196 + * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
3197 + * BEACON_GEN: Enable beacon generator
3198 + */
3199 +#define BCN_TIME_CFG                   0x1114
3200 +#define BCN_TIME_CFG_BEACON_INTERVAL   FIELD32(0x0000ffff)
3201 +#define BCN_TIME_CFG_TSF_TICKING       FIELD32(0x00010000)
3202 +#define BCN_TIME_CFG_TSF_SYNC          FIELD32(0x00060000)
3203 +#define BCN_TIME_CFG_TBTT_ENABLE       FIELD32(0x00080000)
3204 +#define BCN_TIME_CFG_BEACON_GEN                FIELD32(0x00100000)
3205 +#define BCN_TIME_CFG_TX_TIME_COMPENSATE        FIELD32(0xf0000000)
3206 +
3207 +/*
3208 + * TBTT_SYNC_CFG:
3209 + */
3210 +#define TBTT_SYNC_CFG                  0x1118
3211 +
3212 +/*
3213 + * TSF_TIMER_DW0: Local lsb TSF timer, read-only
3214 + */
3215 +#define TSF_TIMER_DW0                  0x111c
3216 +#define TSF_TIMER_DW0_LOW_WORD         FIELD32(0xffffffff)
3217 +
3218 +/*
3219 + * TSF_TIMER_DW1: Local msb TSF timer, read-only
3220 + */
3221 +#define TSF_TIMER_DW1                  0x1120
3222 +#define TSF_TIMER_DW1_HIGH_WORD                FIELD32(0xffffffff)
3223 +
3224 +/*
3225 + * TBTT_TIMER: TImer remains till next TBTT, read-only
3226 + */
3227 +#define TBTT_TIMER                     0x1124
3228 +
3229 +/*
3230 + * INT_TIMER_CFG:
3231 + */
3232 +#define INT_TIMER_CFG                  0x1128
3233 +
3234 +/*
3235 + * INT_TIMER_EN: GP-timer and pre-tbtt Int enable
3236 + */
3237 +#define INT_TIMER_EN                   0x112c
3238 +
3239 +/*
3240 + * CH_IDLE_STA: channel idle time
3241 + */
3242 +#define CH_IDLE_STA                    0x1130
3243 +
3244 +/*
3245 + * CH_BUSY_STA: channel busy time
3246 + */
3247 +#define CH_BUSY_STA                    0x1134
3248 +
3249 +/*
3250 + * MAC_STATUS_CFG:
3251 + * BBP_RF_BUSY: When set to 0, BBP and RF are stable.
3252 + *     if 1 or higher one of the 2 registers is busy.
3253 + */
3254 +#define MAC_STATUS_CFG                 0x1200
3255 +#define MAC_STATUS_CFG_BBP_RF_BUSY     FIELD32(0x00000003)
3256 +
3257 +/*
3258 + * PWR_PIN_CFG:
3259 + */
3260 +#define PWR_PIN_CFG                    0x1204
3261 +
3262 +/*
3263 + * AUTOWAKEUP_CFG: Manual power control / status register
3264 + * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set
3265 + * AUTOWAKE: 0:sleep, 1:awake
3266 + */
3267 +#define AUTOWAKEUP_CFG                 0x1208
3268 +#define AUTOWAKEUP_CFG_AUTO_LEAD_TIME  FIELD32(0x000000ff)
3269 +#define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE        FIELD32(0x00007f00)
3270 +#define AUTOWAKEUP_CFG_AUTOWAKE                FIELD32(0x00008000)
3271 +
3272 +/*
3273 + * EDCA_AC0_CFG:
3274 + */
3275 +#define EDCA_AC0_CFG                   0x1300
3276 +#define EDCA_AC0_CFG_AC_TX_OP          FIELD32(0x000000ff)
3277 +#define EDCA_AC0_CFG_AIFSN             FIELD32(0x00000f00)
3278 +#define EDCA_AC0_CFG_CWMIN             FIELD32(0x0000f000)
3279 +#define EDCA_AC0_CFG_CWMAX             FIELD32(0x000f0000)
3280 +
3281 +/*
3282 + * EDCA_AC1_CFG:
3283 + */
3284 +#define EDCA_AC1_CFG                   0x1304
3285 +#define EDCA_AC1_CFG_AC_TX_OP          FIELD32(0x000000ff)
3286 +#define EDCA_AC1_CFG_AIFSN             FIELD32(0x00000f00)
3287 +#define EDCA_AC1_CFG_CWMIN             FIELD32(0x0000f000)
3288 +#define EDCA_AC1_CFG_CWMAX             FIELD32(0x000f0000)
3289 +
3290 +/*
3291 + * EDCA_AC2_CFG:
3292 + */
3293 +#define EDCA_AC2_CFG                   0x1308
3294 +#define EDCA_AC2_CFG_AC_TX_OP          FIELD32(0x000000ff)
3295 +#define EDCA_AC2_CFG_AIFSN             FIELD32(0x00000f00)
3296 +#define EDCA_AC2_CFG_CWMIN             FIELD32(0x0000f000)
3297 +#define EDCA_AC2_CFG_CWMAX             FIELD32(0x000f0000)
3298 +
3299 +/*
3300 + * EDCA_AC3_CFG:
3301 + */
3302 +#define EDCA_AC3_CFG                   0x130c
3303 +#define EDCA_AC3_CFG_AC_TX_OP          FIELD32(0x000000ff)
3304 +#define EDCA_AC3_CFG_AIFSN             FIELD32(0x00000f00)
3305 +#define EDCA_AC3_CFG_CWMIN             FIELD32(0x0000f000)
3306 +#define EDCA_AC3_CFG_CWMAX             FIELD32(0x000f0000)
3307 +
3308 +/*
3309 + * EDCA_TID_AC_MAP:
3310 + */
3311 +#define EDCA_TID_AC_MAP                        0x1310
3312 +
3313 +/*
3314 + * TX_PWR_CFG_0:
3315 + */
3316 +#define TX_PWR_CFG_0                   0x1314
3317 +#define TX_PWR_CFG_0_1MBS              FIELD32(0x0000000f)
3318 +#define TX_PWR_CFG_0_2MBS              FIELD32(0x000000f0)
3319 +#define TX_PWR_CFG_0_55MBS             FIELD32(0x00000f00)
3320 +#define TX_PWR_CFG_0_11MBS             FIELD32(0x0000f000)
3321 +#define TX_PWR_CFG_0_6MBS              FIELD32(0x000f0000)
3322 +#define TX_PWR_CFG_0_9MBS              FIELD32(0x00f00000)
3323 +#define TX_PWR_CFG_0_12MBS             FIELD32(0x0f000000)
3324 +#define TX_PWR_CFG_0_18MBS             FIELD32(0xf0000000)
3325 +
3326 +/*
3327 + * TX_PWR_CFG_1:
3328 + */
3329 +#define TX_PWR_CFG_1                   0x1318
3330 +#define TX_PWR_CFG_1_24MBS             FIELD32(0x0000000f)
3331 +#define TX_PWR_CFG_1_36MBS             FIELD32(0x000000f0)
3332 +#define TX_PWR_CFG_1_48MBS             FIELD32(0x00000f00)
3333 +#define TX_PWR_CFG_1_54MBS             FIELD32(0x0000f000)
3334 +#define TX_PWR_CFG_1_MCS0              FIELD32(0x000f0000)
3335 +#define TX_PWR_CFG_1_MCS1              FIELD32(0x00f00000)
3336 +#define TX_PWR_CFG_1_MCS2              FIELD32(0x0f000000)
3337 +#define TX_PWR_CFG_1_MCS3              FIELD32(0xf0000000)
3338 +
3339 +/*
3340 + * TX_PWR_CFG_2:
3341 + */
3342 +#define TX_PWR_CFG_2                   0x131c
3343 +#define TX_PWR_CFG_2_MCS4              FIELD32(0x0000000f)
3344 +#define TX_PWR_CFG_2_MCS5              FIELD32(0x000000f0)
3345 +#define TX_PWR_CFG_2_MCS6              FIELD32(0x00000f00)
3346 +#define TX_PWR_CFG_2_MCS7              FIELD32(0x0000f000)
3347 +#define TX_PWR_CFG_2_MCS8              FIELD32(0x000f0000)
3348 +#define TX_PWR_CFG_2_MCS9              FIELD32(0x00f00000)
3349 +#define TX_PWR_CFG_2_MCS10             FIELD32(0x0f000000)
3350 +#define TX_PWR_CFG_2_MCS11             FIELD32(0xf0000000)
3351 +
3352 +/*
3353 + * TX_PWR_CFG_3:
3354 + */
3355 +#define TX_PWR_CFG_3                   0x1320
3356 +#define TX_PWR_CFG_3_MCS12             FIELD32(0x0000000f)
3357 +#define TX_PWR_CFG_3_MCS13             FIELD32(0x000000f0)
3358 +#define TX_PWR_CFG_3_MCS14             FIELD32(0x00000f00)
3359 +#define TX_PWR_CFG_3_MCS15             FIELD32(0x0000f000)
3360 +#define TX_PWR_CFG_3_UKNOWN1           FIELD32(0x000f0000)
3361 +#define TX_PWR_CFG_3_UKNOWN2           FIELD32(0x00f00000)
3362 +#define TX_PWR_CFG_3_UKNOWN3           FIELD32(0x0f000000)
3363 +#define TX_PWR_CFG_3_UKNOWN4           FIELD32(0xf0000000)
3364 +
3365 +/*
3366 + * TX_PWR_CFG_4:
3367 + */
3368 +#define TX_PWR_CFG_4                   0x1324
3369 +#define TX_PWR_CFG_4_UKNOWN5           FIELD32(0x0000000f)
3370 +#define TX_PWR_CFG_4_UKNOWN6           FIELD32(0x000000f0)
3371 +#define TX_PWR_CFG_4_UKNOWN7           FIELD32(0x00000f00)
3372 +#define TX_PWR_CFG_4_UKNOWN8           FIELD32(0x0000f000)
3373 +
3374 +/*
3375 + * TX_PIN_CFG:
3376 + */
3377 +#define TX_PIN_CFG                     0x1328
3378 +#define TX_PIN_CFG_PA_PE_A0_EN         FIELD32(0x00000001)
3379 +#define TX_PIN_CFG_PA_PE_G0_EN         FIELD32(0x00000002)
3380 +#define TX_PIN_CFG_PA_PE_A1_EN         FIELD32(0x00000004)
3381 +#define TX_PIN_CFG_PA_PE_G1_EN         FIELD32(0x00000008)
3382 +#define TX_PIN_CFG_PA_PE_A0_POL                FIELD32(0x00000010)
3383 +#define TX_PIN_CFG_PA_PE_G0_POL                FIELD32(0x00000020)
3384 +#define TX_PIN_CFG_PA_PE_A1_POL                FIELD32(0x00000040)
3385 +#define TX_PIN_CFG_PA_PE_G1_POL                FIELD32(0x00000080)
3386 +#define TX_PIN_CFG_LNA_PE_A0_EN                FIELD32(0x00000100)
3387 +#define TX_PIN_CFG_LNA_PE_G0_EN                FIELD32(0x00000200)
3388 +#define TX_PIN_CFG_LNA_PE_A1_EN                FIELD32(0x00000400)
3389 +#define TX_PIN_CFG_LNA_PE_G1_EN                FIELD32(0x00000800)
3390 +#define TX_PIN_CFG_LNA_PE_A0_POL       FIELD32(0x00001000)
3391 +#define TX_PIN_CFG_LNA_PE_G0_POL       FIELD32(0x00002000)
3392 +#define TX_PIN_CFG_LNA_PE_A1_POL       FIELD32(0x00004000)
3393 +#define TX_PIN_CFG_LNA_PE_G1_POL       FIELD32(0x00008000)
3394 +#define TX_PIN_CFG_RFTR_EN             FIELD32(0x00010000)
3395 +#define TX_PIN_CFG_RFTR_POL            FIELD32(0x00020000)
3396 +#define TX_PIN_CFG_TRSW_EN             FIELD32(0x00040000)
3397 +#define TX_PIN_CFG_TRSW_POL            FIELD32(0x00080000)
3398 +
3399 +/*
3400 + * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz
3401 + */
3402 +#define TX_BAND_CFG                    0x132c
3403 +#define TX_BAND_CFG_A                  FIELD32(0x00000002)
3404 +#define TX_BAND_CFG_BG                 FIELD32(0x00000004)
3405 +
3406 +/*
3407 + * TX_SW_CFG0:
3408 + */
3409 +#define TX_SW_CFG0                     0x1330
3410 +
3411 +/*
3412 + * TX_SW_CFG1:
3413 + */
3414 +#define TX_SW_CFG1                     0x1334
3415 +
3416 +/*
3417 + * TX_SW_CFG2:
3418 + */
3419 +#define TX_SW_CFG2                     0x1338
3420 +
3421 +/*
3422 + * TXOP_THRES_CFG:
3423 + */
3424 +#define TXOP_THRES_CFG                 0x133c
3425 +
3426 +/*
3427 + * TXOP_CTRL_CFG:
3428 + */
3429 +#define TXOP_CTRL_CFG                  0x1340
3430 +
3431 +/*
3432 + * TX_RTS_CFG:
3433 + * RTS_THRES: unit:byte
3434 + * RTS_FBK_EN: enable rts rate fallback
3435 + */
3436 +#define TX_RTS_CFG                     0x1344
3437 +#define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT        FIELD32(0x000000ff)
3438 +#define TX_RTS_CFG_RTS_THRES           FIELD32(0x00ffff00)
3439 +#define TX_RTS_CFG_RTS_FBK_EN          FIELD32(0x01000000)
3440 +
3441 +/*
3442 + * TX_TIMEOUT_CFG:
3443 + * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us
3444 + * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure
3445 + * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation.
3446 + *                it is recommended that:
3447 + *                (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
3448 + */
3449 +#define TX_TIMEOUT_CFG                 0x1348
3450 +#define TX_TIMEOUT_CFG_MPDU_LIFETIME   FIELD32(0x000000f0)
3451 +#define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT  FIELD32(0x0000ff00)
3452 +#define TX_TIMEOUT_CFG_TX_OP_TIMEOUT   FIELD32(0x00ff0000)
3453 +
3454 +/*
3455 + * TX_RTY_CFG:
3456 + * SHORT_RTY_LIMIT: short retry limit
3457 + * LONG_RTY_LIMIT: long retry limit
3458 + * LONG_RTY_THRE: Long retry threshoold
3459 + * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode
3460 + *                   0:expired by retry limit, 1: expired by mpdu life timer
3461 + * AGG_RTY_MODE: Aggregate MPDU retry mode
3462 + *               0:expired by retry limit, 1: expired by mpdu life timer
3463 + * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable
3464 + */
3465 +#define TX_RTY_CFG                     0x134c
3466 +#define TX_RTY_CFG_SHORT_RTY_LIMIT     FIELD32(0x000000ff)
3467 +#define TX_RTY_CFG_LONG_RTY_LIMIT      FIELD32(0x0000ff00)
3468 +#define TX_RTY_CFG_LONG_RTY_THRE       FIELD32(0x0fff0000)
3469 +#define TX_RTY_CFG_NON_AGG_RTY_MODE    FIELD32(0x10000000)
3470 +#define TX_RTY_CFG_AGG_RTY_MODE                FIELD32(0x20000000)
3471 +#define TX_RTY_CFG_TX_AUTO_FB_ENABLE   FIELD32(0x40000000)
3472 +
3473 +/*
3474 + * TX_LINK_CFG:
3475 + * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us
3476 + * MFB_ENABLE: TX apply remote MFB 1:enable
3477 + * REMOTE_UMFS_ENABLE: remote unsolicit  MFB enable
3478 + *                     0: not apply remote remote unsolicit (MFS=7)
3479 + * TX_MRQ_EN: MCS request TX enable
3480 + * TX_RDG_EN: RDG TX enable
3481 + * TX_CF_ACK_EN: Piggyback CF-ACK enable
3482 + * REMOTE_MFB: remote MCS feedback
3483 + * REMOTE_MFS: remote MCS feedback sequence number
3484 + */
3485 +#define TX_LINK_CFG                    0x1350
3486 +#define TX_LINK_CFG_REMOTE_MFB_LIFETIME        FIELD32(0x000000ff)
3487 +#define TX_LINK_CFG_MFB_ENABLE         FIELD32(0x00000100)
3488 +#define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200)
3489 +#define TX_LINK_CFG_TX_MRQ_EN          FIELD32(0x00000400)
3490 +#define TX_LINK_CFG_TX_RDG_EN          FIELD32(0x00000800)
3491 +#define TX_LINK_CFG_TX_CF_ACK_EN       FIELD32(0x00001000)
3492 +#define TX_LINK_CFG_REMOTE_MFB         FIELD32(0x00ff0000)
3493 +#define TX_LINK_CFG_REMOTE_MFS         FIELD32(0xff000000)
3494 +
3495 +/*
3496 + * HT_FBK_CFG0:
3497 + */
3498 +#define HT_FBK_CFG0                    0x1354
3499 +#define HT_FBK_CFG0_HTMCS0FBK          FIELD32(0x0000000f)
3500 +#define HT_FBK_CFG0_HTMCS1FBK          FIELD32(0x000000f0)
3501 +#define HT_FBK_CFG0_HTMCS2FBK          FIELD32(0x00000f00)
3502 +#define HT_FBK_CFG0_HTMCS3FBK          FIELD32(0x0000f000)
3503 +#define HT_FBK_CFG0_HTMCS4FBK          FIELD32(0x000f0000)
3504 +#define HT_FBK_CFG0_HTMCS5FBK          FIELD32(0x00f00000)
3505 +#define HT_FBK_CFG0_HTMCS6FBK          FIELD32(0x0f000000)
3506 +#define HT_FBK_CFG0_HTMCS7FBK          FIELD32(0xf0000000)
3507 +
3508 +/*
3509 + * HT_FBK_CFG1:
3510 + */
3511 +#define HT_FBK_CFG1                    0x1358
3512 +#define HT_FBK_CFG1_HTMCS8FBK          FIELD32(0x0000000f)
3513 +#define HT_FBK_CFG1_HTMCS9FBK          FIELD32(0x000000f0)
3514 +#define HT_FBK_CFG1_HTMCS10FBK         FIELD32(0x00000f00)
3515 +#define HT_FBK_CFG1_HTMCS11FBK         FIELD32(0x0000f000)
3516 +#define HT_FBK_CFG1_HTMCS12FBK         FIELD32(0x000f0000)
3517 +#define HT_FBK_CFG1_HTMCS13FBK         FIELD32(0x00f00000)
3518 +#define HT_FBK_CFG1_HTMCS14FBK         FIELD32(0x0f000000)
3519 +#define HT_FBK_CFG1_HTMCS15FBK         FIELD32(0xf0000000)
3520 +
3521 +/*
3522 + * LG_FBK_CFG0:
3523 + */
3524 +#define LG_FBK_CFG0                    0x135c
3525 +#define LG_FBK_CFG0_OFDMMCS0FBK                FIELD32(0x0000000f)
3526 +#define LG_FBK_CFG0_OFDMMCS1FBK                FIELD32(0x000000f0)
3527 +#define LG_FBK_CFG0_OFDMMCS2FBK                FIELD32(0x00000f00)
3528 +#define LG_FBK_CFG0_OFDMMCS3FBK                FIELD32(0x0000f000)
3529 +#define LG_FBK_CFG0_OFDMMCS4FBK                FIELD32(0x000f0000)
3530 +#define LG_FBK_CFG0_OFDMMCS5FBK                FIELD32(0x00f00000)
3531 +#define LG_FBK_CFG0_OFDMMCS6FBK                FIELD32(0x0f000000)
3532 +#define LG_FBK_CFG0_OFDMMCS7FBK                FIELD32(0xf0000000)
3533 +
3534 +/*
3535 + * LG_FBK_CFG1:
3536 + */
3537 +#define LG_FBK_CFG1                    0x1360
3538 +#define LG_FBK_CFG0_CCKMCS0FBK         FIELD32(0x0000000f)
3539 +#define LG_FBK_CFG0_CCKMCS1FBK         FIELD32(0x000000f0)
3540 +#define LG_FBK_CFG0_CCKMCS2FBK         FIELD32(0x00000f00)
3541 +#define LG_FBK_CFG0_CCKMCS3FBK         FIELD32(0x0000f000)
3542 +
3543 +/*
3544 + * CCK_PROT_CFG: CCK Protection
3545 + * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd)
3546 + * PROTECT_CTRL: Protection control frame type for CCK TX
3547 + *               0:none, 1:RTS/CTS, 2:CTS-to-self
3548 + * PROTECT_NAV: TXOP protection type for CCK TX
3549 + *              0:none, 1:ShortNAVprotect, 2:LongNAVProtect
3550 + * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow
3551 + * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow
3552 + * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow
3553 + * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow
3554 + * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow
3555 + * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow
3556 + * RTS_TH_EN: RTS threshold enable on CCK TX
3557 + */
3558 +#define CCK_PROT_CFG                   0x1364
3559 +#define CCK_PROT_CFG_PROTECT_RATE      FIELD32(0x0000ffff)
3560 +#define CCK_PROT_CFG_PROTECT_CTRL      FIELD32(0x00030000)
3561 +#define CCK_PROT_CFG_PROTECT_NAV       FIELD32(0x000c0000)
3562 +#define CCK_PROT_CFG_TX_OP_ALLOW_CCK   FIELD32(0x00100000)
3563 +#define CCK_PROT_CFG_TX_OP_ALLOW_OFDM  FIELD32(0x00200000)
3564 +#define CCK_PROT_CFG_TX_OP_ALLOW_MM20  FIELD32(0x00400000)
3565 +#define CCK_PROT_CFG_TX_OP_ALLOW_MM40  FIELD32(0x00800000)
3566 +#define CCK_PROT_CFG_TX_OP_ALLOW_GF20  FIELD32(0x01000000)
3567 +#define CCK_PROT_CFG_TX_OP_ALLOW_GF40  FIELD32(0x02000000)
3568 +#define CCK_PROT_CFG_RTS_TH_EN         FIELD32(0x04000000)
3569 +
3570 +/*
3571 + * OFDM_PROT_CFG: OFDM Protection
3572 + */
3573 +#define OFDM_PROT_CFG                  0x1368
3574 +#define OFDM_PROT_CFG_PROTECT_RATE     FIELD32(0x0000ffff)
3575 +#define OFDM_PROT_CFG_PROTECT_CTRL     FIELD32(0x00030000)
3576 +#define OFDM_PROT_CFG_PROTECT_NAV      FIELD32(0x000c0000)
3577 +#define OFDM_PROT_CFG_TX_OP_ALLOW_CCK  FIELD32(0x00100000)
3578 +#define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3579 +#define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3580 +#define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3581 +#define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3582 +#define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3583 +#define OFDM_PROT_CFG_RTS_TH_EN                FIELD32(0x04000000)
3584 +
3585 +/*
3586 + * MM20_PROT_CFG: MM20 Protection
3587 + */
3588 +#define MM20_PROT_CFG                  0x136c
3589 +#define MM20_PROT_CFG_PROTECT_RATE     FIELD32(0x0000ffff)
3590 +#define MM20_PROT_CFG_PROTECT_CTRL     FIELD32(0x00030000)
3591 +#define MM20_PROT_CFG_PROTECT_NAV      FIELD32(0x000c0000)
3592 +#define MM20_PROT_CFG_TX_OP_ALLOW_CCK  FIELD32(0x00100000)
3593 +#define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3594 +#define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3595 +#define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3596 +#define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3597 +#define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3598 +#define MM20_PROT_CFG_RTS_TH_EN                FIELD32(0x04000000)
3599 +
3600 +/*
3601 + * MM40_PROT_CFG: MM40 Protection
3602 + */
3603 +#define MM40_PROT_CFG                  0x1370
3604 +#define MM40_PROT_CFG_PROTECT_RATE     FIELD32(0x0000ffff)
3605 +#define MM40_PROT_CFG_PROTECT_CTRL     FIELD32(0x00030000)
3606 +#define MM40_PROT_CFG_PROTECT_NAV      FIELD32(0x000c0000)
3607 +#define MM40_PROT_CFG_TX_OP_ALLOW_CCK  FIELD32(0x00100000)
3608 +#define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3609 +#define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3610 +#define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3611 +#define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3612 +#define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3613 +#define MM40_PROT_CFG_RTS_TH_EN                FIELD32(0x04000000)
3614 +
3615 +/*
3616 + * GF20_PROT_CFG: GF20 Protection
3617 + */
3618 +#define GF20_PROT_CFG                  0x1374
3619 +#define GF20_PROT_CFG_PROTECT_RATE     FIELD32(0x0000ffff)
3620 +#define GF20_PROT_CFG_PROTECT_CTRL     FIELD32(0x00030000)
3621 +#define GF20_PROT_CFG_PROTECT_NAV      FIELD32(0x000c0000)
3622 +#define GF20_PROT_CFG_TX_OP_ALLOW_CCK  FIELD32(0x00100000)
3623 +#define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3624 +#define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3625 +#define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3626 +#define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3627 +#define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3628 +#define GF20_PROT_CFG_RTS_TH_EN                FIELD32(0x04000000)
3629 +
3630 +/*
3631 + * GF40_PROT_CFG: GF40 Protection
3632 + */
3633 +#define GF40_PROT_CFG                  0x1378
3634 +#define GF40_PROT_CFG_PROTECT_RATE     FIELD32(0x0000ffff)
3635 +#define GF40_PROT_CFG_PROTECT_CTRL     FIELD32(0x00030000)
3636 +#define GF40_PROT_CFG_PROTECT_NAV      FIELD32(0x000c0000)
3637 +#define GF40_PROT_CFG_TX_OP_ALLOW_CCK  FIELD32(0x00100000)
3638 +#define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3639 +#define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3640 +#define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3641 +#define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3642 +#define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3643 +#define GF40_PROT_CFG_RTS_TH_EN                FIELD32(0x04000000)
3644 +
3645 +/*
3646 + * EXP_CTS_TIME:
3647 + */
3648 +#define EXP_CTS_TIME                   0x137c
3649 +
3650 +/*
3651 + * EXP_ACK_TIME:
3652 + */
3653 +#define EXP_ACK_TIME                   0x1380
3654 +
3655 +/*
3656 + * RX_FILTER_CFG: RX configuration register.
3657 + */
3658 +#define RX_FILTER_CFG                  0x1400
3659 +#define RX_FILTER_CFG_DROP_CRC_ERROR   FIELD32(0x00000001)
3660 +#define RX_FILTER_CFG_DROP_PHY_ERROR   FIELD32(0x00000002)
3661 +#define RX_FILTER_CFG_DROP_NOT_TO_ME   FIELD32(0x00000004)
3662 +#define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008)
3663 +#define RX_FILTER_CFG_DROP_VER_ERROR   FIELD32(0x00000010)
3664 +#define RX_FILTER_CFG_DROP_MULTICAST   FIELD32(0x00000020)
3665 +#define RX_FILTER_CFG_DROP_BROADCAST   FIELD32(0x00000040)
3666 +#define RX_FILTER_CFG_DROP_DUPLICATE   FIELD32(0x00000080)
3667 +#define RX_FILTER_CFG_DROP_CF_END_ACK  FIELD32(0x00000100)
3668 +#define RX_FILTER_CFG_DROP_CF_END      FIELD32(0x00000200)
3669 +#define RX_FILTER_CFG_DROP_ACK         FIELD32(0x00000400)
3670 +#define RX_FILTER_CFG_DROP_CTS         FIELD32(0x00000800)
3671 +#define RX_FILTER_CFG_DROP_RTS         FIELD32(0x00001000)
3672 +#define RX_FILTER_CFG_DROP_PSPOLL      FIELD32(0x00002000)
3673 +#define RX_FILTER_CFG_DROP_BA          FIELD32(0x00004000)
3674 +#define RX_FILTER_CFG_DROP_BAR         FIELD32(0x00008000)
3675 +#define RX_FILTER_CFG_DROP_CNTL                FIELD32(0x00010000)
3676 +
3677 +/*
3678 + * AUTO_RSP_CFG:
3679 + * AUTORESPONDER: 0: disable, 1: enable
3680 + * BAC_ACK_POLICY: 0:long, 1:short preamble
3681 + * CTS_40_MMODE: Response CTS 40MHz duplicate mode
3682 + * CTS_40_MREF: Response CTS 40MHz duplicate mode
3683 + * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble
3684 + * DUAL_CTS_EN: Power bit value in control frame
3685 + * ACK_CTS_PSM_BIT:Power bit value in control frame
3686 + */
3687 +#define AUTO_RSP_CFG                   0x1404
3688 +#define AUTO_RSP_CFG_AUTORESPONDER     FIELD32(0x00000001)
3689 +#define AUTO_RSP_CFG_BAC_ACK_POLICY    FIELD32(0x00000002)
3690 +#define AUTO_RSP_CFG_CTS_40_MMODE      FIELD32(0x00000004)
3691 +#define AUTO_RSP_CFG_CTS_40_MREF       FIELD32(0x00000008)
3692 +#define AUTO_RSP_CFG_AR_PREAMBLE       FIELD32(0x00000010)
3693 +#define AUTO_RSP_CFG_DUAL_CTS_EN       FIELD32(0x00000040)
3694 +#define AUTO_RSP_CFG_ACK_CTS_PSM_BIT   FIELD32(0x00000080)
3695 +
3696 +/*
3697 + * LEGACY_BASIC_RATE:
3698 + */
3699 +#define LEGACY_BASIC_RATE              0x1408
3700 +
3701 +/*
3702 + * HT_BASIC_RATE:
3703 + */
3704 +#define HT_BASIC_RATE                  0x140c
3705 +
3706 +/*
3707 + * HT_CTRL_CFG:
3708 + */
3709 +#define HT_CTRL_CFG                    0x1410
3710 +
3711 +/*
3712 + * SIFS_COST_CFG:
3713 + */
3714 +#define SIFS_COST_CFG                  0x1414
3715 +
3716 +/*
3717 + * RX_PARSER_CFG:
3718 + * Set NAV for all received frames
3719 + */
3720 +#define RX_PARSER_CFG                  0x1418
3721 +
3722 +/*
3723 + * TX_SEC_CNT0:
3724 + */
3725 +#define TX_SEC_CNT0                    0x1500
3726 +
3727 +/*
3728 + * RX_SEC_CNT0:
3729 + */
3730 +#define RX_SEC_CNT0                    0x1504
3731 +
3732 +/*
3733 + * CCMP_FC_MUTE:
3734 + */
3735 +#define CCMP_FC_MUTE                   0x1508
3736 +
3737 +/*
3738 + * TXOP_HLDR_ADDR0:
3739 + */
3740 +#define TXOP_HLDR_ADDR0                        0x1600
3741 +
3742 +/*
3743 + * TXOP_HLDR_ADDR1:
3744 + */
3745 +#define TXOP_HLDR_ADDR1                        0x1604
3746 +
3747 +/*
3748 + * TXOP_HLDR_ET:
3749 + */
3750 +#define TXOP_HLDR_ET                   0x1608
3751 +
3752 +/*
3753 + * QOS_CFPOLL_RA_DW0:
3754 + */
3755 +#define QOS_CFPOLL_RA_DW0              0x160c
3756 +
3757 +/*
3758 + * QOS_CFPOLL_RA_DW1:
3759 + */
3760 +#define QOS_CFPOLL_RA_DW1              0x1610
3761 +
3762 +/*
3763 + * QOS_CFPOLL_QC:
3764 + */
3765 +#define QOS_CFPOLL_QC                  0x1614
3766 +
3767 +/*
3768 + * RX_STA_CNT0: RX PLCP error count & RX CRC error count
3769 + */
3770 +#define RX_STA_CNT0                    0x1700
3771 +#define RX_STA_CNT0_CRC_ERR            FIELD32(0x0000ffff)
3772 +#define RX_STA_CNT0_PHY_ERR            FIELD32(0xffff0000)
3773 +
3774 +/*
3775 + * RX_STA_CNT1: RX False CCA count & RX LONG frame count
3776 + */
3777 +#define RX_STA_CNT1                    0x1704
3778 +#define RX_STA_CNT1_FALSE_CCA          FIELD32(0x0000ffff)
3779 +#define RX_STA_CNT1_PLCP_ERR           FIELD32(0xffff0000)
3780 +
3781 +/*
3782 + * RX_STA_CNT2:
3783 + */
3784 +#define RX_STA_CNT2                    0x1708
3785 +#define RX_STA_CNT2_RX_DUPLI_COUNT     FIELD32(0x0000ffff)
3786 +#define RX_STA_CNT2_RX_FIFO_OVERFLOW   FIELD32(0xffff0000)
3787 +
3788 +/*
3789 + * TX_STA_CNT0: TX Beacon count
3790 + */
3791 +#define TX_STA_CNT0                    0x170c
3792 +#define TX_STA_CNT0_TX_FAIL_COUNT      FIELD32(0x0000ffff)
3793 +#define TX_STA_CNT0_TX_BEACON_COUNT    FIELD32(0xffff0000)
3794 +
3795 +/*
3796 + * TX_STA_CNT1: TX tx count
3797 + */
3798 +#define TX_STA_CNT1                    0x1710
3799 +#define TX_STA_CNT1_TX_SUCCESS         FIELD32(0x0000ffff)
3800 +#define TX_STA_CNT1_TX_RETRANSMIT      FIELD32(0xffff0000)
3801 +
3802 +/*
3803 + * TX_STA_CNT2: TX tx count
3804 + */
3805 +#define TX_STA_CNT2                    0x1714
3806 +#define TX_STA_CNT2_TX_ZERO_LEN_COUNT  FIELD32(0x0000ffff)
3807 +#define TX_STA_CNT2_TX_UNDER_FLOW_COUNT        FIELD32(0xffff0000)
3808 +
3809 +/*
3810 + * TX_STA_FIFO: TX Result for specific PID status fifo register
3811 + */
3812 +#define TX_STA_FIFO                    0x1718
3813 +#define TX_STA_FIFO_B_VALID            FIELD32(0x00000001)
3814 +#define TX_STA_FIFO_PID_TYPE           FIELD32(0x0000001e)
3815 +#define TX_STA_FIFO_TX_SUCCESS         FIELD32(0x00000020)
3816 +#define TX_STA_FIFO_TX_AGGRE           FIELD32(0x00000040)
3817 +#define TX_STA_FIFO_TX_ACK_REQUIRED    FIELD32(0x00000080)
3818 +#define TX_STA_FIFO_WCID               FIELD32(0x0000ff00)
3819 +#define TX_STA_FIFO_SUCCESS_RATE       FIELD32(0xffff0000)
3820 +
3821 +/*
3822 + * TX_AGG_CNT: Debug counter
3823 + */
3824 +#define TX_AGG_CNT                     0x171c
3825 +#define TX_AGG_CNT_NON_AGG_TX_COUNT    FIELD32(0x0000ffff)
3826 +#define TX_AGG_CNT_AGG_TX_COUNT                FIELD32(0xffff0000)
3827 +
3828 +/*
3829 + * TX_AGG_CNT0:
3830 + */
3831 +#define TX_AGG_CNT0                    0x1720
3832 +#define TX_AGG_CNT0_AGG_SIZE_1_COUNT   FIELD32(0x0000ffff)
3833 +#define TX_AGG_CNT0_AGG_SIZE_2_COUNT   FIELD32(0xffff0000)
3834 +
3835 +/*
3836 + * TX_AGG_CNT1:
3837 + */
3838 +#define TX_AGG_CNT1                    0x1724
3839 +#define TX_AGG_CNT1_AGG_SIZE_3_COUNT   FIELD32(0x0000ffff)
3840 +#define TX_AGG_CNT1_AGG_SIZE_4_COUNT   FIELD32(0xffff0000)
3841 +
3842 +/*
3843 + * TX_AGG_CNT2:
3844 + */
3845 +#define TX_AGG_CNT2                    0x1728
3846 +#define TX_AGG_CNT2_AGG_SIZE_5_COUNT   FIELD32(0x0000ffff)
3847 +#define TX_AGG_CNT2_AGG_SIZE_6_COUNT   FIELD32(0xffff0000)
3848 +
3849 +/*
3850 + * TX_AGG_CNT3:
3851 + */
3852 +#define TX_AGG_CNT3                    0x172c
3853 +#define TX_AGG_CNT3_AGG_SIZE_7_COUNT   FIELD32(0x0000ffff)
3854 +#define TX_AGG_CNT3_AGG_SIZE_8_COUNT   FIELD32(0xffff0000)
3855 +
3856 +/*
3857 + * TX_AGG_CNT4:
3858 + */
3859 +#define TX_AGG_CNT4                    0x1730
3860 +#define TX_AGG_CNT4_AGG_SIZE_9_COUNT   FIELD32(0x0000ffff)
3861 +#define TX_AGG_CNT4_AGG_SIZE_10_COUNT  FIELD32(0xffff0000)
3862 +
3863 +/*
3864 + * TX_AGG_CNT5:
3865 + */
3866 +#define TX_AGG_CNT5                    0x1734
3867 +#define TX_AGG_CNT5_AGG_SIZE_11_COUNT  FIELD32(0x0000ffff)
3868 +#define TX_AGG_CNT5_AGG_SIZE_12_COUNT  FIELD32(0xffff0000)
3869 +
3870 +/*
3871 + * TX_AGG_CNT6:
3872 + */
3873 +#define TX_AGG_CNT6                    0x1738
3874 +#define TX_AGG_CNT6_AGG_SIZE_13_COUNT  FIELD32(0x0000ffff)
3875 +#define TX_AGG_CNT6_AGG_SIZE_14_COUNT  FIELD32(0xffff0000)
3876 +
3877 +/*
3878 + * TX_AGG_CNT7:
3879 + */
3880 +#define TX_AGG_CNT7                    0x173c
3881 +#define TX_AGG_CNT7_AGG_SIZE_15_COUNT  FIELD32(0x0000ffff)
3882 +#define TX_AGG_CNT7_AGG_SIZE_16_COUNT  FIELD32(0xffff0000)
3883 +
3884 +/*
3885 + * MPDU_DENSITY_CNT:
3886 + * TX_ZERO_DEL: TX zero length delimiter count
3887 + * RX_ZERO_DEL: RX zero length delimiter count
3888 + */
3889 +#define MPDU_DENSITY_CNT               0x1740
3890 +#define MPDU_DENSITY_CNT_TX_ZERO_DEL   FIELD32(0x0000ffff)
3891 +#define MPDU_DENSITY_CNT_RX_ZERO_DEL   FIELD32(0xffff0000)
3892 +
3893 +/*
3894 + * Security key table memory, base address = 0x1800
3895 + */
3896 +struct hw_pairwise_ta_entry {
3897 +       u8 address[6];
3898 +       u8 reserved[2];
3899 +} __attribute__ ((packed));
3900 +
3901 +struct wcid_entry {
3902 +       u8 rx_ba_bitmat7;
3903 +       u8 rx_ba_bitmat0;
3904 +       u8 mac[6];
3905 +} __attribute__ ((packed));
3906 +
3907 +struct hw_key_entry {
3908 +       u8 key[16];
3909 +       u8 tx_mic[8];
3910 +       u8 rx_mic[8];
3911 +} __attribute__ ((packed));
3912 +
3913 +/*
3914 + * Security key table memory.
3915 + * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry
3916 + * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry
3917 + * PAIRWISE_IVEIV_TABLE_BASE: 8-byte * 256-entry
3918 + * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry
3919 + * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry
3920 + * SHARED_KEY_TABLE_BASE: 32-byte * 16-entry
3921 + * SHARED_KEY_MODE_BASE: 32-byte * 16-entry
3922 + */
3923 +#define MAC_WCID_BASE                  0x1800
3924 +#define PAIRWISE_KEY_TABLE_BASE                0x4000
3925 +#define PAIRWISE_IVEIV_TABLE_BASE      0x6000
3926 +#define MAC_IVEIV_TABLE_BASE           0x6000
3927 +#define MAC_WCID_ATTRIBUTE_BASE                0x6800
3928 +#define SHARED_KEY_TABLE_BASE          0x6c00
3929 +#define SHARED_KEY_MODE_BASE           0x7000
3930 +
3931 +#define SHARED_KEY_ENTRY(__idx) \
3932 +       ( SHARED_KEY_TABLE_BASE + \
3933 +               ((__idx) * sizeof(struct hw_key_entry)) )
3934 +#define SHARED_KEY_MODE_ENTRY(__idx) \
3935 +       ( SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)) )
3936 +#define PAIRWISE_KEY_ENTRY(__idx) \
3937 +       ( PAIRWISE_KEY_TABLE_BASE + \
3938 +               ((__idx) * sizeof(struct hw_key_entry)) )
3939 +
3940 +#define MAC_WCID_ENTRY(__idx) \
3941 +       ( MAC_WCID_BASE + (2 * sizeof(u32) * (__idx)) )
3942 +#define MAC_WCID_ATTR_ENTRY(__idx) \
3943 +       ( MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)) )
3944 +
3945 +/*
3946 + * MAC_WCID_ATTRIBUTE:
3947 + * KEYTAB: 0: shared key table, 1: pairwise key table
3948 + * BSS_IDX: multipleBSS index for the WCID
3949 + */
3950 +#define MAC_WCID_ATTRIBUTE_KEYTAB      FIELD32(0x00000001)
3951 +#define MAC_WCID_ATTRIBUTE_PAIRKEY_MODE        FIELD32(0x0000000e)
3952 +#define MAC_WCID_ATTRIBUTE_BSS_IDX     FIELD32(0x00000070)
3953 +#define MAC_WCID_ATTRIBUTE_RX_WIUDF    FIELD32(0x00000380)
3954 +
3955 +/*
3956 + * SHARED_KEY_MODE:
3957 + */
3958 +#define SHARED_KEY_MODE_BSS0_KEY0      FIELD32(0x00000007)
3959 +#define SHARED_KEY_MODE_BSS0_KEY1      FIELD32(0x00000070)
3960 +#define SHARED_KEY_MODE_BSS0_KEY2      FIELD32(0x00000700)
3961 +#define SHARED_KEY_MODE_BSS0_KEY3      FIELD32(0x00007000)
3962 +#define SHARED_KEY_MODE_BSS1_KEY0      FIELD32(0x00070000)
3963 +#define SHARED_KEY_MODE_BSS1_KEY1      FIELD32(0x00700000)
3964 +#define SHARED_KEY_MODE_BSS1_KEY2      FIELD32(0x07000000)
3965 +#define SHARED_KEY_MODE_BSS1_KEY3      FIELD32(0x70000000)
3966 +
3967 +/*
3968 + * HOST-MCU communication
3969 + */
3970 +
3971 +/*
3972 + * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
3973 + */
3974 +#define H2M_MAILBOX_CSR                        0x7010
3975 +#define H2M_MAILBOX_CSR_ARG0           FIELD32(0x000000ff)
3976 +#define H2M_MAILBOX_CSR_ARG1           FIELD32(0x0000ff00)
3977 +#define H2M_MAILBOX_CSR_CMD_TOKEN      FIELD32(0x00ff0000)
3978 +#define H2M_MAILBOX_CSR_OWNER          FIELD32(0xff000000)
3979 +
3980 +/*
3981 + * H2M_MAILBOX_CID:
3982 + */
3983 +#define H2M_MAILBOX_CID                        0x7014
3984 +
3985 +/*
3986 + * H2M_MAILBOX_STATUS:
3987 + */
3988 +#define H2M_MAILBOX_STATUS             0x701c
3989 +
3990 +/*
3991 + * H2M_INT_SRC:
3992 + */
3993 +#define H2M_INT_SRC                    0x7024
3994 +
3995 +/*
3996 + * H2M_BBP_AGENT:
3997 + */
3998 +#define H2M_BBP_AGENT                  0x7028
3999 +
4000 +/*
4001 + * MCU_LEDCS: LED control for MCU Mailbox.
4002 + */
4003 +#define MCU_LEDCS_LED_MODE             FIELD8(0x1f)
4004 +#define MCU_LEDCS_POLARITY             FIELD8(0x01)
4005 +
4006 +/*
4007 + * HW_CS_CTS_BASE:
4008 + * Carrier-sense CTS frame base address.
4009 + * It's where mac stores carrier-sense frame for carrier-sense function.
4010 + */
4011 +#define HW_CS_CTS_BASE                 0x7700
4012 +
4013 +/*
4014 + * HW_DFS_CTS_BASE:
4015 + * FS CTS frame base address. It's where mac stores CTS frame for DFS.
4016 + */
4017 +#define HW_DFS_CTS_BASE                        0x7780
4018 +
4019 +/*
4020 + * TXRX control registers - base address 0x3000
4021 + */
4022 +
4023 +/*
4024 + * TXRX_CSR1:
4025 + * rt2860b  UNKNOWN reg use R/O Reg Addr 0x77d0 first..
4026 + */
4027 +#define TXRX_CSR1                      0x77d0
4028 +
4029 +/*
4030 + * HW_DEBUG_SETTING_BASE:
4031 + * since NULL frame won't be that long (256 byte)
4032 + * We steal 16 tail bytes to save debugging settings
4033 + */
4034 +#define HW_DEBUG_SETTING_BASE          0x77f0
4035 +#define HW_DEBUG_SETTING_BASE2         0x7770
4036 +
4037 +/*
4038 + * HW_BEACON_BASE
4039 + * In order to support maximum 8 MBSS and its maximum length
4040 + * is 512 bytes for each beacon
4041 + * Three section discontinue memory segments will be used.
4042 + * 1. The original region for BCN 0~3
4043 + * 2. Extract memory from FCE table for BCN 4~5
4044 + * 3. Extract memory from Pair-wise key table for BCN 6~7
4045 + *    It occupied those memory of wcid 238~253 for BCN 6
4046 + *    and wcid 222~237 for BCN 7
4047 + *
4048 + * IMPORTANT NOTE: Not sure why legacy driver does this,
4049 + * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6.
4050 + */
4051 +#define HW_BEACON_BASE0                        0x7800
4052 +#define HW_BEACON_BASE1                        0x7a00
4053 +#define HW_BEACON_BASE2                        0x7c00
4054 +#define HW_BEACON_BASE3                        0x7e00
4055 +#define HW_BEACON_BASE4                        0x7200
4056 +#define HW_BEACON_BASE5                        0x7400
4057 +#define HW_BEACON_BASE6                        0x5dc0
4058 +#define HW_BEACON_BASE7                        0x5bc0
4059 +
4060 +#define HW_BEACON_OFFSET(__index) \
4061 +       ( ((__index) < 4) ? ( HW_BEACON_BASE0 + (__index * 0x0200) ) : \
4062 +         (((__index) < 6) ? ( HW_BEACON_BASE4 + ((__index - 4) * 0x0200) ) : \
4063 +         (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))) )
4064 +
4065 +/*
4066 + * 8051 firmware image.
4067 + */
4068 +#define FIRMWARE_RT2860                        "rt2860.bin"
4069 +#define FIRMWARE_IMAGE_BASE            0x2000
4070 +
4071 +/*
4072 + * BBP registers.
4073 + * The wordsize of the BBP is 8 bits.
4074 + */
4075 +
4076 +/*
4077 + * BBP 1: TX Antenna
4078 + */
4079 +#define BBP1_TX_POWER                  FIELD8(0x07)
4080 +#define BBP1_TX_ANTENNA                        FIELD8(0x18)
4081 +
4082 +/*
4083 + * BBP 3: RX Antenna
4084 + */
4085 +#define BBP3_RX_ANTENNA                        FIELD8(0x18)
4086 +
4087 +/*
4088 + * RF registers
4089 + */
4090 +
4091 +/*
4092 + * RF 2
4093 + */
4094 +#define RF2_ANTENNA_RX2                        FIELD32(0x00000040)
4095 +#define RF2_ANTENNA_TX1                        FIELD32(0x00004000)
4096 +#define RF2_ANTENNA_RX1                        FIELD32(0x00020000)
4097 +
4098 +/*
4099 + * RF 3
4100 + */
4101 +#define RF3_TXPOWER_G                  FIELD32(0x00003e00)
4102 +#define RF3_TXPOWER_A_7DBM_BOOST       FIELD32(0x00000200)
4103 +#define RF3_TXPOWER_A                  FIELD32(0x00003c00)
4104 +
4105 +/*
4106 + * RF 4
4107 + */
4108 +#define RF4_TXPOWER_G                  FIELD32(0x000007c0)
4109 +#define RF4_TXPOWER_A_7DBM_BOOST       FIELD32(0x00000040)
4110 +#define RF4_TXPOWER_A                  FIELD32(0x00000780)
4111 +#define RF4_FREQ_OFFSET                        FIELD32(0x001f8000)
4112 +#define RF4_BW40                       FIELD32(0x00200000)
4113 +
4114 +/*
4115 + * EEPROM content.
4116 + * The wordsize of the EEPROM is 16 bits.
4117 + */
4118 +
4119 +/*
4120 + * EEPROM Version
4121 + */
4122 +#define EEPROM_VERSION                 0x0001
4123 +#define EEPROM_VERSION_FAE             FIELD16(0x00ff)
4124 +#define EEPROM_VERSION_VERSION         FIELD16(0xff00)
4125 +
4126 +/*
4127 + * HW MAC address.
4128 + */
4129 +#define EEPROM_MAC_ADDR_0              0x0002
4130 +#define EEPROM_MAC_ADDR_BYTE0          FIELD16(0x00ff)
4131 +#define EEPROM_MAC_ADDR_BYTE1          FIELD16(0xff00)
4132 +#define EEPROM_MAC_ADDR1               0x0003
4133 +#define EEPROM_MAC_ADDR_BYTE2          FIELD16(0x00ff)
4134 +#define EEPROM_MAC_ADDR_BYTE3          FIELD16(0xff00)
4135 +#define EEPROM_MAC_ADDR_2              0x0004
4136 +#define EEPROM_MAC_ADDR_BYTE4          FIELD16(0x00ff)
4137 +#define EEPROM_MAC_ADDR_BYTE5          FIELD16(0xff00)
4138 +
4139 +/*
4140 + * EEPROM ANTENNA config
4141 + * RXPATH: 1: 1R, 2: 2R, 3: 3R
4142 + * TXPATH: 1: 1T, 2: 2T
4143 + */
4144 +#define        EEPROM_ANTENNA                  0x001a
4145 +#define EEPROM_ANTENNA_RXPATH          FIELD16(0x000f)
4146 +#define EEPROM_ANTENNA_TXPATH          FIELD16(0x00f0)
4147 +#define EEPROM_ANTENNA_RF_TYPE         FIELD16(0x0f00)
4148 +
4149 +/*
4150 + * EEPROM NIC config
4151 + * CARDBUS_ACCEL: 0 - enable, 1 - disable
4152 + */
4153 +#define        EEPROM_NIC                      0x001b
4154 +#define EEPROM_NIC_HW_RADIO            FIELD16(0x0001)
4155 +#define EEPROM_NIC_DYNAMIC_TX_AGC      FIELD16(0x0002)
4156 +#define EEPROM_NIC_EXTERNAL_LNA_BG     FIELD16(0x0004)
4157 +#define EEPROM_NIC_EXTERNAL_LNA_A      FIELD16(0x0008)
4158 +#define EEPROM_NIC_CARDBUS_ACCEL       FIELD16(0x0010)
4159 +#define EEPROM_NIC_BW40M_SB_BG         FIELD16(0x0020)
4160 +#define EEPROM_NIC_BW40M_SB_A          FIELD16(0x0040)
4161 +#define EEPROM_NIC_WPS_PBC             FIELD16(0x0080)
4162 +#define EEPROM_NIC_BW40M_BG            FIELD16(0x0100)
4163 +#define EEPROM_NIC_BW40M_A             FIELD16(0x0200)
4164 +
4165 +/*
4166 + * EEPROM frequency
4167 + */
4168 +#define        EEPROM_FREQ                     0x001d
4169 +#define EEPROM_FREQ_OFFSET             FIELD16(0x00ff)
4170 +#define EEPROM_FREQ_LED_MODE           FIELD16(0x7f00)
4171 +#define EEPROM_FREQ_LED_POLARITY       FIELD16(0x1000)
4172 +
4173 +/*
4174 + * EEPROM LED
4175 + * POLARITY_RDY_G: Polarity RDY_G setting.
4176 + * POLARITY_RDY_A: Polarity RDY_A setting.
4177 + * POLARITY_ACT: Polarity ACT setting.
4178 + * POLARITY_GPIO_0: Polarity GPIO0 setting.
4179 + * POLARITY_GPIO_1: Polarity GPIO1 setting.
4180 + * POLARITY_GPIO_2: Polarity GPIO2 setting.
4181 + * POLARITY_GPIO_3: Polarity GPIO3 setting.
4182 + * POLARITY_GPIO_4: Polarity GPIO4 setting.
4183 + * LED_MODE: Led mode.
4184 + */
4185 +#define EEPROM_LED1                    0x001e
4186 +#define EEPROM_LED2                    0x001f
4187 +#define EEPROM_LED3                    0x0020
4188 +#define EEPROM_LED_POLARITY_RDY_BG     FIELD16(0x0001)
4189 +#define EEPROM_LED_POLARITY_RDY_A      FIELD16(0x0002)
4190 +#define EEPROM_LED_POLARITY_ACT                FIELD16(0x0004)
4191 +#define EEPROM_LED_POLARITY_GPIO_0     FIELD16(0x0008)
4192 +#define EEPROM_LED_POLARITY_GPIO_1     FIELD16(0x0010)
4193 +#define EEPROM_LED_POLARITY_GPIO_2     FIELD16(0x0020)
4194 +#define EEPROM_LED_POLARITY_GPIO_3     FIELD16(0x0040)
4195 +#define EEPROM_LED_POLARITY_GPIO_4     FIELD16(0x0080)
4196 +#define EEPROM_LED_LED_MODE            FIELD16(0x1f00)
4197 +
4198 +/*
4199 + * EEPROM LNA
4200 + */
4201 +#define EEPROM_LNA                     0x0022
4202 +#define EEPROM_LNA_BG                  FIELD16(0x00ff)
4203 +#define EEPROM_LNA_A0                  FIELD16(0xff00)
4204 +
4205 +/*
4206 + * EEPROM RSSI BG offset
4207 + */
4208 +#define EEPROM_RSSI_BG                 0x0023
4209 +#define EEPROM_RSSI_BG_OFFSET0         FIELD16(0x00ff)
4210 +#define EEPROM_RSSI_BG_OFFSET1         FIELD16(0xff00)
4211 +
4212 +/*
4213 + * EEPROM RSSI BG2 offset
4214 + */
4215 +#define EEPROM_RSSI_BG2                        0x0024
4216 +#define EEPROM_RSSI_BG2_OFFSET2                FIELD16(0x00ff)
4217 +#define EEPROM_RSSI_BG2_LNA_A1         FIELD16(0xff00)
4218 +
4219 +/*
4220 + * EEPROM RSSI A offset
4221 + */
4222 +#define EEPROM_RSSI_A                  0x0025
4223 +#define EEPROM_RSSI_A_OFFSET0          FIELD16(0x00ff)
4224 +#define EEPROM_RSSI_A_OFFSET1          FIELD16(0xff00)
4225 +
4226 +/*
4227 + * EEPROM RSSI A2 offset
4228 + */
4229 +#define EEPROM_RSSI_A2                 0x0026
4230 +#define EEPROM_RSSI_A2_OFFSET2         FIELD16(0x00ff)
4231 +#define EEPROM_RSSI_A2_LNA_A2          FIELD16(0xff00)
4232 +
4233 +/*
4234 + * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power.
4235 + *     This is delta in 40MHZ.
4236 + * VALUE: Tx Power dalta value (MAX=4)
4237 + * TYPE: 1: Plus the delta value, 0: minus the delta value
4238 + * TXPOWER: Enable:
4239 + */
4240 +#define EEPROM_TXPOWER_DELTA           0x0028
4241 +#define EEPROM_TXPOWER_DELTA_VALUE     FIELD16(0x003f)
4242 +#define EEPROM_TXPOWER_DELTA_TYPE      FIELD16(0x0040)
4243 +#define EEPROM_TXPOWER_DELTA_TXPOWER   FIELD16(0x0080)
4244 +
4245 +/*
4246 + * EEPROM TXPOWER 802.11G
4247 + */
4248 +#define        EEPROM_TXPOWER_BG1              0x0029
4249 +#define        EEPROM_TXPOWER_BG2              0x0030
4250 +#define EEPROM_TXPOWER_BG_SIZE         7
4251 +#define EEPROM_TXPOWER_BG_1            FIELD16(0x00ff)
4252 +#define EEPROM_TXPOWER_BG_2            FIELD16(0xff00)
4253 +
4254 +/*
4255 + * EEPROM TXPOWER 802.11A
4256 + */
4257 +#define EEPROM_TXPOWER_A1              0x003c
4258 +#define EEPROM_TXPOWER_A2              0x0053
4259 +#define EEPROM_TXPOWER_A_SIZE          6
4260 +#define EEPROM_TXPOWER_A_1             FIELD16(0x00ff)
4261 +#define EEPROM_TXPOWER_A_2             FIELD16(0xff00)
4262 +
4263 +/*
4264 + * EEPROM TXpower byrate: 20MHZ power
4265 + */
4266 +#define EEPROM_TXPOWER_BYRATE          0x006f
4267 +
4268 +/*
4269 + * EEPROM BBP.
4270 + */
4271 +#define        EEPROM_BBP_START                0x0078
4272 +#define EEPROM_BBP_SIZE                        16
4273 +#define EEPROM_BBP_VALUE               FIELD16(0x00ff)
4274 +#define EEPROM_BBP_REG_ID              FIELD16(0xff00)
4275 +
4276 +/*
4277 + * MCU mailbox commands.
4278 + */
4279 +#define MCU_SLEEP                      0x30
4280 +#define MCU_WAKEUP                     0x31
4281 +#define MCU_LED                                0x50
4282 +#define MCU_LED_STRENGTH               0x51
4283 +#define MCU_LED_1                      0x52
4284 +#define MCU_LED_2                      0x53
4285 +#define MCU_LED_3                      0x54
4286 +#define MCU_RADAR                      0x60
4287 +#define MCU_BOOT_SIGNAL                        0x72
4288 +
4289 +/*
4290 + * DMA descriptor defines.
4291 + */
4292 +#define TXD_DESC_SIZE                  ( 4 * sizeof(__le32) )
4293 +#define TXWI_DESC_SIZE                 ( 4 * sizeof(__le32) )
4294 +#define RXD_DESC_SIZE                  ( 4 * sizeof(__le32) )
4295 +#define RXWI_DESC_SIZE                 ( 4 * sizeof(__le32) )
4296 +
4297 +/*
4298 + * TX descriptor format for TX, PRIO and Beacon Ring.
4299 + */
4300 +
4301 +/*
4302 + * Word0
4303 + */
4304 +#define TXD_W0_SD_PTR0                 FIELD32(0xffffffff)
4305 +
4306 +/*
4307 + * Word1
4308 + */
4309 +#define TXD_W1_SD_LEN1                 FIELD32(0x00003fff)
4310 +#define TXD_W1_LAST_SEC1               FIELD32(0x00004000)
4311 +#define TXD_W1_BURST                   FIELD32(0x00008000)
4312 +#define TXD_W1_SD_LEN0                 FIELD32(0x3fff0000)
4313 +#define TXD_W1_LAST_SEC0               FIELD32(0x40000000)
4314 +#define TXD_W1_DMA_DONE                        FIELD32(0x80000000)
4315 +
4316 +/*
4317 + * Word2
4318 + */
4319 +#define TXD_W2_SD_PTR1                 FIELD32(0xffffffff)
4320 +
4321 +/*
4322 + * Word3
4323 + * WIV: Wireless Info Valid. 1: Driver filled WI,  0: DMA needs to copy WI
4324 + * QSEL: Select on-chip FIFO ID for 2nd-stage output scheduler.
4325 + *       0:MGMT, 1:HCCA 2:EDCA
4326 + */
4327 +#define TXD_W3_WIV                     FIELD32(0x01000000)
4328 +#define TXD_W3_QSEL                    FIELD32(0x06000000)
4329 +#define TXD_W3_TCO                     FIELD32(0x20000000)
4330 +#define TXD_W3_UCO                     FIELD32(0x40000000)
4331 +#define TXD_W3_ICO                     FIELD32(0x80000000)
4332 +
4333 +/*
4334 + * TX WI structure
4335 + */
4336 +
4337 +/*
4338 + * Word0
4339 + * FRAG: 1 To inform TKIP engine this is a fragment.
4340 + * MIMO_PS: The remote peer is in dynamic MIMO-PS mode
4341 + * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs
4342 + * BW: Channel bandwidth 20MHz or 40 MHz
4343 + * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED
4344 + */
4345 +#define TXWI_W0_FRAG                   FIELD32(0x00000001)
4346 +#define TXWI_W0_MIMO_PS                        FIELD32(0x00000002)
4347 +#define TXWI_W0_CF_ACK                 FIELD32(0x00000004)
4348 +#define TXWI_W0_TS                     FIELD32(0x00000008)
4349 +#define TXWI_W0_AMPDU                  FIELD32(0x00000010)
4350 +#define TXWI_W0_MPDU_DENSITY           FIELD32(0x000000e0)
4351 +#define TXWI_W0_TX_OP                  FIELD32(0x00000300)
4352 +#define TXWI_W0_MCS                    FIELD32(0x007f0000)
4353 +#define TXWI_W0_BW                     FIELD32(0x00800000)
4354 +#define TXWI_W0_SHORT_GI               FIELD32(0x01000000)
4355 +#define TXWI_W0_STBC                   FIELD32(0x06000000)
4356 +#define TXWI_W0_IFS                    FIELD32(0x08000000)
4357 +#define TXWI_W0_PHYMODE                        FIELD32(0xc0000000)
4358 +
4359 +/*
4360 + * Word1
4361 + */
4362 +#define TXWI_W1_ACK                    FIELD32(0x00000001)
4363 +#define TXWI_W1_NSEQ                   FIELD32(0x00000002)
4364 +#define TXWI_W1_BW_WIN_SIZE            FIELD32(0x000000fc)
4365 +#define TXWI_W1_WIRELESS_CLI_ID                FIELD32(0x0000ff00)
4366 +#define TXWI_W1_MPDU_TOTAL_BYTE_COUNT  FIELD32(0x0fff0000)
4367 +#define TXWI_W1_PACKETID               FIELD32(0xf0000000)
4368 +
4369 +/*
4370 + * Word2
4371 + */
4372 +#define TXWI_W2_IV                     FIELD32(0xffffffff)
4373 +
4374 +/*
4375 + * Word3
4376 + */
4377 +#define TXWI_W3_EIV                    FIELD32(0xffffffff)
4378 +
4379 +/*
4380 + * RX descriptor format for RX Ring.
4381 + */
4382 +
4383 +/*
4384 + * Word0
4385 + */
4386 +#define RXD_W0_SDP0                    FIELD32(0xffffffff)
4387 +
4388 +/*
4389 + * Word1
4390 + */
4391 +#define RXD_W1_SDL1                    FIELD32(0x00003fff)
4392 +#define RXD_W1_SDL0                    FIELD32(0x3fff0000)
4393 +#define RXD_W1_LS0                     FIELD32(0x40000000)
4394 +#define RXD_W1_DMA_DONE                        FIELD32(0x80000000)
4395 +
4396 +/*
4397 + * Word2
4398 + */
4399 +#define RXD_W2_SDP1                    FIELD32(0xffffffff)
4400 +
4401 +/*
4402 + * Word3
4403 + * AMSDU: RX with 802.3 header, not 802.11 header.
4404 + * DECRYPTED: This frame is being decrypted.
4405 + */
4406 +#define RXD_W3_BA                      FIELD32(0x00000001)
4407 +#define RXD_W3_DATA                    FIELD32(0x00000002)
4408 +#define RXD_W3_NULLDATA                        FIELD32(0x00000004)
4409 +#define RXD_W3_FRAG                    FIELD32(0x00000008)
4410 +#define RXD_W3_UNICAST_TO_ME           FIELD32(0x00000010)
4411 +#define RXD_W3_MULTICAST               FIELD32(0x00000020)
4412 +#define RXD_W3_BROADCAST               FIELD32(0x00000040)
4413 +#define RXD_W3_MY_BSS                  FIELD32(0x00000080)
4414 +#define RXD_W3_CRC_ERROR               FIELD32(0x00000100)
4415 +#define RXD_W3_CIPHER_ERROR            FIELD32(0x00000600)
4416 +#define RXD_W3_AMSDU                   FIELD32(0x00000800)
4417 +#define RXD_W3_HTC                     FIELD32(0x00001000)
4418 +#define RXD_W3_RSSI                    FIELD32(0x00002000)
4419 +#define RXD_W3_L2PAD                   FIELD32(0x00004000)
4420 +#define RXD_W3_AMPDU                   FIELD32(0x00008000)
4421 +#define RXD_W3_DECRYPTED               FIELD32(0x00010000)
4422 +#define RXD_W3_PLCP_SIGNAL             FIELD32(0x00020000)
4423 +#define RXD_W3_PLCP_RSSI               FIELD32(0x00040000)
4424 +
4425 +/*
4426 + * RX WI structure
4427 + */
4428 +
4429 +/*
4430 + * Word0
4431 + */
4432 +#define RXWI_W0_WIRELESS_CLI_ID                FIELD32(0x000000ff)
4433 +#define RXWI_W0_KEY_INDEX              FIELD32(0x00000300)
4434 +#define RXWI_W0_BSSID                  FIELD32(0x00001c00)
4435 +#define RXWI_W0_UDF                    FIELD32(0x0000e000)
4436 +#define RXWI_W0_MPDU_TOTAL_BYTE_COUNT  FIELD32(0x0fff0000)
4437 +#define RXWI_W0_TID                    FIELD32(0xf0000000)
4438 +
4439 +/*
4440 + * Word1
4441 + */
4442 +#define RXWI_W1_FRAG                   FIELD32(0x0000000f)
4443 +#define RXWI_W1_SEQUENCE               FIELD32(0x0000fff0)
4444 +#define RXWI_W1_MCS                    FIELD32(0x007f0000)
4445 +#define RXWI_W1_BW                     FIELD32(0x00800000)
4446 +#define RXWI_W1_SHORT_GI               FIELD32(0x01000000)
4447 +#define RXWI_W1_STBC                   FIELD32(0x06000000)
4448 +#define RXWI_W1_PHYMODE                        FIELD32(0xc0000000)
4449 +
4450 +/*
4451 + * Word2
4452 + */
4453 +#define RXWI_W2_RSSI0                  FIELD32(0x000000ff)
4454 +#define RXWI_W2_RSSI1                  FIELD32(0x0000ff00)
4455 +#define RXWI_W2_RSSI2                  FIELD32(0x00ff0000)
4456 +
4457 +/*
4458 + * Word3
4459 + */
4460 +#define RXWI_W3_SNR0                   FIELD32(0x000000ff)
4461 +#define RXWI_W3_SNR1                   FIELD32(0x0000ff00)
4462 +
4463 +/*
4464 + * Macro's for converting txpower from EEPROM to mac80211 value
4465 + * and from mac80211 value to register value.
4466 + */
4467 +#define MIN_G_TXPOWER  0
4468 +#define MIN_A_TXPOWER  -7
4469 +#define MAX_G_TXPOWER  31
4470 +#define MAX_A_TXPOWER  15
4471 +#define DEFAULT_TXPOWER        5
4472 +
4473 +#define TXPOWER_G_FROM_DEV(__txpower) \
4474 +       ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
4475 +
4476 +#define TXPOWER_G_TO_DEV(__txpower) \
4477 +       clamp_t(char, __txpower, MIN_G_TXPOWER, MAX_G_TXPOWER)
4478 +
4479 +#define TXPOWER_A_FROM_DEV(__txpower) \
4480 +       ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
4481 +
4482 +#define TXPOWER_A_TO_DEV(__txpower) \
4483 +       clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER)
4484 +
4485 +#endif /* RT2800PCI_H */
4486 diff --git a/drivers/net/wireless/rt2x00/rt2800usb.c b/drivers/net/wireless/rt2x00/rt2800usb.c
4487 new file mode 100644
4488 index 0000000..761a7ec
4489 --- /dev/null
4490 +++ b/drivers/net/wireless/rt2x00/rt2800usb.c
4491 @@ -0,0 +1,2498 @@
4492 +/*
4493 +       Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
4494 +       <http://rt2x00.serialmonkey.com>
4495 +
4496 +       This program is free software; you can redistribute it and/or modify
4497 +       it under the terms of the GNU General Public License as published by
4498 +       the Free Software Foundation; either version 2 of the License, or
4499 +       (at your option) any later version.
4500 +
4501 +       This program is distributed in the hope that it will be useful,
4502 +       but WITHOUT ANY WARRANTY; without even the implied warranty of
4503 +       MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4504 +       GNU General Public License for more details.
4505 +
4506 +       You should have received a copy of the GNU General Public License
4507 +       along with this program; if not, write to the
4508 +       Free Software Foundation, Inc.,
4509 +       59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
4510 + */
4511 +
4512 +/*
4513 +       Module: rt2800usb
4514 +       Abstract: rt2800usb device specific routines.
4515 +       Supported chipsets: RT2800U.
4516 + */
4517 +
4518 +#include <linux/crc-ccitt.h>
4519 +#include <linux/delay.h>
4520 +#include <linux/etherdevice.h>
4521 +#include <linux/init.h>
4522 +#include <linux/kernel.h>
4523 +#include <linux/module.h>
4524 +#include <linux/usb.h>
4525 +
4526 +#include "rt2x00.h"
4527 +#include "rt2x00usb.h"
4528 +#include "rt2800usb.h"
4529 +
4530 +/*
4531 + * Allow hardware encryption to be disabled.
4532 + */
4533 +static int modparam_nohwcrypt = 0;
4534 +module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
4535 +MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
4536 +
4537 +/*
4538 + * Register access.
4539 + * All access to the CSR registers will go through the methods
4540 + * rt2x00usb_register_read and rt2x00usb_register_write.
4541 + * BBP and RF register require indirect register access,
4542 + * and use the CSR registers BBPCSR and RFCSR to achieve this.
4543 + * These indirect registers work with busy bits,
4544 + * and we will try maximal REGISTER_BUSY_COUNT times to access
4545 + * the register while taking a REGISTER_BUSY_DELAY us delay
4546 + * between each attampt. When the busy bit is still set at that time,
4547 + * the access attempt is considered to have failed,
4548 + * and we will print an error.
4549 + * The _lock versions must be used if you already hold the csr_mutex
4550 + */
4551 +#define WAIT_FOR_BBP(__dev, __reg) \
4552 +       rt2x00usb_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
4553 +#define WAIT_FOR_RF(__dev, __reg) \
4554 +       rt2x00usb_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
4555 +#define WAIT_FOR_MCU(__dev, __reg) \
4556 +       rt2x00usb_regbusy_read((__dev), H2M_MAILBOX_CSR, \
4557 +                              H2M_MAILBOX_CSR_OWNER, (__reg))
4558 +
4559 +static void rt2800usb_bbp_write(struct rt2x00_dev *rt2x00dev,
4560 +                               const unsigned int word, const u8 value)
4561 +{
4562 +       u32 reg;
4563 +
4564 +       mutex_lock(&rt2x00dev->csr_mutex);
4565 +
4566 +       /*
4567 +        * Wait until the BBP becomes available, afterwards we
4568 +        * can safely write the new data into the register.
4569 +        */
4570 +       if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
4571 +               reg = 0;
4572 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
4573 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
4574 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
4575 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
4576 +
4577 +               rt2x00usb_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
4578 +       }
4579 +
4580 +       mutex_unlock(&rt2x00dev->csr_mutex);
4581 +}
4582 +
4583 +static void rt2800usb_bbp_read(struct rt2x00_dev *rt2x00dev,
4584 +                              const unsigned int word, u8 *value)
4585 +{
4586 +       u32 reg;
4587 +
4588 +       mutex_lock(&rt2x00dev->csr_mutex);
4589 +
4590 +       /*
4591 +        * Wait until the BBP becomes available, afterwards we
4592 +        * can safely write the read request into the register.
4593 +        * After the data has been written, we wait until hardware
4594 +        * returns the correct value, if at any time the register
4595 +        * doesn't become available in time, reg will be 0xffffffff
4596 +        * which means we return 0xff to the caller.
4597 +        */
4598 +       if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
4599 +               reg = 0;
4600 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
4601 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
4602 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
4603 +
4604 +               rt2x00usb_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
4605 +
4606 +               WAIT_FOR_BBP(rt2x00dev, &reg);
4607 +       }
4608 +
4609 +       *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
4610 +
4611 +       mutex_unlock(&rt2x00dev->csr_mutex);
4612 +}
4613 +
4614 +static void rt2800usb_rf_write(struct rt2x00_dev *rt2x00dev,
4615 +                              const unsigned int word, const u32 value)
4616 +{
4617 +       u32 reg;
4618 +
4619 +       if (!word)
4620 +               return;
4621 +
4622 +       mutex_lock(&rt2x00dev->csr_mutex);
4623 +
4624 +       /*
4625 +        * Wait until the RF becomes available, afterwards we
4626 +        * can safely write the new data into the register.
4627 +        */
4628 +       if (WAIT_FOR_RF(rt2x00dev, &reg)) {
4629 +               reg = 0;
4630 +               rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
4631 +               rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
4632 +               rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
4633 +               rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
4634 +
4635 +               rt2x00usb_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
4636 +               rt2x00_rf_write(rt2x00dev, word, value);
4637 +       }
4638 +
4639 +       mutex_unlock(&rt2x00dev->csr_mutex);
4640 +}
4641 +
4642 +static void rt2800usb_mcu_request(struct rt2x00_dev *rt2x00dev,
4643 +                                 const u8 command, const u8 token,
4644 +                                 const u8 arg0, const u8 arg1)
4645 +{
4646 +       u32 reg;
4647 +
4648 +       mutex_lock(&rt2x00dev->csr_mutex);
4649 +
4650 +       /*
4651 +        * Wait until the MCU becomes available, afterwards we
4652 +        * can safely write the new data into the register.
4653 +        */
4654 +       if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
4655 +               rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
4656 +               rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
4657 +               rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
4658 +               rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
4659 +               rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
4660 +
4661 +               reg = 0;
4662 +               rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
4663 +               rt2x00usb_register_write(rt2x00dev, HOST_CMD_CSR, reg);
4664 +       }
4665 +
4666 +       mutex_unlock(&rt2x00dev->csr_mutex);
4667 +}
4668 +
4669 +#ifdef CONFIG_RT2X00_LIB_DEBUGFS
4670 +static const struct rt2x00debug rt2800usb_rt2x00debug = {
4671 +       .owner  = THIS_MODULE,
4672 +       .csr    = {
4673 +               .read           = rt2x00usb_register_read,
4674 +               .write          = rt2x00usb_register_write,
4675 +               .flags          = RT2X00DEBUGFS_OFFSET,
4676 +               .word_base      = CSR_REG_BASE,
4677 +               .word_size      = sizeof(u32),
4678 +               .word_count     = CSR_REG_SIZE / sizeof(u32),
4679 +       },
4680 +       .eeprom = {
4681 +               .read           = rt2x00_eeprom_read,
4682 +               .write          = rt2x00_eeprom_write,
4683 +               .word_base      = EEPROM_BASE,
4684 +               .word_size      = sizeof(u16),
4685 +               .word_count     = EEPROM_SIZE / sizeof(u16),
4686 +       },
4687 +       .bbp    = {
4688 +               .read           = rt2800usb_bbp_read,
4689 +               .write          = rt2800usb_bbp_write,
4690 +               .word_base      = BBP_BASE,
4691 +               .word_size      = sizeof(u8),
4692 +               .word_count     = BBP_SIZE / sizeof(u8),
4693 +       },
4694 +       .rf     = {
4695 +               .read           = rt2x00_rf_read,
4696 +               .write          = rt2800usb_rf_write,
4697 +               .word_base      = RF_BASE,
4698 +               .word_size      = sizeof(u32),
4699 +               .word_count     = RF_SIZE / sizeof(u32),
4700 +       },
4701 +};
4702 +#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
4703 +
4704 +#ifdef CONFIG_RT2X00_LIB_LEDS
4705 +static void rt2800usb_brightness_set(struct led_classdev *led_cdev,
4706 +                                    enum led_brightness brightness)
4707 +{
4708 +       struct rt2x00_led *led =
4709 +           container_of(led_cdev, struct rt2x00_led, led_dev);
4710 +       unsigned int enabled = brightness != LED_OFF;
4711 +       unsigned int bg_mode =
4712 +           (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
4713 +       unsigned int polarity =
4714 +               rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
4715 +                                  EEPROM_FREQ_LED_POLARITY);
4716 +       unsigned int ledmode =
4717 +               rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
4718 +                                  EEPROM_FREQ_LED_MODE);
4719 +
4720 +       if (led->type == LED_TYPE_RADIO) {
4721 +               rt2800usb_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
4722 +                                     enabled ? 0x20 : 0);
4723 +       } else if (led->type == LED_TYPE_ASSOC) {
4724 +               rt2800usb_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
4725 +                                     enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
4726 +       } else if (led->type == LED_TYPE_QUALITY) {
4727 +               /*
4728 +                * The brightness is divided into 6 levels (0 - 5),
4729 +                * The specs tell us the following levels:
4730 +                *      0, 1 ,3, 7, 15, 31
4731 +                * to determine the level in a simple way we can simply
4732 +                * work with bitshifting:
4733 +                *      (1 << level) - 1
4734 +                */
4735 +               rt2800usb_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
4736 +                                     (1 << brightness / (LED_FULL / 6)) - 1,
4737 +                                     polarity);
4738 +       }
4739 +}
4740 +
4741 +static int rt2800usb_blink_set(struct led_classdev *led_cdev,
4742 +                              unsigned long *delay_on,
4743 +                              unsigned long *delay_off)
4744 +{
4745 +       struct rt2x00_led *led =
4746 +           container_of(led_cdev, struct rt2x00_led, led_dev);
4747 +       u32 reg;
4748 +
4749 +       rt2x00usb_register_read(led->rt2x00dev, LED_CFG, &reg);
4750 +       rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
4751 +       rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
4752 +       rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
4753 +       rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
4754 +       rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 12);
4755 +       rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
4756 +       rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
4757 +       rt2x00usb_register_write(led->rt2x00dev, LED_CFG, reg);
4758 +
4759 +       return 0;
4760 +}
4761 +
4762 +static void rt2800usb_init_led(struct rt2x00_dev *rt2x00dev,
4763 +                              struct rt2x00_led *led,
4764 +                              enum led_type type)
4765 +{
4766 +       led->rt2x00dev = rt2x00dev;
4767 +       led->type = type;
4768 +       led->led_dev.brightness_set = rt2800usb_brightness_set;
4769 +       led->led_dev.blink_set = rt2800usb_blink_set;
4770 +       led->flags = LED_INITIALIZED;
4771 +}
4772 +#endif /* CONFIG_RT2X00_LIB_LEDS */
4773 +
4774 +/*
4775 + * Configuration handlers.
4776 + */
4777 +static void rt2800usb_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
4778 +                                      struct rt2x00lib_crypto *crypto,
4779 +                                      struct ieee80211_key_conf *key)
4780 +{
4781 +       u32 offset;
4782 +       u32 reg;
4783 +
4784 +       offset = MAC_WCID_ATTR_ENTRY(crypto->aid);
4785 +
4786 +       reg = 0;
4787 +       rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
4788 +                          !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
4789 +       rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_PAIRKEY_MODE,
4790 +                          crypto->cipher);
4791 +       rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
4792 +                          (crypto->cmd == SET_KEY) ? crypto->bssidx : 0);
4793 +       rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
4794 +       rt2x00usb_register_write(rt2x00dev, offset, reg);
4795 +}
4796 +
4797 +static int rt2800usb_config_shared_key(struct rt2x00_dev *rt2x00dev,
4798 +                                      struct rt2x00lib_crypto *crypto,
4799 +                                      struct ieee80211_key_conf *key)
4800 +{
4801 +       struct hw_key_entry key_entry;
4802 +       struct rt2x00_field32 field;
4803 +       int timeout;
4804 +       u32 offset;
4805 +       u32 mask;
4806 +       u32 reg;
4807 +
4808 +       if (crypto->cmd == SET_KEY) {
4809 +               memcpy(key_entry.key, crypto->key,
4810 +                      sizeof(key_entry.key));
4811 +               memcpy(key_entry.tx_mic, crypto->tx_mic,
4812 +                      sizeof(key_entry.tx_mic));
4813 +               memcpy(key_entry.rx_mic, crypto->rx_mic,
4814 +                      sizeof(key_entry.rx_mic));
4815 +
4816 +               offset = SHARED_KEY_ENTRY(key->hw_key_idx);
4817 +               timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
4818 +               rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
4819 +                                                   USB_VENDOR_REQUEST_OUT,
4820 +                                                   offset, &key_entry,
4821 +                                                   sizeof(key_entry),
4822 +                                                   timeout);
4823 +
4824 +               /*
4825 +                * The driver does not support the IV/EIV generation
4826 +                * in hardware. However it doesn't support the IV/EIV
4827 +                * inside the ieee80211 frame either, but requires it
4828 +                * to be provided seperately for the descriptor.
4829 +                * rt2x00lib will cut the IV/EIV data out of all frames
4830 +                * given to us by mac80211, but we must tell mac80211
4831 +                * to generate the IV/EIV data.
4832 +                */
4833 +               key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
4834 +       }
4835 +
4836 +       /*
4837 +        * The cipher types are stored over multiple registers
4838 +        * starting with SHARED_KEY_MODE_BASE each word will have
4839 +        * 32 bits and contains the cipher types for 2 modes each.
4840 +        * Using the correct defines correctly will cause overhead,
4841 +        * so just calculate the correct offset.
4842 +        */
4843 +       mask = key->hw_key_idx % 8;
4844 +       field.bit_offset = (3 * mask);
4845 +       field.bit_mask = 0x7 << field.bit_offset;
4846 +
4847 +       offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
4848 +       rt2x00usb_register_read(rt2x00dev, offset, &reg);
4849 +       rt2x00_set_field32(&reg, field,
4850 +                          (crypto->cmd == SET_KEY) ? crypto->cipher : 0);
4851 +       rt2x00usb_register_write(rt2x00dev, offset, reg);
4852 +
4853 +       /*
4854 +        * Update WCID information
4855 +        */
4856 +       rt2800usb_config_wcid_attr(rt2x00dev, crypto, key);
4857 +
4858 +       return 0;
4859 +}
4860 +
4861 +static int rt2800usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
4862 +                                        struct rt2x00lib_crypto *crypto,
4863 +                                        struct ieee80211_key_conf *key)
4864 +{
4865 +       struct hw_key_entry key_entry;
4866 +       int timeout;
4867 +       u32 offset;
4868 +
4869 +       /*
4870 +        * 1 pairwise key is possible per AID, this means that the AID
4871 +        * equals our hw_key_idx.
4872 +        */
4873 +       key->hw_key_idx = crypto->aid;
4874 +
4875 +       if (crypto->cmd == SET_KEY) {
4876 +               memcpy(key_entry.key, crypto->key,
4877 +                      sizeof(key_entry.key));
4878 +               memcpy(key_entry.tx_mic, crypto->tx_mic,
4879 +                      sizeof(key_entry.tx_mic));
4880 +               memcpy(key_entry.rx_mic, crypto->rx_mic,
4881 +                      sizeof(key_entry.rx_mic));
4882 +
4883 +               offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
4884 +               timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
4885 +               rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
4886 +                                                   USB_VENDOR_REQUEST_OUT,
4887 +                                                   offset, &key_entry,
4888 +                                                   sizeof(key_entry),
4889 +                                                   timeout);
4890 +
4891 +               /*
4892 +                * The driver does not support the IV/EIV generation
4893 +                * in hardware. However it doesn't support the IV/EIV
4894 +                * inside the ieee80211 frame either, but requires it
4895 +                * to be provided seperately for the descriptor.
4896 +                * rt2x00lib will cut the IV/EIV data out of all frames
4897 +                * given to us by mac80211, but we must tell mac80211
4898 +                * to generate the IV/EIV data.
4899 +                */
4900 +               key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
4901 +       }
4902 +
4903 +       /*
4904 +        * Update WCID information
4905 +        */
4906 +       rt2800usb_config_wcid_attr(rt2x00dev, crypto, key);
4907 +
4908 +       return 0;
4909 +}
4910 +
4911 +static void rt2800usb_config_filter(struct rt2x00_dev *rt2x00dev,
4912 +                                   const unsigned int filter_flags)
4913 +{
4914 +       u32 reg;
4915 +
4916 +       /*
4917 +        * Start configuration steps.
4918 +        * Note that the version error will always be dropped
4919 +        * and broadcast frames will always be accepted since
4920 +        * there is no filter for it at this time.
4921 +        */
4922 +       rt2x00usb_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
4923 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
4924 +                          !(filter_flags & FIF_FCSFAIL));
4925 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
4926 +                          !(filter_flags & FIF_PLCPFAIL));
4927 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
4928 +                          !(filter_flags & FIF_PROMISC_IN_BSS));
4929 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD,
4930 +                          !(filter_flags & FIF_OTHER_BSS));
4931 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
4932 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
4933 +                          !(filter_flags & FIF_ALLMULTI));
4934 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
4935 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
4936 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
4937 +                          !(filter_flags & FIF_CONTROL));
4938 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
4939 +                          !(filter_flags & FIF_CONTROL));
4940 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
4941 +                          !(filter_flags & FIF_CONTROL));
4942 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
4943 +                          !(filter_flags & FIF_CONTROL));
4944 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
4945 +                          !(filter_flags & FIF_CONTROL));
4946 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
4947 +                          !(filter_flags & FIF_CONTROL));
4948 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
4949 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 1);
4950 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
4951 +                          !(filter_flags & FIF_CONTROL));
4952 +       rt2x00usb_register_write(rt2x00dev, RX_FILTER_CFG, reg);
4953 +}
4954 +
4955 +static void rt2800usb_config_intf(struct rt2x00_dev *rt2x00dev,
4956 +                                 struct rt2x00_intf *intf,
4957 +                                 struct rt2x00intf_conf *conf,
4958 +                                 const unsigned int flags)
4959 +{
4960 +       unsigned int beacon_base;
4961 +       u32 reg;
4962 +
4963 +       if (flags & CONFIG_UPDATE_TYPE) {
4964 +               /*
4965 +                * Clear current synchronisation setup.
4966 +                * For the Beacon base registers we only need to clear
4967 +                * the first byte since that byte contains the VALID and OWNER
4968 +                * bits which (when set to 0) will invalidate the entire beacon.
4969 +                */
4970 +               beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
4971 +               rt2x00usb_register_write(rt2x00dev, beacon_base, 0);
4972 +
4973 +               /*
4974 +                * Enable synchronisation.
4975 +                */
4976 +               rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
4977 +               rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
4978 +               rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
4979 +               rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
4980 +               rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
4981 +       }
4982 +
4983 +       if (flags & CONFIG_UPDATE_MAC) {
4984 +               reg = le32_to_cpu(conf->mac[1]);
4985 +               rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
4986 +               conf->mac[1] = cpu_to_le32(reg);
4987 +
4988 +               rt2x00usb_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
4989 +                                             conf->mac, sizeof(conf->mac));
4990 +       }
4991 +
4992 +       if (flags & CONFIG_UPDATE_BSSID) {
4993 +               reg = le32_to_cpu(conf->bssid[1]);
4994 +               rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
4995 +               rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
4996 +               conf->bssid[1] = cpu_to_le32(reg);
4997 +
4998 +               rt2x00usb_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
4999 +                                             conf->bssid, sizeof(conf->bssid));
5000 +       }
5001 +}
5002 +
5003 +static void rt2800usb_config_erp(struct rt2x00_dev *rt2x00dev,
5004 +                                struct rt2x00lib_erp *erp)
5005 +{
5006 +       u32 reg;
5007 +
5008 +       rt2x00usb_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
5009 +       rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT,
5010 +                          erp->ack_timeout);
5011 +       rt2x00usb_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
5012 +
5013 +       rt2x00usb_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
5014 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
5015 +                          !!erp->short_preamble);
5016 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
5017 +                          !!erp->short_preamble);
5018 +       rt2x00usb_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
5019 +
5020 +       rt2x00usb_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
5021 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
5022 +                          erp->cts_protection ? 2 : 0);
5023 +       rt2x00usb_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
5024 +
5025 +       rt2x00usb_register_write(rt2x00dev, LEGACY_BASIC_RATE,
5026 +                                erp->basic_rates);
5027 +       rt2x00usb_register_write(rt2x00dev, HT_BASIC_RATE,
5028 +                                erp->basic_rates >> 32);
5029 +
5030 +       rt2x00usb_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
5031 +       rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
5032 +       rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
5033 +       rt2x00usb_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
5034 +
5035 +       rt2x00usb_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
5036 +       rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
5037 +       rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
5038 +       rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
5039 +       rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
5040 +       rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
5041 +       rt2x00usb_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
5042 +}
5043 +
5044 +static void rt2800usb_config_ant(struct rt2x00_dev *rt2x00dev,
5045 +                                struct antenna_setup *ant)
5046 +{
5047 +       u16 eeprom;
5048 +       u8 r1;
5049 +       u8 r3;
5050 +
5051 +       /*
5052 +        * FIXME: Use requested antenna configuration.
5053 +        */
5054 +
5055 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
5056 +
5057 +       rt2800usb_bbp_read(rt2x00dev, 1, &r1);
5058 +       rt2800usb_bbp_read(rt2x00dev, 3, &r3);
5059 +
5060 +       /*
5061 +        * Configure the TX antenna.
5062 +        */
5063 +       switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH)) {
5064 +       case 1:
5065 +               rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
5066 +               break;
5067 +       case 2:
5068 +       case 3:
5069 +               /* Do nothing */
5070 +               break;
5071 +       }
5072 +
5073 +       /*
5074 +        * Configure the RX antenna.
5075 +        */
5076 +       switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
5077 +       case 1:
5078 +               rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
5079 +               break;
5080 +       case 2:
5081 +               rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
5082 +               break;
5083 +       case 3:
5084 +               rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
5085 +               break;
5086 +       }
5087 +
5088 +       rt2800usb_bbp_write(rt2x00dev, 3, r3);
5089 +       rt2800usb_bbp_write(rt2x00dev, 1, r1);
5090 +}
5091 +
5092 +static void rt2800usb_config_lna_gain(struct rt2x00_dev *rt2x00dev,
5093 +                                     struct rt2x00lib_conf *libconf)
5094 +{
5095 +       u16 eeprom;
5096 +       short lna_gain;
5097 +
5098 +       if (libconf->rf.channel <= 14) {
5099 +               rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
5100 +               lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
5101 +       } else if (libconf->rf.channel <= 64) {
5102 +               rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
5103 +               lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
5104 +       } else if (libconf->rf.channel <= 128) {
5105 +               rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
5106 +               lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
5107 +       } else {
5108 +               rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
5109 +               lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
5110 +       }
5111 +
5112 +       rt2x00dev->lna_gain = lna_gain;
5113 +}
5114 +
5115 +static void rt2800usb_config_channel(struct rt2x00_dev *rt2x00dev,
5116 +                                    struct rf_channel *rf,
5117 +                                    struct channel_info *info)
5118 +{
5119 +       u32 reg;
5120 +       unsigned int tx_pin;
5121 +       u16 eeprom;
5122 +
5123 +       tx_pin = 0;
5124 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
5125 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
5126 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
5127 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
5128 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
5129 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
5130 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
5131 +
5132 +       rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
5133 +
5134 +       /*
5135 +        * Determine antenna settings from EEPROM
5136 +        */
5137 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
5138 +       if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1) {
5139 +               rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
5140 +               /* Turn off unused PA or LNA when only 1T or 1R */
5141 +               rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 0);
5142 +               rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 0);
5143 +       }
5144 +
5145 +       if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1) {
5146 +               rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
5147 +               rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
5148 +               /* Turn off unused PA or LNA when only 1T or 1R */
5149 +               rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 0);
5150 +               rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 0);
5151 +       } else if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 2)
5152 +               rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
5153 +
5154 +       if (rf->channel > 14) {
5155 +               /*
5156 +                * When TX power is below 0, we should increase it by 7 to
5157 +                * make it a positive value (Minumum value is -7).
5158 +                * However this means that values between 0 and 7 have
5159 +                * double meaning, and we should set a 7DBm boost flag.
5160 +                */
5161 +               rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
5162 +                                  (info->tx_power1 >= 0));
5163 +
5164 +               if (info->tx_power1 < 0)
5165 +                       info->tx_power1 += 7;
5166 +
5167 +               rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
5168 +                                  TXPOWER_A_TO_DEV(info->tx_power1));
5169 +
5170 +               rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
5171 +                                  (info->tx_power2 >= 0));
5172 +
5173 +               if (info->tx_power2 < 0)
5174 +                       info->tx_power2 += 7;
5175 +
5176 +               rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
5177 +                                  TXPOWER_A_TO_DEV(info->tx_power2));
5178 +
5179 +               rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
5180 +       } else {
5181 +               rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
5182 +                                  TXPOWER_G_TO_DEV(info->tx_power1));
5183 +               rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
5184 +                                  TXPOWER_G_TO_DEV(info->tx_power2));
5185 +
5186 +               rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
5187 +       }
5188 +
5189 +
5190 +       /* FIXME: How to determine bandwidth
5191 +       rt2x00_set_field32(&rf->rf4, RF4_BW40, !!(BBPCurrentBW == BW_40));
5192 +       */
5193 +
5194 +       rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
5195 +       rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
5196 +       rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
5197 +       rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
5198 +
5199 +       udelay(200);
5200 +
5201 +       rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
5202 +       rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
5203 +       rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
5204 +       rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
5205 +
5206 +       udelay(200);
5207 +
5208 +       rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
5209 +       rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
5210 +       rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
5211 +       rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
5212 +
5213 +       /*
5214 +        * Change BBP settings
5215 +        */
5216 +       rt2800usb_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
5217 +       rt2800usb_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
5218 +       rt2800usb_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
5219 +       rt2800usb_bbp_write(rt2x00dev, 86, 0);
5220 +
5221 +       if (rf->channel <= 14) {
5222 +               if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
5223 +                       rt2800usb_bbp_write(rt2x00dev, 82, 0x62);
5224 +                       rt2800usb_bbp_write(rt2x00dev, 75, 0x46);
5225 +               } else {
5226 +                       rt2800usb_bbp_write(rt2x00dev, 82, 0x84);
5227 +                       rt2800usb_bbp_write(rt2x00dev, 75, 0x50);
5228 +               }
5229 +
5230 +               rt2x00usb_register_read(rt2x00dev, TX_BAND_CFG, &reg);
5231 +               rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_A, 0);
5232 +               rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_BG, 1);
5233 +               rt2x00usb_register_write(rt2x00dev, TX_BAND_CFG, reg);
5234 +       } else {
5235 +               rt2800usb_bbp_write(rt2x00dev, 82, 0xf2);
5236 +
5237 +               if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
5238 +                       rt2800usb_bbp_write(rt2x00dev, 75, 0x46);
5239 +               else
5240 +                       rt2800usb_bbp_write(rt2x00dev, 75, 0x50);
5241 +
5242 +               rt2x00usb_register_read(rt2x00dev, TX_BAND_CFG, &reg);
5243 +               rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_A, 1);
5244 +               rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_BG, 0);
5245 +               rt2x00usb_register_write(rt2x00dev, TX_BAND_CFG, reg);
5246 +       }
5247 +
5248 +       rt2x00usb_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
5249 +
5250 +       msleep(1);
5251 +}
5252 +
5253 +static void rt2800usb_config_txpower(struct rt2x00_dev *rt2x00dev,
5254 +                                    const int txpower)
5255 +{
5256 +       u32 reg;
5257 +       u32 value = TXPOWER_G_TO_DEV(txpower);
5258 +       u8 r1;
5259 +
5260 +       rt2800usb_bbp_read(rt2x00dev, 1, &r1);
5261 +       rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
5262 +       rt2800usb_bbp_write(rt2x00dev, 1, r1);
5263 +
5264 +       rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
5265 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
5266 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
5267 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
5268 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
5269 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
5270 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
5271 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
5272 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
5273 +       rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
5274 +
5275 +       rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
5276 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
5277 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
5278 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
5279 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
5280 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
5281 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
5282 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
5283 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
5284 +       rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
5285 +
5286 +       rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
5287 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
5288 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
5289 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
5290 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
5291 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
5292 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
5293 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
5294 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
5295 +       rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
5296 +
5297 +       rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
5298 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
5299 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
5300 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
5301 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
5302 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
5303 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
5304 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
5305 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
5306 +       rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
5307 +
5308 +       rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
5309 +       rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
5310 +       rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
5311 +       rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
5312 +       rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
5313 +       rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
5314 +}
5315 +
5316 +static void rt2800usb_config_retry_limit(struct rt2x00_dev *rt2x00dev,
5317 +                                        struct rt2x00lib_conf *libconf)
5318 +{
5319 +       u32 reg;
5320 +
5321 +       rt2x00usb_register_read(rt2x00dev, TX_RTY_CFG, &reg);
5322 +       rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
5323 +                          libconf->conf->short_frame_max_tx_count);
5324 +       rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
5325 +                          libconf->conf->long_frame_max_tx_count);
5326 +       rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
5327 +       rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
5328 +       rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
5329 +       rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
5330 +       rt2x00usb_register_write(rt2x00dev, TX_RTY_CFG, reg);
5331 +}
5332 +
5333 +static void rt2800usb_config_duration(struct rt2x00_dev *rt2x00dev,
5334 +                                     struct rt2x00lib_conf *libconf)
5335 +{
5336 +       u32 reg;
5337 +
5338 +       rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
5339 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
5340 +                          libconf->conf->beacon_int * 16);
5341 +       rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
5342 +}
5343 +
5344 +static void rt2800usb_config(struct rt2x00_dev *rt2x00dev,
5345 +                            struct rt2x00lib_conf *libconf,
5346 +                            const unsigned int flags)
5347 +{
5348 +       /* Always recalculate LNA gain before changing configuration */
5349 +       rt2800usb_config_lna_gain(rt2x00dev, libconf);
5350 +
5351 +       if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
5352 +               rt2800usb_config_channel(rt2x00dev, &libconf->rf,
5353 +                                        &libconf->channel);
5354 +       if (flags & IEEE80211_CONF_CHANGE_POWER)
5355 +               rt2800usb_config_txpower(rt2x00dev, libconf->conf->power_level);
5356 +       if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
5357 +               rt2800usb_config_retry_limit(rt2x00dev, libconf);
5358 +       if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
5359 +               rt2800usb_config_duration(rt2x00dev, libconf);
5360 +}
5361 +
5362 +/*
5363 + * Link tuning
5364 + */
5365 +static void rt2800usb_link_stats(struct rt2x00_dev *rt2x00dev,
5366 +                                struct link_qual *qual)
5367 +{
5368 +       u32 reg;
5369 +
5370 +       /*
5371 +        * Update FCS error count from register.
5372 +        */
5373 +       rt2x00usb_register_read(rt2x00dev, RX_STA_CNT0, &reg);
5374 +       qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
5375 +
5376 +       /*
5377 +        * Update False CCA count from register.
5378 +        */
5379 +       rt2x00usb_register_read(rt2x00dev, RX_STA_CNT1, &reg);
5380 +       qual->false_cca = rt2x00_get_field32(reg, RX_STA_CNT1_FALSE_CCA);
5381 +}
5382 +
5383 +static void rt2800usb_reset_tuner(struct rt2x00_dev *rt2x00dev)
5384 +{
5385 +       u8 r66;
5386 +
5387 +       if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ)
5388 +               r66 = 0x2e + rt2x00dev->lna_gain;
5389 +       else {
5390 +               if (1 /* FIXME:  pAd->CommonCfg.BBPCurrentBW == BW_20 */)
5391 +                       r66 = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
5392 +               else
5393 +                       r66 = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
5394 +       }
5395 +
5396 +       rt2800usb_bbp_write(rt2x00dev, 66, r66);
5397 +}
5398 +
5399 +static void rt2800usb_link_tuner(struct rt2x00_dev *rt2x00dev)
5400 +{
5401 +       int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
5402 +       u8 r66_orig;
5403 +       u8 r66;
5404 +
5405 +       if (rt2x00_rev(&rt2x00dev->chip) == RT2870_VERSION_C)
5406 +               return;
5407 +
5408 +       rt2800usb_bbp_read(rt2x00dev, 66, &r66_orig);
5409 +       r66 = r66_orig;
5410 +
5411 +       if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
5412 +               r66 = 0x2e + rt2x00dev->lna_gain;
5413 +       } else {
5414 +               if (1 /* FIXME: pAd->CommonCfg.BBPCurrentBW == BW_20 */)
5415 +                       r66 = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
5416 +               else
5417 +                       r66 = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
5418 +       }
5419 +
5420 +       if (rssi > -80)
5421 +               r66 += 0x10;
5422 +
5423 +       if (rssi != r66_orig)
5424 +               rt2800usb_bbp_write(rt2x00dev, 66, r66);
5425 +}
5426 +
5427 +/*
5428 + * Firmware functions
5429 + */
5430 +static char *rt2800usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
5431 +{
5432 +       return FIRMWARE_RT2870;
5433 +}
5434 +
5435 +static u16 rt2800usb_get_firmware_crc(const void *data, const size_t len)
5436 +{
5437 +       u16 crc;
5438 +
5439 +       /*
5440 +        * Use the crc ccitt algorithm.
5441 +        * This will return the same value as the legacy driver which
5442 +        * used bit ordering reversion on the both the firmware bytes
5443 +        * before input input as well as on the final output.
5444 +        * Obviously using crc ccitt directly is much more efficient.
5445 +        * The last 2 bytes in the firmware array are the crc checksum itself,
5446 +        * this means that we should never pass those 2 bytes to the crc
5447 +        * algorithm.
5448 +        */
5449 +       crc = crc_ccitt(~0, data, len - 2);
5450 +
5451 +       /*
5452 +        * There is a small difference between the crc-itu-t + bitrev and
5453 +        * the crc-ccitt crc calculation. In the latter method the 2 bytes
5454 +        * will be swapped, use swab16 to convert the crc to the correct
5455 +        * value.
5456 +        */
5457 +       return swab16(crc);
5458 +}
5459 +
5460 +static int rt2800usb_load_firmware(struct rt2x00_dev *rt2x00dev,
5461 +                                  const void *data, const size_t len)
5462 +{
5463 +       unsigned int i;
5464 +       int status;
5465 +       u32 reg;
5466 +
5467 +       /*
5468 +        * Wait for stable hardware.
5469 +        */
5470 +       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
5471 +               rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
5472 +               if (reg && reg != ~0)
5473 +                       break;
5474 +               msleep(1);
5475 +       }
5476 +
5477 +       if (i == REGISTER_BUSY_COUNT) {
5478 +               ERROR(rt2x00dev, "Unstable hardware.\n");
5479 +               return -EBUSY;
5480 +       }
5481 +
5482 +       /*
5483 +        * Write firmware to device.
5484 +        */
5485 +       rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
5486 +                                           USB_VENDOR_REQUEST_OUT,
5487 +                                           FIRMWARE_IMAGE_BASE,
5488 +                                           data, len,
5489 +                                           REGISTER_TIMEOUT32(len));
5490 +
5491 +       rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
5492 +       rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
5493 +
5494 +       /*
5495 +        * Send firmware request to device to load firmware,
5496 +        * we need to specify a long timeout time.
5497 +        */
5498 +       status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
5499 +                                            0, USB_MODE_FIRMWARE,
5500 +                                            REGISTER_TIMEOUT_FIRMWARE);
5501 +       if (status < 0) {
5502 +               ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
5503 +               return status;
5504 +       }
5505 +
5506 +       /*
5507 +        * Wait for device to stabilize.
5508 +        */
5509 +       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
5510 +               rt2x00usb_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
5511 +               if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
5512 +                       break;
5513 +               msleep(1);
5514 +       }
5515 +
5516 +       if (i == REGISTER_BUSY_COUNT) {
5517 +               ERROR(rt2x00dev, "PBF system register not ready.\n");
5518 +               return -EBUSY;
5519 +       }
5520 +
5521 +       /*
5522 +        * Initialize firmware.
5523 +        */
5524 +       rt2x00usb_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
5525 +       rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
5526 +       msleep(1);
5527 +
5528 +       return 0;
5529 +}
5530 +
5531 +/*
5532 + * Initialization functions.
5533 + */
5534 +static int rt2800usb_init_registers(struct rt2x00_dev *rt2x00dev)
5535 +{
5536 +       u32 reg;
5537 +       unsigned int i;
5538 +
5539 +       /*
5540 +        * Wait untill BBP and RF are ready.
5541 +        */
5542 +       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
5543 +               rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
5544 +               if (reg && reg != ~0)
5545 +                       break;
5546 +               msleep(1);
5547 +       }
5548 +
5549 +       if (i == REGISTER_BUSY_COUNT) {
5550 +               ERROR(rt2x00dev, "Unstable hardware.\n");
5551 +               return -EBUSY;
5552 +       }
5553 +
5554 +       rt2x00usb_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
5555 +       rt2x00usb_register_write(rt2x00dev, PBF_SYS_CTRL, reg & ~0x00002000);
5556 +
5557 +       rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
5558 +       rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
5559 +       rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
5560 +       rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
5561 +
5562 +       rt2x00usb_register_write(rt2x00dev, USB_DMA_CFG, 0x00000000);
5563 +
5564 +       rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
5565 +                                   USB_MODE_RESET, REGISTER_TIMEOUT);
5566 +
5567 +       rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
5568 +
5569 +       rt2x00usb_register_read(rt2x00dev, BCN_OFFSET0, &reg);
5570 +       rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
5571 +       rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
5572 +       rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
5573 +       rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
5574 +       rt2x00usb_register_write(rt2x00dev, BCN_OFFSET0, reg);
5575 +
5576 +       rt2x00usb_register_read(rt2x00dev, BCN_OFFSET1, &reg);
5577 +       rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
5578 +       rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
5579 +       rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
5580 +       rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
5581 +       rt2x00usb_register_write(rt2x00dev, BCN_OFFSET1, reg);
5582 +
5583 +       rt2x00usb_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
5584 +       rt2x00usb_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
5585 +
5586 +       rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
5587 +
5588 +       rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
5589 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
5590 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
5591 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
5592 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
5593 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
5594 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
5595 +       rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
5596 +
5597 +       rt2x00usb_register_write(rt2x00dev, TX_SW_CFG0, 0x00040a06);
5598 +       rt2x00usb_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5599 +
5600 +       rt2x00usb_register_read(rt2x00dev, TX_LINK_CFG, &reg);
5601 +       rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
5602 +       rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
5603 +       rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
5604 +       rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
5605 +       rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
5606 +       rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
5607 +       rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
5608 +       rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
5609 +       rt2x00usb_register_write(rt2x00dev, TX_LINK_CFG, reg);
5610 +
5611 +       rt2x00usb_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
5612 +       rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
5613 +       rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
5614 +       rt2x00usb_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
5615 +
5616 +       rt2x00usb_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
5617 +       rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
5618 +       rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
5619 +       rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
5620 +       rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
5621 +       rt2x00usb_register_write(rt2x00dev, MAX_LEN_CFG, reg);
5622 +
5623 +       rt2x00usb_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
5624 +
5625 +       rt2x00usb_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
5626 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
5627 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
5628 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
5629 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
5630 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
5631 +       rt2x00usb_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
5632 +
5633 +       rt2x00usb_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
5634 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
5635 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
5636 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
5637 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
5638 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5639 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5640 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
5641 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5642 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
5643 +       rt2x00usb_register_write(rt2x00dev, CCK_PROT_CFG, reg);
5644 +
5645 +       rt2x00usb_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
5646 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
5647 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
5648 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
5649 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
5650 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5651 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5652 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
5653 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5654 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
5655 +       rt2x00usb_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
5656 +
5657 +       rt2x00usb_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
5658 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
5659 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
5660 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
5661 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
5662 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5663 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5664 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
5665 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5666 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
5667 +       rt2x00usb_register_write(rt2x00dev, MM20_PROT_CFG, reg);
5668 +
5669 +       rt2x00usb_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
5670 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
5671 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
5672 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
5673 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
5674 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5675 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5676 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
5677 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5678 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
5679 +       rt2x00usb_register_write(rt2x00dev, MM40_PROT_CFG, reg);
5680 +
5681 +       rt2x00usb_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
5682 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
5683 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
5684 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
5685 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
5686 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5687 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5688 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
5689 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5690 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
5691 +       rt2x00usb_register_write(rt2x00dev, GF20_PROT_CFG, reg);
5692 +
5693 +       rt2x00usb_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
5694 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
5695 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
5696 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
5697 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
5698 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5699 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5700 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
5701 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5702 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
5703 +       rt2x00usb_register_write(rt2x00dev, GF40_PROT_CFG, reg);
5704 +
5705 +       rt2x00usb_register_write(rt2x00dev, PBF_CFG, 0xf40006);
5706 +
5707 +       rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
5708 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
5709 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
5710 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
5711 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
5712 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
5713 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
5714 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
5715 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
5716 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
5717 +       rt2x00usb_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
5718 +
5719 +       rt2x00usb_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
5720 +       rt2x00usb_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
5721 +
5722 +       rt2x00usb_register_read(rt2x00dev, TX_RTS_CFG, &reg);
5723 +       rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
5724 +       rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
5725 +       rt2x00usb_register_write(rt2x00dev, TX_RTS_CFG, reg);
5726 +
5727 +       rt2x00usb_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
5728 +       rt2x00usb_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
5729 +
5730 +       /*
5731 +        * ASIC will keep garbage value after boot, clear encryption keys.
5732 +        */
5733 +       for (i = 0; i < 254; i++) {
5734 +               u32 wcid[2] = { 0xffffffff, 0x0000ffff };
5735 +               rt2x00usb_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
5736 +                                             wcid, sizeof(wcid));
5737 +       }
5738 +
5739 +       for (i = 0; i < 4; i++)
5740 +               rt2x00usb_register_write(rt2x00dev,
5741 +                                        SHARED_KEY_MODE_ENTRY(i), 0);
5742 +
5743 +       for (i = 0; i < 256; i++)
5744 +               rt2x00usb_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
5745 +
5746 +       /*
5747 +        * Clear all beacons
5748 +        * For the Beacon base registers we only need to clear
5749 +        * the first byte since that byte contains the VALID and OWNER
5750 +        * bits which (when set to 0) will invalidate the entire beacon.
5751 +        */
5752 +       rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
5753 +       rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
5754 +       rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
5755 +       rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
5756 +       rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
5757 +       rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
5758 +       rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
5759 +       rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
5760 +
5761 +       rt2x00usb_register_read(rt2x00dev, USB_CYC_CFG, &reg);
5762 +       rt2x00_set_field32(&reg, USB_CYC_CFG_CLOCK_CYCLE, 30);
5763 +       rt2x00usb_register_write(rt2x00dev, USB_CYC_CFG, reg);
5764 +
5765 +       rt2x00usb_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
5766 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
5767 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
5768 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
5769 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
5770 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
5771 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
5772 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
5773 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
5774 +       rt2x00usb_register_write(rt2x00dev, HT_FBK_CFG0, reg);
5775 +
5776 +       rt2x00usb_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
5777 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
5778 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
5779 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
5780 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
5781 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
5782 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
5783 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
5784 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
5785 +       rt2x00usb_register_write(rt2x00dev, HT_FBK_CFG1, reg);
5786 +
5787 +       rt2x00usb_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
5788 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
5789 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
5790 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 10);
5791 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 11);
5792 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 12);
5793 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 13);
5794 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 14);
5795 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 15);
5796 +       rt2x00usb_register_write(rt2x00dev, LG_FBK_CFG0, reg);
5797 +
5798 +       rt2x00usb_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
5799 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
5800 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
5801 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
5802 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
5803 +       rt2x00usb_register_write(rt2x00dev, LG_FBK_CFG1, reg);
5804 +
5805 +       /*
5806 +        * We must clear the error counters.
5807 +        * These registers are cleared on read,
5808 +        * so we may pass a useless variable to store the value.
5809 +        */
5810 +       rt2x00usb_register_read(rt2x00dev, RX_STA_CNT0, &reg);
5811 +       rt2x00usb_register_read(rt2x00dev, RX_STA_CNT1, &reg);
5812 +       rt2x00usb_register_read(rt2x00dev, RX_STA_CNT2, &reg);
5813 +       rt2x00usb_register_read(rt2x00dev, TX_STA_CNT0, &reg);
5814 +       rt2x00usb_register_read(rt2x00dev, TX_STA_CNT1, &reg);
5815 +       rt2x00usb_register_read(rt2x00dev, TX_STA_CNT2, &reg);
5816 +
5817 +       return 0;
5818 +}
5819 +
5820 +static int rt2800usb_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
5821 +{
5822 +       unsigned int i;
5823 +       u32 reg;
5824 +
5825 +       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
5826 +               rt2x00usb_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
5827 +               if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
5828 +                       return 0;
5829 +
5830 +               udelay(REGISTER_BUSY_DELAY);
5831 +       }
5832 +
5833 +       ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
5834 +       return -EACCES;
5835 +}
5836 +
5837 +static int rt2800usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
5838 +{
5839 +       unsigned int i;
5840 +       u8 value;
5841 +
5842 +       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
5843 +               rt2800usb_bbp_read(rt2x00dev, 0, &value);
5844 +               if ((value != 0xff) && (value != 0x00))
5845 +                       return 0;
5846 +               udelay(REGISTER_BUSY_DELAY);
5847 +       }
5848 +
5849 +       ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
5850 +       return -EACCES;
5851 +}
5852 +
5853 +static int rt2800usb_init_bbp(struct rt2x00_dev *rt2x00dev)
5854 +{
5855 +       unsigned int i;
5856 +       u16 eeprom;
5857 +       u8 reg_id;
5858 +       u8 value;
5859 +
5860 +       if (unlikely(rt2800usb_wait_bbp_rf_ready(rt2x00dev) ||
5861 +                    rt2800usb_wait_bbp_ready(rt2x00dev)))
5862 +               return -EACCES;
5863 +
5864 +       rt2800usb_bbp_write(rt2x00dev, 65, 0x2c);
5865 +       rt2800usb_bbp_write(rt2x00dev, 66, 0x38);
5866 +       rt2800usb_bbp_write(rt2x00dev, 69, 0x12);
5867 +       rt2800usb_bbp_write(rt2x00dev, 70, 0x0a);
5868 +       rt2800usb_bbp_write(rt2x00dev, 73, 0x10);
5869 +       rt2800usb_bbp_write(rt2x00dev, 81, 0x37);
5870 +       rt2800usb_bbp_write(rt2x00dev, 82, 0x62);
5871 +       rt2800usb_bbp_write(rt2x00dev, 83, 0x6a);
5872 +       rt2800usb_bbp_write(rt2x00dev, 84, 0x99);
5873 +       rt2800usb_bbp_write(rt2x00dev, 86, 0x00);
5874 +       rt2800usb_bbp_write(rt2x00dev, 91, 0x04);
5875 +       rt2800usb_bbp_write(rt2x00dev, 92, 0x00);
5876 +       rt2800usb_bbp_write(rt2x00dev, 105, 0x05);
5877 +
5878 +       if (rt2x00_rev(&rt2x00dev->chip) == RT2870_VERSION_C) {
5879 +               rt2800usb_bbp_write(rt2x00dev, 69, 0x16);
5880 +               rt2800usb_bbp_write(rt2x00dev, 73, 0x12);
5881 +       }
5882 +
5883 +       if (rt2x00_rev(&rt2x00dev->chip) != RT2870_VERSION_D)
5884 +               rt2800usb_bbp_write(rt2x00dev, 84, 0x19);
5885 +
5886 +       for (i = 0; i < EEPROM_BBP_SIZE; i++) {
5887 +               rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
5888 +
5889 +               if (eeprom != 0xffff && eeprom != 0x0000) {
5890 +                       reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
5891 +                       value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
5892 +                       rt2800usb_bbp_write(rt2x00dev, reg_id, value);
5893 +               }
5894 +       }
5895 +
5896 +       return 0;
5897 +}
5898 +
5899 +/*
5900 + * Device state switch handlers.
5901 + */
5902 +static void rt2800usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
5903 +                               enum dev_state state)
5904 +{
5905 +       u32 reg;
5906 +
5907 +       rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
5908 +       rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
5909 +                          (state == STATE_RADIO_RX_ON) ||
5910 +                          (state == STATE_RADIO_RX_ON_LINK));
5911 +       rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
5912 +}
5913 +
5914 +static int rt2800usb_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
5915 +{
5916 +       unsigned int i;
5917 +       u32 reg;
5918 +
5919 +       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
5920 +               rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
5921 +               if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
5922 +                   !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
5923 +                       return 0;
5924 +
5925 +               msleep(1);
5926 +       }
5927 +
5928 +       ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
5929 +       return -EACCES;
5930 +}
5931 +
5932 +static int rt2800usb_enable_radio(struct rt2x00_dev *rt2x00dev)
5933 +{
5934 +       u32 reg;
5935 +       u16 word;
5936 +
5937 +       /*
5938 +        * Initialize all registers.
5939 +        */
5940 +       if (unlikely(rt2800usb_wait_wpdma_ready(rt2x00dev) ||
5941 +                    rt2800usb_init_registers(rt2x00dev) ||
5942 +                    rt2800usb_init_bbp(rt2x00dev)))
5943 +               return -EIO;
5944 +
5945 +       rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
5946 +       rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
5947 +       rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
5948 +
5949 +       udelay(50);
5950 +
5951 +       rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
5952 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
5953 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
5954 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
5955 +       rt2x00usb_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
5956 +
5957 +
5958 +       rt2x00usb_register_read(rt2x00dev, USB_DMA_CFG, &reg);
5959 +       rt2x00_set_field32(&reg, USB_DMA_CFG_PHY_CLEAR, 0);
5960 +       /* Don't use bulk in aggregation when working with USB 1.1 */
5961 +       rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_EN,
5962 +                          (rt2x00dev->rx->usb_maxpacket == 512));
5963 +       rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_TIMEOUT, 128);
5964 +       /* FIXME: Calculate this value based on Aggregation defines */
5965 +       rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_LIMIT, 21);
5966 +       rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_EN, 1);
5967 +       rt2x00_set_field32(&reg, USB_DMA_CFG_TX_BULK_EN, 1);
5968 +       rt2x00usb_register_write(rt2x00dev, USB_DMA_CFG, reg);
5969 +
5970 +       rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
5971 +       rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
5972 +       rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
5973 +       rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
5974 +
5975 +       /*
5976 +        * Initialize LED control
5977 +        */
5978 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
5979 +       rt2800usb_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
5980 +                             word & 0xff, (word >> 8) & 0xff);
5981 +
5982 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
5983 +       rt2800usb_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
5984 +                             word & 0xff, (word >> 8) & 0xff);
5985 +
5986 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
5987 +       rt2800usb_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
5988 +                             word & 0xff, (word >> 8) & 0xff);
5989 +
5990 +       /*
5991 +        * Send signal to firmware during boot time.
5992 +        */
5993 +       rt2800usb_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0);
5994 +
5995 +       return 0;
5996 +}
5997 +
5998 +static void rt2800usb_disable_radio(struct rt2x00_dev *rt2x00dev)
5999 +{
6000 +       u32 reg;
6001 +
6002 +       rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
6003 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
6004 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
6005 +       rt2x00usb_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
6006 +
6007 +       rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
6008 +       rt2x00usb_register_write(rt2x00dev, PWR_PIN_CFG, 0);
6009 +       rt2x00usb_register_write(rt2x00dev, TX_PIN_CFG, 0);
6010 +
6011 +       /* Wait for DMA, ignore error */
6012 +       rt2800usb_wait_wpdma_ready(rt2x00dev);
6013 +
6014 +       rt2x00usb_disable_radio(rt2x00dev);
6015 +}
6016 +
6017 +static int rt2800usb_set_state(struct rt2x00_dev *rt2x00dev,
6018 +                              enum dev_state state)
6019 +{
6020 +       rt2x00usb_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
6021 +
6022 +       if (state == STATE_AWAKE)
6023 +               rt2800usb_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
6024 +       else
6025 +               rt2800usb_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
6026 +
6027 +       return 0;
6028 +}
6029 +
6030 +static int rt2800usb_set_device_state(struct rt2x00_dev *rt2x00dev,
6031 +                                     enum dev_state state)
6032 +{
6033 +       int retval = 0;
6034 +
6035 +       switch (state) {
6036 +       case STATE_RADIO_ON:
6037 +               /*
6038 +                * Before the radio can be enabled, the device first has
6039 +                * to be woken up. After that it needs a bit of time
6040 +                * to be fully awake and the radio can be enabled.
6041 +                */
6042 +               rt2800usb_set_state(rt2x00dev, STATE_AWAKE);
6043 +               msleep(1);
6044 +               retval = rt2800usb_enable_radio(rt2x00dev);
6045 +               break;
6046 +       case STATE_RADIO_OFF:
6047 +               /*
6048 +                * After the radio has been disablee, the device should
6049 +                * be put to sleep for powersaving.
6050 +                */
6051 +               rt2800usb_disable_radio(rt2x00dev);
6052 +               rt2800usb_set_state(rt2x00dev, STATE_SLEEP);
6053 +               break;
6054 +       case STATE_RADIO_RX_ON:
6055 +       case STATE_RADIO_RX_ON_LINK:
6056 +       case STATE_RADIO_RX_OFF:
6057 +       case STATE_RADIO_RX_OFF_LINK:
6058 +               rt2800usb_toggle_rx(rt2x00dev, state);
6059 +               break;
6060 +       case STATE_RADIO_IRQ_ON:
6061 +       case STATE_RADIO_IRQ_OFF:
6062 +               /* No support, but no error either */
6063 +               break;
6064 +       case STATE_DEEP_SLEEP:
6065 +       case STATE_SLEEP:
6066 +       case STATE_STANDBY:
6067 +       case STATE_AWAKE:
6068 +               retval = rt2800usb_set_state(rt2x00dev, state);
6069 +               break;
6070 +       default:
6071 +               retval = -ENOTSUPP;
6072 +               break;
6073 +       }
6074 +
6075 +       if (unlikely(retval))
6076 +               ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
6077 +                     state, retval);
6078 +
6079 +       return retval;
6080 +}
6081 +
6082 +/*
6083 + * TX descriptor initialization
6084 + */
6085 +static void rt2800usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
6086 +                                   struct sk_buff *skb,
6087 +                                   struct txentry_desc *txdesc)
6088 +{
6089 +       struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
6090 +       __le32 *txd = skbdesc->desc;
6091 +       __le32 *txwi = txd + TXD_DESC_SIZE;
6092 +       u32 word;
6093 +
6094 +       /*
6095 +        * Initialize TX Info descriptor
6096 +        */
6097 +       rt2x00_desc_read(txwi, 0, &word);
6098 +       rt2x00_set_field32(&word, TXWI_W0_FRAG,
6099 +                          test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags) ||
6100 +                          test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
6101 +       rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
6102 +       rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
6103 +       rt2x00_set_field32(&word, TXWI_W0_TS,
6104 +                          test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
6105 +       rt2x00_set_field32(&word, TXWI_W0_AMPDU,
6106 +                          test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
6107 +       rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
6108 +       rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->ifs);
6109 +       rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
6110 +       rt2x00_set_field32(&word, TXWI_W0_BW,
6111 +                          test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
6112 +       rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
6113 +                          test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
6114 +       rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
6115 +       rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
6116 +       rt2x00_desc_write(txwi, 0, word);
6117 +
6118 +       rt2x00_desc_read(txwi, 1, &word);
6119 +       rt2x00_set_field32(&word, TXWI_W1_ACK,
6120 +                          test_bit(ENTRY_TXD_ACK, &txdesc->flags));
6121 +       rt2x00_set_field32(&word, TXWI_W1_ACK,
6122 +                          test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags));
6123 +       rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
6124 +       rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID, 0xff);
6125 +       rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT, skb->len);
6126 +       rt2x00_set_field32(&word, TXWI_W1_PACKETID,
6127 +                          skbdesc->entry->entry_idx);
6128 +       rt2x00_desc_write(txwi, 1, word);
6129 +
6130 +       if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
6131 +               _rt2x00_desc_write(txwi, 2, skbdesc->iv);
6132 +               _rt2x00_desc_write(txwi, 3, skbdesc->eiv);
6133 +       }
6134 +
6135 +       /*
6136 +        * Initialize TX descriptor
6137 +        */
6138 +       rt2x00_desc_read(txd, 0, &word);
6139 +       rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
6140 +       rt2x00_desc_write(txd, 0, word);
6141 +
6142 +       rt2x00_desc_read(txd, 1, &word);
6143 +       rt2x00_set_field32(&word, TXD_W1_SD_LEN1, skb->len);
6144 +       rt2x00_set_field32(&word, TXD_W1_LAST_SEC1, 1);
6145 +       rt2x00_set_field32(&word, TXD_W1_BURST,
6146 +                          test_bit(ENTRY_TXD_BURST, &txdesc->flags));
6147 +       rt2x00_set_field32(&word, TXD_W1_SD_LEN0,
6148 +                          rt2x00dev->hw->extra_tx_headroom);
6149 +       rt2x00_set_field32(&word, TXD_W1_LAST_SEC0,
6150 +                          !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
6151 +       rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
6152 +       rt2x00_desc_write(txd, 1, word);
6153 +
6154 +       rt2x00_desc_read(txd, 2, &word);
6155 +       rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
6156 +                          skbdesc->skb_dma + rt2x00dev->hw->extra_tx_headroom);
6157 +       rt2x00_desc_write(txd, 2, word);
6158 +
6159 +       rt2x00_desc_read(txd, 3, &word);
6160 +       rt2x00_set_field32(&word, TXD_W3_WIV, 1);
6161 +       rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
6162 +       rt2x00_desc_write(txd, 3, word);
6163 +}
6164 +
6165 +/*
6166 + * TX data initialization
6167 + */
6168 +static void rt2800usb_write_beacon(struct queue_entry *entry)
6169 +{
6170 +       struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
6171 +       struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
6172 +       unsigned int beacon_base;
6173 +       u32 reg;
6174 +
6175 +       /*
6176 +        * Add the descriptor in front of the skb.
6177 +        */
6178 +       skb_push(entry->skb, entry->queue->desc_size);
6179 +       memcpy(entry->skb->data, skbdesc->desc, skbdesc->desc_len);
6180 +       skbdesc->desc = entry->skb->data;
6181 +
6182 +       /*
6183 +        * Disable beaconing while we are reloading the beacon data,
6184 +        * otherwise we might be sending out invalid data.
6185 +        */
6186 +       rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
6187 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
6188 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
6189 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
6190 +       rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
6191 +
6192 +       /*
6193 +        * Write entire beacon with descriptor to register.
6194 +        */
6195 +       beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
6196 +       rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
6197 +                                           USB_VENDOR_REQUEST_OUT, beacon_base,
6198 +                                           entry->skb->data, entry->skb->len,
6199 +                                           REGISTER_TIMEOUT32(entry->skb->len));
6200 +
6201 +       /*
6202 +        * Clean up the beacon skb.
6203 +        */
6204 +       dev_kfree_skb(entry->skb);
6205 +       entry->skb = NULL;
6206 +}
6207 +
6208 +static int rt2800usb_get_tx_data_len(struct queue_entry *entry)
6209 +{
6210 +       int length;
6211 +
6212 +       /*
6213 +        * The length _must_ be a multiple of 4,
6214 +        * but it must _not_ be a multiple of the USB packet size.
6215 +        */
6216 +       length = roundup(entry->skb->len, 4);
6217 +       length += (4 * !(length % entry->queue->usb_maxpacket));
6218 +
6219 +       return length;
6220 +}
6221 +
6222 +static void rt2800usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
6223 +                                   const enum data_queue_qid queue)
6224 +{
6225 +       u32 reg;
6226 +
6227 +       if (queue != QID_BEACON) {
6228 +               rt2x00usb_kick_tx_queue(rt2x00dev, queue);
6229 +               return;
6230 +       }
6231 +
6232 +       rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
6233 +       if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
6234 +               rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
6235 +               rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
6236 +               rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
6237 +               rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
6238 +       }
6239 +}
6240 +
6241 +/*
6242 + * RX control handlers
6243 + */
6244 +static void rt2800usb_fill_rxdone(struct queue_entry *entry,
6245 +                                 struct rxdone_entry_desc *rxdesc)
6246 +{
6247 +       struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
6248 +       struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
6249 +       __le32 *rxd = (__le32 *)entry->skb->data;
6250 +       __le32 *rxwi = (__le32 *)(entry->skb->data + skbdesc->desc_len);
6251 +       u32 rxd0;
6252 +       u32 rxwi0;
6253 +       u32 rxwi1;
6254 +       u32 rxwi2;
6255 +       u32 rxwi3;
6256 +       u8 mcs;
6257 +       u8 mode;
6258 +
6259 +       /*
6260 +        * Copy descriptor to the skbdesc->desc buffer, making it safe from
6261 +        * moving of frame data in rt2x00usb.
6262 +        */
6263 +       memcpy(skbdesc->desc, rxd, skbdesc->desc_len);
6264 +       rxd = (__le32 *)skbdesc->desc;
6265 +
6266 +       /*
6267 +        * It is now safe to read the descriptor on all architectures.
6268 +        */
6269 +       rt2x00_desc_read(rxd, 0, &rxd0);
6270 +       rt2x00_desc_read(rxwi, 0, &rxwi0);
6271 +       rt2x00_desc_read(rxwi, 1, &rxwi1);
6272 +       rt2x00_desc_read(rxwi, 2, &rxwi2);
6273 +       rt2x00_desc_read(rxwi, 3, &rxwi3);
6274 +
6275 +       if (rt2x00_get_field32(rxd0, RXD_W0_CRC_ERROR))
6276 +               rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
6277 +
6278 +       if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
6279 +               /*
6280 +                * FIXME: Set cipher on WEP64 when it has been decrypted,
6281 +                * at the moment we cannot determine the real cipher type yet.
6282 +                */
6283 +               rxdesc->cipher =
6284 +                   rt2x00_get_field32(rxd0, RXD_W0_DECRYPTED);
6285 +               rxdesc->cipher_status =
6286 +                   rt2x00_get_field32(rxd0, RXD_W0_CIPHER_ERROR);
6287 +       }
6288 +
6289 +       if (rxdesc->cipher != CIPHER_NONE) {
6290 +               /*
6291 +                * Hardware has stripped IV/EIV data from 802.11 frame during
6292 +                * decryption. It has provided the data seperately but rt2x00lib
6293 +                * should decide if it should be reinserted.
6294 +                */
6295 +               rxdesc->flags |= RX_FLAG_IV_STRIPPED;
6296 +
6297 +               if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
6298 +                       rxdesc->flags |= RX_FLAG_DECRYPTED;
6299 +               else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
6300 +                       rxdesc->flags |= RX_FLAG_MMIC_ERROR;
6301 +       }
6302 +
6303 +       if (rt2x00_get_field32(rxd0, RXD_W0_MY_BSS))
6304 +               rxdesc->dev_flags |= RXDONE_MY_BSS;
6305 +
6306 +       /*
6307 +        * Create the MCS value, when the mode is CCK, mask of 0x8 bit
6308 +        * to remove the short preamble flag.
6309 +        */
6310 +       mode = rt2x00_get_field32(rxwi1, RXWI_W1_PHYMODE);
6311 +       mcs = rt2x00_get_field32(rxwi1, RXWI_W1_MCS);
6312 +
6313 +       if (mode == RATE_MODE_CCK)
6314 +               mcs &= ~0x8;
6315 +
6316 +       rxdesc->signal = (mode << 8) | mcs;
6317 +
6318 +       rxdesc->rssi =
6319 +           (rt2x00_get_field32(rxwi2, RXWI_W2_RSSI0) +
6320 +            rt2x00_get_field32(rxwi2, RXWI_W2_RSSI1) +
6321 +            rt2x00_get_field32(rxwi2, RXWI_W2_RSSI2)) / 3;
6322 +
6323 +       rxdesc->noise =
6324 +           (rt2x00_get_field32(rxwi3, RXWI_W3_SNR0) +
6325 +            rt2x00_get_field32(rxwi3, RXWI_W3_SNR1)) / 2;
6326 +
6327 +       rxdesc->size = rt2x00_get_field32(rxwi0, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
6328 +
6329 +       /*
6330 +        * Remove TXWI descriptor from start of buffer.
6331 +        */
6332 +       skb_pull(entry->skb, TXWI_DESC_SIZE + skbdesc->desc_len);
6333 +       skb_trim(entry->skb, rxdesc->size);
6334 +}
6335 +
6336 +/*
6337 + * Device probe functions.
6338 + */
6339 +static int rt2800usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
6340 +{
6341 +       u16 word;
6342 +       u8 *mac;
6343 +       u8 default_lna_gain;
6344 +
6345 +       rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
6346 +
6347 +       /*
6348 +        * Start validation of the data that has been read.
6349 +        */
6350 +       mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
6351 +       if (!is_valid_ether_addr(mac)) {
6352 +               DECLARE_MAC_BUF(macbuf);
6353 +
6354 +               random_ether_addr(mac);
6355 +               EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
6356 +       }
6357 +
6358 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
6359 +       if (word == 0xffff) {
6360 +               rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
6361 +               rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
6362 +               rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
6363 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
6364 +               EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
6365 +       }
6366 +
6367 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
6368 +       if (word != 0) {
6369 +               /* NIC configuration must always be 0. */
6370 +               word = 0;
6371 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
6372 +               EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
6373 +       }
6374 +
6375 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
6376 +       if ((word & 0x00ff) == 0x00ff) {
6377 +               rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
6378 +               rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
6379 +                                  LED_MODE_TXRX_ACTIVITY);
6380 +               rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
6381 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
6382 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
6383 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
6384 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
6385 +               EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
6386 +       }
6387 +
6388 +       /*
6389 +        * During the LNA validation we are going to use
6390 +        * lna0 as correct value. Note that EEPROM_LNA
6391 +        * is never validated.
6392 +        */
6393 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
6394 +       default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
6395 +
6396 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
6397 +       if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
6398 +               rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
6399 +       if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
6400 +               rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
6401 +       rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
6402 +
6403 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
6404 +       if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
6405 +               rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
6406 +       if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
6407 +           rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
6408 +               rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
6409 +                                  default_lna_gain);
6410 +       rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
6411 +
6412 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
6413 +       if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
6414 +               rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
6415 +       if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
6416 +               rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
6417 +       rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
6418 +
6419 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
6420 +       if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
6421 +               rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
6422 +       if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
6423 +           rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
6424 +               rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
6425 +                                  default_lna_gain);
6426 +       rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
6427 +
6428 +       return 0;
6429 +}
6430 +
6431 +static int rt2800usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
6432 +{
6433 +       u32 reg;
6434 +       u16 rev;
6435 +       u16 value;
6436 +       u16 eeprom;
6437 +
6438 +       /*
6439 +        * Read EEPROM word for configuration.
6440 +        */
6441 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
6442 +
6443 +       /*
6444 +        * Identify RF chipset.
6445 +        */
6446 +       value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
6447 +       rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
6448 +       rev = rt2x00_get_field32(reg, MAC_CSR0_ASIC_REV);
6449 +       rt2x00_set_chip(rt2x00dev, RT2870, value, rev);
6450 +
6451 +       /*
6452 +        * The check for rt2860 is not a typo, some rt2870 hardware
6453 +        * identifies itself as rt2860 in the CSR register.
6454 +        */
6455 +       if ((rt2x00_get_field32(reg, MAC_CSR0_ASIC_VER) != 0x2860) &&
6456 +           (rt2x00_get_field32(reg, MAC_CSR0_ASIC_VER) != 0x2870)) {
6457 +               ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
6458 +               return -ENODEV;
6459 +       }
6460 +
6461 +       if (!rt2x00_rf(&rt2x00dev->chip, RF2820) &&
6462 +           !rt2x00_rf(&rt2x00dev->chip, RF2850) &&
6463 +           !rt2x00_rf(&rt2x00dev->chip, RF2720) &&
6464 +           !rt2x00_rf(&rt2x00dev->chip, RF2750)) {
6465 +               ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
6466 +               return -ENODEV;
6467 +       }
6468 +
6469 +       /*
6470 +        * Read frequency offset and RF programming sequence.
6471 +        */
6472 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
6473 +       rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
6474 +
6475 +       /*
6476 +        * Read external LNA informations.
6477 +        */
6478 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
6479 +
6480 +       if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
6481 +               __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
6482 +       if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
6483 +               __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
6484 +
6485 +       /*
6486 +        * Store led settings, for correct led behaviour.
6487 +        */
6488 +#ifdef CONFIG_RT2X00_LIB_LEDS
6489 +       rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
6490 +       rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
6491 +       rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
6492 +
6493 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ,
6494 +                          &rt2x00dev->led_mcu_reg);
6495 +#endif /* CONFIG_RT2X00_LIB_LEDS */
6496 +
6497 +       return 0;
6498 +}
6499 +
6500 +/*
6501 + * RF value list for rt2870
6502 + * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
6503 + */
6504 +static const struct rf_channel rf_vals[] = {
6505 +       { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
6506 +       { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
6507 +       { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
6508 +       { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
6509 +       { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
6510 +       { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
6511 +       { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
6512 +       { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
6513 +       { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
6514 +       { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
6515 +       { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
6516 +       { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
6517 +       { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
6518 +       { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
6519 +
6520 +       /* 802.11 UNI / HyperLan 2 */
6521 +       { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
6522 +       { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
6523 +       { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
6524 +       { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
6525 +       { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
6526 +       { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
6527 +       { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
6528 +       { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
6529 +       { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
6530 +       { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
6531 +       { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
6532 +       { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
6533 +
6534 +       /* 802.11 HyperLan 2 */
6535 +       { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
6536 +       { 102, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed793 },
6537 +       { 104, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed1a3 },
6538 +       { 108, 0x18402ecc, 0x184c0a32, 0x18178a55, 0x180ed193 },
6539 +       { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
6540 +       { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
6541 +       { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
6542 +       { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
6543 +       { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
6544 +       { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
6545 +       { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
6546 +       { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
6547 +       { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
6548 +       { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
6549 +       { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
6550 +       { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
6551 +
6552 +       /* 802.11 UNII */
6553 +       { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
6554 +       { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
6555 +       { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
6556 +       { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
6557 +       { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
6558 +       { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
6559 +       { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
6560 +
6561 +       /* 802.11 Japan */
6562 +       { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
6563 +       { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
6564 +       { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
6565 +       { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
6566 +       { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
6567 +       { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
6568 +       { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
6569 +};
6570 +
6571 +static int rt2800usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
6572 +{
6573 +       struct hw_mode_spec *spec = &rt2x00dev->spec;
6574 +       struct channel_info *info;
6575 +       char *tx_power1;
6576 +       char *tx_power2;
6577 +       unsigned int i;
6578 +
6579 +       /*
6580 +        * Initialize all hw fields.
6581 +        */
6582 +       rt2x00dev->hw->flags =
6583 +           IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
6584 +           IEEE80211_HW_SIGNAL_DBM;
6585 +       rt2x00dev->hw->extra_tx_headroom = TXD_DESC_SIZE + TXINFO_DESC_SIZE;
6586 +
6587 +       SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
6588 +       SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
6589 +                               rt2x00_eeprom_addr(rt2x00dev,
6590 +                                                  EEPROM_MAC_ADDR_0));
6591 +
6592 +       /*
6593 +        * Initialize hw_mode information.
6594 +        */
6595 +       spec->supported_bands = SUPPORT_BAND_2GHZ;
6596 +       spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
6597 +
6598 +       if (rt2x00_rf(&rt2x00dev->chip, RF2820) ||
6599 +           rt2x00_rf(&rt2x00dev->chip, RF2720)) {
6600 +               spec->num_channels = 14;
6601 +               spec->channels = rf_vals;
6602 +       } else if (rt2x00_rf(&rt2x00dev->chip, RF2850) ||
6603 +                  rt2x00_rf(&rt2x00dev->chip, RF2750)) {
6604 +               spec->supported_bands |= SUPPORT_BAND_5GHZ;
6605 +               spec->num_channels = ARRAY_SIZE(rf_vals);
6606 +               spec->channels = rf_vals;
6607 +       }
6608 +
6609 +       /*
6610 +        * Create channel information array
6611 +        */
6612 +       info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
6613 +       if (!info)
6614 +               return -ENOMEM;
6615 +
6616 +       spec->channels_info = info;
6617 +
6618 +       tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
6619 +       tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
6620 +
6621 +       for (i = 0; i < 14; i++) {
6622 +               info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
6623 +               info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
6624 +       }
6625 +
6626 +       if (spec->num_channels > 14) {
6627 +               tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
6628 +               tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
6629 +
6630 +               for (i = 14; i < spec->num_channels; i++) {
6631 +                       info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
6632 +                       info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
6633 +               }
6634 +       }
6635 +
6636 +       return 0;
6637 +}
6638 +
6639 +static int rt2800usb_probe_hw(struct rt2x00_dev *rt2x00dev)
6640 +{
6641 +       int retval;
6642 +
6643 +       /*
6644 +        * Allocate eeprom data.
6645 +        */
6646 +       retval = rt2800usb_validate_eeprom(rt2x00dev);
6647 +       if (retval)
6648 +               return retval;
6649 +
6650 +       retval = rt2800usb_init_eeprom(rt2x00dev);
6651 +       if (retval)
6652 +               return retval;
6653 +
6654 +       /*
6655 +        * Initialize hw specifications.
6656 +        */
6657 +       retval = rt2800usb_probe_hw_mode(rt2x00dev);
6658 +       if (retval)
6659 +               return retval;
6660 +
6661 +       /*
6662 +        * This device requires firmware.
6663 +        */
6664 +       __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
6665 +       __set_bit(DRIVER_REQUIRE_SCHEDULED, &rt2x00dev->flags);
6666 +       if (!modparam_nohwcrypt)
6667 +               __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
6668 +
6669 +       /*
6670 +        * Set the rssi offset.
6671 +        */
6672 +       rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
6673 +
6674 +       return 0;
6675 +}
6676 +
6677 +/*
6678 + * IEEE80211 stack callback functions.
6679 + */
6680 +static int rt2800usb_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
6681 +{
6682 +       struct rt2x00_dev *rt2x00dev = hw->priv;
6683 +       u32 reg;
6684 +
6685 +       rt2x00usb_register_read(rt2x00dev, TX_RTS_CFG, &reg);
6686 +       rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
6687 +       rt2x00usb_register_write(rt2x00dev, TX_RTS_CFG, reg);
6688 +
6689 +       rt2x00usb_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
6690 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
6691 +       rt2x00usb_register_write(rt2x00dev, CCK_PROT_CFG, reg);
6692 +
6693 +       rt2x00usb_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
6694 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
6695 +       rt2x00usb_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
6696 +
6697 +       rt2x00usb_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
6698 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 1);
6699 +       rt2x00usb_register_write(rt2x00dev, MM20_PROT_CFG, reg);
6700 +
6701 +       rt2x00usb_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
6702 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 1);
6703 +       rt2x00usb_register_write(rt2x00dev, MM40_PROT_CFG, reg);
6704 +
6705 +       rt2x00usb_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
6706 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 1);
6707 +       rt2x00usb_register_write(rt2x00dev, GF20_PROT_CFG, reg);
6708 +
6709 +       rt2x00usb_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
6710 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 1);
6711 +       rt2x00usb_register_write(rt2x00dev, GF40_PROT_CFG, reg);
6712 +
6713 +       return 0;
6714 +}
6715 +
6716 +static int rt2800usb_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
6717 +                            const struct ieee80211_tx_queue_params *params)
6718 +{
6719 +       struct rt2x00_dev *rt2x00dev = hw->priv;
6720 +       struct data_queue *queue;
6721 +       struct rt2x00_field32 field;
6722 +       int retval;
6723 +       u32 reg;
6724 +       u32 offset;
6725 +
6726 +       /*
6727 +        * First pass the configuration through rt2x00lib, that will
6728 +        * update the queue settings and validate the input. After that
6729 +        * we are free to update the registers based on the value
6730 +        * in the queue parameter.
6731 +        */
6732 +       retval = rt2x00mac_conf_tx(hw, queue_idx, params);
6733 +       if (retval)
6734 +               return retval;
6735 +
6736 +       queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
6737 +
6738 +       /* Update WMM TXOP register */
6739 +       if (queue_idx < 2) {
6740 +               field.bit_offset = queue_idx * 16;
6741 +               field.bit_mask = 0xffff << field.bit_offset;
6742 +
6743 +               rt2x00usb_register_read(rt2x00dev, WMM_TXOP0_CFG, &reg);
6744 +               rt2x00_set_field32(&reg, field, queue->txop);
6745 +               rt2x00usb_register_write(rt2x00dev, WMM_TXOP0_CFG, reg);
6746 +       } else if (queue_idx < 4) {
6747 +               field.bit_offset = (queue_idx - 2) * 16;
6748 +               field.bit_mask = 0xffff << field.bit_offset;
6749 +
6750 +               rt2x00usb_register_read(rt2x00dev, WMM_TXOP1_CFG, &reg);
6751 +               rt2x00_set_field32(&reg, field, queue->txop);
6752 +               rt2x00usb_register_write(rt2x00dev, WMM_TXOP1_CFG, reg);
6753 +       }
6754 +
6755 +       /* Update WMM registers */
6756 +       field.bit_offset = queue_idx * 4;
6757 +       field.bit_mask = 0xf << field.bit_offset;
6758 +
6759 +       rt2x00usb_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
6760 +       rt2x00_set_field32(&reg, field, queue->aifs);
6761 +       rt2x00usb_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
6762 +
6763 +       rt2x00usb_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
6764 +       rt2x00_set_field32(&reg, field, queue->cw_min);
6765 +       rt2x00usb_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
6766 +
6767 +       rt2x00usb_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
6768 +       rt2x00_set_field32(&reg, field, queue->cw_max);
6769 +       rt2x00usb_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
6770 +
6771 +       /* Update EDCA registers */
6772 +       if (queue_idx < 4) {
6773 +               offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
6774 +
6775 +               rt2x00usb_register_read(rt2x00dev, offset, &reg);
6776 +               rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
6777 +               rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
6778 +               rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
6779 +               rt2x00usb_register_write(rt2x00dev, offset, reg);
6780 +       }
6781 +
6782 +       return 0;
6783 +}
6784 +
6785 +#if 0
6786 +/*
6787 + * Mac80211 demands get_tsf must be atomic.
6788 + * This is not possible for rt2800usb since all register access
6789 + * functions require sleeping. Untill mac80211 no longer needs
6790 + * get_tsf to be atomic, this function should be disabled.
6791 + */
6792 +static u64 rt2800usb_get_tsf(struct ieee80211_hw *hw)
6793 +{
6794 +       struct rt2x00_dev *rt2x00dev = hw->priv;
6795 +       u64 tsf;
6796 +       u32 reg;
6797 +
6798 +       rt2x00usb_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
6799 +       tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
6800 +       rt2x00usb_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
6801 +       tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
6802 +
6803 +       return tsf;
6804 +}
6805 +#else
6806 +#define rt2800usb_get_tsf      NULL
6807 +#endif
6808 +
6809 +static const struct ieee80211_ops rt2800usb_mac80211_ops = {
6810 +       .tx                     = rt2x00mac_tx,
6811 +       .start                  = rt2x00mac_start,
6812 +       .stop                   = rt2x00mac_stop,
6813 +       .add_interface          = rt2x00mac_add_interface,
6814 +       .remove_interface       = rt2x00mac_remove_interface,
6815 +       .config                 = rt2x00mac_config,
6816 +       .config_interface       = rt2x00mac_config_interface,
6817 +       .configure_filter       = rt2x00mac_configure_filter,
6818 +       .set_key                = rt2x00mac_set_key,
6819 +       .get_stats              = rt2x00mac_get_stats,
6820 +       .set_rts_threshold      = rt2800usb_set_rts_threshold,
6821 +       .bss_info_changed       = rt2x00mac_bss_info_changed,
6822 +       .conf_tx                = rt2800usb_conf_tx,
6823 +       .get_tx_stats           = rt2x00mac_get_tx_stats,
6824 +       .get_tsf                = rt2800usb_get_tsf,
6825 +};
6826 +
6827 +static const struct rt2x00lib_ops rt2800usb_rt2x00_ops = {
6828 +       .probe_hw               = rt2800usb_probe_hw,
6829 +       .get_firmware_name      = rt2800usb_get_firmware_name,
6830 +       .get_firmware_crc       = rt2800usb_get_firmware_crc,
6831 +       .load_firmware          = rt2800usb_load_firmware,
6832 +       .initialize             = rt2x00usb_initialize,
6833 +       .uninitialize           = rt2x00usb_uninitialize,
6834 +       .clear_entry            = rt2x00usb_clear_entry,
6835 +       .set_device_state       = rt2800usb_set_device_state,
6836 +       .link_stats             = rt2800usb_link_stats,
6837 +       .reset_tuner            = rt2800usb_reset_tuner,
6838 +       .link_tuner             = rt2800usb_link_tuner,
6839 +       .write_tx_desc          = rt2800usb_write_tx_desc,
6840 +       .write_tx_data          = rt2x00usb_write_tx_data,
6841 +       .write_beacon           = rt2800usb_write_beacon,
6842 +       .get_tx_data_len        = rt2800usb_get_tx_data_len,
6843 +       .kick_tx_queue          = rt2800usb_kick_tx_queue,
6844 +       .fill_rxdone            = rt2800usb_fill_rxdone,
6845 +       .config_shared_key      = rt2800usb_config_shared_key,
6846 +       .config_pairwise_key    = rt2800usb_config_pairwise_key,
6847 +       .config_filter          = rt2800usb_config_filter,
6848 +       .config_intf            = rt2800usb_config_intf,
6849 +       .config_erp             = rt2800usb_config_erp,
6850 +       .config_ant             = rt2800usb_config_ant,
6851 +       .config                 = rt2800usb_config,
6852 +};
6853 +
6854 +static const struct data_queue_desc rt2800usb_queue_rx = {
6855 +       .entry_num              = RX_ENTRIES,
6856 +       .data_size              = DATA_FRAME_SIZE,
6857 +       .desc_size              = RXD_DESC_SIZE,
6858 +       .priv_size              = sizeof(struct queue_entry_priv_usb),
6859 +};
6860 +
6861 +static const struct data_queue_desc rt2800usb_queue_tx = {
6862 +       .entry_num              = TX_ENTRIES,
6863 +       .data_size              = DATA_FRAME_SIZE,
6864 +       .desc_size              = TXD_DESC_SIZE,
6865 +       .priv_size              = sizeof(struct queue_entry_priv_usb),
6866 +};
6867 +
6868 +static const struct data_queue_desc rt2800usb_queue_bcn = {
6869 +       .entry_num              = 8 * BEACON_ENTRIES,
6870 +       .data_size              = MGMT_FRAME_SIZE,
6871 +       .desc_size              = TXWI_DESC_SIZE,
6872 +       .priv_size              = sizeof(struct queue_entry_priv_usb),
6873 +};
6874 +
6875 +static const struct rt2x00_ops rt2800usb_ops = {
6876 +       .name           = KBUILD_MODNAME,
6877 +       .max_sta_intf   = 1,
6878 +       .max_ap_intf    = 8,
6879 +       .eeprom_size    = EEPROM_SIZE,
6880 +       .rf_size        = RF_SIZE,
6881 +       .tx_queues      = NUM_TX_QUEUES,
6882 +       .rx             = &rt2800usb_queue_rx,
6883 +       .tx             = &rt2800usb_queue_tx,
6884 +       .bcn            = &rt2800usb_queue_bcn,
6885 +       .lib            = &rt2800usb_rt2x00_ops,
6886 +       .hw             = &rt2800usb_mac80211_ops,
6887 +#ifdef CONFIG_RT2X00_LIB_DEBUGFS
6888 +       .debugfs        = &rt2800usb_rt2x00debug,
6889 +#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
6890 +};
6891 +
6892 +/*
6893 + * rt2800usb module information.
6894 + */
6895 +static struct usb_device_id rt2800usb_device_table[] = {
6896 +       /* Amit */
6897 +       { USB_DEVICE(0x15c5, 0x0008), USB_DEVICE_DATA(&rt2800usb_ops) },
6898 +       /* ASUS */
6899 +       { USB_DEVICE(0x0b05, 0x1731), USB_DEVICE_DATA(&rt2800usb_ops) },
6900 +       { USB_DEVICE(0x0b05, 0x1732), USB_DEVICE_DATA(&rt2800usb_ops) },
6901 +       { USB_DEVICE(0x0b05, 0x1742), USB_DEVICE_DATA(&rt2800usb_ops) },
6902 +       /* AzureWave */
6903 +       { USB_DEVICE(0x13d3, 0x3247), USB_DEVICE_DATA(&rt2800usb_ops) },
6904 +       /* Belkin */
6905 +       { USB_DEVICE(0x050d, 0x8053), USB_DEVICE_DATA(&rt2800usb_ops) },
6906 +       /* Conceptronic */
6907 +       { USB_DEVICE(0x14b2, 0x3c06), USB_DEVICE_DATA(&rt2800usb_ops) },
6908 +       { USB_DEVICE(0x14b2, 0x3c07), USB_DEVICE_DATA(&rt2800usb_ops) },
6909 +       { USB_DEVICE(0x14b2, 0x3c23), USB_DEVICE_DATA(&rt2800usb_ops) },
6910 +       { USB_DEVICE(0x14b2, 0x3c25), USB_DEVICE_DATA(&rt2800usb_ops) },
6911 +       { USB_DEVICE(0x14b2, 0x3c27), USB_DEVICE_DATA(&rt2800usb_ops) },
6912 +       { USB_DEVICE(0x14b2, 0x3c28), USB_DEVICE_DATA(&rt2800usb_ops) },
6913 +       /* Corega */
6914 +       { USB_DEVICE(0x07aa, 0x002f), USB_DEVICE_DATA(&rt2800usb_ops) },
6915 +       { USB_DEVICE(0x07aa, 0x003c), USB_DEVICE_DATA(&rt2800usb_ops) },
6916 +       { USB_DEVICE(0x07aa, 0x003f), USB_DEVICE_DATA(&rt2800usb_ops) },
6917 +       /* D-Link */
6918 +       { USB_DEVICE(0x07d1, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
6919 +       { USB_DEVICE(0x07d1, 0x3c11), USB_DEVICE_DATA(&rt2800usb_ops) },
6920 +       /* EnGenius */
6921 +       { USB_DEVICE(0X1740, 0x9701), USB_DEVICE_DATA(&rt2800usb_ops) },
6922 +       { USB_DEVICE(0x1740, 0x9702), USB_DEVICE_DATA(&rt2800usb_ops) },
6923 +       /* Gigabyte */
6924 +       { USB_DEVICE(0x1044, 0x800b), USB_DEVICE_DATA(&rt2800usb_ops) },
6925 +       /* Hawking */
6926 +       { USB_DEVICE(0x0e66, 0x0001), USB_DEVICE_DATA(&rt2800usb_ops) },
6927 +       { USB_DEVICE(0x0e66, 0x0003), USB_DEVICE_DATA(&rt2800usb_ops) },
6928 +       /* Linksys */
6929 +       { USB_DEVICE(0x1737, 0x0071), USB_DEVICE_DATA(&rt2800usb_ops) },
6930 +       /* Philips */
6931 +       { USB_DEVICE(0x0471, 0x200f), USB_DEVICE_DATA(&rt2800usb_ops) },
6932 +       /* Planex */
6933 +       { USB_DEVICE(0x2019, 0xed06), USB_DEVICE_DATA(&rt2800usb_ops) },
6934 +       /* Ralink */
6935 +       { USB_DEVICE(0x148f, 0x2770), USB_DEVICE_DATA(&rt2800usb_ops) },
6936 +       { USB_DEVICE(0x148f, 0x2870), USB_DEVICE_DATA(&rt2800usb_ops) },
6937 +       /* Siemens */
6938 +       { USB_DEVICE(0x129b, 0x1828), USB_DEVICE_DATA(&rt2800usb_ops) },
6939 +       /* Sitecom */
6940 +       { USB_DEVICE(0x0df6, 0x0017), USB_DEVICE_DATA(&rt2800usb_ops) },
6941 +       { USB_DEVICE(0x0df6, 0x002b), USB_DEVICE_DATA(&rt2800usb_ops) },
6942 +       { USB_DEVICE(0x0df6, 0x002c), USB_DEVICE_DATA(&rt2800usb_ops) },
6943 +       { USB_DEVICE(0x0df6, 0x002d), USB_DEVICE_DATA(&rt2800usb_ops) },
6944 +       /* SMC */
6945 +       { USB_DEVICE(0x083a, 0x6618), USB_DEVICE_DATA(&rt2800usb_ops) },
6946 +       { USB_DEVICE(0x083a, 0x7522), USB_DEVICE_DATA(&rt2800usb_ops) },
6947 +       { USB_DEVICE(0x083a, 0xb522), USB_DEVICE_DATA(&rt2800usb_ops) },
6948 +       { USB_DEVICE(0x083a, 0xa618), USB_DEVICE_DATA(&rt2800usb_ops) },
6949 +       /* Sparklan */
6950 +       { USB_DEVICE(0x15a9, 0x0006), USB_DEVICE_DATA(&rt2800usb_ops) },
6951 +       /* U-Media*/
6952 +       { USB_DEVICE(0x157e, 0x300e), USB_DEVICE_DATA(&rt2800usb_ops) },
6953 +       /* ZCOM */
6954 +       { USB_DEVICE(0x0cde, 0x0022), USB_DEVICE_DATA(&rt2800usb_ops) },
6955 +       { USB_DEVICE(0x0cde, 0x0025), USB_DEVICE_DATA(&rt2800usb_ops) },
6956 +       /* Zyxel */
6957 +       { USB_DEVICE(0x0586, 0x3416), USB_DEVICE_DATA(&rt2800usb_ops) },
6958 +       { 0, }
6959 +};
6960 +
6961 +MODULE_AUTHOR(DRV_PROJECT);
6962 +MODULE_VERSION(DRV_VERSION);
6963 +MODULE_DESCRIPTION("Ralink RT2800 USB Wireless LAN driver.");
6964 +MODULE_SUPPORTED_DEVICE("Ralink RT2870 USB chipset based cards");
6965 +MODULE_DEVICE_TABLE(usb, rt2800usb_device_table);
6966 +MODULE_FIRMWARE(FIRMWARE_RT2870);
6967 +MODULE_LICENSE("GPL");
6968 +
6969 +static struct usb_driver rt2800usb_driver = {
6970 +       .name           = KBUILD_MODNAME,
6971 +       .id_table       = rt2800usb_device_table,
6972 +       .probe          = rt2x00usb_probe,
6973 +       .disconnect     = rt2x00usb_disconnect,
6974 +       .suspend        = rt2x00usb_suspend,
6975 +       .resume         = rt2x00usb_resume,
6976 +};
6977 +
6978 +static int __init rt2800usb_init(void)
6979 +{
6980 +       return usb_register(&rt2800usb_driver);
6981 +}
6982 +
6983 +static void __exit rt2800usb_exit(void)
6984 +{
6985 +       usb_deregister(&rt2800usb_driver);
6986 +}
6987 +
6988 +module_init(rt2800usb_init);
6989 +module_exit(rt2800usb_exit);
6990 diff --git a/drivers/net/wireless/rt2x00/rt2800usb.h b/drivers/net/wireless/rt2x00/rt2800usb.h
6991 new file mode 100644
6992 index 0000000..1843217
6993 --- /dev/null
6994 +++ b/drivers/net/wireless/rt2x00/rt2800usb.h
6995 @@ -0,0 +1,1884 @@
6996 +/*
6997 +       Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
6998 +       <http://rt2x00.serialmonkey.com>
6999 +
7000 +       This program is free software; you can redistribute it and/or modify
7001 +       it under the terms of the GNU General Public License as published by
7002 +       the Free Software Foundation; either version 2 of the License, or
7003 +       (at your option) any later version.
7004 +
7005 +       This program is distributed in the hope that it will be useful,
7006 +       but WITHOUT ANY WARRANTY; without even the implied warranty of
7007 +       MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7008 +       GNU General Public License for more details.
7009 +
7010 +       You should have received a copy of the GNU General Public License
7011 +       along with this program; if not, write to the
7012 +       Free Software Foundation, Inc.,
7013 +       59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
7014 + */
7015 +
7016 +/*
7017 +       Module: rt2800usb
7018 +       Abstract: Data structures and registers for the rt2800usb module.
7019 +       Supported chipsets: RT2800U.
7020 + */
7021 +
7022 +#ifndef RT2800USB_H
7023 +#define RT2800USB_H
7024 +
7025 +/*
7026 + * RF chip defines.
7027 + *
7028 + * RF2820 2.4G 2T3R
7029 + * RF2850 2.4G/5G 2T3R
7030 + * RF2720 2.4G 1T2R
7031 + * RF2750 2.4G/5G 1T2R
7032 + */
7033 +#define RF2820                         0x0001
7034 +#define RF2850                         0x0002
7035 +#define RF2720                         0x0003
7036 +#define RF2750                         0x0004
7037 +
7038 +/*
7039 + * RT2870 version
7040 + */
7041 +#define RT2870_VERSION_C               0x0100
7042 +#define RT2870_VERSION_D               0x0101
7043 +#define RT2870_VERSION_E               0x0200
7044 +
7045 +/*
7046 + * Signal information.
7047 + * Defaul offset is required for RSSI <-> dBm conversion.
7048 + */
7049 +#define MAX_SIGNAL                     0 /* FIXME */
7050 +#define MAX_RX_SSI                     0 /* FIXME */
7051 +#define DEFAULT_RSSI_OFFSET            120 /* FIXME */
7052 +
7053 +/*
7054 + * Register layout information.
7055 + */
7056 +#define CSR_REG_BASE                   0x1000
7057 +#define CSR_REG_SIZE                   0x0800
7058 +#define EEPROM_BASE                    0x0000
7059 +#define EEPROM_SIZE                    0x0110
7060 +#define BBP_BASE                       0x0000
7061 +#define BBP_SIZE                       0x0080
7062 +#define RF_BASE                                0x0000
7063 +#define RF_SIZE                                0x0014
7064 +
7065 +/*
7066 + * Number of TX queues.
7067 + */
7068 +#define NUM_TX_QUEUES                  4
7069 +
7070 +/*
7071 + * USB registers.
7072 + */
7073 +
7074 +/*
7075 + * HOST-MCU shared memory
7076 + */
7077 +#define HOST_CMD_CSR                   0x0404
7078 +#define HOST_CMD_CSR_HOST_COMMAND      FIELD32(0x000000ff)
7079 +
7080 +/*
7081 + * INT_SOURCE_CSR: Interrupt source register.
7082 + * Write one to clear corresponding bit.
7083 + * TX_FIFO_STATUS: FIFO Statistics is full, sw should read 0x171c
7084 + */
7085 +#define INT_SOURCE_CSR                 0x0200
7086 +#define INT_SOURCE_CSR_RXDELAYINT      FIELD32(0x00000001)
7087 +#define INT_SOURCE_CSR_TXDELAYINT      FIELD32(0x00000002)
7088 +#define INT_SOURCE_CSR_RX_DONE         FIELD32(0x00000004)
7089 +#define INT_SOURCE_CSR_AC0_DMA_DONE    FIELD32(0x00000008)
7090 +#define INT_SOURCE_CSR_AC1_DMA_DONE    FIELD32(0x00000010)
7091 +#define INT_SOURCE_CSR_AC2_DMA_DONE    FIELD32(0x00000020)
7092 +#define INT_SOURCE_CSR_AC3_DMA_DONE    FIELD32(0x00000040)
7093 +#define INT_SOURCE_CSR_HCCA_DMA_DONE   FIELD32(0x00000080)
7094 +#define INT_SOURCE_CSR_MGMT_DMA_DONE   FIELD32(0x00000100)
7095 +#define INT_SOURCE_CSR_MCU_COMMAND     FIELD32(0x00000200)
7096 +#define INT_SOURCE_CSR_RXTX_COHERENT   FIELD32(0x00000400)
7097 +#define INT_SOURCE_CSR_TBTT            FIELD32(0x00000800)
7098 +#define INT_SOURCE_CSR_PRE_TBTT                FIELD32(0x00001000)
7099 +#define INT_SOURCE_CSR_TX_FIFO_STATUS  FIELD32(0x00002000)
7100 +#define INT_SOURCE_CSR_AUTO_WAKEUP     FIELD32(0x00004000)
7101 +#define INT_SOURCE_CSR_GPTIMER         FIELD32(0x00008000)
7102 +#define INT_SOURCE_CSR_RX_COHERENT     FIELD32(0x00010000)
7103 +#define INT_SOURCE_CSR_TX_COHERENT     FIELD32(0x00020000)
7104 +
7105 +/*
7106 + * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
7107 + */
7108 +#define INT_MASK_CSR                   0x0204
7109 +#define INT_MASK_CSR_RXDELAYINT                FIELD32(0x00000001)
7110 +#define INT_MASK_CSR_TXDELAYINT                FIELD32(0x00000002)
7111 +#define INT_MASK_CSR_RX_DONE           FIELD32(0x00000004)
7112 +#define INT_MASK_CSR_AC0_DMA_DONE      FIELD32(0x00000008)
7113 +#define INT_MASK_CSR_AC1_DMA_DONE      FIELD32(0x00000010)
7114 +#define INT_MASK_CSR_AC2_DMA_DONE      FIELD32(0x00000020)
7115 +#define INT_MASK_CSR_AC3_DMA_DONE      FIELD32(0x00000040)
7116 +#define INT_MASK_CSR_HCCA_DMA_DONE     FIELD32(0x00000080)
7117 +#define INT_MASK_CSR_MGMT_DMA_DONE     FIELD32(0x00000100)
7118 +#define INT_MASK_CSR_MCU_COMMAND       FIELD32(0x00000200)
7119 +#define INT_MASK_CSR_RX_COHERENT       FIELD32(0x40000000)
7120 +#define INT_MASK_CSR_TX_COHERENT       FIELD32(0x80000000)
7121 +
7122 +/*
7123 + * WPDMA_GLO_CFG
7124 + */
7125 +#define WPDMA_GLO_CFG                  0x0208
7126 +#define WPDMA_GLO_CFG_ENABLE_TX_DMA    FIELD32(0x00000001)
7127 +#define WPDMA_GLO_CFG_TX_DMA_BUSY      FIELD32(0x00000002)
7128 +#define WPDMA_GLO_CFG_ENABLE_RX_DMA    FIELD32(0x00000004)
7129 +#define WPDMA_GLO_CFG_RX_DMA_BUSY      FIELD32(0x00000008)
7130 +#define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE        FIELD32(0x00000030)
7131 +#define WPDMA_GLO_CFG_TX_WRITEBACK_DONE        FIELD32(0x00000040)
7132 +#define WPDMA_GLO_CFG_BIG_ENDIAN       FIELD32(0x00000080)
7133 +#define WPDMA_GLO_CFG_RX_HDR_SCATTER   FIELD32(0x0000ff00)
7134 +#define WPDMA_GLO_CFG_HDR_SEG_LEN      FIELD32(0xffff0000)
7135 +
7136 +/*
7137 + * WPDMA_RST_IDX
7138 + */
7139 +#define WPDMA_RST_IDX                  0x020c
7140 +#define WPDMA_RST_IDX_DTX_IDX0         FIELD32(0x00000001)
7141 +#define WPDMA_RST_IDX_DTX_IDX1         FIELD32(0x00000002)
7142 +#define WPDMA_RST_IDX_DTX_IDX2         FIELD32(0x00000004)
7143 +#define WPDMA_RST_IDX_DTX_IDX3         FIELD32(0x00000008)
7144 +#define WPDMA_RST_IDX_DTX_IDX4         FIELD32(0x00000010)
7145 +#define WPDMA_RST_IDX_DTX_IDX5         FIELD32(0x00000020)
7146 +#define WPDMA_RST_IDX_DRX_IDX0         FIELD32(0x00010000)
7147 +
7148 +/*
7149 + * DELAY_INT_CFG
7150 + */
7151 +#define DELAY_INT_CFG                  0x0210
7152 +#define DELAY_INT_CFG_RXMAX_PTIME      FIELD32(0x000000ff)
7153 +#define DELAY_INT_CFG_RXMAX_PINT       FIELD32(0x00007f00)
7154 +#define DELAY_INT_CFG_RXDLY_INT_EN     FIELD32(0x00008000)
7155 +#define DELAY_INT_CFG_TXMAX_PTIME      FIELD32(0x00ff0000)
7156 +#define DELAY_INT_CFG_TXMAX_PINT       FIELD32(0x7f000000)
7157 +#define DELAY_INT_CFG_TXDLY_INT_EN     FIELD32(0x80000000)
7158 +
7159 +/*
7160 + * WMM_AIFSN_CFG: Aifsn for each EDCA AC
7161 + * AIFSN0: AC_BE
7162 + * AIFSN1: AC_BK
7163 + * AIFSN1: AC_VI
7164 + * AIFSN1: AC_VO
7165 + */
7166 +#define WMM_AIFSN_CFG                  0x0214
7167 +#define WMM_AIFSN_CFG_AIFSN0           FIELD32(0x0000000f)
7168 +#define WMM_AIFSN_CFG_AIFSN1           FIELD32(0x000000f0)
7169 +#define WMM_AIFSN_CFG_AIFSN2           FIELD32(0x00000f00)
7170 +#define WMM_AIFSN_CFG_AIFSN3           FIELD32(0x0000f000)
7171 +
7172 +/*
7173 + * WMM_CWMIN_CSR: CWmin for each EDCA AC
7174 + * CWMIN0: AC_BE
7175 + * CWMIN1: AC_BK
7176 + * CWMIN1: AC_VI
7177 + * CWMIN1: AC_VO
7178 + */
7179 +#define WMM_CWMIN_CFG                  0x0218
7180 +#define WMM_CWMIN_CFG_CWMIN0           FIELD32(0x0000000f)
7181 +#define WMM_CWMIN_CFG_CWMIN1           FIELD32(0x000000f0)
7182 +#define WMM_CWMIN_CFG_CWMIN2           FIELD32(0x00000f00)
7183 +#define WMM_CWMIN_CFG_CWMIN3           FIELD32(0x0000f000)
7184 +
7185 +/*
7186 + * WMM_CWMAX_CSR: CWmax for each EDCA AC
7187 + * CWMAX0: AC_BE
7188 + * CWMAX1: AC_BK
7189 + * CWMAX1: AC_VI
7190 + * CWMAX1: AC_VO
7191 + */
7192 +#define WMM_CWMAX_CFG                  0x021c
7193 +#define WMM_CWMAX_CFG_CWMAX0           FIELD32(0x0000000f)
7194 +#define WMM_CWMAX_CFG_CWMAX1           FIELD32(0x000000f0)
7195 +#define WMM_CWMAX_CFG_CWMAX2           FIELD32(0x00000f00)
7196 +#define WMM_CWMAX_CFG_CWMAX3           FIELD32(0x0000f000)
7197 +
7198 +/*
7199 + * AC_TXOP0: AC_BK/AC_BE TXOP register
7200 + * AC0TXOP: AC_BK in unit of 32us
7201 + * AC1TXOP: AC_BE in unit of 32us
7202 + */
7203 +#define WMM_TXOP0_CFG                  0x0220
7204 +#define WMM_TXOP0_CFG_AC0TXOP          FIELD32(0x0000ffff)
7205 +#define WMM_TXOP0_CFG_AC1TXOP          FIELD32(0xffff0000)
7206 +
7207 +/*
7208 + * AC_TXOP1: AC_VO/AC_VI TXOP register
7209 + * AC2TXOP: AC_VI in unit of 32us
7210 + * AC3TXOP: AC_VO in unit of 32us
7211 + */
7212 +#define WMM_TXOP1_CFG                  0x0224
7213 +#define WMM_TXOP1_CFG_AC2TXOP          FIELD32(0x0000ffff)
7214 +#define WMM_TXOP1_CFG_AC3TXOP          FIELD32(0xffff0000)
7215 +
7216 +/*
7217 + * RINGREG_DIFF
7218 + */
7219 +#define RINGREG_DIFF                   0x0010
7220 +
7221 +/*
7222 + * GPIO_CTRL_CFG:
7223 + */
7224 +#define GPIO_CTRL_CFG                  0x0228
7225 +#define GPIO_CTRL_CFG_BIT0             FIELD32(0x00000001)
7226 +#define GPIO_CTRL_CFG_BIT1             FIELD32(0x00000002)
7227 +#define GPIO_CTRL_CFG_BIT2             FIELD32(0x00000004)
7228 +#define GPIO_CTRL_CFG_BIT3             FIELD32(0x00000008)
7229 +#define GPIO_CTRL_CFG_BIT4             FIELD32(0x00000010)
7230 +#define GPIO_CTRL_CFG_BIT5             FIELD32(0x00000020)
7231 +#define GPIO_CTRL_CFG_BIT6             FIELD32(0x00000040)
7232 +#define GPIO_CTRL_CFG_BIT7             FIELD32(0x00000080)
7233 +#define GPIO_CTRL_CFG_BIT8             FIELD32(0x00000100)
7234 +
7235 +/*
7236 + * MCU_CMD_CFG
7237 + */
7238 +#define MCU_CMD_CFG                    0x022c
7239 +
7240 +/*
7241 + * AC_BK register offsets
7242 + */
7243 +#define TX_BASE_PTR0                   0x0230
7244 +#define TX_MAX_CNT0                    0x0234
7245 +#define TX_CTX_IDX0                    0x0238
7246 +#define TX_DTX_IDX0                    0x023c
7247 +
7248 +/*
7249 + * AC_BE register offsets
7250 + */
7251 +#define TX_BASE_PTR1                   0x0240
7252 +#define TX_MAX_CNT1                    0x0244
7253 +#define TX_CTX_IDX1                    0x0248
7254 +#define TX_DTX_IDX1                    0x024c
7255 +
7256 +/*
7257 + * AC_VI register offsets
7258 + */
7259 +#define TX_BASE_PTR2                   0x0250
7260 +#define TX_MAX_CNT2                    0x0254
7261 +#define TX_CTX_IDX2                    0x0258
7262 +#define TX_DTX_IDX2                    0x025c
7263 +
7264 +/*
7265 + * AC_VO register offsets
7266 + */
7267 +#define TX_BASE_PTR3                   0x0260
7268 +#define TX_MAX_CNT3                    0x0264
7269 +#define TX_CTX_IDX3                    0x0268
7270 +#define TX_DTX_IDX3                    0x026c
7271 +
7272 +/*
7273 + * HCCA register offsets
7274 + */
7275 +#define TX_BASE_PTR4                   0x0270
7276 +#define TX_MAX_CNT4                    0x0274
7277 +#define TX_CTX_IDX4                    0x0278
7278 +#define TX_DTX_IDX4                    0x027c
7279 +
7280 +/*
7281 + * MGMT register offsets
7282 + */
7283 +#define TX_BASE_PTR5                   0x0280
7284 +#define TX_MAX_CNT5                    0x0284
7285 +#define TX_CTX_IDX5                    0x0288
7286 +#define TX_DTX_IDX5                    0x028c
7287 +
7288 +/*
7289 + * RX register offsets
7290 + */
7291 +#define RX_BASE_PTR                    0x0290
7292 +#define RX_MAX_CNT                     0x0294
7293 +#define RX_CRX_IDX                     0x0298
7294 +#define RX_DRX_IDX                     0x029c
7295 +
7296 +/*
7297 + * USB_DMA_CFG
7298 + * RX_BULK_AGG_TIMEOUT: Rx Bulk Aggregation TimeOut in unit of 33ns.
7299 + * RX_BULK_AGG_LIMIT: Rx Bulk Aggregation Limit in unit of 256 bytes.
7300 + * PHY_CLEAR: phy watch dog enable.
7301 + * TX_CLEAR: Clear USB DMA TX path.
7302 + * TXOP_HALT: Halt TXOP count down when TX buffer is full.
7303 + * RX_BULK_AGG_EN: Enable Rx Bulk Aggregation.
7304 + * RX_BULK_EN: Enable USB DMA Rx.
7305 + * TX_BULK_EN: Enable USB DMA Tx.
7306 + * EP_OUT_VALID: OUT endpoint data valid.
7307 + * RX_BUSY: USB DMA RX FSM busy.
7308 + * TX_BUSY: USB DMA TX FSM busy.
7309 + */
7310 +#define USB_DMA_CFG                    0x02a0
7311 +#define USB_DMA_CFG_RX_BULK_AGG_TIMEOUT        FIELD32(0x000000ff)
7312 +#define USB_DMA_CFG_RX_BULK_AGG_LIMIT  FIELD32(0x0000ff00)
7313 +#define USB_DMA_CFG_PHY_CLEAR          FIELD32(0x00010000)
7314 +#define USB_DMA_CFG_TX_CLEAR           FIELD32(0x00080000)
7315 +#define USB_DMA_CFG_TXOP_HALT          FIELD32(0x00100000)
7316 +#define USB_DMA_CFG_RX_BULK_AGG_EN     FIELD32(0x00200000)
7317 +#define USB_DMA_CFG_RX_BULK_EN         FIELD32(0x00400000)
7318 +#define USB_DMA_CFG_TX_BULK_EN         FIELD32(0x00800000)
7319 +#define USB_DMA_CFG_EP_OUT_VALID       FIELD32(0x3f000000)
7320 +#define USB_DMA_CFG_RX_BUSY            FIELD32(0x40000000)
7321 +#define USB_DMA_CFG_TX_BUSY            FIELD32(0x80000000)
7322 +
7323 +/*
7324 + * USB_CYC_CFG
7325 + */
7326 +#define USB_CYC_CFG                    0x02a4
7327 +#define USB_CYC_CFG_CLOCK_CYCLE                FIELD32(0x000000ff)
7328 +
7329 +/*
7330 + * PBF_SYS_CTRL
7331 + * HOST_RAM_WRITE: enable Host program ram write selection
7332 + */
7333 +#define PBF_SYS_CTRL                   0x0400
7334 +#define PBF_SYS_CTRL_READY             FIELD32(0x00000080)
7335 +#define PBF_SYS_CTRL_HOST_RAM_WRITE    FIELD32(0x00010000)
7336 +
7337 +/*
7338 + * PBF registers
7339 + * Most are for debug. Driver doesn't touch PBF register.
7340 + */
7341 +#define PBF_CFG                                0x0408
7342 +#define PBF_MAX_PCNT                   0x040c
7343 +#define PBF_CTRL                       0x0410
7344 +#define PBF_INT_STA                    0x0414
7345 +#define PBF_INT_ENA                    0x0418
7346 +
7347 +/*
7348 + * BCN_OFFSET0:
7349 + */
7350 +#define BCN_OFFSET0                    0x042c
7351 +#define BCN_OFFSET0_BCN0               FIELD32(0x000000ff)
7352 +#define BCN_OFFSET0_BCN1               FIELD32(0x0000ff00)
7353 +#define BCN_OFFSET0_BCN2               FIELD32(0x00ff0000)
7354 +#define BCN_OFFSET0_BCN3               FIELD32(0xff000000)
7355 +
7356 +/*
7357 + * BCN_OFFSET1:
7358 + */
7359 +#define BCN_OFFSET1                    0x0430
7360 +#define BCN_OFFSET1_BCN4               FIELD32(0x000000ff)
7361 +#define BCN_OFFSET1_BCN5               FIELD32(0x0000ff00)
7362 +#define BCN_OFFSET1_BCN6               FIELD32(0x00ff0000)
7363 +#define BCN_OFFSET1_BCN7               FIELD32(0xff000000)
7364 +
7365 +/*
7366 + * PBF registers
7367 + * Most are for debug. Driver doesn't touch PBF register.
7368 + */
7369 +#define TXRXQ_PCNT                     0x0438
7370 +#define PBF_DBG                                0x043c
7371 +
7372 +/*
7373 + * MAC Control/Status Registers(CSR).
7374 + * Some values are set in TU, whereas 1 TU == 1024 us.
7375 + */
7376 +
7377 +/*
7378 + * MAC_CSR0: ASIC revision number.
7379 + * ASIC_REV: 0
7380 + * ASIC_VER: 2870
7381 + */
7382 +#define MAC_CSR0                       0x1000
7383 +#define MAC_CSR0_ASIC_REV              FIELD32(0x0000ffff)
7384 +#define MAC_CSR0_ASIC_VER              FIELD32(0xffff0000)
7385 +
7386 +/*
7387 + * MAC_SYS_CTRL:
7388 + */
7389 +#define MAC_SYS_CTRL                   0x1004
7390 +#define MAC_SYS_CTRL_RESET_CSR         FIELD32(0x00000001)
7391 +#define MAC_SYS_CTRL_RESET_BBP         FIELD32(0x00000002)
7392 +#define MAC_SYS_CTRL_ENABLE_TX         FIELD32(0x00000004)
7393 +#define MAC_SYS_CTRL_ENABLE_RX         FIELD32(0x00000008)
7394 +#define MAC_SYS_CTRL_CONTINUOUS_TX     FIELD32(0x00000010)
7395 +#define MAC_SYS_CTRL_LOOPBACK          FIELD32(0x00000020)
7396 +#define MAC_SYS_CTRL_WLAN_HALT         FIELD32(0x00000040)
7397 +#define MAC_SYS_CTRL_RX_TIMESTAMP      FIELD32(0x00000080)
7398 +
7399 +/*
7400 + * MAC_ADDR_DW0: STA MAC register 0
7401 + */
7402 +#define MAC_ADDR_DW0                   0x1008
7403 +#define MAC_ADDR_DW0_BYTE0             FIELD32(0x000000ff)
7404 +#define MAC_ADDR_DW0_BYTE1             FIELD32(0x0000ff00)
7405 +#define MAC_ADDR_DW0_BYTE2             FIELD32(0x00ff0000)
7406 +#define MAC_ADDR_DW0_BYTE3             FIELD32(0xff000000)
7407 +
7408 +/*
7409 + * MAC_ADDR_DW1: STA MAC register 1
7410 + * UNICAST_TO_ME_MASK:
7411 + * Used to mask off bits from byte 5 of the MAC address
7412 + * to determine the UNICAST_TO_ME bit for RX frames.
7413 + * The full mask is complemented by BSS_ID_MASK:
7414 + *    MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
7415 + */
7416 +#define MAC_ADDR_DW1                   0x100c
7417 +#define MAC_ADDR_DW1_BYTE4             FIELD32(0x000000ff)
7418 +#define MAC_ADDR_DW1_BYTE5             FIELD32(0x0000ff00)
7419 +#define MAC_ADDR_DW1_UNICAST_TO_ME_MASK        FIELD32(0x00ff0000)
7420 +
7421 +/*
7422 + * MAC_BSSID_DW0: BSSID register 0
7423 + */
7424 +#define MAC_BSSID_DW0                  0x1010
7425 +#define MAC_BSSID_DW0_BYTE0            FIELD32(0x000000ff)
7426 +#define MAC_BSSID_DW0_BYTE1            FIELD32(0x0000ff00)
7427 +#define MAC_BSSID_DW0_BYTE2            FIELD32(0x00ff0000)
7428 +#define MAC_BSSID_DW0_BYTE3            FIELD32(0xff000000)
7429 +
7430 +/*
7431 + * MAC_BSSID_DW1: BSSID register 1
7432 + * BSS_ID_MASK:
7433 + *     0: 1-BSSID mode (BSS index = 0)
7434 + *     1: 2-BSSID mode (BSS index: Byte5, bit 0)
7435 + *     2: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
7436 + *     3: 8-BSSID mode (BSS index: byte5, bit 0 - 2)
7437 + * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the
7438 + * BSSID. This will make sure that those bits will be ignored
7439 + * when determining the MY_BSS of RX frames.
7440 + */
7441 +#define MAC_BSSID_DW1                  0x1014
7442 +#define MAC_BSSID_DW1_BYTE4            FIELD32(0x000000ff)
7443 +#define MAC_BSSID_DW1_BYTE5            FIELD32(0x0000ff00)
7444 +#define MAC_BSSID_DW1_BSS_ID_MASK      FIELD32(0x00030000)
7445 +#define MAC_BSSID_DW1_BSS_BCN_NUM      FIELD32(0x001c0000)
7446 +
7447 +/*
7448 + * MAX_LEN_CFG: Maximum frame length register.
7449 + * MAX_MPDU: rt2860b max 16k bytes
7450 + * MAX_PSDU: Maximum PSDU length
7451 + *     (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
7452 + */
7453 +#define MAX_LEN_CFG                    0x1018
7454 +#define MAX_LEN_CFG_MAX_MPDU           FIELD32(0x00000fff)
7455 +#define MAX_LEN_CFG_MAX_PSDU           FIELD32(0x00003000)
7456 +#define MAX_LEN_CFG_MIN_PSDU           FIELD32(0x0000c000)
7457 +#define MAX_LEN_CFG_MIN_MPDU           FIELD32(0x000f0000)
7458 +
7459 +/*
7460 + * BBP_CSR_CFG: BBP serial control register
7461 + * VALUE: Register value to program into BBP
7462 + * REG_NUM: Selected BBP register
7463 + * READ_CONTROL: 0 write BBP, 1 read BBP
7464 + * BUSY: ASIC is busy executing BBP commands
7465 + * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks
7466 + * BBP_RW_MODE: 0 serial, 1 paralell
7467 + */
7468 +#define BBP_CSR_CFG                    0x101c
7469 +#define BBP_CSR_CFG_VALUE              FIELD32(0x000000ff)
7470 +#define BBP_CSR_CFG_REGNUM             FIELD32(0x0000ff00)
7471 +#define BBP_CSR_CFG_READ_CONTROL       FIELD32(0x00010000)
7472 +#define BBP_CSR_CFG_BUSY               FIELD32(0x00020000)
7473 +#define BBP_CSR_CFG_BBP_PAR_DUR                FIELD32(0x00040000)
7474 +#define BBP_CSR_CFG_BBP_RW_MODE                FIELD32(0x00080000)
7475 +
7476 +/*
7477 + * RF_CSR_CFG0: RF control register
7478 + * REGID_AND_VALUE: Register value to program into RF
7479 + * BITWIDTH: Selected RF register
7480 + * STANDBYMODE: 0 high when standby, 1 low when standby
7481 + * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate
7482 + * BUSY: ASIC is busy executing RF commands
7483 + */
7484 +#define RF_CSR_CFG0                    0x1020
7485 +#define RF_CSR_CFG0_REGID_AND_VALUE    FIELD32(0x00ffffff)
7486 +#define RF_CSR_CFG0_BITWIDTH           FIELD32(0x1f000000)
7487 +#define RF_CSR_CFG0_REG_VALUE_BW       FIELD32(0x1fffffff)
7488 +#define RF_CSR_CFG0_STANDBYMODE                FIELD32(0x20000000)
7489 +#define RF_CSR_CFG0_SEL                        FIELD32(0x40000000)
7490 +#define RF_CSR_CFG0_BUSY               FIELD32(0x80000000)
7491 +
7492 +/*
7493 + * RF_CSR_CFG1: RF control register
7494 + * REGID_AND_VALUE: Register value to program into RF
7495 + * RFGAP: Gap between BB_CONTROL_RF and RF_LE
7496 + *        0: 3 system clock cycle (37.5usec)
7497 + *        1: 5 system clock cycle (62.5usec)
7498 + */
7499 +#define RF_CSR_CFG1                    0x1024
7500 +#define RF_CSR_CFG1_REGID_AND_VALUE    FIELD32(0x00ffffff)
7501 +#define RF_CSR_CFG1_RFGAP              FIELD32(0x1f000000)
7502 +
7503 +/*
7504 + * RF_CSR_CFG2: RF control register
7505 + * VALUE: Register value to program into RF
7506 + * RFGAP: Gap between BB_CONTROL_RF and RF_LE
7507 + *        0: 3 system clock cycle (37.5usec)
7508 + *        1: 5 system clock cycle (62.5usec)
7509 + */
7510 +#define RF_CSR_CFG2                    0x1028
7511 +#define RF_CSR_CFG2_VALUE              FIELD32(0x00ffffff)
7512 +
7513 +/*
7514 + * LED_CFG: LED control
7515 + * color LED's:
7516 + *   0: off
7517 + *   1: blinking upon TX2
7518 + *   2: periodic slow blinking
7519 + *   3: always on
7520 + * LED polarity:
7521 + *   0: active low
7522 + *   1: active high
7523 + */
7524 +#define LED_CFG                                0x102c
7525 +#define LED_CFG_ON_PERIOD              FIELD32(0x000000ff)
7526 +#define LED_CFG_OFF_PERIOD             FIELD32(0x0000ff00)
7527 +#define LED_CFG_SLOW_BLINK_PERIOD      FIELD32(0x003f0000)
7528 +#define LED_CFG_R_LED_MODE             FIELD32(0x03000000)
7529 +#define LED_CFG_G_LED_MODE             FIELD32(0x0c000000)
7530 +#define LED_CFG_Y_LED_MODE             FIELD32(0x30000000)
7531 +#define LED_CFG_LED_POLAR              FIELD32(0x40000000)
7532 +
7533 +/*
7534 + * XIFS_TIME_CFG: MAC timing
7535 + * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX
7536 + * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX
7537 + * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX
7538 + *     when MAC doesn't reference BBP signal BBRXEND
7539 + * EIFS: unit 1us
7540 + * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer
7541 + *
7542 + */
7543 +#define XIFS_TIME_CFG                  0x1100
7544 +#define XIFS_TIME_CFG_CCKM_SIFS_TIME   FIELD32(0x000000ff)
7545 +#define XIFS_TIME_CFG_OFDM_SIFS_TIME   FIELD32(0x0000ff00)
7546 +#define XIFS_TIME_CFG_OFDM_XIFS_TIME   FIELD32(0x000f0000)
7547 +#define XIFS_TIME_CFG_EIFS             FIELD32(0x1ff00000)
7548 +#define XIFS_TIME_CFG_BB_RXEND_ENABLE  FIELD32(0x20000000)
7549 +
7550 +/*
7551 + * BKOFF_SLOT_CFG:
7552 + */
7553 +#define BKOFF_SLOT_CFG                 0x1104
7554 +#define BKOFF_SLOT_CFG_SLOT_TIME       FIELD32(0x000000ff)
7555 +#define BKOFF_SLOT_CFG_CC_DELAY_TIME   FIELD32(0x0000ff00)
7556 +
7557 +/*
7558 + * NAV_TIME_CFG:
7559 + */
7560 +#define NAV_TIME_CFG                   0x1108
7561 +#define NAV_TIME_CFG_SIFS              FIELD32(0x000000ff)
7562 +#define NAV_TIME_CFG_SLOT_TIME         FIELD32(0x0000ff00)
7563 +#define NAV_TIME_CFG_EIFS              FIELD32(0x01ff0000)
7564 +#define NAV_TIME_ZERO_SIFS             FIELD32(0x02000000)
7565 +
7566 +/*
7567 + * CH_TIME_CFG: count as channel busy
7568 + */
7569 +#define CH_TIME_CFG                    0x110c
7570 +
7571 +/*
7572 + * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us
7573 + */
7574 +#define PBF_LIFE_TIMER                 0x1110
7575 +
7576 +/*
7577 + * BCN_TIME_CFG:
7578 + * BEACON_INTERVAL: in unit of 1/16 TU
7579 + * TSF_TICKING: Enable TSF auto counting
7580 + * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
7581 + * BEACON_GEN: Enable beacon generator
7582 + */
7583 +#define BCN_TIME_CFG                   0x1114
7584 +#define BCN_TIME_CFG_BEACON_INTERVAL   FIELD32(0x0000ffff)
7585 +#define BCN_TIME_CFG_TSF_TICKING       FIELD32(0x00010000)
7586 +#define BCN_TIME_CFG_TSF_SYNC          FIELD32(0x00060000)
7587 +#define BCN_TIME_CFG_TBTT_ENABLE       FIELD32(0x00080000)
7588 +#define BCN_TIME_CFG_BEACON_GEN                FIELD32(0x00100000)
7589 +#define BCN_TIME_CFG_TX_TIME_COMPENSATE        FIELD32(0xf0000000)
7590 +
7591 +/*
7592 + * TBTT_SYNC_CFG:
7593 + */
7594 +#define TBTT_SYNC_CFG                  0x1118
7595 +
7596 +/*
7597 + * TSF_TIMER_DW0: Local lsb TSF timer, read-only
7598 + */
7599 +#define TSF_TIMER_DW0                  0x111c
7600 +#define TSF_TIMER_DW0_LOW_WORD         FIELD32(0xffffffff)
7601 +
7602 +/*
7603 + * TSF_TIMER_DW1: Local msb TSF timer, read-only
7604 + */
7605 +#define TSF_TIMER_DW1                  0x1120
7606 +#define TSF_TIMER_DW1_HIGH_WORD                FIELD32(0xffffffff)
7607 +
7608 +/*
7609 + * TBTT_TIMER: TImer remains till next TBTT, read-only
7610 + */
7611 +#define TBTT_TIMER                     0x1124
7612 +
7613 +/*
7614 + * INT_TIMER_CFG:
7615 + */
7616 +#define INT_TIMER_CFG                  0x1128
7617 +
7618 +/*
7619 + * INT_TIMER_EN: GP-timer and pre-tbtt Int enable
7620 + */
7621 +#define INT_TIMER_EN                   0x112c
7622 +
7623 +/*
7624 + * CH_IDLE_STA: channel idle time
7625 + */
7626 +#define CH_IDLE_STA                    0x1130
7627 +
7628 +/*
7629 + * CH_BUSY_STA: channel busy time
7630 + */
7631 +#define CH_BUSY_STA                    0x1134
7632 +
7633 +/*
7634 + * MAC_STATUS_CFG:
7635 + * BBP_RF_BUSY: When set to 0, BBP and RF are stable.
7636 + *     if 1 or higher one of the 2 registers is busy.
7637 + */
7638 +#define MAC_STATUS_CFG                 0x1200
7639 +#define MAC_STATUS_CFG_BBP_RF_BUSY     FIELD32(0x00000003)
7640 +
7641 +/*
7642 + * PWR_PIN_CFG:
7643 + */
7644 +#define PWR_PIN_CFG                    0x1204
7645 +
7646 +/*
7647 + * AUTOWAKEUP_CFG: Manual power control / status register
7648 + * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set
7649 + * AUTOWAKE: 0:sleep, 1:awake
7650 + */
7651 +#define AUTOWAKEUP_CFG                 0x1208
7652 +#define AUTOWAKEUP_CFG_AUTO_LEAD_TIME  FIELD32(0x000000ff)
7653 +#define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE        FIELD32(0x00007f00)
7654 +#define AUTOWAKEUP_CFG_AUTOWAKE                FIELD32(0x00008000)
7655 +
7656 +/*
7657 + * EDCA_AC0_CFG:
7658 + */
7659 +#define EDCA_AC0_CFG                   0x1300
7660 +#define EDCA_AC0_CFG_AC_TX_OP          FIELD32(0x000000ff)
7661 +#define EDCA_AC0_CFG_AIFSN             FIELD32(0x00000f00)
7662 +#define EDCA_AC0_CFG_CWMIN             FIELD32(0x0000f000)
7663 +#define EDCA_AC0_CFG_CWMAX             FIELD32(0x000f0000)
7664 +
7665 +/*
7666 + * EDCA_AC1_CFG:
7667 + */
7668 +#define EDCA_AC1_CFG                   0x1304
7669 +#define EDCA_AC1_CFG_AC_TX_OP          FIELD32(0x000000ff)
7670 +#define EDCA_AC1_CFG_AIFSN             FIELD32(0x00000f00)
7671 +#define EDCA_AC1_CFG_CWMIN             FIELD32(0x0000f000)
7672 +#define EDCA_AC1_CFG_CWMAX             FIELD32(0x000f0000)
7673 +
7674 +/*
7675 + * EDCA_AC2_CFG:
7676 + */
7677 +#define EDCA_AC2_CFG                   0x1308
7678 +#define EDCA_AC2_CFG_AC_TX_OP          FIELD32(0x000000ff)
7679 +#define EDCA_AC2_CFG_AIFSN             FIELD32(0x00000f00)
7680 +#define EDCA_AC2_CFG_CWMIN             FIELD32(0x0000f000)
7681 +#define EDCA_AC2_CFG_CWMAX             FIELD32(0x000f0000)
7682 +
7683 +/*
7684 + * EDCA_AC3_CFG:
7685 + */
7686 +#define EDCA_AC3_CFG                   0x130c
7687 +#define EDCA_AC3_CFG_AC_TX_OP          FIELD32(0x000000ff)
7688 +#define EDCA_AC3_CFG_AIFSN             FIELD32(0x00000f00)
7689 +#define EDCA_AC3_CFG_CWMIN             FIELD32(0x0000f000)
7690 +#define EDCA_AC3_CFG_CWMAX             FIELD32(0x000f0000)
7691 +
7692 +/*
7693 + * EDCA_TID_AC_MAP:
7694 + */
7695 +#define EDCA_TID_AC_MAP                        0x1310
7696 +
7697 +/*
7698 + * TX_PWR_CFG_0:
7699 + */
7700 +#define TX_PWR_CFG_0                   0x1314
7701 +#define TX_PWR_CFG_0_1MBS              FIELD32(0x0000000f)
7702 +#define TX_PWR_CFG_0_2MBS              FIELD32(0x000000f0)
7703 +#define TX_PWR_CFG_0_55MBS             FIELD32(0x00000f00)
7704 +#define TX_PWR_CFG_0_11MBS             FIELD32(0x0000f000)
7705 +#define TX_PWR_CFG_0_6MBS              FIELD32(0x000f0000)
7706 +#define TX_PWR_CFG_0_9MBS              FIELD32(0x00f00000)
7707 +#define TX_PWR_CFG_0_12MBS             FIELD32(0x0f000000)
7708 +#define TX_PWR_CFG_0_18MBS             FIELD32(0xf0000000)
7709 +
7710 +/*
7711 + * TX_PWR_CFG_1:
7712 + */
7713 +#define TX_PWR_CFG_1                   0x1318
7714 +#define TX_PWR_CFG_1_24MBS             FIELD32(0x0000000f)
7715 +#define TX_PWR_CFG_1_36MBS             FIELD32(0x000000f0)
7716 +#define TX_PWR_CFG_1_48MBS             FIELD32(0x00000f00)
7717 +#define TX_PWR_CFG_1_54MBS             FIELD32(0x0000f000)
7718 +#define TX_PWR_CFG_1_MCS0              FIELD32(0x000f0000)
7719 +#define TX_PWR_CFG_1_MCS1              FIELD32(0x00f00000)
7720 +#define TX_PWR_CFG_1_MCS2              FIELD32(0x0f000000)
7721 +#define TX_PWR_CFG_1_MCS3              FIELD32(0xf0000000)
7722 +
7723 +/*
7724 + * TX_PWR_CFG_2:
7725 + */
7726 +#define TX_PWR_CFG_2                   0x131c
7727 +#define TX_PWR_CFG_2_MCS4              FIELD32(0x0000000f)
7728 +#define TX_PWR_CFG_2_MCS5              FIELD32(0x000000f0)
7729 +#define TX_PWR_CFG_2_MCS6              FIELD32(0x00000f00)
7730 +#define TX_PWR_CFG_2_MCS7              FIELD32(0x0000f000)
7731 +#define TX_PWR_CFG_2_MCS8              FIELD32(0x000f0000)
7732 +#define TX_PWR_CFG_2_MCS9              FIELD32(0x00f00000)
7733 +#define TX_PWR_CFG_2_MCS10             FIELD32(0x0f000000)
7734 +#define TX_PWR_CFG_2_MCS11             FIELD32(0xf0000000)
7735 +
7736 +/*
7737 + * TX_PWR_CFG_3:
7738 + */
7739 +#define TX_PWR_CFG_3                   0x1320
7740 +#define TX_PWR_CFG_3_MCS12             FIELD32(0x0000000f)
7741 +#define TX_PWR_CFG_3_MCS13             FIELD32(0x000000f0)
7742 +#define TX_PWR_CFG_3_MCS14             FIELD32(0x00000f00)
7743 +#define TX_PWR_CFG_3_MCS15             FIELD32(0x0000f000)
7744 +#define TX_PWR_CFG_3_UKNOWN1           FIELD32(0x000f0000)
7745 +#define TX_PWR_CFG_3_UKNOWN2           FIELD32(0x00f00000)
7746 +#define TX_PWR_CFG_3_UKNOWN3           FIELD32(0x0f000000)
7747 +#define TX_PWR_CFG_3_UKNOWN4           FIELD32(0xf0000000)
7748 +
7749 +/*
7750 + * TX_PWR_CFG_4:
7751 + */
7752 +#define TX_PWR_CFG_4                   0x1324
7753 +#define TX_PWR_CFG_4_UKNOWN5           FIELD32(0x0000000f)
7754 +#define TX_PWR_CFG_4_UKNOWN6           FIELD32(0x000000f0)
7755 +#define TX_PWR_CFG_4_UKNOWN7           FIELD32(0x00000f00)
7756 +#define TX_PWR_CFG_4_UKNOWN8           FIELD32(0x0000f000)
7757 +
7758 +/*
7759 + * TX_PIN_CFG:
7760 + */
7761 +#define TX_PIN_CFG                     0x1328
7762 +#define TX_PIN_CFG_PA_PE_A0_EN         FIELD32(0x00000001)
7763 +#define TX_PIN_CFG_PA_PE_G0_EN         FIELD32(0x00000002)
7764 +#define TX_PIN_CFG_PA_PE_A1_EN         FIELD32(0x00000004)
7765 +#define TX_PIN_CFG_PA_PE_G1_EN         FIELD32(0x00000008)
7766 +#define TX_PIN_CFG_PA_PE_A0_POL                FIELD32(0x00000010)
7767 +#define TX_PIN_CFG_PA_PE_G0_POL                FIELD32(0x00000020)
7768 +#define TX_PIN_CFG_PA_PE_A1_POL                FIELD32(0x00000040)
7769 +#define TX_PIN_CFG_PA_PE_G1_POL                FIELD32(0x00000080)
7770 +#define TX_PIN_CFG_LNA_PE_A0_EN                FIELD32(0x00000100)
7771 +#define TX_PIN_CFG_LNA_PE_G0_EN                FIELD32(0x00000200)
7772 +#define TX_PIN_CFG_LNA_PE_A1_EN                FIELD32(0x00000400)
7773 +#define TX_PIN_CFG_LNA_PE_G1_EN                FIELD32(0x00000800)
7774 +#define TX_PIN_CFG_LNA_PE_A0_POL       FIELD32(0x00001000)
7775 +#define TX_PIN_CFG_LNA_PE_G0_POL       FIELD32(0x00002000)
7776 +#define TX_PIN_CFG_LNA_PE_A1_POL       FIELD32(0x00004000)
7777 +#define TX_PIN_CFG_LNA_PE_G1_POL       FIELD32(0x00008000)
7778 +#define TX_PIN_CFG_RFTR_EN             FIELD32(0x00010000)
7779 +#define TX_PIN_CFG_RFTR_POL            FIELD32(0x00020000)
7780 +#define TX_PIN_CFG_TRSW_EN             FIELD32(0x00040000)
7781 +#define TX_PIN_CFG_TRSW_POL            FIELD32(0x00080000)
7782 +
7783 +/*
7784 + * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz
7785 + */
7786 +#define TX_BAND_CFG                    0x132c
7787 +#define TX_BAND_CFG_A                  FIELD32(0x00000002)
7788 +#define TX_BAND_CFG_BG                 FIELD32(0x00000004)
7789 +
7790 +/*
7791 + * TX_SW_CFG0:
7792 + */
7793 +#define TX_SW_CFG0                     0x1330
7794 +
7795 +/*
7796 + * TX_SW_CFG1:
7797 + */
7798 +#define TX_SW_CFG1                     0x1334
7799 +
7800 +/*
7801 + * TX_SW_CFG2:
7802 + */
7803 +#define TX_SW_CFG2                     0x1338
7804 +
7805 +/*
7806 + * TXOP_THRES_CFG:
7807 + */
7808 +#define TXOP_THRES_CFG                 0x133c
7809 +
7810 +/*
7811 + * TXOP_CTRL_CFG:
7812 + */
7813 +#define TXOP_CTRL_CFG                  0x1340
7814 +
7815 +/*
7816 + * TX_RTS_CFG:
7817 + * RTS_THRES: unit:byte
7818 + * RTS_FBK_EN: enable rts rate fallback
7819 + */
7820 +#define TX_RTS_CFG                     0x1344
7821 +#define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT        FIELD32(0x000000ff)
7822 +#define TX_RTS_CFG_RTS_THRES           FIELD32(0x00ffff00)
7823 +#define TX_RTS_CFG_RTS_FBK_EN          FIELD32(0x01000000)
7824 +
7825 +/*
7826 + * TX_TIMEOUT_CFG:
7827 + * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us
7828 + * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure
7829 + * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation.
7830 + *                it is recommended that:
7831 + *                (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
7832 + */
7833 +#define TX_TIMEOUT_CFG                 0x1348
7834 +#define TX_TIMEOUT_CFG_MPDU_LIFETIME   FIELD32(0x000000f0)
7835 +#define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT  FIELD32(0x0000ff00)
7836 +#define TX_TIMEOUT_CFG_TX_OP_TIMEOUT   FIELD32(0x00ff0000)
7837 +
7838 +/*
7839 + * TX_RTY_CFG:
7840 + * SHORT_RTY_LIMIT: short retry limit
7841 + * LONG_RTY_LIMIT: long retry limit
7842 + * LONG_RTY_THRE: Long retry threshoold
7843 + * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode
7844 + *                   0:expired by retry limit, 1: expired by mpdu life timer
7845 + * AGG_RTY_MODE: Aggregate MPDU retry mode
7846 + *               0:expired by retry limit, 1: expired by mpdu life timer
7847 + * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable
7848 + */
7849 +#define TX_RTY_CFG                     0x134c
7850 +#define TX_RTY_CFG_SHORT_RTY_LIMIT     FIELD32(0x000000ff)
7851 +#define TX_RTY_CFG_LONG_RTY_LIMIT      FIELD32(0x0000ff00)
7852 +#define TX_RTY_CFG_LONG_RTY_THRE       FIELD32(0x0fff0000)
7853 +#define TX_RTY_CFG_NON_AGG_RTY_MODE    FIELD32(0x10000000)
7854 +#define TX_RTY_CFG_AGG_RTY_MODE                FIELD32(0x20000000)
7855 +#define TX_RTY_CFG_TX_AUTO_FB_ENABLE   FIELD32(0x40000000)
7856 +
7857 +/*
7858 + * TX_LINK_CFG:
7859 + * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us
7860 + * MFB_ENABLE: TX apply remote MFB 1:enable
7861 + * REMOTE_UMFS_ENABLE: remote unsolicit  MFB enable
7862 + *                     0: not apply remote remote unsolicit (MFS=7)
7863 + * TX_MRQ_EN: MCS request TX enable
7864 + * TX_RDG_EN: RDG TX enable
7865 + * TX_CF_ACK_EN: Piggyback CF-ACK enable
7866 + * REMOTE_MFB: remote MCS feedback
7867 + * REMOTE_MFS: remote MCS feedback sequence number
7868 + */
7869 +#define TX_LINK_CFG                    0x1350
7870 +#define TX_LINK_CFG_REMOTE_MFB_LIFETIME        FIELD32(0x000000ff)
7871 +#define TX_LINK_CFG_MFB_ENABLE         FIELD32(0x00000100)
7872 +#define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200)
7873 +#define TX_LINK_CFG_TX_MRQ_EN          FIELD32(0x00000400)
7874 +#define TX_LINK_CFG_TX_RDG_EN          FIELD32(0x00000800)
7875 +#define TX_LINK_CFG_TX_CF_ACK_EN       FIELD32(0x00001000)
7876 +#define TX_LINK_CFG_REMOTE_MFB         FIELD32(0x00ff0000)
7877 +#define TX_LINK_CFG_REMOTE_MFS         FIELD32(0xff000000)
7878 +
7879 +/*
7880 + * HT_FBK_CFG0:
7881 + */
7882 +#define HT_FBK_CFG0                    0x1354
7883 +#define HT_FBK_CFG0_HTMCS0FBK          FIELD32(0x0000000f)
7884 +#define HT_FBK_CFG0_HTMCS1FBK          FIELD32(0x000000f0)
7885 +#define HT_FBK_CFG0_HTMCS2FBK          FIELD32(0x00000f00)
7886 +#define HT_FBK_CFG0_HTMCS3FBK          FIELD32(0x0000f000)
7887 +#define HT_FBK_CFG0_HTMCS4FBK          FIELD32(0x000f0000)
7888 +#define HT_FBK_CFG0_HTMCS5FBK          FIELD32(0x00f00000)
7889 +#define HT_FBK_CFG0_HTMCS6FBK          FIELD32(0x0f000000)
7890 +#define HT_FBK_CFG0_HTMCS7FBK          FIELD32(0xf0000000)
7891 +
7892 +/*
7893 + * HT_FBK_CFG1:
7894 + */
7895 +#define HT_FBK_CFG1                    0x1358
7896 +#define HT_FBK_CFG1_HTMCS8FBK          FIELD32(0x0000000f)
7897 +#define HT_FBK_CFG1_HTMCS9FBK          FIELD32(0x000000f0)
7898 +#define HT_FBK_CFG1_HTMCS10FBK         FIELD32(0x00000f00)
7899 +#define HT_FBK_CFG1_HTMCS11FBK         FIELD32(0x0000f000)
7900 +#define HT_FBK_CFG1_HTMCS12FBK         FIELD32(0x000f0000)
7901 +#define HT_FBK_CFG1_HTMCS13FBK         FIELD32(0x00f00000)
7902 +#define HT_FBK_CFG1_HTMCS14FBK         FIELD32(0x0f000000)
7903 +#define HT_FBK_CFG1_HTMCS15FBK         FIELD32(0xf0000000)
7904 +
7905 +/*
7906 + * LG_FBK_CFG0:
7907 + */
7908 +#define LG_FBK_CFG0                    0x135c
7909 +#define LG_FBK_CFG0_OFDMMCS0FBK                FIELD32(0x0000000f)
7910 +#define LG_FBK_CFG0_OFDMMCS1FBK                FIELD32(0x000000f0)
7911 +#define LG_FBK_CFG0_OFDMMCS2FBK                FIELD32(0x00000f00)
7912 +#define LG_FBK_CFG0_OFDMMCS3FBK                FIELD32(0x0000f000)
7913 +#define LG_FBK_CFG0_OFDMMCS4FBK                FIELD32(0x000f0000)
7914 +#define LG_FBK_CFG0_OFDMMCS5FBK                FIELD32(0x00f00000)
7915 +#define LG_FBK_CFG0_OFDMMCS6FBK                FIELD32(0x0f000000)
7916 +#define LG_FBK_CFG0_OFDMMCS7FBK                FIELD32(0xf0000000)
7917 +
7918 +/*
7919 + * LG_FBK_CFG1:
7920 + */
7921 +#define LG_FBK_CFG1                    0x1360
7922 +#define LG_FBK_CFG0_CCKMCS0FBK         FIELD32(0x0000000f)
7923 +#define LG_FBK_CFG0_CCKMCS1FBK         FIELD32(0x000000f0)
7924 +#define LG_FBK_CFG0_CCKMCS2FBK         FIELD32(0x00000f00)
7925 +#define LG_FBK_CFG0_CCKMCS3FBK         FIELD32(0x0000f000)
7926 +
7927 +/*
7928 + * CCK_PROT_CFG: CCK Protection
7929 + * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd)
7930 + * PROTECT_CTRL: Protection control frame type for CCK TX
7931 + *               0:none, 1:RTS/CTS, 2:CTS-to-self
7932 + * PROTECT_NAV: TXOP protection type for CCK TX
7933 + *              0:none, 1:ShortNAVprotect, 2:LongNAVProtect
7934 + * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow
7935 + * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow
7936 + * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow
7937 + * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow
7938 + * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow
7939 + * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow
7940 + * RTS_TH_EN: RTS threshold enable on CCK TX
7941 + */
7942 +#define CCK_PROT_CFG                   0x1364
7943 +#define CCK_PROT_CFG_PROTECT_RATE      FIELD32(0x0000ffff)
7944 +#define CCK_PROT_CFG_PROTECT_CTRL      FIELD32(0x00030000)
7945 +#define CCK_PROT_CFG_PROTECT_NAV       FIELD32(0x000c0000)
7946 +#define CCK_PROT_CFG_TX_OP_ALLOW_CCK   FIELD32(0x00100000)
7947 +#define CCK_PROT_CFG_TX_OP_ALLOW_OFDM  FIELD32(0x00200000)
7948 +#define CCK_PROT_CFG_TX_OP_ALLOW_MM20  FIELD32(0x00400000)
7949 +#define CCK_PROT_CFG_TX_OP_ALLOW_MM40  FIELD32(0x00800000)
7950 +#define CCK_PROT_CFG_TX_OP_ALLOW_GF20  FIELD32(0x01000000)
7951 +#define CCK_PROT_CFG_TX_OP_ALLOW_GF40  FIELD32(0x02000000)
7952 +#define CCK_PROT_CFG_RTS_TH_EN         FIELD32(0x04000000)
7953 +
7954 +/*
7955 + * OFDM_PROT_CFG: OFDM Protection
7956 + */
7957 +#define OFDM_PROT_CFG                  0x1368
7958 +#define OFDM_PROT_CFG_PROTECT_RATE     FIELD32(0x0000ffff)
7959 +#define OFDM_PROT_CFG_PROTECT_CTRL     FIELD32(0x00030000)
7960 +#define OFDM_PROT_CFG_PROTECT_NAV      FIELD32(0x000c0000)
7961 +#define OFDM_PROT_CFG_TX_OP_ALLOW_CCK  FIELD32(0x00100000)
7962 +#define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
7963 +#define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
7964 +#define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
7965 +#define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
7966 +#define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
7967 +#define OFDM_PROT_CFG_RTS_TH_EN                FIELD32(0x04000000)
7968 +
7969 +/*
7970 + * MM20_PROT_CFG: MM20 Protection
7971 + */
7972 +#define MM20_PROT_CFG                  0x136c
7973 +#define MM20_PROT_CFG_PROTECT_RATE     FIELD32(0x0000ffff)
7974 +#define MM20_PROT_CFG_PROTECT_CTRL     FIELD32(0x00030000)
7975 +#define MM20_PROT_CFG_PROTECT_NAV      FIELD32(0x000c0000)
7976 +#define MM20_PROT_CFG_TX_OP_ALLOW_CCK  FIELD32(0x00100000)
7977 +#define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
7978 +#define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
7979 +#define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
7980 +#define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
7981 +#define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
7982 +#define MM20_PROT_CFG_RTS_TH_EN                FIELD32(0x04000000)
7983 +
7984 +/*
7985 + * MM40_PROT_CFG: MM40 Protection
7986 + */
7987 +#define MM40_PROT_CFG                  0x1370
7988 +#define MM40_PROT_CFG_PROTECT_RATE     FIELD32(0x0000ffff)
7989 +#define MM40_PROT_CFG_PROTECT_CTRL     FIELD32(0x00030000)
7990 +#define MM40_PROT_CFG_PROTECT_NAV      FIELD32(0x000c0000)
7991 +#define MM40_PROT_CFG_TX_OP_ALLOW_CCK  FIELD32(0x00100000)
7992 +#define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
7993 +#define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
7994 +#define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
7995 +#define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
7996 +#define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
7997 +#define MM40_PROT_CFG_RTS_TH_EN                FIELD32(0x04000000)
7998 +
7999 +/*
8000 + * GF20_PROT_CFG: GF20 Protection
8001 + */
8002 +#define GF20_PROT_CFG                  0x1374
8003 +#define GF20_PROT_CFG_PROTECT_RATE     FIELD32(0x0000ffff)
8004 +#define GF20_PROT_CFG_PROTECT_CTRL     FIELD32(0x00030000)
8005 +#define GF20_PROT_CFG_PROTECT_NAV      FIELD32(0x000c0000)
8006 +#define GF20_PROT_CFG_TX_OP_ALLOW_CCK  FIELD32(0x00100000)
8007 +#define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
8008 +#define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
8009 +#define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
8010 +#define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
8011 +#define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
8012 +#define GF20_PROT_CFG_RTS_TH_EN                FIELD32(0x04000000)
8013 +
8014 +/*
8015 + * GF40_PROT_CFG: GF40 Protection
8016 + */
8017 +#define GF40_PROT_CFG                  0x1378
8018 +#define GF40_PROT_CFG_PROTECT_RATE     FIELD32(0x0000ffff)
8019 +#define GF40_PROT_CFG_PROTECT_CTRL     FIELD32(0x00030000)
8020 +#define GF40_PROT_CFG_PROTECT_NAV      FIELD32(0x000c0000)
8021 +#define GF40_PROT_CFG_TX_OP_ALLOW_CCK  FIELD32(0x00100000)
8022 +#define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
8023 +#define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
8024 +#define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
8025 +#define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
8026 +#define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
8027 +#define GF40_PROT_CFG_RTS_TH_EN                FIELD32(0x04000000)
8028 +
8029 +/*
8030 + * EXP_CTS_TIME:
8031 + */
8032 +#define EXP_CTS_TIME                   0x137c
8033 +
8034 +/*
8035 + * EXP_ACK_TIME:
8036 + */
8037 +#define EXP_ACK_TIME                   0x1380
8038 +
8039 +/*
8040 + * RX_FILTER_CFG: RX configuration register.
8041 + */
8042 +#define RX_FILTER_CFG                  0x1400
8043 +#define RX_FILTER_CFG_DROP_CRC_ERROR   FIELD32(0x00000001)
8044 +#define RX_FILTER_CFG_DROP_PHY_ERROR   FIELD32(0x00000002)
8045 +#define RX_FILTER_CFG_DROP_NOT_TO_ME   FIELD32(0x00000004)
8046 +#define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008)
8047 +#define RX_FILTER_CFG_DROP_VER_ERROR   FIELD32(0x00000010)
8048 +#define RX_FILTER_CFG_DROP_MULTICAST   FIELD32(0x00000020)
8049 +#define RX_FILTER_CFG_DROP_BROADCAST   FIELD32(0x00000040)
8050 +#define RX_FILTER_CFG_DROP_DUPLICATE   FIELD32(0x00000080)
8051 +#define RX_FILTER_CFG_DROP_CF_END_ACK  FIELD32(0x00000100)
8052 +#define RX_FILTER_CFG_DROP_CF_END      FIELD32(0x00000200)
8053 +#define RX_FILTER_CFG_DROP_ACK         FIELD32(0x00000400)
8054 +#define RX_FILTER_CFG_DROP_CTS         FIELD32(0x00000800)
8055 +#define RX_FILTER_CFG_DROP_RTS         FIELD32(0x00001000)
8056 +#define RX_FILTER_CFG_DROP_PSPOLL      FIELD32(0x00002000)
8057 +#define RX_FILTER_CFG_DROP_BA          FIELD32(0x00004000)
8058 +#define RX_FILTER_CFG_DROP_BAR         FIELD32(0x00008000)
8059 +#define RX_FILTER_CFG_DROP_CNTL                FIELD32(0x00010000)
8060 +
8061 +/*
8062 + * AUTO_RSP_CFG:
8063 + * AUTORESPONDER: 0: disable, 1: enable
8064 + * BAC_ACK_POLICY: 0:long, 1:short preamble
8065 + * CTS_40_MMODE: Response CTS 40MHz duplicate mode
8066 + * CTS_40_MREF: Response CTS 40MHz duplicate mode
8067 + * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble
8068 + * DUAL_CTS_EN: Power bit value in control frame
8069 + * ACK_CTS_PSM_BIT:Power bit value in control frame
8070 + */
8071 +#define AUTO_RSP_CFG                   0x1404
8072 +#define AUTO_RSP_CFG_AUTORESPONDER     FIELD32(0x00000001)
8073 +#define AUTO_RSP_CFG_BAC_ACK_POLICY    FIELD32(0x00000002)
8074 +#define AUTO_RSP_CFG_CTS_40_MMODE      FIELD32(0x00000004)
8075 +#define AUTO_RSP_CFG_CTS_40_MREF       FIELD32(0x00000008)
8076 +#define AUTO_RSP_CFG_AR_PREAMBLE       FIELD32(0x00000010)
8077 +#define AUTO_RSP_CFG_DUAL_CTS_EN       FIELD32(0x00000040)
8078 +#define AUTO_RSP_CFG_ACK_CTS_PSM_BIT   FIELD32(0x00000080)
8079 +
8080 +/*
8081 + * LEGACY_BASIC_RATE:
8082 + */
8083 +#define LEGACY_BASIC_RATE              0x1408
8084 +
8085 +/*
8086 + * HT_BASIC_RATE:
8087 + */
8088 +#define HT_BASIC_RATE                  0x140c
8089 +
8090 +/*
8091 + * HT_CTRL_CFG:
8092 + */
8093 +#define HT_CTRL_CFG                    0x1410
8094 +
8095 +/*
8096 + * SIFS_COST_CFG:
8097 + */
8098 +#define SIFS_COST_CFG                  0x1414
8099 +
8100 +/*
8101 + * RX_PARSER_CFG:
8102 + * Set NAV for all received frames
8103 + */
8104 +#define RX_PARSER_CFG                  0x1418
8105 +
8106 +/*
8107 + * TX_SEC_CNT0:
8108 + */
8109 +#define TX_SEC_CNT0                    0x1500
8110 +
8111 +/*
8112 + * RX_SEC_CNT0:
8113 + */
8114 +#define RX_SEC_CNT0                    0x1504
8115 +
8116 +/*
8117 + * CCMP_FC_MUTE:
8118 + */
8119 +#define CCMP_FC_MUTE                   0x1508
8120 +
8121 +/*
8122 + * TXOP_HLDR_ADDR0:
8123 + */
8124 +#define TXOP_HLDR_ADDR0                        0x1600
8125 +
8126 +/*
8127 + * TXOP_HLDR_ADDR1:
8128 + */
8129 +#define TXOP_HLDR_ADDR1                        0x1604
8130 +
8131 +/*
8132 + * TXOP_HLDR_ET:
8133 + */
8134 +#define TXOP_HLDR_ET                   0x1608
8135 +
8136 +/*
8137 + * QOS_CFPOLL_RA_DW0:
8138 + */
8139 +#define QOS_CFPOLL_RA_DW0              0x160c
8140 +
8141 +/*
8142 + * QOS_CFPOLL_RA_DW1:
8143 + */
8144 +#define QOS_CFPOLL_RA_DW1              0x1610
8145 +
8146 +/*
8147 + * QOS_CFPOLL_QC:
8148 + */
8149 +#define QOS_CFPOLL_QC                  0x1614
8150 +
8151 +/*
8152 + * RX_STA_CNT0: RX PLCP error count & RX CRC error count
8153 + */
8154 +#define RX_STA_CNT0                    0x1700
8155 +#define RX_STA_CNT0_CRC_ERR            FIELD32(0x0000ffff)
8156 +#define RX_STA_CNT0_PHY_ERR            FIELD32(0xffff0000)
8157 +
8158 +/*
8159 + * RX_STA_CNT1: RX False CCA count & RX LONG frame count
8160 + */
8161 +#define RX_STA_CNT1                    0x1704
8162 +#define RX_STA_CNT1_FALSE_CCA          FIELD32(0x0000ffff)
8163 +#define RX_STA_CNT1_PLCP_ERR           FIELD32(0xffff0000)
8164 +
8165 +/*
8166 + * RX_STA_CNT2:
8167 + */
8168 +#define RX_STA_CNT2                    0x1708
8169 +#define RX_STA_CNT2_RX_DUPLI_COUNT     FIELD32(0x0000ffff)
8170 +#define RX_STA_CNT2_RX_FIFO_OVERFLOW   FIELD32(0xffff0000)
8171 +
8172 +/*
8173 + * TX_STA_CNT0: TX Beacon count
8174 + */
8175 +#define TX_STA_CNT0                    0x170c
8176 +#define TX_STA_CNT0_TX_FAIL_COUNT      FIELD32(0x0000ffff)
8177 +#define TX_STA_CNT0_TX_BEACON_COUNT    FIELD32(0xffff0000)
8178 +
8179 +/*
8180 + * TX_STA_CNT1: TX tx count
8181 + */
8182 +#define TX_STA_CNT1                    0x1710
8183 +#define TX_STA_CNT1_TX_SUCCESS         FIELD32(0x0000ffff)
8184 +#define TX_STA_CNT1_TX_RETRANSMIT      FIELD32(0xffff0000)
8185 +
8186 +/*
8187 + * TX_STA_CNT2: TX tx count
8188 + */
8189 +#define TX_STA_CNT2                    0x1714
8190 +#define TX_STA_CNT2_TX_ZERO_LEN_COUNT  FIELD32(0x0000ffff)
8191 +#define TX_STA_CNT2_TX_UNDER_FLOW_COUNT        FIELD32(0xffff0000)
8192 +
8193 +/*
8194 + * TX_STA_FIFO: TX Result for specific PID status fifo register
8195 + */
8196 +#define TX_STA_FIFO                    0x1718
8197 +#define TX_STA_FIFO_B_VALID            FIELD32(0x00000001)
8198 +#define TX_STA_FIFO_PID_TYPE           FIELD32(0x0000001e)
8199 +#define TX_STA_FIFO_TX_SUCCESS         FIELD32(0x00000020)
8200 +#define TX_STA_FIFO_TX_AGGRE           FIELD32(0x00000040)
8201 +#define TX_STA_FIFO_TX_ACK_REQUIRED    FIELD32(0x00000080)
8202 +#define TX_STA_FIFO_WCID               FIELD32(0x0000ff00)
8203 +#define TX_STA_FIFO_SUCCESS_RATE       FIELD32(0xffff0000)
8204 +
8205 +/*
8206 + * TX_AGG_CNT: Debug counter
8207 + */
8208 +#define TX_AGG_CNT                     0x171c
8209 +#define TX_AGG_CNT_NON_AGG_TX_COUNT    FIELD32(0x0000ffff)
8210 +#define TX_AGG_CNT_AGG_TX_COUNT                FIELD32(0xffff0000)
8211 +
8212 +/*
8213 + * TX_AGG_CNT0:
8214 + */
8215 +#define TX_AGG_CNT0                    0x1720
8216 +#define TX_AGG_CNT0_AGG_SIZE_1_COUNT   FIELD32(0x0000ffff)
8217 +#define TX_AGG_CNT0_AGG_SIZE_2_COUNT   FIELD32(0xffff0000)
8218 +
8219 +/*
8220 + * TX_AGG_CNT1:
8221 + */
8222 +#define TX_AGG_CNT1                    0x1724
8223 +#define TX_AGG_CNT1_AGG_SIZE_3_COUNT   FIELD32(0x0000ffff)
8224 +#define TX_AGG_CNT1_AGG_SIZE_4_COUNT   FIELD32(0xffff0000)
8225 +
8226 +/*
8227 + * TX_AGG_CNT2:
8228 + */
8229 +#define TX_AGG_CNT2                    0x1728
8230 +#define TX_AGG_CNT2_AGG_SIZE_5_COUNT   FIELD32(0x0000ffff)
8231 +#define TX_AGG_CNT2_AGG_SIZE_6_COUNT   FIELD32(0xffff0000)
8232 +
8233 +/*
8234 + * TX_AGG_CNT3:
8235 + */
8236 +#define TX_AGG_CNT3                    0x172c
8237 +#define TX_AGG_CNT3_AGG_SIZE_7_COUNT   FIELD32(0x0000ffff)
8238 +#define TX_AGG_CNT3_AGG_SIZE_8_COUNT   FIELD32(0xffff0000)
8239 +
8240 +/*
8241 + * TX_AGG_CNT4:
8242 + */
8243 +#define TX_AGG_CNT4                    0x1730
8244 +#define TX_AGG_CNT4_AGG_SIZE_9_COUNT   FIELD32(0x0000ffff)
8245 +#define TX_AGG_CNT4_AGG_SIZE_10_COUNT  FIELD32(0xffff0000)
8246 +
8247 +/*
8248 + * TX_AGG_CNT5:
8249 + */
8250 +#define TX_AGG_CNT5                    0x1734
8251 +#define TX_AGG_CNT5_AGG_SIZE_11_COUNT  FIELD32(0x0000ffff)
8252 +#define TX_AGG_CNT5_AGG_SIZE_12_COUNT  FIELD32(0xffff0000)
8253 +
8254 +/*
8255 + * TX_AGG_CNT6:
8256 + */
8257 +#define TX_AGG_CNT6                    0x1738
8258 +#define TX_AGG_CNT6_AGG_SIZE_13_COUNT  FIELD32(0x0000ffff)
8259 +#define TX_AGG_CNT6_AGG_SIZE_14_COUNT  FIELD32(0xffff0000)
8260 +
8261 +/*
8262 + * TX_AGG_CNT7:
8263 + */
8264 +#define TX_AGG_CNT7                    0x173c
8265 +#define TX_AGG_CNT7_AGG_SIZE_15_COUNT  FIELD32(0x0000ffff)
8266 +#define TX_AGG_CNT7_AGG_SIZE_16_COUNT  FIELD32(0xffff0000)
8267 +
8268 +/*
8269 + * MPDU_DENSITY_CNT:
8270 + * TX_ZERO_DEL: TX zero length delimiter count
8271 + * RX_ZERO_DEL: RX zero length delimiter count
8272 + */
8273 +#define MPDU_DENSITY_CNT               0x1740
8274 +#define MPDU_DENSITY_CNT_TX_ZERO_DEL   FIELD32(0x0000ffff)
8275 +#define MPDU_DENSITY_CNT_RX_ZERO_DEL   FIELD32(0xffff0000)
8276 +
8277 +/*
8278 + * Security key table memory, base address = 0x1800
8279 + */
8280 +struct hw_pairwise_ta_entry {
8281 +       u8 address[6];
8282 +       u8 reserved[2];
8283 +} __attribute__ ((packed));
8284 +
8285 +struct wcid_entry {
8286 +       u8 rx_ba_bitmat7;
8287 +       u8 rx_ba_bitmat0;
8288 +       u8 mac[6];
8289 +} __attribute__ ((packed));
8290 +
8291 +struct hw_key_entry {
8292 +       u8 key[16];
8293 +       u8 tx_mic[8];
8294 +       u8 rx_mic[8];
8295 +} __attribute__ ((packed));
8296 +
8297 +/*
8298 + * Security key table memory.
8299 + * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry
8300 + * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry
8301 + * PAIRWISE_IVEIV_TABLE_BASE: 8-byte * 256-entry
8302 + * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry
8303 + * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry
8304 + * SHARED_KEY_TABLE_BASE: 32-byte * 16-entry
8305 + * SHARED_KEY_MODE_BASE: 32-byte * 16-entry
8306 + */
8307 +#define MAC_WCID_BASE                  0x1800
8308 +#define PAIRWISE_KEY_TABLE_BASE                0x4000
8309 +#define PAIRWISE_IVEIV_TABLE_BASE      0x6000
8310 +#define MAC_IVEIV_TABLE_BASE           0x6000
8311 +#define MAC_WCID_ATTRIBUTE_BASE                0x6800
8312 +#define SHARED_KEY_TABLE_BASE          0x6c00
8313 +#define SHARED_KEY_MODE_BASE           0x7000
8314 +
8315 +#define SHARED_KEY_ENTRY(__idx) \
8316 +       ( SHARED_KEY_TABLE_BASE + \
8317 +               ((__idx) * sizeof(struct hw_key_entry)) )
8318 +#define SHARED_KEY_MODE_ENTRY(__idx) \
8319 +       ( SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)) )
8320 +#define PAIRWISE_KEY_ENTRY(__idx) \
8321 +       ( PAIRWISE_KEY_TABLE_BASE + \
8322 +               ((__idx) * sizeof(struct hw_key_entry)) )
8323 +
8324 +#define MAC_WCID_ENTRY(__idx) \
8325 +       ( MAC_WCID_BASE + (2 * sizeof(u32) * (__idx)) )
8326 +#define MAC_WCID_ATTR_ENTRY(__idx) \
8327 +       ( MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)) )
8328 +
8329 +/*
8330 + * MAC_WCID_ATTRIBUTE:
8331 + * KEYTAB: 0: shared key table, 1: pairwise key table
8332 + * BSS_IDX: multipleBSS index for the WCID
8333 + */
8334 +#define MAC_WCID_ATTRIBUTE_KEYTAB      FIELD32(0x00000001)
8335 +#define MAC_WCID_ATTRIBUTE_PAIRKEY_MODE        FIELD32(0x0000000e)
8336 +#define MAC_WCID_ATTRIBUTE_BSS_IDX     FIELD32(0x00000070)
8337 +#define MAC_WCID_ATTRIBUTE_RX_WIUDF    FIELD32(0x00000380)
8338 +
8339 +/*
8340 + * SHARED_KEY_MODE:
8341 + */
8342 +#define SHARED_KEY_MODE_BSS0_KEY0      FIELD32(0x00000007)
8343 +#define SHARED_KEY_MODE_BSS0_KEY1      FIELD32(0x00000070)
8344 +#define SHARED_KEY_MODE_BSS0_KEY2      FIELD32(0x00000700)
8345 +#define SHARED_KEY_MODE_BSS0_KEY3      FIELD32(0x00007000)
8346 +#define SHARED_KEY_MODE_BSS1_KEY0      FIELD32(0x00070000)
8347 +#define SHARED_KEY_MODE_BSS1_KEY1      FIELD32(0x00700000)
8348 +#define SHARED_KEY_MODE_BSS1_KEY2      FIELD32(0x07000000)
8349 +#define SHARED_KEY_MODE_BSS1_KEY3      FIELD32(0x70000000)
8350 +
8351 +/*
8352 + * HOST-MCU communication
8353 + */
8354 +
8355 +/*
8356 + * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
8357 + */
8358 +#define H2M_MAILBOX_CSR                        0x7010
8359 +#define H2M_MAILBOX_CSR_ARG0           FIELD32(0x000000ff)
8360 +#define H2M_MAILBOX_CSR_ARG1           FIELD32(0x0000ff00)
8361 +#define H2M_MAILBOX_CSR_CMD_TOKEN      FIELD32(0x00ff0000)
8362 +#define H2M_MAILBOX_CSR_OWNER          FIELD32(0xff000000)
8363 +
8364 +/*
8365 + * H2M_MAILBOX_CID:
8366 + */
8367 +#define H2M_MAILBOX_CID                        0x7014
8368 +
8369 +/*
8370 + * H2M_MAILBOX_STATUS:
8371 + */
8372 +#define H2M_MAILBOX_STATUS             0x701c
8373 +
8374 +/*
8375 + * H2M_INT_SRC:
8376 + */
8377 +#define H2M_INT_SRC                    0x7024
8378 +
8379 +/*
8380 + * H2M_BBP_AGENT:
8381 + */
8382 +#define H2M_BBP_AGENT                  0x7028
8383 +
8384 +/*
8385 + * MCU_LEDCS: LED control for MCU Mailbox.
8386 + */
8387 +#define MCU_LEDCS_LED_MODE             FIELD8(0x1f)
8388 +#define MCU_LEDCS_POLARITY             FIELD8(0x01)
8389 +
8390 +/*
8391 + * HW_CS_CTS_BASE:
8392 + * Carrier-sense CTS frame base address.
8393 + * It's where mac stores carrier-sense frame for carrier-sense function.
8394 + */
8395 +#define HW_CS_CTS_BASE                 0x7700
8396 +
8397 +/*
8398 + * HW_DFS_CTS_BASE:
8399 + * FS CTS frame base address. It's where mac stores CTS frame for DFS.
8400 + */
8401 +#define HW_DFS_CTS_BASE                        0x7780
8402 +
8403 +/*
8404 + * TXRX control registers - base address 0x3000
8405 + */
8406 +
8407 +/*
8408 + * TXRX_CSR1:
8409 + * rt2860b  UNKNOWN reg use R/O Reg Addr 0x77d0 first..
8410 + */
8411 +#define TXRX_CSR1                      0x77d0
8412 +
8413 +/*
8414 + * HW_DEBUG_SETTING_BASE:
8415 + * since NULL frame won't be that long (256 byte)
8416 + * We steal 16 tail bytes to save debugging settings
8417 + */
8418 +#define HW_DEBUG_SETTING_BASE          0x77f0
8419 +#define HW_DEBUG_SETTING_BASE2         0x7770
8420 +
8421 +/*
8422 + * HW_BEACON_BASE
8423 + * In order to support maximum 8 MBSS and its maximum length
8424 + *     is 512 bytes for each beacon
8425 + * Three section discontinue memory segments will be used.
8426 + * 1. The original region for BCN 0~3
8427 + * 2. Extract memory from FCE table for BCN 4~5
8428 + * 3. Extract memory from Pair-wise key table for BCN 6~7
8429 + *    It occupied those memory of wcid 238~253 for BCN 6
8430 + *    and wcid 222~237 for BCN 7
8431 + *
8432 + * IMPORTANT NOTE: Not sure why legacy driver does this,
8433 + * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6.
8434 + */
8435 +#define HW_BEACON_BASE0                        0x7800
8436 +#define HW_BEACON_BASE1                        0x7a00
8437 +#define HW_BEACON_BASE2                        0x7c00
8438 +#define HW_BEACON_BASE3                        0x7e00
8439 +#define HW_BEACON_BASE4                        0x7200
8440 +#define HW_BEACON_BASE5                        0x7400
8441 +#define HW_BEACON_BASE6                        0x5dc0
8442 +#define HW_BEACON_BASE7                        0x5bc0
8443 +
8444 +#define HW_BEACON_OFFSET(__index) \
8445 +       ( ((__index) < 4) ? ( HW_BEACON_BASE0 + (__index * 0x0200) ) : \
8446 +         (((__index) < 6) ? ( HW_BEACON_BASE4 + ((__index - 4) * 0x0200) ) : \
8447 +         (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))) )
8448 +
8449 +/*
8450 + * 8051 firmware image.
8451 + */
8452 +#define FIRMWARE_RT2870                        "rt2870.bin"
8453 +#define FIRMWARE_IMAGE_BASE            0x3000
8454 +
8455 +/*
8456 + * BBP registers.
8457 + * The wordsize of the BBP is 8 bits.
8458 + */
8459 +
8460 +/*
8461 + * BBP 1: TX Antenna
8462 + */
8463 +#define BBP1_TX_POWER                  FIELD8(0x07)
8464 +#define BBP1_TX_ANTENNA                        FIELD8(0x18)
8465 +
8466 +/*
8467 + * BBP 3: RX Antenna
8468 + */
8469 +#define BBP3_RX_ANTENNA                        FIELD8(0x18)
8470 +
8471 +/*
8472 + * RF registers
8473 + */
8474 +
8475 +/*
8476 + * RF 2
8477 + */
8478 +#define RF2_ANTENNA_RX2                        FIELD32(0x00000040)
8479 +#define RF2_ANTENNA_TX1                        FIELD32(0x00004000)
8480 +#define RF2_ANTENNA_RX1                        FIELD32(0x00020000)
8481 +
8482 +/*
8483 + * RF 3
8484 + */
8485 +#define RF3_TXPOWER_G                  FIELD32(0x00003e00)
8486 +#define RF3_TXPOWER_A_7DBM_BOOST       FIELD32(0x00000200)
8487 +#define RF3_TXPOWER_A                  FIELD32(0x00003c00)
8488 +
8489 +/*
8490 + * RF 4
8491 + */
8492 +#define RF4_TXPOWER_G                  FIELD32(0x000007c0)
8493 +#define RF4_TXPOWER_A_7DBM_BOOST       FIELD32(0x00000040)
8494 +#define RF4_TXPOWER_A                  FIELD32(0x00000780)
8495 +#define RF4_FREQ_OFFSET                        FIELD32(0x001f8000)
8496 +#define RF4_BW40                       FIELD32(0x00200000)
8497 +
8498 +/*
8499 + * EEPROM content.
8500 + * The wordsize of the EEPROM is 16 bits.
8501 + */
8502 +
8503 +/*
8504 + * EEPROM Version
8505 + */
8506 +#define EEPROM_VERSION                 0x0001
8507 +#define EEPROM_VERSION_FAE             FIELD16(0x00ff)
8508 +#define EEPROM_VERSION_VERSION         FIELD16(0xff00)
8509 +
8510 +/*
8511 + * HW MAC address.
8512 + */
8513 +#define EEPROM_MAC_ADDR_0              0x0002
8514 +#define EEPROM_MAC_ADDR_BYTE0          FIELD16(0x00ff)
8515 +#define EEPROM_MAC_ADDR_BYTE1          FIELD16(0xff00)
8516 +#define EEPROM_MAC_ADDR1               0x0003
8517 +#define EEPROM_MAC_ADDR_BYTE2          FIELD16(0x00ff)
8518 +#define EEPROM_MAC_ADDR_BYTE3          FIELD16(0xff00)
8519 +#define EEPROM_MAC_ADDR_2              0x0004
8520 +#define EEPROM_MAC_ADDR_BYTE4          FIELD16(0x00ff)
8521 +#define EEPROM_MAC_ADDR_BYTE5          FIELD16(0xff00)
8522 +
8523 +/*
8524 + * EEPROM ANTENNA config
8525 + * RXPATH: 1: 1R, 2: 2R, 3: 3R
8526 + * TXPATH: 1: 1T, 2: 2T
8527 + */
8528 +#define        EEPROM_ANTENNA                  0x001a
8529 +#define EEPROM_ANTENNA_RXPATH          FIELD16(0x000f)
8530 +#define EEPROM_ANTENNA_TXPATH          FIELD16(0x00f0)
8531 +#define EEPROM_ANTENNA_RF_TYPE         FIELD16(0x0f00)
8532 +
8533 +/*
8534 + * EEPROM NIC config
8535 + * CARDBUS_ACCEL: 0 - enable, 1 - disable
8536 + */
8537 +#define        EEPROM_NIC                      0x001b
8538 +#define EEPROM_NIC_HW_RADIO            FIELD16(0x0001)
8539 +#define EEPROM_NIC_DYNAMIC_TX_AGC      FIELD16(0x0002)
8540 +#define EEPROM_NIC_EXTERNAL_LNA_BG     FIELD16(0x0004)
8541 +#define EEPROM_NIC_EXTERNAL_LNA_A      FIELD16(0x0008)
8542 +#define EEPROM_NIC_CARDBUS_ACCEL       FIELD16(0x0010)
8543 +#define EEPROM_NIC_BW40M_SB_BG         FIELD16(0x0020)
8544 +#define EEPROM_NIC_BW40M_SB_A          FIELD16(0x0040)
8545 +#define EEPROM_NIC_WPS_PBC             FIELD16(0x0080)
8546 +#define EEPROM_NIC_BW40M_BG            FIELD16(0x0100)
8547 +#define EEPROM_NIC_BW40M_A             FIELD16(0x0200)
8548 +
8549 +/*
8550 + * EEPROM frequency
8551 + */
8552 +#define        EEPROM_FREQ                     0x001d
8553 +#define EEPROM_FREQ_OFFSET             FIELD16(0x00ff)
8554 +#define EEPROM_FREQ_LED_MODE           FIELD16(0x7f00)
8555 +#define EEPROM_FREQ_LED_POLARITY       FIELD16(0x1000)
8556 +
8557 +/*
8558 + * EEPROM LED
8559 + * POLARITY_RDY_G: Polarity RDY_G setting.
8560 + * POLARITY_RDY_A: Polarity RDY_A setting.
8561 + * POLARITY_ACT: Polarity ACT setting.
8562 + * POLARITY_GPIO_0: Polarity GPIO0 setting.
8563 + * POLARITY_GPIO_1: Polarity GPIO1 setting.
8564 + * POLARITY_GPIO_2: Polarity GPIO2 setting.
8565 + * POLARITY_GPIO_3: Polarity GPIO3 setting.
8566 + * POLARITY_GPIO_4: Polarity GPIO4 setting.
8567 + * LED_MODE: Led mode.
8568 + */
8569 +#define EEPROM_LED1                    0x001e
8570 +#define EEPROM_LED2                    0x001f
8571 +#define EEPROM_LED3                    0x0020
8572 +#define EEPROM_LED_POLARITY_RDY_BG     FIELD16(0x0001)
8573 +#define EEPROM_LED_POLARITY_RDY_A      FIELD16(0x0002)
8574 +#define EEPROM_LED_POLARITY_ACT                FIELD16(0x0004)
8575 +#define EEPROM_LED_POLARITY_GPIO_0     FIELD16(0x0008)
8576 +#define EEPROM_LED_POLARITY_GPIO_1     FIELD16(0x0010)
8577 +#define EEPROM_LED_POLARITY_GPIO_2     FIELD16(0x0020)
8578 +#define EEPROM_LED_POLARITY_GPIO_3     FIELD16(0x0040)
8579 +#define EEPROM_LED_POLARITY_GPIO_4     FIELD16(0x0080)
8580 +#define EEPROM_LED_LED_MODE            FIELD16(0x1f00)
8581 +
8582 +/*
8583 + * EEPROM LNA
8584 + */
8585 +#define EEPROM_LNA                     0x0022
8586 +#define EEPROM_LNA_BG                  FIELD16(0x00ff)
8587 +#define EEPROM_LNA_A0                  FIELD16(0xff00)
8588 +
8589 +/*
8590 + * EEPROM RSSI BG offset
8591 + */
8592 +#define EEPROM_RSSI_BG                 0x0023
8593 +#define EEPROM_RSSI_BG_OFFSET0         FIELD16(0x00ff)
8594 +#define EEPROM_RSSI_BG_OFFSET1         FIELD16(0xff00)
8595 +
8596 +/*
8597 + * EEPROM RSSI BG2 offset
8598 + */
8599 +#define EEPROM_RSSI_BG2                        0x0024
8600 +#define EEPROM_RSSI_BG2_OFFSET2                FIELD16(0x00ff)
8601 +#define EEPROM_RSSI_BG2_LNA_A1         FIELD16(0xff00)
8602 +
8603 +/*
8604 + * EEPROM RSSI A offset
8605 + */
8606 +#define EEPROM_RSSI_A                  0x0025
8607 +#define EEPROM_RSSI_A_OFFSET0          FIELD16(0x00ff)
8608 +#define EEPROM_RSSI_A_OFFSET1          FIELD16(0xff00)
8609 +
8610 +/*
8611 + * EEPROM RSSI A2 offset
8612 + */
8613 +#define EEPROM_RSSI_A2                 0x0026
8614 +#define EEPROM_RSSI_A2_OFFSET2         FIELD16(0x00ff)
8615 +#define EEPROM_RSSI_A2_LNA_A2          FIELD16(0xff00)
8616 +
8617 +/*
8618 + * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power.
8619 + *     This is delta in 40MHZ.
8620 + * VALUE: Tx Power dalta value (MAX=4)
8621 + * TYPE: 1: Plus the delta value, 0: minus the delta value
8622 + * TXPOWER: Enable:
8623 + */
8624 +#define EEPROM_TXPOWER_DELTA           0x0028
8625 +#define EEPROM_TXPOWER_DELTA_VALUE     FIELD16(0x003f)
8626 +#define EEPROM_TXPOWER_DELTA_TYPE      FIELD16(0x0040)
8627 +#define EEPROM_TXPOWER_DELTA_TXPOWER   FIELD16(0x0080)
8628 +
8629 +/*
8630 + * EEPROM TXPOWER 802.11BG
8631 + */
8632 +#define        EEPROM_TXPOWER_BG1              0x0029
8633 +#define        EEPROM_TXPOWER_BG2              0x0030
8634 +#define EEPROM_TXPOWER_BG_SIZE         7
8635 +#define EEPROM_TXPOWER_BG_1            FIELD16(0x00ff)
8636 +#define EEPROM_TXPOWER_BG_2            FIELD16(0xff00)
8637 +
8638 +/*
8639 + * EEPROM TXPOWER 802.11A
8640 + */
8641 +#define EEPROM_TXPOWER_A1              0x003c
8642 +#define EEPROM_TXPOWER_A2              0x0053
8643 +#define EEPROM_TXPOWER_A_SIZE          6
8644 +#define EEPROM_TXPOWER_A_1             FIELD16(0x00ff)
8645 +#define EEPROM_TXPOWER_A_2             FIELD16(0xff00)
8646 +
8647 +/*
8648 + * EEPROM TXpower byrate: 20MHZ power
8649 + */
8650 +#define EEPROM_TXPOWER_BYRATE          0x006f
8651 +
8652 +/*
8653 + * EEPROM BBP.
8654 + */
8655 +#define        EEPROM_BBP_START                0x0078
8656 +#define EEPROM_BBP_SIZE                        16
8657 +#define EEPROM_BBP_VALUE               FIELD16(0x00ff)
8658 +#define EEPROM_BBP_REG_ID              FIELD16(0xff00)
8659 +
8660 +/*
8661 + * MCU mailbox commands.
8662 + */
8663 +#define MCU_SLEEP                      0x30
8664 +#define MCU_WAKEUP                     0x31
8665 +#define MCU_LED                                0x50
8666 +#define MCU_LED_STRENGTH               0x51
8667 +#define MCU_LED_1                      0x52
8668 +#define MCU_LED_2                      0x53
8669 +#define MCU_LED_3                      0x54
8670 +#define MCU_RADAR                      0x60
8671 +#define MCU_BOOT_SIGNAL                        0x72
8672 +
8673 +/*
8674 + * DMA descriptor defines.
8675 + */
8676 +#define TXD_DESC_SIZE                  ( 4 * sizeof(__le32) )
8677 +#define TXINFO_DESC_SIZE               ( 1 * sizeof(__le32) )
8678 +#define TXWI_DESC_SIZE                 ( 4 * sizeof(__le32) )
8679 +#define RXD_DESC_SIZE                  ( 1 * sizeof(__le32) )
8680 +#define RXWI_DESC_SIZE                 ( 4 * sizeof(__le32) )
8681 +
8682 +/*
8683 + * TX descriptor format for TX, PRIO and Beacon Ring.
8684 + */
8685 +
8686 +/*
8687 + * Word0
8688 + */
8689 +#define TXD_W0_SD_PTR0                 FIELD32(0xffffffff)
8690 +
8691 +/*
8692 + * Word1
8693 + */
8694 +#define TXD_W1_SD_LEN1                 FIELD32(0x00003fff)
8695 +#define TXD_W1_LAST_SEC1               FIELD32(0x00004000)
8696 +#define TXD_W1_BURST                   FIELD32(0x00008000)
8697 +#define TXD_W1_SD_LEN0                 FIELD32(0x3fff0000)
8698 +#define TXD_W1_LAST_SEC0               FIELD32(0x40000000)
8699 +#define TXD_W1_DMA_DONE                        FIELD32(0x80000000)
8700 +
8701 +/*
8702 + * Word2
8703 + */
8704 +#define TXD_W2_SD_PTR1                 FIELD32(0xffffffff)
8705 +
8706 +/*
8707 + * Word3
8708 + * WIV: Wireless Info Valid. 1: Driver filled WI,  0: DMA needs to copy WI
8709 + * QSEL: Select on-chip FIFO ID for 2nd-stage output scheduler.
8710 + *       0:MGMT, 1:HCCA 2:EDCA
8711 + */
8712 +#define TXD_W3_WIV                     FIELD32(0x01000000)
8713 +#define TXD_W3_QSEL                    FIELD32(0x06000000)
8714 +#define TXD_W3_TCO                     FIELD32(0x20000000)
8715 +#define TXD_W3_UCO                     FIELD32(0x40000000)
8716 +#define TXD_W3_ICO                     FIELD32(0x80000000)
8717 +
8718 +/*
8719 + * TX Info structure
8720 + */
8721 +
8722 +/*
8723 + * Word0
8724 + * WIV: Wireless Info Valid. 1: Driver filled WI,  0: DMA needs to copy WI
8725 + * QSEL: Select on-chip FIFO ID for 2nd-stage output scheduler.
8726 + *       0:MGMT, 1:HCCA 2:EDCA
8727 + * USB_DMA_NEXT_VALID: Used ONLY in USB bulk Aggregation, NextValid
8728 + * DMA_TX_BURST: used ONLY in USB bulk Aggregation.
8729 + *               Force USB DMA transmit frame from current selected endpoint
8730 + */
8731 +#define TXINFO_W0_USB_DMA_TX_PKT_LEN   FIELD32(0x0000ffff)
8732 +#define TXINFO_W0_WIV                  FIELD32(0x01000000)
8733 +#define TXINFO_W0_QSEL                 FIELD32(0x06000000)
8734 +#define TXINFO_W0_USB_DMA_NEXT_VALID   FIELD32(0x40000000)
8735 +#define TXINFO_W0_USB_DMA_TX_BURST     FIELD32(0x80000000)
8736 +
8737 +/*
8738 + * TX WI structure
8739 + */
8740 +
8741 +/*
8742 + * Word0
8743 + * FRAG: 1 To inform TKIP engine this is a fragment.
8744 + * MIMO_PS: The remote peer is in dynamic MIMO-PS mode
8745 + * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs
8746 + * BW: Channel bandwidth 20MHz or 40 MHz
8747 + * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED
8748 + */
8749 +#define TXWI_W0_FRAG                   FIELD32(0x00000001)
8750 +#define TXWI_W0_MIMO_PS                        FIELD32(0x00000002)
8751 +#define TXWI_W0_CF_ACK                 FIELD32(0x00000004)
8752 +#define TXWI_W0_TS                     FIELD32(0x00000008)
8753 +#define TXWI_W0_AMPDU                  FIELD32(0x00000010)
8754 +#define TXWI_W0_MPDU_DENSITY           FIELD32(0x000000e0)
8755 +#define TXWI_W0_TX_OP                  FIELD32(0x00000300)
8756 +#define TXWI_W0_MCS                    FIELD32(0x007f0000)
8757 +#define TXWI_W0_BW                     FIELD32(0x00800000)
8758 +#define TXWI_W0_SHORT_GI               FIELD32(0x01000000)
8759 +#define TXWI_W0_STBC                   FIELD32(0x06000000)
8760 +#define TXWI_W0_IFS                    FIELD32(0x08000000)
8761 +#define TXWI_W0_PHYMODE                        FIELD32(0xc0000000)
8762 +
8763 +/*
8764 + * Word1
8765 + */
8766 +#define TXWI_W1_ACK                    FIELD32(0x00000001)
8767 +#define TXWI_W1_NSEQ                   FIELD32(0x00000002)
8768 +#define TXWI_W1_BW_WIN_SIZE            FIELD32(0x000000fc)
8769 +#define TXWI_W1_WIRELESS_CLI_ID                FIELD32(0x0000ff00)
8770 +#define TXWI_W1_MPDU_TOTAL_BYTE_COUNT  FIELD32(0x0fff0000)
8771 +#define TXWI_W1_PACKETID               FIELD32(0xf0000000)
8772 +
8773 +/*
8774 + * Word2
8775 + */
8776 +#define TXWI_W2_IV                     FIELD32(0xffffffff)
8777 +
8778 +/*
8779 + * Word3
8780 + */
8781 +#define TXWI_W3_EIV                    FIELD32(0xffffffff)
8782 +
8783 +/*
8784 + * RX descriptor format for RX Ring.
8785 + */
8786 +
8787 +/*
8788 + * Word0
8789 + * UNICAST_TO_ME: This RX frame is unicast to me.
8790 + * MULTICAST: This is a multicast frame.
8791 + * BROADCAST: This is a broadcast frame.
8792 + * MY_BSS: this frame belongs to the same BSSID.
8793 + * CRC_ERROR: CRC error.
8794 + * CIPHER_ERROR: 0: decryption okay, 1:ICV error, 2:MIC error, 3:KEY not valid.
8795 + * AMSDU: rx with 802.3 header, not 802.11 header.
8796 + */
8797 +
8798 +#define RXD_W0_BA                      FIELD32(0x00000001)
8799 +#define RXD_W0_DATA                    FIELD32(0x00000002)
8800 +#define RXD_W0_NULLDATA                        FIELD32(0x00000004)
8801 +#define RXD_W0_FRAG                    FIELD32(0x00000008)
8802 +#define RXD_W0_UNICAST_TO_ME           FIELD32(0x00000010)
8803 +#define RXD_W0_MULTICAST               FIELD32(0x00000020)
8804 +#define RXD_W0_BROADCAST               FIELD32(0x00000040)
8805 +#define RXD_W0_MY_BSS                  FIELD32(0x00000080)
8806 +#define RXD_W0_CRC_ERROR               FIELD32(0x00000100)
8807 +#define RXD_W0_CIPHER_ERROR            FIELD32(0x00000600)
8808 +#define RXD_W0_AMSDU                   FIELD32(0x00000800)
8809 +#define RXD_W0_HTC                     FIELD32(0x00001000)
8810 +#define RXD_W0_RSSI                    FIELD32(0x00002000)
8811 +#define RXD_W0_L2PAD                   FIELD32(0x00004000)
8812 +#define RXD_W0_AMPDU                   FIELD32(0x00008000)
8813 +#define RXD_W0_DECRYPTED               FIELD32(0x00010000)
8814 +#define RXD_W0_PLCP_RSSI               FIELD32(0x00020000)
8815 +#define RXD_W0_CIPHER_ALG              FIELD32(0x00040000)
8816 +#define RXD_W0_LAST_AMSDU              FIELD32(0x00080000)
8817 +#define RXD_W0_PLCP_SIGNAL             FIELD32(0xfff00000)
8818 +
8819 +/*
8820 + * RX WI structure
8821 + */
8822 +
8823 +/*
8824 + * Word0
8825 + */
8826 +#define RXWI_W0_WIRELESS_CLI_ID                FIELD32(0x000000ff)
8827 +#define RXWI_W0_KEY_INDEX              FIELD32(0x00000300)
8828 +#define RXWI_W0_BSSID                  FIELD32(0x00001c00)
8829 +#define RXWI_W0_UDF                    FIELD32(0x0000e000)
8830 +#define RXWI_W0_MPDU_TOTAL_BYTE_COUNT  FIELD32(0x0fff0000)
8831 +#define RXWI_W0_TID                    FIELD32(0xf0000000)
8832 +
8833 +/*
8834 + * Word1
8835 + */
8836 +#define RXWI_W1_FRAG                   FIELD32(0x0000000f)
8837 +#define RXWI_W1_SEQUENCE               FIELD32(0x0000fff0)
8838 +#define RXWI_W1_MCS                    FIELD32(0x007f0000)
8839 +#define RXWI_W1_BW                     FIELD32(0x00800000)
8840 +#define RXWI_W1_SHORT_GI               FIELD32(0x01000000)
8841 +#define RXWI_W1_STBC                   FIELD32(0x06000000)
8842 +#define RXWI_W1_PHYMODE                        FIELD32(0xc0000000)
8843 +
8844 +/*
8845 + * Word2
8846 + */
8847 +#define RXWI_W2_RSSI0                  FIELD32(0x000000ff)
8848 +#define RXWI_W2_RSSI1                  FIELD32(0x0000ff00)
8849 +#define RXWI_W2_RSSI2                  FIELD32(0x00ff0000)
8850 +
8851 +/*
8852 + * Word3
8853 + */
8854 +#define RXWI_W3_SNR0                   FIELD32(0x000000ff)
8855 +#define RXWI_W3_SNR1                   FIELD32(0x0000ff00)
8856 +
8857 +/*
8858 + * Macro's for converting txpower from EEPROM to mac80211 value
8859 + * and from mac80211 value to register value.
8860 + */
8861 +#define MIN_G_TXPOWER  0
8862 +#define MIN_A_TXPOWER  -7
8863 +#define MAX_G_TXPOWER  31
8864 +#define MAX_A_TXPOWER  15
8865 +#define DEFAULT_TXPOWER        5
8866 +
8867 +#define TXPOWER_G_FROM_DEV(__txpower) \
8868 +       ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
8869 +
8870 +#define TXPOWER_G_TO_DEV(__txpower) \
8871 +       clamp_t(char, __txpower, MIN_G_TXPOWER, MAX_G_TXPOWER)
8872 +
8873 +#define TXPOWER_A_FROM_DEV(__txpower) \
8874 +       ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
8875 +
8876 +#define TXPOWER_A_TO_DEV(__txpower) \
8877 +       clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER)
8878 +
8879 +#endif /* RT2800USB_H */
8880 diff --git a/drivers/net/wireless/rt2x00/rt2x00.h b/drivers/net/wireless/rt2x00/rt2x00.h
8881 index 780ba73..f462424 100644
8882 --- a/drivers/net/wireless/rt2x00/rt2x00.h
8883 +++ b/drivers/net/wireless/rt2x00/rt2x00.h
8884 @@ -107,6 +107,7 @@
8885   */
8886  #define ACK_SIZE               14
8887  #define IEEE80211_HEADER       24
8888 +#define AGGREGATION_SIZE       3840
8889  #define PLCP                   48
8890  #define BEACON                 100
8891  #define PREAMBLE               144
8892 @@ -137,6 +138,11 @@ struct rt2x00_chip {
8893  #define RT2561         0x0302
8894  #define RT2661         0x0401
8895  #define RT2571         0x1300
8896 +#define RT2860         0x0601  /* 2.4GHz PCI/CB */
8897 +#define RT2860D                0x0681  /* 2.4GHz, 5GHz PCI/CB */
8898 +#define RT2890         0x0701  /* 2.4GHz PCIe */
8899 +#define RT2890D                0x0781  /* 2.4GHz, 5GHz PCIe */
8900 +#define RT2870         0x1600
8901
8902         u16 rf;
8903         u32 rev;
8904 diff --git a/drivers/net/wireless/rt2x00/rt2x00dev.c b/drivers/net/wireless/rt2x00/rt2x00dev.c
8905 index 7fc1d76..853cc51 100644
8906 --- a/drivers/net/wireless/rt2x00/rt2x00dev.c
8907 +++ b/drivers/net/wireless/rt2x00/rt2x00dev.c
8908 @@ -659,7 +659,9 @@ void rt2x00lib_rxdone(struct rt2x00_dev *rt2x00dev,
8909                 if (((rxdesc.dev_flags & RXDONE_SIGNAL_PLCP) &&
8910                      (rate->plcp == rxdesc.signal)) ||
8911                     ((rxdesc.dev_flags & RXDONE_SIGNAL_BITRATE) &&
8912 -                     (rate->bitrate == rxdesc.signal))) {
8913 +                     (rate->bitrate == rxdesc.signal)) ||
8914 +                   ((rxdesc.dev_flags & RXDONE_SIGNAL_MCS) &&
8915 +                     (rate->mcs == rxdesc.signal))) {
8916                         idx = i;
8917                         break;
8918                 }
8919 @@ -691,6 +693,7 @@ void rt2x00lib_rxdone(struct rt2x00_dev *rt2x00dev,
8920         rx_status->qual =
8921             rt2x00lib_calculate_link_signal(rt2x00dev, rxdesc.rssi);
8922         rx_status->signal = rxdesc.rssi;
8923 +       rx_status->noise = rxdesc.noise;
8924         rx_status->flag = rxdesc.flags;
8925         rx_status->antenna = rt2x00dev->link.ant.active.rx;
8926
8927 @@ -722,72 +725,84 @@ const struct rt2x00_rate rt2x00_supported_rates[12] = {
8928                 .bitrate = 10,
8929                 .ratemask = BIT(0),
8930                 .plcp = 0x00,
8931 +               .mcs = RATE_MCS(RATE_MODE_CCK, 0),
8932         },
8933         {
8934                 .flags = DEV_RATE_CCK | DEV_RATE_SHORT_PREAMBLE,
8935                 .bitrate = 20,
8936                 .ratemask = BIT(1),
8937                 .plcp = 0x01,
8938 +               .mcs = RATE_MCS(RATE_MODE_CCK, 1),
8939         },
8940         {
8941                 .flags = DEV_RATE_CCK | DEV_RATE_SHORT_PREAMBLE,
8942                 .bitrate = 55,
8943                 .ratemask = BIT(2),
8944                 .plcp = 0x02,
8945 +               .mcs = RATE_MCS(RATE_MODE_CCK, 2),
8946         },
8947         {
8948                 .flags = DEV_RATE_CCK | DEV_RATE_SHORT_PREAMBLE,
8949                 .bitrate = 110,
8950                 .ratemask = BIT(3),
8951                 .plcp = 0x03,
8952 +               .mcs = RATE_MCS(RATE_MODE_CCK, 3),
8953         },
8954         {
8955                 .flags = DEV_RATE_OFDM,
8956                 .bitrate = 60,
8957                 .ratemask = BIT(4),
8958                 .plcp = 0x0b,
8959 +               .mcs = RATE_MCS(RATE_MODE_OFDM, 0),
8960         },
8961         {
8962                 .flags = DEV_RATE_OFDM,
8963                 .bitrate = 90,
8964                 .ratemask = BIT(5),
8965                 .plcp = 0x0f,
8966 +               .mcs = RATE_MCS(RATE_MODE_OFDM, 1),
8967         },
8968         {
8969                 .flags = DEV_RATE_OFDM,
8970                 .bitrate = 120,
8971                 .ratemask = BIT(6),
8972                 .plcp = 0x0a,
8973 +               .mcs = RATE_MCS(RATE_MODE_OFDM, 2),
8974         },
8975         {
8976                 .flags = DEV_RATE_OFDM,
8977                 .bitrate = 180,
8978                 .ratemask = BIT(7),
8979                 .plcp = 0x0e,
8980 +               .mcs = RATE_MCS(RATE_MODE_OFDM, 3),
8981         },
8982         {
8983                 .flags = DEV_RATE_OFDM,
8984                 .bitrate = 240,
8985                 .ratemask = BIT(8),
8986                 .plcp = 0x09,
8987 +               .mcs = RATE_MCS(RATE_MODE_OFDM, 4),
8988         },
8989         {
8990                 .flags = DEV_RATE_OFDM,
8991                 .bitrate = 360,
8992                 .ratemask = BIT(9),
8993                 .plcp = 0x0d,
8994 +               .mcs = RATE_MCS(RATE_MODE_OFDM, 5),
8995         },
8996         {
8997                 .flags = DEV_RATE_OFDM,
8998                 .bitrate = 480,
8999                 .ratemask = BIT(10),
9000                 .plcp = 0x08,
9001 +               .mcs = RATE_MCS(RATE_MODE_OFDM, 6),
9002         },
9003         {
9004                 .flags = DEV_RATE_OFDM,
9005                 .bitrate = 540,
9006                 .ratemask = BIT(11),
9007                 .plcp = 0x0c,
9008 +               .mcs = RATE_MCS(RATE_MODE_OFDM, 7),
9009         },
9010  };
9011
9012 diff --git a/drivers/net/wireless/rt2x00/rt2x00lib.h b/drivers/net/wireless/rt2x00/rt2x00lib.h
9013 index 9399733..b6aa417 100644
9014 --- a/drivers/net/wireless/rt2x00/rt2x00lib.h
9015 +++ b/drivers/net/wireless/rt2x00/rt2x00lib.h
9016 @@ -48,6 +48,7 @@ struct rt2x00_rate {
9017         unsigned short ratemask;
9018
9019         unsigned short plcp;
9020 +       unsigned short mcs;
9021  };
9022
9023  extern const struct rt2x00_rate rt2x00_supported_rates[12];
9024 @@ -68,6 +69,9 @@ static inline int rt2x00_get_rate_preamble(const u16 hw_value)
9025         return (hw_value & 0xff00);
9026  }
9027
9028 +#define RATE_MCS(__mode, __mcs) \
9029 +       ( (((__mode) & 0x00ff) << 8) | ((__mcs) & 0x00ff) )
9030 +
9031  /*
9032   * Radio control handlers.
9033   */
9034 diff --git a/drivers/net/wireless/rt2x00/rt2x00queue.c b/drivers/net/wireless/rt2x00/rt2x00queue.c
9035 index b8de9d2..effe93e 100644
9036 --- a/drivers/net/wireless/rt2x00/rt2x00queue.c
9037 +++ b/drivers/net/wireless/rt2x00/rt2x00queue.c
9038 @@ -303,6 +303,19 @@ static void rt2x00queue_create_tx_descriptor(struct queue_entry *entry,
9039         }
9040
9041         /*
9042 +        * Check HT properties for this frame.
9043 +        */
9044 +       if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
9045 +               __set_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags);
9046 +       if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ)
9047 +               __set_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags);
9048 +
9049 +       txdesc->ba_size = 0; /* FIXME: What value is needed? */
9050 +       txdesc->mpdu_density = 0; /* FIXME: What value is needed? */
9051 +       txdesc->stbc = 0;
9052 +       txdesc->mcs = 33; /* Let hardware handle this */
9053 +
9054 +       /*
9055          * PLCP setup
9056          * Length calculation depends on OFDM/CCK rate.
9057          */
9058 @@ -342,6 +355,20 @@ static void rt2x00queue_create_tx_descriptor(struct queue_entry *entry,
9059                 if (rt2x00_get_rate_preamble(rate->hw_value))
9060                         txdesc->signal |= 0x08;
9061         }
9062 +
9063 +       /*
9064 +        * Determine CCK/OFDM/HT rate mode
9065 +        */
9066 +       txdesc->rate_mode = TXRATE_MODE_CCK;
9067 +       if (hwrate->flags & DEV_RATE_OFDM)
9068 +               txdesc->rate_mode = TXRATE_MODE_OFDM;
9069 +       if (tx_info->control.rates[0].flags & IEEE80211_TX_RC_MCS)
9070 +               txdesc->rate_mode = TXRATE_MODE_HTMIX;
9071 +       if (tx_info->control.rates[0].flags & IEEE80211_TX_RC_GREEN_FIELD)
9072 +               txdesc->rate_mode = TXRATE_MODE_GREENFIELD;
9073 +
9074 +       if (tx_info->control.rates[0].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
9075 +               __set_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags);
9076  }
9077
9078  static void rt2x00queue_write_tx_descriptor(struct queue_entry *entry,
9079 diff --git a/drivers/net/wireless/rt2x00/rt2x00queue.h b/drivers/net/wireless/rt2x00/rt2x00queue.h
9080 index 2e99ab5..1772cdd 100644
9081 --- a/drivers/net/wireless/rt2x00/rt2x00queue.h
9082 +++ b/drivers/net/wireless/rt2x00/rt2x00queue.h
9083 @@ -147,12 +147,14 @@ static inline struct skb_frame_desc* get_skb_frame_desc(struct sk_buff *skb)
9084   *
9085   * @RXDONE_SIGNAL_PLCP: Signal field contains the plcp value.
9086   * @RXDONE_SIGNAL_BITRATE: Signal field contains the bitrate value.
9087 + * @RXDONE_SIGNAL_MCS: Signal field contains the mcs value.
9088   * @RXDONE_MY_BSS: Does this frame originate from device's BSS.
9089   */
9090  enum rxdone_entry_desc_flags {
9091         RXDONE_SIGNAL_PLCP = 1 << 0,
9092         RXDONE_SIGNAL_BITRATE = 1 << 1,
9093 -       RXDONE_MY_BSS = 1 << 2,
9094 +       RXDONE_SIGNAL_MCS = 1 << 2,
9095 +       RXDONE_MY_BSS = 1 << 3,
9096  };
9097
9098  /**
9099 @@ -163,6 +165,7 @@ enum rxdone_entry_desc_flags {
9100   * @timestamp: RX Timestamp
9101   * @signal: Signal of the received frame.
9102   * @rssi: RSSI of the received frame.
9103 + * @noise: Measured noise during frame reception.
9104   * @size: Data size of the received frame.
9105   * @flags: MAC80211 receive flags (See &enum mac80211_rx_flags).
9106   * @dev_flags: Ralink receive flags (See &enum rxdone_entry_desc_flags).
9107 @@ -176,6 +179,7 @@ struct rxdone_entry_desc {
9108         u64 timestamp;
9109         int signal;
9110         int rssi;
9111 +       int noise;
9112         int size;
9113         int flags;
9114         int dev_flags;
9115 @@ -234,6 +238,9 @@ struct txdone_entry_desc {
9116   * @ENTRY_TXD_ENCRYPT_PAIRWISE: Use pairwise key table (instead of shared).
9117   * @ENTRY_TXD_ENCRYPT_IV: Generate IV/EIV in hardware.
9118   * @ENTRY_TXD_ENCRYPT_MMIC: Generate MIC in hardware.
9119 + * @ENTRY_TXD_HT_AMPDU: This frame is part of an AMPDU.
9120 + * @ENTRY_TXD_HT_BW_40: Use 40MHz Bandwidth.
9121 + * @ENTRY_TXD_HT_SHORT_GI: Use short GI.
9122   */
9123  enum txentry_desc_flags {
9124         ENTRY_TXD_RTS_FRAME,
9125 @@ -250,6 +257,9 @@ enum txentry_desc_flags {
9126         ENTRY_TXD_ENCRYPT_PAIRWISE,
9127         ENTRY_TXD_ENCRYPT_IV,
9128         ENTRY_TXD_ENCRYPT_MMIC,
9129 +       ENTRY_TXD_HT_AMPDU,
9130 +       ENTRY_TXD_HT_BW_40,
9131 +       ENTRY_TXD_HT_SHORT_GI,
9132  };
9133
9134  /**
9135 @@ -263,6 +273,11 @@ enum txentry_desc_flags {
9136   * @length_low: PLCP length low word.
9137   * @signal: PLCP signal.
9138   * @service: PLCP service.
9139 + * @msc: MCS.
9140 + * @stbc: STBC.
9141 + * @ba_size: BA size.
9142 + * @rate_mode: Rate mode (CCK, OFDM, HT).
9143 + * @mpdu_density: MDPU density.
9144   * @retry_limit: Max number of retries.
9145   * @aifs: AIFS value.
9146   * @ifs: IFS value.
9147 @@ -282,6 +297,12 @@ struct txentry_desc {
9148         u16 signal;
9149         u16 service;
9150
9151 +       u16 mcs;
9152 +       u16 stbc;
9153 +       u16 ba_size;
9154 +       u16 rate_mode;
9155 +       u16 mpdu_density;
9156 +
9157         short retry_limit;
9158         short aifs;
9159         short ifs;
9160 diff --git a/drivers/net/wireless/rt2x00/rt2x00reg.h b/drivers/net/wireless/rt2x00/rt2x00reg.h
9161 index c2fba7c..52cc166 100644
9162 --- a/drivers/net/wireless/rt2x00/rt2x00reg.h
9163 +++ b/drivers/net/wireless/rt2x00/rt2x00reg.h
9164 @@ -67,6 +67,16 @@ enum tsf_sync {
9165  };
9166
9167  /*
9168 + * TX frame rate mode
9169 + */
9170 +enum txrate_mode {
9171 +       TXRATE_MODE_CCK = 0,
9172 +       TXRATE_MODE_OFDM = 1,
9173 +       TXRATE_MODE_HTMIX = 2,
9174 +       TXRATE_MODE_GREENFIELD = 3,
9175 +};
9176 +
9177 +/*
9178   * Device states
9179   */
9180  enum dev_state {
9181 @@ -125,6 +135,16 @@ enum cipher {
9182  };
9183
9184  /*
9185 + * Rate modulations for 802.11n
9186 + */
9187 +enum rate_modulation {
9188 +       RATE_MODE_CCK = 0,
9189 +       RATE_MODE_OFDM = 1,
9190 +       RATE_MODE_HT_MIX = 2,
9191 +       RATE_MODE_HT_GREENFIELD = 3,
9192 +};
9193 +
9194 +/*
9195   * Register handlers.
9196   * We store the position of a register field inside a field structure,
9197   * This will simplify the process of setting and reading a certain field