package/kernel/mac80211/patches/300-pending_work.patch

   1 --- a/drivers/net/wireless/ath/ath10k/mac.c
   2 +++ b/drivers/net/wireless/ath/ath10k/mac.c
   3 @@ -1351,12 +1351,12 @@ static int ath10k_update_channel_list(st
   4                         ch->allow_vht = true;
   5
   6                         ch->allow_ibss =
   7 -                               !(channel->flags & IEEE80211_CHAN_NO_IBSS);
   8 +                               !(channel->flags & IEEE80211_CHAN_NO_IR);
   9
  10                         ch->ht40plus =
  11                                 !(channel->flags & IEEE80211_CHAN_NO_HT40PLUS);
  12
  13 -                       passive = channel->flags & IEEE80211_CHAN_PASSIVE_SCAN;
  14 +                       passive = channel->flags & IEEE80211_CHAN_NO_IR;
  15                         ch->passive = passive;
  16
  17                         ch->freq = channel->center_freq;
  18 --- a/drivers/net/wireless/ath/ath9k/Kconfig
  19 +++ b/drivers/net/wireless/ath/ath9k/Kconfig
  20 @@ -90,7 +90,7 @@ config ATH9K_DFS_CERTIFIED
  21
  22  config ATH9K_TX99
  23         bool "Atheros ath9k TX99 testing support"
  24 -       depends on CFG80211_CERTIFICATION_ONUS
  25 +       depends on ATH9K_DEBUGFS && CFG80211_CERTIFICATION_ONUS
  26         default n
  27         ---help---
  28           Say N. This should only be enabled on systems undergoing
  29 @@ -108,6 +108,14 @@ config ATH9K_TX99
  30           be evaluated to meet the RF exposure limits set forth in the
  31           governmental SAR regulations.
  32
  33 +config ATH9K_WOW
  34 +       bool "Wake on Wireless LAN support (EXPERIMENTAL)"
  35 +       depends on ATH9K && PM
  36 +       default n
  37 +       ---help---
  38 +         This option enables Wake on Wireless LAN support for certain cards.
  39 +         Currently, AR9462 is supported.
  40 +
  41  config ATH9K_LEGACY_RATE_CONTROL
  42         bool "Atheros ath9k rate control"
  43         depends on ATH9K
  44 --- a/drivers/net/wireless/ath/ath9k/Makefile
  45 +++ b/drivers/net/wireless/ath/ath9k/Makefile
  46 @@ -11,11 +11,13 @@ ath9k-$(CPTCFG_ATH9K_BTCOEX_SUPPORT) +=
  47  ath9k-$(CPTCFG_ATH9K_LEGACY_RATE_CONTROL) += rc.o
  48  ath9k-$(CPTCFG_ATH9K_PCI) += pci.o
  49  ath9k-$(CPTCFG_ATH9K_AHB) += ahb.o
  50 -ath9k-$(CPTCFG_ATH9K_DEBUGFS) += debug.o
  51  ath9k-$(CPTCFG_ATH9K_DFS_DEBUGFS) += dfs_debug.o
  52 -ath9k-$(CPTCFG_ATH9K_DFS_CERTIFIED) += \
  53 -               dfs.o
  54 -ath9k-$(CONFIG_PM_SLEEP) += wow.o
  55 +ath9k-$(CPTCFG_ATH9K_DFS_CERTIFIED) += dfs.o
  56 +ath9k-$(CPTCFG_ATH9K_TX99) += tx99.o
  57 +ath9k-$(CPTCFG_ATH9K_WOW) += wow.o
  58 +
  59 +ath9k-$(CPTCFG_ATH9K_DEBUGFS) += debug.o \
  60 +                                spectral.o
  61
  62  obj-$(CPTCFG_ATH9K) += ath9k.o
  63
  64 @@ -41,6 +43,8 @@ ath9k_hw-y:=  \
  65                 ar9003_eeprom.o \
  66                 ar9003_paprd.o
  67
  68 +ath9k_hw-$(CPTCFG_ATH9K_WOW) += ar9003_wow.o
  69 +
  70  ath9k_hw-$(CPTCFG_ATH9K_BTCOEX_SUPPORT) += btcoex.o \
  71                                            ar9003_mci.o
  72  obj-$(CPTCFG_ATH9K_HW) += ath9k_hw.o
  73 --- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c
  74 +++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
  75 @@ -17,6 +17,7 @@
  76  #include "hw.h"
  77  #include "ar9003_mac.h"
  78  #include "ar9003_2p2_initvals.h"
  79 +#include "ar9003_buffalo_initvals.h"
  80  #include "ar9485_initvals.h"
  81  #include "ar9340_initvals.h"
  82  #include "ar9330_1p1_initvals.h"
  83 @@ -26,6 +27,7 @@
  84  #include "ar9462_2p0_initvals.h"
  85  #include "ar9462_2p1_initvals.h"
  86  #include "ar9565_1p0_initvals.h"
  87 +#include "ar9565_1p1_initvals.h"
  88
  89  /* General hardware code for the AR9003 hadware family */
  90
  91 @@ -148,7 +150,11 @@ static void ar9003_hw_init_mode_regs(str
  92                                 ar9340Modes_high_ob_db_tx_gain_table_1p0);
  93
  94                 INIT_INI_ARRAY(&ah->iniModesFastClock,
  95 -                               ar9340Modes_fast_clock_1p0);
  96 +                              ar9340Modes_fast_clock_1p0);
  97 +               INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
  98 +                              ar9340_1p0_baseband_core_txfir_coeff_japan_2484);
  99 +               INIT_INI_ARRAY(&ah->ini_dfs,
 100 +                              ar9340_1p0_baseband_postamble_dfs_channel);
 101
 102                 if (!ah->is_clk_25mhz)
 103                         INIT_INI_ARRAY(&ah->iniAdditional,
 104 @@ -187,17 +193,17 @@ static void ar9003_hw_init_mode_regs(str
 105                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 106                                ar9485_1_1_baseband_core_txfir_coeff_japan_2484);
 107
 108 -               /* Load PCIE SERDES settings from INI */
 109 -
 110 -               /* Awake Setting */
 111 -
 112 -               INIT_INI_ARRAY(&ah->iniPcieSerdes,
 113 -                               ar9485_1_1_pcie_phy_clkreq_disable_L1);
 114 -
 115 -               /* Sleep Setting */
 116 -
 117 -               INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 118 -                               ar9485_1_1_pcie_phy_clkreq_disable_L1);
 119 +               if (ah->config.no_pll_pwrsave) {
 120 +                       INIT_INI_ARRAY(&ah->iniPcieSerdes,
 121 +                                      ar9485_1_1_pcie_phy_clkreq_disable_L1);
 122 +                       INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 123 +                                      ar9485_1_1_pcie_phy_clkreq_disable_L1);
 124 +               } else {
 125 +                       INIT_INI_ARRAY(&ah->iniPcieSerdes,
 126 +                                      ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1);
 127 +                       INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 128 +                                      ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1);
 129 +               }
 130         } else if (AR_SREV_9462_21(ah)) {
 131                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 132                                ar9462_2p1_mac_core);
 133 @@ -223,6 +229,10 @@ static void ar9003_hw_init_mode_regs(str
 134                                ar9462_2p1_modes_fast_clock);
 135                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 136                                ar9462_2p1_baseband_core_txfir_coeff_japan_2484);
 137 +               INIT_INI_ARRAY(&ah->iniPcieSerdes,
 138 +                              ar9462_2p1_pciephy_clkreq_disable_L1);
 139 +               INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 140 +                              ar9462_2p1_pciephy_clkreq_disable_L1);
 141         } else if (AR_SREV_9462_20(ah)) {
 142
 143                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core);
 144 @@ -247,18 +257,18 @@ static void ar9003_hw_init_mode_regs(str
 145                                 ar9462_2p0_soc_postamble);
 146
 147                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 148 -                               ar9462_common_rx_gain_table_2p0);
 149 +                               ar9462_2p0_common_rx_gain);
 150
 151                 /* Awake -> Sleep Setting */
 152                 INIT_INI_ARRAY(&ah->iniPcieSerdes,
 153 -                              ar9462_pciephy_clkreq_disable_L1_2p0);
 154 +                              ar9462_2p0_pciephy_clkreq_disable_L1);
 155                 /* Sleep -> Awake Setting */
 156                 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 157 -                              ar9462_pciephy_clkreq_disable_L1_2p0);
 158 +                              ar9462_2p0_pciephy_clkreq_disable_L1);
 159
 160                 /* Fast clock modal settings */
 161                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 162 -                               ar9462_modes_fast_clock_2p0);
 163 +                               ar9462_2p0_modes_fast_clock);
 164
 165                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 166                                ar9462_2p0_baseband_core_txfir_coeff_japan_2484);
 167 @@ -330,7 +340,46 @@ static void ar9003_hw_init_mode_regs(str
 168                                 ar9580_1p0_low_ob_db_tx_gain_table);
 169
 170                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 171 -                               ar9580_1p0_modes_fast_clock);
 172 +                              ar9580_1p0_modes_fast_clock);
 173 +               INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 174 +                              ar9580_1p0_baseband_core_txfir_coeff_japan_2484);
 175 +               INIT_INI_ARRAY(&ah->ini_dfs,
 176 +                              ar9580_1p0_baseband_postamble_dfs_channel);
 177 +       } else if (AR_SREV_9565_11_OR_LATER(ah)) {
 178 +               INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 179 +                              ar9565_1p1_mac_core);
 180 +               INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 181 +                              ar9565_1p1_mac_postamble);
 182 +
 183 +               INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 184 +                              ar9565_1p1_baseband_core);
 185 +               INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 186 +                              ar9565_1p1_baseband_postamble);
 187 +
 188 +               INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 189 +                              ar9565_1p1_radio_core);
 190 +               INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 191 +                              ar9565_1p1_radio_postamble);
 192 +
 193 +               INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 194 +                              ar9565_1p1_soc_preamble);
 195 +               INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 196 +                              ar9565_1p1_soc_postamble);
 197 +
 198 +               INIT_INI_ARRAY(&ah->iniModesRxGain,
 199 +                              ar9565_1p1_Common_rx_gain_table);
 200 +               INIT_INI_ARRAY(&ah->iniModesTxGain,
 201 +                              ar9565_1p1_Modes_lowest_ob_db_tx_gain_table);
 202 +
 203 +               INIT_INI_ARRAY(&ah->iniPcieSerdes,
 204 +                              ar9565_1p1_pciephy_clkreq_disable_L1);
 205 +               INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 206 +                              ar9565_1p1_pciephy_clkreq_disable_L1);
 207 +
 208 +               INIT_INI_ARRAY(&ah->iniModesFastClock,
 209 +                               ar9565_1p1_modes_fast_clock);
 210 +               INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 211 +                              ar9565_1p1_baseband_core_txfir_coeff_japan_2484);
 212         } else if (AR_SREV_9565(ah)) {
 213                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 214                                ar9565_1p0_mac_core);
 215 @@ -411,7 +460,11 @@ static void ar9003_hw_init_mode_regs(str
 216
 217                 /* Fast clock modal settings */
 218                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 219 -                               ar9300Modes_fast_clock_2p2);
 220 +                              ar9300Modes_fast_clock_2p2);
 221 +               INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 222 +                              ar9300_2p2_baseband_core_txfir_coeff_japan_2484);
 223 +               INIT_INI_ARRAY(&ah->ini_dfs,
 224 +                              ar9300_2p2_baseband_postamble_dfs_channel);
 225         }
 226  }
 227
 228 @@ -440,7 +493,10 @@ static void ar9003_tx_gain_table_mode0(s
 229                         ar9462_2p1_modes_low_ob_db_tx_gain);
 230         else if (AR_SREV_9462_20(ah))
 231                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 232 -                       ar9462_modes_low_ob_db_tx_gain_table_2p0);
 233 +                       ar9462_2p0_modes_low_ob_db_tx_gain);
 234 +       else if (AR_SREV_9565_11(ah))
 235 +               INIT_INI_ARRAY(&ah->iniModesTxGain,
 236 +                              ar9565_1p1_modes_low_ob_db_tx_gain_table);
 237         else if (AR_SREV_9565(ah))
 238                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 239                                ar9565_1p0_modes_low_ob_db_tx_gain_table);
 240 @@ -474,7 +530,10 @@ static void ar9003_tx_gain_table_mode1(s
 241                         ar9462_2p1_modes_high_ob_db_tx_gain);
 242         else if (AR_SREV_9462_20(ah))
 243                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 244 -                       ar9462_modes_high_ob_db_tx_gain_table_2p0);
 245 +                       ar9462_2p0_modes_high_ob_db_tx_gain);
 246 +       else if (AR_SREV_9565_11(ah))
 247 +               INIT_INI_ARRAY(&ah->iniModesTxGain,
 248 +                              ar9565_1p1_modes_high_ob_db_tx_gain_table);
 249         else if (AR_SREV_9565(ah))
 250                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 251                                ar9565_1p0_modes_high_ob_db_tx_gain_table);
 252 @@ -500,6 +559,9 @@ static void ar9003_tx_gain_table_mode2(s
 253         else if (AR_SREV_9580(ah))
 254                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 255                         ar9580_1p0_low_ob_db_tx_gain_table);
 256 +       else if (AR_SREV_9565_11(ah))
 257 +               INIT_INI_ARRAY(&ah->iniModesTxGain,
 258 +                              ar9565_1p1_modes_low_ob_db_tx_gain_table);
 259         else if (AR_SREV_9565(ah))
 260                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 261                                ar9565_1p0_modes_low_ob_db_tx_gain_table);
 262 @@ -525,12 +587,20 @@ static void ar9003_tx_gain_table_mode3(s
 263         else if (AR_SREV_9580(ah))
 264                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 265                         ar9580_1p0_high_power_tx_gain_table);
 266 +       else if (AR_SREV_9565_11(ah))
 267 +               INIT_INI_ARRAY(&ah->iniModesTxGain,
 268 +                              ar9565_1p1_modes_high_power_tx_gain_table);
 269         else if (AR_SREV_9565(ah))
 270                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 271                                ar9565_1p0_modes_high_power_tx_gain_table);
 272 -       else
 273 -               INIT_INI_ARRAY(&ah->iniModesTxGain,
 274 -                       ar9300Modes_high_power_tx_gain_table_2p2);
 275 +       else {
 276 +               if (ah->config.tx_gain_buffalo)
 277 +                       INIT_INI_ARRAY(&ah->iniModesTxGain,
 278 +                                      ar9300Modes_high_power_tx_gain_table_buffalo);
 279 +               else
 280 +                       INIT_INI_ARRAY(&ah->iniModesTxGain,
 281 +                                      ar9300Modes_high_power_tx_gain_table_2p2);
 282 +       }
 283  }
 284
 285  static void ar9003_tx_gain_table_mode4(struct ath_hw *ah)
 286 @@ -546,7 +616,7 @@ static void ar9003_tx_gain_table_mode4(s
 287                        ar9462_2p1_modes_mix_ob_db_tx_gain);
 288         else if (AR_SREV_9462_20(ah))
 289                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 290 -                      ar9462_modes_mix_ob_db_tx_gain_table_2p0);
 291 +                      ar9462_2p0_modes_mix_ob_db_tx_gain);
 292         else
 293                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 294                         ar9300Modes_mixed_ob_db_tx_gain_table_2p2);
 295 @@ -581,6 +651,13 @@ static void ar9003_tx_gain_table_mode6(s
 296                         ar9580_1p0_type6_tx_gain_table);
 297  }
 298
 299 +static void ar9003_tx_gain_table_mode7(struct ath_hw *ah)
 300 +{
 301 +       if (AR_SREV_9340(ah))
 302 +               INIT_INI_ARRAY(&ah->iniModesTxGain,
 303 +                              ar9340_cus227_tx_gain_table_1p0);
 304 +}
 305 +
 306  typedef void (*ath_txgain_tab)(struct ath_hw *ah);
 307
 308  static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
 309 @@ -593,6 +670,7 @@ static void ar9003_tx_gain_table_apply(s
 310                 ar9003_tx_gain_table_mode4,
 311                 ar9003_tx_gain_table_mode5,
 312                 ar9003_tx_gain_table_mode6,
 313 +               ar9003_tx_gain_table_mode7,
 314         };
 315         int idx = ar9003_hw_get_tx_gain_idx(ah);
 316
 317 @@ -629,7 +707,10 @@ static void ar9003_rx_gain_table_mode0(s
 318                                 ar9462_2p1_common_rx_gain);
 319         else if (AR_SREV_9462_20(ah))
 320                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 321 -                               ar9462_common_rx_gain_table_2p0);
 322 +                               ar9462_2p0_common_rx_gain);
 323 +       else if (AR_SREV_9565_11(ah))
 324 +               INIT_INI_ARRAY(&ah->iniModesRxGain,
 325 +                              ar9565_1p1_Common_rx_gain_table);
 326         else if (AR_SREV_9565(ah))
 327                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 328                                ar9565_1p0_Common_rx_gain_table);
 329 @@ -657,7 +738,7 @@ static void ar9003_rx_gain_table_mode1(s
 330                         ar9462_2p1_common_wo_xlna_rx_gain);
 331         else if (AR_SREV_9462_20(ah))
 332                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 333 -                       ar9462_common_wo_xlna_rx_gain_table_2p0);
 334 +                       ar9462_2p0_common_wo_xlna_rx_gain);
 335         else if (AR_SREV_9550(ah)) {
 336                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 337                         ar955x_1p0_common_wo_xlna_rx_gain_table);
 338 @@ -666,6 +747,9 @@ static void ar9003_rx_gain_table_mode1(s
 339         } else if (AR_SREV_9580(ah))
 340                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 341                         ar9580_1p0_wo_xlna_rx_gain_table);
 342 +       else if (AR_SREV_9565_11(ah))
 343 +               INIT_INI_ARRAY(&ah->iniModesRxGain,
 344 +                              ar9565_1p1_common_wo_xlna_rx_gain_table);
 345         else if (AR_SREV_9565(ah))
 346                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 347                                ar9565_1p0_common_wo_xlna_rx_gain_table);
 348 @@ -687,7 +771,7 @@ static void ar9003_rx_gain_table_mode2(s
 349                                ar9462_2p1_baseband_postamble_5g_xlna);
 350         } else if (AR_SREV_9462_20(ah)) {
 351                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 352 -                              ar9462_common_mixed_rx_gain_table_2p0);
 353 +                              ar9462_2p0_common_mixed_rx_gain);
 354                 INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_core,
 355                                ar9462_2p0_baseband_core_mix_rxgain);
 356                 INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
 357 @@ -701,12 +785,12 @@ static void ar9003_rx_gain_table_mode3(s
 358  {
 359         if (AR_SREV_9462_21(ah)) {
 360                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 361 -                              ar9462_2p1_common_5g_xlna_only_rx_gain);
 362 +                              ar9462_2p1_common_5g_xlna_only_rxgain);
 363                 INIT_INI_ARRAY(&ah->ini_modes_rxgain_5g_xlna,
 364                                ar9462_2p1_baseband_postamble_5g_xlna);
 365         } else if (AR_SREV_9462_20(ah)) {
 366                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 367 -                              ar9462_2p0_5g_xlna_only_rxgain);
 368 +                              ar9462_2p0_common_5g_xlna_only_rxgain);
 369                 INIT_INI_ARRAY(&ah->ini_modes_rxgain_5g_xlna,
 370                                ar9462_2p0_baseband_postamble_5g_xlna);
 371         }
 372 @@ -750,6 +834,9 @@ static void ar9003_hw_init_mode_gain_reg
 373  static void ar9003_hw_configpcipowersave(struct ath_hw *ah,
 374                                          bool power_off)
 375  {
 376 +       unsigned int i;
 377 +       struct ar5416IniArray *array;
 378 +
 379         /*
 380          * Increase L1 Entry Latency. Some WB222 boards don't have
 381          * this change in eeprom/OTP.
 382 @@ -775,18 +862,13 @@ static void ar9003_hw_configpcipowersave
 383          * Configire PCIE after Ini init. SERDES values now come from ini file
 384          * This enables PCIe low power mode.
 385          */
 386 -       if (ah->config.pcieSerDesWrite) {
 387 -               unsigned int i;
 388 -               struct ar5416IniArray *array;
 389 -
 390 -               array = power_off ? &ah->iniPcieSerdes :
 391 -                                   &ah->iniPcieSerdesLowPower;
 392 -
 393 -               for (i = 0; i < array->ia_rows; i++) {
 394 -                       REG_WRITE(ah,
 395 -                                 INI_RA(array, i, 0),
 396 -                                 INI_RA(array, i, 1));
 397 -               }
 398 +       array = power_off ? &ah->iniPcieSerdes :
 399 +               &ah->iniPcieSerdesLowPower;
 400 +
 401 +       for (i = 0; i < array->ia_rows; i++) {
 402 +               REG_WRITE(ah,
 403 +                         INI_RA(array, i, 0),
 404 +                         INI_RA(array, i, 1));
 405         }
 406  }
 407
 408 --- a/drivers/net/wireless/ath/ath9k/ar9340_initvals.h
 409 +++ b/drivers/net/wireless/ath/ath9k/ar9340_initvals.h
 410 @@ -18,6 +18,20 @@
 411  #ifndef INITVALS_9340_H
 412  #define INITVALS_9340_H
 413
 414 +#define ar9340_1p0_mac_postamble ar9300_2p2_mac_postamble
 415 +
 416 +#define ar9340_1p0_soc_postamble ar9300_2p2_soc_postamble
 417 +
 418 +#define ar9340Modes_fast_clock_1p0 ar9300Modes_fast_clock_2p2
 419 +
 420 +#define ar9340Common_rx_gain_table_1p0 ar9300Common_rx_gain_table_2p2
 421 +
 422 +#define ar9340Common_wo_xlna_rx_gain_table_1p0 ar9300Common_wo_xlna_rx_gain_table_2p2
 423 +
 424 +#define ar9340_1p0_baseband_core_txfir_coeff_japan_2484 ar9300_2p2_baseband_core_txfir_coeff_japan_2484
 425 +
 426 +#define ar9340_1p0_baseband_postamble_dfs_channel ar9300_2p2_baseband_postamble_dfs_channel
 427 +
 428  static const u32 ar9340_1p0_radio_postamble[][5] = {
 429         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
 430         {0x000160ac, 0xa4646800, 0xa4646800, 0xa4646800, 0xa4646800},
 431 @@ -100,8 +114,6 @@ static const u32 ar9340Modes_lowest_ob_d
 432         {0x00016448, 0x24925266, 0x24925266, 0x24925266, 0x24925266},
 433  };
 434
 435 -#define ar9340Modes_fast_clock_1p0 ar9300Modes_fast_clock_2p2
 436 -
 437  static const u32 ar9340_1p0_radio_core[][2] = {
 438         /* Addr      allmodes  */
 439         {0x00016000, 0x36db6db6},
 440 @@ -215,16 +227,12 @@ static const u32 ar9340_1p0_radio_core_4
 441         {0x0000824c, 0x0001e800},
 442  };
 443
 444 -#define ar9340_1p0_mac_postamble ar9300_2p2_mac_postamble
 445 -
 446 -#define ar9340_1p0_soc_postamble ar9300_2p2_soc_postamble
 447 -
 448  static const u32 ar9340_1p0_baseband_postamble[][5] = {
 449         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
 450         {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a8011},
 451         {0x00009820, 0x206a022e, 0x206a022e, 0x206a022e, 0x206a022e},
 452         {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0},
 453 -       {0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881},
 454 +       {0x00009828, 0x06903081, 0x06903081, 0x09103881, 0x09103881},
 455         {0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4},
 456         {0x00009830, 0x0000059c, 0x0000059c, 0x0000119c, 0x0000119c},
 457         {0x00009c00, 0x000000c4, 0x000000c4, 0x000000c4, 0x000000c4},
 458 @@ -340,9 +348,9 @@ static const u32 ar9340_1p0_baseband_cor
 459         {0x0000a370, 0x00000000},
 460         {0x0000a390, 0x00000001},
 461         {0x0000a394, 0x00000444},
 462 -       {0x0000a398, 0x001f0e0f},
 463 -       {0x0000a39c, 0x0075393f},
 464 -       {0x0000a3a0, 0xb79f6427},
 465 +       {0x0000a398, 0x00000000},
 466 +       {0x0000a39c, 0x210d0401},
 467 +       {0x0000a3a0, 0xab9a7144},
 468         {0x0000a3a4, 0x00000000},
 469         {0x0000a3a8, 0xaaaaaaaa},
 470         {0x0000a3ac, 0x3c466478},
 471 @@ -714,266 +722,6 @@ static const u32 ar9340Modes_ub124_tx_ga
 472         {0x0000b2e8, 0xfffe0000, 0xfffe0000, 0xfffc0000, 0xfffc0000},
 473  };
 474
 475 -static const u32 ar9340Common_rx_gain_table_1p0[][2] = {
 476 -       /* Addr      allmodes  */
 477 -       {0x0000a000, 0x00010000},
 478 -       {0x0000a004, 0x00030002},
 479 -       {0x0000a008, 0x00050004},
 480 -       {0x0000a00c, 0x00810080},
 481 -       {0x0000a010, 0x00830082},
 482 -       {0x0000a014, 0x01810180},
 483 -       {0x0000a018, 0x01830182},
 484 -       {0x0000a01c, 0x01850184},
 485 -       {0x0000a020, 0x01890188},
 486 -       {0x0000a024, 0x018b018a},
 487 -       {0x0000a028, 0x018d018c},
 488 -       {0x0000a02c, 0x01910190},
 489 -       {0x0000a030, 0x01930192},
 490 -       {0x0000a034, 0x01950194},
 491 -       {0x0000a038, 0x038a0196},
 492 -       {0x0000a03c, 0x038c038b},
 493 -       {0x0000a040, 0x0390038d},
 494 -       {0x0000a044, 0x03920391},
 495 -       {0x0000a048, 0x03940393},
 496 -       {0x0000a04c, 0x03960395},
 497 -       {0x0000a050, 0x00000000},
 498 -       {0x0000a054, 0x00000000},
 499 -       {0x0000a058, 0x00000000},
 500 -       {0x0000a05c, 0x00000000},
 501 -       {0x0000a060, 0x00000000},
 502 -       {0x0000a064, 0x00000000},
 503 -       {0x0000a068, 0x00000000},
 504 -       {0x0000a06c, 0x00000000},
 505 -       {0x0000a070, 0x00000000},
 506 -       {0x0000a074, 0x00000000},
 507 -       {0x0000a078, 0x00000000},
 508 -       {0x0000a07c, 0x00000000},
 509 -       {0x0000a080, 0x22222229},
 510 -       {0x0000a084, 0x1d1d1d1d},
 511 -       {0x0000a088, 0x1d1d1d1d},
 512 -       {0x0000a08c, 0x1d1d1d1d},
 513 -       {0x0000a090, 0x171d1d1d},
 514 -       {0x0000a094, 0x11111717},
 515 -       {0x0000a098, 0x00030311},
 516 -       {0x0000a09c, 0x00000000},
 517 -       {0x0000a0a0, 0x00000000},
 518 -       {0x0000a0a4, 0x00000000},
 519 -       {0x0000a0a8, 0x00000000},
 520 -       {0x0000a0ac, 0x00000000},
 521 -       {0x0000a0b0, 0x00000000},
 522 -       {0x0000a0b4, 0x00000000},
 523 -       {0x0000a0b8, 0x00000000},
 524 -       {0x0000a0bc, 0x00000000},
 525 -       {0x0000a0c0, 0x001f0000},
 526 -       {0x0000a0c4, 0x01000101},
 527 -       {0x0000a0c8, 0x011e011f},
 528 -       {0x0000a0cc, 0x011c011d},
 529 -       {0x0000a0d0, 0x02030204},
 530 -       {0x0000a0d4, 0x02010202},
 531 -       {0x0000a0d8, 0x021f0200},
 532 -       {0x0000a0dc, 0x0302021e},
 533 -       {0x0000a0e0, 0x03000301},
 534 -       {0x0000a0e4, 0x031e031f},
 535 -       {0x0000a0e8, 0x0402031d},
 536 -       {0x0000a0ec, 0x04000401},
 537 -       {0x0000a0f0, 0x041e041f},
 538 -       {0x0000a0f4, 0x0502041d},
 539 -       {0x0000a0f8, 0x05000501},
 540 -       {0x0000a0fc, 0x051e051f},
 541 -       {0x0000a100, 0x06010602},
 542 -       {0x0000a104, 0x061f0600},
 543 -       {0x0000a108, 0x061d061e},
 544 -       {0x0000a10c, 0x07020703},
 545 -       {0x0000a110, 0x07000701},
 546 -       {0x0000a114, 0x00000000},
 547 -       {0x0000a118, 0x00000000},
 548 -       {0x0000a11c, 0x00000000},
 549 -       {0x0000a120, 0x00000000},
 550 -       {0x0000a124, 0x00000000},
 551 -       {0x0000a128, 0x00000000},
 552 -       {0x0000a12c, 0x00000000},
 553 -       {0x0000a130, 0x00000000},
 554 -       {0x0000a134, 0x00000000},
 555 -       {0x0000a138, 0x00000000},
 556 -       {0x0000a13c, 0x00000000},
 557 -       {0x0000a140, 0x001f0000},
 558 -       {0x0000a144, 0x01000101},
 559 -       {0x0000a148, 0x011e011f},
 560 -       {0x0000a14c, 0x011c011d},
 561 -       {0x0000a150, 0x02030204},
 562 -       {0x0000a154, 0x02010202},
 563 -       {0x0000a158, 0x021f0200},
 564 -       {0x0000a15c, 0x0302021e},
 565 -       {0x0000a160, 0x03000301},
 566 -       {0x0000a164, 0x031e031f},
 567 -       {0x0000a168, 0x0402031d},
 568 -       {0x0000a16c, 0x04000401},
 569 -       {0x0000a170, 0x041e041f},
 570 -       {0x0000a174, 0x0502041d},
 571 -       {0x0000a178, 0x05000501},
 572 -       {0x0000a17c, 0x051e051f},
 573 -       {0x0000a180, 0x06010602},
 574 -       {0x0000a184, 0x061f0600},
 575 -       {0x0000a188, 0x061d061e},
 576 -       {0x0000a18c, 0x07020703},
 577 -       {0x0000a190, 0x07000701},
 578 -       {0x0000a194, 0x00000000},
 579 -       {0x0000a198, 0x00000000},
 580 -       {0x0000a19c, 0x00000000},
 581 -       {0x0000a1a0, 0x00000000},
 582 -       {0x0000a1a4, 0x00000000},
 583 -       {0x0000a1a8, 0x00000000},
 584 -       {0x0000a1ac, 0x00000000},
 585 -       {0x0000a1b0, 0x00000000},
 586 -       {0x0000a1b4, 0x00000000},
 587 -       {0x0000a1b8, 0x00000000},
 588 -       {0x0000a1bc, 0x00000000},
 589 -       {0x0000a1c0, 0x00000000},
 590 -       {0x0000a1c4, 0x00000000},
 591 -       {0x0000a1c8, 0x00000000},
 592 -       {0x0000a1cc, 0x00000000},
 593 -       {0x0000a1d0, 0x00000000},
 594 -       {0x0000a1d4, 0x00000000},
 595 -       {0x0000a1d8, 0x00000000},
 596 -       {0x0000a1dc, 0x00000000},
 597 -       {0x0000a1e0, 0x00000000},
 598 -       {0x0000a1e4, 0x00000000},
 599 -       {0x0000a1e8, 0x00000000},
 600 -       {0x0000a1ec, 0x00000000},
 601 -       {0x0000a1f0, 0x00000396},
 602 -       {0x0000a1f4, 0x00000396},
 603 -       {0x0000a1f8, 0x00000396},
 604 -       {0x0000a1fc, 0x00000196},
 605 -       {0x0000b000, 0x00010000},
 606 -       {0x0000b004, 0x00030002},
 607 -       {0x0000b008, 0x00050004},
 608 -       {0x0000b00c, 0x00810080},
 609 -       {0x0000b010, 0x00830082},
 610 -       {0x0000b014, 0x01810180},
 611 -       {0x0000b018, 0x01830182},
 612 -       {0x0000b01c, 0x01850184},
 613 -       {0x0000b020, 0x02810280},
 614 -       {0x0000b024, 0x02830282},
 615 -       {0x0000b028, 0x02850284},
 616 -       {0x0000b02c, 0x02890288},
 617 -       {0x0000b030, 0x028b028a},
 618 -       {0x0000b034, 0x0388028c},
 619 -       {0x0000b038, 0x038a0389},
 620 -       {0x0000b03c, 0x038c038b},
 621 -       {0x0000b040, 0x0390038d},
 622 -       {0x0000b044, 0x03920391},
 623 -       {0x0000b048, 0x03940393},
 624 -       {0x0000b04c, 0x03960395},
 625 -       {0x0000b050, 0x00000000},
 626 -       {0x0000b054, 0x00000000},
 627 -       {0x0000b058, 0x00000000},
 628 -       {0x0000b05c, 0x00000000},
 629 -       {0x0000b060, 0x00000000},
 630 -       {0x0000b064, 0x00000000},
 631 -       {0x0000b068, 0x00000000},
 632 -       {0x0000b06c, 0x00000000},
 633 -       {0x0000b070, 0x00000000},
 634 -       {0x0000b074, 0x00000000},
 635 -       {0x0000b078, 0x00000000},
 636 -       {0x0000b07c, 0x00000000},
 637 -       {0x0000b080, 0x23232323},
 638 -       {0x0000b084, 0x21232323},
 639 -       {0x0000b088, 0x19191c1e},
 640 -       {0x0000b08c, 0x12141417},
 641 -       {0x0000b090, 0x07070e0e},
 642 -       {0x0000b094, 0x03030305},
 643 -       {0x0000b098, 0x00000003},
 644 -       {0x0000b09c, 0x00000000},
 645 -       {0x0000b0a0, 0x00000000},
 646 -       {0x0000b0a4, 0x00000000},
 647 -       {0x0000b0a8, 0x00000000},
 648 -       {0x0000b0ac, 0x00000000},
 649 -       {0x0000b0b0, 0x00000000},
 650 -       {0x0000b0b4, 0x00000000},
 651 -       {0x0000b0b8, 0x00000000},
 652 -       {0x0000b0bc, 0x00000000},
 653 -       {0x0000b0c0, 0x003f0020},
 654 -       {0x0000b0c4, 0x00400041},
 655 -       {0x0000b0c8, 0x0140005f},
 656 -       {0x0000b0cc, 0x0160015f},
 657 -       {0x0000b0d0, 0x017e017f},
 658 -       {0x0000b0d4, 0x02410242},
 659 -       {0x0000b0d8, 0x025f0240},
 660 -       {0x0000b0dc, 0x027f0260},
 661 -       {0x0000b0e0, 0x0341027e},
 662 -       {0x0000b0e4, 0x035f0340},
 663 -       {0x0000b0e8, 0x037f0360},
 664 -       {0x0000b0ec, 0x04400441},
 665 -       {0x0000b0f0, 0x0460045f},
 666 -       {0x0000b0f4, 0x0541047f},
 667 -       {0x0000b0f8, 0x055f0540},
 668 -       {0x0000b0fc, 0x057f0560},
 669 -       {0x0000b100, 0x06400641},
 670 -       {0x0000b104, 0x0660065f},
 671 -       {0x0000b108, 0x067e067f},
 672 -       {0x0000b10c, 0x07410742},
 673 -       {0x0000b110, 0x075f0740},
 674 -       {0x0000b114, 0x077f0760},
 675 -       {0x0000b118, 0x07800781},
 676 -       {0x0000b11c, 0x07a0079f},
 677 -       {0x0000b120, 0x07c107bf},
 678 -       {0x0000b124, 0x000007c0},
 679 -       {0x0000b128, 0x00000000},
 680 -       {0x0000b12c, 0x00000000},
 681 -       {0x0000b130, 0x00000000},
 682 -       {0x0000b134, 0x00000000},
 683 -       {0x0000b138, 0x00000000},
 684 -       {0x0000b13c, 0x00000000},
 685 -       {0x0000b140, 0x003f0020},
 686 -       {0x0000b144, 0x00400041},
 687 -       {0x0000b148, 0x0140005f},
 688 -       {0x0000b14c, 0x0160015f},
 689 -       {0x0000b150, 0x017e017f},
 690 -       {0x0000b154, 0x02410242},
 691 -       {0x0000b158, 0x025f0240},
 692 -       {0x0000b15c, 0x027f0260},
 693 -       {0x0000b160, 0x0341027e},
 694 -       {0x0000b164, 0x035f0340},
 695 -       {0x0000b168, 0x037f0360},
 696 -       {0x0000b16c, 0x04400441},
 697 -       {0x0000b170, 0x0460045f},
 698 -       {0x0000b174, 0x0541047f},
 699 -       {0x0000b178, 0x055f0540},
 700 -       {0x0000b17c, 0x057f0560},
 701 -       {0x0000b180, 0x06400641},
 702 -       {0x0000b184, 0x0660065f},
 703 -       {0x0000b188, 0x067e067f},
 704 -       {0x0000b18c, 0x07410742},
 705 -       {0x0000b190, 0x075f0740},
 706 -       {0x0000b194, 0x077f0760},
 707 -       {0x0000b198, 0x07800781},
 708 -       {0x0000b19c, 0x07a0079f},
 709 -       {0x0000b1a0, 0x07c107bf},
 710 -       {0x0000b1a4, 0x000007c0},
 711 -       {0x0000b1a8, 0x00000000},
 712 -       {0x0000b1ac, 0x00000000},
 713 -       {0x0000b1b0, 0x00000000},
 714 -       {0x0000b1b4, 0x00000000},
 715 -       {0x0000b1b8, 0x00000000},
 716 -       {0x0000b1bc, 0x00000000},
 717 -       {0x0000b1c0, 0x00000000},
 718 -       {0x0000b1c4, 0x00000000},
 719 -       {0x0000b1c8, 0x00000000},
 720 -       {0x0000b1cc, 0x00000000},
 721 -       {0x0000b1d0, 0x00000000},
 722 -       {0x0000b1d4, 0x00000000},
 723 -       {0x0000b1d8, 0x00000000},
 724 -       {0x0000b1dc, 0x00000000},
 725 -       {0x0000b1e0, 0x00000000},
 726 -       {0x0000b1e4, 0x00000000},
 727 -       {0x0000b1e8, 0x00000000},
 728 -       {0x0000b1ec, 0x00000000},
 729 -       {0x0000b1f0, 0x00000396},
 730 -       {0x0000b1f4, 0x00000396},
 731 -       {0x0000b1f8, 0x00000396},
 732 -       {0x0000b1fc, 0x00000196},
 733 -};
 734 -
 735  static const u32 ar9340Modes_low_ob_db_tx_gain_table_1p0[][5] = {
 736         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
 737         {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
 738 @@ -1437,8 +1185,6 @@ static const u32 ar9340_1p0_mac_core[][2
 739         {0x000083d0, 0x000101ff},
 740  };
 741
 742 -#define ar9340Common_wo_xlna_rx_gain_table_1p0 ar9300Common_wo_xlna_rx_gain_table_2p2
 743 -
 744  static const u32 ar9340_1p0_soc_preamble[][2] = {
 745         /* Addr      allmodes  */
 746         {0x00007008, 0x00000000},
 747 @@ -1447,4 +1193,106 @@ static const u32 ar9340_1p0_soc_preamble
 748         {0x00007038, 0x000004c2},
 749  };
 750
 751 +static const u32 ar9340_cus227_tx_gain_table_1p0[][5] = {
 752 +       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
 753 +       {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
 754 +       {0x0000a2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
 755 +       {0x0000a2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
 756 +       {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
 757 +       {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
 758 +       {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
 759 +       {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
 760 +       {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004},
 761 +       {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
 762 +       {0x0000a510, 0x16000220, 0x16000220, 0x0f000202, 0x0f000202},
 763 +       {0x0000a514, 0x1c000223, 0x1c000223, 0x11000400, 0x11000400},
 764 +       {0x0000a518, 0x21002220, 0x21002220, 0x15000402, 0x15000402},
 765 +       {0x0000a51c, 0x27002223, 0x27002223, 0x19000404, 0x19000404},
 766 +       {0x0000a520, 0x2c022220, 0x2c022220, 0x1b000603, 0x1b000603},
 767 +       {0x0000a524, 0x30022222, 0x30022222, 0x1f000a02, 0x1f000a02},
 768 +       {0x0000a528, 0x35022225, 0x35022225, 0x23000a04, 0x23000a04},
 769 +       {0x0000a52c, 0x3b02222a, 0x3b02222a, 0x26000a20, 0x26000a20},
 770 +       {0x0000a530, 0x3f02222c, 0x3f02222c, 0x2a000e20, 0x2a000e20},
 771 +       {0x0000a534, 0x4202242a, 0x4202242a, 0x2e000e22, 0x2e000e22},
 772 +       {0x0000a538, 0x4702244a, 0x4702244a, 0x31000e24, 0x31000e24},
 773 +       {0x0000a53c, 0x4b02244c, 0x4b02244c, 0x34001640, 0x34001640},
 774 +       {0x0000a540, 0x4e02246c, 0x4e02246c, 0x38001660, 0x38001660},
 775 +       {0x0000a544, 0x5302266c, 0x5302266c, 0x3b001861, 0x3b001861},
 776 +       {0x0000a548, 0x5702286c, 0x5702286c, 0x3e001a81, 0x3e001a81},
 777 +       {0x0000a54c, 0x5c02486b, 0x5c02486b, 0x42001a83, 0x42001a83},
 778 +       {0x0000a550, 0x61024a6c, 0x61024a6c, 0x44001c84, 0x44001c84},
 779 +       {0x0000a554, 0x66026a6c, 0x66026a6c, 0x48001ce3, 0x48001ce3},
 780 +       {0x0000a558, 0x6b026e6c, 0x6b026e6c, 0x4c001ce5, 0x4c001ce5},
 781 +       {0x0000a55c, 0x7002708c, 0x7002708c, 0x50001ce9, 0x50001ce9},
 782 +       {0x0000a560, 0x7302b08a, 0x7302b08a, 0x54001ceb, 0x54001ceb},
 783 +       {0x0000a564, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
 784 +       {0x0000a568, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
 785 +       {0x0000a56c, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
 786 +       {0x0000a570, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
 787 +       {0x0000a574, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
 788 +       {0x0000a578, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
 789 +       {0x0000a57c, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
 790 +       {0x0000a580, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
 791 +       {0x0000a584, 0x06800003, 0x06800003, 0x04800002, 0x04800002},
 792 +       {0x0000a588, 0x0a800020, 0x0a800020, 0x08800004, 0x08800004},
 793 +       {0x0000a58c, 0x10800023, 0x10800023, 0x0b800200, 0x0b800200},
 794 +       {0x0000a590, 0x16800220, 0x16800220, 0x0f800202, 0x0f800202},
 795 +       {0x0000a594, 0x1c800223, 0x1c800223, 0x11800400, 0x11800400},
 796 +       {0x0000a598, 0x21820220, 0x21820220, 0x15800402, 0x15800402},
 797 +       {0x0000a59c, 0x27820223, 0x27820223, 0x19800404, 0x19800404},
 798 +       {0x0000a5a0, 0x2b822220, 0x2b822220, 0x1b800603, 0x1b800603},
 799 +       {0x0000a5a4, 0x2f822222, 0x2f822222, 0x1f800a02, 0x1f800a02},
 800 +       {0x0000a5a8, 0x34822225, 0x34822225, 0x23800a04, 0x23800a04},
 801 +       {0x0000a5ac, 0x3a82222a, 0x3a82222a, 0x26800a20, 0x26800a20},
 802 +       {0x0000a5b0, 0x3e82222c, 0x3e82222c, 0x2a800e20, 0x2a800e20},
 803 +       {0x0000a5b4, 0x4282242a, 0x4282242a, 0x2e800e22, 0x2e800e22},
 804 +       {0x0000a5b8, 0x4782244a, 0x4782244a, 0x31800e24, 0x31800e24},
 805 +       {0x0000a5bc, 0x4b82244c, 0x4b82244c, 0x34801640, 0x34801640},
 806 +       {0x0000a5c0, 0x4e82246c, 0x4e82246c, 0x38801660, 0x38801660},
 807 +       {0x0000a5c4, 0x5382266c, 0x5382266c, 0x3b801861, 0x3b801861},
 808 +       {0x0000a5c8, 0x5782286c, 0x5782286c, 0x3e801a81, 0x3e801a81},
 809 +       {0x0000a5cc, 0x5c84286b, 0x5c84286b, 0x42801a83, 0x42801a83},
 810 +       {0x0000a5d0, 0x61842a6c, 0x61842a6c, 0x44801c84, 0x44801c84},
 811 +       {0x0000a5d4, 0x66862a6c, 0x66862a6c, 0x48801ce3, 0x48801ce3},
 812 +       {0x0000a5d8, 0x6b862e6c, 0x6b862e6c, 0x4c801ce5, 0x4c801ce5},
 813 +       {0x0000a5dc, 0x7086308c, 0x7086308c, 0x50801ce9, 0x50801ce9},
 814 +       {0x0000a5e0, 0x738a308a, 0x738a308a, 0x54801ceb, 0x54801ceb},
 815 +       {0x0000a5e4, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
 816 +       {0x0000a5e8, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
 817 +       {0x0000a5ec, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
 818 +       {0x0000a5f0, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
 819 +       {0x0000a5f4, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
 820 +       {0x0000a5f8, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
 821 +       {0x0000a5fc, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
 822 +       {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
 823 +       {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
 824 +       {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
 825 +       {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
 826 +       {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
 827 +       {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000},
 828 +       {0x0000a618, 0x01404501, 0x01404501, 0x01404501, 0x01404501},
 829 +       {0x0000a61c, 0x02008802, 0x02008802, 0x02008501, 0x02008501},
 830 +       {0x0000a620, 0x0300cc03, 0x0300cc03, 0x0280ca03, 0x0280ca03},
 831 +       {0x0000a624, 0x0300cc03, 0x0300cc03, 0x03010c04, 0x03010c04},
 832 +       {0x0000a628, 0x0300cc03, 0x0300cc03, 0x04014c04, 0x04014c04},
 833 +       {0x0000a62c, 0x03810c03, 0x03810c03, 0x04015005, 0x04015005},
 834 +       {0x0000a630, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
 835 +       {0x0000a634, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
 836 +       {0x0000a638, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
 837 +       {0x0000a63c, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
 838 +       {0x0000b2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
 839 +       {0x0000b2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
 840 +       {0x0000b2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
 841 +       {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
 842 +       {0x00016044, 0x056db2db, 0x056db2db, 0x03b6d2e4, 0x03b6d2e4},
 843 +       {0x00016048, 0x24925666, 0x24925666, 0x8e481266, 0x8e481266},
 844 +       {0x00016280, 0x01000015, 0x01000015, 0x01001015, 0x01001015},
 845 +       {0x00016288, 0x30318000, 0x30318000, 0x00318000, 0x00318000},
 846 +       {0x00016444, 0x056db2db, 0x056db2db, 0x03b6d2e4, 0x03b6d2e4},
 847 +       {0x00016448, 0x24925666, 0x24925666, 0x8e481266, 0x8e481266},
 848 +       {0x0000a3a4, 0x00000011, 0x00000011, 0x00000011, 0x00000011},
 849 +       {0x0000a3a8, 0x3c3c3c3c, 0x3c3c3c3c, 0x3c3c3c3c, 0x3c3c3c3c},
 850 +       {0x0000a3ac, 0x30303030, 0x30303030, 0x30303030, 0x30303030},
 851 +};
 852 +
 853  #endif /* INITVALS_9340_H */
 854 --- a/drivers/net/wireless/ath/ath9k/ath9k.h
 855 +++ b/drivers/net/wireless/ath/ath9k/ath9k.h
 856 @@ -27,40 +27,15 @@
 857  #include "common.h"
 858  #include "mci.h"
 859  #include "dfs.h"
 860 -
 861 -/*
 862 - * Header for the ath9k.ko driver core *only* -- hw code nor any other driver
 863 - * should rely on this file or its contents.
 864 - */
 865 +#include "spectral.h"
 866
 867  struct ath_node;
 868 +struct ath_rate_table;
 869
 870 -/* Macro to expand scalars to 64-bit objects */
 871 -
 872 -#define        ito64(x) (sizeof(x) == 1) ?                     \
 873 -       (((unsigned long long int)(x)) & (0xff)) :      \
 874 -       (sizeof(x) == 2) ?                              \
 875 -       (((unsigned long long int)(x)) & 0xffff) :      \
 876 -       ((sizeof(x) == 4) ?                             \
 877 -        (((unsigned long long int)(x)) & 0xffffffff) : \
 878 -        (unsigned long long int)(x))
 879 -
 880 -/* increment with wrap-around */
 881 -#define INCR(_l, _sz)   do {                   \
 882 -               (_l)++;                         \
 883 -               (_l) &= ((_sz) - 1);            \
 884 -       } while (0)
 885 -
 886 -/* decrement with wrap-around */
 887 -#define DECR(_l,  _sz)  do {                   \
 888 -               (_l)--;                         \
 889 -               (_l) &= ((_sz) - 1);            \
 890 -       } while (0)
 891 -
 892 -#define TSF_TO_TU(_h,_l) \
 893 -       ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
 894 -
 895 -#define        ATH_TXQ_SETUP(sc, i)        ((sc)->tx.txqsetup & (1<<i))
 896 +extern struct ieee80211_ops ath9k_ops;
 897 +extern int ath9k_modparam_nohwcrypt;
 898 +extern int led_blink;
 899 +extern bool is_ath9k_unloaded;
 900
 901  struct ath_config {
 902         u16 txpowlimit;
 903 @@ -70,6 +45,17 @@ struct ath_config {
 904  /* Descriptor Management */
 905  /*************************/
 906
 907 +#define ATH_TXSTATUS_RING_SIZE 512
 908 +
 909 +/* Macro to expand scalars to 64-bit objects */
 910 +#define        ito64(x) (sizeof(x) == 1) ?                     \
 911 +       (((unsigned long long int)(x)) & (0xff)) :      \
 912 +       (sizeof(x) == 2) ?                              \
 913 +       (((unsigned long long int)(x)) & 0xffff) :      \
 914 +       ((sizeof(x) == 4) ?                             \
 915 +        (((unsigned long long int)(x)) & 0xffffffff) : \
 916 +        (unsigned long long int)(x))
 917 +
 918  #define ATH_TXBUF_RESET(_bf) do {                              \
 919                 (_bf)->bf_lastbf = NULL;                        \
 920                 (_bf)->bf_next = NULL;                          \
 921 @@ -77,23 +63,6 @@ struct ath_config {
 922                        sizeof(struct ath_buf_state));           \
 923         } while (0)
 924
 925 -/**
 926 - * enum buffer_type - Buffer type flags
 927 - *
 928 - * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX)
 929 - * @BUF_AGGR: Indicates whether the buffer can be aggregated
 930 - *     (used in aggregation scheduling)
 931 - */
 932 -enum buffer_type {
 933 -       BUF_AMPDU               = BIT(0),
 934 -       BUF_AGGR                = BIT(1),
 935 -};
 936 -
 937 -#define bf_isampdu(bf)         (bf->bf_state.bf_type & BUF_AMPDU)
 938 -#define bf_isaggr(bf)          (bf->bf_state.bf_type & BUF_AGGR)
 939 -
 940 -#define ATH_TXSTATUS_RING_SIZE 512
 941 -
 942  #define        DS2PHYS(_dd, _ds)                                               \
 943         ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
 944  #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
 945 @@ -113,11 +82,20 @@ int ath_descdma_setup(struct ath_softc *
 946  /* RX / TX */
 947  /***********/
 948
 949 +#define        ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i))
 950 +
 951 +/* increment with wrap-around */
 952 +#define INCR(_l, _sz)   do {                   \
 953 +               (_l)++;                         \
 954 +               (_l) &= ((_sz) - 1);            \
 955 +       } while (0)
 956 +
 957  #define ATH_RXBUF               512
 958  #define ATH_TXBUF               512
 959  #define ATH_TXBUF_RESERVE       5
 960  #define ATH_MAX_QDEPTH          (ATH_TXBUF / 4 - ATH_TXBUF_RESERVE)
 961  #define ATH_TXMAXTRY            13
 962 +#define ATH_MAX_SW_RETRIES      30
 963
 964  #define TID_TO_WME_AC(_tid)                            \
 965         ((((_tid) == 0) || ((_tid) == 3)) ? IEEE80211_AC_BE :   \
 966 @@ -133,6 +111,9 @@ int ath_descdma_setup(struct ath_softc *
 967  #define ATH_AGGR_MIN_QDEPTH        2
 968  /* minimum h/w qdepth for non-aggregated traffic */
 969  #define ATH_NON_AGGR_MIN_QDEPTH    8
 970 +#define ATH_TX_COMPLETE_POLL_INT   1000
 971 +#define ATH_TXFIFO_DEPTH           8
 972 +#define ATH_TX_ERROR               0x01
 973
 974  #define IEEE80211_SEQ_SEQ_SHIFT    4
 975  #define IEEE80211_SEQ_MAX          4096
 976 @@ -167,9 +148,6 @@ int ath_descdma_setup(struct ath_softc *
 977
 978  #define IS_CCK_RATE(rate) ((rate >= 0x18) && (rate <= 0x1e))
 979
 980 -#define ATH_TX_COMPLETE_POLL_INT       1000
 981 -
 982 -#define ATH_TXFIFO_DEPTH 8
 983  struct ath_txq {
 984         int mac80211_qnum; /* mac80211 queue number, -1 means not mac80211 Q */
 985         u32 axq_qnum; /* ath9k hardware queue number */
 986 @@ -214,6 +192,21 @@ struct ath_rxbuf {
 987         dma_addr_t bf_buf_addr;
 988  };
 989
 990 +/**
 991 + * enum buffer_type - Buffer type flags
 992 + *
 993 + * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX)
 994 + * @BUF_AGGR: Indicates whether the buffer can be aggregated
 995 + *     (used in aggregation scheduling)
 996 + */
 997 +enum buffer_type {
 998 +       BUF_AMPDU               = BIT(0),
 999 +       BUF_AGGR                = BIT(1),
1000 +};
1001 +
1002 +#define bf_isampdu(bf)         (bf->bf_state.bf_type & BUF_AMPDU)
1003 +#define bf_isaggr(bf)          (bf->bf_state.bf_type & BUF_AGGR)
1004 +
1005  struct ath_buf_state {
1006         u8 bf_type;
1007         u8 bfs_paprd;
1008 @@ -278,7 +271,6 @@ struct ath_tx_control {
1009         struct ieee80211_sta *sta;
1010  };
1011
1012 -#define ATH_TX_ERROR        0x01
1013
1014  /**
1015   * @txq_map:  Index is mac80211 queue number.  This is
1016 @@ -372,6 +364,22 @@ struct ath_vif {
1017         struct ath_buf *av_bcbuf;
1018  };
1019
1020 +struct ath9k_vif_iter_data {
1021 +       u8 hw_macaddr[ETH_ALEN]; /* address of the first vif */
1022 +       u8 mask[ETH_ALEN]; /* bssid mask */
1023 +       bool has_hw_macaddr;
1024 +
1025 +       int naps;      /* number of AP vifs */
1026 +       int nmeshes;   /* number of mesh vifs */
1027 +       int nstations; /* number of station vifs */
1028 +       int nwds;      /* number of WDS vifs */
1029 +       int nadhocs;   /* number of adhoc vifs */
1030 +};
1031 +
1032 +void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
1033 +                              struct ieee80211_vif *vif,
1034 +                              struct ath9k_vif_iter_data *iter_data);
1035 +
1036  /*******************/
1037  /* Beacon Handling */
1038  /*******************/
1039 @@ -387,6 +395,9 @@ struct ath_vif {
1040  #define ATH_DEFAULT_BMISS_LIMIT        10
1041  #define IEEE80211_MS_TO_TU(x)           (((x) * 1000) / 1024)
1042
1043 +#define TSF_TO_TU(_h,_l) \
1044 +       ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
1045 +
1046  struct ath_beacon_config {
1047         int beacon_interval;
1048         u16 listen_interval;
1049 @@ -420,12 +431,10 @@ struct ath_beacon {
1050  };
1051
1052  void ath9k_beacon_tasklet(unsigned long data);
1053 -bool ath9k_allow_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif);
1054  void ath9k_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif,
1055                          u32 changed);
1056  void ath9k_beacon_assign_slot(struct ath_softc *sc, struct ieee80211_vif *vif);
1057  void ath9k_beacon_remove_slot(struct ath_softc *sc, struct ieee80211_vif *vif);
1058 -void ath9k_set_tsfadjust(struct ath_softc *sc, struct ieee80211_vif *vif);
1059  void ath9k_set_beacon(struct ath_softc *sc);
1060  bool ath9k_csa_is_finished(struct ath_softc *sc);
1061
1062 @@ -440,10 +449,9 @@ bool ath9k_csa_is_finished(struct ath_so
1063  #define ATH_LONG_CALINTERVAL_INT  1000    /* 1000 ms */
1064  #define ATH_LONG_CALINTERVAL      30000   /* 30 seconds */
1065  #define ATH_RESTART_CALINTERVAL   1200000 /* 20 minutes */
1066 -#define ATH_ANI_MAX_SKIP_COUNT  10
1067 -
1068 -#define ATH_PAPRD_TIMEOUT      100 /* msecs */
1069 -#define ATH_PLL_WORK_INTERVAL   100
1070 +#define ATH_ANI_MAX_SKIP_COUNT    10
1071 +#define ATH_PAPRD_TIMEOUT         100 /* msecs */
1072 +#define ATH_PLL_WORK_INTERVAL     100
1073
1074  void ath_tx_complete_poll_work(struct work_struct *work);
1075  void ath_reset_work(struct work_struct *work);
1076 @@ -459,6 +467,7 @@ void ath_check_ani(struct ath_softc *sc)
1077  int ath_update_survey_stats(struct ath_softc *sc);
1078  void ath_update_survey_nf(struct ath_softc *sc, int channel);
1079  void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type);
1080 +void ath_ps_full_sleep(unsigned long data);
1081
1082  /**********/
1083  /* BTCOEX */
1084 @@ -476,20 +485,19 @@ enum bt_op_flags {
1085  };
1086
1087  struct ath_btcoex {
1088 -       bool hw_timer_enabled;
1089         spinlock_t btcoex_lock;
1090         struct timer_list period_timer; /* Timer for BT period */
1091 +       struct timer_list no_stomp_timer;
1092         u32 bt_priority_cnt;
1093         unsigned long bt_priority_time;
1094         unsigned long op_flags;
1095         int bt_stomp_type; /* Types of BT stomping */
1096 -       u32 btcoex_no_stomp; /* in usec */
1097 +       u32 btcoex_no_stomp; /* in msec */
1098         u32 btcoex_period; /* in msec */
1099 -       u32 btscan_no_stomp; /* in usec */
1100 +       u32 btscan_no_stomp; /* in msec */
1101         u32 duty_cycle;
1102         u32 bt_wait_time;
1103         int rssi_count;
1104 -       struct ath_gen_timer *no_stomp_timer; /* Timer for no BT stomping */
1105         struct ath_mci_profile mci;
1106         u8 stomp_audio;
1107  };
1108 @@ -537,12 +545,6 @@ static inline int ath9k_dump_btcoex(stru
1109  }
1110  #endif /* CPTCFG_ATH9K_BTCOEX_SUPPORT */
1111
1112 -struct ath9k_wow_pattern {
1113 -       u8 pattern_bytes[MAX_PATTERN_SIZE];
1114 -       u8 mask_bytes[MAX_PATTERN_SIZE];
1115 -       u32 pattern_len;
1116 -};
1117 -
1118  /********************/
1119  /*   LED Control    */
1120  /********************/
1121 @@ -570,6 +572,40 @@ static inline void ath_fill_led_pin(stru
1122  }
1123  #endif
1124
1125 +/************************/
1126 +/* Wake on Wireless LAN */
1127 +/************************/
1128 +
1129 +struct ath9k_wow_pattern {
1130 +       u8 pattern_bytes[MAX_PATTERN_SIZE];
1131 +       u8 mask_bytes[MAX_PATTERN_SIZE];
1132 +       u32 pattern_len;
1133 +};
1134 +
1135 +#ifdef CPTCFG_ATH9K_WOW
1136 +void ath9k_init_wow(struct ieee80211_hw *hw);
1137 +int ath9k_suspend(struct ieee80211_hw *hw,
1138 +                 struct cfg80211_wowlan *wowlan);
1139 +int ath9k_resume(struct ieee80211_hw *hw);
1140 +void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled);
1141 +#else
1142 +static inline void ath9k_init_wow(struct ieee80211_hw *hw)
1143 +{
1144 +}
1145 +static inline int ath9k_suspend(struct ieee80211_hw *hw,
1146 +                               struct cfg80211_wowlan *wowlan)
1147 +{
1148 +       return 0;
1149 +}
1150 +static inline int ath9k_resume(struct ieee80211_hw *hw)
1151 +{
1152 +       return 0;
1153 +}
1154 +static inline void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled)
1155 +{
1156 +}
1157 +#endif /* CONFIG_ATH9K_WOW */
1158 +
1159  /*******************************/
1160  /* Antenna diversity/combining */
1161  /*******************************/
1162 @@ -632,28 +668,24 @@ void ath_ant_comb_scan(struct ath_softc
1163  /* Main driver core */
1164  /********************/
1165
1166 -#define ATH9K_PCI_CUS198      0x0001
1167 -#define ATH9K_PCI_CUS230      0x0002
1168 -#define ATH9K_PCI_CUS217      0x0004
1169 -#define ATH9K_PCI_CUS252      0x0008
1170 -#define ATH9K_PCI_WOW         0x0010
1171 -#define ATH9K_PCI_BT_ANT_DIV  0x0020
1172 -#define ATH9K_PCI_D3_L1_WAR   0x0040
1173 -#define ATH9K_PCI_AR9565_1ANT 0x0080
1174 -#define ATH9K_PCI_AR9565_2ANT 0x0100
1175 +#define ATH9K_PCI_CUS198          0x0001
1176 +#define ATH9K_PCI_CUS230          0x0002
1177 +#define ATH9K_PCI_CUS217          0x0004
1178 +#define ATH9K_PCI_CUS252          0x0008
1179 +#define ATH9K_PCI_WOW             0x0010
1180 +#define ATH9K_PCI_BT_ANT_DIV      0x0020
1181 +#define ATH9K_PCI_D3_L1_WAR       0x0040
1182 +#define ATH9K_PCI_AR9565_1ANT     0x0080
1183 +#define ATH9K_PCI_AR9565_2ANT     0x0100
1184 +#define ATH9K_PCI_NO_PLL_PWRSAVE  0x0200
1185
1186  /*
1187   * Default cache line size, in bytes.
1188   * Used when PCI device not fully initialized by bootrom/BIOS
1189  */
1190  #define DEFAULT_CACHELINE       32
1191 -#define ATH_REGCLASSIDS_MAX     10
1192  #define ATH_CABQ_READY_TIME     80      /* % of beacon interval */
1193 -#define ATH_MAX_SW_RETRIES      30
1194 -#define ATH_CHAN_MAX            255
1195 -
1196  #define ATH_TXPOWER_MAX         100     /* .5 dBm units */
1197 -#define ATH_RATE_DUMMY_MARKER   0
1198
1199  enum sc_op_flags {
1200         SC_OP_INVALID,
1201 @@ -672,37 +704,6 @@ enum sc_op_flags {
1202  #define PS_BEACON_SYNC            BIT(4)
1203  #define PS_WAIT_FOR_ANI           BIT(5)
1204
1205 -struct ath_rate_table;
1206 -
1207 -struct ath9k_vif_iter_data {
1208 -       u8 hw_macaddr[ETH_ALEN]; /* address of the first vif */
1209 -       u8 mask[ETH_ALEN]; /* bssid mask */
1210 -       bool has_hw_macaddr;
1211 -
1212 -       int naps;      /* number of AP vifs */
1213 -       int nmeshes;   /* number of mesh vifs */
1214 -       int nstations; /* number of station vifs */
1215 -       int nwds;      /* number of WDS vifs */
1216 -       int nadhocs;   /* number of adhoc vifs */
1217 -};
1218 -
1219 -/* enum spectral_mode:
1220 - *
1221 - * @SPECTRAL_DISABLED: spectral mode is disabled
1222 - * @SPECTRAL_BACKGROUND: hardware sends samples when it is not busy with
1223 - *     something else.
1224 - * @SPECTRAL_MANUAL: spectral scan is enabled, triggering for samples
1225 - *     is performed manually.
1226 - * @SPECTRAL_CHANSCAN: Like manual, but also triggered when changing channels
1227 - *     during a channel scan.
1228 - */
1229 -enum spectral_mode {
1230 -       SPECTRAL_DISABLED = 0,
1231 -       SPECTRAL_BACKGROUND,
1232 -       SPECTRAL_MANUAL,
1233 -       SPECTRAL_CHANSCAN,
1234 -};
1235 -
1236  struct ath_softc {
1237         struct ieee80211_hw *hw;
1238         struct device *dev;
1239 @@ -723,6 +724,7 @@ struct ath_softc {
1240         struct work_struct hw_check_work;
1241         struct work_struct hw_reset_work;
1242         struct completion paprd_complete;
1243 +       wait_queue_head_t tx_wait;
1244
1245         unsigned int hw_busy_count;
1246         unsigned long sc_flags;
1247 @@ -759,6 +761,7 @@ struct ath_softc {
1248         struct delayed_work tx_complete_work;
1249         struct delayed_work hw_pll_work;
1250         struct timer_list rx_poll_timer;
1251 +       struct timer_list sleep_timer;
1252
1253  #ifdef CPTCFG_ATH9K_BTCOEX_SUPPORT
1254         struct ath_btcoex btcoex;
1255 @@ -783,199 +786,54 @@ struct ath_softc {
1256         bool tx99_state;
1257         s16 tx99_power;
1258
1259 -#ifdef CONFIG_PM_SLEEP
1260 +#ifdef CONFIG_ATH9K_WOW
1261         atomic_t wow_got_bmiss_intr;
1262         atomic_t wow_sleep_proc_intr; /* in the middle of WoW sleep ? */
1263         u32 wow_intr_before_sleep;
1264  #endif
1265  };
1266
1267 -#define SPECTRAL_SCAN_BITMASK          0x10
1268 -/* Radar info packet format, used for DFS and spectral formats. */
1269 -struct ath_radar_info {
1270 -       u8 pulse_length_pri;
1271 -       u8 pulse_length_ext;
1272 -       u8 pulse_bw_info;
1273 -} __packed;
1274 -
1275 -/* The HT20 spectral data has 4 bytes of additional information at it's end.
1276 - *
1277 - * [7:0]: all bins {max_magnitude[1:0], bitmap_weight[5:0]}
1278 - * [7:0]: all bins  max_magnitude[9:2]
1279 - * [7:0]: all bins {max_index[5:0], max_magnitude[11:10]}
1280 - * [3:0]: max_exp (shift amount to size max bin to 8-bit unsigned)
1281 - */
1282 -struct ath_ht20_mag_info {
1283 -       u8 all_bins[3];
1284 -       u8 max_exp;
1285 -} __packed;
1286 -
1287 -#define SPECTRAL_HT20_NUM_BINS         56
1288 -
1289 -/* WARNING: don't actually use this struct! MAC may vary the amount of
1290 - * data by -1/+2. This struct is for reference only.
1291 - */
1292 -struct ath_ht20_fft_packet {
1293 -       u8 data[SPECTRAL_HT20_NUM_BINS];
1294 -       struct ath_ht20_mag_info mag_info;
1295 -       struct ath_radar_info radar_info;
1296 -} __packed;
1297 -
1298 -#define SPECTRAL_HT20_TOTAL_DATA_LEN   (sizeof(struct ath_ht20_fft_packet))
1299 -
1300 -/* Dynamic 20/40 mode:
1301 - *
1302 - * [7:0]: lower bins {max_magnitude[1:0], bitmap_weight[5:0]}
1303 - * [7:0]: lower bins  max_magnitude[9:2]
1304 - * [7:0]: lower bins {max_index[5:0], max_magnitude[11:10]}
1305 - * [7:0]: upper bins {max_magnitude[1:0], bitmap_weight[5:0]}
1306 - * [7:0]: upper bins  max_magnitude[9:2]
1307 - * [7:0]: upper bins {max_index[5:0], max_magnitude[11:10]}
1308 - * [3:0]: max_exp (shift amount to size max bin to 8-bit unsigned)
1309 - */
1310 -struct ath_ht20_40_mag_info {
1311 -       u8 lower_bins[3];
1312 -       u8 upper_bins[3];
1313 -       u8 max_exp;
1314 -} __packed;
1315 -
1316 -#define SPECTRAL_HT20_40_NUM_BINS              128
1317 -
1318 -/* WARNING: don't actually use this struct! MAC may vary the amount of
1319 - * data. This struct is for reference only.
1320 - */
1321 -struct ath_ht20_40_fft_packet {
1322 -       u8 data[SPECTRAL_HT20_40_NUM_BINS];
1323 -       struct ath_ht20_40_mag_info mag_info;
1324 -       struct ath_radar_info radar_info;
1325 -} __packed;
1326 -
1327 -
1328 -#define SPECTRAL_HT20_40_TOTAL_DATA_LEN        (sizeof(struct ath_ht20_40_fft_packet))
1329 -
1330 -/* grabs the max magnitude from the all/upper/lower bins */
1331 -static inline u16 spectral_max_magnitude(u8 *bins)
1332 -{
1333 -       return (bins[0] & 0xc0) >> 6 |
1334 -              (bins[1] & 0xff) << 2 |
1335 -              (bins[2] & 0x03) << 10;
1336 -}
1337 +/********/
1338 +/* TX99 */
1339 +/********/
1340
1341 -/* return the max magnitude from the all/upper/lower bins */
1342 -static inline u8 spectral_max_index(u8 *bins)
1343 +#ifdef CONFIG_ATH9K_TX99
1344 +void ath9k_tx99_init_debug(struct ath_softc *sc);
1345 +int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb,
1346 +                   struct ath_tx_control *txctl);
1347 +#else
1348 +static inline void ath9k_tx99_init_debug(struct ath_softc *sc)
1349  {
1350 -       s8 m = (bins[2] & 0xfc) >> 2;
1351 -
1352 -       /* TODO: this still doesn't always report the right values ... */
1353 -       if (m > 32)
1354 -               m |= 0xe0;
1355 -       else
1356 -               m &= ~0xe0;
1357 -
1358 -       return m + 29;
1359  }
1360 -
1361 -/* return the bitmap weight from the all/upper/lower bins */
1362 -static inline u8 spectral_bitmap_weight(u8 *bins)
1363 +static inline int ath9k_tx99_send(struct ath_softc *sc,
1364 +                                 struct sk_buff *skb,
1365 +                                 struct ath_tx_control *txctl)
1366  {
1367 -       return bins[0] & 0x3f;
1368 +       return 0;
1369  }
1370 -
1371 -/* FFT sample format given to userspace via debugfs.
1372 - *
1373 - * Please keep the type/length at the front position and change
1374 - * other fields after adding another sample type
1375 - *
1376 - * TODO: this might need rework when switching to nl80211-based
1377 - * interface.
1378 - */
1379 -enum ath_fft_sample_type {
1380 -       ATH_FFT_SAMPLE_HT20 = 1,
1381 -       ATH_FFT_SAMPLE_HT20_40,
1382 -};
1383 -
1384 -struct fft_sample_tlv {
1385 -       u8 type;        /* see ath_fft_sample */
1386 -       __be16 length;
1387 -       /* type dependent data follows */
1388 -} __packed;
1389 -
1390 -struct fft_sample_ht20 {
1391 -       struct fft_sample_tlv tlv;
1392 -
1393 -       u8 max_exp;
1394 -
1395 -       __be16 freq;
1396 -       s8 rssi;
1397 -       s8 noise;
1398 -
1399 -       __be16 max_magnitude;
1400 -       u8 max_index;
1401 -       u8 bitmap_weight;
1402 -
1403 -       __be64 tsf;
1404 -
1405 -       u8 data[SPECTRAL_HT20_NUM_BINS];
1406 -} __packed;
1407 -
1408 -struct fft_sample_ht20_40 {
1409 -       struct fft_sample_tlv tlv;
1410 -
1411 -       u8 channel_type;
1412 -       __be16 freq;
1413 -
1414 -       s8 lower_rssi;
1415 -       s8 upper_rssi;
1416 -
1417 -       __be64 tsf;
1418 -
1419 -       s8 lower_noise;
1420 -       s8 upper_noise;
1421 -
1422 -       __be16 lower_max_magnitude;
1423 -       __be16 upper_max_magnitude;
1424 -
1425 -       u8 lower_max_index;
1426 -       u8 upper_max_index;
1427 -
1428 -       u8 lower_bitmap_weight;
1429 -       u8 upper_bitmap_weight;
1430 -
1431 -       u8 max_exp;
1432 -
1433 -       u8 data[SPECTRAL_HT20_40_NUM_BINS];
1434 -} __packed;
1435 -
1436 -int ath9k_tx99_init(struct ath_softc *sc);
1437 -void ath9k_tx99_deinit(struct ath_softc *sc);
1438 -int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb,
1439 -                   struct ath_tx_control *txctl);
1440 -
1441 -void ath9k_tasklet(unsigned long data);
1442 -int ath_cabq_update(struct ath_softc *);
1443 +#endif /* CONFIG_ATH9K_TX99 */
1444
1445  static inline void ath_read_cachesize(struct ath_common *common, int *csz)
1446  {
1447         common->bus_ops->read_cachesize(common, csz);
1448  }
1449
1450 -extern struct ieee80211_ops ath9k_ops;
1451 -extern int ath9k_modparam_nohwcrypt;
1452 -extern int led_blink;
1453 -extern bool is_ath9k_unloaded;
1454 -
1455 +void ath9k_tasklet(unsigned long data);
1456 +int ath_cabq_update(struct ath_softc *);
1457  u8 ath9k_parse_mpdudensity(u8 mpdudensity);
1458  irqreturn_t ath_isr(int irq, void *dev);
1459 +int ath_reset(struct ath_softc *sc);
1460 +void ath_cancel_work(struct ath_softc *sc);
1461 +void ath_restart_work(struct ath_softc *sc);
1462  int ath9k_init_device(u16 devid, struct ath_softc *sc,
1463                     const struct ath_bus_ops *bus_ops);
1464  void ath9k_deinit_device(struct ath_softc *sc);
1465 -void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw);
1466  void ath9k_reload_chainmask_settings(struct ath_softc *sc);
1467 -
1468 -void ath9k_spectral_scan_trigger(struct ieee80211_hw *hw);
1469 -int ath9k_spectral_scan_config(struct ieee80211_hw *hw,
1470 -                              enum spectral_mode spectral_mode);
1471 -
1472 +u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate);
1473 +void ath_start_rfkill_poll(struct ath_softc *sc);
1474 +void ath9k_rfkill_poll_state(struct ieee80211_hw *hw);
1475 +void ath9k_ps_wakeup(struct ath_softc *sc);
1476 +void ath9k_ps_restore(struct ath_softc *sc);
1477
1478  #ifdef CPTCFG_ATH9K_PCI
1479  int ath_pci_init(void);
1480 @@ -993,15 +851,4 @@ static inline int ath_ahb_init(void) { r
1481  static inline void ath_ahb_exit(void) {};
1482  #endif
1483
1484 -void ath9k_ps_wakeup(struct ath_softc *sc);
1485 -void ath9k_ps_restore(struct ath_softc *sc);
1486 -
1487 -u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate);
1488 -
1489 -void ath_start_rfkill_poll(struct ath_softc *sc);
1490 -extern void ath9k_rfkill_poll_state(struct ieee80211_hw *hw);
1491 -void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
1492 -                              struct ieee80211_vif *vif,
1493 -                              struct ath9k_vif_iter_data *iter_data);
1494 -
1495  #endif /* ATH9K_H */
1496 --- a/drivers/net/wireless/ath/ath9k/debug.c
1497 +++ b/drivers/net/wireless/ath/ath9k/debug.c
1498 @@ -17,7 +17,6 @@
1499  #include <linux/slab.h>
1500  #include <linux/vmalloc.h>
1501  #include <linux/export.h>
1502 -#include <linux/relay.h>
1503  #include <asm/unaligned.h>
1504
1505  #include "ath9k.h"
1506 @@ -27,6 +26,47 @@
1507  #define REG_READ_D(_ah, _reg) \
1508         ath9k_hw_common(_ah)->ops->read((_ah), (_reg))
1509
1510 +void ath9k_debug_sync_cause(struct ath_softc *sc, u32 sync_cause)
1511 +{
1512 +       if (sync_cause)
1513 +               sc->debug.stats.istats.sync_cause_all++;
1514 +       if (sync_cause & AR_INTR_SYNC_RTC_IRQ)
1515 +               sc->debug.stats.istats.sync_rtc_irq++;
1516 +       if (sync_cause & AR_INTR_SYNC_MAC_IRQ)
1517 +               sc->debug.stats.istats.sync_mac_irq++;
1518 +       if (sync_cause & AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS)
1519 +               sc->debug.stats.istats.eeprom_illegal_access++;
1520 +       if (sync_cause & AR_INTR_SYNC_APB_TIMEOUT)
1521 +               sc->debug.stats.istats.apb_timeout++;
1522 +       if (sync_cause & AR_INTR_SYNC_PCI_MODE_CONFLICT)
1523 +               sc->debug.stats.istats.pci_mode_conflict++;
1524 +       if (sync_cause & AR_INTR_SYNC_HOST1_FATAL)
1525 +               sc->debug.stats.istats.host1_fatal++;
1526 +       if (sync_cause & AR_INTR_SYNC_HOST1_PERR)
1527 +               sc->debug.stats.istats.host1_perr++;
1528 +       if (sync_cause & AR_INTR_SYNC_TRCV_FIFO_PERR)
1529 +               sc->debug.stats.istats.trcv_fifo_perr++;
1530 +       if (sync_cause & AR_INTR_SYNC_RADM_CPL_EP)
1531 +               sc->debug.stats.istats.radm_cpl_ep++;
1532 +       if (sync_cause & AR_INTR_SYNC_RADM_CPL_DLLP_ABORT)
1533 +               sc->debug.stats.istats.radm_cpl_dllp_abort++;
1534 +       if (sync_cause & AR_INTR_SYNC_RADM_CPL_TLP_ABORT)
1535 +               sc->debug.stats.istats.radm_cpl_tlp_abort++;
1536 +       if (sync_cause & AR_INTR_SYNC_RADM_CPL_ECRC_ERR)
1537 +               sc->debug.stats.istats.radm_cpl_ecrc_err++;
1538 +       if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT)
1539 +               sc->debug.stats.istats.radm_cpl_timeout++;
1540 +       if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT)
1541 +               sc->debug.stats.istats.local_timeout++;
1542 +       if (sync_cause & AR_INTR_SYNC_PM_ACCESS)
1543 +               sc->debug.stats.istats.pm_access++;
1544 +       if (sync_cause & AR_INTR_SYNC_MAC_AWAKE)
1545 +               sc->debug.stats.istats.mac_awake++;
1546 +       if (sync_cause & AR_INTR_SYNC_MAC_ASLEEP)
1547 +               sc->debug.stats.istats.mac_asleep++;
1548 +       if (sync_cause & AR_INTR_SYNC_MAC_SLEEP_ACCESS)
1549 +               sc->debug.stats.istats.mac_sleep_access++;
1550 +}
1551
1552  static ssize_t ath9k_debugfs_read_buf(struct file *file, char __user *user_buf,
1553                                       size_t count, loff_t *ppos)
1554 @@ -1016,297 +1056,6 @@ static const struct file_operations fops
1555         .llseek = default_llseek,
1556  };
1557
1558 -static ssize_t read_file_spec_scan_ctl(struct file *file, char __user *user_buf,
1559 -                                      size_t count, loff_t *ppos)
1560 -{
1561 -       struct ath_softc *sc = file->private_data;
1562 -       char *mode = "";
1563 -       unsigned int len;
1564 -
1565 -       switch (sc->spectral_mode) {
1566 -       case SPECTRAL_DISABLED:
1567 -               mode = "disable";
1568 -               break;
1569 -       case SPECTRAL_BACKGROUND:
1570 -               mode = "background";
1571 -               break;
1572 -       case SPECTRAL_CHANSCAN:
1573 -               mode = "chanscan";
1574 -               break;
1575 -       case SPECTRAL_MANUAL:
1576 -               mode = "manual";
1577 -               break;
1578 -       }
1579 -       len = strlen(mode);
1580 -       return simple_read_from_buffer(user_buf, count, ppos, mode, len);
1581 -}
1582 -
1583 -static ssize_t write_file_spec_scan_ctl(struct file *file,
1584 -                                       const char __user *user_buf,
1585 -                                       size_t count, loff_t *ppos)
1586 -{
1587 -       struct ath_softc *sc = file->private_data;
1588 -       struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1589 -       char buf[32];
1590 -       ssize_t len;
1591 -
1592 -       if (config_enabled(CPTCFG_ATH9K_TX99))
1593 -               return -EOPNOTSUPP;
1594 -
1595 -       len = min(count, sizeof(buf) - 1);
1596 -       if (copy_from_user(buf, user_buf, len))
1597 -               return -EFAULT;
1598 -
1599 -       buf[len] = '\0';
1600 -
1601 -       if (strncmp("trigger", buf, 7) == 0) {
1602 -               ath9k_spectral_scan_trigger(sc->hw);
1603 -       } else if (strncmp("background", buf, 9) == 0) {
1604 -               ath9k_spectral_scan_config(sc->hw, SPECTRAL_BACKGROUND);
1605 -               ath_dbg(common, CONFIG, "spectral scan: background mode enabled\n");
1606 -       } else if (strncmp("chanscan", buf, 8) == 0) {
1607 -               ath9k_spectral_scan_config(sc->hw, SPECTRAL_CHANSCAN);
1608 -               ath_dbg(common, CONFIG, "spectral scan: channel scan mode enabled\n");
1609 -       } else if (strncmp("manual", buf, 6) == 0) {
1610 -               ath9k_spectral_scan_config(sc->hw, SPECTRAL_MANUAL);
1611 -               ath_dbg(common, CONFIG, "spectral scan: manual mode enabled\n");
1612 -       } else if (strncmp("disable", buf, 7) == 0) {
1613 -               ath9k_spectral_scan_config(sc->hw, SPECTRAL_DISABLED);
1614 -               ath_dbg(common, CONFIG, "spectral scan: disabled\n");
1615 -       } else {
1616 -               return -EINVAL;
1617 -       }
1618 -
1619 -       return count;
1620 -}
1621 -
1622 -static const struct file_operations fops_spec_scan_ctl = {
1623 -       .read = read_file_spec_scan_ctl,
1624 -       .write = write_file_spec_scan_ctl,
1625 -       .open = simple_open,
1626 -       .owner = THIS_MODULE,
1627 -       .llseek = default_llseek,
1628 -};
1629 -
1630 -static ssize_t read_file_spectral_short_repeat(struct file *file,
1631 -                                              char __user *user_buf,
1632 -                                              size_t count, loff_t *ppos)
1633 -{
1634 -       struct ath_softc *sc = file->private_data;
1635 -       char buf[32];
1636 -       unsigned int len;
1637 -
1638 -       len = sprintf(buf, "%d\n", sc->spec_config.short_repeat);
1639 -       return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1640 -}
1641 -
1642 -static ssize_t write_file_spectral_short_repeat(struct file *file,
1643 -                                               const char __user *user_buf,
1644 -                                               size_t count, loff_t *ppos)
1645 -{
1646 -       struct ath_softc *sc = file->private_data;
1647 -       unsigned long val;
1648 -       char buf[32];
1649 -       ssize_t len;
1650 -
1651 -       len = min(count, sizeof(buf) - 1);
1652 -       if (copy_from_user(buf, user_buf, len))
1653 -               return -EFAULT;
1654 -
1655 -       buf[len] = '\0';
1656 -       if (kstrtoul(buf, 0, &val))
1657 -               return -EINVAL;
1658 -
1659 -       if (val < 0 || val > 1)
1660 -               return -EINVAL;
1661 -
1662 -       sc->spec_config.short_repeat = val;
1663 -       return count;
1664 -}
1665 -
1666 -static const struct file_operations fops_spectral_short_repeat = {
1667 -       .read = read_file_spectral_short_repeat,
1668 -       .write = write_file_spectral_short_repeat,
1669 -       .open = simple_open,
1670 -       .owner = THIS_MODULE,
1671 -       .llseek = default_llseek,
1672 -};
1673 -
1674 -static ssize_t read_file_spectral_count(struct file *file,
1675 -                                       char __user *user_buf,
1676 -                                       size_t count, loff_t *ppos)
1677 -{
1678 -       struct ath_softc *sc = file->private_data;
1679 -       char buf[32];
1680 -       unsigned int len;
1681 -
1682 -       len = sprintf(buf, "%d\n", sc->spec_config.count);
1683 -       return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1684 -}
1685 -
1686 -static ssize_t write_file_spectral_count(struct file *file,
1687 -                                        const char __user *user_buf,
1688 -                                        size_t count, loff_t *ppos)
1689 -{
1690 -       struct ath_softc *sc = file->private_data;
1691 -       unsigned long val;
1692 -       char buf[32];
1693 -       ssize_t len;
1694 -
1695 -       len = min(count, sizeof(buf) - 1);
1696 -       if (copy_from_user(buf, user_buf, len))
1697 -               return -EFAULT;
1698 -
1699 -       buf[len] = '\0';
1700 -       if (kstrtoul(buf, 0, &val))
1701 -               return -EINVAL;
1702 -
1703 -       if (val < 0 || val > 255)
1704 -               return -EINVAL;
1705 -
1706 -       sc->spec_config.count = val;
1707 -       return count;
1708 -}
1709 -
1710 -static const struct file_operations fops_spectral_count = {
1711 -       .read = read_file_spectral_count,
1712 -       .write = write_file_spectral_count,
1713 -       .open = simple_open,
1714 -       .owner = THIS_MODULE,
1715 -       .llseek = default_llseek,
1716 -};
1717 -
1718 -static ssize_t read_file_spectral_period(struct file *file,
1719 -                                        char __user *user_buf,
1720 -                                        size_t count, loff_t *ppos)
1721 -{
1722 -       struct ath_softc *sc = file->private_data;
1723 -       char buf[32];
1724 -       unsigned int len;
1725 -
1726 -       len = sprintf(buf, "%d\n", sc->spec_config.period);
1727 -       return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1728 -}
1729 -
1730 -static ssize_t write_file_spectral_period(struct file *file,
1731 -                                         const char __user *user_buf,
1732 -                                         size_t count, loff_t *ppos)
1733 -{
1734 -       struct ath_softc *sc = file->private_data;
1735 -       unsigned long val;
1736 -       char buf[32];
1737 -       ssize_t len;
1738 -
1739 -       len = min(count, sizeof(buf) - 1);
1740 -       if (copy_from_user(buf, user_buf, len))
1741 -               return -EFAULT;
1742 -
1743 -       buf[len] = '\0';
1744 -       if (kstrtoul(buf, 0, &val))
1745 -               return -EINVAL;
1746 -
1747 -       if (val < 0 || val > 255)
1748 -               return -EINVAL;
1749 -
1750 -       sc->spec_config.period = val;
1751 -       return count;
1752 -}
1753 -
1754 -static const struct file_operations fops_spectral_period = {
1755 -       .read = read_file_spectral_period,
1756 -       .write = write_file_spectral_period,
1757 -       .open = simple_open,
1758 -       .owner = THIS_MODULE,
1759 -       .llseek = default_llseek,
1760 -};
1761 -
1762 -static ssize_t read_file_spectral_fft_period(struct file *file,
1763 -                                            char __user *user_buf,
1764 -                                            size_t count, loff_t *ppos)
1765 -{
1766 -       struct ath_softc *sc = file->private_data;
1767 -       char buf[32];
1768 -       unsigned int len;
1769 -
1770 -       len = sprintf(buf, "%d\n", sc->spec_config.fft_period);
1771 -       return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1772 -}
1773 -
1774 -static ssize_t write_file_spectral_fft_period(struct file *file,
1775 -                                             const char __user *user_buf,
1776 -                                             size_t count, loff_t *ppos)
1777 -{
1778 -       struct ath_softc *sc = file->private_data;
1779 -       unsigned long val;
1780 -       char buf[32];
1781 -       ssize_t len;
1782 -
1783 -       len = min(count, sizeof(buf) - 1);
1784 -       if (copy_from_user(buf, user_buf, len))
1785 -               return -EFAULT;
1786 -
1787 -       buf[len] = '\0';
1788 -       if (kstrtoul(buf, 0, &val))
1789 -               return -EINVAL;
1790 -
1791 -       if (val < 0 || val > 15)
1792 -               return -EINVAL;
1793 -
1794 -       sc->spec_config.fft_period = val;
1795 -       return count;
1796 -}
1797 -
1798 -static const struct file_operations fops_spectral_fft_period = {
1799 -       .read = read_file_spectral_fft_period,
1800 -       .write = write_file_spectral_fft_period,
1801 -       .open = simple_open,
1802 -       .owner = THIS_MODULE,
1803 -       .llseek = default_llseek,
1804 -};
1805 -
1806 -static struct dentry *create_buf_file_handler(const char *filename,
1807 -                                             struct dentry *parent,
1808 -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,3,0))
1809 -                                             umode_t mode,
1810 -#else
1811 -                                             int mode,
1812 -#endif
1813 -                                             struct rchan_buf *buf,
1814 -                                             int *is_global)
1815 -{
1816 -       struct dentry *buf_file;
1817 -
1818 -       buf_file = debugfs_create_file(filename, mode, parent, buf,
1819 -                                      &relay_file_operations);
1820 -       *is_global = 1;
1821 -       return buf_file;
1822 -}
1823 -
1824 -static int remove_buf_file_handler(struct dentry *dentry)
1825 -{
1826 -       debugfs_remove(dentry);
1827 -
1828 -       return 0;
1829 -}
1830 -
1831 -void ath_debug_send_fft_sample(struct ath_softc *sc,
1832 -                              struct fft_sample_tlv *fft_sample_tlv)
1833 -{
1834 -       int length;
1835 -       if (!sc->rfs_chan_spec_scan)
1836 -               return;
1837 -
1838 -       length = __be16_to_cpu(fft_sample_tlv->length) +
1839 -                sizeof(*fft_sample_tlv);
1840 -       relay_write(sc->rfs_chan_spec_scan, fft_sample_tlv, length);
1841 -}
1842 -
1843 -static struct rchan_callbacks rfs_spec_scan_cb = {
1844 -       .create_buf_file = create_buf_file_handler,
1845 -       .remove_buf_file = remove_buf_file_handler,
1846 -};
1847 -
1848 -
1849  static ssize_t read_file_regidx(struct file *file, char __user *user_buf,
1850                                  size_t count, loff_t *ppos)
1851  {
1852 @@ -1776,117 +1525,9 @@ void ath9k_get_et_stats(struct ieee80211
1853
1854  void ath9k_deinit_debug(struct ath_softc *sc)
1855  {
1856 -       if (config_enabled(CPTCFG_ATH9K_DEBUGFS) && sc->rfs_chan_spec_scan) {
1857 -               relay_close(sc->rfs_chan_spec_scan);
1858 -               sc->rfs_chan_spec_scan = NULL;
1859 -       }
1860 +       ath9k_spectral_deinit_debug(sc);
1861  }
1862
1863 -static ssize_t read_file_tx99(struct file *file, char __user *user_buf,
1864 -                             size_t count, loff_t *ppos)
1865 -{
1866 -       struct ath_softc *sc = file->private_data;
1867 -       char buf[3];
1868 -       unsigned int len;
1869 -
1870 -       len = sprintf(buf, "%d\n", sc->tx99_state);
1871 -       return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1872 -}
1873 -
1874 -static ssize_t write_file_tx99(struct file *file, const char __user *user_buf,
1875 -                              size_t count, loff_t *ppos)
1876 -{
1877 -       struct ath_softc *sc = file->private_data;
1878 -       struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1879 -       char buf[32];
1880 -       bool start;
1881 -       ssize_t len;
1882 -       int r;
1883 -
1884 -       if (sc->nvifs > 1)
1885 -               return -EOPNOTSUPP;
1886 -
1887 -       len = min(count, sizeof(buf) - 1);
1888 -       if (copy_from_user(buf, user_buf, len))
1889 -               return -EFAULT;
1890 -
1891 -       if (strtobool(buf, &start))
1892 -               return -EINVAL;
1893 -
1894 -       if (start == sc->tx99_state) {
1895 -               if (!start)
1896 -                       return count;
1897 -               ath_dbg(common, XMIT, "Resetting TX99\n");
1898 -               ath9k_tx99_deinit(sc);
1899 -       }
1900 -
1901 -       if (!start) {
1902 -               ath9k_tx99_deinit(sc);
1903 -               return count;
1904 -       }
1905 -
1906 -       r = ath9k_tx99_init(sc);
1907 -       if (r)
1908 -               return r;
1909 -
1910 -       return count;
1911 -}
1912 -
1913 -static const struct file_operations fops_tx99 = {
1914 -       .read = read_file_tx99,
1915 -       .write = write_file_tx99,
1916 -       .open = simple_open,
1917 -       .owner = THIS_MODULE,
1918 -       .llseek = default_llseek,
1919 -};
1920 -
1921 -static ssize_t read_file_tx99_power(struct file *file,
1922 -                                   char __user *user_buf,
1923 -                                   size_t count, loff_t *ppos)
1924 -{
1925 -       struct ath_softc *sc = file->private_data;
1926 -       char buf[32];
1927 -       unsigned int len;
1928 -
1929 -       len = sprintf(buf, "%d (%d dBm)\n",
1930 -                     sc->tx99_power,
1931 -                     sc->tx99_power / 2);
1932 -
1933 -       return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1934 -}
1935 -
1936 -static ssize_t write_file_tx99_power(struct file *file,
1937 -                                    const char __user *user_buf,
1938 -                                    size_t count, loff_t *ppos)
1939 -{
1940 -       struct ath_softc *sc = file->private_data;
1941 -       int r;
1942 -       u8 tx_power;
1943 -
1944 -       r = kstrtou8_from_user(user_buf, count, 0, &tx_power);
1945 -       if (r)
1946 -               return r;
1947 -
1948 -       if (tx_power > MAX_RATE_POWER)
1949 -               return -EINVAL;
1950 -
1951 -       sc->tx99_power = tx_power;
1952 -
1953 -       ath9k_ps_wakeup(sc);
1954 -       ath9k_hw_tx99_set_txpower(sc->sc_ah, sc->tx99_power);
1955 -       ath9k_ps_restore(sc);
1956 -
1957 -       return count;
1958 -}
1959 -
1960 -static const struct file_operations fops_tx99_power = {
1961 -       .read = read_file_tx99_power,
1962 -       .write = write_file_tx99_power,
1963 -       .open = simple_open,
1964 -       .owner = THIS_MODULE,
1965 -       .llseek = default_llseek,
1966 -};
1967 -
1968  int ath9k_init_debug(struct ath_hw *ah)
1969  {
1970         struct ath_common *common = ath9k_hw_common(ah);
1971 @@ -1903,6 +1544,8 @@ int ath9k_init_debug(struct ath_hw *ah)
1972  #endif
1973
1974         ath9k_dfs_init_debug(sc);
1975 +       ath9k_tx99_init_debug(sc);
1976 +       ath9k_spectral_init_debug(sc);
1977
1978         debugfs_create_file("dma", S_IRUSR, sc->debug.debugfs_phy, sc,
1979                             &fops_dma);
1980 @@ -1949,23 +1592,6 @@ int ath9k_init_debug(struct ath_hw *ah)
1981                             &fops_base_eeprom);
1982         debugfs_create_file("modal_eeprom", S_IRUSR, sc->debug.debugfs_phy, sc,
1983                             &fops_modal_eeprom);
1984 -       sc->rfs_chan_spec_scan = relay_open("spectral_scan",
1985 -                                           sc->debug.debugfs_phy,
1986 -                                           1024, 256, &rfs_spec_scan_cb,
1987 -                                           NULL);
1988 -       debugfs_create_file("spectral_scan_ctl", S_IRUSR | S_IWUSR,
1989 -                           sc->debug.debugfs_phy, sc,
1990 -                           &fops_spec_scan_ctl);
1991 -       debugfs_create_file("spectral_short_repeat", S_IRUSR | S_IWUSR,
1992 -                           sc->debug.debugfs_phy, sc,
1993 -                           &fops_spectral_short_repeat);
1994 -       debugfs_create_file("spectral_count", S_IRUSR | S_IWUSR,
1995 -                           sc->debug.debugfs_phy, sc, &fops_spectral_count);
1996 -       debugfs_create_file("spectral_period", S_IRUSR | S_IWUSR,
1997 -                           sc->debug.debugfs_phy, sc, &fops_spectral_period);
1998 -       debugfs_create_file("spectral_fft_period", S_IRUSR | S_IWUSR,
1999 -                           sc->debug.debugfs_phy, sc,
2000 -                           &fops_spectral_fft_period);
2001         debugfs_create_u32("gpio_mask", S_IRUSR | S_IWUSR,
2002                            sc->debug.debugfs_phy, &sc->sc_ah->gpio_mask);
2003         debugfs_create_u32("gpio_val", S_IRUSR | S_IWUSR,
2004 @@ -1978,15 +1604,6 @@ int ath9k_init_debug(struct ath_hw *ah)
2005         debugfs_create_file("btcoex", S_IRUSR, sc->debug.debugfs_phy, sc,
2006                             &fops_btcoex);
2007  #endif
2008 -       if (config_enabled(CPTCFG_ATH9K_TX99) &&
2009 -           AR_SREV_9300_20_OR_LATER(ah)) {
2010 -               debugfs_create_file("tx99", S_IRUSR | S_IWUSR,
2011 -                                   sc->debug.debugfs_phy, sc,
2012 -                                   &fops_tx99);
2013 -               debugfs_create_file("tx99_power", S_IRUSR | S_IWUSR,
2014 -                                   sc->debug.debugfs_phy, sc,
2015 -                                   &fops_tx99_power);
2016 -       }
2017
2018         return 0;
2019  }
2020 --- a/drivers/net/wireless/ath/ath9k/hw.c
2021 +++ b/drivers/net/wireless/ath/ath9k/hw.c
2022 @@ -17,6 +17,8 @@
2023  #include <linux/io.h>
2024  #include <linux/slab.h>
2025  #include <linux/module.h>
2026 +#include <linux/time.h>
2027 +#include <linux/bitops.h>
2028  #include <asm/unaligned.h>
2029
2030  #include "hw.h"
2031 @@ -83,48 +85,6 @@ static void ath9k_hw_ani_cache_ini_regs(
2032
2033  #ifdef CPTCFG_ATH9K_DEBUGFS
2034
2035 -void ath9k_debug_sync_cause(struct ath_common *common, u32 sync_cause)
2036 -{
2037 -       struct ath_softc *sc = common->priv;
2038 -       if (sync_cause)
2039 -               sc->debug.stats.istats.sync_cause_all++;
2040 -       if (sync_cause & AR_INTR_SYNC_RTC_IRQ)
2041 -               sc->debug.stats.istats.sync_rtc_irq++;
2042 -       if (sync_cause & AR_INTR_SYNC_MAC_IRQ)
2043 -               sc->debug.stats.istats.sync_mac_irq++;
2044 -       if (sync_cause & AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS)
2045 -               sc->debug.stats.istats.eeprom_illegal_access++;
2046 -       if (sync_cause & AR_INTR_SYNC_APB_TIMEOUT)
2047 -               sc->debug.stats.istats.apb_timeout++;
2048 -       if (sync_cause & AR_INTR_SYNC_PCI_MODE_CONFLICT)
2049 -               sc->debug.stats.istats.pci_mode_conflict++;
2050 -       if (sync_cause & AR_INTR_SYNC_HOST1_FATAL)
2051 -               sc->debug.stats.istats.host1_fatal++;
2052 -       if (sync_cause & AR_INTR_SYNC_HOST1_PERR)
2053 -               sc->debug.stats.istats.host1_perr++;
2054 -       if (sync_cause & AR_INTR_SYNC_TRCV_FIFO_PERR)
2055 -               sc->debug.stats.istats.trcv_fifo_perr++;
2056 -       if (sync_cause & AR_INTR_SYNC_RADM_CPL_EP)
2057 -               sc->debug.stats.istats.radm_cpl_ep++;
2058 -       if (sync_cause & AR_INTR_SYNC_RADM_CPL_DLLP_ABORT)
2059 -               sc->debug.stats.istats.radm_cpl_dllp_abort++;
2060 -       if (sync_cause & AR_INTR_SYNC_RADM_CPL_TLP_ABORT)
2061 -               sc->debug.stats.istats.radm_cpl_tlp_abort++;
2062 -       if (sync_cause & AR_INTR_SYNC_RADM_CPL_ECRC_ERR)
2063 -               sc->debug.stats.istats.radm_cpl_ecrc_err++;
2064 -       if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT)
2065 -               sc->debug.stats.istats.radm_cpl_timeout++;
2066 -       if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT)
2067 -               sc->debug.stats.istats.local_timeout++;
2068 -       if (sync_cause & AR_INTR_SYNC_PM_ACCESS)
2069 -               sc->debug.stats.istats.pm_access++;
2070 -       if (sync_cause & AR_INTR_SYNC_MAC_AWAKE)
2071 -               sc->debug.stats.istats.mac_awake++;
2072 -       if (sync_cause & AR_INTR_SYNC_MAC_ASLEEP)
2073 -               sc->debug.stats.istats.mac_asleep++;
2074 -       if (sync_cause & AR_INTR_SYNC_MAC_SLEEP_ACCESS)
2075 -               sc->debug.stats.istats.mac_sleep_access++;
2076 -}
2077  #endif
2078
2079
2080 @@ -438,23 +398,13 @@ static bool ath9k_hw_chip_test(struct at
2081
2082  static void ath9k_hw_init_config(struct ath_hw *ah)
2083  {
2084 -       int i;
2085 -
2086         ah->config.dma_beacon_response_time = 1;
2087         ah->config.sw_beacon_response_time = 6;
2088 -       ah->config.additional_swba_backoff = 0;
2089         ah->config.ack_6mb = 0x0;
2090         ah->config.cwm_ignore_extcca = 0;
2091 -       ah->config.pcie_clock_req = 0;
2092         ah->config.analog_shiftreg = 1;
2093
2094 -       for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2095 -               ah->config.spurchans[i][0] = AR_NO_SPUR;
2096 -               ah->config.spurchans[i][1] = AR_NO_SPUR;
2097 -       }
2098 -
2099         ah->config.rx_intr_mitigation = true;
2100 -       ah->config.pcieSerDesWrite = true;
2101
2102         /*
2103          * We need this for PCI devices only (Cardbus, PCI, miniPCI)
2104 @@ -486,7 +436,6 @@ static void ath9k_hw_init_defaults(struc
2105         ah->hw_version.magic = AR5416_MAGIC;
2106         ah->hw_version.subvendorid = 0;
2107
2108 -       ah->atim_window = 0;
2109         ah->sta_id1_defaults =
2110                 AR_STA_ID1_CRPT_MIC_ENABLE |
2111                 AR_STA_ID1_MCAST_KSRCH;
2112 @@ -549,11 +498,11 @@ static int ath9k_hw_post_init(struct ath
2113          * EEPROM needs to be initialized before we do this.
2114          * This is required for regulatory compliance.
2115          */
2116 -       if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
2117 +       if (AR_SREV_9300_20_OR_LATER(ah)) {
2118                 u16 regdmn = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
2119                 if ((regdmn & 0xF0) == CTL_FCC) {
2120 -                       ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9462_FCC_2GHZ;
2121 -                       ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9462_FCC_5GHZ;
2122 +                       ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ;
2123 +                       ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ;
2124                 }
2125         }
2126
2127 @@ -1282,6 +1231,42 @@ void ath9k_hw_get_delta_slope_vals(struc
2128         *coef_exponent = coef_exp - 16;
2129  }
2130
2131 +/* AR9330 WAR:
2132 + * call external reset function to reset WMAC if:
2133 + * - doing a cold reset
2134 + * - we have pending frames in the TX queues.
2135 + */
2136 +static bool ath9k_hw_ar9330_reset_war(struct ath_hw *ah, int type)
2137 +{
2138 +       int i, npend = 0;
2139 +
2140 +       for (i = 0; i < AR_NUM_QCU; i++) {
2141 +               npend = ath9k_hw_numtxpending(ah, i);
2142 +               if (npend)
2143 +                       break;
2144 +       }
2145 +
2146 +       if (ah->external_reset &&
2147 +           (npend || type == ATH9K_RESET_COLD)) {
2148 +               int reset_err = 0;
2149 +
2150 +               ath_dbg(ath9k_hw_common(ah), RESET,
2151 +                       "reset MAC via external reset\n");
2152 +
2153 +               reset_err = ah->external_reset();
2154 +               if (reset_err) {
2155 +                       ath_err(ath9k_hw_common(ah),
2156 +                               "External reset failed, err=%d\n",
2157 +                               reset_err);
2158 +                       return false;
2159 +               }
2160 +
2161 +               REG_WRITE(ah, AR_RTC_RESET, 1);
2162 +       }
2163 +
2164 +       return true;
2165 +}
2166 +
2167  static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
2168  {
2169         u32 rst_flags;
2170 @@ -1332,38 +1317,8 @@ static bool ath9k_hw_set_reset(struct at
2171         }
2172
2173         if (AR_SREV_9330(ah)) {
2174 -               int npend = 0;
2175 -               int i;
2176 -
2177 -               /* AR9330 WAR:
2178 -                * call external reset function to reset WMAC if:
2179 -                * - doing a cold reset
2180 -                * - we have pending frames in the TX queues
2181 -                */
2182 -
2183 -               for (i = 0; i < AR_NUM_QCU; i++) {
2184 -                       npend = ath9k_hw_numtxpending(ah, i);
2185 -                       if (npend)
2186 -                               break;
2187 -               }
2188 -
2189 -               if (ah->external_reset &&
2190 -                   (npend || type == ATH9K_RESET_COLD)) {
2191 -                       int reset_err = 0;
2192 -
2193 -                       ath_dbg(ath9k_hw_common(ah), RESET,
2194 -                               "reset MAC via external reset\n");
2195 -
2196 -                       reset_err = ah->external_reset();
2197 -                       if (reset_err) {
2198 -                               ath_err(ath9k_hw_common(ah),
2199 -                                       "External reset failed, err=%d\n",
2200 -                                       reset_err);
2201 -                               return false;
2202 -                       }
2203 -
2204 -                       REG_WRITE(ah, AR_RTC_RESET, 1);
2205 -               }
2206 +               if (!ath9k_hw_ar9330_reset_war(ah, type))
2207 +                       return false;
2208         }
2209
2210         if (ath9k_hw_mci_is_enabled(ah))
2211 @@ -1373,7 +1328,12 @@ static bool ath9k_hw_set_reset(struct at
2212
2213         REGWRITE_BUFFER_FLUSH(ah);
2214
2215 -       udelay(50);
2216 +       if (AR_SREV_9300_20_OR_LATER(ah))
2217 +               udelay(50);
2218 +       else if (AR_SREV_9100(ah))
2219 +               udelay(10000);
2220 +       else
2221 +               udelay(100);
2222
2223         REG_WRITE(ah, AR_RTC_RC, 0);
2224         if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
2225 @@ -1409,8 +1369,7 @@ static bool ath9k_hw_set_reset_power_on(
2226
2227         REGWRITE_BUFFER_FLUSH(ah);
2228
2229 -       if (!AR_SREV_9300_20_OR_LATER(ah))
2230 -               udelay(2);
2231 +       udelay(2);
2232
2233         if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
2234                 REG_WRITE(ah, AR_RC, 0);
2235 @@ -1502,8 +1461,9 @@ static bool ath9k_hw_channel_change(stru
2236         int r;
2237
2238         if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) {
2239 -               band_switch = IS_CHAN_5GHZ(ah->curchan) != IS_CHAN_5GHZ(chan);
2240 -               mode_diff = (chan->channelFlags != ah->curchan->channelFlags);
2241 +               u32 flags_diff = chan->channelFlags ^ ah->curchan->channelFlags;
2242 +               band_switch = !!(flags_diff & CHANNEL_5GHZ);
2243 +               mode_diff = !!(flags_diff & ~CHANNEL_HT);
2244         }
2245
2246         for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
2247 @@ -1815,7 +1775,7 @@ static int ath9k_hw_do_fastcc(struct ath
2248          * If cross-band fcc is not supoprted, bail out if channelFlags differ.
2249          */
2250         if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) &&
2251 -           chan->channelFlags != ah->curchan->channelFlags)
2252 +           ((chan->channelFlags ^ ah->curchan->channelFlags) & ~CHANNEL_HT))
2253                 goto fail;
2254
2255         if (!ath9k_hw_check_alive(ah))
2256 @@ -1856,10 +1816,12 @@ int ath9k_hw_reset(struct ath_hw *ah, st
2257                    struct ath9k_hw_cal_data *caldata, bool fastcc)
2258  {
2259         struct ath_common *common = ath9k_hw_common(ah);
2260 +       struct timespec ts;
2261         u32 saveLedState;
2262         u32 saveDefAntenna;
2263         u32 macStaId1;
2264         u64 tsf = 0;
2265 +       s64 usec = 0;
2266         int r;
2267         bool start_mci_reset = false;
2268         bool save_fullsleep = ah->chip_fullsleep;
2269 @@ -1902,10 +1864,10 @@ int ath9k_hw_reset(struct ath_hw *ah, st
2270
2271         macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2272
2273 -       /* For chips on which RTC reset is done, save TSF before it gets cleared */
2274 -       if (AR_SREV_9100(ah) ||
2275 -           (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)))
2276 -               tsf = ath9k_hw_gettsf64(ah);
2277 +       /* Save TSF before chip reset, a cold reset clears it */
2278 +       tsf = ath9k_hw_gettsf64(ah);
2279 +       getrawmonotonic(&ts);
2280 +       usec = ts.tv_sec * 1000000ULL + ts.tv_nsec / 1000;
2281
2282         saveLedState = REG_READ(ah, AR_CFG_LED) &
2283                 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2284 @@ -1938,8 +1900,9 @@ int ath9k_hw_reset(struct ath_hw *ah, st
2285         }
2286
2287         /* Restore TSF */
2288 -       if (tsf)
2289 -               ath9k_hw_settsf64(ah, tsf);
2290 +       getrawmonotonic(&ts);
2291 +       usec = ts.tv_sec * 1000000ULL + ts.tv_nsec / 1000 - usec;
2292 +       ath9k_hw_settsf64(ah, tsf + usec);
2293
2294         if (AR_SREV_9280_20_OR_LATER(ah))
2295                 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
2296 @@ -2261,9 +2224,6 @@ void ath9k_hw_beaconinit(struct ath_hw *
2297         case NL80211_IFTYPE_ADHOC:
2298                 REG_SET_BIT(ah, AR_TXCFG,
2299                             AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2300 -               REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon +
2301 -                         TU_TO_USEC(ah->atim_window ? ah->atim_window : 1));
2302 -               flags |= AR_NDP_TIMER_EN;
2303         case NL80211_IFTYPE_MESH_POINT:
2304         case NL80211_IFTYPE_AP:
2305                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
2306 @@ -2284,7 +2244,6 @@ void ath9k_hw_beaconinit(struct ath_hw *
2307         REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
2308         REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
2309         REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
2310 -       REG_WRITE(ah, AR_NDP_PERIOD, beacon_period);
2311
2312         REGWRITE_BUFFER_FLUSH(ah);
2313
2314 @@ -2301,12 +2260,9 @@ void ath9k_hw_set_sta_beacon_timers(stru
2315
2316         ENABLE_REGWRITE_BUFFER(ah);
2317
2318 -       REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
2319 -
2320 -       REG_WRITE(ah, AR_BEACON_PERIOD,
2321 -                 TU_TO_USEC(bs->bs_intval));
2322 -       REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
2323 -                 TU_TO_USEC(bs->bs_intval));
2324 +       REG_WRITE(ah, AR_NEXT_TBTT_TIMER, bs->bs_nexttbtt);
2325 +       REG_WRITE(ah, AR_BEACON_PERIOD, bs->bs_intval);
2326 +       REG_WRITE(ah, AR_DMA_BEACON_PERIOD, bs->bs_intval);
2327
2328         REGWRITE_BUFFER_FLUSH(ah);
2329
2330 @@ -2334,9 +2290,8 @@ void ath9k_hw_set_sta_beacon_timers(stru
2331
2332         ENABLE_REGWRITE_BUFFER(ah);
2333
2334 -       REG_WRITE(ah, AR_NEXT_DTIM,
2335 -                 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
2336 -       REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
2337 +       REG_WRITE(ah, AR_NEXT_DTIM, bs->bs_nextdtim - SLEEP_SLOP);
2338 +       REG_WRITE(ah, AR_NEXT_TIM, nextTbtt - SLEEP_SLOP);
2339
2340         REG_WRITE(ah, AR_SLEEP1,
2341                   SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
2342 @@ -2350,8 +2305,8 @@ void ath9k_hw_set_sta_beacon_timers(stru
2343         REG_WRITE(ah, AR_SLEEP2,
2344                   SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
2345
2346 -       REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
2347 -       REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
2348 +       REG_WRITE(ah, AR_TIM_PERIOD, beaconintval);
2349 +       REG_WRITE(ah, AR_DTIM_PERIOD, dtimperiod);
2350
2351         REGWRITE_BUFFER_FLUSH(ah);
2352
2353 @@ -2987,20 +2942,6 @@ static const struct ath_gen_timer_config
2354
2355  /* HW generic timer primitives */
2356
2357 -/* compute and clear index of rightmost 1 */
2358 -static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2359 -{
2360 -       u32 b;
2361 -
2362 -       b = *mask;
2363 -       b &= (0-b);
2364 -       *mask &= ~b;
2365 -       b *= debruijn32;
2366 -       b >>= 27;
2367 -
2368 -       return timer_table->gen_timer_index[b];
2369 -}
2370 -
2371  u32 ath9k_hw_gettsf32(struct ath_hw *ah)
2372  {
2373         return REG_READ(ah, AR_TSF_L32);
2374 @@ -3016,6 +2957,10 @@ struct ath_gen_timer *ath_gen_timer_allo
2375         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2376         struct ath_gen_timer *timer;
2377
2378 +       if ((timer_index < AR_FIRST_NDP_TIMER) ||
2379 +               (timer_index >= ATH_MAX_GEN_TIMER))
2380 +               return NULL;
2381 +
2382         timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2383         if (timer == NULL)
2384                 return NULL;
2385 @@ -3033,23 +2978,13 @@ EXPORT_SYMBOL(ath_gen_timer_alloc);
2386
2387  void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2388                               struct ath_gen_timer *timer,
2389 -                             u32 trig_timeout,
2390 +                             u32 timer_next,
2391                               u32 timer_period)
2392  {
2393         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2394 -       u32 tsf, timer_next;
2395 -
2396 -       BUG_ON(!timer_period);
2397 -
2398 -       set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2399 -
2400 -       tsf = ath9k_hw_gettsf32(ah);
2401 +       u32 mask = 0;
2402
2403 -       timer_next = tsf + trig_timeout;
2404 -
2405 -       ath_dbg(ath9k_hw_common(ah), BTCOEX,
2406 -               "current tsf %x period %x timer_next %x\n",
2407 -               tsf, timer_period, timer_next);
2408 +       timer_table->timer_mask |= BIT(timer->index);
2409
2410         /*
2411          * Program generic timer registers
2412 @@ -3075,10 +3010,19 @@ void ath9k_hw_gen_timer_start(struct ath
2413                                        (1 << timer->index));
2414         }
2415
2416 -       /* Enable both trigger and thresh interrupt masks */
2417 -       REG_SET_BIT(ah, AR_IMR_S5,
2418 -               (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2419 -               SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2420 +       if (timer->trigger)
2421 +               mask |= SM(AR_GENTMR_BIT(timer->index),
2422 +                          AR_IMR_S5_GENTIMER_TRIG);
2423 +       if (timer->overflow)
2424 +               mask |= SM(AR_GENTMR_BIT(timer->index),
2425 +                          AR_IMR_S5_GENTIMER_THRESH);
2426 +
2427 +       REG_SET_BIT(ah, AR_IMR_S5, mask);
2428 +
2429 +       if ((ah->imask & ATH9K_INT_GENTIMER) == 0) {
2430 +               ah->imask |= ATH9K_INT_GENTIMER;
2431 +               ath9k_hw_set_interrupts(ah);
2432 +       }
2433  }
2434  EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
2435
2436 @@ -3086,11 +3030,6 @@ void ath9k_hw_gen_timer_stop(struct ath_
2437  {
2438         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2439
2440 -       if ((timer->index < AR_FIRST_NDP_TIMER) ||
2441 -               (timer->index >= ATH_MAX_GEN_TIMER)) {
2442 -               return;
2443 -       }
2444 -
2445         /* Clear generic timer enable bits. */
2446         REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2447                         gen_tmr_configuration[timer->index].mode_mask);
2448 @@ -3110,7 +3049,12 @@ void ath9k_hw_gen_timer_stop(struct ath_
2449                 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2450                 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2451
2452 -       clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
2453 +       timer_table->timer_mask &= ~BIT(timer->index);
2454 +
2455 +       if (timer_table->timer_mask == 0) {
2456 +               ah->imask &= ~ATH9K_INT_GENTIMER;
2457 +               ath9k_hw_set_interrupts(ah);
2458 +       }
2459  }
2460  EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
2461
2462 @@ -3131,32 +3075,32 @@ void ath_gen_timer_isr(struct ath_hw *ah
2463  {
2464         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2465         struct ath_gen_timer *timer;
2466 -       struct ath_common *common = ath9k_hw_common(ah);
2467 -       u32 trigger_mask, thresh_mask, index;
2468 +       unsigned long trigger_mask, thresh_mask;
2469 +       unsigned int index;
2470
2471         /* get hardware generic timer interrupt status */
2472         trigger_mask = ah->intr_gen_timer_trigger;
2473         thresh_mask = ah->intr_gen_timer_thresh;
2474 -       trigger_mask &= timer_table->timer_mask.val;
2475 -       thresh_mask &= timer_table->timer_mask.val;
2476 +       trigger_mask &= timer_table->timer_mask;
2477 +       thresh_mask &= timer_table->timer_mask;
2478
2479 -       trigger_mask &= ~thresh_mask;
2480 -
2481 -       while (thresh_mask) {
2482 -               index = rightmost_index(timer_table, &thresh_mask);
2483 +       for_each_set_bit(index, &thresh_mask, ARRAY_SIZE(timer_table->timers)) {
2484                 timer = timer_table->timers[index];
2485 -               BUG_ON(!timer);
2486 -               ath_dbg(common, BTCOEX, "TSF overflow for Gen timer %d\n",
2487 -                       index);
2488 +               if (!timer)
2489 +                   continue;
2490 +               if (!timer->overflow)
2491 +                   continue;
2492 +
2493 +               trigger_mask &= ~BIT(index);
2494                 timer->overflow(timer->arg);
2495         }
2496
2497 -       while (trigger_mask) {
2498 -               index = rightmost_index(timer_table, &trigger_mask);
2499 +       for_each_set_bit(index, &trigger_mask, ARRAY_SIZE(timer_table->timers)) {
2500                 timer = timer_table->timers[index];
2501 -               BUG_ON(!timer);
2502 -               ath_dbg(common, BTCOEX,
2503 -                       "Gen timer[%d] trigger\n", index);
2504 +               if (!timer)
2505 +                   continue;
2506 +               if (!timer->trigger)
2507 +                   continue;
2508                 timer->trigger(timer->arg);
2509         }
2510  }
2511 --- a/drivers/net/wireless/ath/ath9k/hw.h
2512 +++ b/drivers/net/wireless/ath/ath9k/hw.h
2513 @@ -168,7 +168,7 @@
2514  #define CAB_TIMEOUT_VAL             10
2515  #define BEACON_TIMEOUT_VAL          10
2516  #define MIN_BEACON_TIMEOUT_VAL      1
2517 -#define SLEEP_SLOP                  3
2518 +#define SLEEP_SLOP                  TU_TO_USEC(3)
2519
2520  #define INIT_CONFIG_STATUS          0x00000000
2521  #define INIT_RSSI_THR               0x00000700
2522 @@ -280,11 +280,8 @@ struct ath9k_hw_capabilities {
2523  struct ath9k_ops_config {
2524         int dma_beacon_response_time;
2525         int sw_beacon_response_time;
2526 -       int additional_swba_backoff;
2527         int ack_6mb;
2528         u32 cwm_ignore_extcca;
2529 -       bool pcieSerDesWrite;
2530 -       u8 pcie_clock_req;
2531         u32 pcie_waen;
2532         u8 analog_shiftreg;
2533         u32 ofdm_trig_low;
2534 @@ -295,18 +292,11 @@ struct ath9k_ops_config {
2535         int serialize_regmode;
2536         bool rx_intr_mitigation;
2537         bool tx_intr_mitigation;
2538 -#define SPUR_DISABLE           0
2539 -#define SPUR_ENABLE_IOCTL      1
2540 -#define SPUR_ENABLE_EEPROM     2
2541 -#define AR_SPUR_5413_1         1640
2542 -#define AR_SPUR_5413_2         1200
2543  #define AR_NO_SPUR             0x8000
2544  #define AR_BASE_FREQ_2GHZ      2300
2545  #define AR_BASE_FREQ_5GHZ      4900
2546  #define AR_SPUR_FEEQ_BOUND_HT40 19
2547  #define AR_SPUR_FEEQ_BOUND_HT20 10
2548 -       int spurmode;
2549 -       u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
2550         u8 max_txtrig_level;
2551         u16 ani_poll_interval; /* ANI poll interval in ms */
2552
2553 @@ -316,6 +306,8 @@ struct ath9k_ops_config {
2554         u32 ant_ctrl_comm2g_switch_enable;
2555         bool xatten_margin_cfg;
2556         bool alt_mingainidx;
2557 +       bool no_pll_pwrsave;
2558 +       bool tx_gain_buffalo;
2559  };
2560
2561  enum ath9k_int {
2562 @@ -459,10 +451,6 @@ struct ath9k_beacon_state {
2563         u32 bs_intval;
2564  #define ATH9K_TSFOOR_THRESHOLD    0x00004240 /* 16k us */
2565         u32 bs_dtimperiod;
2566 -       u16 bs_cfpperiod;
2567 -       u16 bs_cfpmaxduration;
2568 -       u32 bs_cfpnext;
2569 -       u16 bs_timoffset;
2570         u16 bs_bmissthreshold;
2571         u32 bs_sleepduration;
2572         u32 bs_tsfoor_threshold;
2573 @@ -498,12 +486,6 @@ struct ath9k_hw_version {
2574
2575  #define AR_GENTMR_BIT(_index)  (1 << (_index))
2576
2577 -/*
2578 - * Using de Bruijin sequence to look up 1's index in a 32 bit number
2579 - * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
2580 - */
2581 -#define debruijn32 0x077CB531U
2582 -
2583  struct ath_gen_timer_configuration {
2584         u32 next_addr;
2585         u32 period_addr;
2586 @@ -519,12 +501,8 @@ struct ath_gen_timer {
2587  };
2588
2589  struct ath_gen_timer_table {
2590 -       u32 gen_timer_index[32];
2591         struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
2592 -       union {
2593 -               unsigned long timer_bits;
2594 -               u16 val;
2595 -       } timer_mask;
2596 +       u16 timer_mask;
2597  };
2598
2599  struct ath_hw_antcomb_conf {
2600 @@ -689,7 +667,8 @@ struct ath_hw_ops {
2601                           struct ath9k_channel *chan,
2602                           u8 rxchainmask,
2603                           bool longcal);
2604 -       bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked);
2605 +       bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked,
2606 +                       u32 *sync_cause_p);
2607         void (*set_txdesc)(struct ath_hw *ah, void *ds,
2608                            struct ath_tx_info *i);
2609         int (*proc_txdesc)(struct ath_hw *ah, void *ds,
2610 @@ -785,7 +764,6 @@ struct ath_hw {
2611         u32 txurn_interrupt_mask;
2612         atomic_t intr_ref_cnt;
2613         bool chip_fullsleep;
2614 -       u32 atim_window;
2615         u32 modes_index;
2616
2617         /* Calibration */
2618 @@ -864,6 +842,7 @@ struct ath_hw {
2619         u32 gpio_mask;
2620         u32 gpio_val;
2621
2622 +       struct ar5416IniArray ini_dfs;
2623         struct ar5416IniArray iniModes;
2624         struct ar5416IniArray iniCommon;
2625         struct ar5416IniArray iniBB_RfGain;
2626 @@ -920,7 +899,7 @@ struct ath_hw {
2627         /* Enterprise mode cap */
2628         u32 ent_mode;
2629
2630 -#ifdef CONFIG_PM_SLEEP
2631 +#ifdef CONFIG_ATH9K_WOW
2632         u32 wow_event_mask;
2633  #endif
2634         bool is_clk_25mhz;
2635 @@ -1016,13 +995,6 @@ bool ath9k_hw_check_alive(struct ath_hw
2636
2637  bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
2638
2639 -#ifdef CPTCFG_ATH9K_DEBUGFS
2640 -void ath9k_debug_sync_cause(struct ath_common *common, u32 sync_cause);
2641 -#else
2642 -static inline void ath9k_debug_sync_cause(struct ath_common *common,
2643 -                                         u32 sync_cause) {}
2644 -#endif
2645 -
2646  /* Generic hw timer primitives */
2647  struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2648                                           void (*trigger)(void *),
2649 @@ -1126,7 +1098,7 @@ ath9k_hw_get_btcoex_scheme(struct ath_hw
2650  #endif /* CPTCFG_ATH9K_BTCOEX_SUPPORT */
2651
2652
2653 -#ifdef CONFIG_PM_SLEEP
2654 +#ifdef CONFIG_ATH9K_WOW
2655  const char *ath9k_hw_wow_event_to_string(u32 wow_event);
2656  void ath9k_hw_wow_apply_pattern(struct ath_hw *ah, u8 *user_pattern,
2657                                 u8 *user_mask, int pattern_count,
2658 --- a/drivers/net/wireless/ath/ath9k/init.c
2659 +++ b/drivers/net/wireless/ath/ath9k/init.c
2660 @@ -470,7 +470,6 @@ static int ath9k_init_queues(struct ath_
2661
2662         sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah);
2663         sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
2664 -
2665         ath_cabq_update(sc);
2666
2667         sc->tx.uapsdq = ath_txq_setup(sc, ATH9K_TX_QUEUE_UAPSD, 0);
2668 @@ -554,7 +553,7 @@ static void ath9k_init_misc(struct ath_s
2669         sc->spec_config.fft_period = 0xF;
2670  }
2671
2672 -static void ath9k_init_platform(struct ath_softc *sc)
2673 +static void ath9k_init_pcoem_platform(struct ath_softc *sc)
2674  {
2675         struct ath_hw *ah = sc->sc_ah;
2676         struct ath9k_hw_capabilities *pCap = &ah->caps;
2677 @@ -609,6 +608,11 @@ static void ath9k_init_platform(struct a
2678                 ah->config.pcie_waen = 0x0040473b;
2679                 ath_info(common, "Enable WAR for ASPM D3/L1\n");
2680         }
2681 +
2682 +       if (sc->driver_data & ATH9K_PCI_NO_PLL_PWRSAVE) {
2683 +               ah->config.no_pll_pwrsave = true;
2684 +               ath_info(common, "Disable PLL PowerSave\n");
2685 +       }
2686  }
2687
2688  static void ath9k_eeprom_request_cb(const struct firmware *eeprom_blob,
2689 @@ -656,6 +660,27 @@ static void ath9k_eeprom_release(struct
2690         release_firmware(sc->sc_ah->eeprom_blob);
2691  }
2692
2693 +static int ath9k_init_soc_platform(struct ath_softc *sc)
2694 +{
2695 +       struct ath9k_platform_data *pdata = sc->dev->platform_data;
2696 +       struct ath_hw *ah = sc->sc_ah;
2697 +       int ret = 0;
2698 +
2699 +       if (!pdata)
2700 +               return 0;
2701 +
2702 +       if (pdata->eeprom_name) {
2703 +               ret = ath9k_eeprom_request(sc, pdata->eeprom_name);
2704 +               if (ret)
2705 +                       return ret;
2706 +       }
2707 +
2708 +       if (pdata->tx_gain_buffalo)
2709 +               ah->config.tx_gain_buffalo = true;
2710 +
2711 +       return ret;
2712 +}
2713 +
2714  static int ath9k_init_softc(u16 devid, struct ath_softc *sc,
2715                             const struct ath_bus_ops *bus_ops)
2716  {
2717 @@ -676,13 +701,13 @@ static int ath9k_init_softc(u16 devid, s
2718         ah->reg_ops.read = ath9k_ioread32;
2719         ah->reg_ops.write = ath9k_iowrite32;
2720         ah->reg_ops.rmw = ath9k_reg_rmw;
2721 -       atomic_set(&ah->intr_ref_cnt, -1);
2722         sc->sc_ah = ah;
2723         pCap = &ah->caps;
2724
2725         common = ath9k_hw_common(ah);
2726         sc->dfs_detector = dfs_pattern_detector_init(common, NL80211_DFS_UNSET);
2727         sc->tx99_power = MAX_RATE_POWER + 1;
2728 +       init_waitqueue_head(&sc->tx_wait);
2729
2730         if (!pdata) {
2731                 ah->ah_flags |= AH_USE_EEPROM;
2732 @@ -708,7 +733,11 @@ static int ath9k_init_softc(u16 devid, s
2733         /*
2734          * Platform quirks.
2735          */
2736 -       ath9k_init_platform(sc);
2737 +       ath9k_init_pcoem_platform(sc);
2738 +
2739 +       ret = ath9k_init_soc_platform(sc);
2740 +       if (ret)
2741 +               return ret;
2742
2743         /*
2744          * Enable WLAN/BT RX Antenna diversity only when:
2745 @@ -722,7 +751,6 @@ static int ath9k_init_softc(u16 devid, s
2746                 common->bt_ant_diversity = 1;
2747
2748         spin_lock_init(&common->cc_lock);
2749 -
2750         spin_lock_init(&sc->sc_serial_rw);
2751         spin_lock_init(&sc->sc_pm_lock);
2752         mutex_init(&sc->mutex);
2753 @@ -730,6 +758,7 @@ static int ath9k_init_softc(u16 devid, s
2754         tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
2755                      (unsigned long)sc);
2756
2757 +       setup_timer(&sc->sleep_timer, ath_ps_full_sleep, (unsigned long)sc);
2758         INIT_WORK(&sc->hw_reset_work, ath_reset_work);
2759         INIT_WORK(&sc->hw_check_work, ath_hw_check);
2760         INIT_WORK(&sc->paprd_work, ath_paprd_calibrate);
2761 @@ -743,12 +772,6 @@ static int ath9k_init_softc(u16 devid, s
2762         ath_read_cachesize(common, &csz);
2763         common->cachelsz = csz << 2; /* convert to bytes */
2764
2765 -       if (pdata && pdata->eeprom_name) {
2766 -               ret = ath9k_eeprom_request(sc, pdata->eeprom_name);
2767 -               if (ret)
2768 -                       return ret;
2769 -       }
2770 -
2771         /* Initializes the hardware for all supported chipsets */
2772         ret = ath9k_hw_init(ah);
2773         if (ret)
2774 @@ -845,7 +868,8 @@ static const struct ieee80211_iface_limi
2775  };
2776
2777  static const struct ieee80211_iface_limit if_dfs_limits[] = {
2778 -       { .max = 1,     .types = BIT(NL80211_IFTYPE_AP) },
2779 +       { .max = 1,     .types = BIT(NL80211_IFTYPE_AP) |
2780 +                                BIT(NL80211_IFTYPE_ADHOC) },
2781  };
2782
2783  static const struct ieee80211_iface_combination if_comb[] = {
2784 @@ -862,21 +886,12 @@ static const struct ieee80211_iface_comb
2785                 .max_interfaces = 1,
2786                 .num_different_channels = 1,
2787                 .beacon_int_infra_match = true,
2788 -               .radar_detect_widths =  BIT(NL80211_CHAN_NO_HT) |
2789 -                                       BIT(NL80211_CHAN_HT20),
2790 +               .radar_detect_widths =  BIT(NL80211_CHAN_WIDTH_20_NOHT) |
2791 +                                       BIT(NL80211_CHAN_WIDTH_20),
2792         }
2793  };
2794
2795 -#ifdef CONFIG_PM
2796 -static const struct wiphy_wowlan_support ath9k_wowlan_support = {
2797 -       .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT,
2798 -       .n_patterns = MAX_NUM_USER_PATTERN,
2799 -       .pattern_min_len = 1,
2800 -       .pattern_max_len = MAX_PATTERN_SIZE,
2801 -};
2802 -#endif
2803 -
2804 -void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
2805 +static void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
2806  {
2807         struct ath_hw *ah = sc->sc_ah;
2808         struct ath_common *common = ath9k_hw_common(ah);
2809 @@ -925,16 +940,6 @@ void ath9k_set_hw_capab(struct ath_softc
2810         hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_5_10_MHZ;
2811         hw->wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH;
2812
2813 -#ifdef CONFIG_PM_SLEEP
2814 -       if ((ah->caps.hw_caps & ATH9K_HW_WOW_DEVICE_CAPABLE) &&
2815 -           (sc->driver_data & ATH9K_PCI_WOW) &&
2816 -           device_can_wakeup(sc->dev))
2817 -               hw->wiphy->wowlan = &ath9k_wowlan_support;
2818 -
2819 -       atomic_set(&sc->wow_sleep_proc_intr, -1);
2820 -       atomic_set(&sc->wow_got_bmiss_intr, -1);
2821 -#endif
2822 -
2823         hw->queues = 4;
2824         hw->max_rates = 4;
2825         hw->channel_change_time = 5000;
2826 @@ -960,6 +965,7 @@ void ath9k_set_hw_capab(struct ath_softc
2827                 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
2828                         &sc->sbands[IEEE80211_BAND_5GHZ];
2829
2830 +       ath9k_init_wow(hw);
2831         ath9k_reload_chainmask_settings(sc);
2832
2833         SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
2834 @@ -1058,6 +1064,7 @@ static void ath9k_deinit_softc(struct at
2835                 if (ATH_TXQ_SETUP(sc, i))
2836                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
2837
2838 +       del_timer_sync(&sc->sleep_timer);
2839         ath9k_hw_deinit(sc->sc_ah);
2840         if (sc->dfs_detector != NULL)
2841                 sc->dfs_detector->exit(sc->dfs_detector);
2842 --- a/drivers/net/wireless/ath/ath9k/main.c
2843 +++ b/drivers/net/wireless/ath/ath9k/main.c
2844 @@ -82,6 +82,22 @@ static bool ath9k_setpower(struct ath_so
2845         return ret;
2846  }
2847
2848 +void ath_ps_full_sleep(unsigned long data)
2849 +{
2850 +       struct ath_softc *sc = (struct ath_softc *) data;
2851 +       struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2852 +       bool reset;
2853 +
2854 +       spin_lock(&common->cc_lock);
2855 +       ath_hw_cycle_counters_update(common);
2856 +       spin_unlock(&common->cc_lock);
2857 +
2858 +       ath9k_hw_setrxabort(sc->sc_ah, 1);
2859 +       ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
2860 +
2861 +       ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
2862 +}
2863 +
2864  void ath9k_ps_wakeup(struct ath_softc *sc)
2865  {
2866         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2867 @@ -92,6 +108,7 @@ void ath9k_ps_wakeup(struct ath_softc *s
2868         if (++sc->ps_usecount != 1)
2869                 goto unlock;
2870
2871 +       del_timer_sync(&sc->sleep_timer);
2872         power_mode = sc->sc_ah->power_mode;
2873         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
2874
2875 @@ -117,17 +134,17 @@ void ath9k_ps_restore(struct ath_softc *
2876         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2877         enum ath9k_power_mode mode;
2878         unsigned long flags;
2879 -       bool reset;
2880
2881         spin_lock_irqsave(&sc->sc_pm_lock, flags);
2882         if (--sc->ps_usecount != 0)
2883                 goto unlock;
2884
2885         if (sc->ps_idle) {
2886 -               ath9k_hw_setrxabort(sc->sc_ah, 1);
2887 -               ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
2888 -               mode = ATH9K_PM_FULL_SLEEP;
2889 -       } else if (sc->ps_enabled &&
2890 +               mod_timer(&sc->sleep_timer, jiffies + HZ / 10);
2891 +               goto unlock;
2892 +       }
2893 +
2894 +       if (sc->ps_enabled &&
2895                    !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
2896                                      PS_WAIT_FOR_CAB |
2897                                      PS_WAIT_FOR_PSPOLL_DATA |
2898 @@ -163,13 +180,13 @@ static void __ath_cancel_work(struct ath
2899  #endif
2900  }
2901
2902 -static void ath_cancel_work(struct ath_softc *sc)
2903 +void ath_cancel_work(struct ath_softc *sc)
2904  {
2905         __ath_cancel_work(sc);
2906         cancel_work_sync(&sc->hw_reset_work);
2907  }
2908
2909 -static void ath_restart_work(struct ath_softc *sc)
2910 +void ath_restart_work(struct ath_softc *sc)
2911  {
2912         ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
2913
2914 @@ -487,8 +504,13 @@ void ath9k_tasklet(unsigned long data)
2915                         ath_tx_edma_tasklet(sc);
2916                 else
2917                         ath_tx_tasklet(sc);
2918 +
2919 +               wake_up(&sc->tx_wait);
2920         }
2921
2922 +       if (status & ATH9K_INT_GENTIMER)
2923 +               ath_gen_timer_isr(sc->sc_ah);
2924 +
2925         ath9k_btcoex_handle_interrupt(sc, status);
2926
2927         /* re-enable hardware interrupt */
2928 @@ -519,6 +541,7 @@ irqreturn_t ath_isr(int irq, void *dev)
2929         struct ath_hw *ah = sc->sc_ah;
2930         struct ath_common *common = ath9k_hw_common(ah);
2931         enum ath9k_int status;
2932 +       u32 sync_cause;
2933         bool sched = false;
2934
2935         /*
2936 @@ -545,7 +568,8 @@ irqreturn_t ath_isr(int irq, void *dev)
2937          * bits we haven't explicitly enabled so we mask the
2938          * value to insure we only process bits we requested.
2939          */
2940 -       ath9k_hw_getisr(ah, &status);   /* NB: clears ISR too */
2941 +       ath9k_hw_getisr(ah, &status, &sync_cause); /* NB: clears ISR too */
2942 +       ath9k_debug_sync_cause(sc, sync_cause);
2943         status &= ah->imask;    /* discard unasked-for bits */
2944
2945         /*
2946 @@ -579,7 +603,8 @@ irqreturn_t ath_isr(int irq, void *dev)
2947
2948                 goto chip_reset;
2949         }
2950 -#ifdef CONFIG_PM_SLEEP
2951 +
2952 +#ifdef CONFIG_ATH9K_WOW
2953         if (status & ATH9K_INT_BMISS) {
2954                 if (atomic_read(&sc->wow_sleep_proc_intr) == 0) {
2955                         ath_dbg(common, ANY, "during WoW we got a BMISS\n");
2956 @@ -588,6 +613,8 @@ irqreturn_t ath_isr(int irq, void *dev)
2957                 }
2958         }
2959  #endif
2960 +
2961 +
2962         if (status & ATH9K_INT_SWBA)
2963                 tasklet_schedule(&sc->bcon_tasklet);
2964
2965 @@ -627,7 +654,7 @@ chip_reset:
2966  #undef SCHED_INTR
2967  }
2968
2969 -static int ath_reset(struct ath_softc *sc)
2970 +int ath_reset(struct ath_softc *sc)
2971  {
2972         int r;
2973
2974 @@ -735,6 +762,8 @@ static int ath9k_start(struct ieee80211_
2975          */
2976         ath9k_cmn_init_crypto(sc->sc_ah);
2977
2978 +       ath9k_hw_reset_tsf(ah);
2979 +
2980         spin_unlock_bh(&sc->sc_pcu_lock);
2981
2982         mutex_unlock(&sc->mutex);
2983 @@ -1635,13 +1664,8 @@ static void ath9k_bss_info_changed(struc
2984         }
2985
2986         if ((changed & BSS_CHANGED_BEACON_ENABLED) ||
2987 -           (changed & BSS_CHANGED_BEACON_INT)) {
2988 -               if (ah->opmode == NL80211_IFTYPE_AP &&
2989 -                   bss_conf->enable_beacon)
2990 -                       ath9k_set_tsfadjust(sc, vif);
2991 -               if (ath9k_allow_beacon_config(sc, vif))
2992 -                       ath9k_beacon_config(sc, vif, changed);
2993 -       }
2994 +           (changed & BSS_CHANGED_BEACON_INT))
2995 +               ath9k_beacon_config(sc, vif, changed);
2996
2997         if (changed & BSS_CHANGED_ERP_SLOT) {
2998                 if (bss_conf->use_short_slot)
2999 @@ -1817,13 +1841,31 @@ static void ath9k_set_coverage_class(str
3000         mutex_unlock(&sc->mutex);
3001  }
3002
3003 +static bool ath9k_has_tx_pending(struct ath_softc *sc)
3004 +{
3005 +       int i, npend;
3006 +
3007 +       for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
3008 +               if (!ATH_TXQ_SETUP(sc, i))
3009 +                       continue;
3010 +
3011 +               if (!sc->tx.txq[i].axq_depth)
3012 +                       continue;
3013 +
3014 +               npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
3015 +               if (npend)
3016 +                       break;
3017 +       }
3018 +
3019 +       return !!npend;
3020 +}
3021 +
3022  static void ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop)
3023  {
3024         struct ath_softc *sc = hw->priv;
3025         struct ath_hw *ah = sc->sc_ah;
3026         struct ath_common *common = ath9k_hw_common(ah);
3027 -       int timeout = 200; /* ms */
3028 -       int i, j;
3029 +       int timeout = HZ / 5; /* 200 ms */
3030         bool drain_txq;
3031
3032         mutex_lock(&sc->mutex);
3033 @@ -1841,25 +1883,9 @@ static void ath9k_flush(struct ieee80211
3034                 return;
3035         }
3036
3037 -       for (j = 0; j < timeout; j++) {
3038 -               bool npend = false;
3039 -
3040 -               if (j)
3041 -                       usleep_range(1000, 2000);
3042 -
3043 -               for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
3044 -                       if (!ATH_TXQ_SETUP(sc, i))
3045 -                               continue;
3046 -
3047 -                       npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
3048 -
3049 -                       if (npend)
3050 -                               break;
3051 -               }
3052 -
3053 -               if (!npend)
3054 -                   break;
3055 -       }
3056 +       if (wait_event_timeout(sc->tx_wait, !ath9k_has_tx_pending(sc),
3057 +                              timeout) > 0)
3058 +               drop = false;
3059
3060         if (drop) {
3061                 ath9k_ps_wakeup(sc);
3062 @@ -2021,333 +2047,6 @@ static int ath9k_get_antenna(struct ieee
3063         return 0;
3064  }
3065
3066 -#ifdef CONFIG_PM_SLEEP
3067 -
3068 -static void ath9k_wow_map_triggers(struct ath_softc *sc,
3069 -                                  struct cfg80211_wowlan *wowlan,
3070 -                                  u32 *wow_triggers)
3071 -{
3072 -       if (wowlan->disconnect)
3073 -               *wow_triggers |= AH_WOW_LINK_CHANGE |
3074 -                                AH_WOW_BEACON_MISS;
3075 -       if (wowlan->magic_pkt)
3076 -               *wow_triggers |= AH_WOW_MAGIC_PATTERN_EN;
3077 -
3078 -       if (wowlan->n_patterns)
3079 -               *wow_triggers |= AH_WOW_USER_PATTERN_EN;
3080 -
3081 -       sc->wow_enabled = *wow_triggers;
3082 -
3083 -}
3084 -
3085 -static void ath9k_wow_add_disassoc_deauth_pattern(struct ath_softc *sc)
3086 -{
3087 -       struct ath_hw *ah = sc->sc_ah;
3088 -       struct ath_common *common = ath9k_hw_common(ah);
3089 -       int pattern_count = 0;
3090 -       int i, byte_cnt;
3091 -       u8 dis_deauth_pattern[MAX_PATTERN_SIZE];
3092 -       u8 dis_deauth_mask[MAX_PATTERN_SIZE];
3093 -
3094 -       memset(dis_deauth_pattern, 0, MAX_PATTERN_SIZE);
3095 -       memset(dis_deauth_mask, 0, MAX_PATTERN_SIZE);
3096 -
3097 -       /*
3098 -        * Create Dissassociate / Deauthenticate packet filter
3099 -        *
3100 -        *     2 bytes        2 byte    6 bytes   6 bytes  6 bytes
3101 -        *  +--------------+----------+---------+--------+--------+----
3102 -        *  + Frame Control+ Duration +   DA    +  SA    +  BSSID +
3103 -        *  +--------------+----------+---------+--------+--------+----
3104 -        *
3105 -        * The above is the management frame format for disassociate/
3106 -        * deauthenticate pattern, from this we need to match the first byte
3107 -        * of 'Frame Control' and DA, SA, and BSSID fields
3108 -        * (skipping 2nd byte of FC and Duration feild.
3109 -        *
3110 -        * Disassociate pattern
3111 -        * --------------------
3112 -        * Frame control = 00 00 1010
3113 -        * DA, SA, BSSID = x:x:x:x:x:x
3114 -        * Pattern will be A0000000 | x:x:x:x:x:x | x:x:x:x:x:x
3115 -        *                          | x:x:x:x:x:x  -- 22 bytes
3116 -        *
3117 -        * Deauthenticate pattern
3118 -        * ----------------------
3119 -        * Frame control = 00 00 1100
3120 -        * DA, SA, BSSID = x:x:x:x:x:x
3121 -        * Pattern will be C0000000 | x:x:x:x:x:x | x:x:x:x:x:x
3122 -        *                          | x:x:x:x:x:x  -- 22 bytes
3123 -        */
3124 -
3125 -       /* Create Disassociate Pattern first */
3126 -
3127 -       byte_cnt = 0;
3128 -
3129 -       /* Fill out the mask with all FF's */
3130 -
3131 -       for (i = 0; i < MAX_PATTERN_MASK_SIZE; i++)
3132 -               dis_deauth_mask[i] = 0xff;
3133 -
3134 -       /* copy the first byte of frame control field */
3135 -       dis_deauth_pattern[byte_cnt] = 0xa0;
3136 -       byte_cnt++;
3137 -
3138 -       /* skip 2nd byte of frame control and Duration field */
3139 -       byte_cnt += 3;
3140 -
3141 -       /*
3142 -        * need not match the destination mac address, it can be a broadcast
3143 -        * mac address or an unicast to this station
3144 -        */
3145 -       byte_cnt += 6;
3146 -
3147 -       /* copy the source mac address */
3148 -       memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
3149 -
3150 -       byte_cnt += 6;
3151 -
3152 -       /* copy the bssid, its same as the source mac address */
3153 -
3154 -       memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
3155 -
3156 -       /* Create Disassociate pattern mask */
3157 -
3158 -       dis_deauth_mask[0] = 0xfe;
3159 -       dis_deauth_mask[1] = 0x03;
3160 -       dis_deauth_mask[2] = 0xc0;
3161 -
3162 -       ath_dbg(common, WOW, "Adding disassoc/deauth patterns for WoW\n");
3163 -
3164 -       ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
3165 -                                  pattern_count, byte_cnt);
3166 -
3167 -       pattern_count++;
3168 -       /*
3169 -        * for de-authenticate pattern, only the first byte of the frame
3170 -        * control field gets changed from 0xA0 to 0xC0
3171 -        */
3172 -       dis_deauth_pattern[0] = 0xC0;
3173 -
3174 -       ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
3175 -                                  pattern_count, byte_cnt);
3176 -
3177 -}
3178 -
3179 -static void ath9k_wow_add_pattern(struct ath_softc *sc,
3180 -                                 struct cfg80211_wowlan *wowlan)
3181 -{
3182 -       struct ath_hw *ah = sc->sc_ah;
3183 -       struct ath9k_wow_pattern *wow_pattern = NULL;
3184 -       struct cfg80211_pkt_pattern *patterns = wowlan->patterns;
3185 -       int mask_len;
3186 -       s8 i = 0;
3187 -
3188 -       if (!wowlan->n_patterns)
3189 -               return;
3190 -
3191 -       /*
3192 -        * Add the new user configured patterns
3193 -        */
3194 -       for (i = 0; i < wowlan->n_patterns; i++) {
3195 -
3196 -               wow_pattern = kzalloc(sizeof(*wow_pattern), GFP_KERNEL);
3197 -
3198 -               if (!wow_pattern)
3199 -                       return;
3200 -
3201 -               /*
3202 -                * TODO: convert the generic user space pattern to
3203 -                * appropriate chip specific/802.11 pattern.
3204 -                */
3205 -
3206 -               mask_len = DIV_ROUND_UP(wowlan->patterns[i].pattern_len, 8);
3207 -               memset(wow_pattern->pattern_bytes, 0, MAX_PATTERN_SIZE);
3208 -               memset(wow_pattern->mask_bytes, 0, MAX_PATTERN_SIZE);
3209 -               memcpy(wow_pattern->pattern_bytes, patterns[i].pattern,
3210 -                      patterns[i].pattern_len);
3211 -               memcpy(wow_pattern->mask_bytes, patterns[i].mask, mask_len);
3212 -               wow_pattern->pattern_len = patterns[i].pattern_len;
3213 -
3214 -               /*
3215 -                * just need to take care of deauth and disssoc pattern,
3216 -                * make sure we don't overwrite them.
3217 -                */
3218 -
3219 -               ath9k_hw_wow_apply_pattern(ah, wow_pattern->pattern_bytes,
3220 -                                          wow_pattern->mask_bytes,
3221 -                                          i + 2,
3222 -                                          wow_pattern->pattern_len);
3223 -               kfree(wow_pattern);
3224 -
3225 -       }
3226 -
3227 -}
3228 -
3229 -static int ath9k_suspend(struct ieee80211_hw *hw,
3230 -                        struct cfg80211_wowlan *wowlan)
3231 -{
3232 -       struct ath_softc *sc = hw->priv;
3233 -       struct ath_hw *ah = sc->sc_ah;
3234 -       struct ath_common *common = ath9k_hw_common(ah);
3235 -       u32 wow_triggers_enabled = 0;
3236 -       int ret = 0;
3237 -
3238 -       mutex_lock(&sc->mutex);
3239 -
3240 -       ath_cancel_work(sc);
3241 -       ath_stop_ani(sc);
3242 -       del_timer_sync(&sc->rx_poll_timer);
3243 -
3244 -       if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
3245 -               ath_dbg(common, ANY, "Device not present\n");
3246 -               ret = -EINVAL;
3247 -               goto fail_wow;
3248 -       }
3249 -
3250 -       if (WARN_ON(!wowlan)) {
3251 -               ath_dbg(common, WOW, "None of the WoW triggers enabled\n");
3252 -               ret = -EINVAL;
3253 -               goto fail_wow;
3254 -       }
3255 -
3256 -       if (!device_can_wakeup(sc->dev)) {
3257 -               ath_dbg(common, WOW, "device_can_wakeup failed, WoW is not enabled\n");
3258 -               ret = 1;
3259 -               goto fail_wow;
3260 -       }
3261 -
3262 -       /*
3263 -        * none of the sta vifs are associated
3264 -        * and we are not currently handling multivif
3265 -        * cases, for instance we have to seperately
3266 -        * configure 'keep alive frame' for each
3267 -        * STA.
3268 -        */
3269 -
3270 -       if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
3271 -               ath_dbg(common, WOW, "None of the STA vifs are associated\n");
3272 -               ret = 1;
3273 -               goto fail_wow;
3274 -       }
3275 -
3276 -       if (sc->nvifs > 1) {
3277 -               ath_dbg(common, WOW, "WoW for multivif is not yet supported\n");
3278 -               ret = 1;
3279 -               goto fail_wow;
3280 -       }
3281 -
3282 -       ath9k_wow_map_triggers(sc, wowlan, &wow_triggers_enabled);
3283 -
3284 -       ath_dbg(common, WOW, "WoW triggers enabled 0x%x\n",
3285 -               wow_triggers_enabled);
3286 -
3287 -       ath9k_ps_wakeup(sc);
3288 -
3289 -       ath9k_stop_btcoex(sc);
3290 -
3291 -       /*
3292 -        * Enable wake up on recieving disassoc/deauth
3293 -        * frame by default.
3294 -        */
3295 -       ath9k_wow_add_disassoc_deauth_pattern(sc);
3296 -
3297 -       if (wow_triggers_enabled & AH_WOW_USER_PATTERN_EN)
3298 -               ath9k_wow_add_pattern(sc, wowlan);
3299 -
3300 -       spin_lock_bh(&sc->sc_pcu_lock);
3301 -       /*
3302 -        * To avoid false wake, we enable beacon miss interrupt only
3303 -        * when we go to sleep. We save the current interrupt mask
3304 -        * so we can restore it after the system wakes up
3305 -        */
3306 -       sc->wow_intr_before_sleep = ah->imask;
3307 -       ah->imask &= ~ATH9K_INT_GLOBAL;
3308 -       ath9k_hw_disable_interrupts(ah);
3309 -       ah->imask = ATH9K_INT_BMISS | ATH9K_INT_GLOBAL;
3310 -       ath9k_hw_set_interrupts(ah);
3311 -       ath9k_hw_enable_interrupts(ah);
3312 -
3313 -       spin_unlock_bh(&sc->sc_pcu_lock);
3314 -
3315 -       /*
3316 -        * we can now sync irq and kill any running tasklets, since we already
3317 -        * disabled interrupts and not holding a spin lock
3318 -        */
3319 -       synchronize_irq(sc->irq);
3320 -       tasklet_kill(&sc->intr_tq);
3321 -
3322 -       ath9k_hw_wow_enable(ah, wow_triggers_enabled);
3323 -
3324 -       ath9k_ps_restore(sc);
3325 -       ath_dbg(common, ANY, "WoW enabled in ath9k\n");
3326 -       atomic_inc(&sc->wow_sleep_proc_intr);
3327 -
3328 -fail_wow:
3329 -       mutex_unlock(&sc->mutex);
3330 -       return ret;
3331 -}
3332 -
3333 -static int ath9k_resume(struct ieee80211_hw *hw)
3334 -{
3335 -       struct ath_softc *sc = hw->priv;
3336 -       struct ath_hw *ah = sc->sc_ah;
3337 -       struct ath_common *common = ath9k_hw_common(ah);
3338 -       u32 wow_status;
3339 -
3340 -       mutex_lock(&sc->mutex);
3341 -
3342 -       ath9k_ps_wakeup(sc);
3343 -
3344 -       spin_lock_bh(&sc->sc_pcu_lock);
3345 -
3346 -       ath9k_hw_disable_interrupts(ah);
3347 -       ah->imask = sc->wow_intr_before_sleep;
3348 -       ath9k_hw_set_interrupts(ah);
3349 -       ath9k_hw_enable_interrupts(ah);
3350 -
3351 -       spin_unlock_bh(&sc->sc_pcu_lock);
3352 -
3353 -       wow_status = ath9k_hw_wow_wakeup(ah);
3354 -
3355 -       if (atomic_read(&sc->wow_got_bmiss_intr) == 0) {
3356 -               /*
3357 -                * some devices may not pick beacon miss
3358 -                * as the reason they woke up so we add
3359 -                * that here for that shortcoming.
3360 -                */
3361 -               wow_status |= AH_WOW_BEACON_MISS;
3362 -               atomic_dec(&sc->wow_got_bmiss_intr);
3363 -               ath_dbg(common, ANY, "Beacon miss interrupt picked up during WoW sleep\n");
3364 -       }
3365 -
3366 -       atomic_dec(&sc->wow_sleep_proc_intr);
3367 -
3368 -       if (wow_status) {
3369 -               ath_dbg(common, ANY, "Waking up due to WoW triggers %s with WoW status = %x\n",
3370 -                       ath9k_hw_wow_event_to_string(wow_status), wow_status);
3371 -       }
3372 -
3373 -       ath_restart_work(sc);
3374 -       ath9k_start_btcoex(sc);
3375 -
3376 -       ath9k_ps_restore(sc);
3377 -       mutex_unlock(&sc->mutex);
3378 -
3379 -       return 0;
3380 -}
3381 -
3382 -static void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled)
3383 -{
3384 -       struct ath_softc *sc = hw->priv;
3385 -
3386 -       mutex_lock(&sc->mutex);
3387 -       device_init_wakeup(sc->dev, 1);
3388 -       device_set_wakeup_enable(sc->dev, enabled);
3389 -       mutex_unlock(&sc->mutex);
3390 -}
3391 -
3392 -#endif
3393  static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
3394  {
3395         struct ath_softc *sc = hw->priv;
3396 @@ -2373,134 +2072,6 @@ static void ath9k_channel_switch_beacon(
3397         sc->csa_vif = vif;
3398  }
3399
3400 -static void ath9k_tx99_stop(struct ath_softc *sc)
3401 -{
3402 -       struct ath_hw *ah = sc->sc_ah;
3403 -       struct ath_common *common = ath9k_hw_common(ah);
3404 -
3405 -       ath_drain_all_txq(sc);
3406 -       ath_startrecv(sc);
3407 -
3408 -       ath9k_hw_set_interrupts(ah);
3409 -       ath9k_hw_enable_interrupts(ah);
3410 -
3411 -       ieee80211_wake_queues(sc->hw);
3412 -
3413 -       kfree_skb(sc->tx99_skb);
3414 -       sc->tx99_skb = NULL;
3415 -       sc->tx99_state = false;
3416 -
3417 -       ath9k_hw_tx99_stop(sc->sc_ah);
3418 -       ath_dbg(common, XMIT, "TX99 stopped\n");
3419 -}
3420 -
3421 -static struct sk_buff *ath9k_build_tx99_skb(struct ath_softc *sc)
3422 -{
3423 -       static u8 PN9Data[] = {0xff, 0x87, 0xb8, 0x59, 0xb7, 0xa1, 0xcc, 0x24,
3424 -                              0x57, 0x5e, 0x4b, 0x9c, 0x0e, 0xe9, 0xea, 0x50,
3425 -                              0x2a, 0xbe, 0xb4, 0x1b, 0xb6, 0xb0, 0x5d, 0xf1,
3426 -                              0xe6, 0x9a, 0xe3, 0x45, 0xfd, 0x2c, 0x53, 0x18,
3427 -                              0x0c, 0xca, 0xc9, 0xfb, 0x49, 0x37, 0xe5, 0xa8,
3428 -                              0x51, 0x3b, 0x2f, 0x61, 0xaa, 0x72, 0x18, 0x84,
3429 -                              0x02, 0x23, 0x23, 0xab, 0x63, 0x89, 0x51, 0xb3,
3430 -                              0xe7, 0x8b, 0x72, 0x90, 0x4c, 0xe8, 0xfb, 0xc0};
3431 -       u32 len = 1200;
3432 -       struct ieee80211_hw *hw = sc->hw;
3433 -       struct ieee80211_hdr *hdr;
3434 -       struct ieee80211_tx_info *tx_info;
3435 -       struct sk_buff *skb;
3436 -
3437 -       skb = alloc_skb(len, GFP_KERNEL);
3438 -       if (!skb)
3439 -               return NULL;
3440 -
3441 -       skb_put(skb, len);
3442 -
3443 -       memset(skb->data, 0, len);
3444 -
3445 -       hdr = (struct ieee80211_hdr *)skb->data;
3446 -       hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_DATA);
3447 -       hdr->duration_id = 0;
3448 -
3449 -       memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN);
3450 -       memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN);
3451 -       memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);
3452 -
3453 -       hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
3454 -
3455 -       tx_info = IEEE80211_SKB_CB(skb);
3456 -       memset(tx_info, 0, sizeof(*tx_info));
3457 -       tx_info->band = hw->conf.chandef.chan->band;
3458 -       tx_info->flags = IEEE80211_TX_CTL_NO_ACK;
3459 -       tx_info->control.vif = sc->tx99_vif;
3460 -
3461 -       memcpy(skb->data + sizeof(*hdr), PN9Data, sizeof(PN9Data));
3462 -
3463 -       return skb;
3464 -}
3465 -
3466 -void ath9k_tx99_deinit(struct ath_softc *sc)
3467 -{
3468 -       ath_reset(sc);
3469 -
3470 -       ath9k_ps_wakeup(sc);
3471 -       ath9k_tx99_stop(sc);
3472 -       ath9k_ps_restore(sc);
3473 -}
3474 -
3475 -int ath9k_tx99_init(struct ath_softc *sc)
3476 -{
3477 -       struct ieee80211_hw *hw = sc->hw;
3478 -       struct ath_hw *ah = sc->sc_ah;
3479 -       struct ath_common *common = ath9k_hw_common(ah);
3480 -       struct ath_tx_control txctl;
3481 -       int r;
3482 -
3483 -       if (sc->sc_flags & SC_OP_INVALID) {
3484 -               ath_err(common,
3485 -                       "driver is in invalid state unable to use TX99");
3486 -               return -EINVAL;
3487 -       }
3488 -
3489 -       sc->tx99_skb = ath9k_build_tx99_skb(sc);
3490 -       if (!sc->tx99_skb)
3491 -               return -ENOMEM;
3492 -
3493 -       memset(&txctl, 0, sizeof(txctl));
3494 -       txctl.txq = sc->tx.txq_map[IEEE80211_AC_VO];
3495 -
3496 -       ath_reset(sc);
3497 -
3498 -       ath9k_ps_wakeup(sc);
3499 -
3500 -       ath9k_hw_disable_interrupts(ah);
3501 -       atomic_set(&ah->intr_ref_cnt, -1);
3502 -       ath_drain_all_txq(sc);
3503 -       ath_stoprecv(sc);
3504 -
3505 -       sc->tx99_state = true;
3506 -
3507 -       ieee80211_stop_queues(hw);
3508 -
3509 -       if (sc->tx99_power == MAX_RATE_POWER + 1)
3510 -               sc->tx99_power = MAX_RATE_POWER;
3511 -
3512 -       ath9k_hw_tx99_set_txpower(ah, sc->tx99_power);
3513 -       r = ath9k_tx99_send(sc, sc->tx99_skb, &txctl);
3514 -       if (r) {
3515 -               ath_dbg(common, XMIT, "Failed to xmit TX99 skb\n");
3516 -               return r;
3517 -       }
3518 -
3519 -       ath_dbg(common, XMIT, "TX99 xmit started using %d ( %ddBm)\n",
3520 -               sc->tx99_power,
3521 -               sc->tx99_power / 2);
3522 -
3523 -       /* We leave the harware awake as it will be chugging on */
3524 -
3525 -       return 0;
3526 -}
3527 -
3528  struct ieee80211_ops ath9k_ops = {
3529         .tx                 = ath9k_tx,
3530         .start              = ath9k_start,
3531 @@ -2531,7 +2102,7 @@ struct ieee80211_ops ath9k_ops = {
3532         .set_antenna        = ath9k_set_antenna,
3533         .get_antenna        = ath9k_get_antenna,
3534
3535 -#ifdef CONFIG_PM_SLEEP
3536 +#ifdef CONFIG_ATH9K_WOW
3537         .suspend            = ath9k_suspend,
3538         .resume             = ath9k_resume,
3539         .set_wakeup         = ath9k_set_wakeup,
3540 --- a/drivers/net/wireless/ath/ath9k/wow.c
3541 +++ b/drivers/net/wireless/ath/ath9k/wow.c
3542 @@ -1,5 +1,5 @@
3543  /*
3544 - * Copyright (c) 2012 Qualcomm Atheros, Inc.
3545 + * Copyright (c) 2013 Qualcomm Atheros, Inc.
3546   *
3547   * Permission to use, copy, modify, and/or distribute this software for any
3548   * purpose with or without fee is hereby granted, provided that the above
3549 @@ -14,409 +14,348 @@
3550   * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
3551   */
3552
3553 -#include <linux/export.h>
3554  #include "ath9k.h"
3555 -#include "reg.h"
3556 -#include "hw-ops.h"
3557
3558 -const char *ath9k_hw_wow_event_to_string(u32 wow_event)
3559 +static const struct wiphy_wowlan_support ath9k_wowlan_support = {
3560 +       .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT,
3561 +       .n_patterns = MAX_NUM_USER_PATTERN,
3562 +       .pattern_min_len = 1,
3563 +       .pattern_max_len = MAX_PATTERN_SIZE,
3564 +};
3565 +
3566 +static void ath9k_wow_map_triggers(struct ath_softc *sc,
3567 +                                  struct cfg80211_wowlan *wowlan,
3568 +                                  u32 *wow_triggers)
3569  {
3570 -       if (wow_event & AH_WOW_MAGIC_PATTERN_EN)
3571 -               return "Magic pattern";
3572 -       if (wow_event & AH_WOW_USER_PATTERN_EN)
3573 -               return "User pattern";
3574 -       if (wow_event & AH_WOW_LINK_CHANGE)
3575 -               return "Link change";
3576 -       if (wow_event & AH_WOW_BEACON_MISS)
3577 -               return "Beacon miss";
3578 +       if (wowlan->disconnect)
3579 +               *wow_triggers |= AH_WOW_LINK_CHANGE |
3580 +                                AH_WOW_BEACON_MISS;
3581 +       if (wowlan->magic_pkt)
3582 +               *wow_triggers |= AH_WOW_MAGIC_PATTERN_EN;
3583 +
3584 +       if (wowlan->n_patterns)
3585 +               *wow_triggers |= AH_WOW_USER_PATTERN_EN;
3586 +
3587 +       sc->wow_enabled = *wow_triggers;
3588
3589 -       return  "unknown reason";
3590  }
3591 -EXPORT_SYMBOL(ath9k_hw_wow_event_to_string);
3592
3593 -static void ath9k_hw_set_powermode_wow_sleep(struct ath_hw *ah)
3594 +static void ath9k_wow_add_disassoc_deauth_pattern(struct ath_softc *sc)
3595  {
3596 +       struct ath_hw *ah = sc->sc_ah;
3597         struct ath_common *common = ath9k_hw_common(ah);
3598 +       int pattern_count = 0;
3599 +       int i, byte_cnt;
3600 +       u8 dis_deauth_pattern[MAX_PATTERN_SIZE];
3601 +       u8 dis_deauth_mask[MAX_PATTERN_SIZE];
3602
3603 -       REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
3604 +       memset(dis_deauth_pattern, 0, MAX_PATTERN_SIZE);
3605 +       memset(dis_deauth_mask, 0, MAX_PATTERN_SIZE);
3606
3607 -       /* set rx disable bit */
3608 -       REG_WRITE(ah, AR_CR, AR_CR_RXD);
3609 +       /*
3610 +        * Create Dissassociate / Deauthenticate packet filter
3611 +        *
3612 +        *     2 bytes        2 byte    6 bytes   6 bytes  6 bytes
3613 +        *  +--------------+----------+---------+--------+--------+----
3614 +        *  + Frame Control+ Duration +   DA    +  SA    +  BSSID +
3615 +        *  +--------------+----------+---------+--------+--------+----
3616 +        *
3617 +        * The above is the management frame format for disassociate/
3618 +        * deauthenticate pattern, from this we need to match the first byte
3619 +        * of 'Frame Control' and DA, SA, and BSSID fields
3620 +        * (skipping 2nd byte of FC and Duration feild.
3621 +        *
3622 +        * Disassociate pattern
3623 +        * --------------------
3624 +        * Frame control = 00 00 1010
3625 +        * DA, SA, BSSID = x:x:x:x:x:x
3626 +        * Pattern will be A0000000 | x:x:x:x:x:x | x:x:x:x:x:x
3627 +        *                          | x:x:x:x:x:x  -- 22 bytes
3628 +        *
3629 +        * Deauthenticate pattern
3630 +        * ----------------------
3631 +        * Frame control = 00 00 1100
3632 +        * DA, SA, BSSID = x:x:x:x:x:x
3633 +        * Pattern will be C0000000 | x:x:x:x:x:x | x:x:x:x:x:x
3634 +        *                          | x:x:x:x:x:x  -- 22 bytes
3635 +        */
3636
3637 -       if (!ath9k_hw_wait(ah, AR_CR, AR_CR_RXE, 0, AH_WAIT_TIMEOUT)) {
3638 -               ath_err(common, "Failed to stop Rx DMA in 10ms AR_CR=0x%08x AR_DIAG_SW=0x%08x\n",
3639 -                       REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW));
3640 -               return;
3641 -       }
3642 +       /* Create Disassociate Pattern first */
3643
3644 -       REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_ON_INT);
3645 -}
3646 +       byte_cnt = 0;
3647
3648 -static void ath9k_wow_create_keep_alive_pattern(struct ath_hw *ah)
3649 -{
3650 -       struct ath_common *common = ath9k_hw_common(ah);
3651 -       u8 sta_mac_addr[ETH_ALEN], ap_mac_addr[ETH_ALEN];
3652 -       u32 ctl[13] = {0};
3653 -       u32 data_word[KAL_NUM_DATA_WORDS];
3654 -       u8 i;
3655 -       u32 wow_ka_data_word0;
3656 -
3657 -       memcpy(sta_mac_addr, common->macaddr, ETH_ALEN);
3658 -       memcpy(ap_mac_addr, common->curbssid, ETH_ALEN);
3659 -
3660 -       /* set the transmit buffer */
3661 -       ctl[0] = (KAL_FRAME_LEN | (MAX_RATE_POWER << 16));
3662 -       ctl[1] = 0;
3663 -       ctl[3] = 0xb;   /* OFDM_6M hardware value for this rate */
3664 -       ctl[4] = 0;
3665 -       ctl[7] = (ah->txchainmask) << 2;
3666 -       ctl[2] = 0xf << 16; /* tx_tries 0 */
3667 -
3668 -       for (i = 0; i < KAL_NUM_DESC_WORDS; i++)
3669 -               REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + i * 4), ctl[i]);
3670 -
3671 -       REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + i * 4), ctl[i]);
3672 -
3673 -       data_word[0] = (KAL_FRAME_TYPE << 2) | (KAL_FRAME_SUB_TYPE << 4) |
3674 -                      (KAL_TO_DS << 8) | (KAL_DURATION_ID << 16);
3675 -       data_word[1] = (ap_mac_addr[3] << 24) | (ap_mac_addr[2] << 16) |
3676 -                      (ap_mac_addr[1] << 8) | (ap_mac_addr[0]);
3677 -       data_word[2] = (sta_mac_addr[1] << 24) | (sta_mac_addr[0] << 16) |
3678 -                      (ap_mac_addr[5] << 8) | (ap_mac_addr[4]);
3679 -       data_word[3] = (sta_mac_addr[5] << 24) | (sta_mac_addr[4] << 16) |
3680 -                      (sta_mac_addr[3] << 8) | (sta_mac_addr[2]);
3681 -       data_word[4] = (ap_mac_addr[3] << 24) | (ap_mac_addr[2] << 16) |
3682 -                      (ap_mac_addr[1] << 8) | (ap_mac_addr[0]);
3683 -       data_word[5] = (ap_mac_addr[5] << 8) | (ap_mac_addr[4]);
3684 -
3685 -       if (AR_SREV_9462_20(ah)) {
3686 -               /* AR9462 2.0 has an extra descriptor word (time based
3687 -                * discard) compared to other chips */
3688 -               REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + (12 * 4)), 0);
3689 -               wow_ka_data_word0 = AR_WOW_TXBUF(13);
3690 -       } else {
3691 -               wow_ka_data_word0 = AR_WOW_TXBUF(12);
3692 -       }
3693 +       /* Fill out the mask with all FF's */
3694
3695 -       for (i = 0; i < KAL_NUM_DATA_WORDS; i++)
3696 -               REG_WRITE(ah, (wow_ka_data_word0 + i*4), data_word[i]);
3697 +       for (i = 0; i < MAX_PATTERN_MASK_SIZE; i++)
3698 +               dis_deauth_mask[i] = 0xff;
3699
3700 -}
3701 +       /* copy the first byte of frame control field */
3702 +       dis_deauth_pattern[byte_cnt] = 0xa0;
3703 +       byte_cnt++;
3704
3705 -void ath9k_hw_wow_apply_pattern(struct ath_hw *ah, u8 *user_pattern,
3706 -                               u8 *user_mask, int pattern_count,
3707 -                               int pattern_len)
3708 -{
3709 -       int i;
3710 -       u32 pattern_val, mask_val;
3711 -       u32 set, clr;
3712 +       /* skip 2nd byte of frame control and Duration field */
3713 +       byte_cnt += 3;
3714
3715 -       /* FIXME: should check count by querying the hardware capability */
3716 -       if (pattern_count >= MAX_NUM_PATTERN)
3717 -               return;
3718 +       /*
3719 +        * need not match the destination mac address, it can be a broadcast
3720 +        * mac address or an unicast to this station
3721 +        */
3722 +       byte_cnt += 6;
3723
3724 -       REG_SET_BIT(ah, AR_WOW_PATTERN, BIT(pattern_count));
3725 +       /* copy the source mac address */
3726 +       memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
3727
3728 -       /* set the registers for pattern */
3729 -       for (i = 0; i < MAX_PATTERN_SIZE; i += 4) {
3730 -               memcpy(&pattern_val, user_pattern, 4);
3731 -               REG_WRITE(ah, (AR_WOW_TB_PATTERN(pattern_count) + i),
3732 -                         pattern_val);
3733 -               user_pattern += 4;
3734 -       }
3735 +       byte_cnt += 6;
3736
3737 -       /* set the registers for mask */
3738 -       for (i = 0; i < MAX_PATTERN_MASK_SIZE; i += 4) {
3739 -               memcpy(&mask_val, user_mask, 4);
3740 -               REG_WRITE(ah, (AR_WOW_TB_MASK(pattern_count) + i), mask_val);
3741 -               user_mask += 4;
3742 -       }
3743 +       /* copy the bssid, its same as the source mac address */
3744
3745 -       /* set the pattern length to be matched
3746 -        *
3747 -        * AR_WOW_LENGTH1_REG1
3748 -        * bit 31:24 pattern 0 length
3749 -        * bit 23:16 pattern 1 length
3750 -        * bit 15:8 pattern 2 length
3751 -        * bit 7:0 pattern 3 length
3752 -        *
3753 -        * AR_WOW_LENGTH1_REG2
3754 -        * bit 31:24 pattern 4 length
3755 -        * bit 23:16 pattern 5 length
3756 -        * bit 15:8 pattern 6 length
3757 -        * bit 7:0 pattern 7 length
3758 -        *
3759 -        * the below logic writes out the new
3760 -        * pattern length for the corresponding
3761 -        * pattern_count, while masking out the
3762 -        * other fields
3763 -        */
3764 +       memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
3765
3766 -       ah->wow_event_mask |= BIT(pattern_count + AR_WOW_PAT_FOUND_SHIFT);
3767 +       /* Create Disassociate pattern mask */
3768
3769 -       if (pattern_count < 4) {
3770 -               /* Pattern 0-3 uses AR_WOW_LENGTH1 register */
3771 -               set = (pattern_len & AR_WOW_LENGTH_MAX) <<
3772 -                      AR_WOW_LEN1_SHIFT(pattern_count);
3773 -               clr = AR_WOW_LENGTH1_MASK(pattern_count);
3774 -               REG_RMW(ah, AR_WOW_LENGTH1, set, clr);
3775 -       } else {
3776 -               /* Pattern 4-7 uses AR_WOW_LENGTH2 register */
3777 -               set = (pattern_len & AR_WOW_LENGTH_MAX) <<
3778 -                      AR_WOW_LEN2_SHIFT(pattern_count);
3779 -               clr = AR_WOW_LENGTH2_MASK(pattern_count);
3780 -               REG_RMW(ah, AR_WOW_LENGTH2, set, clr);
3781 -       }
3782 +       dis_deauth_mask[0] = 0xfe;
3783 +       dis_deauth_mask[1] = 0x03;
3784 +       dis_deauth_mask[2] = 0xc0;
3785
3786 -}
3787 -EXPORT_SYMBOL(ath9k_hw_wow_apply_pattern);
3788 +       ath_dbg(common, WOW, "Adding disassoc/deauth patterns for WoW\n");
3789
3790 -u32 ath9k_hw_wow_wakeup(struct ath_hw *ah)
3791 -{
3792 -       u32 wow_status = 0;
3793 -       u32 val = 0, rval;
3794 +       ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
3795 +                                  pattern_count, byte_cnt);
3796
3797 +       pattern_count++;
3798         /*
3799 -        * read the WoW status register to know
3800 -        * the wakeup reason
3801 +        * for de-authenticate pattern, only the first byte of the frame
3802 +        * control field gets changed from 0xA0 to 0xC0
3803          */
3804 -       rval = REG_READ(ah, AR_WOW_PATTERN);
3805 -       val = AR_WOW_STATUS(rval);
3806 +       dis_deauth_pattern[0] = 0xC0;
3807
3808 -       /*
3809 -        * mask only the WoW events that we have enabled. Sometimes
3810 -        * we have spurious WoW events from the AR_WOW_PATTERN
3811 -        * register. This mask will clean it up.
3812 -        */
3813 +       ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
3814 +                                  pattern_count, byte_cnt);
3815
3816 -       val &= ah->wow_event_mask;
3817 +}
3818
3819 -       if (val) {
3820 -               if (val & AR_WOW_MAGIC_PAT_FOUND)
3821 -                       wow_status |= AH_WOW_MAGIC_PATTERN_EN;
3822 -               if (AR_WOW_PATTERN_FOUND(val))
3823 -                       wow_status |= AH_WOW_USER_PATTERN_EN;
3824 -               if (val & AR_WOW_KEEP_ALIVE_FAIL)
3825 -                       wow_status |= AH_WOW_LINK_CHANGE;
3826 -               if (val & AR_WOW_BEACON_FAIL)
3827 -                       wow_status |= AH_WOW_BEACON_MISS;
3828 -       }
3829 +static void ath9k_wow_add_pattern(struct ath_softc *sc,
3830 +                                 struct cfg80211_wowlan *wowlan)
3831 +{
3832 +       struct ath_hw *ah = sc->sc_ah;
3833 +       struct ath9k_wow_pattern *wow_pattern = NULL;
3834 +       struct cfg80211_pkt_pattern *patterns = wowlan->patterns;
3835 +       int mask_len;
3836 +       s8 i = 0;
3837 +
3838 +       if (!wowlan->n_patterns)
3839 +               return;
3840
3841         /*
3842 -        * set and clear WOW_PME_CLEAR registers for the chip to
3843 -        * generate next wow signal.
3844 -        * disable D3 before accessing other registers ?
3845 +        * Add the new user configured patterns
3846          */
3847 +       for (i = 0; i < wowlan->n_patterns; i++) {
3848
3849 -       /* do we need to check the bit value 0x01000000 (7-10) ?? */
3850 -       REG_RMW(ah, AR_PCIE_PM_CTRL, AR_PMCTRL_WOW_PME_CLR,
3851 -               AR_PMCTRL_PWR_STATE_D1D3);
3852 +               wow_pattern = kzalloc(sizeof(*wow_pattern), GFP_KERNEL);
3853
3854 -       /*
3855 -        * clear all events
3856 -        */
3857 -       REG_WRITE(ah, AR_WOW_PATTERN,
3858 -                 AR_WOW_CLEAR_EVENTS(REG_READ(ah, AR_WOW_PATTERN)));
3859 +               if (!wow_pattern)
3860 +                       return;
3861
3862 -       /*
3863 -        * restore the beacon threshold to init value
3864 -        */
3865 -       REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
3866 +               /*
3867 +                * TODO: convert the generic user space pattern to
3868 +                * appropriate chip specific/802.11 pattern.
3869 +                */
3870
3871 -       /*
3872 -        * Restore the way the PCI-E reset, Power-On-Reset, external
3873 -        * PCIE_POR_SHORT pins are tied to its original value.
3874 -        * Previously just before WoW sleep, we untie the PCI-E
3875 -        * reset to our Chip's Power On Reset so that any PCI-E
3876 -        * reset from the bus will not reset our chip
3877 -        */
3878 -       if (ah->is_pciexpress)
3879 -               ath9k_hw_configpcipowersave(ah, false);
3880 +               mask_len = DIV_ROUND_UP(wowlan->patterns[i].pattern_len, 8);
3881 +               memset(wow_pattern->pattern_bytes, 0, MAX_PATTERN_SIZE);
3882 +               memset(wow_pattern->mask_bytes, 0, MAX_PATTERN_SIZE);
3883 +               memcpy(wow_pattern->pattern_bytes, patterns[i].pattern,
3884 +                      patterns[i].pattern_len);
3885 +               memcpy(wow_pattern->mask_bytes, patterns[i].mask, mask_len);
3886 +               wow_pattern->pattern_len = patterns[i].pattern_len;
3887 +
3888 +               /*
3889 +                * just need to take care of deauth and disssoc pattern,
3890 +                * make sure we don't overwrite them.
3891 +                */
3892 +
3893 +               ath9k_hw_wow_apply_pattern(ah, wow_pattern->pattern_bytes,
3894 +                                          wow_pattern->mask_bytes,
3895 +                                          i + 2,
3896 +                                          wow_pattern->pattern_len);
3897 +               kfree(wow_pattern);
3898
3899 -       ah->wow_event_mask = 0;
3900 +       }
3901
3902 -       return wow_status;
3903  }
3904 -EXPORT_SYMBOL(ath9k_hw_wow_wakeup);
3905
3906 -void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable)
3907 +int ath9k_suspend(struct ieee80211_hw *hw,
3908 +                 struct cfg80211_wowlan *wowlan)
3909  {
3910 -       u32 wow_event_mask;
3911 -       u32 set, clr;
3912 +       struct ath_softc *sc = hw->priv;
3913 +       struct ath_hw *ah = sc->sc_ah;
3914 +       struct ath_common *common = ath9k_hw_common(ah);
3915 +       u32 wow_triggers_enabled = 0;
3916 +       int ret = 0;
3917
3918 -       /*
3919 -        * wow_event_mask is a mask to the AR_WOW_PATTERN register to
3920 -        * indicate which WoW events we have enabled. The WoW events
3921 -        * are from the 'pattern_enable' in this function and
3922 -        * 'pattern_count' of ath9k_hw_wow_apply_pattern()
3923 -        */
3924 -       wow_event_mask = ah->wow_event_mask;
3925 +       mutex_lock(&sc->mutex);
3926
3927 -       /*
3928 -        * Untie Power-on-Reset from the PCI-E-Reset. When we are in
3929 -        * WOW sleep, we do want the Reset from the PCI-E to disturb
3930 -        * our hw state
3931 -        */
3932 -       if (ah->is_pciexpress) {
3933 -               /*
3934 -                * we need to untie the internal POR (power-on-reset)
3935 -                * to the external PCI-E reset. We also need to tie
3936 -                * the PCI-E Phy reset to the PCI-E reset.
3937 -                */
3938 -               set = AR_WA_RESET_EN | AR_WA_POR_SHORT;
3939 -               clr = AR_WA_UNTIE_RESET_EN | AR_WA_D3_L1_DISABLE;
3940 -               REG_RMW(ah, AR_WA, set, clr);
3941 +       ath_cancel_work(sc);
3942 +       ath_stop_ani(sc);
3943 +       del_timer_sync(&sc->rx_poll_timer);
3944 +
3945 +       if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
3946 +               ath_dbg(common, ANY, "Device not present\n");
3947 +               ret = -EINVAL;
3948 +               goto fail_wow;
3949         }
3950
3951 -       /*
3952 -        * set the power states appropriately and enable PME
3953 -        */
3954 -       set = AR_PMCTRL_HOST_PME_EN | AR_PMCTRL_PWR_PM_CTRL_ENA |
3955 -             AR_PMCTRL_AUX_PWR_DET | AR_PMCTRL_WOW_PME_CLR;
3956 +       if (WARN_ON(!wowlan)) {
3957 +               ath_dbg(common, WOW, "None of the WoW triggers enabled\n");
3958 +               ret = -EINVAL;
3959 +               goto fail_wow;
3960 +       }
3961
3962 -       /*
3963 -        * set and clear WOW_PME_CLEAR registers for the chip
3964 -        * to generate next wow signal.
3965 -        */
3966 -       REG_SET_BIT(ah, AR_PCIE_PM_CTRL, set);
3967 -       clr = AR_PMCTRL_WOW_PME_CLR;
3968 -       REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, clr);
3969 +       if (!device_can_wakeup(sc->dev)) {
3970 +               ath_dbg(common, WOW, "device_can_wakeup failed, WoW is not enabled\n");
3971 +               ret = 1;
3972 +               goto fail_wow;
3973 +       }
3974
3975         /*
3976 -        * Setup for:
3977 -        *      - beacon misses
3978 -        *      - magic pattern
3979 -        *      - keep alive timeout
3980 -        *      - pattern matching
3981 +        * none of the sta vifs are associated
3982 +        * and we are not currently handling multivif
3983 +        * cases, for instance we have to seperately
3984 +        * configure 'keep alive frame' for each
3985 +        * STA.
3986          */
3987
3988 -       /*
3989 -        * Program default values for pattern backoff, aifs/slot/KAL count,
3990 -        * beacon miss timeout, KAL timeout, etc.
3991 -        */
3992 -       set = AR_WOW_BACK_OFF_SHIFT(AR_WOW_PAT_BACKOFF);
3993 -       REG_SET_BIT(ah, AR_WOW_PATTERN, set);
3994 +       if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
3995 +               ath_dbg(common, WOW, "None of the STA vifs are associated\n");
3996 +               ret = 1;
3997 +               goto fail_wow;
3998 +       }
3999 +
4000 +       if (sc->nvifs > 1) {
4001 +               ath_dbg(common, WOW, "WoW for multivif is not yet supported\n");
4002 +               ret = 1;
4003 +               goto fail_wow;
4004 +       }
4005
4006 -       set = AR_WOW_AIFS_CNT(AR_WOW_CNT_AIFS_CNT) |
4007 -             AR_WOW_SLOT_CNT(AR_WOW_CNT_SLOT_CNT) |
4008 -             AR_WOW_KEEP_ALIVE_CNT(AR_WOW_CNT_KA_CNT);
4009 -       REG_SET_BIT(ah, AR_WOW_COUNT, set);
4010 -
4011 -       if (pattern_enable & AH_WOW_BEACON_MISS)
4012 -               set = AR_WOW_BEACON_TIMO;
4013 -       /* We are not using beacon miss, program a large value */
4014 -       else
4015 -               set = AR_WOW_BEACON_TIMO_MAX;
4016 +       ath9k_wow_map_triggers(sc, wowlan, &wow_triggers_enabled);
4017
4018 -       REG_WRITE(ah, AR_WOW_BCN_TIMO, set);
4019 +       ath_dbg(common, WOW, "WoW triggers enabled 0x%x\n",
4020 +               wow_triggers_enabled);
4021
4022 -       /*
4023 -        * Keep alive timo in ms except AR9280
4024 -        */
4025 -       if (!pattern_enable)
4026 -               set = AR_WOW_KEEP_ALIVE_NEVER;
4027 -       else
4028 -               set = KAL_TIMEOUT * 32;
4029 +       ath9k_ps_wakeup(sc);
4030
4031 -       REG_WRITE(ah, AR_WOW_KEEP_ALIVE_TIMO, set);
4032 +       ath9k_stop_btcoex(sc);
4033
4034         /*
4035 -        * Keep alive delay in us. based on 'power on clock',
4036 -        * therefore in usec
4037 +        * Enable wake up on recieving disassoc/deauth
4038 +        * frame by default.
4039          */
4040 -       set = KAL_DELAY * 1000;
4041 -       REG_WRITE(ah, AR_WOW_KEEP_ALIVE_DELAY, set);
4042 +       ath9k_wow_add_disassoc_deauth_pattern(sc);
4043
4044 -       /*
4045 -        * Create keep alive pattern to respond to beacons
4046 -        */
4047 -       ath9k_wow_create_keep_alive_pattern(ah);
4048 +       if (wow_triggers_enabled & AH_WOW_USER_PATTERN_EN)
4049 +               ath9k_wow_add_pattern(sc, wowlan);
4050
4051 +       spin_lock_bh(&sc->sc_pcu_lock);
4052         /*
4053 -        * Configure MAC WoW Registers
4054 +        * To avoid false wake, we enable beacon miss interrupt only
4055 +        * when we go to sleep. We save the current interrupt mask
4056 +        * so we can restore it after the system wakes up
4057          */
4058 -       set = 0;
4059 -       /* Send keep alive timeouts anyway */
4060 -       clr = AR_WOW_KEEP_ALIVE_AUTO_DIS;
4061 -
4062 -       if (pattern_enable & AH_WOW_LINK_CHANGE)
4063 -               wow_event_mask |= AR_WOW_KEEP_ALIVE_FAIL;
4064 -       else
4065 -               set = AR_WOW_KEEP_ALIVE_FAIL_DIS;
4066 +       sc->wow_intr_before_sleep = ah->imask;
4067 +       ah->imask &= ~ATH9K_INT_GLOBAL;
4068 +       ath9k_hw_disable_interrupts(ah);
4069 +       ah->imask = ATH9K_INT_BMISS | ATH9K_INT_GLOBAL;
4070 +       ath9k_hw_set_interrupts(ah);
4071 +       ath9k_hw_enable_interrupts(ah);
4072
4073 -       set = AR_WOW_KEEP_ALIVE_FAIL_DIS;
4074 -       REG_RMW(ah, AR_WOW_KEEP_ALIVE, set, clr);
4075 +       spin_unlock_bh(&sc->sc_pcu_lock);
4076
4077         /*
4078 -        * we are relying on a bmiss failure. ensure we have
4079 -        * enough threshold to prevent false positives
4080 +        * we can now sync irq and kill any running tasklets, since we already
4081 +        * disabled interrupts and not holding a spin lock
4082          */
4083 -       REG_RMW_FIELD(ah, AR_RSSI_THR, AR_RSSI_THR_BM_THR,
4084 -                     AR_WOW_BMISSTHRESHOLD);
4085 +       synchronize_irq(sc->irq);
4086 +       tasklet_kill(&sc->intr_tq);
4087 +
4088 +       ath9k_hw_wow_enable(ah, wow_triggers_enabled);
4089
4090 -       set = 0;
4091 -       clr = 0;
4092 +       ath9k_ps_restore(sc);
4093 +       ath_dbg(common, ANY, "WoW enabled in ath9k\n");
4094 +       atomic_inc(&sc->wow_sleep_proc_intr);
4095
4096 -       if (pattern_enable & AH_WOW_BEACON_MISS) {
4097 -               set = AR_WOW_BEACON_FAIL_EN;
4098 -               wow_event_mask |= AR_WOW_BEACON_FAIL;
4099 -       } else {
4100 -               clr = AR_WOW_BEACON_FAIL_EN;
4101 +fail_wow:
4102 +       mutex_unlock(&sc->mutex);
4103 +       return ret;
4104 +}
4105 +
4106 +int ath9k_resume(struct ieee80211_hw *hw)
4107 +{
4108 +       struct ath_softc *sc = hw->priv;
4109 +       struct ath_hw *ah = sc->sc_ah;
4110 +       struct ath_common *common = ath9k_hw_common(ah);
4111 +       u32 wow_status;
4112 +
4113 +       mutex_lock(&sc->mutex);
4114 +
4115 +       ath9k_ps_wakeup(sc);
4116 +
4117 +       spin_lock_bh(&sc->sc_pcu_lock);
4118 +
4119 +       ath9k_hw_disable_interrupts(ah);
4120 +       ah->imask = sc->wow_intr_before_sleep;
4121 +       ath9k_hw_set_interrupts(ah);
4122 +       ath9k_hw_enable_interrupts(ah);
4123 +
4124 +       spin_unlock_bh(&sc->sc_pcu_lock);
4125 +
4126 +       wow_status = ath9k_hw_wow_wakeup(ah);
4127 +
4128 +       if (atomic_read(&sc->wow_got_bmiss_intr) == 0) {
4129 +               /*
4130 +                * some devices may not pick beacon miss
4131 +                * as the reason they woke up so we add
4132 +                * that here for that shortcoming.
4133 +                */
4134 +               wow_status |= AH_WOW_BEACON_MISS;
4135 +               atomic_dec(&sc->wow_got_bmiss_intr);
4136 +               ath_dbg(common, ANY, "Beacon miss interrupt picked up during WoW sleep\n");
4137         }
4138
4139 -       REG_RMW(ah, AR_WOW_BCN_EN, set, clr);
4140 +       atomic_dec(&sc->wow_sleep_proc_intr);
4141
4142 -       set = 0;
4143 -       clr = 0;
4144 -       /*
4145 -        * Enable the magic packet registers
4146 -        */
4147 -       if (pattern_enable & AH_WOW_MAGIC_PATTERN_EN) {
4148 -               set = AR_WOW_MAGIC_EN;
4149 -               wow_event_mask |= AR_WOW_MAGIC_PAT_FOUND;
4150 -       } else {
4151 -               clr = AR_WOW_MAGIC_EN;
4152 +       if (wow_status) {
4153 +               ath_dbg(common, ANY, "Waking up due to WoW triggers %s with WoW status = %x\n",
4154 +                       ath9k_hw_wow_event_to_string(wow_status), wow_status);
4155         }
4156 -       set |= AR_WOW_MAC_INTR_EN;
4157 -       REG_RMW(ah, AR_WOW_PATTERN, set, clr);
4158
4159 -       REG_WRITE(ah, AR_WOW_PATTERN_MATCH_LT_256B,
4160 -                 AR_WOW_PATTERN_SUPPORTED);
4161 +       ath_restart_work(sc);
4162 +       ath9k_start_btcoex(sc);
4163
4164 -       /*
4165 -        * Set the power states appropriately and enable PME
4166 -        */
4167 -       clr = 0;
4168 -       set = AR_PMCTRL_PWR_STATE_D1D3 | AR_PMCTRL_HOST_PME_EN |
4169 -             AR_PMCTRL_PWR_PM_CTRL_ENA;
4170 +       ath9k_ps_restore(sc);
4171 +       mutex_unlock(&sc->mutex);
4172
4173 -       clr = AR_PCIE_PM_CTRL_ENA;
4174 -       REG_RMW(ah, AR_PCIE_PM_CTRL, set, clr);
4175 +       return 0;
4176 +}
4177
4178 -       /*
4179 -        * this is needed to prevent the chip waking up
4180 -        * the host within 3-4 seconds with certain
4181 -        * platform/BIOS. The fix is to enable
4182 -        * D1 & D3 to match original definition and
4183 -        * also match the OTP value. Anyway this
4184 -        * is more related to SW WOW.
4185 -        */
4186 -       clr = AR_PMCTRL_PWR_STATE_D1D3;
4187 -       REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, clr);
4188 +void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled)
4189 +{
4190 +       struct ath_softc *sc = hw->priv;
4191
4192 -       set = AR_PMCTRL_PWR_STATE_D1D3_REAL;
4193 -       REG_SET_BIT(ah, AR_PCIE_PM_CTRL, set);
4194 +       mutex_lock(&sc->mutex);
4195 +       device_init_wakeup(sc->dev, 1);
4196 +       device_set_wakeup_enable(sc->dev, enabled);
4197 +       mutex_unlock(&sc->mutex);
4198 +}
4199
4200 -       REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
4201 +void ath9k_init_wow(struct ieee80211_hw *hw)
4202 +{
4203 +       struct ath_softc *sc = hw->priv;
4204
4205 -       /* to bring down WOW power low margin */
4206 -       set = BIT(13);
4207 -       REG_SET_BIT(ah, AR_PCIE_PHY_REG3, set);
4208 -       /* HW WoW */
4209 -       clr = BIT(5);
4210 -       REG_CLR_BIT(ah, AR_PCU_MISC_MODE3, clr);
4211 +       if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_WOW_DEVICE_CAPABLE) &&
4212 +           (sc->driver_data & ATH9K_PCI_WOW) &&
4213 +           device_can_wakeup(sc->dev))
4214 +               hw->wiphy->wowlan = &ath9k_wowlan_support;
4215
4216 -       ath9k_hw_set_powermode_wow_sleep(ah);
4217 -       ah->wow_event_mask = wow_event_mask;
4218 +       atomic_set(&sc->wow_sleep_proc_intr, -1);
4219 +       atomic_set(&sc->wow_got_bmiss_intr, -1);
4220  }
4221 -EXPORT_SYMBOL(ath9k_hw_wow_enable);
4222 --- a/drivers/net/wireless/ath/ath9k/xmit.c
4223 +++ b/drivers/net/wireless/ath/ath9k/xmit.c
4224 @@ -174,14 +174,7 @@ static void ath_txq_skb_done(struct ath_
4225  static struct ath_atx_tid *
4226  ath_get_skb_tid(struct ath_softc *sc, struct ath_node *an, struct sk_buff *skb)
4227  {
4228 -       struct ieee80211_hdr *hdr;
4229 -       u8 tidno = 0;
4230 -
4231 -       hdr = (struct ieee80211_hdr *) skb->data;
4232 -       if (ieee80211_is_data_qos(hdr->frame_control))
4233 -               tidno = ieee80211_get_qos_ctl(hdr)[0];
4234 -
4235 -       tidno &= IEEE80211_QOS_CTL_TID_MASK;
4236 +       u8 tidno = skb->priority & IEEE80211_QOS_CTL_TID_MASK;
4237         return ATH_AN_2_TID(an, tidno);
4238  }
4239
4240 @@ -1276,6 +1269,10 @@ static void ath_tx_fill_desc(struct ath_
4241                                 if (!rts_thresh || (len > rts_thresh))
4242                                         rts = true;
4243                         }
4244 +
4245 +                       if (!aggr)
4246 +                               len = fi->framelen;
4247 +
4248                         ath_buf_set_rate(sc, bf, &info, len, rts);
4249                 }
4250
4251 @@ -1786,6 +1783,9 @@ bool ath_drain_all_txq(struct ath_softc
4252                 if (!ATH_TXQ_SETUP(sc, i))
4253                         continue;
4254
4255 +               if (!sc->tx.txq[i].axq_depth)
4256 +                       continue;
4257 +
4258                 if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum))
4259                         npend |= BIT(i);
4260         }
4261 @@ -2749,6 +2749,8 @@ void ath_tx_node_cleanup(struct ath_soft
4262         }
4263  }
4264
4265 +#ifdef CONFIG_ATH9K_TX99
4266 +
4267  int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb,
4268                     struct ath_tx_control *txctl)
4269  {
4270 @@ -2791,3 +2793,5 @@ int ath9k_tx99_send(struct ath_softc *sc
4271
4272         return 0;
4273  }
4274 +
4275 +#endif /* CONFIG_ATH9K_TX99 */
4276 --- a/drivers/net/wireless/ath/regd.c
4277 +++ b/drivers/net/wireless/ath/regd.c
4278 @@ -37,17 +37,17 @@ static int __ath_regd_init(struct ath_re
4279
4280  /* We enable active scan on these a case by case basis by regulatory domain */
4281  #define ATH9K_2GHZ_CH12_13     REG_RULE(2467-10, 2472+10, 40, 0, 20,\
4282 -                                       NL80211_RRF_PASSIVE_SCAN)
4283 +                                       NL80211_RRF_NO_IR)
4284  #define ATH9K_2GHZ_CH14                REG_RULE(2484-10, 2484+10, 40, 0, 20,\
4285 -                               NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_OFDM)
4286 +                               NL80211_RRF_NO_IR | NL80211_RRF_NO_OFDM)
4287
4288  /* We allow IBSS on these on a case by case basis by regulatory domain */
4289  #define ATH9K_5GHZ_5150_5350   REG_RULE(5150-10, 5350+10, 80, 0, 30,\
4290 -                               NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS)
4291 +                               NL80211_RRF_NO_IR)
4292  #define ATH9K_5GHZ_5470_5850   REG_RULE(5470-10, 5850+10, 80, 0, 30,\
4293 -                               NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS)
4294 +                               NL80211_RRF_NO_IR)
4295  #define ATH9K_5GHZ_5725_5850   REG_RULE(5725-10, 5850+10, 80, 0, 30,\
4296 -                               NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS)
4297 +                               NL80211_RRF_NO_IR)
4298
4299  #define ATH9K_2GHZ_ALL         ATH9K_2GHZ_CH01_11, \
4300                                 ATH9K_2GHZ_CH12_13, \
4301 @@ -224,17 +224,16 @@ ath_reg_apply_beaconing_flags(struct wip
4302                                  * regulatory_hint().
4303                                  */
4304                                 if (!(reg_rule->flags &
4305 -                                   NL80211_RRF_NO_IBSS))
4306 +                                   NL80211_RRF_NO_IR))
4307                                         ch->flags &=
4308 -                                         ~IEEE80211_CHAN_NO_IBSS;
4309 +                                         ~IEEE80211_CHAN_NO_IR;
4310                                 if (!(reg_rule->flags &
4311 -                                   NL80211_RRF_PASSIVE_SCAN))
4312 +                                   NL80211_RRF_NO_IR))
4313                                         ch->flags &=
4314 -                                         ~IEEE80211_CHAN_PASSIVE_SCAN;
4315 +                                         ~IEEE80211_CHAN_NO_IR;
4316                         } else {
4317                                 if (ch->beacon_found)
4318 -                                       ch->flags &= ~(IEEE80211_CHAN_NO_IBSS |
4319 -                                         IEEE80211_CHAN_PASSIVE_SCAN);
4320 +                                       ch->flags &= ~IEEE80211_CHAN_NO_IR;
4321                         }
4322                 }
4323         }
4324 @@ -260,11 +259,11 @@ ath_reg_apply_active_scan_flags(struct w
4325          */
4326         if (initiator != NL80211_REGDOM_SET_BY_COUNTRY_IE) {
4327                 ch = &sband->channels[11]; /* CH 12 */
4328 -               if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
4329 -                       ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
4330 +               if (ch->flags & IEEE80211_CHAN_NO_IR)
4331 +                       ch->flags &= ~IEEE80211_CHAN_NO_IR;
4332                 ch = &sband->channels[12]; /* CH 13 */
4333 -               if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
4334 -                       ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
4335 +               if (ch->flags & IEEE80211_CHAN_NO_IR)
4336 +                       ch->flags &= ~IEEE80211_CHAN_NO_IR;
4337                 return;
4338         }
4339
4340 @@ -278,17 +277,17 @@ ath_reg_apply_active_scan_flags(struct w
4341         ch = &sband->channels[11]; /* CH 12 */
4342         reg_rule = freq_reg_info(wiphy, ch->center_freq);
4343         if (!IS_ERR(reg_rule)) {
4344 -               if (!(reg_rule->flags & NL80211_RRF_PASSIVE_SCAN))
4345 -                       if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
4346 -                               ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
4347 +               if (!(reg_rule->flags & NL80211_RRF_NO_IR))
4348 +                       if (ch->flags & IEEE80211_CHAN_NO_IR)
4349 +                               ch->flags &= ~IEEE80211_CHAN_NO_IR;
4350         }
4351
4352         ch = &sband->channels[12]; /* CH 13 */
4353         reg_rule = freq_reg_info(wiphy, ch->center_freq);
4354         if (!IS_ERR(reg_rule)) {
4355 -               if (!(reg_rule->flags & NL80211_RRF_PASSIVE_SCAN))
4356 -                       if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
4357 -                               ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
4358 +               if (!(reg_rule->flags & NL80211_RRF_NO_IR))
4359 +                       if (ch->flags & IEEE80211_CHAN_NO_IR)
4360 +                               ch->flags &= ~IEEE80211_CHAN_NO_IR;
4361         }
4362  }
4363
4364 @@ -320,8 +319,8 @@ static void ath_reg_apply_radar_flags(st
4365                  */
4366                 if (!(ch->flags & IEEE80211_CHAN_DISABLED))
4367                         ch->flags |= IEEE80211_CHAN_RADAR |
4368 -                                    IEEE80211_CHAN_NO_IBSS |
4369 -                                    IEEE80211_CHAN_PASSIVE_SCAN;
4370 +                                    IEEE80211_CHAN_NO_IR |
4371 +                                    IEEE80211_CHAN_NO_IR;
4372         }
4373  }
4374
4375 --- a/drivers/net/wireless/brcm80211/brcmfmac/p2p.c
4376 +++ b/drivers/net/wireless/brcm80211/brcmfmac/p2p.c
4377 @@ -812,7 +812,7 @@ static s32 brcmf_p2p_run_escan(struct br
4378                         struct ieee80211_channel *chan = request->channels[i];
4379
4380                         if (chan->flags & (IEEE80211_CHAN_RADAR |
4381 -                                          IEEE80211_CHAN_PASSIVE_SCAN))
4382 +                                          IEEE80211_CHAN_NO_IR))
4383                                 continue;
4384
4385                         chanspecs[i] = channel_to_chanspec(&p2p->cfg->d11inf,
4386 --- a/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.c
4387 +++ b/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.c
4388 @@ -202,9 +202,9 @@ static struct ieee80211_supported_band _
4389
4390  /* This is to override regulatory domains defined in cfg80211 module (reg.c)
4391   * By default world regulatory domain defined in reg.c puts the flags
4392 - * NL80211_RRF_PASSIVE_SCAN and NL80211_RRF_NO_IBSS for 5GHz channels (for
4393 - * 36..48 and 149..165). With respect to these flags, wpa_supplicant doesn't
4394 - * start p2p operations on 5GHz channels. All the changes in world regulatory
4395 + * NL80211_RRF_NO_IR for 5GHz channels (for * 36..48 and 149..165).
4396 + * With respect to these flags, wpa_supplicant doesn't * start p2p
4397 + * operations on 5GHz channels. All the changes in world regulatory
4398   * domain are to be done here.
4399   */
4400  static const struct ieee80211_regdomain brcmf_regdom = {
4401 @@ -5197,10 +5197,10 @@ static s32 brcmf_construct_reginfo(struc
4402                                         if (channel & WL_CHAN_RADAR)
4403                                                 band_chan_arr[index].flags |=
4404                                                         (IEEE80211_CHAN_RADAR |
4405 -                                                       IEEE80211_CHAN_NO_IBSS);
4406 +                                                       IEEE80211_CHAN_NO_IR);
4407                                         if (channel & WL_CHAN_PASSIVE)
4408                                                 band_chan_arr[index].flags |=
4409 -                                                   IEEE80211_CHAN_PASSIVE_SCAN;
4410 +                                                   IEEE80211_CHAN_NO_IR;
4411                                 }
4412                         }
4413                         if (!update)
4414 --- a/drivers/net/wireless/brcm80211/brcmsmac/channel.c
4415 +++ b/drivers/net/wireless/brcm80211/brcmsmac/channel.c
4416 @@ -59,23 +59,20 @@
4417
4418  #define BRCM_2GHZ_2412_2462    REG_RULE(2412-10, 2462+10, 40, 0, 19, 0)
4419  #define BRCM_2GHZ_2467_2472    REG_RULE(2467-10, 2472+10, 20, 0, 19, \
4420 -                                        NL80211_RRF_PASSIVE_SCAN | \
4421 -                                        NL80211_RRF_NO_IBSS)
4422 +                                        NL80211_RRF_NO_IR)
4423
4424  #define BRCM_5GHZ_5180_5240    REG_RULE(5180-10, 5240+10, 40, 0, 21, \
4425 -                                        NL80211_RRF_PASSIVE_SCAN | \
4426 -                                        NL80211_RRF_NO_IBSS)
4427 +                                        NL80211_RRF_NO_IR)
4428  #define BRCM_5GHZ_5260_5320    REG_RULE(5260-10, 5320+10, 40, 0, 21, \
4429 -                                        NL80211_RRF_PASSIVE_SCAN | \
4430 +                                        NL80211_RRF_NO_IR | \
4431                                          NL80211_RRF_DFS | \
4432 -                                        NL80211_RRF_NO_IBSS)
4433 +                                        NL80211_RRF_NO_IR)
4434  #define BRCM_5GHZ_5500_5700    REG_RULE(5500-10, 5700+10, 40, 0, 21, \
4435 -                                        NL80211_RRF_PASSIVE_SCAN | \
4436 +                                        NL80211_RRF_NO_IR | \
4437                                          NL80211_RRF_DFS | \
4438 -                                        NL80211_RRF_NO_IBSS)
4439 +                                        NL80211_RRF_NO_IR)
4440  #define BRCM_5GHZ_5745_5825    REG_RULE(5745-10, 5825+10, 40, 0, 21, \
4441 -                                        NL80211_RRF_PASSIVE_SCAN | \
4442 -                                        NL80211_RRF_NO_IBSS)
4443 +                                        NL80211_RRF_NO_IR)
4444
4445  static const struct ieee80211_regdomain brcms_regdom_x2 = {
4446         .n_reg_rules = 6,
4447 @@ -395,7 +392,7 @@ brcms_c_channel_set_chanspec(struct brcm
4448                 brcms_c_set_gmode(wlc, wlc->protection->gmode_user, false);
4449
4450         brcms_b_set_chanspec(wlc->hw, chanspec,
4451 -                             !!(ch->flags & IEEE80211_CHAN_PASSIVE_SCAN),
4452 +                             !!(ch->flags & IEEE80211_CHAN_NO_IR),
4453                               &txpwr);
4454  }
4455
4456 @@ -657,8 +654,8 @@ static void brcms_reg_apply_radar_flags(
4457                  */
4458                 if (!(ch->flags & IEEE80211_CHAN_DISABLED))
4459                         ch->flags |= IEEE80211_CHAN_RADAR |
4460 -                                    IEEE80211_CHAN_NO_IBSS |
4461 -                                    IEEE80211_CHAN_PASSIVE_SCAN;
4462 +                                    IEEE80211_CHAN_NO_IR |
4463 +                                    IEEE80211_CHAN_NO_IR;
4464         }
4465  }
4466
4467 @@ -688,14 +685,13 @@ brcms_reg_apply_beaconing_flags(struct w
4468                                 if (IS_ERR(rule))
4469                                         continue;
4470
4471 -                               if (!(rule->flags & NL80211_RRF_NO_IBSS))
4472 -                                       ch->flags &= ~IEEE80211_CHAN_NO_IBSS;
4473 -                               if (!(rule->flags & NL80211_RRF_PASSIVE_SCAN))
4474 +                               if (!(rule->flags & NL80211_RRF_NO_IR))
4475 +                                       ch->flags &= ~IEEE80211_CHAN_NO_IR;
4476 +                               if (!(rule->flags & NL80211_RRF_NO_IR))
4477                                         ch->flags &=
4478 -                                               ~IEEE80211_CHAN_PASSIVE_SCAN;
4479 +                                               ~IEEE80211_CHAN_NO_IR;
4480                         } else if (ch->beacon_found) {
4481 -                               ch->flags &= ~(IEEE80211_CHAN_NO_IBSS |
4482 -                                              IEEE80211_CHAN_PASSIVE_SCAN);
4483 +                               ch->flags &= ~IEEE80211_CHAN_NO_IR;
4484                         }
4485                 }
4486         }
4487 --- a/drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.c
4488 +++ b/drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.c
4489 @@ -125,13 +125,13 @@ static struct ieee80211_channel brcms_2g
4490         CHAN2GHZ(10, 2457, IEEE80211_CHAN_NO_HT40PLUS),
4491         CHAN2GHZ(11, 2462, IEEE80211_CHAN_NO_HT40PLUS),
4492         CHAN2GHZ(12, 2467,
4493 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_IBSS |
4494 +                IEEE80211_CHAN_NO_IR |
4495                  IEEE80211_CHAN_NO_HT40PLUS),
4496         CHAN2GHZ(13, 2472,
4497 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_IBSS |
4498 +                IEEE80211_CHAN_NO_IR |
4499                  IEEE80211_CHAN_NO_HT40PLUS),
4500         CHAN2GHZ(14, 2484,
4501 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_IBSS |
4502 +                IEEE80211_CHAN_NO_IR |
4503                  IEEE80211_CHAN_NO_HT40PLUS | IEEE80211_CHAN_NO_HT40MINUS |
4504                  IEEE80211_CHAN_NO_OFDM)
4505  };
4506 @@ -144,51 +144,51 @@ static struct ieee80211_channel brcms_5g
4507         CHAN5GHZ(48, IEEE80211_CHAN_NO_HT40PLUS),
4508         /* UNII-2 */
4509         CHAN5GHZ(52,
4510 -                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
4511 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
4512 +                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
4513 +                IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40MINUS),
4514         CHAN5GHZ(56,
4515 -                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
4516 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
4517 +                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
4518 +                IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40PLUS),
4519         CHAN5GHZ(60,
4520 -                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
4521 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
4522 +                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
4523 +                IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40MINUS),
4524         CHAN5GHZ(64,
4525 -                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
4526 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
4527 +                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
4528 +                IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40PLUS),
4529         /* MID */
4530         CHAN5GHZ(100,
4531 -                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
4532 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
4533 +                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
4534 +                IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40MINUS),
4535         CHAN5GHZ(104,
4536 -                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
4537 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
4538 +                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
4539 +                IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40PLUS),
4540         CHAN5GHZ(108,
4541 -                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
4542 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
4543 +                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
4544 +                IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40MINUS),
4545         CHAN5GHZ(112,
4546 -                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
4547 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
4548 +                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
4549 +                IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40PLUS),
4550         CHAN5GHZ(116,
4551 -                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
4552 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
4553 +                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
4554 +                IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40MINUS),
4555         CHAN5GHZ(120,
4556 -                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
4557 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
4558 +                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
4559 +                IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40PLUS),
4560         CHAN5GHZ(124,
4561 -                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
4562 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
4563 +                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
4564 +                IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40MINUS),
4565         CHAN5GHZ(128,
4566 -                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
4567 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
4568 +                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
4569 +                IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40PLUS),
4570         CHAN5GHZ(132,
4571 -                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
4572 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
4573 +                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
4574 +                IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40MINUS),
4575         CHAN5GHZ(136,
4576 -                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
4577 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
4578 +                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
4579 +                IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40PLUS),
4580         CHAN5GHZ(140,
4581 -                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
4582 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS |
4583 +                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
4584 +                IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40PLUS |
4585                  IEEE80211_CHAN_NO_HT40MINUS),
4586         /* UNII-3 */
4587         CHAN5GHZ(149, IEEE80211_CHAN_NO_HT40MINUS),
4588 --- a/drivers/net/wireless/cw1200/scan.c
4589 +++ b/drivers/net/wireless/cw1200/scan.c
4590 @@ -197,9 +197,9 @@ void cw1200_scan_work(struct work_struct
4591                         if ((*it)->band != first->band)
4592                                 break;
4593                         if (((*it)->flags ^ first->flags) &
4594 -                                       IEEE80211_CHAN_PASSIVE_SCAN)
4595 +                                       IEEE80211_CHAN_NO_IR)
4596                                 break;
4597 -                       if (!(first->flags & IEEE80211_CHAN_PASSIVE_SCAN) &&
4598 +                       if (!(first->flags & IEEE80211_CHAN_NO_IR) &&
4599                             (*it)->max_power != first->max_power)
4600                                 break;
4601                 }
4602 @@ -210,7 +210,7 @@ void cw1200_scan_work(struct work_struct
4603                 else
4604                         scan.max_tx_rate = WSM_TRANSMIT_RATE_1;
4605                 scan.num_probes =
4606 -                       (first->flags & IEEE80211_CHAN_PASSIVE_SCAN) ? 0 : 2;
4607 +                       (first->flags & IEEE80211_CHAN_NO_IR) ? 0 : 2;
4608                 scan.num_ssids = priv->scan.n_ssids;
4609                 scan.ssids = &priv->scan.ssids[0];
4610                 scan.num_channels = it - priv->scan.curr;
4611 @@ -233,7 +233,7 @@ void cw1200_scan_work(struct work_struct
4612                 }
4613                 for (i = 0; i < scan.num_channels; ++i) {
4614                         scan.ch[i].number = priv->scan.curr[i]->hw_value;
4615 -                       if (priv->scan.curr[i]->flags & IEEE80211_CHAN_PASSIVE_SCAN) {
4616 +                       if (priv->scan.curr[i]->flags & IEEE80211_CHAN_NO_IR) {
4617                                 scan.ch[i].min_chan_time = 50;
4618                                 scan.ch[i].max_chan_time = 100;
4619                         } else {
4620 @@ -241,7 +241,7 @@ void cw1200_scan_work(struct work_struct
4621                                 scan.ch[i].max_chan_time = 25;
4622                         }
4623                 }
4624 -               if (!(first->flags & IEEE80211_CHAN_PASSIVE_SCAN) &&
4625 +               if (!(first->flags & IEEE80211_CHAN_NO_IR) &&
4626                     priv->scan.output_power != first->max_power) {
4627                         priv->scan.output_power = first->max_power;
4628                         wsm_set_output_power(priv,
4629 --- a/drivers/net/wireless/ipw2x00/ipw2100.c
4630 +++ b/drivers/net/wireless/ipw2x00/ipw2100.c
4631 @@ -1934,10 +1934,10 @@ static int ipw2100_wdev_init(struct net_
4632                         bg_band->channels[i].max_power = geo->bg[i].max_power;
4633                         if (geo->bg[i].flags & LIBIPW_CH_PASSIVE_ONLY)
4634                                 bg_band->channels[i].flags |=
4635 -                                       IEEE80211_CHAN_PASSIVE_SCAN;
4636 +                                       IEEE80211_CHAN_NO_IR;
4637                         if (geo->bg[i].flags & LIBIPW_CH_NO_IBSS)
4638                                 bg_band->channels[i].flags |=
4639 -                                       IEEE80211_CHAN_NO_IBSS;
4640 +                                       IEEE80211_CHAN_NO_IR;
4641                         if (geo->bg[i].flags & LIBIPW_CH_RADAR_DETECT)
4642                                 bg_band->channels[i].flags |=
4643                                         IEEE80211_CHAN_RADAR;
4644 --- a/drivers/net/wireless/ipw2x00/ipw2200.c
4645 +++ b/drivers/net/wireless/ipw2x00/ipw2200.c
4646 @@ -11472,10 +11472,10 @@ static int ipw_wdev_init(struct net_devi
4647                         bg_band->channels[i].max_power = geo->bg[i].max_power;
4648                         if (geo->bg[i].flags & LIBIPW_CH_PASSIVE_ONLY)
4649                                 bg_band->channels[i].flags |=
4650 -                                       IEEE80211_CHAN_PASSIVE_SCAN;
4651 +                                       IEEE80211_CHAN_NO_IR;
4652                         if (geo->bg[i].flags & LIBIPW_CH_NO_IBSS)
4653                                 bg_band->channels[i].flags |=
4654 -                                       IEEE80211_CHAN_NO_IBSS;
4655 +                                       IEEE80211_CHAN_NO_IR;
4656                         if (geo->bg[i].flags & LIBIPW_CH_RADAR_DETECT)
4657                                 bg_band->channels[i].flags |=
4658                                         IEEE80211_CHAN_RADAR;
4659 @@ -11511,10 +11511,10 @@ static int ipw_wdev_init(struct net_devi
4660                         a_band->channels[i].max_power = geo->a[i].max_power;
4661                         if (geo->a[i].flags & LIBIPW_CH_PASSIVE_ONLY)
4662                                 a_band->channels[i].flags |=
4663 -                                       IEEE80211_CHAN_PASSIVE_SCAN;
4664 +                                       IEEE80211_CHAN_NO_IR;
4665                         if (geo->a[i].flags & LIBIPW_CH_NO_IBSS)
4666                                 a_band->channels[i].flags |=
4667 -                                       IEEE80211_CHAN_NO_IBSS;
4668 +                                       IEEE80211_CHAN_NO_IR;
4669                         if (geo->a[i].flags & LIBIPW_CH_RADAR_DETECT)
4670                                 a_band->channels[i].flags |=
4671                                         IEEE80211_CHAN_RADAR;
4672 --- a/drivers/net/wireless/iwlegacy/3945-mac.c
4673 +++ b/drivers/net/wireless/iwlegacy/3945-mac.c
4674 @@ -1595,7 +1595,7 @@ il3945_get_channels_for_scan(struct il_p
4675                  *  and use long active_dwell time.
4676                  */
4677                 if (!is_active || il_is_channel_passive(ch_info) ||
4678 -                   (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN)) {
4679 +                   (chan->flags & IEEE80211_CHAN_NO_IR)) {
4680                         scan_ch->type = 0;      /* passive */
4681                         if (IL_UCODE_API(il->ucode_ver) == 1)
4682                                 scan_ch->active_dwell =
4683 --- a/drivers/net/wireless/iwlegacy/4965-mac.c
4684 +++ b/drivers/net/wireless/iwlegacy/4965-mac.c
4685 @@ -805,7 +805,7 @@ il4965_get_channels_for_scan(struct il_p
4686                 }
4687
4688                 if (!is_active || il_is_channel_passive(ch_info) ||
4689 -                   (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN))
4690 +                   (chan->flags & IEEE80211_CHAN_NO_IR))
4691                         scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
4692                 else
4693                         scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE;
4694 --- a/drivers/net/wireless/iwlegacy/common.c
4695 +++ b/drivers/net/wireless/iwlegacy/common.c
4696 @@ -3447,10 +3447,10 @@ il_init_geos(struct il_priv *il)
4697
4698                 if (il_is_channel_valid(ch)) {
4699                         if (!(ch->flags & EEPROM_CHANNEL_IBSS))
4700 -                               geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
4701 +                               geo_ch->flags |= IEEE80211_CHAN_NO_IR;
4702
4703                         if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
4704 -                               geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
4705 +                               geo_ch->flags |= IEEE80211_CHAN_NO_IR;
4706
4707                         if (ch->flags & EEPROM_CHANNEL_RADAR)
4708                                 geo_ch->flags |= IEEE80211_CHAN_RADAR;
4709 --- a/drivers/net/wireless/iwlegacy/debug.c
4710 +++ b/drivers/net/wireless/iwlegacy/debug.c
4711 @@ -567,12 +567,12 @@ il_dbgfs_channels_read(struct file *file
4712                                       flags & IEEE80211_CHAN_RADAR ?
4713                                       " (IEEE 802.11h required)" : "",
4714                                       ((channels[i].
4715 -                                       flags & IEEE80211_CHAN_NO_IBSS) ||
4716 +                                       flags & IEEE80211_CHAN_NO_IR) ||
4717                                        (channels[i].
4718                                         flags & IEEE80211_CHAN_RADAR)) ? "" :
4719                                       ", IBSS",
4720                                       channels[i].
4721 -                                     flags & IEEE80211_CHAN_PASSIVE_SCAN ?
4722 +                                     flags & IEEE80211_CHAN_NO_IR ?
4723                                       "passive only" : "active/passive");
4724         }
4725         supp_band = il_get_hw_mode(il, IEEE80211_BAND_5GHZ);
4726 @@ -594,12 +594,12 @@ il_dbgfs_channels_read(struct file *file
4727                                       flags & IEEE80211_CHAN_RADAR ?
4728                                       " (IEEE 802.11h required)" : "",
4729                                       ((channels[i].
4730 -                                       flags & IEEE80211_CHAN_NO_IBSS) ||
4731 +                                       flags & IEEE80211_CHAN_NO_IR) ||
4732                                        (channels[i].
4733                                         flags & IEEE80211_CHAN_RADAR)) ? "" :
4734                                       ", IBSS",
4735                                       channels[i].
4736 -                                     flags & IEEE80211_CHAN_PASSIVE_SCAN ?
4737 +                                     flags & IEEE80211_CHAN_NO_IR ?
4738                                       "passive only" : "active/passive");
4739         }
4740         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
4741 --- a/drivers/net/wireless/iwlwifi/dvm/debugfs.c
4742 +++ b/drivers/net/wireless/iwlwifi/dvm/debugfs.c
4743 @@ -352,12 +352,12 @@ static ssize_t iwl_dbgfs_channels_read(s
4744                                         channels[i].max_power,
4745                                         channels[i].flags & IEEE80211_CHAN_RADAR ?
4746                                         " (IEEE 802.11h required)" : "",
4747 -                                       ((channels[i].flags & IEEE80211_CHAN_NO_IBSS)
4748 +                                       ((channels[i].flags & IEEE80211_CHAN_NO_IR)
4749                                         || (channels[i].flags &
4750                                         IEEE80211_CHAN_RADAR)) ? "" :
4751                                         ", IBSS",
4752                                         channels[i].flags &
4753 -                                       IEEE80211_CHAN_PASSIVE_SCAN ?
4754 +                                       IEEE80211_CHAN_NO_IR ?
4755                                         "passive only" : "active/passive");
4756         }
4757         supp_band = iwl_get_hw_mode(priv, IEEE80211_BAND_5GHZ);
4758 @@ -375,12 +375,12 @@ static ssize_t iwl_dbgfs_channels_read(s
4759                                         channels[i].max_power,
4760                                         channels[i].flags & IEEE80211_CHAN_RADAR ?
4761                                         " (IEEE 802.11h required)" : "",
4762 -                                       ((channels[i].flags & IEEE80211_CHAN_NO_IBSS)
4763 +                                       ((channels[i].flags & IEEE80211_CHAN_NO_IR)
4764                                         || (channels[i].flags &
4765                                         IEEE80211_CHAN_RADAR)) ? "" :
4766                                         ", IBSS",
4767                                         channels[i].flags &
4768 -                                       IEEE80211_CHAN_PASSIVE_SCAN ?
4769 +                                       IEEE80211_CHAN_NO_IR ?
4770                                         "passive only" : "active/passive");
4771         }
4772         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
4773 --- a/drivers/net/wireless/iwlwifi/dvm/scan.c
4774 +++ b/drivers/net/wireless/iwlwifi/dvm/scan.c
4775 @@ -544,7 +544,7 @@ static int iwl_get_channels_for_scan(str
4776                 channel = chan->hw_value;
4777                 scan_ch->channel = cpu_to_le16(channel);
4778
4779 -               if (!is_active || (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN))
4780 +               if (!is_active || (chan->flags & IEEE80211_CHAN_NO_IR))
4781                         scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
4782                 else
4783                         scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE;
4784 --- a/drivers/net/wireless/iwlwifi/iwl-eeprom-parse.c
4785 +++ b/drivers/net/wireless/iwlwifi/iwl-eeprom-parse.c
4786 @@ -614,10 +614,10 @@ static int iwl_init_channel_map(struct d
4787                         channel->flags = IEEE80211_CHAN_NO_HT40;
4788
4789                         if (!(eeprom_ch->flags & EEPROM_CHANNEL_IBSS))
4790 -                               channel->flags |= IEEE80211_CHAN_NO_IBSS;
4791 +                               channel->flags |= IEEE80211_CHAN_NO_IR;
4792
4793                         if (!(eeprom_ch->flags & EEPROM_CHANNEL_ACTIVE))
4794 -                               channel->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
4795 +                               channel->flags |= IEEE80211_CHAN_NO_IR;
4796
4797                         if (eeprom_ch->flags & EEPROM_CHANNEL_RADAR)
4798                                 channel->flags |= IEEE80211_CHAN_RADAR;
4799 --- a/drivers/net/wireless/iwlwifi/iwl-nvm-parse.c
4800 +++ b/drivers/net/wireless/iwlwifi/iwl-nvm-parse.c
4801 @@ -223,10 +223,10 @@ static int iwl_init_channel_map(struct d
4802                         channel->flags |= IEEE80211_CHAN_NO_160MHZ;
4803
4804                 if (!(ch_flags & NVM_CHANNEL_IBSS))
4805 -                       channel->flags |= IEEE80211_CHAN_NO_IBSS;
4806 +                       channel->flags |= IEEE80211_CHAN_NO_IR;
4807
4808                 if (!(ch_flags & NVM_CHANNEL_ACTIVE))
4809 -                       channel->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
4810 +                       channel->flags |= IEEE80211_CHAN_NO_IR;
4811
4812                 if (ch_flags & NVM_CHANNEL_RADAR)
4813                         channel->flags |= IEEE80211_CHAN_RADAR;
4814 --- a/drivers/net/wireless/iwlwifi/mvm/scan.c
4815 +++ b/drivers/net/wireless/iwlwifi/mvm/scan.c
4816 @@ -192,7 +192,7 @@ static void iwl_mvm_scan_fill_channels(s
4817         for (i = 0; i < cmd->channel_count; i++) {
4818                 chan->channel = cpu_to_le16(req->channels[i]->hw_value);
4819                 chan->type = cpu_to_le32(type);
4820 -               if (req->channels[i]->flags & IEEE80211_CHAN_PASSIVE_SCAN)
4821 +               if (req->channels[i]->flags & IEEE80211_CHAN_NO_IR)
4822                         chan->type &= cpu_to_le32(~SCAN_CHANNEL_TYPE_ACTIVE);
4823                 chan->active_dwell = cpu_to_le16(active_dwell);
4824                 chan->passive_dwell = cpu_to_le16(passive_dwell);
4825 @@ -642,7 +642,7 @@ static void iwl_build_channel_cfg(struct
4826                 channels->iter_count[index] = cpu_to_le16(1);
4827                 channels->iter_interval[index] = 0;
4828
4829 -               if (!(s_band->channels[i].flags & IEEE80211_CHAN_PASSIVE_SCAN))
4830 +               if (!(s_band->channels[i].flags & IEEE80211_CHAN_NO_IR))
4831                         channels->type[index] |=
4832                                 cpu_to_le32(IWL_SCAN_OFFLOAD_CHANNEL_ACTIVE);
4833
4834 --- a/drivers/net/wireless/mac80211_hwsim.c
4835 +++ b/drivers/net/wireless/mac80211_hwsim.c
4836 @@ -159,7 +159,7 @@ static const struct ieee80211_regdomain
4837         .reg_rules = {
4838                 REG_RULE(2412-10, 2462+10, 40, 0, 20, 0),
4839                 REG_RULE(5725-10, 5850+10, 40, 0, 30,
4840 -                       NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS),
4841 +                        NL80211_RRF_NO_IR),
4842         }
4843  };
4844
4845 @@ -1485,7 +1485,7 @@ static void hw_scan_work(struct work_str
4846                     req->channels[hwsim->scan_chan_idx]->center_freq);
4847
4848         hwsim->tmp_chan = req->channels[hwsim->scan_chan_idx];
4849 -       if (hwsim->tmp_chan->flags & IEEE80211_CHAN_PASSIVE_SCAN ||
4850 +       if (hwsim->tmp_chan->flags & IEEE80211_CHAN_NO_IR ||
4851             !req->n_ssids) {
4852                 dwell = 120;
4853         } else {
4854 --- a/drivers/net/wireless/mwifiex/cfg80211.c
4855 +++ b/drivers/net/wireless/mwifiex/cfg80211.c
4856 @@ -50,24 +50,24 @@ static const struct ieee80211_regdomain
4857                 REG_RULE(2412-10, 2462+10, 40, 3, 20, 0),
4858                 /* Channel 12 - 13 */
4859                 REG_RULE(2467-10, 2472+10, 20, 3, 20,
4860 -                        NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS),
4861 +                        NL80211_RRF_NO_IR),
4862                 /* Channel 14 */
4863                 REG_RULE(2484-10, 2484+10, 20, 3, 20,
4864 -                        NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS |
4865 +                        NL80211_RRF_NO_IR |
4866                          NL80211_RRF_NO_OFDM),
4867                 /* Channel 36 - 48 */
4868                 REG_RULE(5180-10, 5240+10, 40, 3, 20,
4869 -                        NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS),
4870 +                        NL80211_RRF_NO_IR),
4871                 /* Channel 149 - 165 */
4872                 REG_RULE(5745-10, 5825+10, 40, 3, 20,
4873 -                        NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS),
4874 +                        NL80211_RRF_NO_IR),
4875                 /* Channel 52 - 64 */
4876                 REG_RULE(5260-10, 5320+10, 40, 3, 30,
4877 -                        NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS |
4878 +                        NL80211_RRF_NO_IR |
4879                          NL80211_RRF_DFS),
4880                 /* Channel 100 - 140 */
4881                 REG_RULE(5500-10, 5700+10, 40, 3, 30,
4882 -                        NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS |
4883 +                        NL80211_RRF_NO_IR |
4884                          NL80211_RRF_DFS),
4885         }
4886  };
4887 @@ -1968,7 +1968,7 @@ mwifiex_cfg80211_scan(struct wiphy *wiph
4888                 user_scan_cfg->chan_list[i].chan_number = chan->hw_value;
4889                 user_scan_cfg->chan_list[i].radio_type = chan->band;
4890
4891 -               if (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN)
4892 +               if (chan->flags & IEEE80211_CHAN_NO_IR)
4893                         user_scan_cfg->chan_list[i].scan_type =
4894                                                 MWIFIEX_SCAN_TYPE_PASSIVE;
4895                 else
4896 --- a/drivers/net/wireless/mwifiex/scan.c
4897 +++ b/drivers/net/wireless/mwifiex/scan.c
4898 @@ -515,14 +515,14 @@ mwifiex_scan_create_channel_list(struct
4899                                 scan_chan_list[chan_idx].max_scan_time =
4900                                         cpu_to_le16((u16) user_scan_in->
4901                                         chan_list[0].scan_time);
4902 -                       else if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
4903 +                       else if (ch->flags & IEEE80211_CHAN_NO_IR)
4904                                 scan_chan_list[chan_idx].max_scan_time =
4905                                         cpu_to_le16(adapter->passive_scan_time);
4906                         else
4907                                 scan_chan_list[chan_idx].max_scan_time =
4908                                         cpu_to_le16(adapter->active_scan_time);
4909
4910 -                       if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
4911 +                       if (ch->flags & IEEE80211_CHAN_NO_IR)
4912                                 scan_chan_list[chan_idx].chan_scan_mode_bitmap
4913                                         |= MWIFIEX_PASSIVE_SCAN;
4914                         else
4915 --- a/drivers/net/wireless/rt2x00/rt2x00lib.h
4916 +++ b/drivers/net/wireless/rt2x00/rt2x00lib.h
4917 @@ -146,7 +146,7 @@ void rt2x00queue_remove_l2pad(struct sk_
4918   * @local: frame is not from mac80211
4919   */
4920  int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb,
4921 -                              bool local);
4922 +                              struct ieee80211_sta *sta, bool local);
4923
4924  /**
4925   * rt2x00queue_update_beacon - Send new beacon from mac80211
4926 --- a/drivers/net/wireless/rt2x00/rt2x00mac.c
4927 +++ b/drivers/net/wireless/rt2x00/rt2x00mac.c
4928 @@ -90,7 +90,7 @@ static int rt2x00mac_tx_rts_cts(struct r
4929                                   frag_skb->data, data_length, tx_info,
4930                                   (struct ieee80211_rts *)(skb->data));
4931
4932 -       retval = rt2x00queue_write_tx_frame(queue, skb, true);
4933 +       retval = rt2x00queue_write_tx_frame(queue, skb, NULL, true);
4934         if (retval) {
4935                 dev_kfree_skb_any(skb);
4936                 rt2x00_warn(rt2x00dev, "Failed to send RTS/CTS frame\n");
4937 @@ -151,7 +151,7 @@ void rt2x00mac_tx(struct ieee80211_hw *h
4938                         goto exit_fail;
4939         }
4940
4941 -       if (unlikely(rt2x00queue_write_tx_frame(queue, skb, false)))
4942 +       if (unlikely(rt2x00queue_write_tx_frame(queue, skb, control->sta, false)))
4943                 goto exit_fail;
4944
4945         /*
4946 --- a/drivers/net/wireless/rt2x00/rt2x00queue.c
4947 +++ b/drivers/net/wireless/rt2x00/rt2x00queue.c
4948 @@ -635,7 +635,7 @@ static void rt2x00queue_bar_check(struct
4949  }
4950
4951  int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb,
4952 -                              bool local)
4953 +                              struct ieee80211_sta *sta, bool local)
4954  {
4955         struct ieee80211_tx_info *tx_info;
4956         struct queue_entry *entry;
4957 @@ -649,7 +649,7 @@ int rt2x00queue_write_tx_frame(struct da
4958          * after that we are free to use the skb->cb array
4959          * for our information.
4960          */
4961 -       rt2x00queue_create_tx_descriptor(queue->rt2x00dev, skb, &txdesc, NULL);
4962 +       rt2x00queue_create_tx_descriptor(queue->rt2x00dev, skb, &txdesc, sta);
4963
4964         /*
4965          * All information is retrieved from the skb->cb array,
4966 --- a/drivers/net/wireless/rtl818x/rtl8187/dev.c
4967 +++ b/drivers/net/wireless/rtl818x/rtl8187/dev.c
4968 @@ -416,7 +416,7 @@ static int rtl8187_init_urbs(struct ieee
4969         struct rtl8187_rx_info *info;
4970         int ret = 0;
4971
4972 -       while (skb_queue_len(&priv->rx_queue) < 16) {
4973 +       while (skb_queue_len(&priv->rx_queue) < 32) {
4974                 skb = __dev_alloc_skb(RTL8187_MAX_RX, GFP_KERNEL);
4975                 if (!skb) {
4976                         ret = -ENOMEM;
4977 --- a/drivers/net/wireless/rtlwifi/base.c
4978 +++ b/drivers/net/wireless/rtlwifi/base.c
4979 @@ -1078,8 +1078,8 @@ u8 rtl_is_special_data(struct ieee80211_
4980
4981         ip = (struct iphdr *)((u8 *) skb->data + mac_hdr_len +
4982                               SNAP_SIZE + PROTOC_TYPE_SIZE);
4983 -       ether_type = *(u16 *) ((u8 *) skb->data + mac_hdr_len + SNAP_SIZE);
4984 -       /*      ether_type = ntohs(ether_type); */
4985 +       ether_type = be16_to_cpu(*(__be16 *)((u8 *)skb->data + mac_hdr_len +
4986 +                                            SNAP_SIZE));
4987
4988         if (ETH_P_IP == ether_type) {
4989                 if (IPPROTO_UDP == ip->protocol) {
4990 --- a/drivers/net/wireless/rtlwifi/regd.c
4991 +++ b/drivers/net/wireless/rtlwifi/regd.c
4992 @@ -59,30 +59,27 @@ static struct country_code_to_enum_rd al
4993   */
4994  #define RTL819x_2GHZ_CH12_13   \
4995         REG_RULE(2467-10, 2472+10, 40, 0, 20,\
4996 -       NL80211_RRF_PASSIVE_SCAN)
4997 +       NL80211_RRF_NO_IR)
4998
4999  #define RTL819x_2GHZ_CH14      \
5000         REG_RULE(2484-10, 2484+10, 40, 0, 20, \
5001 -       NL80211_RRF_PASSIVE_SCAN | \
5002 +       NL80211_RRF_NO_IR | \
5003         NL80211_RRF_NO_OFDM)
5004
5005  /* 5G chan 36 - chan 64*/
5006  #define RTL819x_5GHZ_5150_5350 \
5007         REG_RULE(5150-10, 5350+10, 40, 0, 30, \
5008 -       NL80211_RRF_PASSIVE_SCAN | \
5009 -       NL80211_RRF_NO_IBSS)
5010 +       NL80211_RRF_NO_IR)
5011
5012  /* 5G chan 100 - chan 165*/
5013  #define RTL819x_5GHZ_5470_5850 \
5014         REG_RULE(5470-10, 5850+10, 40, 0, 30, \
5015 -       NL80211_RRF_PASSIVE_SCAN | \
5016 -       NL80211_RRF_NO_IBSS)
5017 +       NL80211_RRF_NO_IR)
5018
5019  /* 5G chan 149 - chan 165*/
5020  #define RTL819x_5GHZ_5725_5850 \
5021         REG_RULE(5725-10, 5850+10, 40, 0, 30, \
5022 -       NL80211_RRF_PASSIVE_SCAN | \
5023 -       NL80211_RRF_NO_IBSS)
5024 +       NL80211_RRF_NO_IR)
5025
5026  #define RTL819x_5GHZ_ALL       \
5027         (RTL819x_5GHZ_5150_5350, RTL819x_5GHZ_5470_5850)
5028 @@ -185,16 +182,15 @@ static void _rtl_reg_apply_beaconing_fla
5029                                  *regulatory_hint().
5030                                  */
5031
5032 -                               if (!(reg_rule->flags & NL80211_RRF_NO_IBSS))
5033 -                                       ch->flags &= ~IEEE80211_CHAN_NO_IBSS;
5034 +                               if (!(reg_rule->flags & NL80211_RRF_NO_IR))
5035 +                                       ch->flags &= ~IEEE80211_CHAN_NO_IR;
5036                                 if (!(reg_rule->
5037 -                                    flags & NL80211_RRF_PASSIVE_SCAN))
5038 +                                    flags & NL80211_RRF_NO_IR))
5039                                         ch->flags &=
5040 -                                           ~IEEE80211_CHAN_PASSIVE_SCAN;
5041 +                                           ~IEEE80211_CHAN_NO_IR;
5042                         } else {
5043                                 if (ch->beacon_found)
5044 -                                       ch->flags &= ~(IEEE80211_CHAN_NO_IBSS |
5045 -                                                 IEEE80211_CHAN_PASSIVE_SCAN);
5046 +                                       ch->flags &= ~IEEE80211_CHAN_NO_IR;
5047                         }
5048                 }
5049         }
5050 @@ -219,11 +215,11 @@ static void _rtl_reg_apply_active_scan_f
5051          */
5052         if (initiator != NL80211_REGDOM_SET_BY_COUNTRY_IE) {
5053                 ch = &sband->channels[11];      /* CH 12 */
5054 -               if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
5055 -                       ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
5056 +               if (ch->flags & IEEE80211_CHAN_NO_IR)
5057 +                       ch->flags &= ~IEEE80211_CHAN_NO_IR;
5058                 ch = &sband->channels[12];      /* CH 13 */
5059 -               if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
5060 -                       ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
5061 +               if (ch->flags & IEEE80211_CHAN_NO_IR)
5062 +                       ch->flags &= ~IEEE80211_CHAN_NO_IR;
5063                 return;
5064         }
5065
5066 @@ -237,17 +233,17 @@ static void _rtl_reg_apply_active_scan_f
5067         ch = &sband->channels[11];      /* CH 12 */
5068         reg_rule = freq_reg_info(wiphy, ch->center_freq);
5069         if (!IS_ERR(reg_rule)) {
5070 -               if (!(reg_rule->flags & NL80211_RRF_PASSIVE_SCAN))
5071 -                       if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
5072 -                               ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
5073 +               if (!(reg_rule->flags & NL80211_RRF_NO_IR))
5074 +                       if (ch->flags & IEEE80211_CHAN_NO_IR)
5075 +                               ch->flags &= ~IEEE80211_CHAN_NO_IR;
5076         }
5077
5078         ch = &sband->channels[12];      /* CH 13 */
5079         reg_rule = freq_reg_info(wiphy, ch->center_freq);
5080         if (!IS_ERR(reg_rule)) {
5081 -               if (!(reg_rule->flags & NL80211_RRF_PASSIVE_SCAN))
5082 -                       if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
5083 -                               ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
5084 +               if (!(reg_rule->flags & NL80211_RRF_NO_IR))
5085 +                       if (ch->flags & IEEE80211_CHAN_NO_IR)
5086 +                               ch->flags &= ~IEEE80211_CHAN_NO_IR;
5087         }
5088  }
5089
5090 @@ -284,8 +280,8 @@ static void _rtl_reg_apply_radar_flags(s
5091                  */
5092                 if (!(ch->flags & IEEE80211_CHAN_DISABLED))
5093                         ch->flags |= IEEE80211_CHAN_RADAR |
5094 -                           IEEE80211_CHAN_NO_IBSS |
5095 -                           IEEE80211_CHAN_PASSIVE_SCAN;
5096 +                           IEEE80211_CHAN_NO_IR |
5097 +                           IEEE80211_CHAN_NO_IR;
5098         }
5099  }
5100
5101 --- a/drivers/net/wireless/ti/wl12xx/scan.c
5102 +++ b/drivers/net/wireless/ti/wl12xx/scan.c
5103 @@ -47,7 +47,7 @@ static int wl1271_get_scan_channels(stru
5104                      * In active scans, we only scan channels not
5105                      * marked as passive.
5106                      */
5107 -                   (passive || !(flags & IEEE80211_CHAN_PASSIVE_SCAN))) {
5108 +                   (passive || !(flags & IEEE80211_CHAN_NO_IR))) {
5109                         wl1271_debug(DEBUG_SCAN, "band %d, center_freq %d ",
5110                                      req->channels[i]->band,
5111                                      req->channels[i]->center_freq);
5112 --- a/drivers/net/wireless/ti/wlcore/cmd.c
5113 +++ b/drivers/net/wireless/ti/wlcore/cmd.c
5114 @@ -1688,7 +1688,7 @@ int wlcore_cmd_regdomain_config_locked(s
5115
5116                         if (channel->flags & (IEEE80211_CHAN_DISABLED |
5117                                               IEEE80211_CHAN_RADAR |
5118 -                                             IEEE80211_CHAN_PASSIVE_SCAN))
5119 +                                             IEEE80211_CHAN_NO_IR))
5120                                 continue;
5121
5122                         ch_bit_idx = wlcore_get_reg_conf_ch_idx(b, ch);
5123 --- a/drivers/net/wireless/ti/wlcore/main.c
5124 +++ b/drivers/net/wireless/ti/wlcore/main.c
5125 @@ -91,8 +91,7 @@ static void wl1271_reg_notify(struct wip
5126                         continue;
5127
5128                 if (ch->flags & IEEE80211_CHAN_RADAR)
5129 -                       ch->flags |= IEEE80211_CHAN_NO_IBSS |
5130 -                                    IEEE80211_CHAN_PASSIVE_SCAN;
5131 +                       ch->flags |= IEEE80211_CHAN_NO_IR;
5132
5133         }
5134
5135 --- a/drivers/net/wireless/ti/wlcore/scan.c
5136 +++ b/drivers/net/wireless/ti/wlcore/scan.c
5137 @@ -189,14 +189,14 @@ wlcore_scan_get_channels(struct wl1271 *
5138                 flags = req_channels[i]->flags;
5139
5140                 if (force_passive)
5141 -                       flags |= IEEE80211_CHAN_PASSIVE_SCAN;
5142 +                       flags |= IEEE80211_CHAN_NO_IR;
5143
5144                 if ((req_channels[i]->band == band) &&
5145                     !(flags & IEEE80211_CHAN_DISABLED) &&
5146                     (!!(flags & IEEE80211_CHAN_RADAR) == radar) &&
5147                     /* if radar is set, we ignore the passive flag */
5148                     (radar ||
5149 -                    !!(flags & IEEE80211_CHAN_PASSIVE_SCAN) == passive)) {
5150 +                    !!(flags & IEEE80211_CHAN_NO_IR) == passive)) {
5151
5152
5153                         if (flags & IEEE80211_CHAN_RADAR) {
5154 @@ -221,7 +221,7 @@ wlcore_scan_get_channels(struct wl1271 *
5155                             (band == IEEE80211_BAND_2GHZ) &&
5156                             (channels[j].channel >= 12) &&
5157                             (channels[j].channel <= 14) &&
5158 -                           (flags & IEEE80211_CHAN_PASSIVE_SCAN) &&
5159 +                           (flags & IEEE80211_CHAN_NO_IR) &&
5160                             !force_passive) {
5161                                 /* pactive channels treated as DFS */
5162                                 channels[j].flags = SCAN_CHANNEL_FLAGS_DFS;
5163 @@ -244,7 +244,7 @@ wlcore_scan_get_channels(struct wl1271 *
5164                                      max_dwell_time_active,
5165                                      flags & IEEE80211_CHAN_RADAR ?
5166                                         ", DFS" : "",
5167 -                                    flags & IEEE80211_CHAN_PASSIVE_SCAN ?
5168 +                                    flags & IEEE80211_CHAN_NO_IR ?
5169                                         ", PASSIVE" : "");
5170                         j++;
5171                 }
5172 --- a/include/net/cfg80211.h
5173 +++ b/include/net/cfg80211.h
5174 @@ -91,9 +91,8 @@ enum ieee80211_band {
5175   * Channel flags set by the regulatory control code.
5176   *
5177   * @IEEE80211_CHAN_DISABLED: This channel is disabled.
5178 - * @IEEE80211_CHAN_PASSIVE_SCAN: Only passive scanning is permitted
5179 - *     on this channel.
5180 - * @IEEE80211_CHAN_NO_IBSS: IBSS is not allowed on this channel.
5181 + * @IEEE80211_CHAN_NO_IR: do not initiate radiation, this includes
5182 + *     sending probe requests or beaconing.
5183   * @IEEE80211_CHAN_RADAR: Radar detection is required on this channel.
5184   * @IEEE80211_CHAN_NO_HT40PLUS: extension channel above this channel
5185   *     is not permitted.
5186 @@ -113,8 +112,8 @@ enum ieee80211_band {
5187   */
5188  enum ieee80211_channel_flags {
5189         IEEE80211_CHAN_DISABLED         = 1<<0,
5190 -       IEEE80211_CHAN_PASSIVE_SCAN     = 1<<1,
5191 -       IEEE80211_CHAN_NO_IBSS          = 1<<2,
5192 +       IEEE80211_CHAN_NO_IR            = 1<<1,
5193 +       /* hole at 1<<2 */
5194         IEEE80211_CHAN_RADAR            = 1<<3,
5195         IEEE80211_CHAN_NO_HT40PLUS      = 1<<4,
5196         IEEE80211_CHAN_NO_HT40MINUS     = 1<<5,
5197 @@ -4149,6 +4148,7 @@ void cfg80211_radar_event(struct wiphy *
5198  /**
5199   * cfg80211_cac_event - Channel availability check (CAC) event
5200   * @netdev: network device
5201 + * @chandef: chandef for the current channel
5202   * @event: type of event
5203   * @gfp: context flags
5204   *
5205 @@ -4157,6 +4157,7 @@ void cfg80211_radar_event(struct wiphy *
5206   * also by full-MAC drivers.
5207   */
5208  void cfg80211_cac_event(struct net_device *netdev,
5209 +                       const struct cfg80211_chan_def *chandef,
5210                         enum nl80211_radar_event event, gfp_t gfp);
5211
5212
5213 @@ -4282,7 +4283,8 @@ bool cfg80211_reg_can_beacon(struct wiph
5214   * @dev: the device which switched channels
5215   * @chandef: the new channel definition
5216   *
5217 - * Acquires wdev_lock, so must only be called from sleepable driver context!
5218 + * Caller must acquire wdev_lock, therefore must only be called from sleepable
5219 + * driver context!
5220   */
5221  void cfg80211_ch_switch_notify(struct net_device *dev,
5222                                struct cfg80211_chan_def *chandef);
5223 --- a/include/uapi/linux/nl80211.h
5224 +++ b/include/uapi/linux/nl80211.h
5225 @@ -1508,6 +1508,12 @@ enum nl80211_commands {
5226   *     to react to radar events, e.g. initiate a channel switch or leave the
5227   *     IBSS network.
5228   *
5229 + * @NL80211_ATTR_SUPPORT_5_MHZ: A flag indicating that the device supports
5230 + *     5 MHz channel bandwidth.
5231 + *
5232 + * @NL80211_ATTR_SUPPORT_10_MHZ: A flag indicating that the device supports
5233 + *     10 MHz channel bandwidth.
5234 + *
5235   * @NL80211_ATTR_MAX: highest attribute number currently defined
5236   * @__NL80211_ATTR_AFTER_LAST: internal use
5237   */
5238 @@ -1824,6 +1830,9 @@ enum nl80211_attrs {
5239
5240         NL80211_ATTR_HANDLE_DFS,
5241
5242 +       NL80211_ATTR_SUPPORT_5_MHZ,
5243 +       NL80211_ATTR_SUPPORT_10_MHZ,
5244 +
5245         /* add attributes here, update the policy in nl80211.c */
5246
5247         __NL80211_ATTR_AFTER_LAST,
5248 @@ -2224,10 +2233,9 @@ enum nl80211_band_attr {
5249   * @NL80211_FREQUENCY_ATTR_FREQ: Frequency in MHz
5250   * @NL80211_FREQUENCY_ATTR_DISABLED: Channel is disabled in current
5251   *     regulatory domain.
5252 - * @NL80211_FREQUENCY_ATTR_PASSIVE_SCAN: Only passive scanning is
5253 - *     permitted on this channel in current regulatory domain.
5254 - * @NL80211_FREQUENCY_ATTR_NO_IBSS: IBSS networks are not permitted
5255 - *     on this channel in current regulatory domain.
5256 + * @NL80211_FREQUENCY_ATTR_NO_IR: no mechanisms that initiate radiation
5257 + *     are permitted on this channel, this includes sending probe
5258 + *     requests, or modes of operation that require beaconing.
5259   * @NL80211_FREQUENCY_ATTR_RADAR: Radar detection is mandatory
5260   *     on this channel in current regulatory domain.
5261   * @NL80211_FREQUENCY_ATTR_MAX_TX_POWER: Maximum transmission power in mBm
5262 @@ -2254,8 +2262,8 @@ enum nl80211_frequency_attr {
5263         __NL80211_FREQUENCY_ATTR_INVALID,
5264         NL80211_FREQUENCY_ATTR_FREQ,
5265         NL80211_FREQUENCY_ATTR_DISABLED,
5266 -       NL80211_FREQUENCY_ATTR_PASSIVE_SCAN,
5267 -       NL80211_FREQUENCY_ATTR_NO_IBSS,
5268 +       NL80211_FREQUENCY_ATTR_NO_IR,
5269 +       __NL80211_FREQUENCY_ATTR_NO_IBSS,
5270         NL80211_FREQUENCY_ATTR_RADAR,
5271         NL80211_FREQUENCY_ATTR_MAX_TX_POWER,
5272         NL80211_FREQUENCY_ATTR_DFS_STATE,
5273 @@ -2271,6 +2279,9 @@ enum nl80211_frequency_attr {
5274  };
5275
5276  #define NL80211_FREQUENCY_ATTR_MAX_TX_POWER NL80211_FREQUENCY_ATTR_MAX_TX_POWER
5277 +#define NL80211_FREQUENCY_ATTR_PASSIVE_SCAN    NL80211_FREQUENCY_ATTR_NO_IR
5278 +#define NL80211_FREQUENCY_ATTR_NO_IBSS         NL80211_FREQUENCY_ATTR_NO_IR
5279 +#define NL80211_FREQUENCY_ATTR_NO_IR           NL80211_FREQUENCY_ATTR_NO_IR
5280
5281  /**
5282   * enum nl80211_bitrate_attr - bitrate attributes
5283 @@ -2413,8 +2424,9 @@ enum nl80211_sched_scan_match_attr {
5284   * @NL80211_RRF_DFS: DFS support is required to be used
5285   * @NL80211_RRF_PTP_ONLY: this is only for Point To Point links
5286   * @NL80211_RRF_PTMP_ONLY: this is only for Point To Multi Point links
5287 - * @NL80211_RRF_PASSIVE_SCAN: passive scan is required
5288 - * @NL80211_RRF_NO_IBSS: no IBSS is allowed
5289 + * @NL80211_RRF_NO_IR: no mechanisms that initiate radiation are allowed,
5290 + *     this includes probe requests or modes of operation that require
5291 + *     beaconing.
5292   */
5293  enum nl80211_reg_rule_flags {
5294         NL80211_RRF_NO_OFDM             = 1<<0,
5295 @@ -2424,10 +2436,17 @@ enum nl80211_reg_rule_flags {
5296         NL80211_RRF_DFS                 = 1<<4,
5297         NL80211_RRF_PTP_ONLY            = 1<<5,
5298         NL80211_RRF_PTMP_ONLY           = 1<<6,
5299 -       NL80211_RRF_PASSIVE_SCAN        = 1<<7,
5300 -       NL80211_RRF_NO_IBSS             = 1<<8,
5301 +       NL80211_RRF_NO_IR               = 1<<7,
5302 +       __NL80211_RRF_NO_IBSS           = 1<<8,
5303  };
5304
5305 +#define NL80211_RRF_PASSIVE_SCAN       NL80211_RRF_NO_IR
5306 +#define NL80211_RRF_NO_IBSS            NL80211_RRF_NO_IR
5307 +#define NL80211_RRF_NO_IR              NL80211_RRF_NO_IR
5308 +
5309 +/* For backport compatibility with older userspace */
5310 +#define NL80211_RRF_NO_IR_ALL          (NL80211_RRF_NO_IR | __NL80211_RRF_NO_IBSS)
5311 +
5312  /**
5313   * enum nl80211_dfs_regions - regulatory DFS regions
5314   *
5315 --- a/net/mac80211/cfg.c
5316 +++ b/net/mac80211/cfg.c
5317 @@ -846,7 +846,7 @@ static int ieee80211_set_probe_resp(stru
5318         if (!resp || !resp_len)
5319                 return 1;
5320
5321 -       old = rtnl_dereference(sdata->u.ap.probe_resp);
5322 +       old = sdata_dereference(sdata->u.ap.probe_resp, sdata);
5323
5324         new = kzalloc(sizeof(struct probe_resp) + resp_len, GFP_KERNEL);
5325         if (!new)
5326 @@ -870,7 +870,8 @@ int ieee80211_assign_beacon(struct ieee8
5327         int size, err;
5328         u32 changed = BSS_CHANGED_BEACON;
5329
5330 -       old = rtnl_dereference(sdata->u.ap.beacon);
5331 +       old = sdata_dereference(sdata->u.ap.beacon, sdata);
5332 +
5333
5334         /* Need to have a beacon head if we don't have one yet */
5335         if (!params->head && !old)
5336 @@ -947,7 +948,7 @@ static int ieee80211_start_ap(struct wip
5337                       BSS_CHANGED_P2P_PS;
5338         int err;
5339
5340 -       old = rtnl_dereference(sdata->u.ap.beacon);
5341 +       old = sdata_dereference(sdata->u.ap.beacon, sdata);
5342         if (old)
5343                 return -EALREADY;
5344
5345 @@ -1001,7 +1002,8 @@ static int ieee80211_start_ap(struct wip
5346
5347         err = drv_start_ap(sdata->local, sdata);
5348         if (err) {
5349 -               old = rtnl_dereference(sdata->u.ap.beacon);
5350 +               old = sdata_dereference(sdata->u.ap.beacon, sdata);
5351 +
5352                 if (old)
5353                         kfree_rcu(old, rcu_head);
5354                 RCU_INIT_POINTER(sdata->u.ap.beacon, NULL);
5355 @@ -1032,7 +1034,7 @@ static int ieee80211_change_beacon(struc
5356         if (sdata->vif.csa_active)
5357                 return -EBUSY;
5358
5359 -       old = rtnl_dereference(sdata->u.ap.beacon);
5360 +       old = sdata_dereference(sdata->u.ap.beacon, sdata);
5361         if (!old)
5362                 return -ENOENT;
5363
5364 @@ -1050,15 +1052,18 @@ static int ieee80211_stop_ap(struct wiph
5365         struct ieee80211_local *local = sdata->local;
5366         struct beacon_data *old_beacon;
5367         struct probe_resp *old_probe_resp;
5368 +       struct cfg80211_chan_def chandef;
5369
5370 -       old_beacon = rtnl_dereference(sdata->u.ap.beacon);
5371 +       old_beacon = sdata_dereference(sdata->u.ap.beacon, sdata);
5372         if (!old_beacon)
5373                 return -ENOENT;
5374 -       old_probe_resp = rtnl_dereference(sdata->u.ap.probe_resp);
5375 +       old_probe_resp = sdata_dereference(sdata->u.ap.probe_resp, sdata);
5376
5377         /* abort any running channel switch */
5378         sdata->vif.csa_active = false;
5379 -       cancel_work_sync(&sdata->csa_finalize_work);
5380 +       kfree(sdata->u.ap.next_beacon);
5381 +       sdata->u.ap.next_beacon = NULL;
5382 +
5383         cancel_work_sync(&sdata->u.ap.request_smps_work);
5384
5385         /* turn off carrier for this interface and dependent VLANs */
5386 @@ -1091,8 +1096,10 @@ static int ieee80211_stop_ap(struct wiph
5387         ieee80211_bss_info_change_notify(sdata, BSS_CHANGED_BEACON_ENABLED);
5388
5389         if (sdata->wdev.cac_started) {
5390 +               chandef = sdata->vif.bss_conf.chandef;
5391                 cancel_delayed_work_sync(&sdata->dfs_cac_timer_work);
5392 -               cfg80211_cac_event(sdata->dev, NL80211_RADAR_CAC_ABORTED,
5393 +               cfg80211_cac_event(sdata->dev, &chandef,
5394 +                                  NL80211_RADAR_CAC_ABORTED,
5395                                    GFP_KERNEL);
5396         }
5397
5398 @@ -1368,7 +1375,7 @@ static int sta_apply_parameters(struct i
5399                         changed |=
5400                               ieee80211_mps_set_sta_local_pm(sta,
5401                                                              params->local_pm);
5402 -               ieee80211_bss_info_change_notify(sdata, changed);
5403 +               ieee80211_mbss_info_change_notify(sdata, changed);
5404  #endif
5405         }
5406
5407 @@ -1953,7 +1960,7 @@ static int ieee80211_change_bss(struct w
5408         enum ieee80211_band band;
5409         u32 changed = 0;
5410
5411 -       if (!rtnl_dereference(sdata->u.ap.beacon))
5412 +       if (!sdata_dereference(sdata->u.ap.beacon, sdata))
5413                 return -ENOENT;
5414
5415         band = ieee80211_get_sdata_band(sdata);
5416 @@ -2964,27 +2971,33 @@ void ieee80211_csa_finalize_work(struct
5417         struct ieee80211_local *local = sdata->local;
5418         int err, changed = 0;
5419
5420 +       sdata_lock(sdata);
5421 +       /* AP might have been stopped while waiting for the lock. */
5422 +       if (!sdata->vif.csa_active)
5423 +               goto unlock;
5424 +
5425         if (!ieee80211_sdata_running(sdata))
5426 -               return;
5427 +               goto unlock;
5428
5429         sdata->radar_required = sdata->csa_radar_required;
5430 -       err = ieee80211_vif_change_channel(sdata, &local->csa_chandef,
5431 -                                          &changed);
5432 +       err = ieee80211_vif_change_channel(sdata, &changed);
5433         if (WARN_ON(err < 0))
5434 -               return;
5435 +               goto unlock;
5436
5437         if (!local->use_chanctx) {
5438 -               local->_oper_chandef = local->csa_chandef;
5439 +               local->_oper_chandef = sdata->csa_chandef;
5440                 ieee80211_hw_config(local, 0);
5441         }
5442
5443         ieee80211_bss_info_change_notify(sdata, changed);
5444
5445 +       sdata->vif.csa_active = false;
5446         switch (sdata->vif.type) {
5447         case NL80211_IFTYPE_AP:
5448                 err = ieee80211_assign_beacon(sdata, sdata->u.ap.next_beacon);
5449                 if (err < 0)
5450 -                       return;
5451 +                       goto unlock;
5452 +
5453                 changed |= err;
5454                 kfree(sdata->u.ap.next_beacon);
5455                 sdata->u.ap.next_beacon = NULL;
5456 @@ -2998,20 +3011,22 @@ void ieee80211_csa_finalize_work(struct
5457         case NL80211_IFTYPE_MESH_POINT:
5458                 err = ieee80211_mesh_finish_csa(sdata);
5459                 if (err < 0)
5460 -                       return;
5461 +                       goto unlock;
5462                 break;
5463  #endif
5464         default:
5465                 WARN_ON(1);
5466 -               return;
5467 +               goto unlock;
5468         }
5469 -       sdata->vif.csa_active = false;
5470
5471         ieee80211_wake_queues_by_reason(&sdata->local->hw,
5472                                         IEEE80211_MAX_QUEUE_MAP,
5473                                         IEEE80211_QUEUE_STOP_REASON_CSA);
5474
5475 -       cfg80211_ch_switch_notify(sdata->dev, &local->csa_chandef);
5476 +       cfg80211_ch_switch_notify(sdata->dev, &sdata->csa_chandef);
5477 +
5478 +unlock:
5479 +       sdata_unlock(sdata);
5480  }
5481
5482  static int ieee80211_channel_switch(struct wiphy *wiphy, struct net_device *dev,
5483 @@ -3024,6 +3039,8 @@ static int ieee80211_channel_switch(stru
5484         struct ieee80211_if_mesh __maybe_unused *ifmsh;
5485         int err, num_chanctx;
5486
5487 +       lockdep_assert_held(&sdata->wdev.mtx);
5488 +
5489         if (!list_empty(&local->roc_list) || local->scanning)
5490                 return -EBUSY;
5491
5492 @@ -3120,9 +3137,17 @@ static int ieee80211_channel_switch(stru
5493                     params->chandef.chan->band)
5494                         return -EINVAL;
5495
5496 +               ifmsh->chsw_init = true;
5497 +               if (!ifmsh->pre_value)
5498 +                       ifmsh->pre_value = 1;
5499 +               else
5500 +                       ifmsh->pre_value++;
5501 +
5502                 err = ieee80211_mesh_csa_beacon(sdata, params, true);
5503 -               if (err < 0)
5504 +               if (err < 0) {
5505 +                       ifmsh->chsw_init = false;
5506                         return err;
5507 +               }
5508                 break;
5509  #endif
5510         default:
5511 @@ -3136,7 +3161,7 @@ static int ieee80211_channel_switch(stru
5512                                 IEEE80211_MAX_QUEUE_MAP,
5513                                 IEEE80211_QUEUE_STOP_REASON_CSA);
5514
5515 -       local->csa_chandef = params->chandef;
5516 +       sdata->csa_chandef = params->chandef;
5517         sdata->vif.csa_active = true;
5518
5519         ieee80211_bss_info_change_notify(sdata, err);
5520 --- a/net/mac80211/iface.c
5521 +++ b/net/mac80211/iface.c
5522 @@ -749,6 +749,7 @@ static void ieee80211_do_stop(struct iee
5523         u32 hw_reconf_flags = 0;
5524         int i, flushed;
5525         struct ps_data *ps;
5526 +       struct cfg80211_chan_def chandef;
5527
5528         clear_bit(SDATA_STATE_RUNNING, &sdata->state);
5529
5530 @@ -828,11 +829,13 @@ static void ieee80211_do_stop(struct iee
5531         cancel_delayed_work_sync(&sdata->dfs_cac_timer_work);
5532
5533         if (sdata->wdev.cac_started) {
5534 +               chandef = sdata->vif.bss_conf.chandef;
5535                 WARN_ON(local->suspended);
5536                 mutex_lock(&local->iflist_mtx);
5537                 ieee80211_vif_release_channel(sdata);
5538                 mutex_unlock(&local->iflist_mtx);
5539 -               cfg80211_cac_event(sdata->dev, NL80211_RADAR_CAC_ABORTED,
5540 +               cfg80211_cac_event(sdata->dev, &chandef,
5541 +                                  NL80211_RADAR_CAC_ABORTED,
5542                                    GFP_KERNEL);
5543         }
5544
5545 @@ -1340,7 +1343,6 @@ static void ieee80211_setup_sdata(struct
5546                 sdata->vif.bss_conf.bssid = NULL;
5547                 break;
5548         case NL80211_IFTYPE_AP_VLAN:
5549 -               break;
5550         case NL80211_IFTYPE_P2P_DEVICE:
5551                 sdata->vif.bss_conf.bssid = sdata->vif.addr;
5552                 break;
5553 --- a/net/mac80211/mlme.c
5554 +++ b/net/mac80211/mlme.c
5555 @@ -886,8 +886,7 @@ static void ieee80211_chswitch_work(stru
5556         if (!ifmgd->associated)
5557                 goto out;
5558
5559 -       ret = ieee80211_vif_change_channel(sdata, &local->csa_chandef,
5560 -                                          &changed);
5561 +       ret = ieee80211_vif_change_channel(sdata, &changed);
5562         if (ret) {
5563                 sdata_info(sdata,
5564                            "vif channel switch failed, disconnecting\n");
5565 @@ -897,7 +896,7 @@ static void ieee80211_chswitch_work(stru
5566         }
5567
5568         if (!local->use_chanctx) {
5569 -               local->_oper_chandef = local->csa_chandef;
5570 +               local->_oper_chandef = sdata->csa_chandef;
5571                 /* Call "hw_config" only if doing sw channel switch.
5572                  * Otherwise update the channel directly
5573                  */
5574 @@ -908,7 +907,7 @@ static void ieee80211_chswitch_work(stru
5575         }
5576
5577         /* XXX: shouldn't really modify cfg80211-owned data! */
5578 -       ifmgd->associated->channel = local->csa_chandef.chan;
5579 +       ifmgd->associated->channel = sdata->csa_chandef.chan;
5580
5581         /* XXX: wait for a beacon first? */
5582         ieee80211_wake_queues_by_reason(&local->hw,
5583 @@ -1035,7 +1034,7 @@ ieee80211_sta_process_chanswitch(struct
5584         }
5585         mutex_unlock(&local->chanctx_mtx);
5586
5587 -       local->csa_chandef = csa_ie.chandef;
5588 +       sdata->csa_chandef = csa_ie.chandef;
5589
5590         if (csa_ie.mode)
5591                 ieee80211_stop_queues_by_reason(&local->hw,
5592 @@ -1398,10 +1397,12 @@ void ieee80211_dfs_cac_timer_work(struct
5593         struct ieee80211_sub_if_data *sdata =
5594                 container_of(delayed_work, struct ieee80211_sub_if_data,
5595                              dfs_cac_timer_work);
5596 +       struct cfg80211_chan_def chandef = sdata->vif.bss_conf.chandef;
5597
5598         ieee80211_vif_release_channel(sdata);
5599 -
5600 -       cfg80211_cac_event(sdata->dev, NL80211_RADAR_CAC_FINISHED, GFP_KERNEL);
5601 +       cfg80211_cac_event(sdata->dev, &chandef,
5602 +                          NL80211_RADAR_CAC_FINISHED,
5603 +                          GFP_KERNEL);
5604  }
5605
5606  /* MLME */
5607 --- a/net/mac80211/rx.c
5608 +++ b/net/mac80211/rx.c
5609 @@ -729,9 +729,7 @@ static void ieee80211_release_reorder_fr
5610         lockdep_assert_held(&tid_agg_rx->reorder_lock);
5611
5612         while (ieee80211_sn_less(tid_agg_rx->head_seq_num, head_seq_num)) {
5613 -               index = ieee80211_sn_sub(tid_agg_rx->head_seq_num,
5614 -                                        tid_agg_rx->ssn) %
5615 -                                                       tid_agg_rx->buf_size;
5616 +               index = tid_agg_rx->head_seq_num % tid_agg_rx->buf_size;
5617                 ieee80211_release_reorder_frame(sdata, tid_agg_rx, index,
5618                                                 frames);
5619         }
5620 @@ -757,8 +755,7 @@ static void ieee80211_sta_reorder_releas
5621         lockdep_assert_held(&tid_agg_rx->reorder_lock);
5622
5623         /* release the buffer until next missing frame */
5624 -       index = ieee80211_sn_sub(tid_agg_rx->head_seq_num,
5625 -                                tid_agg_rx->ssn) % tid_agg_rx->buf_size;
5626 +       index = tid_agg_rx->head_seq_num % tid_agg_rx->buf_size;
5627         if (!tid_agg_rx->reorder_buf[index] &&
5628             tid_agg_rx->stored_mpdu_num) {
5629                 /*
5630 @@ -793,15 +790,11 @@ static void ieee80211_sta_reorder_releas
5631         } else while (tid_agg_rx->reorder_buf[index]) {
5632                 ieee80211_release_reorder_frame(sdata, tid_agg_rx, index,
5633                                                 frames);
5634 -               index = ieee80211_sn_sub(tid_agg_rx->head_seq_num,
5635 -                                        tid_agg_rx->ssn) %
5636 -                                                       tid_agg_rx->buf_size;
5637 +               index = tid_agg_rx->head_seq_num % tid_agg_rx->buf_size;
5638         }
5639
5640         if (tid_agg_rx->stored_mpdu_num) {
5641 -               j = index = ieee80211_sn_sub(tid_agg_rx->head_seq_num,
5642 -                                            tid_agg_rx->ssn) %
5643 -                                                       tid_agg_rx->buf_size;
5644 +               j = index = tid_agg_rx->head_seq_num % tid_agg_rx->buf_size;
5645
5646                 for (; j != (index - 1) % tid_agg_rx->buf_size;
5647                      j = (j + 1) % tid_agg_rx->buf_size) {
5648 @@ -861,8 +854,7 @@ static bool ieee80211_sta_manage_reorder
5649
5650         /* Now the new frame is always in the range of the reordering buffer */
5651
5652 -       index = ieee80211_sn_sub(mpdu_seq_num,
5653 -                                tid_agg_rx->ssn) % tid_agg_rx->buf_size;
5654 +       index = mpdu_seq_num % tid_agg_rx->buf_size;
5655
5656         /* check if we already stored this frame */
5657         if (tid_agg_rx->reorder_buf[index]) {
5658 @@ -911,7 +903,8 @@ static void ieee80211_rx_reorder_ampdu(s
5659         u16 sc;
5660         u8 tid, ack_policy;
5661
5662 -       if (!ieee80211_is_data_qos(hdr->frame_control))
5663 +       if (!ieee80211_is_data_qos(hdr->frame_control) ||
5664 +           is_multicast_ether_addr(hdr->addr1))
5665                 goto dont_reorder;
5666
5667         /*
5668 --- a/net/mac80211/scan.c
5669 +++ b/net/mac80211/scan.c
5670 @@ -526,7 +526,7 @@ static int __ieee80211_start_scan(struct
5671                 ieee80211_hw_config(local, 0);
5672
5673                 if ((req->channels[0]->flags &
5674 -                    IEEE80211_CHAN_PASSIVE_SCAN) ||
5675 +                    IEEE80211_CHAN_NO_IR) ||
5676                     !local->scan_req->n_ssids) {
5677                         next_delay = IEEE80211_PASSIVE_CHANNEL_TIME;
5678                 } else {
5679 @@ -572,7 +572,7 @@ ieee80211_scan_get_channel_time(struct i
5680          * TODO: channel switching also consumes quite some time,
5681          * add that delay as well to get a better estimation
5682          */
5683 -       if (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN)
5684 +       if (chan->flags & IEEE80211_CHAN_NO_IR)
5685                 return IEEE80211_PASSIVE_CHANNEL_TIME;
5686         return IEEE80211_PROBE_DELAY + IEEE80211_CHANNEL_TIME;
5687  }
5688 @@ -696,7 +696,7 @@ static void ieee80211_scan_state_set_cha
5689          *
5690          * In any case, it is not necessary for a passive scan.
5691          */
5692 -       if (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN ||
5693 +       if (chan->flags & IEEE80211_CHAN_NO_IR ||
5694             !local->scan_req->n_ssids) {
5695                 *next_delay = IEEE80211_PASSIVE_CHANNEL_TIME;
5696                 local->next_scan_state = SCAN_DECISION;
5697 @@ -881,7 +881,7 @@ int ieee80211_request_ibss_scan(struct i
5698                                 struct ieee80211_channel *tmp_ch =
5699                                     &local->hw.wiphy->bands[band]->channels[i];
5700
5701 -                               if (tmp_ch->flags & (IEEE80211_CHAN_NO_IBSS |
5702 +                               if (tmp_ch->flags & (IEEE80211_CHAN_NO_IR |
5703                                                      IEEE80211_CHAN_DISABLED))
5704                                         continue;
5705
5706 @@ -895,7 +895,7 @@ int ieee80211_request_ibss_scan(struct i
5707
5708                 local->int_scan_req->n_channels = n_ch;
5709         } else {
5710 -               if (WARN_ON_ONCE(chan->flags & (IEEE80211_CHAN_NO_IBSS |
5711 +               if (WARN_ON_ONCE(chan->flags & (IEEE80211_CHAN_NO_IR |
5712                                                 IEEE80211_CHAN_DISABLED)))
5713                         goto unlock;
5714
5715 --- a/net/mac80211/tx.c
5716 +++ b/net/mac80211/tx.c
5717 @@ -463,7 +463,6 @@ ieee80211_tx_h_unicast_ps_buf(struct iee
5718  {
5719         struct sta_info *sta = tx->sta;
5720         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx->skb);
5721 -       struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)tx->skb->data;
5722         struct ieee80211_local *local = tx->local;
5723
5724         if (unlikely(!sta))
5725 @@ -474,15 +473,6 @@ ieee80211_tx_h_unicast_ps_buf(struct iee
5726                      !(info->flags & IEEE80211_TX_CTL_NO_PS_BUFFER))) {
5727                 int ac = skb_get_queue_mapping(tx->skb);
5728
5729 -               /* only deauth, disassoc and action are bufferable MMPDUs */
5730 -               if (ieee80211_is_mgmt(hdr->frame_control) &&
5731 -                   !ieee80211_is_deauth(hdr->frame_control) &&
5732 -                   !ieee80211_is_disassoc(hdr->frame_control) &&
5733 -                   !ieee80211_is_action(hdr->frame_control)) {
5734 -                       info->flags |= IEEE80211_TX_CTL_NO_PS_BUFFER;
5735 -                       return TX_CONTINUE;
5736 -               }
5737 -
5738                 ps_dbg(sta->sdata, "STA %pM aid %d: PS buffer for AC %d\n",
5739                        sta->sta.addr, sta->sta.aid, ac);
5740                 if (tx->local->total_ps_buffered >= TOTAL_MAX_TX_BUFFER)
5741 @@ -525,9 +515,21 @@ ieee80211_tx_h_unicast_ps_buf(struct iee
5742  static ieee80211_tx_result debug_noinline
5743  ieee80211_tx_h_ps_buf(struct ieee80211_tx_data *tx)
5744  {
5745 +       struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx->skb);
5746 +       struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)tx->skb->data;
5747 +
5748         if (unlikely(tx->flags & IEEE80211_TX_PS_BUFFERED))
5749                 return TX_CONTINUE;
5750
5751 +       /* only deauth, disassoc and action are bufferable MMPDUs */
5752 +       if (ieee80211_is_mgmt(hdr->frame_control) &&
5753 +           !ieee80211_is_deauth(hdr->frame_control) &&
5754 +           !ieee80211_is_disassoc(hdr->frame_control) &&
5755 +           !ieee80211_is_action(hdr->frame_control)) {
5756 +               info->flags |= IEEE80211_TX_CTL_NO_PS_BUFFER;
5757 +               return TX_CONTINUE;
5758 +       }
5759 +
5760         if (tx->flags & IEEE80211_TX_UNICAST)
5761                 return ieee80211_tx_h_unicast_ps_buf(tx);
5762         else
5763 @@ -1728,8 +1730,7 @@ netdev_tx_t ieee80211_monitor_start_xmit
5764          * radar detection by itself. We can do that later by adding a
5765          * monitor flag interfaces used for AP support.
5766          */
5767 -       if ((chan->flags & (IEEE80211_CHAN_NO_IBSS | IEEE80211_CHAN_RADAR |
5768 -                           IEEE80211_CHAN_PASSIVE_SCAN)))
5769 +       if ((chan->flags & (IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_RADAR)))
5770                 goto fail_rcu;
5771
5772         ieee80211_xmit(sdata, skb, chan->band);
5773 @@ -2530,7 +2531,8 @@ struct sk_buff *ieee80211_beacon_get_tim
5774                          */
5775                         skb = dev_alloc_skb(local->tx_headroom +
5776                                             beacon->head_len +
5777 -                                           beacon->tail_len + 256);
5778 +                                           beacon->tail_len + 256 +
5779 +                                           local->hw.extra_beacon_tailroom);
5780                         if (!skb)
5781                                 goto out;
5782
5783 @@ -2562,7 +2564,8 @@ struct sk_buff *ieee80211_beacon_get_tim
5784                         ieee80211_update_csa(sdata, presp);
5785
5786
5787 -               skb = dev_alloc_skb(local->tx_headroom + presp->head_len);
5788 +               skb = dev_alloc_skb(local->tx_headroom + presp->head_len +
5789 +                                   local->hw.extra_beacon_tailroom);
5790                 if (!skb)
5791                         goto out;
5792                 skb_reserve(skb, local->tx_headroom);
5793 @@ -2589,7 +2592,8 @@ struct sk_buff *ieee80211_beacon_get_tim
5794                 skb = dev_alloc_skb(local->tx_headroom +
5795                                     bcn->head_len +
5796                                     256 + /* TIM IE */
5797 -                                   bcn->tail_len);
5798 +                                   bcn->tail_len +
5799 +                                   local->hw.extra_beacon_tailroom);
5800                 if (!skb)
5801                         goto out;
5802                 skb_reserve(skb, local->tx_headroom);
5803 --- a/net/mac80211/util.c
5804 +++ b/net/mac80211/util.c
5805 @@ -2259,14 +2259,17 @@ u64 ieee80211_calculate_rx_timestamp(str
5806  void ieee80211_dfs_cac_cancel(struct ieee80211_local *local)
5807  {
5808         struct ieee80211_sub_if_data *sdata;
5809 +       struct cfg80211_chan_def chandef;
5810
5811         mutex_lock(&local->iflist_mtx);
5812         list_for_each_entry(sdata, &local->interfaces, list) {
5813                 cancel_delayed_work_sync(&sdata->dfs_cac_timer_work);
5814
5815                 if (sdata->wdev.cac_started) {
5816 +                       chandef = sdata->vif.bss_conf.chandef;
5817                         ieee80211_vif_release_channel(sdata);
5818                         cfg80211_cac_event(sdata->dev,
5819 +                                          &chandef,
5820                                            NL80211_RADAR_CAC_ABORTED,
5821                                            GFP_KERNEL);
5822                 }
5823 @@ -2459,16 +2462,146 @@ int ieee80211_send_action_csa(struct iee
5824                           WLAN_EID_CHAN_SWITCH_PARAM_TX_RESTRICT : 0x00;
5825                 put_unaligned_le16(WLAN_REASON_MESH_CHAN, pos); /* Reason Cd */
5826                 pos += 2;
5827 -               if (!ifmsh->pre_value)
5828 -                       ifmsh->pre_value = 1;
5829 -               else
5830 -                       ifmsh->pre_value++;
5831                 pre_value = cpu_to_le16(ifmsh->pre_value);
5832                 memcpy(pos, &pre_value, 2);             /* Precedence Value */
5833                 pos += 2;
5834 -               ifmsh->chsw_init = true;
5835         }
5836
5837         ieee80211_tx_skb(sdata, skb);
5838         return 0;
5839  }
5840 +
5841 +static bool
5842 +ieee80211_extend_noa_desc(struct ieee80211_noa_data *data, u32 tsf, int i)
5843 +{
5844 +       s32 end = data->desc[i].start + data->desc[i].duration - (tsf + 1);
5845 +       int skip;
5846 +
5847 +       if (end > 0)
5848 +               return false;
5849 +
5850 +       /* End time is in the past, check for repetitions */
5851 +       skip = DIV_ROUND_UP(-end, data->desc[i].interval);
5852 +       if (data->count[i] < 255) {
5853 +               if (data->count[i] <= skip) {
5854 +                       data->count[i] = 0;
5855 +                       return false;
5856 +               }
5857 +
5858 +               data->count[i] -= skip;
5859 +       }
5860 +
5861 +       data->desc[i].start += skip * data->desc[i].interval;
5862 +
5863 +       return true;
5864 +}
5865 +
5866 +static bool
5867 +ieee80211_extend_absent_time(struct ieee80211_noa_data *data, u32 tsf,
5868 +                            s32 *offset)
5869 +{
5870 +       bool ret = false;
5871 +       int i;
5872 +
5873 +       for (i = 0; i < IEEE80211_P2P_NOA_DESC_MAX; i++) {
5874 +               s32 cur;
5875 +
5876 +               if (!data->count[i])
5877 +                       continue;
5878 +
5879 +               if (ieee80211_extend_noa_desc(data, tsf + *offset, i))
5880 +                       ret = true;
5881 +
5882 +               cur = data->desc[i].start - tsf;
5883 +               if (cur > *offset)
5884 +                       continue;
5885 +
5886 +               cur = data->desc[i].start + data->desc[i].duration - tsf;
5887 +               if (cur > *offset)
5888 +                       *offset = cur;
5889 +       }
5890 +
5891 +       return ret;
5892 +}
5893 +
5894 +static u32
5895 +ieee80211_get_noa_absent_time(struct ieee80211_noa_data *data, u32 tsf)
5896 +{
5897 +       s32 offset = 0;
5898 +       int tries = 0;
5899 +
5900 +       ieee80211_extend_absent_time(data, tsf, &offset);
5901 +       do {
5902 +               if (!ieee80211_extend_absent_time(data, tsf, &offset))
5903 +                       break;
5904 +
5905 +               tries++;
5906 +       } while (tries < 5);
5907 +
5908 +       return offset;
5909 +}
5910 +
5911 +void ieee80211_update_p2p_noa(struct ieee80211_noa_data *data, u32 tsf)
5912 +{
5913 +       u32 next_offset = BIT(31) - 1;
5914 +       int i;
5915 +
5916 +       data->absent = 0;
5917 +       data->has_next_tsf = false;
5918 +       for (i = 0; i < IEEE80211_P2P_NOA_DESC_MAX; i++) {
5919 +               s32 start;
5920 +
5921 +               if (!data->count[i])
5922 +                       continue;
5923 +
5924 +               ieee80211_extend_noa_desc(data, tsf, i);
5925 +               start = data->desc[i].start - tsf;
5926 +               if (start <= 0)
5927 +                       data->absent |= BIT(i);
5928 +
5929 +               if (next_offset > start)
5930 +                       next_offset = start;
5931 +
5932 +               data->has_next_tsf = true;
5933 +       }
5934 +
5935 +       if (data->absent)
5936 +               next_offset = ieee80211_get_noa_absent_time(data, tsf);
5937 +
5938 +       data->next_tsf = tsf + next_offset;
5939 +}
5940 +EXPORT_SYMBOL(ieee80211_update_p2p_noa);
5941 +
5942 +int ieee80211_parse_p2p_noa(const struct ieee80211_p2p_noa_attr *attr,
5943 +                           struct ieee80211_noa_data *data, u32 tsf)
5944 +{
5945 +       int ret = 0;
5946 +       int i;
5947 +
5948 +       memset(data, 0, sizeof(*data));
5949 +
5950 +       for (i = 0; i < IEEE80211_P2P_NOA_DESC_MAX; i++) {
5951 +               const struct ieee80211_p2p_noa_desc *desc = &attr->desc[i];
5952 +
5953 +               if (!desc->count || !desc->duration)
5954 +                       continue;
5955 +
5956 +               data->count[i] = desc->count;
5957 +               data->desc[i].start = le32_to_cpu(desc->start_time);
5958 +               data->desc[i].duration = le32_to_cpu(desc->duration);
5959 +               data->desc[i].interval = le32_to_cpu(desc->interval);
5960 +
5961 +               if (data->count[i] > 1 &&
5962 +                   data->desc[i].interval < data->desc[i].duration)
5963 +                       continue;
5964 +
5965 +               ieee80211_extend_noa_desc(data, tsf, i);
5966 +               ret++;
5967 +       }
5968 +
5969 +       if (ret)
5970 +               ieee80211_update_p2p_noa(data, tsf);
5971 +
5972 +       return ret;
5973 +}
5974 +EXPORT_SYMBOL(ieee80211_parse_p2p_noa);
5975 --- a/net/wireless/chan.c
5976 +++ b/net/wireless/chan.c
5977 @@ -277,6 +277,32 @@ void cfg80211_set_dfs_state(struct wiphy
5978                                      width, dfs_state);
5979  }
5980
5981 +static u32 cfg80211_get_start_freq(u32 center_freq,
5982 +                                  u32 bandwidth)
5983 +{
5984 +       u32 start_freq;
5985 +
5986 +       if (bandwidth <= 20)
5987 +               start_freq = center_freq;
5988 +       else
5989 +               start_freq = center_freq - bandwidth/2 + 10;
5990 +
5991 +       return start_freq;
5992 +}
5993 +
5994 +static u32 cfg80211_get_end_freq(u32 center_freq,
5995 +                                u32 bandwidth)
5996 +{
5997 +       u32 end_freq;
5998 +
5999 +       if (bandwidth <= 20)
6000 +               end_freq = center_freq;
6001 +       else
6002 +               end_freq = center_freq + bandwidth/2 - 10;
6003 +
6004 +       return end_freq;
6005 +}
6006 +
6007  static int cfg80211_get_chans_dfs_required(struct wiphy *wiphy,
6008                                             u32 center_freq,
6009                                             u32 bandwidth)
6010 @@ -284,13 +310,8 @@ static int cfg80211_get_chans_dfs_requir
6011         struct ieee80211_channel *c;
6012         u32 freq, start_freq, end_freq;
6013
6014 -       if (bandwidth <= 20) {
6015 -               start_freq = center_freq;
6016 -               end_freq = center_freq;
6017 -       } else {
6018 -               start_freq = center_freq - bandwidth/2 + 10;
6019 -               end_freq = center_freq + bandwidth/2 - 10;
6020 -       }
6021 +       start_freq = cfg80211_get_start_freq(center_freq, bandwidth);
6022 +       end_freq = cfg80211_get_end_freq(center_freq, bandwidth);
6023
6024         for (freq = start_freq; freq <= end_freq; freq += 20) {
6025                 c = ieee80211_get_channel(wiphy, freq);
6026 @@ -330,33 +351,159 @@ int cfg80211_chandef_dfs_required(struct
6027  }
6028  EXPORT_SYMBOL(cfg80211_chandef_dfs_required);
6029
6030 -static bool cfg80211_secondary_chans_ok(struct wiphy *wiphy,
6031 -                                       u32 center_freq, u32 bandwidth,
6032 -                                       u32 prohibited_flags)
6033 +static int cfg80211_get_chans_dfs_usable(struct wiphy *wiphy,
6034 +                                        u32 center_freq,
6035 +                                        u32 bandwidth)
6036  {
6037         struct ieee80211_channel *c;
6038         u32 freq, start_freq, end_freq;
6039 +       int count = 0;
6040
6041 -       if (bandwidth <= 20) {
6042 -               start_freq = center_freq;
6043 -               end_freq = center_freq;
6044 -       } else {
6045 -               start_freq = center_freq - bandwidth/2 + 10;
6046 -               end_freq = center_freq + bandwidth/2 - 10;
6047 +       start_freq = cfg80211_get_start_freq(center_freq, bandwidth);
6048 +       end_freq = cfg80211_get_end_freq(center_freq, bandwidth);
6049 +
6050 +       /*
6051 +        * Check entire range of channels for the bandwidth.
6052 +        * Check all channels are DFS channels (DFS_USABLE or
6053 +        * DFS_AVAILABLE). Return number of usable channels
6054 +        * (require CAC). Allow DFS and non-DFS channel mix.
6055 +        */
6056 +       for (freq = start_freq; freq <= end_freq; freq += 20) {
6057 +               c = ieee80211_get_channel(wiphy, freq);
6058 +               if (!c)
6059 +                       return -EINVAL;
6060 +
6061 +               if (c->flags & IEEE80211_CHAN_DISABLED)
6062 +                       return -EINVAL;
6063 +
6064 +               if (c->flags & IEEE80211_CHAN_RADAR) {
6065 +                       if (c->dfs_state == NL80211_DFS_UNAVAILABLE)
6066 +                               return -EINVAL;
6067 +
6068 +                       if (c->dfs_state == NL80211_DFS_USABLE)
6069 +                               count++;
6070 +               }
6071 +       }
6072 +
6073 +       return count;
6074 +}
6075 +
6076 +bool cfg80211_chandef_dfs_usable(struct wiphy *wiphy,
6077 +                                const struct cfg80211_chan_def *chandef)
6078 +{
6079 +       int width;
6080 +       int r1, r2 = 0;
6081 +
6082 +       if (WARN_ON(!cfg80211_chandef_valid(chandef)))
6083 +               return false;
6084 +
6085 +       width = cfg80211_chandef_get_width(chandef);
6086 +       if (width < 0)
6087 +               return false;
6088 +
6089 +       r1 = cfg80211_get_chans_dfs_usable(wiphy, chandef->center_freq1,
6090 +                                         width);
6091 +
6092 +       if (r1 < 0)
6093 +               return false;
6094 +
6095 +       switch (chandef->width) {
6096 +       case NL80211_CHAN_WIDTH_80P80:
6097 +               WARN_ON(!chandef->center_freq2);
6098 +               r2 = cfg80211_get_chans_dfs_usable(wiphy,
6099 +                                                  chandef->center_freq2,
6100 +                                                  width);
6101 +               if (r2 < 0)
6102 +                       return false;
6103 +               break;
6104 +       default:
6105 +               WARN_ON(chandef->center_freq2);
6106 +               break;
6107         }
6108
6109 +       return (r1 + r2 > 0);
6110 +}
6111 +
6112 +
6113 +static bool cfg80211_get_chans_dfs_available(struct wiphy *wiphy,
6114 +                                            u32 center_freq,
6115 +                                            u32 bandwidth)
6116 +{
6117 +       struct ieee80211_channel *c;
6118 +       u32 freq, start_freq, end_freq;
6119 +
6120 +       start_freq = cfg80211_get_start_freq(center_freq, bandwidth);
6121 +       end_freq = cfg80211_get_end_freq(center_freq, bandwidth);
6122 +
6123 +       /*
6124 +        * Check entire range of channels for the bandwidth.
6125 +        * If any channel in between is disabled or has not
6126 +        * had gone through CAC return false
6127 +        */
6128         for (freq = start_freq; freq <= end_freq; freq += 20) {
6129                 c = ieee80211_get_channel(wiphy, freq);
6130                 if (!c)
6131                         return false;
6132
6133 -               /* check for radar flags */
6134 -               if ((prohibited_flags & c->flags & IEEE80211_CHAN_RADAR) &&
6135 +               if (c->flags & IEEE80211_CHAN_DISABLED)
6136 +                       return false;
6137 +
6138 +               if ((c->flags & IEEE80211_CHAN_RADAR)  &&
6139                     (c->dfs_state != NL80211_DFS_AVAILABLE))
6140                         return false;
6141 +       }
6142 +
6143 +       return true;
6144 +}
6145 +
6146 +static bool cfg80211_chandef_dfs_available(struct wiphy *wiphy,
6147 +                               const struct cfg80211_chan_def *chandef)
6148 +{
6149 +       int width;
6150 +       int r;
6151 +
6152 +       if (WARN_ON(!cfg80211_chandef_valid(chandef)))
6153 +               return false;
6154
6155 -               /* check for the other flags */
6156 -               if (c->flags & prohibited_flags & ~IEEE80211_CHAN_RADAR)
6157 +       width = cfg80211_chandef_get_width(chandef);
6158 +       if (width < 0)
6159 +               return false;
6160 +
6161 +       r = cfg80211_get_chans_dfs_available(wiphy, chandef->center_freq1,
6162 +                                            width);
6163 +
6164 +       /* If any of channels unavailable for cf1 just return */
6165 +       if (!r)
6166 +               return r;
6167 +
6168 +       switch (chandef->width) {
6169 +       case NL80211_CHAN_WIDTH_80P80:
6170 +               WARN_ON(!chandef->center_freq2);
6171 +               r = cfg80211_get_chans_dfs_available(wiphy,
6172 +                                                    chandef->center_freq2,
6173 +                                                    width);
6174 +       default:
6175 +               WARN_ON(chandef->center_freq2);
6176 +               break;
6177 +       }
6178 +
6179 +       return r;
6180 +}
6181 +
6182 +
6183 +static bool cfg80211_secondary_chans_ok(struct wiphy *wiphy,
6184 +                                       u32 center_freq, u32 bandwidth,
6185 +                                       u32 prohibited_flags)
6186 +{
6187 +       struct ieee80211_channel *c;
6188 +       u32 freq, start_freq, end_freq;
6189 +
6190 +       start_freq = cfg80211_get_start_freq(center_freq, bandwidth);
6191 +       end_freq = cfg80211_get_end_freq(center_freq, bandwidth);
6192 +
6193 +       for (freq = start_freq; freq <= end_freq; freq += 20) {
6194 +               c = ieee80211_get_channel(wiphy, freq);
6195 +               if (!c || c->flags & prohibited_flags)
6196                         return false;
6197         }
6198
6199 @@ -462,14 +609,19 @@ bool cfg80211_reg_can_beacon(struct wiph
6200                              struct cfg80211_chan_def *chandef)
6201  {
6202         bool res;
6203 +       u32 prohibited_flags = IEEE80211_CHAN_DISABLED |
6204 +                              IEEE80211_CHAN_NO_IR |
6205 +                              IEEE80211_CHAN_RADAR;
6206
6207         trace_cfg80211_reg_can_beacon(wiphy, chandef);
6208
6209 -       res = cfg80211_chandef_usable(wiphy, chandef,
6210 -                                     IEEE80211_CHAN_DISABLED |
6211 -                                     IEEE80211_CHAN_PASSIVE_SCAN |
6212 -                                     IEEE80211_CHAN_NO_IBSS |
6213 -                                     IEEE80211_CHAN_RADAR);
6214 +       if (cfg80211_chandef_dfs_required(wiphy, chandef) > 0 &&
6215 +           cfg80211_chandef_dfs_available(wiphy, chandef)) {
6216 +               /* We can skip IEEE80211_CHAN_NO_IR if chandef dfs available */
6217 +               prohibited_flags = IEEE80211_CHAN_DISABLED;
6218 +       }
6219 +
6220 +       res = cfg80211_chandef_usable(wiphy, chandef, prohibited_flags);
6221
6222         trace_cfg80211_return_bool(res);
6223         return res;
6224 --- a/net/wireless/core.h
6225 +++ b/net/wireless/core.h
6226 @@ -382,6 +382,19 @@ int cfg80211_can_use_iftype_chan(struct
6227                                  enum cfg80211_chan_mode chanmode,
6228                                  u8 radar_detect);
6229
6230 +/**
6231 + * cfg80211_chandef_dfs_usable - checks if chandef is DFS usable
6232 + * @wiphy: the wiphy to validate against
6233 + * @chandef: the channel definition to check
6234 + *
6235 + * Checks if chandef is usable and we can/need start CAC on such channel.
6236 + *
6237 + * Return: Return true if all channels available and at least
6238 + *        one channel require CAC (NL80211_DFS_USABLE)
6239 + */
6240 +bool cfg80211_chandef_dfs_usable(struct wiphy *wiphy,
6241 +                                const struct cfg80211_chan_def *chandef);
6242 +
6243  void cfg80211_set_dfs_state(struct wiphy *wiphy,
6244                             const struct cfg80211_chan_def *chandef,
6245                             enum nl80211_dfs_state dfs_state);
6246 --- a/net/wireless/genregdb.awk
6247 +++ b/net/wireless/genregdb.awk
6248 @@ -107,10 +107,13 @@ active && /^[ \t]*\(/ {
6249                 } else if (flagarray[arg] == "PTMP-ONLY") {
6250                         flags = flags "\n\t\t\tNL80211_RRF_PTMP_ONLY | "
6251                 } else if (flagarray[arg] == "PASSIVE-SCAN") {
6252 -                       flags = flags "\n\t\t\tNL80211_RRF_PASSIVE_SCAN | "
6253 +                       flags = flags "\n\t\t\tNL80211_RRF_NO_IR | "
6254                 } else if (flagarray[arg] == "NO-IBSS") {
6255 -                       flags = flags "\n\t\t\tNL80211_RRF_NO_IBSS | "
6256 +                       flags = flags "\n\t\t\tNL80211_RRF_NO_IR | "
6257 +               } else if (flagarray[arg] == "NO-IR") {
6258 +                       flags = flags "\n\t\t\tNL80211_RRF_NO_IR | "
6259                 }
6260 +
6261         }
6262         flags = flags "0"
6263         printf "\t\tREG_RULE(%d, %d, %d, %d, %d, %s),\n", start, end, bw, gain, power, flags
6264 --- a/net/wireless/ibss.c
6265 +++ b/net/wireless/ibss.c
6266 @@ -274,7 +274,7 @@ int cfg80211_ibss_wext_join(struct cfg80
6267
6268                         for (i = 0; i < sband->n_channels; i++) {
6269                                 chan = &sband->channels[i];
6270 -                               if (chan->flags & IEEE80211_CHAN_NO_IBSS)
6271 +                               if (chan->flags & IEEE80211_CHAN_NO_IR)
6272                                         continue;
6273                                 if (chan->flags & IEEE80211_CHAN_DISABLED)
6274                                         continue;
6275 @@ -345,7 +345,7 @@ int cfg80211_ibss_wext_siwfreq(struct ne
6276                 chan = ieee80211_get_channel(wdev->wiphy, freq);
6277                 if (!chan)
6278                         return -EINVAL;
6279 -               if (chan->flags & IEEE80211_CHAN_NO_IBSS ||
6280 +               if (chan->flags & IEEE80211_CHAN_NO_IR ||
6281                     chan->flags & IEEE80211_CHAN_DISABLED)
6282                         return -EINVAL;
6283         }
6284 --- a/net/wireless/mesh.c
6285 +++ b/net/wireless/mesh.c
6286 @@ -141,8 +141,7 @@ int __cfg80211_join_mesh(struct cfg80211
6287
6288                         for (i = 0; i < sband->n_channels; i++) {
6289                                 chan = &sband->channels[i];
6290 -                               if (chan->flags & (IEEE80211_CHAN_NO_IBSS |
6291 -                                                  IEEE80211_CHAN_PASSIVE_SCAN |
6292 +                               if (chan->flags & (IEEE80211_CHAN_NO_IR |
6293                                                    IEEE80211_CHAN_DISABLED |
6294                                                    IEEE80211_CHAN_RADAR))
6295                                         continue;
6296 --- a/net/wireless/mlme.c
6297 +++ b/net/wireless/mlme.c
6298 @@ -763,12 +763,12 @@ void cfg80211_radar_event(struct wiphy *
6299  EXPORT_SYMBOL(cfg80211_radar_event);
6300
6301  void cfg80211_cac_event(struct net_device *netdev,
6302 +                       const struct cfg80211_chan_def *chandef,
6303                         enum nl80211_radar_event event, gfp_t gfp)
6304  {
6305         struct wireless_dev *wdev = netdev->ieee80211_ptr;
6306         struct wiphy *wiphy = wdev->wiphy;
6307         struct cfg80211_registered_device *rdev = wiphy_to_dev(wiphy);
6308 -       struct cfg80211_chan_def chandef;
6309         unsigned long timeout;
6310
6311         trace_cfg80211_cac_event(netdev, event);
6312 @@ -779,14 +779,12 @@ void cfg80211_cac_event(struct net_devic
6313         if (WARN_ON(!wdev->channel))
6314                 return;
6315
6316 -       cfg80211_chandef_create(&chandef, wdev->channel, NL80211_CHAN_NO_HT);
6317 -
6318         switch (event) {
6319         case NL80211_RADAR_CAC_FINISHED:
6320                 timeout = wdev->cac_start_time +
6321                           msecs_to_jiffies(IEEE80211_DFS_MIN_CAC_TIME_MS);
6322                 WARN_ON(!time_after_eq(jiffies, timeout));
6323 -               cfg80211_set_dfs_state(wiphy, &chandef, NL80211_DFS_AVAILABLE);
6324 +               cfg80211_set_dfs_state(wiphy, chandef, NL80211_DFS_AVAILABLE);
6325                 break;
6326         case NL80211_RADAR_CAC_ABORTED:
6327                 break;
6328 @@ -796,6 +794,6 @@ void cfg80211_cac_event(struct net_devic
6329         }
6330         wdev->cac_started = false;
6331
6332 -       nl80211_radar_notify(rdev, &chandef, event, netdev, gfp);
6333 +       nl80211_radar_notify(rdev, chandef, event, netdev, gfp);
6334  }
6335  EXPORT_SYMBOL(cfg80211_cac_event);
6336 --- a/net/wireless/nl80211.c
6337 +++ b/net/wireless/nl80211.c
6338 @@ -545,12 +545,12 @@ static int nl80211_msg_put_channel(struc
6339         if ((chan->flags & IEEE80211_CHAN_DISABLED) &&
6340             nla_put_flag(msg, NL80211_FREQUENCY_ATTR_DISABLED))
6341                 goto nla_put_failure;
6342 -       if ((chan->flags & IEEE80211_CHAN_PASSIVE_SCAN) &&
6343 -           nla_put_flag(msg, NL80211_FREQUENCY_ATTR_PASSIVE_SCAN))
6344 -               goto nla_put_failure;
6345 -       if ((chan->flags & IEEE80211_CHAN_NO_IBSS) &&
6346 -           nla_put_flag(msg, NL80211_FREQUENCY_ATTR_NO_IBSS))
6347 -               goto nla_put_failure;
6348 +       if (chan->flags & IEEE80211_CHAN_NO_IR) {
6349 +               if (nla_put_flag(msg, NL80211_FREQUENCY_ATTR_NO_IR))
6350 +                       goto nla_put_failure;
6351 +               if (nla_put_flag(msg, __NL80211_FREQUENCY_ATTR_NO_IBSS))
6352 +                       goto nla_put_failure;
6353 +       }
6354         if (chan->flags & IEEE80211_CHAN_RADAR) {
6355                 if (nla_put_flag(msg, NL80211_FREQUENCY_ATTR_RADAR))
6356                         goto nla_put_failure;
6357 @@ -1229,7 +1229,8 @@ static int nl80211_send_wiphy(struct cfg
6358                     nla_put_flag(msg, NL80211_ATTR_TDLS_EXTERNAL_SETUP))
6359                         goto nla_put_failure;
6360                 if ((dev->wiphy.flags & WIPHY_FLAG_SUPPORTS_5_10_MHZ) &&
6361 -                   nla_put_flag(msg, WIPHY_FLAG_SUPPORTS_5_10_MHZ))
6362 +                   (nla_put_flag(msg, NL80211_ATTR_SUPPORT_5_MHZ) ||
6363 +                    nla_put_flag(msg, NL80211_ATTR_SUPPORT_10_MHZ)))
6364                         goto nla_put_failure;
6365
6366                 state->split_start++;
6367 @@ -2170,7 +2171,7 @@ static inline u64 wdev_id(struct wireles
6368  }
6369
6370  static int nl80211_send_chandef(struct sk_buff *msg,
6371 -                                struct cfg80211_chan_def *chandef)
6372 +                               const struct cfg80211_chan_def *chandef)
6373  {
6374         WARN_ON(!cfg80211_chandef_valid(chandef));
6375
6376 @@ -3219,6 +3220,7 @@ static int nl80211_start_ap(struct sk_bu
6377                         return PTR_ERR(params.acl);
6378         }
6379
6380 +       wdev_lock(wdev);
6381         err = rdev_start_ap(rdev, dev, &params);
6382         if (!err) {
6383                 wdev->preset_chandef = params.chandef;
6384 @@ -3227,6 +3229,7 @@ static int nl80211_start_ap(struct sk_bu
6385                 wdev->ssid_len = params.ssid_len;
6386                 memcpy(wdev->ssid, params.ssid, wdev->ssid_len);
6387         }
6388 +       wdev_unlock(wdev);
6389
6390         kfree(params.acl);
6391
6392 @@ -3255,7 +3258,11 @@ static int nl80211_set_beacon(struct sk_
6393         if (err)
6394                 return err;
6395
6396 -       return rdev_change_beacon(rdev, dev, &params);
6397 +       wdev_lock(wdev);
6398 +       err = rdev_change_beacon(rdev, dev, &params);
6399 +       wdev_unlock(wdev);
6400 +
6401 +       return err;
6402  }
6403
6404  static int nl80211_stop_ap(struct sk_buff *skb, struct genl_info *info)
6405 @@ -4461,7 +4468,9 @@ static int nl80211_set_bss(struct sk_buf
6406  {
6407         struct cfg80211_registered_device *rdev = info->user_ptr[0];
6408         struct net_device *dev = info->user_ptr[1];
6409 +       struct wireless_dev *wdev = dev->ieee80211_ptr;
6410         struct bss_parameters params;
6411 +       int err;
6412
6413         memset(&params, 0, sizeof(params));
6414         /* default to not changing parameters */
6415 @@ -4527,7 +4536,11 @@ static int nl80211_set_bss(struct sk_buf
6416             dev->ieee80211_ptr->iftype != NL80211_IFTYPE_P2P_GO)
6417                 return -EOPNOTSUPP;
6418
6419 -       return rdev_change_bss(rdev, dev, &params);
6420 +       wdev_lock(wdev);
6421 +       err = rdev_change_bss(rdev, dev, &params);
6422 +       wdev_unlock(wdev);
6423 +
6424 +       return err;
6425  }
6426
6427  static const struct nla_policy reg_rule_policy[NL80211_REG_RULE_ATTR_MAX + 1] = {
6428 @@ -5653,7 +5666,7 @@ static int nl80211_start_radar_detection
6429         if (err == 0)
6430                 return -EINVAL;
6431
6432 -       if (chandef.chan->dfs_state != NL80211_DFS_USABLE)
6433 +       if (!cfg80211_chandef_dfs_usable(wdev->wiphy, &chandef))
6434                 return -EINVAL;
6435
6436         if (!rdev->ops->start_radar_detection)
6437 @@ -5793,7 +5806,11 @@ skip_beacons:
6438         if (info->attrs[NL80211_ATTR_CH_SWITCH_BLOCK_TX])
6439                 params.block_tx = true;
6440
6441 -       return rdev_channel_switch(rdev, dev, &params);
6442 +       wdev_lock(wdev);
6443 +       err = rdev_channel_switch(rdev, dev, &params);
6444 +       wdev_unlock(wdev);
6445 +
6446 +       return err;
6447  }
6448
6449  static int nl80211_send_bss(struct sk_buff *msg, struct netlink_callback *cb,
6450 @@ -10809,21 +10826,18 @@ void cfg80211_ch_switch_notify(struct ne
6451         struct wiphy *wiphy = wdev->wiphy;
6452         struct cfg80211_registered_device *rdev = wiphy_to_dev(wiphy);
6453
6454 -       trace_cfg80211_ch_switch_notify(dev, chandef);
6455 +       ASSERT_WDEV_LOCK(wdev);
6456
6457 -       wdev_lock(wdev);
6458 +       trace_cfg80211_ch_switch_notify(dev, chandef);
6459
6460         if (WARN_ON(wdev->iftype != NL80211_IFTYPE_AP &&
6461                     wdev->iftype != NL80211_IFTYPE_P2P_GO &&
6462                     wdev->iftype != NL80211_IFTYPE_ADHOC &&
6463                     wdev->iftype != NL80211_IFTYPE_MESH_POINT))
6464 -               goto out;
6465 +               return;
6466
6467         wdev->channel = chandef->chan;
6468         nl80211_ch_switch_notify(rdev, dev, chandef, GFP_KERNEL);
6469 -out:
6470 -       wdev_unlock(wdev);
6471 -       return;
6472  }
6473  EXPORT_SYMBOL(cfg80211_ch_switch_notify);
6474
6475 @@ -10882,7 +10896,7 @@ EXPORT_SYMBOL(cfg80211_cqm_txe_notify);
6476
6477  void
6478  nl80211_radar_notify(struct cfg80211_registered_device *rdev,
6479 -                    struct cfg80211_chan_def *chandef,
6480 +                    const struct cfg80211_chan_def *chandef,
6481                      enum nl80211_radar_event event,
6482                      struct net_device *netdev, gfp_t gfp)
6483  {
6484 --- a/net/wireless/nl80211.h
6485 +++ b/net/wireless/nl80211.h
6486 @@ -70,7 +70,7 @@ int nl80211_send_mgmt(struct cfg80211_re
6487
6488  void
6489  nl80211_radar_notify(struct cfg80211_registered_device *rdev,
6490 -                    struct cfg80211_chan_def *chandef,
6491 +                    const struct cfg80211_chan_def *chandef,
6492                      enum nl80211_radar_event event,
6493                      struct net_device *netdev, gfp_t gfp);
6494
6495 --- a/net/wireless/reg.c
6496 +++ b/net/wireless/reg.c
6497 @@ -163,35 +163,29 @@ static const struct ieee80211_regdomain
6498                 REG_RULE(2412-10, 2462+10, 40, 6, 20, 0),
6499                 /* IEEE 802.11b/g, channels 12..13. */
6500                 REG_RULE(2467-10, 2472+10, 40, 6, 20,
6501 -                       NL80211_RRF_PASSIVE_SCAN |
6502 -                       NL80211_RRF_NO_IBSS),
6503 +                       NL80211_RRF_NO_IR),
6504                 /* IEEE 802.11 channel 14 - Only JP enables
6505                  * this and for 802.11b only */
6506                 REG_RULE(2484-10, 2484+10, 20, 6, 20,
6507 -                       NL80211_RRF_PASSIVE_SCAN |
6508 -                       NL80211_RRF_NO_IBSS |
6509 +                       NL80211_RRF_NO_IR |
6510                         NL80211_RRF_NO_OFDM),
6511                 /* IEEE 802.11a, channel 36..48 */
6512                 REG_RULE(5180-10, 5240+10, 160, 6, 20,
6513 -                        NL80211_RRF_PASSIVE_SCAN |
6514 -                        NL80211_RRF_NO_IBSS),
6515 +                        NL80211_RRF_NO_IR),
6516
6517                 /* IEEE 802.11a, channel 52..64 - DFS required */
6518                 REG_RULE(5260-10, 5320+10, 160, 6, 20,
6519 -                       NL80211_RRF_PASSIVE_SCAN |
6520 -                       NL80211_RRF_NO_IBSS |
6521 +                       NL80211_RRF_NO_IR |
6522                         NL80211_RRF_DFS),
6523
6524                 /* IEEE 802.11a, channel 100..144 - DFS required */
6525                 REG_RULE(5500-10, 5720+10, 160, 6, 20,
6526 -                       NL80211_RRF_PASSIVE_SCAN |
6527 -                       NL80211_RRF_NO_IBSS |
6528 +                       NL80211_RRF_NO_IR |
6529                         NL80211_RRF_DFS),
6530
6531                 /* IEEE 802.11a, channel 149..165 */
6532                 REG_RULE(5745-10, 5825+10, 80, 6, 20,
6533 -                       NL80211_RRF_PASSIVE_SCAN |
6534 -                       NL80211_RRF_NO_IBSS),
6535 +                       NL80211_RRF_NO_IR),
6536
6537                 /* IEEE 802.11ad (60gHz), channels 1..3 */
6538                 REG_RULE(56160+2160*1-1080, 56160+2160*3+1080, 2160, 0, 0, 0),
6539 @@ -698,10 +692,8 @@ regdom_intersect(const struct ieee80211_
6540  static u32 map_regdom_flags(u32 rd_flags)
6541  {
6542         u32 channel_flags = 0;
6543 -       if (rd_flags & NL80211_RRF_PASSIVE_SCAN)
6544 -               channel_flags |= IEEE80211_CHAN_PASSIVE_SCAN;
6545 -       if (rd_flags & NL80211_RRF_NO_IBSS)
6546 -               channel_flags |= IEEE80211_CHAN_NO_IBSS;
6547 +       if (rd_flags & NL80211_RRF_NO_IR_ALL)
6548 +               channel_flags |= IEEE80211_CHAN_NO_IR;
6549         if (rd_flags & NL80211_RRF_DFS)
6550                 channel_flags |= IEEE80211_CHAN_RADAR;
6551         if (rd_flags & NL80211_RRF_NO_OFDM)
6552 @@ -1066,13 +1058,8 @@ static void handle_reg_beacon(struct wip
6553         chan_before.center_freq = chan->center_freq;
6554         chan_before.flags = chan->flags;
6555
6556 -       if (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN) {
6557 -               chan->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
6558 -               channel_changed = true;
6559 -       }
6560 -
6561 -       if (chan->flags & IEEE80211_CHAN_NO_IBSS) {
6562 -               chan->flags &= ~IEEE80211_CHAN_NO_IBSS;
6563 +       if (chan->flags & IEEE80211_CHAN_NO_IR) {
6564 +               chan->flags &= ~IEEE80211_CHAN_NO_IR;
6565                 channel_changed = true;
6566         }
6567
6568 --- /dev/null
6569 +++ b/drivers/net/wireless/ath/ath9k/ar9003_wow.c
6570 @@ -0,0 +1,422 @@
6571 +/*
6572 + * Copyright (c) 2012 Qualcomm Atheros, Inc.
6573 + *
6574 + * Permission to use, copy, modify, and/or distribute this software for any
6575 + * purpose with or without fee is hereby granted, provided that the above
6576 + * copyright notice and this permission notice appear in all copies.
6577 + *
6578 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
6579 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
6580 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
6581 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
6582 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
6583 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
6584 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
6585 + */
6586 +
6587 +#include <linux/export.h>
6588 +#include "ath9k.h"
6589 +#include "reg.h"
6590 +#include "hw-ops.h"
6591 +
6592 +const char *ath9k_hw_wow_event_to_string(u32 wow_event)
6593 +{
6594 +       if (wow_event & AH_WOW_MAGIC_PATTERN_EN)
6595 +               return "Magic pattern";
6596 +       if (wow_event & AH_WOW_USER_PATTERN_EN)
6597 +               return "User pattern";
6598 +       if (wow_event & AH_WOW_LINK_CHANGE)
6599 +               return "Link change";
6600 +       if (wow_event & AH_WOW_BEACON_MISS)
6601 +               return "Beacon miss";
6602 +
6603 +       return  "unknown reason";
6604 +}
6605 +EXPORT_SYMBOL(ath9k_hw_wow_event_to_string);
6606 +
6607 +static void ath9k_hw_set_powermode_wow_sleep(struct ath_hw *ah)
6608 +{
6609 +       struct ath_common *common = ath9k_hw_common(ah);
6610 +
6611 +       REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
6612 +
6613 +       /* set rx disable bit */
6614 +       REG_WRITE(ah, AR_CR, AR_CR_RXD);
6615 +
6616 +       if (!ath9k_hw_wait(ah, AR_CR, AR_CR_RXE, 0, AH_WAIT_TIMEOUT)) {
6617 +               ath_err(common, "Failed to stop Rx DMA in 10ms AR_CR=0x%08x AR_DIAG_SW=0x%08x\n",
6618 +                       REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW));
6619 +               return;
6620 +       }
6621 +
6622 +       REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_ON_INT);
6623 +}
6624 +
6625 +static void ath9k_wow_create_keep_alive_pattern(struct ath_hw *ah)
6626 +{
6627 +       struct ath_common *common = ath9k_hw_common(ah);
6628 +       u8 sta_mac_addr[ETH_ALEN], ap_mac_addr[ETH_ALEN];
6629 +       u32 ctl[13] = {0};
6630 +       u32 data_word[KAL_NUM_DATA_WORDS];
6631 +       u8 i;
6632 +       u32 wow_ka_data_word0;
6633 +
6634 +       memcpy(sta_mac_addr, common->macaddr, ETH_ALEN);
6635 +       memcpy(ap_mac_addr, common->curbssid, ETH_ALEN);
6636 +
6637 +       /* set the transmit buffer */
6638 +       ctl[0] = (KAL_FRAME_LEN | (MAX_RATE_POWER << 16));
6639 +       ctl[1] = 0;
6640 +       ctl[3] = 0xb;   /* OFDM_6M hardware value for this rate */
6641 +       ctl[4] = 0;
6642 +       ctl[7] = (ah->txchainmask) << 2;
6643 +       ctl[2] = 0xf << 16; /* tx_tries 0 */
6644 +
6645 +       for (i = 0; i < KAL_NUM_DESC_WORDS; i++)
6646 +               REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + i * 4), ctl[i]);
6647 +
6648 +       REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + i * 4), ctl[i]);
6649 +
6650 +       data_word[0] = (KAL_FRAME_TYPE << 2) | (KAL_FRAME_SUB_TYPE << 4) |
6651 +                      (KAL_TO_DS << 8) | (KAL_DURATION_ID << 16);
6652 +       data_word[1] = (ap_mac_addr[3] << 24) | (ap_mac_addr[2] << 16) |
6653 +                      (ap_mac_addr[1] << 8) | (ap_mac_addr[0]);
6654 +       data_word[2] = (sta_mac_addr[1] << 24) | (sta_mac_addr[0] << 16) |
6655 +                      (ap_mac_addr[5] << 8) | (ap_mac_addr[4]);
6656 +       data_word[3] = (sta_mac_addr[5] << 24) | (sta_mac_addr[4] << 16) |
6657 +                      (sta_mac_addr[3] << 8) | (sta_mac_addr[2]);
6658 +       data_word[4] = (ap_mac_addr[3] << 24) | (ap_mac_addr[2] << 16) |
6659 +                      (ap_mac_addr[1] << 8) | (ap_mac_addr[0]);
6660 +       data_word[5] = (ap_mac_addr[5] << 8) | (ap_mac_addr[4]);
6661 +
6662 +       if (AR_SREV_9462_20(ah)) {
6663 +               /* AR9462 2.0 has an extra descriptor word (time based
6664 +                * discard) compared to other chips */
6665 +               REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + (12 * 4)), 0);
6666 +               wow_ka_data_word0 = AR_WOW_TXBUF(13);
6667 +       } else {
6668 +               wow_ka_data_word0 = AR_WOW_TXBUF(12);
6669 +       }
6670 +
6671 +       for (i = 0; i < KAL_NUM_DATA_WORDS; i++)
6672 +               REG_WRITE(ah, (wow_ka_data_word0 + i*4), data_word[i]);
6673 +
6674 +}
6675 +
6676 +void ath9k_hw_wow_apply_pattern(struct ath_hw *ah, u8 *user_pattern,
6677 +                               u8 *user_mask, int pattern_count,
6678 +                               int pattern_len)
6679 +{
6680 +       int i;
6681 +       u32 pattern_val, mask_val;
6682 +       u32 set, clr;
6683 +
6684 +       /* FIXME: should check count by querying the hardware capability */
6685 +       if (pattern_count >= MAX_NUM_PATTERN)
6686 +               return;
6687 +
6688 +       REG_SET_BIT(ah, AR_WOW_PATTERN, BIT(pattern_count));
6689 +
6690 +       /* set the registers for pattern */
6691 +       for (i = 0; i < MAX_PATTERN_SIZE; i += 4) {
6692 +               memcpy(&pattern_val, user_pattern, 4);
6693 +               REG_WRITE(ah, (AR_WOW_TB_PATTERN(pattern_count) + i),
6694 +                         pattern_val);
6695 +               user_pattern += 4;
6696 +       }
6697 +
6698 +       /* set the registers for mask */
6699 +       for (i = 0; i < MAX_PATTERN_MASK_SIZE; i += 4) {
6700 +               memcpy(&mask_val, user_mask, 4);
6701 +               REG_WRITE(ah, (AR_WOW_TB_MASK(pattern_count) + i), mask_val);
6702 +               user_mask += 4;
6703 +       }
6704 +
6705 +       /* set the pattern length to be matched
6706 +        *
6707 +        * AR_WOW_LENGTH1_REG1
6708 +        * bit 31:24 pattern 0 length
6709 +        * bit 23:16 pattern 1 length
6710 +        * bit 15:8 pattern 2 length
6711 +        * bit 7:0 pattern 3 length
6712 +        *
6713 +        * AR_WOW_LENGTH1_REG2
6714 +        * bit 31:24 pattern 4 length
6715 +        * bit 23:16 pattern 5 length
6716 +        * bit 15:8 pattern 6 length
6717 +        * bit 7:0 pattern 7 length
6718 +        *
6719 +        * the below logic writes out the new
6720 +        * pattern length for the corresponding
6721 +        * pattern_count, while masking out the
6722 +        * other fields
6723 +        */
6724 +
6725 +       ah->wow_event_mask |= BIT(pattern_count + AR_WOW_PAT_FOUND_SHIFT);
6726 +
6727 +       if (pattern_count < 4) {
6728 +               /* Pattern 0-3 uses AR_WOW_LENGTH1 register */
6729 +               set = (pattern_len & AR_WOW_LENGTH_MAX) <<
6730 +                      AR_WOW_LEN1_SHIFT(pattern_count);
6731 +               clr = AR_WOW_LENGTH1_MASK(pattern_count);
6732 +               REG_RMW(ah, AR_WOW_LENGTH1, set, clr);
6733 +       } else {
6734 +               /* Pattern 4-7 uses AR_WOW_LENGTH2 register */
6735 +               set = (pattern_len & AR_WOW_LENGTH_MAX) <<
6736 +                      AR_WOW_LEN2_SHIFT(pattern_count);
6737 +               clr = AR_WOW_LENGTH2_MASK(pattern_count);
6738 +               REG_RMW(ah, AR_WOW_LENGTH2, set, clr);
6739 +       }
6740 +
6741 +}
6742 +EXPORT_SYMBOL(ath9k_hw_wow_apply_pattern);
6743 +
6744 +u32 ath9k_hw_wow_wakeup(struct ath_hw *ah)
6745 +{
6746 +       u32 wow_status = 0;
6747 +       u32 val = 0, rval;
6748 +
6749 +       /*
6750 +        * read the WoW status register to know
6751 +        * the wakeup reason
6752 +        */
6753 +       rval = REG_READ(ah, AR_WOW_PATTERN);
6754 +       val = AR_WOW_STATUS(rval);
6755 +
6756 +       /*
6757 +        * mask only the WoW events that we have enabled. Sometimes
6758 +        * we have spurious WoW events from the AR_WOW_PATTERN
6759 +        * register. This mask will clean it up.
6760 +        */
6761 +
6762 +       val &= ah->wow_event_mask;
6763 +
6764 +       if (val) {
6765 +               if (val & AR_WOW_MAGIC_PAT_FOUND)
6766 +                       wow_status |= AH_WOW_MAGIC_PATTERN_EN;
6767 +               if (AR_WOW_PATTERN_FOUND(val))
6768 +                       wow_status |= AH_WOW_USER_PATTERN_EN;
6769 +               if (val & AR_WOW_KEEP_ALIVE_FAIL)
6770 +                       wow_status |= AH_WOW_LINK_CHANGE;
6771 +               if (val & AR_WOW_BEACON_FAIL)
6772 +                       wow_status |= AH_WOW_BEACON_MISS;
6773 +       }
6774 +
6775 +       /*
6776 +        * set and clear WOW_PME_CLEAR registers for the chip to
6777 +        * generate next wow signal.
6778 +        * disable D3 before accessing other registers ?
6779 +        */
6780 +
6781 +       /* do we need to check the bit value 0x01000000 (7-10) ?? */
6782 +       REG_RMW(ah, AR_PCIE_PM_CTRL, AR_PMCTRL_WOW_PME_CLR,
6783 +               AR_PMCTRL_PWR_STATE_D1D3);
6784 +
6785 +       /*
6786 +        * clear all events
6787 +        */
6788 +       REG_WRITE(ah, AR_WOW_PATTERN,
6789 +                 AR_WOW_CLEAR_EVENTS(REG_READ(ah, AR_WOW_PATTERN)));
6790 +
6791 +       /*
6792 +        * restore the beacon threshold to init value
6793 +        */
6794 +       REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
6795 +
6796 +       /*
6797 +        * Restore the way the PCI-E reset, Power-On-Reset, external
6798 +        * PCIE_POR_SHORT pins are tied to its original value.
6799 +        * Previously just before WoW sleep, we untie the PCI-E
6800 +        * reset to our Chip's Power On Reset so that any PCI-E
6801 +        * reset from the bus will not reset our chip
6802 +        */
6803 +       if (ah->is_pciexpress)
6804 +               ath9k_hw_configpcipowersave(ah, false);
6805 +
6806 +       ah->wow_event_mask = 0;
6807 +
6808 +       return wow_status;
6809 +}
6810 +EXPORT_SYMBOL(ath9k_hw_wow_wakeup);
6811 +
6812 +void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable)
6813 +{
6814 +       u32 wow_event_mask;
6815 +       u32 set, clr;
6816 +
6817 +       /*
6818 +        * wow_event_mask is a mask to the AR_WOW_PATTERN register to
6819 +        * indicate which WoW events we have enabled. The WoW events
6820 +        * are from the 'pattern_enable' in this function and
6821 +        * 'pattern_count' of ath9k_hw_wow_apply_pattern()
6822 +        */
6823 +       wow_event_mask = ah->wow_event_mask;
6824 +
6825 +       /*
6826 +        * Untie Power-on-Reset from the PCI-E-Reset. When we are in
6827 +        * WOW sleep, we do want the Reset from the PCI-E to disturb
6828 +        * our hw state
6829 +        */
6830 +       if (ah->is_pciexpress) {
6831 +               /*
6832 +                * we need to untie the internal POR (power-on-reset)
6833 +                * to the external PCI-E reset. We also need to tie
6834 +                * the PCI-E Phy reset to the PCI-E reset.
6835 +                */
6836 +               set = AR_WA_RESET_EN | AR_WA_POR_SHORT;
6837 +               clr = AR_WA_UNTIE_RESET_EN | AR_WA_D3_L1_DISABLE;
6838 +               REG_RMW(ah, AR_WA, set, clr);
6839 +       }
6840 +
6841 +       /*
6842 +        * set the power states appropriately and enable PME
6843 +        */
6844 +       set = AR_PMCTRL_HOST_PME_EN | AR_PMCTRL_PWR_PM_CTRL_ENA |
6845 +             AR_PMCTRL_AUX_PWR_DET | AR_PMCTRL_WOW_PME_CLR;
6846 +
6847 +       /*
6848 +        * set and clear WOW_PME_CLEAR registers for the chip
6849 +        * to generate next wow signal.
6850 +        */
6851 +       REG_SET_BIT(ah, AR_PCIE_PM_CTRL, set);
6852 +       clr = AR_PMCTRL_WOW_PME_CLR;
6853 +       REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, clr);
6854 +
6855 +       /*
6856 +        * Setup for:
6857 +        *      - beacon misses
6858 +        *      - magic pattern
6859 +        *      - keep alive timeout
6860 +        *      - pattern matching
6861 +        */
6862 +
6863 +       /*
6864 +        * Program default values for pattern backoff, aifs/slot/KAL count,
6865 +        * beacon miss timeout, KAL timeout, etc.
6866 +        */
6867 +       set = AR_WOW_BACK_OFF_SHIFT(AR_WOW_PAT_BACKOFF);
6868 +       REG_SET_BIT(ah, AR_WOW_PATTERN, set);
6869 +
6870 +       set = AR_WOW_AIFS_CNT(AR_WOW_CNT_AIFS_CNT) |
6871 +             AR_WOW_SLOT_CNT(AR_WOW_CNT_SLOT_CNT) |
6872 +             AR_WOW_KEEP_ALIVE_CNT(AR_WOW_CNT_KA_CNT);
6873 +       REG_SET_BIT(ah, AR_WOW_COUNT, set);
6874 +
6875 +       if (pattern_enable & AH_WOW_BEACON_MISS)
6876 +               set = AR_WOW_BEACON_TIMO;
6877 +       /* We are not using beacon miss, program a large value */
6878 +       else
6879 +               set = AR_WOW_BEACON_TIMO_MAX;
6880 +
6881 +       REG_WRITE(ah, AR_WOW_BCN_TIMO, set);
6882 +
6883 +       /*
6884 +        * Keep alive timo in ms except AR9280
6885 +        */
6886 +       if (!pattern_enable)
6887 +               set = AR_WOW_KEEP_ALIVE_NEVER;
6888 +       else
6889 +               set = KAL_TIMEOUT * 32;
6890 +
6891 +       REG_WRITE(ah, AR_WOW_KEEP_ALIVE_TIMO, set);
6892 +
6893 +       /*
6894 +        * Keep alive delay in us. based on 'power on clock',
6895 +        * therefore in usec
6896 +        */
6897 +       set = KAL_DELAY * 1000;
6898 +       REG_WRITE(ah, AR_WOW_KEEP_ALIVE_DELAY, set);
6899 +
6900 +       /*
6901 +        * Create keep alive pattern to respond to beacons
6902 +        */
6903 +       ath9k_wow_create_keep_alive_pattern(ah);
6904 +
6905 +       /*
6906 +        * Configure MAC WoW Registers
6907 +        */
6908 +       set = 0;
6909 +       /* Send keep alive timeouts anyway */
6910 +       clr = AR_WOW_KEEP_ALIVE_AUTO_DIS;
6911 +
6912 +       if (pattern_enable & AH_WOW_LINK_CHANGE)
6913 +               wow_event_mask |= AR_WOW_KEEP_ALIVE_FAIL;
6914 +       else
6915 +               set = AR_WOW_KEEP_ALIVE_FAIL_DIS;
6916 +
6917 +       set = AR_WOW_KEEP_ALIVE_FAIL_DIS;
6918 +       REG_RMW(ah, AR_WOW_KEEP_ALIVE, set, clr);
6919 +
6920 +       /*
6921 +        * we are relying on a bmiss failure. ensure we have
6922 +        * enough threshold to prevent false positives
6923 +        */
6924 +       REG_RMW_FIELD(ah, AR_RSSI_THR, AR_RSSI_THR_BM_THR,
6925 +                     AR_WOW_BMISSTHRESHOLD);
6926 +
6927 +       set = 0;
6928 +       clr = 0;
6929 +
6930 +       if (pattern_enable & AH_WOW_BEACON_MISS) {
6931 +               set = AR_WOW_BEACON_FAIL_EN;
6932 +               wow_event_mask |= AR_WOW_BEACON_FAIL;
6933 +       } else {
6934 +               clr = AR_WOW_BEACON_FAIL_EN;
6935 +       }
6936 +
6937 +       REG_RMW(ah, AR_WOW_BCN_EN, set, clr);
6938 +
6939 +       set = 0;
6940 +       clr = 0;
6941 +       /*
6942 +        * Enable the magic packet registers
6943 +        */
6944 +       if (pattern_enable & AH_WOW_MAGIC_PATTERN_EN) {
6945 +               set = AR_WOW_MAGIC_EN;
6946 +               wow_event_mask |= AR_WOW_MAGIC_PAT_FOUND;
6947 +       } else {
6948 +               clr = AR_WOW_MAGIC_EN;
6949 +       }
6950 +       set |= AR_WOW_MAC_INTR_EN;
6951 +       REG_RMW(ah, AR_WOW_PATTERN, set, clr);
6952 +
6953 +       REG_WRITE(ah, AR_WOW_PATTERN_MATCH_LT_256B,
6954 +                 AR_WOW_PATTERN_SUPPORTED);
6955 +
6956 +       /*
6957 +        * Set the power states appropriately and enable PME
6958 +        */
6959 +       clr = 0;
6960 +       set = AR_PMCTRL_PWR_STATE_D1D3 | AR_PMCTRL_HOST_PME_EN |
6961 +             AR_PMCTRL_PWR_PM_CTRL_ENA;
6962 +
6963 +       clr = AR_PCIE_PM_CTRL_ENA;
6964 +       REG_RMW(ah, AR_PCIE_PM_CTRL, set, clr);
6965 +
6966 +       /*
6967 +        * this is needed to prevent the chip waking up
6968 +        * the host within 3-4 seconds with certain
6969 +        * platform/BIOS. The fix is to enable
6970 +        * D1 & D3 to match original definition and
6971 +        * also match the OTP value. Anyway this
6972 +        * is more related to SW WOW.
6973 +        */
6974 +       clr = AR_PMCTRL_PWR_STATE_D1D3;
6975 +       REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, clr);
6976 +
6977 +       set = AR_PMCTRL_PWR_STATE_D1D3_REAL;
6978 +       REG_SET_BIT(ah, AR_PCIE_PM_CTRL, set);
6979 +
6980 +       REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
6981 +
6982 +       /* to bring down WOW power low margin */
6983 +       set = BIT(13);
6984 +       REG_SET_BIT(ah, AR_PCIE_PHY_REG3, set);
6985 +       /* HW WoW */
6986 +       clr = BIT(5);
6987 +       REG_CLR_BIT(ah, AR_PCU_MISC_MODE3, clr);
6988 +
6989 +       ath9k_hw_set_powermode_wow_sleep(ah);
6990 +       ah->wow_event_mask = wow_event_mask;
6991 +}
6992 +EXPORT_SYMBOL(ath9k_hw_wow_enable);
6993 --- /dev/null
6994 +++ b/drivers/net/wireless/ath/ath9k/tx99.c
6995 @@ -0,0 +1,263 @@
6996 +/*
6997 + * Copyright (c) 2013 Qualcomm Atheros, Inc.
6998 + *
6999 + * Permission to use, copy, modify, and/or distribute this software for any
7000 + * purpose with or without fee is hereby granted, provided that the above
7001 + * copyright notice and this permission notice appear in all copies.
7002 + *
7003 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
7004 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
7005 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
7006 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
7007 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
7008 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
7009 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
7010 + */
7011 +
7012 +#include "ath9k.h"
7013 +
7014 +static void ath9k_tx99_stop(struct ath_softc *sc)
7015 +{
7016 +       struct ath_hw *ah = sc->sc_ah;
7017 +       struct ath_common *common = ath9k_hw_common(ah);
7018 +
7019 +       ath_drain_all_txq(sc);
7020 +       ath_startrecv(sc);
7021 +
7022 +       ath9k_hw_set_interrupts(ah);
7023 +       ath9k_hw_enable_interrupts(ah);
7024 +
7025 +       ieee80211_wake_queues(sc->hw);
7026 +
7027 +       kfree_skb(sc->tx99_skb);
7028 +       sc->tx99_skb = NULL;
7029 +       sc->tx99_state = false;
7030 +
7031 +       ath9k_hw_tx99_stop(sc->sc_ah);
7032 +       ath_dbg(common, XMIT, "TX99 stopped\n");
7033 +}
7034 +
7035 +static struct sk_buff *ath9k_build_tx99_skb(struct ath_softc *sc)
7036 +{
7037 +       static u8 PN9Data[] = {0xff, 0x87, 0xb8, 0x59, 0xb7, 0xa1, 0xcc, 0x24,
7038 +                              0x57, 0x5e, 0x4b, 0x9c, 0x0e, 0xe9, 0xea, 0x50,
7039 +                              0x2a, 0xbe, 0xb4, 0x1b, 0xb6, 0xb0, 0x5d, 0xf1,
7040 +                              0xe6, 0x9a, 0xe3, 0x45, 0xfd, 0x2c, 0x53, 0x18,
7041 +                              0x0c, 0xca, 0xc9, 0xfb, 0x49, 0x37, 0xe5, 0xa8,
7042 +                              0x51, 0x3b, 0x2f, 0x61, 0xaa, 0x72, 0x18, 0x84,
7043 +                              0x02, 0x23, 0x23, 0xab, 0x63, 0x89, 0x51, 0xb3,
7044 +                              0xe7, 0x8b, 0x72, 0x90, 0x4c, 0xe8, 0xfb, 0xc0};
7045 +       u32 len = 1200;
7046 +       struct ieee80211_hw *hw = sc->hw;
7047 +       struct ieee80211_hdr *hdr;
7048 +       struct ieee80211_tx_info *tx_info;
7049 +       struct sk_buff *skb;
7050 +
7051 +       skb = alloc_skb(len, GFP_KERNEL);
7052 +       if (!skb)
7053 +               return NULL;
7054 +
7055 +       skb_put(skb, len);
7056 +
7057 +       memset(skb->data, 0, len);
7058 +
7059 +       hdr = (struct ieee80211_hdr *)skb->data;
7060 +       hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_DATA);
7061 +       hdr->duration_id = 0;
7062 +
7063 +       memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN);
7064 +       memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN);
7065 +       memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);
7066 +
7067 +       hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
7068 +
7069 +       tx_info = IEEE80211_SKB_CB(skb);
7070 +       memset(tx_info, 0, sizeof(*tx_info));
7071 +       tx_info->band = hw->conf.chandef.chan->band;
7072 +       tx_info->flags = IEEE80211_TX_CTL_NO_ACK;
7073 +       tx_info->control.vif = sc->tx99_vif;
7074 +
7075 +       memcpy(skb->data + sizeof(*hdr), PN9Data, sizeof(PN9Data));
7076 +
7077 +       return skb;
7078 +}
7079 +
7080 +static void ath9k_tx99_deinit(struct ath_softc *sc)
7081 +{
7082 +       ath_reset(sc);
7083 +
7084 +       ath9k_ps_wakeup(sc);
7085 +       ath9k_tx99_stop(sc);
7086 +       ath9k_ps_restore(sc);
7087 +}
7088 +
7089 +static int ath9k_tx99_init(struct ath_softc *sc)
7090 +{
7091 +       struct ieee80211_hw *hw = sc->hw;
7092 +       struct ath_hw *ah = sc->sc_ah;
7093 +       struct ath_common *common = ath9k_hw_common(ah);
7094 +       struct ath_tx_control txctl;
7095 +       int r;
7096 +
7097 +       if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
7098 +               ath_err(common,
7099 +                       "driver is in invalid state unable to use TX99");
7100 +               return -EINVAL;
7101 +       }
7102 +
7103 +       sc->tx99_skb = ath9k_build_tx99_skb(sc);
7104 +       if (!sc->tx99_skb)
7105 +               return -ENOMEM;
7106 +
7107 +       memset(&txctl, 0, sizeof(txctl));
7108 +       txctl.txq = sc->tx.txq_map[IEEE80211_AC_VO];
7109 +
7110 +       ath_reset(sc);
7111 +
7112 +       ath9k_ps_wakeup(sc);
7113 +
7114 +       ath9k_hw_disable_interrupts(ah);
7115 +       atomic_set(&ah->intr_ref_cnt, -1);
7116 +       ath_drain_all_txq(sc);
7117 +       ath_stoprecv(sc);
7118 +
7119 +       sc->tx99_state = true;
7120 +
7121 +       ieee80211_stop_queues(hw);
7122 +
7123 +       if (sc->tx99_power == MAX_RATE_POWER + 1)
7124 +               sc->tx99_power = MAX_RATE_POWER;
7125 +
7126 +       ath9k_hw_tx99_set_txpower(ah, sc->tx99_power);
7127 +       r = ath9k_tx99_send(sc, sc->tx99_skb, &txctl);
7128 +       if (r) {
7129 +               ath_dbg(common, XMIT, "Failed to xmit TX99 skb\n");
7130 +               return r;
7131 +       }
7132 +
7133 +       ath_dbg(common, XMIT, "TX99 xmit started using %d ( %ddBm)\n",
7134 +               sc->tx99_power,
7135 +               sc->tx99_power / 2);
7136 +
7137 +       /* We leave the harware awake as it will be chugging on */
7138 +
7139 +       return 0;
7140 +}
7141 +
7142 +static ssize_t read_file_tx99(struct file *file, char __user *user_buf,
7143 +                             size_t count, loff_t *ppos)
7144 +{
7145 +       struct ath_softc *sc = file->private_data;
7146 +       char buf[3];
7147 +       unsigned int len;
7148 +
7149 +       len = sprintf(buf, "%d\n", sc->tx99_state);
7150 +       return simple_read_from_buffer(user_buf, count, ppos, buf, len);
7151 +}
7152 +
7153 +static ssize_t write_file_tx99(struct file *file, const char __user *user_buf,
7154 +                              size_t count, loff_t *ppos)
7155 +{
7156 +       struct ath_softc *sc = file->private_data;
7157 +       struct ath_common *common = ath9k_hw_common(sc->sc_ah);
7158 +       char buf[32];
7159 +       bool start;
7160 +       ssize_t len;
7161 +       int r;
7162 +
7163 +       if (sc->nvifs > 1)
7164 +               return -EOPNOTSUPP;
7165 +
7166 +       len = min(count, sizeof(buf) - 1);
7167 +       if (copy_from_user(buf, user_buf, len))
7168 +               return -EFAULT;
7169 +
7170 +       if (strtobool(buf, &start))
7171 +               return -EINVAL;
7172 +
7173 +       if (start == sc->tx99_state) {
7174 +               if (!start)
7175 +                       return count;
7176 +               ath_dbg(common, XMIT, "Resetting TX99\n");
7177 +               ath9k_tx99_deinit(sc);
7178 +       }
7179 +
7180 +       if (!start) {
7181 +               ath9k_tx99_deinit(sc);
7182 +               return count;
7183 +       }
7184 +
7185 +       r = ath9k_tx99_init(sc);
7186 +       if (r)
7187 +               return r;
7188 +
7189 +       return count;
7190 +}
7191 +
7192 +static const struct file_operations fops_tx99 = {
7193 +       .read = read_file_tx99,
7194 +       .write = write_file_tx99,
7195 +       .open = simple_open,
7196 +       .owner = THIS_MODULE,
7197 +       .llseek = default_llseek,
7198 +};
7199 +
7200 +static ssize_t read_file_tx99_power(struct file *file,
7201 +                                   char __user *user_buf,
7202 +                                   size_t count, loff_t *ppos)
7203 +{
7204 +       struct ath_softc *sc = file->private_data;
7205 +       char buf[32];
7206 +       unsigned int len;
7207 +
7208 +       len = sprintf(buf, "%d (%d dBm)\n",
7209 +                     sc->tx99_power,
7210 +                     sc->tx99_power / 2);
7211 +
7212 +       return simple_read_from_buffer(user_buf, count, ppos, buf, len);
7213 +}
7214 +
7215 +static ssize_t write_file_tx99_power(struct file *file,
7216 +                                    const char __user *user_buf,
7217 +                                    size_t count, loff_t *ppos)
7218 +{
7219 +       struct ath_softc *sc = file->private_data;
7220 +       int r;
7221 +       u8 tx_power;
7222 +
7223 +       r = kstrtou8_from_user(user_buf, count, 0, &tx_power);
7224 +       if (r)
7225 +               return r;
7226 +
7227 +       if (tx_power > MAX_RATE_POWER)
7228 +               return -EINVAL;
7229 +
7230 +       sc->tx99_power = tx_power;
7231 +
7232 +       ath9k_ps_wakeup(sc);
7233 +       ath9k_hw_tx99_set_txpower(sc->sc_ah, sc->tx99_power);
7234 +       ath9k_ps_restore(sc);
7235 +
7236 +       return count;
7237 +}
7238 +
7239 +static const struct file_operations fops_tx99_power = {
7240 +       .read = read_file_tx99_power,
7241 +       .write = write_file_tx99_power,
7242 +       .open = simple_open,
7243 +       .owner = THIS_MODULE,
7244 +       .llseek = default_llseek,
7245 +};
7246 +
7247 +void ath9k_tx99_init_debug(struct ath_softc *sc)
7248 +{
7249 +       if (!AR_SREV_9300_20_OR_LATER(sc->sc_ah))
7250 +               return;
7251 +
7252 +       debugfs_create_file("tx99", S_IRUSR | S_IWUSR,
7253 +                           sc->debug.debugfs_phy, sc,
7254 +                           &fops_tx99);
7255 +       debugfs_create_file("tx99_power", S_IRUSR | S_IWUSR,
7256 +                           sc->debug.debugfs_phy, sc,
7257 +                           &fops_tx99_power);
7258 +}
7259 --- a/drivers/net/wireless/ath/ath9k/dfs_debug.c
7260 +++ b/drivers/net/wireless/ath/ath9k/dfs_debug.c
7261 @@ -44,14 +44,20 @@ static ssize_t read_file_dfs(struct file
7262         if (buf == NULL)
7263                 return -ENOMEM;
7264
7265 -       if (sc->dfs_detector)
7266 -               dfs_pool_stats = sc->dfs_detector->get_stats(sc->dfs_detector);
7267 -
7268         len += scnprintf(buf + len, size - len, "DFS support for "
7269                          "macVersion = 0x%x, macRev = 0x%x: %s\n",
7270                          hw_ver->macVersion, hw_ver->macRev,
7271                          (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_DFS) ?
7272                                         "enabled" : "disabled");
7273 +
7274 +       if (!sc->dfs_detector) {
7275 +               len += scnprintf(buf + len, size - len,
7276 +                               "DFS detector not enabled\n");
7277 +               goto exit;
7278 +       }
7279 +
7280 +       dfs_pool_stats = sc->dfs_detector->get_stats(sc->dfs_detector);
7281 +
7282         len += scnprintf(buf + len, size - len, "Pulse detector statistics:\n");
7283         ATH9K_DFS_STAT("pulse events reported   ", pulses_total);
7284         ATH9K_DFS_STAT("invalid pulse events    ", pulses_no_dfs);
7285 @@ -76,6 +82,7 @@ static ssize_t read_file_dfs(struct file
7286         ATH9K_DFS_POOL_STAT("Seqs. alloc error       ", pseq_alloc_error);
7287         ATH9K_DFS_POOL_STAT("Seqs. in use            ", pseq_used);
7288
7289 +exit:
7290         if (len > size)
7291                 len = size;
7292
7293 --- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
7294 +++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
7295 @@ -641,11 +641,12 @@ static void ar9003_hw_override_ini(struc
7296                 else
7297                         ah->enabled_cals &= ~TX_IQ_CAL;
7298
7299 -               if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE)
7300 -                       ah->enabled_cals |= TX_CL_CAL;
7301 -               else
7302 -                       ah->enabled_cals &= ~TX_CL_CAL;
7303         }
7304 +
7305 +       if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE)
7306 +               ah->enabled_cals |= TX_CL_CAL;
7307 +       else
7308 +               ah->enabled_cals &= ~TX_CL_CAL;
7309  }
7310
7311  static void ar9003_hw_prog_ini(struct ath_hw *ah,
7312 @@ -701,6 +702,54 @@ static int ar9550_hw_get_modes_txgain_in
7313         return ret;
7314  }
7315
7316 +static void ar9003_doubler_fix(struct ath_hw *ah)
7317 +{
7318 +       if (AR_SREV_9300(ah) || AR_SREV_9580(ah) || AR_SREV_9550(ah)) {
7319 +               REG_RMW(ah, AR_PHY_65NM_CH0_RXTX2,
7320 +                       1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
7321 +                       1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0);
7322 +               REG_RMW(ah, AR_PHY_65NM_CH1_RXTX2,
7323 +                       1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
7324 +                       1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0);
7325 +               REG_RMW(ah, AR_PHY_65NM_CH2_RXTX2,
7326 +                       1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
7327 +                       1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0);
7328 +
7329 +               udelay(200);
7330 +
7331 +               REG_CLR_BIT(ah, AR_PHY_65NM_CH0_RXTX2,
7332 +                           AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK);
7333 +               REG_CLR_BIT(ah, AR_PHY_65NM_CH1_RXTX2,
7334 +                           AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK);
7335 +               REG_CLR_BIT(ah, AR_PHY_65NM_CH2_RXTX2,
7336 +                           AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK);
7337 +
7338 +               udelay(1);
7339 +
7340 +               REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX2,
7341 +                             AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1);
7342 +               REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX2,
7343 +                             AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1);
7344 +               REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX2,
7345 +                             AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1);
7346 +
7347 +               udelay(200);
7348 +
7349 +               REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH12,
7350 +                             AR_PHY_65NM_CH0_SYNTH12_VREFMUL3, 0xf);
7351 +
7352 +               REG_RMW(ah, AR_PHY_65NM_CH0_RXTX2, 0,
7353 +                       1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
7354 +                       1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S);
7355 +               REG_RMW(ah, AR_PHY_65NM_CH1_RXTX2, 0,
7356 +                       1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
7357 +                       1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S);
7358 +               REG_RMW(ah, AR_PHY_65NM_CH2_RXTX2, 0,
7359 +                       1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
7360 +                       1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S);
7361 +       }
7362 +}
7363 +
7364  static int ar9003_hw_process_ini(struct ath_hw *ah,
7365                                  struct ath9k_channel *chan)
7366  {
7367 @@ -726,6 +775,8 @@ static int ar9003_hw_process_ini(struct
7368                                            modesIndex);
7369         }
7370
7371 +       ar9003_doubler_fix(ah);
7372 +
7373         /*
7374          * RXGAIN initvals.
7375          */
7376 @@ -1281,6 +1332,7 @@ static void ar9003_hw_ani_cache_ini_regs
7377  static void ar9003_hw_set_radar_params(struct ath_hw *ah,
7378                                        struct ath_hw_radar_conf *conf)
7379  {
7380 +       unsigned int regWrites = 0;
7381         u32 radar_0 = 0, radar_1 = 0;
7382
7383         if (!conf) {
7384 @@ -1307,6 +1359,11 @@ static void ar9003_hw_set_radar_params(s
7385                 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
7386         else
7387                 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
7388 +
7389 +       if (AR_SREV_9300(ah) || AR_SREV_9340(ah) || AR_SREV_9580(ah)) {
7390 +               REG_WRITE_ARRAY(&ah->ini_dfs,
7391 +                               IS_CHAN_HT40(ah->curchan) ? 2 : 1, regWrites);
7392 +       }
7393  }
7394
7395  static void ar9003_hw_set_radar_conf(struct ath_hw *ah)
7396 --- a/drivers/net/wireless/ath/ath9k/ar9003_phy.h
7397 +++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
7398 @@ -270,7 +270,7 @@
7399  #define AR_PHY_AGC              (AR_AGC_BASE + 0x14)
7400  #define AR_PHY_EXT_ATTEN_CTL_0  (AR_AGC_BASE + 0x18)
7401  #define AR_PHY_CCA_0            (AR_AGC_BASE + 0x1c)
7402 -#define AR_PHY_EXT_CCA0         (AR_AGC_BASE + 0x20)
7403 +#define AR_PHY_CCA_CTRL_0       (AR_AGC_BASE + 0x20)
7404  #define AR_PHY_RESTART          (AR_AGC_BASE + 0x24)
7405
7406  /*
7407 @@ -341,14 +341,15 @@
7408  #define AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ     -95
7409  #define AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ     -100
7410
7411 +#define AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ -95
7412 +#define AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ -100
7413 +
7414  #define AR_PHY_CCA_NOM_VAL_9462_2GHZ          -127
7415  #define AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ     -127
7416  #define AR_PHY_CCA_MAX_GOOD_VAL_9462_2GHZ     -60
7417 -#define AR_PHY_CCA_MAX_GOOD_VAL_9462_FCC_2GHZ -95
7418  #define AR_PHY_CCA_NOM_VAL_9462_5GHZ          -127
7419  #define AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ     -127
7420  #define AR_PHY_CCA_MAX_GOOD_VAL_9462_5GHZ     -60
7421 -#define AR_PHY_CCA_MAX_GOOD_VAL_9462_FCC_5GHZ -100
7422
7423  #define AR_PHY_CCA_NOM_VAL_9330_2GHZ          -118
7424
7425 @@ -397,6 +398,8 @@
7426  #define AR9280_PHY_CCA_THRESH62_S   12
7427  #define AR_PHY_EXT_CCA0_THRESH62    0x000000FF
7428  #define AR_PHY_EXT_CCA0_THRESH62_S  0
7429 +#define AR_PHY_EXT_CCA0_THRESH62_1    0x000001FF
7430 +#define AR_PHY_EXT_CCA0_THRESH62_1_S  0
7431  #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK          0x0000003F
7432  #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S        0
7433  #define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME           0x00001FC0
7434 @@ -656,13 +659,24 @@
7435  #define AR_PHY_SYNTH4_LONG_SHIFT_SELECT   ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x00000001 : 0x00000002)
7436  #define AR_PHY_SYNTH4_LONG_SHIFT_SELECT_S ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0 : 1)
7437  #define AR_PHY_65NM_CH0_SYNTH7      0x16098
7438 +#define AR_PHY_65NM_CH0_SYNTH12     0x160ac
7439  #define AR_PHY_65NM_CH0_BIAS1       0x160c0
7440  #define AR_PHY_65NM_CH0_BIAS2       0x160c4
7441  #define AR_PHY_65NM_CH0_BIAS4       0x160cc
7442 +#define AR_PHY_65NM_CH0_RXTX2       0x16104
7443 +#define AR_PHY_65NM_CH1_RXTX2       0x16504
7444 +#define AR_PHY_65NM_CH2_RXTX2       0x16904
7445  #define AR_PHY_65NM_CH0_RXTX4       0x1610c
7446  #define AR_PHY_65NM_CH1_RXTX4       0x1650c
7447  #define AR_PHY_65NM_CH2_RXTX4       0x1690c
7448
7449 +#define AR_PHY_65NM_CH0_SYNTH12_VREFMUL3           0x00780000
7450 +#define AR_PHY_65NM_CH0_SYNTH12_VREFMUL3_S         19
7451 +#define AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK         0x00000004
7452 +#define AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S       2
7453 +#define AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK        0x00000008
7454 +#define AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S      3
7455 +
7456  #define AR_CH0_TOP     (AR_SREV_9300(ah) ? 0x16288 : \
7457                          (((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x1628c : 0x16280)))
7458  #define AR_CH0_TOP_XPABIASLVL (AR_SREV_9550(ah) ? 0x3c0 : 0x300)
7459 --- a/drivers/net/wireless/rt2x00/rt2x00dev.c
7460 +++ b/drivers/net/wireless/rt2x00/rt2x00dev.c
7461 @@ -181,6 +181,7 @@ static void rt2x00lib_autowakeup(struct
7462  static void rt2x00lib_bc_buffer_iter(void *data, u8 *mac,
7463                                      struct ieee80211_vif *vif)
7464  {
7465 +       struct ieee80211_tx_control control = {};
7466         struct rt2x00_dev *rt2x00dev = data;
7467         struct sk_buff *skb;
7468
7469 @@ -195,7 +196,7 @@ static void rt2x00lib_bc_buffer_iter(voi
7470          */
7471         skb = ieee80211_get_buffered_bc(rt2x00dev->hw, vif);
7472         while (skb) {
7473 -               rt2x00mac_tx(rt2x00dev->hw, NULL, skb);
7474 +               rt2x00mac_tx(rt2x00dev->hw, &control, skb);
7475                 skb = ieee80211_get_buffered_bc(rt2x00dev->hw, vif);
7476         }
7477  }
7478 --- a/drivers/net/wireless/ath/ath9k/ar9003_calib.c
7479 +++ b/drivers/net/wireless/ath/ath9k/ar9003_calib.c
7480 @@ -898,7 +898,7 @@ static void ar9003_hw_tx_iq_cal_reload(s
7481
7482  static void ar9003_hw_manual_peak_cal(struct ath_hw *ah, u8 chain, bool is_2g)
7483  {
7484 -       int offset[8], total = 0, test;
7485 +       int offset[8] = {0}, total = 0, test;
7486         int agc_out, i;
7487
7488         REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_GAINSTAGES(chain),
7489 @@ -923,12 +923,18 @@ static void ar9003_hw_manual_peak_cal(st
7490                       AR_PHY_65NM_RXRF_AGC_AGC_ON_OVR, 0x1);
7491         REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
7492                       AR_PHY_65NM_RXRF_AGC_AGC_CAL_OVR, 0x1);
7493 -       if (is_2g)
7494 -               REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
7495 -                             AR_PHY_65NM_RXRF_AGC_AGC2G_DBDAC_OVR, 0x0);
7496 -       else
7497 +
7498 +       if (AR_SREV_9330_11(ah)) {
7499                 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
7500 -                             AR_PHY_65NM_RXRF_AGC_AGC5G_DBDAC_OVR, 0x0);
7501 +                             AR_PHY_65NM_RXRF_AGC_AGC2G_CALDAC_OVR, 0x0);
7502 +       } else {
7503 +               if (is_2g)
7504 +                       REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
7505 +                                     AR_PHY_65NM_RXRF_AGC_AGC2G_DBDAC_OVR, 0x0);
7506 +               else
7507 +                       REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
7508 +                                     AR_PHY_65NM_RXRF_AGC_AGC5G_DBDAC_OVR, 0x0);
7509 +       }
7510
7511         for (i = 6; i > 0; i--) {
7512                 offset[i] = BIT(i - 1);
7513 @@ -964,9 +970,9 @@ static void ar9003_hw_manual_peak_cal(st
7514                       AR_PHY_65NM_RXRF_AGC_AGC_CAL_OVR, 0);
7515  }
7516
7517 -static void ar9003_hw_do_manual_peak_cal(struct ath_hw *ah,
7518 -                                        struct ath9k_channel *chan,
7519 -                                        bool run_rtt_cal)
7520 +static void ar9003_hw_do_pcoem_manual_peak_cal(struct ath_hw *ah,
7521 +                                              struct ath9k_channel *chan,
7522 +                                              bool run_rtt_cal)
7523  {
7524         struct ath9k_hw_cal_data *caldata = ah->caldata;
7525         int i;
7526 @@ -1040,14 +1046,14 @@ static void ar9003_hw_cl_cal_post_proc(s
7527         }
7528  }
7529
7530 -static bool ar9003_hw_init_cal(struct ath_hw *ah,
7531 -                              struct ath9k_channel *chan)
7532 +static bool ar9003_hw_init_cal_pcoem(struct ath_hw *ah,
7533 +                                    struct ath9k_channel *chan)
7534  {
7535         struct ath_common *common = ath9k_hw_common(ah);
7536         struct ath9k_hw_cal_data *caldata = ah->caldata;
7537         bool txiqcal_done = false;
7538         bool is_reusable = true, status = true;
7539 -       bool run_rtt_cal = false, run_agc_cal, sep_iq_cal = false;
7540 +       bool run_rtt_cal = false, run_agc_cal;
7541         bool rtt = !!(ah->caps.hw_caps & ATH9K_HW_CAP_RTT);
7542         u32 rx_delay = 0;
7543         u32 agc_ctrl = 0, agc_supp_cals = AR_PHY_AGC_CONTROL_OFFSET_CAL |
7544 @@ -1119,22 +1125,12 @@ static bool ar9003_hw_init_cal(struct at
7545                         REG_CLR_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0,
7546                                     AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL);
7547                 txiqcal_done = run_agc_cal = true;
7548 -       } else if (caldata && !test_bit(TXIQCAL_DONE, &caldata->cal_flags)) {
7549 -               run_agc_cal = true;
7550 -               sep_iq_cal = true;
7551         }
7552
7553  skip_tx_iqcal:
7554         if (ath9k_hw_mci_is_enabled(ah) && IS_CHAN_2GHZ(chan) && run_agc_cal)
7555                 ar9003_mci_init_cal_req(ah, &is_reusable);
7556
7557 -       if (sep_iq_cal) {
7558 -               txiqcal_done = ar9003_hw_tx_iq_cal_run(ah);
7559 -               REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
7560 -               udelay(5);
7561 -               REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
7562 -       }
7563 -
7564         if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE) {
7565                 rx_delay = REG_READ(ah, AR_PHY_RX_DELAY);
7566                 /* Disable BB_active */
7567 @@ -1155,7 +1151,7 @@ skip_tx_iqcal:
7568                                        AR_PHY_AGC_CONTROL_CAL,
7569                                        0, AH_WAIT_TIMEOUT);
7570
7571 -               ar9003_hw_do_manual_peak_cal(ah, chan, run_rtt_cal);
7572 +               ar9003_hw_do_pcoem_manual_peak_cal(ah, chan, run_rtt_cal);
7573         }
7574
7575         if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE) {
7576 @@ -1228,13 +1224,112 @@ skip_tx_iqcal:
7577         return true;
7578  }
7579
7580 +static bool ar9003_hw_init_cal_soc(struct ath_hw *ah,
7581 +                                  struct ath9k_channel *chan)
7582 +{
7583 +       struct ath_common *common = ath9k_hw_common(ah);
7584 +       struct ath9k_hw_cal_data *caldata = ah->caldata;
7585 +       bool txiqcal_done = false;
7586 +       bool is_reusable = true, status = true;
7587 +       bool run_agc_cal = false, sep_iq_cal = false;
7588 +
7589 +       /* Use chip chainmask only for calibration */
7590 +       ar9003_hw_set_chain_masks(ah, ah->caps.rx_chainmask, ah->caps.tx_chainmask);
7591 +
7592 +       if (ah->enabled_cals & TX_CL_CAL) {
7593 +               REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
7594 +               run_agc_cal = true;
7595 +       }
7596 +
7597 +       if (IS_CHAN_HALF_RATE(chan) || IS_CHAN_QUARTER_RATE(chan))
7598 +               goto skip_tx_iqcal;
7599 +
7600 +       /* Do Tx IQ Calibration */
7601 +       REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_1,
7602 +                     AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT,
7603 +                     DELPT);
7604 +
7605 +       /*
7606 +        * For AR9485 or later chips, TxIQ cal runs as part of
7607 +        * AGC calibration. Specifically, AR9550 in SoC chips.
7608 +        */
7609 +       if (ah->enabled_cals & TX_IQ_ON_AGC_CAL) {
7610 +               txiqcal_done = true;
7611 +               run_agc_cal = true;
7612 +       } else {
7613 +               sep_iq_cal = true;
7614 +               run_agc_cal = true;
7615 +       }
7616 +
7617 +       /*
7618 +        * In the SoC family, this will run for AR9300, AR9331 and AR9340.
7619 +        */
7620 +       if (sep_iq_cal) {
7621 +               txiqcal_done = ar9003_hw_tx_iq_cal_run(ah);
7622 +               REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
7623 +               udelay(5);
7624 +               REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
7625 +       }
7626 +
7627 +skip_tx_iqcal:
7628 +       if (run_agc_cal || !(ah->ah_flags & AH_FASTCC)) {
7629 +               if (AR_SREV_9330_11(ah))
7630 +                       ar9003_hw_manual_peak_cal(ah, 0, IS_CHAN_2GHZ(chan));
7631 +
7632 +               /* Calibrate the AGC */
7633 +               REG_WRITE(ah, AR_PHY_AGC_CONTROL,
7634 +                         REG_READ(ah, AR_PHY_AGC_CONTROL) |
7635 +                         AR_PHY_AGC_CONTROL_CAL);
7636 +
7637 +               /* Poll for offset calibration complete */
7638 +               status = ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
7639 +                                      AR_PHY_AGC_CONTROL_CAL,
7640 +                                      0, AH_WAIT_TIMEOUT);
7641 +       }
7642 +
7643 +       if (!status) {
7644 +               ath_dbg(common, CALIBRATE,
7645 +                       "offset calibration failed to complete in %d ms; noisy environment?\n",
7646 +                       AH_WAIT_TIMEOUT / 1000);
7647 +               return false;
7648 +       }
7649 +
7650 +       if (txiqcal_done)
7651 +               ar9003_hw_tx_iq_cal_post_proc(ah, is_reusable);
7652 +
7653 +       /* Revert chainmask to runtime parameters */
7654 +       ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
7655 +
7656 +       /* Initialize list pointers */
7657 +       ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL;
7658 +
7659 +       INIT_CAL(&ah->iq_caldata);
7660 +       INSERT_CAL(ah, &ah->iq_caldata);
7661 +       ath_dbg(common, CALIBRATE, "enabling IQ Calibration\n");
7662 +
7663 +       /* Initialize current pointer to first element in list */
7664 +       ah->cal_list_curr = ah->cal_list;
7665 +
7666 +       if (ah->cal_list_curr)
7667 +               ath9k_hw_reset_calibration(ah, ah->cal_list_curr);
7668 +
7669 +       if (caldata)
7670 +               caldata->CalValid = 0;
7671 +
7672 +       return true;
7673 +}
7674 +
7675  void ar9003_hw_attach_calib_ops(struct ath_hw *ah)
7676  {
7677         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
7678         struct ath_hw_ops *ops = ath9k_hw_ops(ah);
7679
7680 +       if (AR_SREV_9485(ah) || AR_SREV_9462(ah) || AR_SREV_9565(ah))
7681 +               priv_ops->init_cal = ar9003_hw_init_cal_pcoem;
7682 +       else
7683 +               priv_ops->init_cal = ar9003_hw_init_cal_soc;
7684 +
7685         priv_ops->init_cal_settings = ar9003_hw_init_cal_settings;
7686 -       priv_ops->init_cal = ar9003_hw_init_cal;
7687         priv_ops->setup_calibration = ar9003_hw_setup_calibration;
7688
7689         ops->calibrate = ar9003_hw_calibrate;
7690 --- a/drivers/net/wireless/ath/ath9k/common.c
7691 +++ b/drivers/net/wireless/ath/ath9k/common.c
7692 @@ -98,10 +98,8 @@ struct ath9k_channel *ath9k_cmn_get_chan
7693  {
7694         struct ieee80211_channel *curchan = chandef->chan;
7695         struct ath9k_channel *channel;
7696 -       u8 chan_idx;
7697
7698 -       chan_idx = curchan->hw_value;
7699 -       channel = &ah->channels[chan_idx];
7700 +       channel = &ah->channels[curchan->hw_value];
7701         ath9k_cmn_update_ichannel(channel, chandef);
7702
7703         return channel;
7704 --- a/net/mac80211/rc80211_minstrel_ht.c
7705 +++ b/net/mac80211/rc80211_minstrel_ht.c
7706 @@ -226,7 +226,7 @@ minstrel_ht_calc_tp(struct minstrel_ht_s
7707                 nsecs = 1000 * mi->overhead / MINSTREL_TRUNC(mi->avg_ampdu_len);
7708
7709         nsecs += minstrel_mcs_groups[group].duration[rate];
7710 -       tp = 1000000 * ((mr->probability * 1000) / nsecs);
7711 +       tp = 1000000 * ((prob * 1000) / nsecs);
7712
7713         mr->cur_tp = MINSTREL_TRUNC(tp);
7714  }
7715 --- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
7716 +++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
7717 @@ -131,6 +131,7 @@ static const struct ar9300_eeprom ar9300
7718                 .thresh62 = 28,
7719                 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
7720                 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
7721 +               .switchcomspdt = 0,
7722                 .xlna_bias_strength = 0,
7723                 .futureModal = {
7724                         0, 0, 0, 0, 0, 0, 0,
7725 @@ -138,7 +139,7 @@ static const struct ar9300_eeprom ar9300
7726          },
7727         .base_ext1 = {
7728                 .ant_div_control = 0,
7729 -               .future = {0, 0, 0},
7730 +               .future = {0, 0},
7731                 .tempslopextension = {0, 0, 0, 0, 0, 0, 0, 0}
7732         },
7733         .calFreqPier2G = {
7734 @@ -333,6 +334,7 @@ static const struct ar9300_eeprom ar9300
7735                 .thresh62 = 28,
7736                 .papdRateMaskHt20 = LE32(0x0c80c080),
7737                 .papdRateMaskHt40 = LE32(0x0080c080),
7738 +               .switchcomspdt = 0,
7739                 .xlna_bias_strength = 0,
7740                 .futureModal = {
7741                         0, 0, 0, 0, 0, 0, 0,
7742 @@ -707,6 +709,7 @@ static const struct ar9300_eeprom ar9300
7743                 .thresh62 = 28,
7744                 .papdRateMaskHt20 = LE32(0x0c80c080),
7745                 .papdRateMaskHt40 = LE32(0x0080c080),
7746 +               .switchcomspdt = 0,
7747                 .xlna_bias_strength = 0,
7748                 .futureModal = {
7749                         0, 0, 0, 0, 0, 0, 0,
7750 @@ -714,7 +717,7 @@ static const struct ar9300_eeprom ar9300
7751          },
7752          .base_ext1 = {
7753                 .ant_div_control = 0,
7754 -               .future = {0, 0, 0},
7755 +               .future = {0, 0},
7756                 .tempslopextension = {0, 0, 0, 0, 0, 0, 0, 0}
7757          },
7758         .calFreqPier2G = {
7759 @@ -909,6 +912,7 @@ static const struct ar9300_eeprom ar9300
7760                 .thresh62 = 28,
7761                 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
7762                 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
7763 +               .switchcomspdt = 0,
7764                 .xlna_bias_strength = 0,
7765                 .futureModal = {
7766                         0, 0, 0, 0, 0, 0, 0,
7767 @@ -1284,6 +1288,7 @@ static const struct ar9300_eeprom ar9300
7768                 .thresh62 = 28,
7769                 .papdRateMaskHt20 = LE32(0x0c80c080),
7770                 .papdRateMaskHt40 = LE32(0x0080c080),
7771 +               .switchcomspdt = 0,
7772                 .xlna_bias_strength = 0,
7773                 .futureModal = {
7774                         0, 0, 0, 0, 0, 0, 0,
7775 @@ -1291,7 +1296,7 @@ static const struct ar9300_eeprom ar9300
7776         },
7777         .base_ext1 = {
7778                 .ant_div_control = 0,
7779 -               .future = {0, 0, 0},
7780 +               .future = {0, 0},
7781                 .tempslopextension = {0, 0, 0, 0, 0, 0, 0, 0}
7782         },
7783         .calFreqPier2G = {
7784 @@ -1486,6 +1491,7 @@ static const struct ar9300_eeprom ar9300
7785                 .thresh62 = 28,
7786                 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
7787                 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
7788 +               .switchcomspdt = 0,
7789                 .xlna_bias_strength = 0,
7790                 .futureModal = {
7791                         0, 0, 0, 0, 0, 0, 0,
7792 @@ -1861,6 +1867,7 @@ static const struct ar9300_eeprom ar9300
7793                 .thresh62 = 28,
7794                 .papdRateMaskHt20 = LE32(0x0c80c080),
7795                 .papdRateMaskHt40 = LE32(0x0080c080),
7796 +               .switchcomspdt = 0,
7797                 .xlna_bias_strength = 0,
7798                 .futureModal = {
7799                         0, 0, 0, 0, 0, 0, 0,
7800 @@ -1868,7 +1875,7 @@ static const struct ar9300_eeprom ar9300
7801         },
7802         .base_ext1 = {
7803                 .ant_div_control = 0,
7804 -               .future = {0, 0, 0},
7805 +               .future = {0, 0},
7806                 .tempslopextension = {0, 0, 0, 0, 0, 0, 0, 0}
7807         },
7808         .calFreqPier2G = {
7809 @@ -2063,6 +2070,7 @@ static const struct ar9300_eeprom ar9300
7810                 .thresh62 = 28,
7811                 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
7812                 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
7813 +               .switchcomspdt = 0,
7814                 .xlna_bias_strength = 0,
7815                 .futureModal = {
7816                         0, 0, 0, 0, 0, 0, 0,
7817 @@ -2437,6 +2445,7 @@ static const struct ar9300_eeprom ar9300
7818                 .thresh62 = 28,
7819                 .papdRateMaskHt20 = LE32(0x0c80C080),
7820                 .papdRateMaskHt40 = LE32(0x0080C080),
7821 +               .switchcomspdt = 0,
7822                 .xlna_bias_strength = 0,
7823                 .futureModal = {
7824                         0, 0, 0, 0, 0, 0, 0,
7825 @@ -2444,7 +2453,7 @@ static const struct ar9300_eeprom ar9300
7826          },
7827          .base_ext1 = {
7828                 .ant_div_control = 0,
7829 -               .future = {0, 0, 0},
7830 +               .future = {0, 0},
7831                 .tempslopextension = {0, 0, 0, 0, 0, 0, 0, 0}
7832          },
7833         .calFreqPier2G = {
7834 @@ -2639,6 +2648,7 @@ static const struct ar9300_eeprom ar9300
7835                 .thresh62 = 28,
7836                 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
7837                 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
7838 +               .switchcomspdt = 0,
7839                 .xlna_bias_strength = 0,
7840                 .futureModal = {
7841                         0, 0, 0, 0, 0, 0, 0,
7842 @@ -3965,7 +3975,7 @@ static void ar9003_hw_apply_tuning_caps(
7843         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
7844         u8 tuning_caps_param = eep->baseEepHeader.params_for_tuning_caps[0];
7845
7846 -       if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
7847 +       if (AR_SREV_9340(ah))
7848                 return;
7849
7850         if (eep->baseEepHeader.featureEnable & 0x40) {
7851 @@ -3984,18 +3994,20 @@ static void ar9003_hw_quick_drop_apply(s
7852         int quick_drop;
7853         s32 t[3], f[3] = {5180, 5500, 5785};
7854
7855 -       if (!(pBase->miscConfiguration & BIT(1)))
7856 +       if (!(pBase->miscConfiguration & BIT(4)))
7857                 return;
7858
7859 -       if (freq < 4000)
7860 -               quick_drop = eep->modalHeader2G.quick_drop;
7861 -       else {
7862 -               t[0] = eep->base_ext1.quick_drop_low;
7863 -               t[1] = eep->modalHeader5G.quick_drop;
7864 -               t[2] = eep->base_ext1.quick_drop_high;
7865 -               quick_drop = ar9003_hw_power_interpolate(freq, f, t, 3);
7866 +       if (AR_SREV_9300(ah) || AR_SREV_9580(ah) || AR_SREV_9340(ah)) {
7867 +               if (freq < 4000) {
7868 +                       quick_drop = eep->modalHeader2G.quick_drop;
7869 +               } else {
7870 +                       t[0] = eep->base_ext1.quick_drop_low;
7871 +                       t[1] = eep->modalHeader5G.quick_drop;
7872 +                       t[2] = eep->base_ext1.quick_drop_high;
7873 +                       quick_drop = ar9003_hw_power_interpolate(freq, f, t, 3);
7874 +               }
7875 +               REG_RMW_FIELD(ah, AR_PHY_AGC, AR_PHY_AGC_QUICK_DROP, quick_drop);
7876         }
7877 -       REG_RMW_FIELD(ah, AR_PHY_AGC, AR_PHY_AGC_QUICK_DROP, quick_drop);
7878  }
7879
7880  static void ar9003_hw_txend_to_xpa_off_apply(struct ath_hw *ah, bool is2ghz)
7881 @@ -4035,7 +4047,7 @@ static void ar9003_hw_xlna_bias_strength
7882         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
7883         u8 bias;
7884
7885 -       if (!(eep->baseEepHeader.featureEnable & 0x40))
7886 +       if (!(eep->baseEepHeader.miscConfiguration & 0x40))
7887                 return;
7888
7889         if (!AR_SREV_9300(ah))
7890 @@ -4109,6 +4121,37 @@ static void ar9003_hw_thermo_cal_apply(s
7891         }
7892  }
7893
7894 +static void ar9003_hw_apply_minccapwr_thresh(struct ath_hw *ah,
7895 +                                            bool is2ghz)
7896 +{
7897 +       struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
7898 +       const u_int32_t cca_ctrl[AR9300_MAX_CHAINS] = {
7899 +               AR_PHY_CCA_CTRL_0,
7900 +               AR_PHY_CCA_CTRL_1,
7901 +               AR_PHY_CCA_CTRL_2,
7902 +       };
7903 +       int chain;
7904 +       u32 val;
7905 +
7906 +       if (is2ghz) {
7907 +               if (!(eep->base_ext1.misc_enable & BIT(2)))
7908 +                       return;
7909 +       } else {
7910 +               if (!(eep->base_ext1.misc_enable & BIT(3)))
7911 +                       return;
7912 +       }
7913 +
7914 +       for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
7915 +               if (!(ah->caps.tx_chainmask & BIT(chain)))
7916 +                       continue;
7917 +
7918 +               val = ar9003_modal_header(ah, is2ghz)->noiseFloorThreshCh[chain];
7919 +               REG_RMW_FIELD(ah, cca_ctrl[chain],
7920 +                             AR_PHY_EXT_CCA0_THRESH62_1, val);
7921 +       }
7922 +
7923 +}
7924 +
7925  static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
7926                                              struct ath9k_channel *chan)
7927  {
7928 @@ -4120,9 +4163,10 @@ static void ath9k_hw_ar9300_set_board_va
7929         ar9003_hw_xlna_bias_strength_apply(ah, is2ghz);
7930         ar9003_hw_atten_apply(ah, chan);
7931         ar9003_hw_quick_drop_apply(ah, chan->channel);
7932 -       if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah) && !AR_SREV_9550(ah))
7933 +       if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah))
7934                 ar9003_hw_internal_regulator_apply(ah);
7935         ar9003_hw_apply_tuning_caps(ah);
7936 +       ar9003_hw_apply_minccapwr_thresh(ah, chan);
7937         ar9003_hw_txend_to_xpa_off_apply(ah, is2ghz);
7938         ar9003_hw_thermometer_apply(ah);
7939         ar9003_hw_thermo_cal_apply(ah);
7940 --- a/net/mac80211/ieee80211_i.h
7941 +++ b/net/mac80211/ieee80211_i.h
7942 @@ -735,6 +735,7 @@ struct ieee80211_sub_if_data {
7943         int csa_counter_offset_beacon;
7944         int csa_counter_offset_presp;
7945         bool csa_radar_required;
7946 +       struct cfg80211_chan_def csa_chandef;
7947
7948         /* used to reconfigure hardware SM PS */
7949         struct work_struct recalc_smps;
7950 @@ -811,6 +812,9 @@ static inline void sdata_unlock(struct i
7951         __release(&sdata->wdev.mtx);
7952  }
7953
7954 +#define sdata_dereference(p, sdata) \
7955 +       rcu_dereference_protected(p, lockdep_is_held(&sdata->wdev.mtx))
7956 +
7957  static inline void
7958  sdata_assert_lock(struct ieee80211_sub_if_data *sdata)
7959  {
7960 @@ -1098,7 +1102,6 @@ struct ieee80211_local {
7961         enum mac80211_scan_state next_scan_state;
7962         struct delayed_work scan_work;
7963         struct ieee80211_sub_if_data __rcu *scan_sdata;
7964 -       struct cfg80211_chan_def csa_chandef;
7965         /* For backward compatibility only -- do not use */
7966         struct cfg80211_chan_def _oper_chandef;
7967
7968 @@ -1236,6 +1239,7 @@ struct ieee80211_csa_ie {
7969         u8 mode;
7970         u8 count;
7971         u8 ttl;
7972 +       u16 pre_value;
7973  };
7974
7975  /* Parsed Information Elements */
7976 @@ -1738,7 +1742,6 @@ ieee80211_vif_change_bandwidth(struct ie
7977  /* NOTE: only use ieee80211_vif_change_channel() for channel switch */
7978  int __must_check
7979  ieee80211_vif_change_channel(struct ieee80211_sub_if_data *sdata,
7980 -                            const struct cfg80211_chan_def *chandef,
7981                              u32 *changed);
7982  void ieee80211_vif_release_channel(struct ieee80211_sub_if_data *sdata);
7983  void ieee80211_vif_vlan_copy_chanctx(struct ieee80211_sub_if_data *sdata);
7984 --- a/net/mac80211/chan.c
7985 +++ b/net/mac80211/chan.c
7986 @@ -411,12 +411,12 @@ int ieee80211_vif_use_channel(struct iee
7987  }
7988
7989  int ieee80211_vif_change_channel(struct ieee80211_sub_if_data *sdata,
7990 -                                const struct cfg80211_chan_def *chandef,
7991                                  u32 *changed)
7992  {
7993         struct ieee80211_local *local = sdata->local;
7994         struct ieee80211_chanctx_conf *conf;
7995         struct ieee80211_chanctx *ctx;
7996 +       const struct cfg80211_chan_def *chandef = &sdata->csa_chandef;
7997         int ret;
7998         u32 chanctx_changed = 0;
7999
8000 --- a/net/mac80211/ibss.c
8001 +++ b/net/mac80211/ibss.c
8002 @@ -534,7 +534,7 @@ int ieee80211_ibss_finish_csa(struct iee
8003         int err;
8004         u16 capability;
8005
8006 -       sdata_lock(sdata);
8007 +       sdata_assert_lock(sdata);
8008         /* update cfg80211 bss information with the new channel */
8009         if (!is_zero_ether_addr(ifibss->bssid)) {
8010                 capability = WLAN_CAPABILITY_IBSS;
8011 @@ -550,16 +550,15 @@ int ieee80211_ibss_finish_csa(struct iee
8012                                         capability);
8013                 /* XXX: should not really modify cfg80211 data */
8014                 if (cbss) {
8015 -                       cbss->channel = sdata->local->csa_chandef.chan;
8016 +                       cbss->channel = sdata->csa_chandef.chan;
8017                         cfg80211_put_bss(sdata->local->hw.wiphy, cbss);
8018                 }
8019         }
8020
8021 -       ifibss->chandef = sdata->local->csa_chandef;
8022 +       ifibss->chandef = sdata->csa_chandef;
8023
8024         /* generate the beacon */
8025         err = ieee80211_ibss_csa_beacon(sdata, NULL);
8026 -       sdata_unlock(sdata);
8027         if (err < 0)
8028                 return err;
8029
8030 @@ -922,7 +921,7 @@ ieee80211_ibss_process_chanswitch(struct
8031                                 IEEE80211_MAX_QUEUE_MAP,
8032                                 IEEE80211_QUEUE_STOP_REASON_CSA);
8033
8034 -       sdata->local->csa_chandef = params.chandef;
8035 +       sdata->csa_chandef = params.chandef;
8036         sdata->vif.csa_active = true;
8037
8038         ieee80211_bss_info_change_notify(sdata, err);
8039 --- a/net/mac80211/mesh.c
8040 +++ b/net/mac80211/mesh.c
8041 @@ -943,14 +943,19 @@ ieee80211_mesh_process_chnswitch(struct
8042                  params.chandef.chan->center_freq);
8043
8044         params.block_tx = csa_ie.mode & WLAN_EID_CHAN_SWITCH_PARAM_TX_RESTRICT;
8045 -       if (beacon)
8046 +       if (beacon) {
8047                 ifmsh->chsw_ttl = csa_ie.ttl - 1;
8048 -       else
8049 -               ifmsh->chsw_ttl = 0;
8050 +               if (ifmsh->pre_value >= csa_ie.pre_value)
8051 +                       return false;
8052 +               ifmsh->pre_value = csa_ie.pre_value;
8053 +       }
8054
8055 -       if (ifmsh->chsw_ttl > 0)
8056 +       if (ifmsh->chsw_ttl < ifmsh->mshcfg.dot11MeshTTL) {
8057                 if (ieee80211_mesh_csa_beacon(sdata, &params, false) < 0)
8058                         return false;
8059 +       } else {
8060 +               return false;
8061 +       }
8062
8063         sdata->csa_radar_required = params.radar_required;
8064
8065 @@ -959,7 +964,7 @@ ieee80211_mesh_process_chnswitch(struct
8066                                 IEEE80211_MAX_QUEUE_MAP,
8067                                 IEEE80211_QUEUE_STOP_REASON_CSA);
8068
8069 -       sdata->local->csa_chandef = params.chandef;
8070 +       sdata->csa_chandef = params.chandef;
8071         sdata->vif.csa_active = true;
8072
8073         ieee80211_bss_info_change_notify(sdata, err);
8074 @@ -1163,7 +1168,6 @@ static int mesh_fwd_csa_frame(struct iee
8075         offset_ttl = (len < 42) ? 7 : 10;
8076         *(pos + offset_ttl) -= 1;
8077         *(pos + offset_ttl + 1) &= ~WLAN_EID_CHAN_SWITCH_PARAM_INITIATOR;
8078 -       sdata->u.mesh.chsw_ttl = *(pos + offset_ttl);
8079
8080         memcpy(mgmt_fwd, mgmt, len);
8081         eth_broadcast_addr(mgmt_fwd->da);
8082 @@ -1182,7 +1186,7 @@ static void mesh_rx_csa_frame(struct iee
8083         u16 pre_value;
8084         bool fwd_csa = true;
8085         size_t baselen;
8086 -       u8 *pos, ttl;
8087 +       u8 *pos;
8088
8089         if (mgmt->u.action.u.measurement.action_code !=
8090             WLAN_ACTION_SPCT_CHL_SWITCH)
8091 @@ -1193,8 +1197,8 @@ static void mesh_rx_csa_frame(struct iee
8092                            u.action.u.chan_switch.variable);
8093         ieee802_11_parse_elems(pos, len - baselen, false, &elems);
8094
8095 -       ttl = elems.mesh_chansw_params_ie->mesh_ttl;
8096 -       if (!--ttl)
8097 +       ifmsh->chsw_ttl = elems.mesh_chansw_params_ie->mesh_ttl;
8098 +       if (!--ifmsh->chsw_ttl)
8099                 fwd_csa = false;
8100
8101         pre_value = le16_to_cpu(elems.mesh_chansw_params_ie->mesh_pre_value);
8102 --- a/net/mac80211/spectmgmt.c
8103 +++ b/net/mac80211/spectmgmt.c
8104 @@ -78,6 +78,8 @@ int ieee80211_parse_ch_switch_ie(struct
8105         if (elems->mesh_chansw_params_ie) {
8106                 csa_ie->ttl = elems->mesh_chansw_params_ie->mesh_ttl;
8107                 csa_ie->mode = elems->mesh_chansw_params_ie->mesh_flags;
8108 +               csa_ie->pre_value = le16_to_cpu(
8109 +                               elems->mesh_chansw_params_ie->mesh_pre_value);
8110         }
8111
8112         new_freq = ieee80211_channel_to_frequency(new_chan_no, new_band);
8113 --- a/drivers/net/wireless/ath/ath6kl/cfg80211.c
8114 +++ b/drivers/net/wireless/ath/ath6kl/cfg80211.c
8115 @@ -1109,7 +1109,9 @@ void ath6kl_cfg80211_ch_switch_notify(st
8116                                 (mode == WMI_11G_HT20) ?
8117                                         NL80211_CHAN_HT20 : NL80211_CHAN_NO_HT);
8118
8119 +       mutex_lock(vif->wdev->mtx);
8120         cfg80211_ch_switch_notify(vif->ndev, &chandef);
8121 +       mutex_unlock(vif->wdev->mtx);
8122  }
8123
8124  static int ath6kl_cfg80211_add_key(struct wiphy *wiphy, struct net_device *ndev,
8125 --- a/drivers/net/wireless/ath/ath9k/ar9462_2p1_initvals.h
8126 +++ b/drivers/net/wireless/ath/ath9k/ar9462_2p1_initvals.h
8127 @@ -20,6 +20,44 @@
8128
8129  /* AR9462 2.1 */
8130
8131 +#define ar9462_2p1_mac_postamble ar9462_2p0_mac_postamble
8132 +
8133 +#define ar9462_2p1_baseband_core ar9462_2p0_baseband_core
8134 +
8135 +#define ar9462_2p1_radio_core ar9462_2p0_radio_core
8136 +
8137 +#define ar9462_2p1_radio_postamble ar9462_2p0_radio_postamble
8138 +
8139 +#define ar9462_2p1_soc_postamble ar9462_2p0_soc_postamble
8140 +
8141 +#define ar9462_2p1_radio_postamble_sys2ant ar9462_2p0_radio_postamble_sys2ant
8142 +
8143 +#define ar9462_2p1_common_rx_gain ar9462_2p0_common_rx_gain
8144 +
8145 +#define ar9462_2p1_common_mixed_rx_gain ar9462_2p0_common_mixed_rx_gain
8146 +
8147 +#define ar9462_2p1_common_5g_xlna_only_rxgain ar9462_2p0_common_5g_xlna_only_rxgain
8148 +
8149 +#define ar9462_2p1_baseband_core_mix_rxgain ar9462_2p0_baseband_core_mix_rxgain
8150 +
8151 +#define ar9462_2p1_baseband_postamble_mix_rxgain ar9462_2p0_baseband_postamble_mix_rxgain
8152 +
8153 +#define ar9462_2p1_baseband_postamble_5g_xlna ar9462_2p0_baseband_postamble_5g_xlna
8154 +
8155 +#define ar9462_2p1_common_wo_xlna_rx_gain ar9462_2p0_common_wo_xlna_rx_gain
8156 +
8157 +#define ar9462_2p1_modes_low_ob_db_tx_gain ar9462_2p0_modes_low_ob_db_tx_gain
8158 +
8159 +#define ar9462_2p1_modes_high_ob_db_tx_gain ar9462_2p0_modes_high_ob_db_tx_gain
8160 +
8161 +#define ar9462_2p1_modes_mix_ob_db_tx_gain ar9462_2p0_modes_mix_ob_db_tx_gain
8162 +
8163 +#define ar9462_2p1_modes_fast_clock ar9462_2p0_modes_fast_clock
8164 +
8165 +#define ar9462_2p1_baseband_core_txfir_coeff_japan_2484 ar9462_2p0_baseband_core_txfir_coeff_japan_2484
8166 +
8167 +#define ar9462_2p1_pciephy_clkreq_disable_L1 ar9462_2p0_pciephy_clkreq_disable_L1
8168 +
8169  static const u32 ar9462_2p1_mac_core[][2] = {
8170         /* Addr      allmodes  */
8171         {0x00000008, 0x00000000},
8172 @@ -183,168 +221,6 @@ static const u32 ar9462_2p1_mac_core[][2
8173         {0x000083d0, 0x000301ff},
8174  };
8175
8176 -static const u32 ar9462_2p1_mac_postamble[][5] = {
8177 -       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
8178 -       {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
8179 -       {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
8180 -       {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
8181 -       {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
8182 -       {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b},
8183 -       {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
8184 -       {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
8185 -       {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
8186 -};
8187 -
8188 -static const u32 ar9462_2p1_baseband_core[][2] = {
8189 -       /* Addr      allmodes  */
8190 -       {0x00009800, 0xafe68e30},
8191 -       {0x00009804, 0xfd14e000},
8192 -       {0x00009808, 0x9c0a9f6b},
8193 -       {0x0000980c, 0x04900000},
8194 -       {0x00009814, 0x9280c00a},
8195 -       {0x00009818, 0x00000000},
8196 -       {0x0000981c, 0x00020028},
8197 -       {0x00009834, 0x6400a290},
8198 -       {0x00009838, 0x0108ecff},
8199 -       {0x0000983c, 0x0d000600},
8200 -       {0x00009880, 0x201fff00},
8201 -       {0x00009884, 0x00001042},
8202 -       {0x000098a4, 0x00200400},
8203 -       {0x000098b0, 0x32440bbe},
8204 -       {0x000098d0, 0x004b6a8e},
8205 -       {0x000098d4, 0x00000820},
8206 -       {0x000098dc, 0x00000000},
8207 -       {0x000098e4, 0x01ffffff},
8208 -       {0x000098e8, 0x01ffffff},
8209 -       {0x000098ec, 0x01ffffff},
8210 -       {0x000098f0, 0x00000000},
8211 -       {0x000098f4, 0x00000000},
8212 -       {0x00009bf0, 0x80000000},
8213 -       {0x00009c04, 0xff55ff55},
8214 -       {0x00009c08, 0x0320ff55},
8215 -       {0x00009c0c, 0x00000000},
8216 -       {0x00009c10, 0x00000000},
8217 -       {0x00009c14, 0x00046384},
8218 -       {0x00009c18, 0x05b6b440},
8219 -       {0x00009c1c, 0x00b6b440},
8220 -       {0x00009d00, 0xc080a333},
8221 -       {0x00009d04, 0x40206c10},
8222 -       {0x00009d08, 0x009c4060},
8223 -       {0x00009d0c, 0x9883800a},
8224 -       {0x00009d10, 0x01834061},
8225 -       {0x00009d14, 0x00c0040b},
8226 -       {0x00009d18, 0x00000000},
8227 -       {0x00009e08, 0x0038230c},
8228 -       {0x00009e24, 0x990bb515},
8229 -       {0x00009e28, 0x0c6f0000},
8230 -       {0x00009e30, 0x06336f77},
8231 -       {0x00009e34, 0x6af6532f},
8232 -       {0x00009e38, 0x0cc80c00},
8233 -       {0x00009e40, 0x15262820},
8234 -       {0x00009e4c, 0x00001004},
8235 -       {0x00009e50, 0x00ff03f1},
8236 -       {0x00009e54, 0xe4c555c2},
8237 -       {0x00009e58, 0xfd857722},
8238 -       {0x00009e5c, 0xe9198724},
8239 -       {0x00009fc0, 0x803e4788},
8240 -       {0x00009fc4, 0x0001efb5},
8241 -       {0x00009fcc, 0x40000014},
8242 -       {0x00009fd0, 0x0a193b93},
8243 -       {0x0000a20c, 0x00000000},
8244 -       {0x0000a220, 0x00000000},
8245 -       {0x0000a224, 0x00000000},
8246 -       {0x0000a228, 0x10002310},
8247 -       {0x0000a23c, 0x00000000},
8248 -       {0x0000a244, 0x0c000000},
8249 -       {0x0000a2a0, 0x00000001},
8250 -       {0x0000a2c0, 0x00000001},
8251 -       {0x0000a2c8, 0x00000000},
8252 -       {0x0000a2cc, 0x18c43433},
8253 -       {0x0000a2d4, 0x00000000},
8254 -       {0x0000a2ec, 0x00000000},
8255 -       {0x0000a2f0, 0x00000000},
8256 -       {0x0000a2f4, 0x00000000},
8257 -       {0x0000a2f8, 0x00000000},
8258 -       {0x0000a344, 0x00000000},
8259 -       {0x0000a34c, 0x00000000},
8260 -       {0x0000a350, 0x0000a000},
8261 -       {0x0000a364, 0x00000000},
8262 -       {0x0000a370, 0x00000000},
8263 -       {0x0000a390, 0x00000001},
8264 -       {0x0000a394, 0x00000444},
8265 -       {0x0000a398, 0x001f0e0f},
8266 -       {0x0000a39c, 0x0075393f},
8267 -       {0x0000a3a0, 0xb79f6427},
8268 -       {0x0000a3c0, 0x20202020},
8269 -       {0x0000a3c4, 0x22222220},
8270 -       {0x0000a3c8, 0x20200020},
8271 -       {0x0000a3cc, 0x20202020},
8272 -       {0x0000a3d0, 0x20202020},
8273 -       {0x0000a3d4, 0x20202020},
8274 -       {0x0000a3d8, 0x20202020},
8275 -       {0x0000a3dc, 0x20202020},
8276 -       {0x0000a3e0, 0x20202020},
8277 -       {0x0000a3e4, 0x20202020},
8278 -       {0x0000a3e8, 0x20202020},
8279 -       {0x0000a3ec, 0x20202020},
8280 -       {0x0000a3f0, 0x00000000},
8281 -       {0x0000a3f4, 0x00000006},
8282 -       {0x0000a3f8, 0x0c9bd380},
8283 -       {0x0000a3fc, 0x000f0f01},
8284 -       {0x0000a400, 0x8fa91f01},
8285 -       {0x0000a404, 0x00000000},
8286 -       {0x0000a408, 0x0e79e5c6},
8287 -       {0x0000a40c, 0x00820820},
8288 -       {0x0000a414, 0x1ce739ce},
8289 -       {0x0000a418, 0x2d001dce},
8290 -       {0x0000a434, 0x00000000},
8291 -       {0x0000a438, 0x00001801},
8292 -       {0x0000a43c, 0x00100000},
8293 -       {0x0000a444, 0x00000000},
8294 -       {0x0000a448, 0x05000080},
8295 -       {0x0000a44c, 0x00000001},
8296 -       {0x0000a450, 0x00010000},
8297 -       {0x0000a454, 0x07000000},
8298 -       {0x0000a644, 0xbfad9d74},
8299 -       {0x0000a648, 0x0048060a},
8300 -       {0x0000a64c, 0x00002037},
8301 -       {0x0000a670, 0x03020100},
8302 -       {0x0000a674, 0x09080504},
8303 -       {0x0000a678, 0x0d0c0b0a},
8304 -       {0x0000a67c, 0x13121110},
8305 -       {0x0000a680, 0x31301514},
8306 -       {0x0000a684, 0x35343332},
8307 -       {0x0000a688, 0x00000036},
8308 -       {0x0000a690, 0x00000838},
8309 -       {0x0000a6b0, 0x0000000a},
8310 -       {0x0000a6b4, 0x00512c01},
8311 -       {0x0000a7c0, 0x00000000},
8312 -       {0x0000a7c4, 0xfffffffc},
8313 -       {0x0000a7c8, 0x00000000},
8314 -       {0x0000a7cc, 0x00000000},
8315 -       {0x0000a7d0, 0x00000000},
8316 -       {0x0000a7d4, 0x00000004},
8317 -       {0x0000a7dc, 0x00000000},
8318 -       {0x0000a7f0, 0x80000000},
8319 -       {0x0000a8d0, 0x004b6a8e},
8320 -       {0x0000a8d4, 0x00000820},
8321 -       {0x0000a8dc, 0x00000000},
8322 -       {0x0000a8f0, 0x00000000},
8323 -       {0x0000a8f4, 0x00000000},
8324 -       {0x0000abf0, 0x80000000},
8325 -       {0x0000b2d0, 0x00000080},
8326 -       {0x0000b2d4, 0x00000000},
8327 -       {0x0000b2ec, 0x00000000},
8328 -       {0x0000b2f0, 0x00000000},
8329 -       {0x0000b2f4, 0x00000000},
8330 -       {0x0000b2f8, 0x00000000},
8331 -       {0x0000b408, 0x0e79e5c0},
8332 -       {0x0000b40c, 0x00820820},
8333 -       {0x0000b420, 0x00000000},
8334 -       {0x0000b6b0, 0x0000000a},
8335 -       {0x0000b6b4, 0x00000001},
8336 -};
8337 -
8338  static const u32 ar9462_2p1_baseband_postamble[][5] = {
8339         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
8340         {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a800d},
8341 @@ -361,7 +237,7 @@ static const u32 ar9462_2p1_baseband_pos
8342         {0x00009e14, 0x37b95d5e, 0x37b9605e, 0x3236605e, 0x32365a5e},
8343         {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8344         {0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c},
8345 -       {0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce},
8346 +       {0x00009e20, 0x000003a5, 0x000003a5, 0x000003a5, 0x000003a5},
8347         {0x00009e2c, 0x0000001c, 0x0000001c, 0x00000021, 0x00000021},
8348         {0x00009e3c, 0xcf946220, 0xcf946220, 0xcfd5c782, 0xcfd5c282},
8349         {0x00009e44, 0x62321e27, 0x62321e27, 0xfe291e27, 0xfe291e27},
8350 @@ -400,1375 +276,16 @@ static const u32 ar9462_2p1_baseband_pos
8351         {0x0000ae04, 0x001c0000, 0x001c0000, 0x001c0000, 0x00100000},
8352         {0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8353         {0x0000ae1c, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
8354 -       {0x0000ae20, 0x000001b5, 0x000001b5, 0x000001ce, 0x000001ce},
8355 +       {0x0000ae20, 0x000001a6, 0x000001a6, 0x000001aa, 0x000001aa},
8356         {0x0000b284, 0x00000000, 0x00000000, 0x00000550, 0x00000550},
8357  };
8358
8359 -static const u32 ar9462_2p1_radio_core[][2] = {
8360 -       /* Addr      allmodes  */
8361 -       {0x00016000, 0x36db6db6},
8362 -       {0x00016004, 0x6db6db40},
8363 -       {0x00016008, 0x73f00000},
8364 -       {0x0001600c, 0x00000000},
8365 -       {0x00016010, 0x6d820001},
8366 -       {0x00016040, 0x7f80fff8},
8367 -       {0x0001604c, 0x2699e04f},
8368 -       {0x00016050, 0x6db6db6c},
8369 -       {0x00016058, 0x6c200000},
8370 -       {0x00016080, 0x000c0000},
8371 -       {0x00016084, 0x9a68048c},
8372 -       {0x00016088, 0x54214514},
8373 -       {0x0001608c, 0x1203040b},
8374 -       {0x00016090, 0x24926490},
8375 -       {0x00016098, 0xd2888888},
8376 -       {0x000160a0, 0x0a108ffe},
8377 -       {0x000160a4, 0x812fc491},
8378 -       {0x000160a8, 0x423c8000},
8379 -       {0x000160b4, 0x92000000},
8380 -       {0x000160b8, 0x0285dddc},
8381 -       {0x000160bc, 0x02908888},
8382 -       {0x000160c0, 0x00adb6d0},
8383 -       {0x000160c4, 0x6db6db60},
8384 -       {0x000160c8, 0x6db6db6c},
8385 -       {0x000160cc, 0x0de6c1b0},
8386 -       {0x00016100, 0x3fffbe04},
8387 -       {0x00016104, 0xfff80000},
8388 -       {0x00016108, 0x00200400},
8389 -       {0x00016110, 0x00000000},
8390 -       {0x00016144, 0x02084080},
8391 -       {0x00016148, 0x000080c0},
8392 -       {0x00016280, 0x050a0001},
8393 -       {0x00016284, 0x3d841418},
8394 -       {0x00016288, 0x00000000},
8395 -       {0x0001628c, 0xe3000000},
8396 -       {0x00016290, 0xa1005080},
8397 -       {0x00016294, 0x00000020},
8398 -       {0x00016298, 0x54a82900},
8399 -       {0x00016340, 0x121e4276},
8400 -       {0x00016344, 0x00300000},
8401 -       {0x00016400, 0x36db6db6},
8402 -       {0x00016404, 0x6db6db40},
8403 -       {0x00016408, 0x73f00000},
8404 -       {0x0001640c, 0x00000000},
8405 -       {0x00016410, 0x6c800001},
8406 -       {0x00016440, 0x7f80fff8},
8407 -       {0x0001644c, 0x4699e04f},
8408 -       {0x00016450, 0x6db6db6c},
8409 -       {0x00016500, 0x3fffbe04},
8410 -       {0x00016504, 0xfff80000},
8411 -       {0x00016508, 0x00200400},
8412 -       {0x00016510, 0x00000000},
8413 -       {0x00016544, 0x02084080},
8414 -       {0x00016548, 0x000080c0},
8415 -};
8416 -
8417 -static const u32 ar9462_2p1_radio_postamble[][5] = {
8418 -       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
8419 -       {0x0001609c, 0x0b8ee524, 0x0b8ee524, 0x0b8ee524, 0x0b8ee524},
8420 -       {0x000160b0, 0x01d67f70, 0x01d67f70, 0x01d67f70, 0x01d67f70},
8421 -       {0x0001610c, 0x48000000, 0x40000000, 0x40000000, 0x40000000},
8422 -       {0x0001650c, 0x48000000, 0x40000000, 0x40000000, 0x40000000},
8423 -};
8424 -
8425  static const u32 ar9462_2p1_soc_preamble[][2] = {
8426         /* Addr      allmodes  */
8427 -       {0x000040a4, 0x00a0c1c9},
8428 +       {0x000040a4, 0x00a0c9c9},
8429         {0x00007020, 0x00000000},
8430         {0x00007034, 0x00000002},
8431         {0x00007038, 0x000004c2},
8432  };
8433
8434 -static const u32 ar9462_2p1_soc_postamble[][5] = {
8435 -       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
8436 -       {0x00007010, 0x00000033, 0x00000033, 0x00000033, 0x00000033},
8437 -};
8438 -
8439 -static const u32 ar9462_2p1_radio_postamble_sys2ant[][5] = {
8440 -       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
8441 -       {0x000160ac, 0xa4646c08, 0xa4646c08, 0x24645808, 0x24645808},
8442 -       {0x00016140, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
8443 -       {0x00016540, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
8444 -};
8445 -
8446 -static const u32 ar9462_2p1_common_rx_gain[][2] = {
8447 -       /* Addr      allmodes  */
8448 -       {0x0000a000, 0x00010000},
8449 -       {0x0000a004, 0x00030002},
8450 -       {0x0000a008, 0x00050004},
8451 -       {0x0000a00c, 0x00810080},
8452 -       {0x0000a010, 0x00830082},
8453 -       {0x0000a014, 0x01810180},
8454 -       {0x0000a018, 0x01830182},
8455 -       {0x0000a01c, 0x01850184},
8456 -       {0x0000a020, 0x01890188},
8457 -       {0x0000a024, 0x018b018a},
8458 -       {0x0000a028, 0x018d018c},
8459 -       {0x0000a02c, 0x01910190},
8460 -       {0x0000a030, 0x01930192},
8461 -       {0x0000a034, 0x01950194},
8462 -       {0x0000a038, 0x038a0196},
8463 -       {0x0000a03c, 0x038c038b},
8464 -       {0x0000a040, 0x0390038d},
8465 -       {0x0000a044, 0x03920391},
8466 -       {0x0000a048, 0x03940393},
8467 -       {0x0000a04c, 0x03960395},
8468 -       {0x0000a050, 0x00000000},
8469 -       {0x0000a054, 0x00000000},
8470 -       {0x0000a058, 0x00000000},
8471 -       {0x0000a05c, 0x00000000},
8472 -       {0x0000a060, 0x00000000},
8473 -       {0x0000a064, 0x00000000},
8474 -       {0x0000a068, 0x00000000},
8475 -       {0x0000a06c, 0x00000000},
8476 -       {0x0000a070, 0x00000000},
8477 -       {0x0000a074, 0x00000000},
8478 -       {0x0000a078, 0x00000000},
8479 -       {0x0000a07c, 0x00000000},
8480 -       {0x0000a080, 0x22222229},
8481 -       {0x0000a084, 0x1d1d1d1d},
8482 -       {0x0000a088, 0x1d1d1d1d},
8483 -       {0x0000a08c, 0x1d1d1d1d},
8484 -       {0x0000a090, 0x171d1d1d},
8485 -       {0x0000a094, 0x11111717},
8486 -       {0x0000a098, 0x00030311},
8487 -       {0x0000a09c, 0x00000000},
8488 -       {0x0000a0a0, 0x00000000},
8489 -       {0x0000a0a4, 0x00000000},
8490 -       {0x0000a0a8, 0x00000000},
8491 -       {0x0000a0ac, 0x00000000},
8492 -       {0x0000a0b0, 0x00000000},
8493 -       {0x0000a0b4, 0x00000000},
8494 -       {0x0000a0b8, 0x00000000},
8495 -       {0x0000a0bc, 0x00000000},
8496 -       {0x0000a0c0, 0x001f0000},
8497 -       {0x0000a0c4, 0x01000101},
8498 -       {0x0000a0c8, 0x011e011f},
8499 -       {0x0000a0cc, 0x011c011d},
8500 -       {0x0000a0d0, 0x02030204},
8501 -       {0x0000a0d4, 0x02010202},
8502 -       {0x0000a0d8, 0x021f0200},
8503 -       {0x0000a0dc, 0x0302021e},
8504 -       {0x0000a0e0, 0x03000301},
8505 -       {0x0000a0e4, 0x031e031f},
8506 -       {0x0000a0e8, 0x0402031d},
8507 -       {0x0000a0ec, 0x04000401},
8508 -       {0x0000a0f0, 0x041e041f},
8509 -       {0x0000a0f4, 0x0502041d},
8510 -       {0x0000a0f8, 0x05000501},
8511 -       {0x0000a0fc, 0x051e051f},
8512 -       {0x0000a100, 0x06010602},
8513 -       {0x0000a104, 0x061f0600},
8514 -       {0x0000a108, 0x061d061e},
8515 -       {0x0000a10c, 0x07020703},
8516 -       {0x0000a110, 0x07000701},
8517 -       {0x0000a114, 0x00000000},
8518 -       {0x0000a118, 0x00000000},
8519 -       {0x0000a11c, 0x00000000},
8520 -       {0x0000a120, 0x00000000},
8521 -       {0x0000a124, 0x00000000},
8522 -       {0x0000a128, 0x00000000},
8523 -       {0x0000a12c, 0x00000000},
8524 -       {0x0000a130, 0x00000000},
8525 -       {0x0000a134, 0x00000000},
8526 -       {0x0000a138, 0x00000000},
8527 -       {0x0000a13c, 0x00000000},
8528 -       {0x0000a140, 0x001f0000},
8529 -       {0x0000a144, 0x01000101},
8530 -       {0x0000a148, 0x011e011f},
8531 -       {0x0000a14c, 0x011c011d},
8532 -       {0x0000a150, 0x02030204},
8533 -       {0x0000a154, 0x02010202},
8534 -       {0x0000a158, 0x021f0200},
8535 -       {0x0000a15c, 0x0302021e},
8536 -       {0x0000a160, 0x03000301},
8537 -       {0x0000a164, 0x031e031f},
8538 -       {0x0000a168, 0x0402031d},
8539 -       {0x0000a16c, 0x04000401},
8540 -       {0x0000a170, 0x041e041f},
8541 -       {0x0000a174, 0x0502041d},
8542 -       {0x0000a178, 0x05000501},
8543 -       {0x0000a17c, 0x051e051f},
8544 -       {0x0000a180, 0x06010602},
8545 -       {0x0000a184, 0x061f0600},
8546 -       {0x0000a188, 0x061d061e},
8547 -       {0x0000a18c, 0x07020703},
8548 -       {0x0000a190, 0x07000701},
8549 -       {0x0000a194, 0x00000000},
8550 -       {0x0000a198, 0x00000000},
8551 -       {0x0000a19c, 0x00000000},
8552 -       {0x0000a1a0, 0x00000000},
8553 -       {0x0000a1a4, 0x00000000},
8554 -       {0x0000a1a8, 0x00000000},
8555 -       {0x0000a1ac, 0x00000000},
8556 -       {0x0000a1b0, 0x00000000},
8557 -       {0x0000a1b4, 0x00000000},
8558 -       {0x0000a1b8, 0x00000000},
8559 -       {0x0000a1bc, 0x00000000},
8560 -       {0x0000a1c0, 0x00000000},
8561 -       {0x0000a1c4, 0x00000000},
8562 -       {0x0000a1c8, 0x00000000},
8563 -       {0x0000a1cc, 0x00000000},
8564 -       {0x0000a1d0, 0x00000000},
8565 -       {0x0000a1d4, 0x00000000},
8566 -       {0x0000a1d8, 0x00000000},
8567 -       {0x0000a1dc, 0x00000000},
8568 -       {0x0000a1e0, 0x00000000},
8569 -       {0x0000a1e4, 0x00000000},
8570 -       {0x0000a1e8, 0x00000000},
8571 -       {0x0000a1ec, 0x00000000},
8572 -       {0x0000a1f0, 0x00000396},
8573 -       {0x0000a1f4, 0x00000396},
8574 -       {0x0000a1f8, 0x00000396},
8575 -       {0x0000a1fc, 0x00000196},
8576 -       {0x0000b000, 0x00010000},
8577 -       {0x0000b004, 0x00030002},
8578 -       {0x0000b008, 0x00050004},
8579 -       {0x0000b00c, 0x00810080},
8580 -       {0x0000b010, 0x00830082},
8581 -       {0x0000b014, 0x01810180},
8582 -       {0x0000b018, 0x01830182},
8583 -       {0x0000b01c, 0x01850184},
8584 -       {0x0000b020, 0x02810280},
8585 -       {0x0000b024, 0x02830282},
8586 -       {0x0000b028, 0x02850284},
8587 -       {0x0000b02c, 0x02890288},
8588 -       {0x0000b030, 0x028b028a},
8589 -       {0x0000b034, 0x0388028c},
8590 -       {0x0000b038, 0x038a0389},
8591 -       {0x0000b03c, 0x038c038b},
8592 -       {0x0000b040, 0x0390038d},
8593 -       {0x0000b044, 0x03920391},
8594 -       {0x0000b048, 0x03940393},
8595 -       {0x0000b04c, 0x03960395},
8596 -       {0x0000b050, 0x00000000},
8597 -       {0x0000b054, 0x00000000},
8598 -       {0x0000b058, 0x00000000},
8599 -       {0x0000b05c, 0x00000000},
8600 -       {0x0000b060, 0x00000000},
8601 -       {0x0000b064, 0x00000000},
8602 -       {0x0000b068, 0x00000000},
8603 -       {0x0000b06c, 0x00000000},
8604 -       {0x0000b070, 0x00000000},
8605 -       {0x0000b074, 0x00000000},
8606 -       {0x0000b078, 0x00000000},
8607 -       {0x0000b07c, 0x00000000},
8608 -       {0x0000b080, 0x2a2d2f32},
8609 -       {0x0000b084, 0x21232328},
8610 -       {0x0000b088, 0x19191c1e},
8611 -       {0x0000b08c, 0x12141417},
8612 -       {0x0000b090, 0x07070e0e},
8613 -       {0x0000b094, 0x03030305},
8614 -       {0x0000b098, 0x00000003},
8615 -       {0x0000b09c, 0x00000000},
8616 -       {0x0000b0a0, 0x00000000},
8617 -       {0x0000b0a4, 0x00000000},
8618 -       {0x0000b0a8, 0x00000000},
8619 -       {0x0000b0ac, 0x00000000},
8620 -       {0x0000b0b0, 0x00000000},
8621 -       {0x0000b0b4, 0x00000000},
8622 -       {0x0000b0b8, 0x00000000},
8623 -       {0x0000b0bc, 0x00000000},
8624 -       {0x0000b0c0, 0x003f0020},
8625 -       {0x0000b0c4, 0x00400041},
8626 -       {0x0000b0c8, 0x0140005f},
8627 -       {0x0000b0cc, 0x0160015f},
8628 -       {0x0000b0d0, 0x017e017f},
8629 -       {0x0000b0d4, 0x02410242},
8630 -       {0x0000b0d8, 0x025f0240},
8631 -       {0x0000b0dc, 0x027f0260},
8632 -       {0x0000b0e0, 0x0341027e},
8633 -       {0x0000b0e4, 0x035f0340},
8634 -       {0x0000b0e8, 0x037f0360},
8635 -       {0x0000b0ec, 0x04400441},
8636 -       {0x0000b0f0, 0x0460045f},
8637 -       {0x0000b0f4, 0x0541047f},
8638 -       {0x0000b0f8, 0x055f0540},
8639 -       {0x0000b0fc, 0x057f0560},
8640 -       {0x0000b100, 0x06400641},
8641 -       {0x0000b104, 0x0660065f},
8642 -       {0x0000b108, 0x067e067f},
8643 -       {0x0000b10c, 0x07410742},
8644 -       {0x0000b110, 0x075f0740},
8645 -       {0x0000b114, 0x077f0760},
8646 -       {0x0000b118, 0x07800781},
8647 -       {0x0000b11c, 0x07a0079f},
8648 -       {0x0000b120, 0x07c107bf},
8649 -       {0x0000b124, 0x000007c0},
8650 -       {0x0000b128, 0x00000000},
8651 -       {0x0000b12c, 0x00000000},
8652 -       {0x0000b130, 0x00000000},
8653 -       {0x0000b134, 0x00000000},
8654 -       {0x0000b138, 0x00000000},
8655 -       {0x0000b13c, 0x00000000},
8656 -       {0x0000b140, 0x003f0020},
8657 -       {0x0000b144, 0x00400041},
8658 -       {0x0000b148, 0x0140005f},
8659 -       {0x0000b14c, 0x0160015f},
8660 -       {0x0000b150, 0x017e017f},
8661 -       {0x0000b154, 0x02410242},
8662 -       {0x0000b158, 0x025f0240},
8663 -       {0x0000b15c, 0x027f0260},
8664 -       {0x0000b160, 0x0341027e},
8665 -       {0x0000b164, 0x035f0340},
8666 -       {0x0000b168, 0x037f0360},
8667 -       {0x0000b16c, 0x04400441},
8668 -       {0x0000b170, 0x0460045f},
8669 -       {0x0000b174, 0x0541047f},
8670 -       {0x0000b178, 0x055f0540},
8671 -       {0x0000b17c, 0x057f0560},
8672 -       {0x0000b180, 0x06400641},
8673 -       {0x0000b184, 0x0660065f},
8674 -       {0x0000b188, 0x067e067f},
8675 -       {0x0000b18c, 0x07410742},
8676 -       {0x0000b190, 0x075f0740},
8677 -       {0x0000b194, 0x077f0760},
8678 -       {0x0000b198, 0x07800781},
8679 -       {0x0000b19c, 0x07a0079f},
8680 -       {0x0000b1a0, 0x07c107bf},
8681 -       {0x0000b1a4, 0x000007c0},
8682 -       {0x0000b1a8, 0x00000000},
8683 -       {0x0000b1ac, 0x00000000},
8684 -       {0x0000b1b0, 0x00000000},
8685 -       {0x0000b1b4, 0x00000000},
8686 -       {0x0000b1b8, 0x00000000},
8687 -       {0x0000b1bc, 0x00000000},
8688 -       {0x0000b1c0, 0x00000000},
8689 -       {0x0000b1c4, 0x00000000},
8690 -       {0x0000b1c8, 0x00000000},
8691 -       {0x0000b1cc, 0x00000000},
8692 -       {0x0000b1d0, 0x00000000},
8693 -       {0x0000b1d4, 0x00000000},
8694 -       {0x0000b1d8, 0x00000000},
8695 -       {0x0000b1dc, 0x00000000},
8696 -       {0x0000b1e0, 0x00000000},
8697 -       {0x0000b1e4, 0x00000000},
8698 -       {0x0000b1e8, 0x00000000},
8699 -       {0x0000b1ec, 0x00000000},
8700 -       {0x0000b1f0, 0x00000396},
8701 -       {0x0000b1f4, 0x00000396},
8702 -       {0x0000b1f8, 0x00000396},
8703 -       {0x0000b1fc, 0x00000196},
8704 -};
8705 -
8706 -static const u32 ar9462_2p1_common_mixed_rx_gain[][2] = {
8707 -       /* Addr      allmodes  */
8708 -       {0x0000a000, 0x00010000},
8709 -       {0x0000a004, 0x00030002},
8710 -       {0x0000a008, 0x00050004},
8711 -       {0x0000a00c, 0x00810080},
8712 -       {0x0000a010, 0x00830082},
8713 -       {0x0000a014, 0x01810180},
8714 -       {0x0000a018, 0x01830182},
8715 -       {0x0000a01c, 0x01850184},
8716 -       {0x0000a020, 0x01890188},
8717 -       {0x0000a024, 0x018b018a},
8718 -       {0x0000a028, 0x018d018c},
8719 -       {0x0000a02c, 0x03820190},
8720 -       {0x0000a030, 0x03840383},
8721 -       {0x0000a034, 0x03880385},
8722 -       {0x0000a038, 0x038a0389},
8723 -       {0x0000a03c, 0x038c038b},
8724 -       {0x0000a040, 0x0390038d},
8725 -       {0x0000a044, 0x03920391},
8726 -       {0x0000a048, 0x03940393},
8727 -       {0x0000a04c, 0x03960395},
8728 -       {0x0000a050, 0x00000000},
8729 -       {0x0000a054, 0x00000000},
8730 -       {0x0000a058, 0x00000000},
8731 -       {0x0000a05c, 0x00000000},
8732 -       {0x0000a060, 0x00000000},
8733 -       {0x0000a064, 0x00000000},
8734 -       {0x0000a068, 0x00000000},
8735 -       {0x0000a06c, 0x00000000},
8736 -       {0x0000a070, 0x00000000},
8737 -       {0x0000a074, 0x00000000},
8738 -       {0x0000a078, 0x00000000},
8739 -       {0x0000a07c, 0x00000000},
8740 -       {0x0000a080, 0x29292929},
8741 -       {0x0000a084, 0x29292929},
8742 -       {0x0000a088, 0x29292929},
8743 -       {0x0000a08c, 0x29292929},
8744 -       {0x0000a090, 0x22292929},
8745 -       {0x0000a094, 0x1d1d2222},
8746 -       {0x0000a098, 0x0c111117},
8747 -       {0x0000a09c, 0x00030303},
8748 -       {0x0000a0a0, 0x00000000},
8749 -       {0x0000a0a4, 0x00000000},
8750 -       {0x0000a0a8, 0x00000000},
8751 -       {0x0000a0ac, 0x00000000},
8752 -       {0x0000a0b0, 0x00000000},
8753 -       {0x0000a0b4, 0x00000000},
8754 -       {0x0000a0b8, 0x00000000},
8755 -       {0x0000a0bc, 0x00000000},
8756 -       {0x0000a0c0, 0x001f0000},
8757 -       {0x0000a0c4, 0x01000101},
8758 -       {0x0000a0c8, 0x011e011f},
8759 -       {0x0000a0cc, 0x011c011d},
8760 -       {0x0000a0d0, 0x02030204},
8761 -       {0x0000a0d4, 0x02010202},
8762 -       {0x0000a0d8, 0x021f0200},
8763 -       {0x0000a0dc, 0x0302021e},
8764 -       {0x0000a0e0, 0x03000301},
8765 -       {0x0000a0e4, 0x031e031f},
8766 -       {0x0000a0e8, 0x0402031d},
8767 -       {0x0000a0ec, 0x04000401},
8768 -       {0x0000a0f0, 0x041e041f},
8769 -       {0x0000a0f4, 0x0502041d},
8770 -       {0x0000a0f8, 0x05000501},
8771 -       {0x0000a0fc, 0x051e051f},
8772 -       {0x0000a100, 0x06010602},
8773 -       {0x0000a104, 0x061f0600},
8774 -       {0x0000a108, 0x061d061e},
8775 -       {0x0000a10c, 0x07020703},
8776 -       {0x0000a110, 0x07000701},
8777 -       {0x0000a114, 0x00000000},
8778 -       {0x0000a118, 0x00000000},
8779 -       {0x0000a11c, 0x00000000},
8780 -       {0x0000a120, 0x00000000},
8781 -       {0x0000a124, 0x00000000},
8782 -       {0x0000a128, 0x00000000},
8783 -       {0x0000a12c, 0x00000000},
8784 -       {0x0000a130, 0x00000000},
8785 -       {0x0000a134, 0x00000000},
8786 -       {0x0000a138, 0x00000000},
8787 -       {0x0000a13c, 0x00000000},
8788 -       {0x0000a140, 0x001f0000},
8789 -       {0x0000a144, 0x01000101},
8790 -       {0x0000a148, 0x011e011f},
8791 -       {0x0000a14c, 0x011c011d},
8792 -       {0x0000a150, 0x02030204},
8793 -       {0x0000a154, 0x02010202},
8794 -       {0x0000a158, 0x021f0200},
8795 -       {0x0000a15c, 0x0302021e},
8796 -       {0x0000a160, 0x03000301},
8797 -       {0x0000a164, 0x031e031f},
8798 -       {0x0000a168, 0x0402031d},
8799 -       {0x0000a16c, 0x04000401},
8800 -       {0x0000a170, 0x041e041f},
8801 -       {0x0000a174, 0x0502041d},
8802 -       {0x0000a178, 0x05000501},
8803 -       {0x0000a17c, 0x051e051f},
8804 -       {0x0000a180, 0x06010602},
8805 -       {0x0000a184, 0x061f0600},
8806 -       {0x0000a188, 0x061d061e},
8807 -       {0x0000a18c, 0x07020703},
8808 -       {0x0000a190, 0x07000701},
8809 -       {0x0000a194, 0x00000000},
8810 -       {0x0000a198, 0x00000000},
8811 -       {0x0000a19c, 0x00000000},
8812 -       {0x0000a1a0, 0x00000000},
8813 -       {0x0000a1a4, 0x00000000},
8814 -       {0x0000a1a8, 0x00000000},
8815 -       {0x0000a1ac, 0x00000000},
8816 -       {0x0000a1b0, 0x00000000},
8817 -       {0x0000a1b4, 0x00000000},
8818 -       {0x0000a1b8, 0x00000000},
8819 -       {0x0000a1bc, 0x00000000},
8820 -       {0x0000a1c0, 0x00000000},
8821 -       {0x0000a1c4, 0x00000000},
8822 -       {0x0000a1c8, 0x00000000},
8823 -       {0x0000a1cc, 0x00000000},
8824 -       {0x0000a1d0, 0x00000000},
8825 -       {0x0000a1d4, 0x00000000},
8826 -       {0x0000a1d8, 0x00000000},
8827 -       {0x0000a1dc, 0x00000000},
8828 -       {0x0000a1e0, 0x00000000},
8829 -       {0x0000a1e4, 0x00000000},
8830 -       {0x0000a1e8, 0x00000000},
8831 -       {0x0000a1ec, 0x00000000},
8832 -       {0x0000a1f0, 0x00000396},
8833 -       {0x0000a1f4, 0x00000396},
8834 -       {0x0000a1f8, 0x00000396},
8835 -       {0x0000a1fc, 0x00000196},
8836 -       {0x0000b000, 0x00010000},
8837 -       {0x0000b004, 0x00030002},
8838 -       {0x0000b008, 0x00050004},
8839 -       {0x0000b00c, 0x00810080},
8840 -       {0x0000b010, 0x00830082},
8841 -       {0x0000b014, 0x01810180},
8842 -       {0x0000b018, 0x01830182},
8843 -       {0x0000b01c, 0x01850184},
8844 -       {0x0000b020, 0x02810280},
8845 -       {0x0000b024, 0x02830282},
8846 -       {0x0000b028, 0x02850284},
8847 -       {0x0000b02c, 0x02890288},
8848 -       {0x0000b030, 0x028b028a},
8849 -       {0x0000b034, 0x0388028c},
8850 -       {0x0000b038, 0x038a0389},
8851 -       {0x0000b03c, 0x038c038b},
8852 -       {0x0000b040, 0x0390038d},
8853 -       {0x0000b044, 0x03920391},
8854 -       {0x0000b048, 0x03940393},
8855 -       {0x0000b04c, 0x03960395},
8856 -       {0x0000b050, 0x00000000},
8857 -       {0x0000b054, 0x00000000},
8858 -       {0x0000b058, 0x00000000},
8859 -       {0x0000b05c, 0x00000000},
8860 -       {0x0000b060, 0x00000000},
8861 -       {0x0000b064, 0x00000000},
8862 -       {0x0000b068, 0x00000000},
8863 -       {0x0000b06c, 0x00000000},
8864 -       {0x0000b070, 0x00000000},
8865 -       {0x0000b074, 0x00000000},
8866 -       {0x0000b078, 0x00000000},
8867 -       {0x0000b07c, 0x00000000},
8868 -       {0x0000b080, 0x2a2d2f32},
8869 -       {0x0000b084, 0x21232328},
8870 -       {0x0000b088, 0x19191c1e},
8871 -       {0x0000b08c, 0x12141417},
8872 -       {0x0000b090, 0x07070e0e},
8873 -       {0x0000b094, 0x03030305},
8874 -       {0x0000b098, 0x00000003},
8875 -       {0x0000b09c, 0x00000000},
8876 -       {0x0000b0a0, 0x00000000},
8877 -       {0x0000b0a4, 0x00000000},
8878 -       {0x0000b0a8, 0x00000000},
8879 -       {0x0000b0ac, 0x00000000},
8880 -       {0x0000b0b0, 0x00000000},
8881 -       {0x0000b0b4, 0x00000000},
8882 -       {0x0000b0b8, 0x00000000},
8883 -       {0x0000b0bc, 0x00000000},
8884 -       {0x0000b0c0, 0x003f0020},
8885 -       {0x0000b0c4, 0x00400041},
8886 -       {0x0000b0c8, 0x0140005f},
8887 -       {0x0000b0cc, 0x0160015f},
8888 -       {0x0000b0d0, 0x017e017f},
8889 -       {0x0000b0d4, 0x02410242},
8890 -       {0x0000b0d8, 0x025f0240},
8891 -       {0x0000b0dc, 0x027f0260},
8892 -       {0x0000b0e0, 0x0341027e},
8893 -       {0x0000b0e4, 0x035f0340},
8894 -       {0x0000b0e8, 0x037f0360},
8895 -       {0x0000b0ec, 0x04400441},
8896 -       {0x0000b0f0, 0x0460045f},
8897 -       {0x0000b0f4, 0x0541047f},
8898 -       {0x0000b0f8, 0x055f0540},
8899 -       {0x0000b0fc, 0x057f0560},
8900 -       {0x0000b100, 0x06400641},
8901 -       {0x0000b104, 0x0660065f},
8902 -       {0x0000b108, 0x067e067f},
8903 -       {0x0000b10c, 0x07410742},
8904 -       {0x0000b110, 0x075f0740},
8905 -       {0x0000b114, 0x077f0760},
8906 -       {0x0000b118, 0x07800781},
8907 -       {0x0000b11c, 0x07a0079f},
8908 -       {0x0000b120, 0x07c107bf},
8909 -       {0x0000b124, 0x000007c0},
8910 -       {0x0000b128, 0x00000000},
8911 -       {0x0000b12c, 0x00000000},
8912 -       {0x0000b130, 0x00000000},
8913 -       {0x0000b134, 0x00000000},
8914 -       {0x0000b138, 0x00000000},
8915 -       {0x0000b13c, 0x00000000},
8916 -       {0x0000b140, 0x003f0020},
8917 -       {0x0000b144, 0x00400041},
8918 -       {0x0000b148, 0x0140005f},
8919 -       {0x0000b14c, 0x0160015f},
8920 -       {0x0000b150, 0x017e017f},
8921 -       {0x0000b154, 0x02410242},
8922 -       {0x0000b158, 0x025f0240},
8923 -       {0x0000b15c, 0x027f0260},
8924 -       {0x0000b160, 0x0341027e},
8925 -       {0x0000b164, 0x035f0340},
8926 -       {0x0000b168, 0x037f0360},
8927 -       {0x0000b16c, 0x04400441},
8928 -       {0x0000b170, 0x0460045f},
8929 -       {0x0000b174, 0x0541047f},
8930 -       {0x0000b178, 0x055f0540},
8931 -       {0x0000b17c, 0x057f0560},
8932 -       {0x0000b180, 0x06400641},
8933 -       {0x0000b184, 0x0660065f},
8934 -       {0x0000b188, 0x067e067f},
8935 -       {0x0000b18c, 0x07410742},
8936 -       {0x0000b190, 0x075f0740},
8937 -       {0x0000b194, 0x077f0760},
8938 -       {0x0000b198, 0x07800781},
8939 -       {0x0000b19c, 0x07a0079f},
8940 -       {0x0000b1a0, 0x07c107bf},
8941 -       {0x0000b1a4, 0x000007c0},
8942 -       {0x0000b1a8, 0x00000000},
8943 -       {0x0000b1ac, 0x00000000},
8944 -       {0x0000b1b0, 0x00000000},
8945 -       {0x0000b1b4, 0x00000000},
8946 -       {0x0000b1b8, 0x00000000},
8947 -       {0x0000b1bc, 0x00000000},
8948 -       {0x0000b1c0, 0x00000000},
8949 -       {0x0000b1c4, 0x00000000},
8950 -       {0x0000b1c8, 0x00000000},
8951 -       {0x0000b1cc, 0x00000000},
8952 -       {0x0000b1d0, 0x00000000},
8953 -       {0x0000b1d4, 0x00000000},
8954 -       {0x0000b1d8, 0x00000000},
8955 -       {0x0000b1dc, 0x00000000},
8956 -       {0x0000b1e0, 0x00000000},
8957 -       {0x0000b1e4, 0x00000000},
8958 -       {0x0000b1e8, 0x00000000},
8959 -       {0x0000b1ec, 0x00000000},
8960 -       {0x0000b1f0, 0x00000396},
8961 -       {0x0000b1f4, 0x00000396},
8962 -       {0x0000b1f8, 0x00000396},
8963 -       {0x0000b1fc, 0x00000196},
8964 -};
8965 -
8966 -static const u32 ar9462_2p1_baseband_core_mix_rxgain[][2] = {
8967 -       /* Addr      allmodes  */
8968 -       {0x00009fd0, 0x0a2d6b93},
8969 -};
8970 -
8971 -static const u32 ar9462_2p1_baseband_postamble_mix_rxgain[][5] = {
8972 -       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
8973 -       {0x00009820, 0x206a022e, 0x206a022e, 0x206a01ae, 0x206a01ae},
8974 -       {0x00009824, 0x63c640de, 0x5ac640d0, 0x63c640da, 0x63c640da},
8975 -       {0x00009828, 0x0796be89, 0x0696b081, 0x0916be81, 0x0916be81},
8976 -       {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000d8, 0x6c4000d8},
8977 -       {0x00009e10, 0x92c88d2e, 0x7ec88d2e, 0x7ec86d2e, 0x7ec86d2e},
8978 -       {0x00009e14, 0x37b95d5e, 0x37b9605e, 0x3236605e, 0x32395c5e},
8979 -};
8980 -
8981 -static const u32 ar9462_2p1_baseband_postamble_5g_xlna[][5] = {
8982 -       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
8983 -       {0x00009e3c, 0xcf946220, 0xcf946220, 0xcfd5c782, 0xcfd5c282},
8984 -};
8985 -
8986 -static const u32 ar9462_2p1_common_wo_xlna_rx_gain[][2] = {
8987 -       /* Addr      allmodes  */
8988 -       {0x0000a000, 0x00010000},
8989 -       {0x0000a004, 0x00030002},
8990 -       {0x0000a008, 0x00050004},
8991 -       {0x0000a00c, 0x00810080},
8992 -       {0x0000a010, 0x00830082},
8993 -       {0x0000a014, 0x01810180},
8994 -       {0x0000a018, 0x01830182},
8995 -       {0x0000a01c, 0x01850184},
8996 -       {0x0000a020, 0x01890188},
8997 -       {0x0000a024, 0x018b018a},
8998 -       {0x0000a028, 0x018d018c},
8999 -       {0x0000a02c, 0x03820190},
9000 -       {0x0000a030, 0x03840383},
9001 -       {0x0000a034, 0x03880385},
9002 -       {0x0000a038, 0x038a0389},
9003 -       {0x0000a03c, 0x038c038b},
9004 -       {0x0000a040, 0x0390038d},
9005 -       {0x0000a044, 0x03920391},
9006 -       {0x0000a048, 0x03940393},
9007 -       {0x0000a04c, 0x03960395},
9008 -       {0x0000a050, 0x00000000},
9009 -       {0x0000a054, 0x00000000},
9010 -       {0x0000a058, 0x00000000},
9011 -       {0x0000a05c, 0x00000000},
9012 -       {0x0000a060, 0x00000000},
9013 -       {0x0000a064, 0x00000000},
9014 -       {0x0000a068, 0x00000000},
9015 -       {0x0000a06c, 0x00000000},
9016 -       {0x0000a070, 0x00000000},
9017 -       {0x0000a074, 0x00000000},
9018 -       {0x0000a078, 0x00000000},
9019 -       {0x0000a07c, 0x00000000},
9020 -       {0x0000a080, 0x29292929},
9021 -       {0x0000a084, 0x29292929},
9022 -       {0x0000a088, 0x29292929},
9023 -       {0x0000a08c, 0x29292929},
9024 -       {0x0000a090, 0x22292929},
9025 -       {0x0000a094, 0x1d1d2222},
9026 -       {0x0000a098, 0x0c111117},
9027 -       {0x0000a09c, 0x00030303},
9028 -       {0x0000a0a0, 0x00000000},
9029 -       {0x0000a0a4, 0x00000000},
9030 -       {0x0000a0a8, 0x00000000},
9031 -       {0x0000a0ac, 0x00000000},
9032 -       {0x0000a0b0, 0x00000000},
9033 -       {0x0000a0b4, 0x00000000},
9034 -       {0x0000a0b8, 0x00000000},
9035 -       {0x0000a0bc, 0x00000000},
9036 -       {0x0000a0c0, 0x001f0000},
9037 -       {0x0000a0c4, 0x01000101},
9038 -       {0x0000a0c8, 0x011e011f},
9039 -       {0x0000a0cc, 0x011c011d},
9040 -       {0x0000a0d0, 0x02030204},
9041 -       {0x0000a0d4, 0x02010202},
9042 -       {0x0000a0d8, 0x021f0200},
9043 -       {0x0000a0dc, 0x0302021e},
9044 -       {0x0000a0e0, 0x03000301},
9045 -       {0x0000a0e4, 0x031e031f},
9046 -       {0x0000a0e8, 0x0402031d},
9047 -       {0x0000a0ec, 0x04000401},
9048 -       {0x0000a0f0, 0x041e041f},
9049 -       {0x0000a0f4, 0x0502041d},
9050 -       {0x0000a0f8, 0x05000501},
9051 -       {0x0000a0fc, 0x051e051f},
9052 -       {0x0000a100, 0x06010602},
9053 -       {0x0000a104, 0x061f0600},
9054 -       {0x0000a108, 0x061d061e},
9055 -       {0x0000a10c, 0x07020703},
9056 -       {0x0000a110, 0x07000701},
9057 -       {0x0000a114, 0x00000000},
9058 -       {0x0000a118, 0x00000000},
9059 -       {0x0000a11c, 0x00000000},
9060 -       {0x0000a120, 0x00000000},
9061 -       {0x0000a124, 0x00000000},
9062 -       {0x0000a128, 0x00000000},
9063 -       {0x0000a12c, 0x00000000},
9064 -       {0x0000a130, 0x00000000},
9065 -       {0x0000a134, 0x00000000},
9066 -       {0x0000a138, 0x00000000},
9067 -       {0x0000a13c, 0x00000000},
9068 -       {0x0000a140, 0x001f0000},
9069 -       {0x0000a144, 0x01000101},
9070 -       {0x0000a148, 0x011e011f},
9071 -       {0x0000a14c, 0x011c011d},
9072 -       {0x0000a150, 0x02030204},
9073 -       {0x0000a154, 0x02010202},
9074 -       {0x0000a158, 0x021f0200},
9075 -       {0x0000a15c, 0x0302021e},
9076 -       {0x0000a160, 0x03000301},
9077 -       {0x0000a164, 0x031e031f},
9078 -       {0x0000a168, 0x0402031d},
9079 -       {0x0000a16c, 0x04000401},
9080 -       {0x0000a170, 0x041e041f},
9081 -       {0x0000a174, 0x0502041d},
9082 -       {0x0000a178, 0x05000501},
9083 -       {0x0000a17c, 0x051e051f},
9084 -       {0x0000a180, 0x06010602},
9085 -       {0x0000a184, 0x061f0600},
9086 -       {0x0000a188, 0x061d061e},
9087 -       {0x0000a18c, 0x07020703},
9088 -       {0x0000a190, 0x07000701},
9089 -       {0x0000a194, 0x00000000},
9090 -       {0x0000a198, 0x00000000},
9091 -       {0x0000a19c, 0x00000000},
9092 -       {0x0000a1a0, 0x00000000},
9093 -       {0x0000a1a4, 0x00000000},
9094 -       {0x0000a1a8, 0x00000000},
9095 -       {0x0000a1ac, 0x00000000},
9096 -       {0x0000a1b0, 0x00000000},
9097 -       {0x0000a1b4, 0x00000000},
9098 -       {0x0000a1b8, 0x00000000},
9099 -       {0x0000a1bc, 0x00000000},
9100 -       {0x0000a1c0, 0x00000000},
9101 -       {0x0000a1c4, 0x00000000},
9102 -       {0x0000a1c8, 0x00000000},
9103 -       {0x0000a1cc, 0x00000000},
9104 -       {0x0000a1d0, 0x00000000},
9105 -       {0x0000a1d4, 0x00000000},
9106 -       {0x0000a1d8, 0x00000000},
9107 -       {0x0000a1dc, 0x00000000},
9108 -       {0x0000a1e0, 0x00000000},
9109 -       {0x0000a1e4, 0x00000000},
9110 -       {0x0000a1e8, 0x00000000},
9111 -       {0x0000a1ec, 0x00000000},
9112 -       {0x0000a1f0, 0x00000396},
9113 -       {0x0000a1f4, 0x00000396},
9114 -       {0x0000a1f8, 0x00000396},
9115 -       {0x0000a1fc, 0x00000196},
9116 -       {0x0000b000, 0x00010000},
9117 -       {0x0000b004, 0x00030002},
9118 -       {0x0000b008, 0x00050004},
9119 -       {0x0000b00c, 0x00810080},
9120 -       {0x0000b010, 0x00830082},
9121 -       {0x0000b014, 0x01810180},
9122 -       {0x0000b018, 0x01830182},
9123 -       {0x0000b01c, 0x01850184},
9124 -       {0x0000b020, 0x02810280},
9125 -       {0x0000b024, 0x02830282},
9126 -       {0x0000b028, 0x02850284},
9127 -       {0x0000b02c, 0x02890288},
9128 -       {0x0000b030, 0x028b028a},
9129 -       {0x0000b034, 0x0388028c},
9130 -       {0x0000b038, 0x038a0389},
9131 -       {0x0000b03c, 0x038c038b},
9132 -       {0x0000b040, 0x0390038d},
9133 -       {0x0000b044, 0x03920391},
9134 -       {0x0000b048, 0x03940393},
9135 -       {0x0000b04c, 0x03960395},
9136 -       {0x0000b050, 0x00000000},
9137 -       {0x0000b054, 0x00000000},
9138 -       {0x0000b058, 0x00000000},
9139 -       {0x0000b05c, 0x00000000},
9140 -       {0x0000b060, 0x00000000},
9141 -       {0x0000b064, 0x00000000},
9142 -       {0x0000b068, 0x00000000},
9143 -       {0x0000b06c, 0x00000000},
9144 -       {0x0000b070, 0x00000000},
9145 -       {0x0000b074, 0x00000000},
9146 -       {0x0000b078, 0x00000000},
9147 -       {0x0000b07c, 0x00000000},
9148 -       {0x0000b080, 0x32323232},
9149 -       {0x0000b084, 0x2f2f3232},
9150 -       {0x0000b088, 0x23282a2d},
9151 -       {0x0000b08c, 0x1c1e2123},
9152 -       {0x0000b090, 0x14171919},
9153 -       {0x0000b094, 0x0e0e1214},
9154 -       {0x0000b098, 0x03050707},
9155 -       {0x0000b09c, 0x00030303},
9156 -       {0x0000b0a0, 0x00000000},
9157 -       {0x0000b0a4, 0x00000000},
9158 -       {0x0000b0a8, 0x00000000},
9159 -       {0x0000b0ac, 0x00000000},
9160 -       {0x0000b0b0, 0x00000000},
9161 -       {0x0000b0b4, 0x00000000},
9162 -       {0x0000b0b8, 0x00000000},
9163 -       {0x0000b0bc, 0x00000000},
9164 -       {0x0000b0c0, 0x003f0020},
9165 -       {0x0000b0c4, 0x00400041},
9166 -       {0x0000b0c8, 0x0140005f},
9167 -       {0x0000b0cc, 0x0160015f},
9168 -       {0x0000b0d0, 0x017e017f},
9169 -       {0x0000b0d4, 0x02410242},
9170 -       {0x0000b0d8, 0x025f0240},
9171 -       {0x0000b0dc, 0x027f0260},
9172 -       {0x0000b0e0, 0x0341027e},
9173 -       {0x0000b0e4, 0x035f0340},
9174 -       {0x0000b0e8, 0x037f0360},
9175 -       {0x0000b0ec, 0x04400441},
9176 -       {0x0000b0f0, 0x0460045f},
9177 -       {0x0000b0f4, 0x0541047f},
9178 -       {0x0000b0f8, 0x055f0540},
9179 -       {0x0000b0fc, 0x057f0560},
9180 -       {0x0000b100, 0x06400641},
9181 -       {0x0000b104, 0x0660065f},
9182 -       {0x0000b108, 0x067e067f},
9183 -       {0x0000b10c, 0x07410742},
9184 -       {0x0000b110, 0x075f0740},
9185 -       {0x0000b114, 0x077f0760},
9186 -       {0x0000b118, 0x07800781},
9187 -       {0x0000b11c, 0x07a0079f},
9188 -       {0x0000b120, 0x07c107bf},
9189 -       {0x0000b124, 0x000007c0},
9190 -       {0x0000b128, 0x00000000},
9191 -       {0x0000b12c, 0x00000000},
9192 -       {0x0000b130, 0x00000000},
9193 -       {0x0000b134, 0x00000000},
9194 -       {0x0000b138, 0x00000000},
9195 -       {0x0000b13c, 0x00000000},
9196 -       {0x0000b140, 0x003f0020},
9197 -       {0x0000b144, 0x00400041},
9198 -       {0x0000b148, 0x0140005f},
9199 -       {0x0000b14c, 0x0160015f},
9200 -       {0x0000b150, 0x017e017f},
9201 -       {0x0000b154, 0x02410242},
9202 -       {0x0000b158, 0x025f0240},
9203 -       {0x0000b15c, 0x027f0260},
9204 -       {0x0000b160, 0x0341027e},
9205 -       {0x0000b164, 0x035f0340},
9206 -       {0x0000b168, 0x037f0360},
9207 -       {0x0000b16c, 0x04400441},
9208 -       {0x0000b170, 0x0460045f},
9209 -       {0x0000b174, 0x0541047f},
9210 -       {0x0000b178, 0x055f0540},
9211 -       {0x0000b17c, 0x057f0560},
9212 -       {0x0000b180, 0x06400641},
9213 -       {0x0000b184, 0x0660065f},
9214 -       {0x0000b188, 0x067e067f},
9215 -       {0x0000b18c, 0x07410742},
9216 -       {0x0000b190, 0x075f0740},
9217 -       {0x0000b194, 0x077f0760},
9218 -       {0x0000b198, 0x07800781},
9219 -       {0x0000b19c, 0x07a0079f},
9220 -       {0x0000b1a0, 0x07c107bf},
9221 -       {0x0000b1a4, 0x000007c0},
9222 -       {0x0000b1a8, 0x00000000},
9223 -       {0x0000b1ac, 0x00000000},
9224 -       {0x0000b1b0, 0x00000000},
9225 -       {0x0000b1b4, 0x00000000},
9226 -       {0x0000b1b8, 0x00000000},
9227 -       {0x0000b1bc, 0x00000000},
9228 -       {0x0000b1c0, 0x00000000},
9229 -       {0x0000b1c4, 0x00000000},
9230 -       {0x0000b1c8, 0x00000000},
9231 -       {0x0000b1cc, 0x00000000},
9232 -       {0x0000b1d0, 0x00000000},
9233 -       {0x0000b1d4, 0x00000000},
9234 -       {0x0000b1d8, 0x00000000},
9235 -       {0x0000b1dc, 0x00000000},
9236 -       {0x0000b1e0, 0x00000000},
9237 -       {0x0000b1e4, 0x00000000},
9238 -       {0x0000b1e8, 0x00000000},
9239 -       {0x0000b1ec, 0x00000000},
9240 -       {0x0000b1f0, 0x00000396},
9241 -       {0x0000b1f4, 0x00000396},
9242 -       {0x0000b1f8, 0x00000396},
9243 -       {0x0000b1fc, 0x00000196},
9244 -};
9245 -
9246 -static const u32 ar9462_2p1_common_5g_xlna_only_rx_gain[][2] = {
9247 -       /* Addr      allmodes  */
9248 -       {0x0000a000, 0x00010000},
9249 -       {0x0000a004, 0x00030002},
9250 -       {0x0000a008, 0x00050004},
9251 -       {0x0000a00c, 0x00810080},
9252 -       {0x0000a010, 0x00830082},
9253 -       {0x0000a014, 0x01810180},
9254 -       {0x0000a018, 0x01830182},
9255 -       {0x0000a01c, 0x01850184},
9256 -       {0x0000a020, 0x01890188},
9257 -       {0x0000a024, 0x018b018a},
9258 -       {0x0000a028, 0x018d018c},
9259 -       {0x0000a02c, 0x03820190},
9260 -       {0x0000a030, 0x03840383},
9261 -       {0x0000a034, 0x03880385},
9262 -       {0x0000a038, 0x038a0389},
9263 -       {0x0000a03c, 0x038c038b},
9264 -       {0x0000a040, 0x0390038d},
9265 -       {0x0000a044, 0x03920391},
9266 -       {0x0000a048, 0x03940393},
9267 -       {0x0000a04c, 0x03960395},
9268 -       {0x0000a050, 0x00000000},
9269 -       {0x0000a054, 0x00000000},
9270 -       {0x0000a058, 0x00000000},
9271 -       {0x0000a05c, 0x00000000},
9272 -       {0x0000a060, 0x00000000},
9273 -       {0x0000a064, 0x00000000},
9274 -       {0x0000a068, 0x00000000},
9275 -       {0x0000a06c, 0x00000000},
9276 -       {0x0000a070, 0x00000000},
9277 -       {0x0000a074, 0x00000000},
9278 -       {0x0000a078, 0x00000000},
9279 -       {0x0000a07c, 0x00000000},
9280 -       {0x0000a080, 0x29292929},
9281 -       {0x0000a084, 0x29292929},
9282 -       {0x0000a088, 0x29292929},
9283 -       {0x0000a08c, 0x29292929},
9284 -       {0x0000a090, 0x22292929},
9285 -       {0x0000a094, 0x1d1d2222},
9286 -       {0x0000a098, 0x0c111117},
9287 -       {0x0000a09c, 0x00030303},
9288 -       {0x0000a0a0, 0x00000000},
9289 -       {0x0000a0a4, 0x00000000},
9290 -       {0x0000a0a8, 0x00000000},
9291 -       {0x0000a0ac, 0x00000000},
9292 -       {0x0000a0b0, 0x00000000},
9293 -       {0x0000a0b4, 0x00000000},
9294 -       {0x0000a0b8, 0x00000000},
9295 -       {0x0000a0bc, 0x00000000},
9296 -       {0x0000a0c0, 0x001f0000},
9297 -       {0x0000a0c4, 0x01000101},
9298 -       {0x0000a0c8, 0x011e011f},
9299 -       {0x0000a0cc, 0x011c011d},
9300 -       {0x0000a0d0, 0x02030204},
9301 -       {0x0000a0d4, 0x02010202},
9302 -       {0x0000a0d8, 0x021f0200},
9303 -       {0x0000a0dc, 0x0302021e},
9304 -       {0x0000a0e0, 0x03000301},
9305 -       {0x0000a0e4, 0x031e031f},
9306 -       {0x0000a0e8, 0x0402031d},
9307 -       {0x0000a0ec, 0x04000401},
9308 -       {0x0000a0f0, 0x041e041f},
9309 -       {0x0000a0f4, 0x0502041d},
9310 -       {0x0000a0f8, 0x05000501},
9311 -       {0x0000a0fc, 0x051e051f},
9312 -       {0x0000a100, 0x06010602},
9313 -       {0x0000a104, 0x061f0600},
9314 -       {0x0000a108, 0x061d061e},
9315 -       {0x0000a10c, 0x07020703},
9316 -       {0x0000a110, 0x07000701},
9317 -       {0x0000a114, 0x00000000},
9318 -       {0x0000a118, 0x00000000},
9319 -       {0x0000a11c, 0x00000000},
9320 -       {0x0000a120, 0x00000000},
9321 -       {0x0000a124, 0x00000000},
9322 -       {0x0000a128, 0x00000000},
9323 -       {0x0000a12c, 0x00000000},
9324 -       {0x0000a130, 0x00000000},
9325 -       {0x0000a134, 0x00000000},
9326 -       {0x0000a138, 0x00000000},
9327 -       {0x0000a13c, 0x00000000},
9328 -       {0x0000a140, 0x001f0000},
9329 -       {0x0000a144, 0x01000101},
9330 -       {0x0000a148, 0x011e011f},
9331 -       {0x0000a14c, 0x011c011d},
9332 -       {0x0000a150, 0x02030204},
9333 -       {0x0000a154, 0x02010202},
9334 -       {0x0000a158, 0x021f0200},
9335 -       {0x0000a15c, 0x0302021e},
9336 -       {0x0000a160, 0x03000301},
9337 -       {0x0000a164, 0x031e031f},
9338 -       {0x0000a168, 0x0402031d},
9339 -       {0x0000a16c, 0x04000401},
9340 -       {0x0000a170, 0x041e041f},
9341 -       {0x0000a174, 0x0502041d},
9342 -       {0x0000a178, 0x05000501},
9343 -       {0x0000a17c, 0x051e051f},
9344 -       {0x0000a180, 0x06010602},
9345 -       {0x0000a184, 0x061f0600},
9346 -       {0x0000a188, 0x061d061e},
9347 -       {0x0000a18c, 0x07020703},
9348 -       {0x0000a190, 0x07000701},
9349 -       {0x0000a194, 0x00000000},
9350 -       {0x0000a198, 0x00000000},
9351 -       {0x0000a19c, 0x00000000},
9352 -       {0x0000a1a0, 0x00000000},
9353 -       {0x0000a1a4, 0x00000000},
9354 -       {0x0000a1a8, 0x00000000},
9355 -       {0x0000a1ac, 0x00000000},
9356 -       {0x0000a1b0, 0x00000000},
9357 -       {0x0000a1b4, 0x00000000},
9358 -       {0x0000a1b8, 0x00000000},
9359 -       {0x0000a1bc, 0x00000000},
9360 -       {0x0000a1c0, 0x00000000},
9361 -       {0x0000a1c4, 0x00000000},
9362 -       {0x0000a1c8, 0x00000000},
9363 -       {0x0000a1cc, 0x00000000},
9364 -       {0x0000a1d0, 0x00000000},
9365 -       {0x0000a1d4, 0x00000000},
9366 -       {0x0000a1d8, 0x00000000},
9367 -       {0x0000a1dc, 0x00000000},
9368 -       {0x0000a1e0, 0x00000000},
9369 -       {0x0000a1e4, 0x00000000},
9370 -       {0x0000a1e8, 0x00000000},
9371 -       {0x0000a1ec, 0x00000000},
9372 -       {0x0000a1f0, 0x00000396},
9373 -       {0x0000a1f4, 0x00000396},
9374 -       {0x0000a1f8, 0x00000396},
9375 -       {0x0000a1fc, 0x00000196},
9376 -       {0x0000b000, 0x00010000},
9377 -       {0x0000b004, 0x00030002},
9378 -       {0x0000b008, 0x00050004},
9379 -       {0x0000b00c, 0x00810080},
9380 -       {0x0000b010, 0x00830082},
9381 -       {0x0000b014, 0x01810180},
9382 -       {0x0000b018, 0x01830182},
9383 -       {0x0000b01c, 0x01850184},
9384 -       {0x0000b020, 0x02810280},
9385 -       {0x0000b024, 0x02830282},
9386 -       {0x0000b028, 0x02850284},
9387 -       {0x0000b02c, 0x02890288},
9388 -       {0x0000b030, 0x028b028a},
9389 -       {0x0000b034, 0x0388028c},
9390 -       {0x0000b038, 0x038a0389},
9391 -       {0x0000b03c, 0x038c038b},
9392 -       {0x0000b040, 0x0390038d},
9393 -       {0x0000b044, 0x03920391},
9394 -       {0x0000b048, 0x03940393},
9395 -       {0x0000b04c, 0x03960395},
9396 -       {0x0000b050, 0x00000000},
9397 -       {0x0000b054, 0x00000000},
9398 -       {0x0000b058, 0x00000000},
9399 -       {0x0000b05c, 0x00000000},
9400 -       {0x0000b060, 0x00000000},
9401 -       {0x0000b064, 0x00000000},
9402 -       {0x0000b068, 0x00000000},
9403 -       {0x0000b06c, 0x00000000},
9404 -       {0x0000b070, 0x00000000},
9405 -       {0x0000b074, 0x00000000},
9406 -       {0x0000b078, 0x00000000},
9407 -       {0x0000b07c, 0x00000000},
9408 -       {0x0000b080, 0x2a2d2f32},
9409 -       {0x0000b084, 0x21232328},
9410 -       {0x0000b088, 0x19191c1e},
9411 -       {0x0000b08c, 0x12141417},
9412 -       {0x0000b090, 0x07070e0e},
9413 -       {0x0000b094, 0x03030305},
9414 -       {0x0000b098, 0x00000003},
9415 -       {0x0000b09c, 0x00000000},
9416 -       {0x0000b0a0, 0x00000000},
9417 -       {0x0000b0a4, 0x00000000},
9418 -       {0x0000b0a8, 0x00000000},
9419 -       {0x0000b0ac, 0x00000000},
9420 -       {0x0000b0b0, 0x00000000},
9421 -       {0x0000b0b4, 0x00000000},
9422 -       {0x0000b0b8, 0x00000000},
9423 -       {0x0000b0bc, 0x00000000},
9424 -       {0x0000b0c0, 0x003f0020},
9425 -       {0x0000b0c4, 0x00400041},
9426 -       {0x0000b0c8, 0x0140005f},
9427 -       {0x0000b0cc, 0x0160015f},
9428 -       {0x0000b0d0, 0x017e017f},
9429 -       {0x0000b0d4, 0x02410242},
9430 -       {0x0000b0d8, 0x025f0240},
9431 -       {0x0000b0dc, 0x027f0260},
9432 -       {0x0000b0e0, 0x0341027e},
9433 -       {0x0000b0e4, 0x035f0340},
9434 -       {0x0000b0e8, 0x037f0360},
9435 -       {0x0000b0ec, 0x04400441},
9436 -       {0x0000b0f0, 0x0460045f},
9437 -       {0x0000b0f4, 0x0541047f},
9438 -       {0x0000b0f8, 0x055f0540},
9439 -       {0x0000b0fc, 0x057f0560},
9440 -       {0x0000b100, 0x06400641},
9441 -       {0x0000b104, 0x0660065f},
9442 -       {0x0000b108, 0x067e067f},
9443 -       {0x0000b10c, 0x07410742},
9444 -       {0x0000b110, 0x075f0740},
9445 -       {0x0000b114, 0x077f0760},
9446 -       {0x0000b118, 0x07800781},
9447 -       {0x0000b11c, 0x07a0079f},
9448 -       {0x0000b120, 0x07c107bf},
9449 -       {0x0000b124, 0x000007c0},
9450 -       {0x0000b128, 0x00000000},
9451 -       {0x0000b12c, 0x00000000},
9452 -       {0x0000b130, 0x00000000},
9453 -       {0x0000b134, 0x00000000},
9454 -       {0x0000b138, 0x00000000},
9455 -       {0x0000b13c, 0x00000000},
9456 -       {0x0000b140, 0x003f0020},
9457 -       {0x0000b144, 0x00400041},
9458 -       {0x0000b148, 0x0140005f},
9459 -       {0x0000b14c, 0x0160015f},
9460 -       {0x0000b150, 0x017e017f},
9461 -       {0x0000b154, 0x02410242},
9462 -       {0x0000b158, 0x025f0240},
9463 -       {0x0000b15c, 0x027f0260},
9464 -       {0x0000b160, 0x0341027e},
9465 -       {0x0000b164, 0x035f0340},
9466 -       {0x0000b168, 0x037f0360},
9467 -       {0x0000b16c, 0x04400441},
9468 -       {0x0000b170, 0x0460045f},
9469 -       {0x0000b174, 0x0541047f},
9470 -       {0x0000b178, 0x055f0540},
9471 -       {0x0000b17c, 0x057f0560},
9472 -       {0x0000b180, 0x06400641},
9473 -       {0x0000b184, 0x0660065f},
9474 -       {0x0000b188, 0x067e067f},
9475 -       {0x0000b18c, 0x07410742},
9476 -       {0x0000b190, 0x075f0740},
9477 -       {0x0000b194, 0x077f0760},
9478 -       {0x0000b198, 0x07800781},
9479 -       {0x0000b19c, 0x07a0079f},
9480 -       {0x0000b1a0, 0x07c107bf},
9481 -       {0x0000b1a4, 0x000007c0},
9482 -       {0x0000b1a8, 0x00000000},
9483 -       {0x0000b1ac, 0x00000000},
9484 -       {0x0000b1b0, 0x00000000},
9485 -       {0x0000b1b4, 0x00000000},
9486 -       {0x0000b1b8, 0x00000000},
9487 -       {0x0000b1bc, 0x00000000},
9488 -       {0x0000b1c0, 0x00000000},
9489 -       {0x0000b1c4, 0x00000000},
9490 -       {0x0000b1c8, 0x00000000},
9491 -       {0x0000b1cc, 0x00000000},
9492 -       {0x0000b1d0, 0x00000000},
9493 -       {0x0000b1d4, 0x00000000},
9494 -       {0x0000b1d8, 0x00000000},
9495 -       {0x0000b1dc, 0x00000000},
9496 -       {0x0000b1e0, 0x00000000},
9497 -       {0x0000b1e4, 0x00000000},
9498 -       {0x0000b1e8, 0x00000000},
9499 -       {0x0000b1ec, 0x00000000},
9500 -       {0x0000b1f0, 0x00000396},
9501 -       {0x0000b1f4, 0x00000396},
9502 -       {0x0000b1f8, 0x00000396},
9503 -       {0x0000b1fc, 0x00000196},
9504 -};
9505 -
9506 -static const u32 ar9462_2p1_modes_low_ob_db_tx_gain[][5] = {
9507 -       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
9508 -       {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
9509 -       {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
9510 -       {0x0000a2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
9511 -       {0x0000a2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
9512 -       {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
9513 -       {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
9514 -       {0x0000a458, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9515 -       {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9516 -       {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
9517 -       {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004},
9518 -       {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
9519 -       {0x0000a510, 0x16000220, 0x16000220, 0x0f000202, 0x0f000202},
9520 -       {0x0000a514, 0x1c000223, 0x1c000223, 0x12000400, 0x12000400},
9521 -       {0x0000a518, 0x21020220, 0x21020220, 0x16000402, 0x16000402},
9522 -       {0x0000a51c, 0x27020223, 0x27020223, 0x19000404, 0x19000404},
9523 -       {0x0000a520, 0x2b022220, 0x2b022220, 0x1c000603, 0x1c000603},
9524 -       {0x0000a524, 0x2f022222, 0x2f022222, 0x21000a02, 0x21000a02},
9525 -       {0x0000a528, 0x34022225, 0x34022225, 0x25000a04, 0x25000a04},
9526 -       {0x0000a52c, 0x3a02222a, 0x3a02222a, 0x28000a20, 0x28000a20},
9527 -       {0x0000a530, 0x3e02222c, 0x3e02222c, 0x2c000e20, 0x2c000e20},
9528 -       {0x0000a534, 0x4202242a, 0x4202242a, 0x30000e22, 0x30000e22},
9529 -       {0x0000a538, 0x4702244a, 0x4702244a, 0x34000e24, 0x34000e24},
9530 -       {0x0000a53c, 0x4b02244c, 0x4b02244c, 0x38001640, 0x38001640},
9531 -       {0x0000a540, 0x4e02246c, 0x4e02246c, 0x3c001660, 0x3c001660},
9532 -       {0x0000a544, 0x5302266c, 0x5302266c, 0x3f001861, 0x3f001861},
9533 -       {0x0000a548, 0x5702286c, 0x5702286c, 0x43001a81, 0x43001a81},
9534 -       {0x0000a54c, 0x5c04286b, 0x5c04286b, 0x47001a83, 0x47001a83},
9535 -       {0x0000a550, 0x61042a6c, 0x61042a6c, 0x4a001c84, 0x4a001c84},
9536 -       {0x0000a554, 0x66062a6c, 0x66062a6c, 0x4e001ce3, 0x4e001ce3},
9537 -       {0x0000a558, 0x6b062e6c, 0x6b062e6c, 0x52001ce5, 0x52001ce5},
9538 -       {0x0000a55c, 0x7006308c, 0x7006308c, 0x56001ce9, 0x56001ce9},
9539 -       {0x0000a560, 0x730a308a, 0x730a308a, 0x5a001ceb, 0x5a001ceb},
9540 -       {0x0000a564, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
9541 -       {0x0000a568, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
9542 -       {0x0000a56c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
9543 -       {0x0000a570, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
9544 -       {0x0000a574, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
9545 -       {0x0000a578, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
9546 -       {0x0000a57c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
9547 -       {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9548 -       {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9549 -       {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9550 -       {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9551 -       {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9552 -       {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000},
9553 -       {0x0000a618, 0x01404501, 0x01404501, 0x01404501, 0x01404501},
9554 -       {0x0000a61c, 0x02008802, 0x02008802, 0x02008501, 0x02008501},
9555 -       {0x0000a620, 0x0300cc03, 0x0300cc03, 0x0280ca03, 0x0280ca03},
9556 -       {0x0000a624, 0x0300cc03, 0x0300cc03, 0x03010c04, 0x03010c04},
9557 -       {0x0000a628, 0x0300cc03, 0x0300cc03, 0x04014c04, 0x04014c04},
9558 -       {0x0000a62c, 0x03810c03, 0x03810c03, 0x04015005, 0x04015005},
9559 -       {0x0000a630, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
9560 -       {0x0000a634, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
9561 -       {0x0000a638, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
9562 -       {0x0000a63c, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
9563 -       {0x0000b2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
9564 -       {0x0000b2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
9565 -       {0x0000b2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
9566 -       {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
9567 -       {0x00016044, 0x012482d4, 0x012482d4, 0x012482d4, 0x012482d4},
9568 -       {0x00016048, 0x64992060, 0x64992060, 0x64992060, 0x64992060},
9569 -       {0x00016054, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000},
9570 -       {0x00016444, 0x012482d4, 0x012482d4, 0x012482d4, 0x012482d4},
9571 -       {0x00016448, 0x64992000, 0x64992000, 0x64992000, 0x64992000},
9572 -       {0x00016454, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000},
9573 -};
9574 -
9575 -static const u32 ar9462_2p1_modes_high_ob_db_tx_gain[][5] = {
9576 -       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
9577 -       {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
9578 -       {0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
9579 -       {0x0000a2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584},
9580 -       {0x0000a2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800},
9581 -       {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
9582 -       {0x0000a410, 0x000050da, 0x000050da, 0x000050de, 0x000050de},
9583 -       {0x0000a458, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9584 -       {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000},
9585 -       {0x0000a504, 0x06002223, 0x06002223, 0x04000002, 0x04000002},
9586 -       {0x0000a508, 0x0a022220, 0x0a022220, 0x08000004, 0x08000004},
9587 -       {0x0000a50c, 0x0f022223, 0x0f022223, 0x0b000200, 0x0b000200},
9588 -       {0x0000a510, 0x14022620, 0x14022620, 0x0f000202, 0x0f000202},
9589 -       {0x0000a514, 0x18022622, 0x18022622, 0x11000400, 0x11000400},
9590 -       {0x0000a518, 0x1b022822, 0x1b022822, 0x15000402, 0x15000402},
9591 -       {0x0000a51c, 0x20022842, 0x20022842, 0x19000404, 0x19000404},
9592 -       {0x0000a520, 0x22022c41, 0x22022c41, 0x1b000603, 0x1b000603},
9593 -       {0x0000a524, 0x28023042, 0x28023042, 0x1f000a02, 0x1f000a02},
9594 -       {0x0000a528, 0x2c023044, 0x2c023044, 0x23000a04, 0x23000a04},
9595 -       {0x0000a52c, 0x2f023644, 0x2f023644, 0x26000a20, 0x26000a20},
9596 -       {0x0000a530, 0x34025643, 0x34025643, 0x2a000e20, 0x2a000e20},
9597 -       {0x0000a534, 0x38025a44, 0x38025a44, 0x2e000e22, 0x2e000e22},
9598 -       {0x0000a538, 0x3b025e45, 0x3b025e45, 0x31000e24, 0x31000e24},
9599 -       {0x0000a53c, 0x41025e4a, 0x41025e4a, 0x34001640, 0x34001640},
9600 -       {0x0000a540, 0x48025e6c, 0x48025e6c, 0x38001660, 0x38001660},
9601 -       {0x0000a544, 0x4e025e8e, 0x4e025e8e, 0x3b001861, 0x3b001861},
9602 -       {0x0000a548, 0x55025eb3, 0x55025eb3, 0x3e001a81, 0x3e001a81},
9603 -       {0x0000a54c, 0x58025ef3, 0x58025ef3, 0x42001a83, 0x42001a83},
9604 -       {0x0000a550, 0x5d025ef6, 0x5d025ef6, 0x44001a84, 0x44001a84},
9605 -       {0x0000a554, 0x62025f56, 0x62025f56, 0x48001ce3, 0x48001ce3},
9606 -       {0x0000a558, 0x66027f56, 0x66027f56, 0x4c001ce5, 0x4c001ce5},
9607 -       {0x0000a55c, 0x6a029f56, 0x6a029f56, 0x50001ce9, 0x50001ce9},
9608 -       {0x0000a560, 0x70049f56, 0x70049f56, 0x54001ceb, 0x54001ceb},
9609 -       {0x0000a564, 0x751ffff6, 0x751ffff6, 0x56001eec, 0x56001eec},
9610 -       {0x0000a568, 0x751ffff6, 0x751ffff6, 0x58001ef0, 0x58001ef0},
9611 -       {0x0000a56c, 0x751ffff6, 0x751ffff6, 0x5a001ef4, 0x5a001ef4},
9612 -       {0x0000a570, 0x751ffff6, 0x751ffff6, 0x5c001ff6, 0x5c001ff6},
9613 -       {0x0000a574, 0x751ffff6, 0x751ffff6, 0x5c001ff6, 0x5c001ff6},
9614 -       {0x0000a578, 0x751ffff6, 0x751ffff6, 0x5c001ff6, 0x5c001ff6},
9615 -       {0x0000a57c, 0x751ffff6, 0x751ffff6, 0x5c001ff6, 0x5c001ff6},
9616 -       {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9617 -       {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9618 -       {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9619 -       {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9620 -       {0x0000a610, 0x00804000, 0x00804000, 0x00000000, 0x00000000},
9621 -       {0x0000a614, 0x00804201, 0x00804201, 0x01404000, 0x01404000},
9622 -       {0x0000a618, 0x0280c802, 0x0280c802, 0x01404501, 0x01404501},
9623 -       {0x0000a61c, 0x0280ca03, 0x0280ca03, 0x02008501, 0x02008501},
9624 -       {0x0000a620, 0x04c15104, 0x04c15104, 0x0280ca03, 0x0280ca03},
9625 -       {0x0000a624, 0x04c15305, 0x04c15305, 0x03010c04, 0x03010c04},
9626 -       {0x0000a628, 0x04c15305, 0x04c15305, 0x04014c04, 0x04014c04},
9627 -       {0x0000a62c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
9628 -       {0x0000a630, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
9629 -       {0x0000a634, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
9630 -       {0x0000a638, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
9631 -       {0x0000a63c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
9632 -       {0x0000b2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
9633 -       {0x0000b2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584},
9634 -       {0x0000b2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800},
9635 -       {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
9636 -       {0x00016044, 0x056d82e4, 0x056d82e4, 0x056d82e4, 0x056d82e4},
9637 -       {0x00016048, 0x8db49060, 0x8db49060, 0x8db49060, 0x8db49060},
9638 -       {0x00016054, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000},
9639 -       {0x00016444, 0x056d82e4, 0x056d82e4, 0x056d82e4, 0x056d82e4},
9640 -       {0x00016448, 0x8db49000, 0x8db49000, 0x8db49000, 0x8db49000},
9641 -       {0x00016454, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000},
9642 -};
9643 -
9644 -static const u32 ar9462_2p1_modes_mix_ob_db_tx_gain[][5] = {
9645 -       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
9646 -       {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
9647 -       {0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
9648 -       {0x0000a2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584},
9649 -       {0x0000a2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800},
9650 -       {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
9651 -       {0x0000a410, 0x0000d0da, 0x0000d0da, 0x0000d0de, 0x0000d0de},
9652 -       {0x0000a458, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9653 -       {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000},
9654 -       {0x0000a504, 0x06002223, 0x06002223, 0x04000002, 0x04000002},
9655 -       {0x0000a508, 0x0a022220, 0x0a022220, 0x08000004, 0x08000004},
9656 -       {0x0000a50c, 0x0f022223, 0x0f022223, 0x0b000200, 0x0b000200},
9657 -       {0x0000a510, 0x14022620, 0x14022620, 0x0f000202, 0x0f000202},
9658 -       {0x0000a514, 0x18022622, 0x18022622, 0x12000400, 0x12000400},
9659 -       {0x0000a518, 0x1b022822, 0x1b022822, 0x16000402, 0x16000402},
9660 -       {0x0000a51c, 0x20022842, 0x20022842, 0x19000404, 0x19000404},
9661 -       {0x0000a520, 0x22022c41, 0x22022c41, 0x1c000603, 0x1c000603},
9662 -       {0x0000a524, 0x28023042, 0x28023042, 0x21000a02, 0x21000a02},
9663 -       {0x0000a528, 0x2c023044, 0x2c023044, 0x25000a04, 0x25000a04},
9664 -       {0x0000a52c, 0x2f023644, 0x2f023644, 0x28000a20, 0x28000a20},
9665 -       {0x0000a530, 0x34025643, 0x34025643, 0x2c000e20, 0x2c000e20},
9666 -       {0x0000a534, 0x38025a44, 0x38025a44, 0x30000e22, 0x30000e22},
9667 -       {0x0000a538, 0x3b025e45, 0x3b025e45, 0x34000e24, 0x34000e24},
9668 -       {0x0000a53c, 0x41025e4a, 0x41025e4a, 0x38001640, 0x38001640},
9669 -       {0x0000a540, 0x48025e6c, 0x48025e6c, 0x3c001660, 0x3c001660},
9670 -       {0x0000a544, 0x4e025e8e, 0x4e025e8e, 0x3f001861, 0x3f001861},
9671 -       {0x0000a548, 0x55025eb3, 0x55025eb3, 0x43001a81, 0x43001a81},
9672 -       {0x0000a54c, 0x58025ef3, 0x58025ef3, 0x47001a83, 0x47001a83},
9673 -       {0x0000a550, 0x5d025ef6, 0x5d025ef6, 0x4a001c84, 0x4a001c84},
9674 -       {0x0000a554, 0x62025f56, 0x62025f56, 0x4e001ce3, 0x4e001ce3},
9675 -       {0x0000a558, 0x66027f56, 0x66027f56, 0x52001ce5, 0x52001ce5},
9676 -       {0x0000a55c, 0x6a029f56, 0x6a029f56, 0x56001ce9, 0x56001ce9},
9677 -       {0x0000a560, 0x70049f56, 0x70049f56, 0x5a001ceb, 0x5a001ceb},
9678 -       {0x0000a564, 0x751ffff6, 0x751ffff6, 0x5c001eec, 0x5c001eec},
9679 -       {0x0000a568, 0x751ffff6, 0x751ffff6, 0x5e001ef0, 0x5e001ef0},
9680 -       {0x0000a56c, 0x751ffff6, 0x751ffff6, 0x60001ef4, 0x60001ef4},
9681 -       {0x0000a570, 0x751ffff6, 0x751ffff6, 0x62001ff6, 0x62001ff6},
9682 -       {0x0000a574, 0x751ffff6, 0x751ffff6, 0x62001ff6, 0x62001ff6},
9683 -       {0x0000a578, 0x751ffff6, 0x751ffff6, 0x62001ff6, 0x62001ff6},
9684 -       {0x0000a57c, 0x751ffff6, 0x751ffff6, 0x62001ff6, 0x62001ff6},
9685 -       {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9686 -       {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9687 -       {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9688 -       {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9689 -       {0x0000a610, 0x00804000, 0x00804000, 0x00000000, 0x00000000},
9690 -       {0x0000a614, 0x00804201, 0x00804201, 0x01404000, 0x01404000},
9691 -       {0x0000a618, 0x0280c802, 0x0280c802, 0x01404501, 0x01404501},
9692 -       {0x0000a61c, 0x0280ca03, 0x0280ca03, 0x02008501, 0x02008501},
9693 -       {0x0000a620, 0x04c15104, 0x04c15104, 0x0280ca03, 0x0280ca03},
9694 -       {0x0000a624, 0x04c15305, 0x04c15305, 0x03010c04, 0x03010c04},
9695 -       {0x0000a628, 0x04c15305, 0x04c15305, 0x04014c04, 0x04014c04},
9696 -       {0x0000a62c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
9697 -       {0x0000a630, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
9698 -       {0x0000a634, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
9699 -       {0x0000a638, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
9700 -       {0x0000a63c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
9701 -       {0x0000b2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
9702 -       {0x0000b2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584},
9703 -       {0x0000b2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800},
9704 -       {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
9705 -};
9706 -
9707 -static const u32 ar9462_2p1_modes_fast_clock[][3] = {
9708 -       /* Addr      5G_HT20     5G_HT40   */
9709 -       {0x00001030, 0x00000268, 0x000004d0},
9710 -       {0x00001070, 0x0000018c, 0x00000318},
9711 -       {0x000010b0, 0x00000fd0, 0x00001fa0},
9712 -       {0x00008014, 0x044c044c, 0x08980898},
9713 -       {0x0000801c, 0x148ec02b, 0x148ec057},
9714 -       {0x00008318, 0x000044c0, 0x00008980},
9715 -       {0x00009e00, 0x0372131c, 0x0372131c},
9716 -       {0x0000a230, 0x0000400b, 0x00004016},
9717 -       {0x0000a254, 0x00000898, 0x00001130},
9718 -};
9719 -
9720 -static const u32 ar9462_2p1_baseband_core_txfir_coeff_japan_2484[][2] = {
9721 -       /* Addr      allmodes  */
9722 -       {0x0000a398, 0x00000000},
9723 -       {0x0000a39c, 0x6f7f0301},
9724 -       {0x0000a3a0, 0xca9228ee},
9725 -};
9726 -
9727  #endif /* INITVALS_9462_2P1_H */
9728 --- a/drivers/net/wireless/ath/ath9k/ar9485_initvals.h
9729 +++ b/drivers/net/wireless/ath/ath9k/ar9485_initvals.h
9730 @@ -20,24 +20,11 @@
9731
9732  /* AR9485 1.1 */
9733
9734 -static const u32 ar9485_1_1_mac_postamble[][5] = {
9735 -       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
9736 -       {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
9737 -       {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
9738 -       {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
9739 -       {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
9740 -       {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b},
9741 -       {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
9742 -       {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
9743 -       {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
9744 -};
9745 +#define ar9485_modes_lowest_ob_db_tx_gain_1_1 ar9485Modes_low_ob_db_tx_gain_1_1
9746
9747 -static const u32 ar9485_1_1_pcie_phy_pll_on_clkreq_disable_L1[][2] = {
9748 -       /* Addr      allmodes  */
9749 -       {0x00018c00, 0x18012e5e},
9750 -       {0x00018c04, 0x000801d8},
9751 -       {0x00018c08, 0x0000080c},
9752 -};
9753 +#define ar9485_1_1_mac_postamble ar9331_1p1_mac_postamble
9754 +
9755 +#define ar9485_1_1_baseband_core_txfir_coeff_japan_2484 ar9300_2p2_baseband_core_txfir_coeff_japan_2484
9756
9757  static const u32 ar9485Common_wo_xlna_rx_gain_1_1[][2] = {
9758         /* Addr      allmodes  */
9759 @@ -553,100 +540,6 @@ static const u32 ar9485Modes_low_ob_db_t
9760         {0x00016048, 0x6c924260, 0x6c924260, 0x6c924260, 0x6c924260},
9761  };
9762
9763 -static const u32 ar9485_modes_lowest_ob_db_tx_gain_1_1[][5] = {
9764 -       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
9765 -       {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
9766 -       {0x0000a2d8, 0xf999a83a, 0xf999a83a, 0x7999a83a, 0x7999a83a},
9767 -       {0x0000a2dc, 0x00000000, 0x00000000, 0xfe2d3552, 0xfe2d3552},
9768 -       {0x0000a2e0, 0x00000000, 0x00000000, 0xfe2d3552, 0xfe2d3552},
9769 -       {0x0000a2e4, 0x00000000, 0x00000000, 0xfe2d3552, 0xfe2d3552},
9770 -       {0x0000a2e8, 0x00000000, 0x00000000, 0xfe2d3552, 0xfe2d3552},
9771 -       {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d8, 0x000050d8},
9772 -       {0x0000a458, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9773 -       {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
9774 -       {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
9775 -       {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
9776 -       {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
9777 -       {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
9778 -       {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
9779 -       {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
9780 -       {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
9781 -       {0x0000a520, 0x2f001f04, 0x2f001f04, 0x21000603, 0x21000603},
9782 -       {0x0000a524, 0x35001fc4, 0x35001fc4, 0x25000605, 0x25000605},
9783 -       {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2a000a03, 0x2a000a03},
9784 -       {0x0000a52c, 0x41023e85, 0x41023e85, 0x2c000a04, 0x2c000a04},
9785 -       {0x0000a530, 0x48023ec6, 0x48023ec6, 0x34000e20, 0x34000e20},
9786 -       {0x0000a534, 0x4d023f01, 0x4d023f01, 0x35000e21, 0x35000e21},
9787 -       {0x0000a538, 0x53023f4b, 0x53023f4b, 0x43000e62, 0x43000e62},
9788 -       {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x45000e63, 0x45000e63},
9789 -       {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x49000e65, 0x49000e65},
9790 -       {0x0000a544, 0x6502feca, 0x6502feca, 0x4b000e66, 0x4b000e66},
9791 -       {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x4d001645, 0x4d001645},
9792 -       {0x0000a54c, 0x7203feca, 0x7203feca, 0x51001865, 0x51001865},
9793 -       {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x55001a86, 0x55001a86},
9794 -       {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x57001ce9, 0x57001ce9},
9795 -       {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x5a001ceb, 0x5a001ceb},
9796 -       {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x5e001eeb, 0x5e001eeb},
9797 -       {0x0000a560, 0x900fff0b, 0x900fff0b, 0x5e001eeb, 0x5e001eeb},
9798 -       {0x0000a564, 0x960fffcb, 0x960fffcb, 0x5e001eeb, 0x5e001eeb},
9799 -       {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
9800 -       {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
9801 -       {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
9802 -       {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
9803 -       {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
9804 -       {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
9805 -       {0x0000a580, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9806 -       {0x0000a584, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9807 -       {0x0000a588, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9808 -       {0x0000a58c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9809 -       {0x0000a590, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9810 -       {0x0000a594, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9811 -       {0x0000a598, 0x00000000, 0x00000000, 0x01404501, 0x01404501},
9812 -       {0x0000a59c, 0x00000000, 0x00000000, 0x02808a02, 0x02808a02},
9813 -       {0x0000a5a0, 0x00000000, 0x00000000, 0x02808a02, 0x02808a02},
9814 -       {0x0000a5a4, 0x00000000, 0x00000000, 0x02808803, 0x02808803},
9815 -       {0x0000a5a8, 0x00000000, 0x00000000, 0x04c14b04, 0x04c14b04},
9816 -       {0x0000a5ac, 0x00000000, 0x00000000, 0x04c15305, 0x04c15305},
9817 -       {0x0000a5b0, 0x00000000, 0x00000000, 0x04c15305, 0x04c15305},
9818 -       {0x0000a5b4, 0x00000000, 0x00000000, 0x04c15305, 0x04c15305},
9819 -       {0x0000a5b8, 0x00000000, 0x00000000, 0x04c15305, 0x04c15305},
9820 -       {0x0000a5bc, 0x00000000, 0x00000000, 0x04c15305, 0x04c15305},
9821 -       {0x0000b500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9822 -       {0x0000b504, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9823 -       {0x0000b508, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9824 -       {0x0000b50c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9825 -       {0x0000b510, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9826 -       {0x0000b514, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9827 -       {0x0000b518, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9828 -       {0x0000b51c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9829 -       {0x0000b520, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9830 -       {0x0000b524, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9831 -       {0x0000b528, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9832 -       {0x0000b52c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9833 -       {0x0000b530, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9834 -       {0x0000b534, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9835 -       {0x0000b538, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9836 -       {0x0000b53c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9837 -       {0x0000b540, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9838 -       {0x0000b544, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9839 -       {0x0000b548, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9840 -       {0x0000b54c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9841 -       {0x0000b550, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9842 -       {0x0000b554, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9843 -       {0x0000b558, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9844 -       {0x0000b55c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9845 -       {0x0000b560, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9846 -       {0x0000b564, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9847 -       {0x0000b568, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9848 -       {0x0000b56c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9849 -       {0x0000b570, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9850 -       {0x0000b574, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9851 -       {0x0000b578, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9852 -       {0x0000b57c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9853 -       {0x00016044, 0x05d6b2db, 0x05d6b2db, 0x05d6b2db, 0x05d6b2db},
9854 -       {0x00016048, 0x6c924260, 0x6c924260, 0x6c924260, 0x6c924260},
9855 -};
9856 -
9857  static const u32 ar9485Modes_green_spur_ob_db_tx_gain_1_1[][5] = {
9858         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
9859         {0x000098bc, 0x00000003, 0x00000003, 0x00000003, 0x00000003},
9860 @@ -1101,20 +994,6 @@ static const u32 ar9485_common_rx_gain_1
9861         {0x0000a1fc, 0x00000296},
9862  };
9863
9864 -static const u32 ar9485_1_1_pcie_phy_pll_on_clkreq_enable_L1[][2] = {
9865 -       /* Addr      allmodes  */
9866 -       {0x00018c00, 0x18052e5e},
9867 -       {0x00018c04, 0x000801d8},
9868 -       {0x00018c08, 0x0000080c},
9869 -};
9870 -
9871 -static const u32 ar9485_1_1_pcie_phy_clkreq_enable_L1[][2] = {
9872 -       /* Addr      allmodes  */
9873 -       {0x00018c00, 0x18053e5e},
9874 -       {0x00018c04, 0x000801d8},
9875 -       {0x00018c08, 0x0000080c},
9876 -};
9877 -
9878  static const u32 ar9485_1_1_soc_preamble[][2] = {
9879         /* Addr      allmodes  */
9880         {0x00004014, 0xba280400},
9881 @@ -1173,13 +1052,6 @@ static const u32 ar9485_1_1_baseband_pos
9882         {0x0000be18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9883  };
9884
9885 -static const u32 ar9485_1_1_pcie_phy_clkreq_disable_L1[][2] = {
9886 -       /* Addr      allmodes  */
9887 -       {0x00018c00, 0x18013e5e},
9888 -       {0x00018c04, 0x000801d8},
9889 -       {0x00018c08, 0x0000080c},
9890 -};
9891 -
9892  static const u32 ar9485_1_1_radio_postamble[][2] = {
9893         /* Addr      allmodes  */
9894         {0x0001609c, 0x0b283f31},
9895 @@ -1351,11 +1223,18 @@ static const u32 ar9485_1_1_mac_core[][2
9896         {0x000083d0, 0x000301ff},
9897  };
9898
9899 -static const u32 ar9485_1_1_baseband_core_txfir_coeff_japan_2484[][2] = {
9900 +static const u32 ar9485_1_1_pcie_phy_clkreq_disable_L1[][2] = {
9901         /* Addr      allmodes  */
9902 -       {0x0000a398, 0x00000000},
9903 -       {0x0000a39c, 0x6f7f0301},
9904 -       {0x0000a3a0, 0xca9228ee},
9905 +       {0x00018c00, 0x18013e5e},
9906 +       {0x00018c04, 0x000801d8},
9907 +       {0x00018c08, 0x0000080c},
9908 +};
9909 +
9910 +static const u32 ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1[][2] = {
9911 +       /* Addr      allmodes  */
9912 +       {0x00018c00, 0x1801265e},
9913 +       {0x00018c04, 0x000801d8},
9914 +       {0x00018c08, 0x0000080c},
9915  };
9916
9917  #endif /* INITVALS_9485_H */
9918 --- a/drivers/net/wireless/ath/ath9k/pci.c
9919 +++ b/drivers/net/wireless/ath/ath9k/pci.c
9920 @@ -195,6 +195,93 @@ static DEFINE_PCI_DEVICE_TABLE(ath_pci_i
9921                          0x3219),
9922           .driver_data = ATH9K_PCI_BT_ANT_DIV },
9923
9924 +       /* AR9485 cards with PLL power-save disabled by default. */
9925 +       { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
9926 +                        0x0032,
9927 +                        PCI_VENDOR_ID_AZWAVE,
9928 +                        0x2C97),
9929 +         .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
9930 +       { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
9931 +                        0x0032,
9932 +                        PCI_VENDOR_ID_AZWAVE,
9933 +                        0x2100),
9934 +         .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
9935 +       { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
9936 +                        0x0032,
9937 +                        0x1C56, /* ASKEY */
9938 +                        0x4001),
9939 +         .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
9940 +       { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
9941 +                        0x0032,
9942 +                        0x11AD, /* LITEON */
9943 +                        0x6627),
9944 +         .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
9945 +       { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
9946 +                        0x0032,
9947 +                        0x11AD, /* LITEON */
9948 +                        0x6628),
9949 +         .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
9950 +       { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
9951 +                        0x0032,
9952 +                        PCI_VENDOR_ID_FOXCONN,
9953 +                        0xE04E),
9954 +         .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
9955 +       { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
9956 +                        0x0032,
9957 +                        PCI_VENDOR_ID_FOXCONN,
9958 +                        0xE04F),
9959 +         .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
9960 +       { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
9961 +                        0x0032,
9962 +                        0x144F, /* ASKEY */
9963 +                        0x7197),
9964 +         .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
9965 +       { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
9966 +                        0x0032,
9967 +                        0x1B9A, /* XAVI */
9968 +                        0x2000),
9969 +         .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
9970 +       { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
9971 +                        0x0032,
9972 +                        0x1B9A, /* XAVI */
9973 +                        0x2001),
9974 +         .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
9975 +       { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
9976 +                        0x0032,
9977 +                        PCI_VENDOR_ID_AZWAVE,
9978 +                        0x1186),
9979 +         .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
9980 +       { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
9981 +                        0x0032,
9982 +                        PCI_VENDOR_ID_AZWAVE,
9983 +                        0x1F86),
9984 +         .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
9985 +       { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
9986 +                        0x0032,
9987 +                        PCI_VENDOR_ID_AZWAVE,
9988 +                        0x1195),
9989 +         .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
9990 +       { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
9991 +                        0x0032,
9992 +                        PCI_VENDOR_ID_AZWAVE,
9993 +                        0x1F95),
9994 +         .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
9995 +       { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
9996 +                        0x0032,
9997 +                        0x1B9A, /* XAVI */
9998 +                        0x1C00),
9999 +         .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
10000 +       { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
10001 +                        0x0032,
10002 +                        0x1B9A, /* XAVI */
10003 +                        0x1C01),
10004 +         .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
10005 +       { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
10006 +                        0x0032,
10007 +                        PCI_VENDOR_ID_ASUSTEK,
10008 +                        0x850D),
10009 +         .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
10010 +
10011         { PCI_VDEVICE(ATHEROS, 0x0032) }, /* PCI-E  AR9485 */
10012         { PCI_VDEVICE(ATHEROS, 0x0033) }, /* PCI-E  AR9580 */
10013
10014 --- a/drivers/net/wireless/ath/ath9k/ar9462_2p0_initvals.h
10015 +++ b/drivers/net/wireless/ath/ath9k/ar9462_2p0_initvals.h
10016 @@ -20,7 +20,15 @@
10017
10018  /* AR9462 2.0 */
10019
10020 -static const u32 ar9462_modes_fast_clock_2p0[][3] = {
10021 +#define ar9462_2p0_mac_postamble ar9331_1p1_mac_postamble
10022 +
10023 +#define ar9462_2p0_common_wo_xlna_rx_gain ar9300Common_wo_xlna_rx_gain_table_2p2
10024 +
10025 +#define ar9462_2p0_common_5g_xlna_only_rxgain ar9462_2p0_common_mixed_rx_gain
10026 +
10027 +#define ar9462_2p0_baseband_core_txfir_coeff_japan_2484 ar9300_2p2_baseband_core_txfir_coeff_japan_2484
10028 +
10029 +static const u32 ar9462_2p0_modes_fast_clock[][3] = {
10030         /* Addr      5G_HT20     5G_HT40   */
10031         {0x00001030, 0x00000268, 0x000004d0},
10032         {0x00001070, 0x0000018c, 0x00000318},
10033 @@ -33,13 +41,6 @@ static const u32 ar9462_modes_fast_clock
10034         {0x0000a254, 0x00000898, 0x00001130},
10035  };
10036
10037 -static const u32 ar9462_pciephy_clkreq_enable_L1_2p0[][2] = {
10038 -       /* Addr      allmodes  */
10039 -       {0x00018c00, 0x18253ede},
10040 -       {0x00018c04, 0x000801d8},
10041 -       {0x00018c08, 0x0003780c},
10042 -};
10043 -
10044  static const u32 ar9462_2p0_baseband_postamble[][5] = {
10045         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
10046         {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a800d},
10047 @@ -99,7 +100,7 @@ static const u32 ar9462_2p0_baseband_pos
10048         {0x0000b284, 0x00000000, 0x00000000, 0x00000550, 0x00000550},
10049  };
10050
10051 -static const u32 ar9462_common_rx_gain_table_2p0[][2] = {
10052 +static const u32 ar9462_2p0_common_rx_gain[][2] = {
10053         /* Addr      allmodes  */
10054         {0x0000a000, 0x00010000},
10055         {0x0000a004, 0x00030002},
10056 @@ -359,20 +360,13 @@ static const u32 ar9462_common_rx_gain_t
10057         {0x0000b1fc, 0x00000196},
10058  };
10059
10060 -static const u32 ar9462_pciephy_clkreq_disable_L1_2p0[][2] = {
10061 +static const u32 ar9462_2p0_pciephy_clkreq_disable_L1[][2] = {
10062         /* Addr      allmodes  */
10063         {0x00018c00, 0x18213ede},
10064         {0x00018c04, 0x000801d8},
10065         {0x00018c08, 0x0003780c},
10066  };
10067
10068 -static const u32 ar9462_pciephy_pll_on_clkreq_disable_L1_2p0[][2] = {
10069 -       /* Addr      allmodes  */
10070 -       {0x00018c00, 0x18212ede},
10071 -       {0x00018c04, 0x000801d8},
10072 -       {0x00018c08, 0x0003780c},
10073 -};
10074 -
10075  static const u32 ar9462_2p0_radio_postamble_sys2ant[][5] = {
10076         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
10077         {0x000160ac, 0xa4646c08, 0xa4646c08, 0x24645808, 0x24645808},
10078 @@ -380,348 +374,81 @@ static const u32 ar9462_2p0_radio_postam
10079         {0x00016540, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
10080  };
10081
10082 -static const u32 ar9462_common_wo_xlna_rx_gain_table_2p0[][2] = {
10083 -       /* Addr      allmodes  */
10084 -       {0x0000a000, 0x00010000},
10085 -       {0x0000a004, 0x00030002},
10086 -       {0x0000a008, 0x00050004},
10087 -       {0x0000a00c, 0x00810080},
10088 -       {0x0000a010, 0x00830082},
10089 -       {0x0000a014, 0x01810180},
10090 -       {0x0000a018, 0x01830182},
10091 -       {0x0000a01c, 0x01850184},
10092 -       {0x0000a020, 0x01890188},
10093 -       {0x0000a024, 0x018b018a},
10094 -       {0x0000a028, 0x018d018c},
10095 -       {0x0000a02c, 0x03820190},
10096 -       {0x0000a030, 0x03840383},
10097 -       {0x0000a034, 0x03880385},
10098 -       {0x0000a038, 0x038a0389},
10099 -       {0x0000a03c, 0x038c038b},
10100 -       {0x0000a040, 0x0390038d},
10101 -       {0x0000a044, 0x03920391},
10102 -       {0x0000a048, 0x03940393},
10103 -       {0x0000a04c, 0x03960395},
10104 -       {0x0000a050, 0x00000000},
10105 -       {0x0000a054, 0x00000000},
10106 -       {0x0000a058, 0x00000000},
10107 -       {0x0000a05c, 0x00000000},
10108 -       {0x0000a060, 0x00000000},
10109 -       {0x0000a064, 0x00000000},
10110 -       {0x0000a068, 0x00000000},
10111 -       {0x0000a06c, 0x00000000},
10112 -       {0x0000a070, 0x00000000},
10113 -       {0x0000a074, 0x00000000},
10114 -       {0x0000a078, 0x00000000},
10115 -       {0x0000a07c, 0x00000000},
10116 -       {0x0000a080, 0x29292929},
10117 -       {0x0000a084, 0x29292929},
10118 -       {0x0000a088, 0x29292929},
10119 -       {0x0000a08c, 0x29292929},
10120 -       {0x0000a090, 0x22292929},
10121 -       {0x0000a094, 0x1d1d2222},
10122 -       {0x0000a098, 0x0c111117},
10123 -       {0x0000a09c, 0x00030303},
10124 -       {0x0000a0a0, 0x00000000},
10125 -       {0x0000a0a4, 0x00000000},
10126 -       {0x0000a0a8, 0x00000000},
10127 -       {0x0000a0ac, 0x00000000},
10128 -       {0x0000a0b0, 0x00000000},
10129 -       {0x0000a0b4, 0x00000000},
10130 -       {0x0000a0b8, 0x00000000},
10131 -       {0x0000a0bc, 0x00000000},
10132 -       {0x0000a0c0, 0x001f0000},
10133 -       {0x0000a0c4, 0x01000101},
10134 -       {0x0000a0c8, 0x011e011f},
10135 -       {0x0000a0cc, 0x011c011d},
10136 -       {0x0000a0d0, 0x02030204},
10137 -       {0x0000a0d4, 0x02010202},
10138 -       {0x0000a0d8, 0x021f0200},
10139 -       {0x0000a0dc, 0x0302021e},
10140 -       {0x0000a0e0, 0x03000301},
10141 -       {0x0000a0e4, 0x031e031f},
10142 -       {0x0000a0e8, 0x0402031d},
10143 -       {0x0000a0ec, 0x04000401},
10144 -       {0x0000a0f0, 0x041e041f},
10145 -       {0x0000a0f4, 0x0502041d},
10146 -       {0x0000a0f8, 0x05000501},
10147 -       {0x0000a0fc, 0x051e051f},
10148 -       {0x0000a100, 0x06010602},
10149 -       {0x0000a104, 0x061f0600},
10150 -       {0x0000a108, 0x061d061e},
10151 -       {0x0000a10c, 0x07020703},
10152 -       {0x0000a110, 0x07000701},
10153 -       {0x0000a114, 0x00000000},
10154 -       {0x0000a118, 0x00000000},
10155 -       {0x0000a11c, 0x00000000},
10156 -       {0x0000a120, 0x00000000},
10157 -       {0x0000a124, 0x00000000},
10158 -       {0x0000a128, 0x00000000},
10159 -       {0x0000a12c, 0x00000000},
10160 -       {0x0000a130, 0x00000000},
10161 -       {0x0000a134, 0x00000000},
10162 -       {0x0000a138, 0x00000000},
10163 -       {0x0000a13c, 0x00000000},
10164 -       {0x0000a140, 0x001f0000},
10165 -       {0x0000a144, 0x01000101},
10166 -       {0x0000a148, 0x011e011f},
10167 -       {0x0000a14c, 0x011c011d},
10168 -       {0x0000a150, 0x02030204},
10169 -       {0x0000a154, 0x02010202},
10170 -       {0x0000a158, 0x021f0200},
10171 -       {0x0000a15c, 0x0302021e},
10172 -       {0x0000a160, 0x03000301},
10173 -       {0x0000a164, 0x031e031f},
10174 -       {0x0000a168, 0x0402031d},
10175 -       {0x0000a16c, 0x04000401},
10176 -       {0x0000a170, 0x041e041f},
10177 -       {0x0000a174, 0x0502041d},
10178 -       {0x0000a178, 0x05000501},
10179 -       {0x0000a17c, 0x051e051f},
10180 -       {0x0000a180, 0x06010602},
10181 -       {0x0000a184, 0x061f0600},
10182 -       {0x0000a188, 0x061d061e},
10183 -       {0x0000a18c, 0x07020703},
10184 -       {0x0000a190, 0x07000701},
10185 -       {0x0000a194, 0x00000000},
10186 -       {0x0000a198, 0x00000000},
10187 -       {0x0000a19c, 0x00000000},
10188 -       {0x0000a1a0, 0x00000000},
10189 -       {0x0000a1a4, 0x00000000},
10190 -       {0x0000a1a8, 0x00000000},
10191 -       {0x0000a1ac, 0x00000000},
10192 -       {0x0000a1b0, 0x00000000},
10193 -       {0x0000a1b4, 0x00000000},
10194 -       {0x0000a1b8, 0x00000000},
10195 -       {0x0000a1bc, 0x00000000},
10196 -       {0x0000a1c0, 0x00000000},
10197 -       {0x0000a1c4, 0x00000000},
10198 -       {0x0000a1c8, 0x00000000},
10199 -       {0x0000a1cc, 0x00000000},
10200 -       {0x0000a1d0, 0x00000000},
10201 -       {0x0000a1d4, 0x00000000},
10202 -       {0x0000a1d8, 0x00000000},
10203 -       {0x0000a1dc, 0x00000000},
10204 -       {0x0000a1e0, 0x00000000},
10205 -       {0x0000a1e4, 0x00000000},
10206 -       {0x0000a1e8, 0x00000000},
10207 -       {0x0000a1ec, 0x00000000},
10208 -       {0x0000a1f0, 0x00000396},
10209 -       {0x0000a1f4, 0x00000396},
10210 -       {0x0000a1f8, 0x00000396},
10211 -       {0x0000a1fc, 0x00000196},
10212 -       {0x0000b000, 0x00010000},
10213 -       {0x0000b004, 0x00030002},
10214 -       {0x0000b008, 0x00050004},
10215 -       {0x0000b00c, 0x00810080},
10216 -       {0x0000b010, 0x00830082},
10217 -       {0x0000b014, 0x01810180},
10218 -       {0x0000b018, 0x01830182},
10219 -       {0x0000b01c, 0x01850184},
10220 -       {0x0000b020, 0x02810280},
10221 -       {0x0000b024, 0x02830282},
10222 -       {0x0000b028, 0x02850284},
10223 -       {0x0000b02c, 0x02890288},
10224 -       {0x0000b030, 0x028b028a},
10225 -       {0x0000b034, 0x0388028c},
10226 -       {0x0000b038, 0x038a0389},
10227 -       {0x0000b03c, 0x038c038b},
10228 -       {0x0000b040, 0x0390038d},
10229 -       {0x0000b044, 0x03920391},
10230 -       {0x0000b048, 0x03940393},
10231 -       {0x0000b04c, 0x03960395},
10232 -       {0x0000b050, 0x00000000},
10233 -       {0x0000b054, 0x00000000},
10234 -       {0x0000b058, 0x00000000},
10235 -       {0x0000b05c, 0x00000000},
10236 -       {0x0000b060, 0x00000000},
10237 -       {0x0000b064, 0x00000000},
10238 -       {0x0000b068, 0x00000000},
10239 -       {0x0000b06c, 0x00000000},
10240 -       {0x0000b070, 0x00000000},
10241 -       {0x0000b074, 0x00000000},
10242 -       {0x0000b078, 0x00000000},
10243 -       {0x0000b07c, 0x00000000},
10244 -       {0x0000b080, 0x32323232},
10245 -       {0x0000b084, 0x2f2f3232},
10246 -       {0x0000b088, 0x23282a2d},
10247 -       {0x0000b08c, 0x1c1e2123},
10248 -       {0x0000b090, 0x14171919},
10249 -       {0x0000b094, 0x0e0e1214},
10250 -       {0x0000b098, 0x03050707},
10251 -       {0x0000b09c, 0x00030303},
10252 -       {0x0000b0a0, 0x00000000},
10253 -       {0x0000b0a4, 0x00000000},
10254 -       {0x0000b0a8, 0x00000000},
10255 -       {0x0000b0ac, 0x00000000},
10256 -       {0x0000b0b0, 0x00000000},
10257 -       {0x0000b0b4, 0x00000000},
10258 -       {0x0000b0b8, 0x00000000},
10259 -       {0x0000b0bc, 0x00000000},
10260 -       {0x0000b0c0, 0x003f0020},
10261 -       {0x0000b0c4, 0x00400041},
10262 -       {0x0000b0c8, 0x0140005f},
10263 -       {0x0000b0cc, 0x0160015f},
10264 -       {0x0000b0d0, 0x017e017f},
10265 -       {0x0000b0d4, 0x02410242},
10266 -       {0x0000b0d8, 0x025f0240},
10267 -       {0x0000b0dc, 0x027f0260},
10268 -       {0x0000b0e0, 0x0341027e},
10269 -       {0x0000b0e4, 0x035f0340},
10270 -       {0x0000b0e8, 0x037f0360},
10271 -       {0x0000b0ec, 0x04400441},
10272 -       {0x0000b0f0, 0x0460045f},
10273 -       {0x0000b0f4, 0x0541047f},
10274 -       {0x0000b0f8, 0x055f0540},
10275 -       {0x0000b0fc, 0x057f0560},
10276 -       {0x0000b100, 0x06400641},
10277 -       {0x0000b104, 0x0660065f},
10278 -       {0x0000b108, 0x067e067f},
10279 -       {0x0000b10c, 0x07410742},
10280 -       {0x0000b110, 0x075f0740},
10281 -       {0x0000b114, 0x077f0760},
10282 -       {0x0000b118, 0x07800781},
10283 -       {0x0000b11c, 0x07a0079f},
10284 -       {0x0000b120, 0x07c107bf},
10285 -       {0x0000b124, 0x000007c0},
10286 -       {0x0000b128, 0x00000000},
10287 -       {0x0000b12c, 0x00000000},
10288 -       {0x0000b130, 0x00000000},
10289 -       {0x0000b134, 0x00000000},
10290 -       {0x0000b138, 0x00000000},
10291 -       {0x0000b13c, 0x00000000},
10292 -       {0x0000b140, 0x003f0020},
10293 -       {0x0000b144, 0x00400041},
10294 -       {0x0000b148, 0x0140005f},
10295 -       {0x0000b14c, 0x0160015f},
10296 -       {0x0000b150, 0x017e017f},
10297 -       {0x0000b154, 0x02410242},
10298 -       {0x0000b158, 0x025f0240},
10299 -       {0x0000b15c, 0x027f0260},
10300 -       {0x0000b160, 0x0341027e},
10301 -       {0x0000b164, 0x035f0340},
10302 -       {0x0000b168, 0x037f0360},
10303 -       {0x0000b16c, 0x04400441},
10304 -       {0x0000b170, 0x0460045f},
10305 -       {0x0000b174, 0x0541047f},
10306 -       {0x0000b178, 0x055f0540},
10307 -       {0x0000b17c, 0x057f0560},
10308 -       {0x0000b180, 0x06400641},
10309 -       {0x0000b184, 0x0660065f},
10310 -       {0x0000b188, 0x067e067f},
10311 -       {0x0000b18c, 0x07410742},
10312 -       {0x0000b190, 0x075f0740},
10313 -       {0x0000b194, 0x077f0760},
10314 -       {0x0000b198, 0x07800781},
10315 -       {0x0000b19c, 0x07a0079f},
10316 -       {0x0000b1a0, 0x07c107bf},
10317 -       {0x0000b1a4, 0x000007c0},
10318 -       {0x0000b1a8, 0x00000000},
10319 -       {0x0000b1ac, 0x00000000},
10320 -       {0x0000b1b0, 0x00000000},
10321 -       {0x0000b1b4, 0x00000000},
10322 -       {0x0000b1b8, 0x00000000},
10323 -       {0x0000b1bc, 0x00000000},
10324 -       {0x0000b1c0, 0x00000000},
10325 -       {0x0000b1c4, 0x00000000},
10326 -       {0x0000b1c8, 0x00000000},
10327 -       {0x0000b1cc, 0x00000000},
10328 -       {0x0000b1d0, 0x00000000},
10329 -       {0x0000b1d4, 0x00000000},
10330 -       {0x0000b1d8, 0x00000000},
10331 -       {0x0000b1dc, 0x00000000},
10332 -       {0x0000b1e0, 0x00000000},
10333 -       {0x0000b1e4, 0x00000000},
10334 -       {0x0000b1e8, 0x00000000},
10335 -       {0x0000b1ec, 0x00000000},
10336 -       {0x0000b1f0, 0x00000396},
10337 -       {0x0000b1f4, 0x00000396},
10338 -       {0x0000b1f8, 0x00000396},
10339 -       {0x0000b1fc, 0x00000196},
10340 -};
10341 -
10342 -static const u32 ar9462_2p0_baseband_core_txfir_coeff_japan_2484[][2] = {
10343 -       /* Addr      allmodes  */
10344 -       {0x0000a398, 0x00000000},
10345 -       {0x0000a39c, 0x6f7f0301},
10346 -       {0x0000a3a0, 0xca9228ee},
10347 -};
10348 -
10349 -static const u32 ar9462_modes_low_ob_db_tx_gain_table_2p0[][5] = {
10350 -       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
10351 -       {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
10352 -       {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
10353 -       {0x0000a2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
10354 -       {0x0000a2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
10355 -       {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
10356 -       {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
10357 -       {0x0000a458, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
10358 -       {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
10359 -       {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
10360 -       {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004},
10361 -       {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
10362 -       {0x0000a510, 0x16000220, 0x16000220, 0x0f000202, 0x0f000202},
10363 -       {0x0000a514, 0x1c000223, 0x1c000223, 0x12000400, 0x12000400},
10364 -       {0x0000a518, 0x21020220, 0x21020220, 0x16000402, 0x16000402},
10365 -       {0x0000a51c, 0x27020223, 0x27020223, 0x19000404, 0x19000404},
10366 -       {0x0000a520, 0x2b022220, 0x2b022220, 0x1c000603, 0x1c000603},
10367 -       {0x0000a524, 0x2f022222, 0x2f022222, 0x21000a02, 0x21000a02},
10368 -       {0x0000a528, 0x34022225, 0x34022225, 0x25000a04, 0x25000a04},
10369 -       {0x0000a52c, 0x3a02222a, 0x3a02222a, 0x28000a20, 0x28000a20},
10370 -       {0x0000a530, 0x3e02222c, 0x3e02222c, 0x2c000e20, 0x2c000e20},
10371 -       {0x0000a534, 0x4202242a, 0x4202242a, 0x30000e22, 0x30000e22},
10372 -       {0x0000a538, 0x4702244a, 0x4702244a, 0x34000e24, 0x34000e24},
10373 -       {0x0000a53c, 0x4b02244c, 0x4b02244c, 0x38001640, 0x38001640},
10374 -       {0x0000a540, 0x4e02246c, 0x4e02246c, 0x3c001660, 0x3c001660},
10375 -       {0x0000a544, 0x5302266c, 0x5302266c, 0x3f001861, 0x3f001861},
10376 -       {0x0000a548, 0x5702286c, 0x5702286c, 0x43001a81, 0x43001a81},
10377 -       {0x0000a54c, 0x5c04286b, 0x5c04286b, 0x47001a83, 0x47001a83},
10378 -       {0x0000a550, 0x61042a6c, 0x61042a6c, 0x4a001c84, 0x4a001c84},
10379 -       {0x0000a554, 0x66062a6c, 0x66062a6c, 0x4e001ce3, 0x4e001ce3},
10380 -       {0x0000a558, 0x6b062e6c, 0x6b062e6c, 0x52001ce5, 0x52001ce5},
10381 -       {0x0000a55c, 0x7006308c, 0x7006308c, 0x56001ce9, 0x56001ce9},
10382 -       {0x0000a560, 0x730a308a, 0x730a308a, 0x5a001ceb, 0x5a001ceb},
10383 -       {0x0000a564, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
10384 -       {0x0000a568, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
10385 -       {0x0000a56c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
10386 -       {0x0000a570, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
10387 -       {0x0000a574, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
10388 -       {0x0000a578, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
10389 -       {0x0000a57c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
10390 -       {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
10391 -       {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
10392 -       {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
10393 -       {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
10394 -       {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
10395 -       {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000},
10396 -       {0x0000a618, 0x01404501, 0x01404501, 0x01404501, 0x01404501},
10397 -       {0x0000a61c, 0x02008802, 0x02008802, 0x02008501, 0x02008501},
10398 -       {0x0000a620, 0x0300cc03, 0x0300cc03, 0x0280ca03, 0x0280ca03},
10399 -       {0x0000a624, 0x0300cc03, 0x0300cc03, 0x03010c04, 0x03010c04},
10400 -       {0x0000a628, 0x0300cc03, 0x0300cc03, 0x04014c04, 0x04014c04},
10401 -       {0x0000a62c, 0x03810c03, 0x03810c03, 0x04015005, 0x04015005},
10402 -       {0x0000a630, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
10403 -       {0x0000a634, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
10404 -       {0x0000a638, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
10405 -       {0x0000a63c, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
10406 -       {0x0000b2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
10407 -       {0x0000b2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
10408 -       {0x0000b2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
10409 -       {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
10410 -       {0x00016044, 0x012482d4, 0x012482d4, 0x012482d4, 0x012482d4},
10411 -       {0x00016048, 0x64992060, 0x64992060, 0x64992060, 0x64992060},
10412 -       {0x00016054, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000},
10413 -       {0x00016444, 0x012482d4, 0x012482d4, 0x012482d4, 0x012482d4},
10414 -       {0x00016448, 0x64992000, 0x64992000, 0x64992000, 0x64992000},
10415 -       {0x00016454, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000},
10416 -};
10417 -
10418 -static const u32 ar9462_2p0_soc_postamble[][5] = {
10419 -       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
10420 -       {0x00007010, 0x00000033, 0x00000033, 0x00000033, 0x00000033},
10421 -};
10422 -
10423 -static const u32 ar9462_2p0_baseband_core[][2] = {
10424 +static const u32 ar9462_2p0_modes_low_ob_db_tx_gain[][5] = {
10425 +       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
10426 +       {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
10427 +       {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
10428 +       {0x0000a2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
10429 +       {0x0000a2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
10430 +       {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
10431 +       {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
10432 +       {0x0000a458, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
10433 +       {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
10434 +       {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
10435 +       {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004},
10436 +       {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
10437 +       {0x0000a510, 0x16000220, 0x16000220, 0x0f000202, 0x0f000202},
10438 +       {0x0000a514, 0x1c000223, 0x1c000223, 0x12000400, 0x12000400},
10439 +       {0x0000a518, 0x21020220, 0x21020220, 0x16000402, 0x16000402},
10440 +       {0x0000a51c, 0x27020223, 0x27020223, 0x19000404, 0x19000404},
10441 +       {0x0000a520, 0x2b022220, 0x2b022220, 0x1c000603, 0x1c000603},
10442 +       {0x0000a524, 0x2f022222, 0x2f022222, 0x21000a02, 0x21000a02},
10443 +       {0x0000a528, 0x34022225, 0x34022225, 0x25000a04, 0x25000a04},
10444 +       {0x0000a52c, 0x3a02222a, 0x3a02222a, 0x28000a20, 0x28000a20},
10445 +       {0x0000a530, 0x3e02222c, 0x3e02222c, 0x2c000e20, 0x2c000e20},
10446 +       {0x0000a534, 0x4202242a, 0x4202242a, 0x30000e22, 0x30000e22},
10447 +       {0x0000a538, 0x4702244a, 0x4702244a, 0x34000e24, 0x34000e24},
10448 +       {0x0000a53c, 0x4b02244c, 0x4b02244c, 0x38001640, 0x38001640},
10449 +       {0x0000a540, 0x4e02246c, 0x4e02246c, 0x3c001660, 0x3c001660},
10450 +       {0x0000a544, 0x5302266c, 0x5302266c, 0x3f001861, 0x3f001861},
10451 +       {0x0000a548, 0x5702286c, 0x5702286c, 0x43001a81, 0x43001a81},
10452 +       {0x0000a54c, 0x5c04286b, 0x5c04286b, 0x47001a83, 0x47001a83},
10453 +       {0x0000a550, 0x61042a6c, 0x61042a6c, 0x4a001c84, 0x4a001c84},
10454 +       {0x0000a554, 0x66062a6c, 0x66062a6c, 0x4e001ce3, 0x4e001ce3},
10455 +       {0x0000a558, 0x6b062e6c, 0x6b062e6c, 0x52001ce5, 0x52001ce5},
10456 +       {0x0000a55c, 0x7006308c, 0x7006308c, 0x56001ce9, 0x56001ce9},
10457 +       {0x0000a560, 0x730a308a, 0x730a308a, 0x5a001ceb, 0x5a001ceb},
10458 +       {0x0000a564, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
10459 +       {0x0000a568, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
10460 +       {0x0000a56c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
10461 +       {0x0000a570, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
10462 +       {0x0000a574, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
10463 +       {0x0000a578, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
10464 +       {0x0000a57c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
10465 +       {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
10466 +       {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
10467 +       {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
10468 +       {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
10469 +       {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
10470 +       {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000},
10471 +       {0x0000a618, 0x01404501, 0x01404501, 0x01404501, 0x01404501},
10472 +       {0x0000a61c, 0x02008802, 0x02008802, 0x02008501, 0x02008501},
10473 +       {0x0000a620, 0x0300cc03, 0x0300cc03, 0x0280ca03, 0x0280ca03},
10474 +       {0x0000a624, 0x0300cc03, 0x0300cc03, 0x03010c04, 0x03010c04},
10475 +       {0x0000a628, 0x0300cc03, 0x0300cc03, 0x04014c04, 0x04014c04},
10476 +       {0x0000a62c, 0x03810c03, 0x03810c03, 0x04015005, 0x04015005},
10477 +       {0x0000a630, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
10478 +       {0x0000a634, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
10479 +       {0x0000a638, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
10480 +       {0x0000a63c, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
10481 +       {0x0000b2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
10482 +       {0x0000b2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
10483 +       {0x0000b2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
10484 +       {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
10485 +       {0x00016044, 0x012482d4, 0x012482d4, 0x012482d4, 0x012482d4},
10486 +       {0x00016048, 0x64992060, 0x64992060, 0x64992060, 0x64992060},
10487 +       {0x00016054, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000},
10488 +       {0x00016444, 0x012482d4, 0x012482d4, 0x012482d4, 0x012482d4},
10489 +       {0x00016448, 0x64992000, 0x64992000, 0x64992000, 0x64992000},
10490 +       {0x00016454, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000},
10491 +};
10492 +
10493 +static const u32 ar9462_2p0_soc_postamble[][5] = {
10494 +       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
10495 +       {0x00007010, 0x00000033, 0x00000033, 0x00000033, 0x00000033},
10496 +};
10497 +
10498 +static const u32 ar9462_2p0_baseband_core[][2] = {
10499         /* Addr      allmodes  */
10500         {0x00009800, 0xafe68e30},
10501         {0x00009804, 0xfd14e000},
10502 @@ -879,7 +606,7 @@ static const u32 ar9462_2p0_radio_postam
10503         {0x0001650c, 0x48000000, 0x40000000, 0x40000000, 0x40000000},
10504  };
10505
10506 -static const u32 ar9462_modes_mix_ob_db_tx_gain_table_2p0[][5] = {
10507 +static const u32 ar9462_2p0_modes_mix_ob_db_tx_gain[][5] = {
10508         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
10509         {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
10510         {0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
10511 @@ -942,7 +669,7 @@ static const u32 ar9462_modes_mix_ob_db_
10512         {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
10513  };
10514
10515 -static const u32 ar9462_modes_high_ob_db_tx_gain_table_2p0[][5] = {
10516 +static const u32 ar9462_2p0_modes_high_ob_db_tx_gain[][5] = {
10517         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
10518         {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
10519         {0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
10520 @@ -1240,19 +967,7 @@ static const u32 ar9462_2p0_mac_core[][2
10521         {0x000083d0, 0x000301ff},
10522  };
10523
10524 -static const u32 ar9462_2p0_mac_postamble[][5] = {
10525 -       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
10526 -       {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
10527 -       {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
10528 -       {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
10529 -       {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
10530 -       {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b},
10531 -       {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
10532 -       {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
10533 -       {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
10534 -};
10535 -
10536 -static const u32 ar9462_common_mixed_rx_gain_table_2p0[][2] = {
10537 +static const u32 ar9462_2p0_common_mixed_rx_gain[][2] = {
10538         /* Addr      allmodes  */
10539         {0x0000a000, 0x00010000},
10540         {0x0000a004, 0x00030002},
10541 @@ -1517,266 +1232,6 @@ static const u32 ar9462_2p0_baseband_pos
10542         {0x00009e3c, 0xcf946220, 0xcf946220, 0xcfd5c782, 0xcfd5c282},
10543  };
10544
10545 -static const u32 ar9462_2p0_5g_xlna_only_rxgain[][2] = {
10546 -       /* Addr      allmodes  */
10547 -       {0x0000a000, 0x00010000},
10548 -       {0x0000a004, 0x00030002},
10549 -       {0x0000a008, 0x00050004},
10550 -       {0x0000a00c, 0x00810080},
10551 -       {0x0000a010, 0x00830082},
10552 -       {0x0000a014, 0x01810180},
10553 -       {0x0000a018, 0x01830182},
10554 -       {0x0000a01c, 0x01850184},
10555 -       {0x0000a020, 0x01890188},
10556 -       {0x0000a024, 0x018b018a},
10557 -       {0x0000a028, 0x018d018c},
10558 -       {0x0000a02c, 0x03820190},
10559 -       {0x0000a030, 0x03840383},
10560 -       {0x0000a034, 0x03880385},
10561 -       {0x0000a038, 0x038a0389},
10562 -       {0x0000a03c, 0x038c038b},
10563 -       {0x0000a040, 0x0390038d},
10564 -       {0x0000a044, 0x03920391},
10565 -       {0x0000a048, 0x03940393},
10566 -       {0x0000a04c, 0x03960395},
10567 -       {0x0000a050, 0x00000000},
10568 -       {0x0000a054, 0x00000000},
10569 -       {0x0000a058, 0x00000000},
10570 -       {0x0000a05c, 0x00000000},
10571 -       {0x0000a060, 0x00000000},
10572 -       {0x0000a064, 0x00000000},
10573 -       {0x0000a068, 0x00000000},
10574 -       {0x0000a06c, 0x00000000},
10575 -       {0x0000a070, 0x00000000},
10576 -       {0x0000a074, 0x00000000},
10577 -       {0x0000a078, 0x00000000},
10578 -       {0x0000a07c, 0x00000000},
10579 -       {0x0000a080, 0x29292929},
10580 -       {0x0000a084, 0x29292929},
10581 -       {0x0000a088, 0x29292929},
10582 -       {0x0000a08c, 0x29292929},
10583 -       {0x0000a090, 0x22292929},
10584 -       {0x0000a094, 0x1d1d2222},
10585 -       {0x0000a098, 0x0c111117},
10586 -       {0x0000a09c, 0x00030303},
10587 -       {0x0000a0a0, 0x00000000},
10588 -       {0x0000a0a4, 0x00000000},
10589 -       {0x0000a0a8, 0x00000000},
10590 -       {0x0000a0ac, 0x00000000},
10591 -       {0x0000a0b0, 0x00000000},
10592 -       {0x0000a0b4, 0x00000000},
10593 -       {0x0000a0b8, 0x00000000},
10594 -       {0x0000a0bc, 0x00000000},
10595 -       {0x0000a0c0, 0x001f0000},
10596 -       {0x0000a0c4, 0x01000101},
10597 -       {0x0000a0c8, 0x011e011f},
10598 -       {0x0000a0cc, 0x011c011d},
10599 -       {0x0000a0d0, 0x02030204},
10600 -       {0x0000a0d4, 0x02010202},
10601 -       {0x0000a0d8, 0x021f0200},
10602 -       {0x0000a0dc, 0x0302021e},
10603 -       {0x0000a0e0, 0x03000301},
10604 -       {0x0000a0e4, 0x031e031f},
10605 -       {0x0000a0e8, 0x0402031d},
10606 -       {0x0000a0ec, 0x04000401},
10607 -       {0x0000a0f0, 0x041e041f},
10608 -       {0x0000a0f4, 0x0502041d},
10609 -       {0x0000a0f8, 0x05000501},
10610 -       {0x0000a0fc, 0x051e051f},
10611 -       {0x0000a100, 0x06010602},
10612 -       {0x0000a104, 0x061f0600},
10613 -       {0x0000a108, 0x061d061e},
10614 -       {0x0000a10c, 0x07020703},
10615 -       {0x0000a110, 0x07000701},
10616 -       {0x0000a114, 0x00000000},
10617 -       {0x0000a118, 0x00000000},
10618 -       {0x0000a11c, 0x00000000},
10619 -       {0x0000a120, 0x00000000},
10620 -       {0x0000a124, 0x00000000},
10621 -       {0x0000a128, 0x00000000},
10622 -       {0x0000a12c, 0x00000000},
10623 -       {0x0000a130, 0x00000000},
10624 -       {0x0000a134, 0x00000000},
10625 -       {0x0000a138, 0x00000000},
10626 -       {0x0000a13c, 0x00000000},
10627 -       {0x0000a140, 0x001f0000},
10628 -       {0x0000a144, 0x01000101},
10629 -       {0x0000a148, 0x011e011f},
10630 -       {0x0000a14c, 0x011c011d},
10631 -       {0x0000a150, 0x02030204},
10632 -       {0x0000a154, 0x02010202},
10633 -       {0x0000a158, 0x021f0200},
10634 -       {0x0000a15c, 0x0302021e},
10635 -       {0x0000a160, 0x03000301},
10636 -       {0x0000a164, 0x031e031f},
10637 -       {0x0000a168, 0x0402031d},
10638 -       {0x0000a16c, 0x04000401},
10639 -       {0x0000a170, 0x041e041f},
10640 -       {0x0000a174, 0x0502041d},
10641 -       {0x0000a178, 0x05000501},
10642 -       {0x0000a17c, 0x051e051f},
10643 -       {0x0000a180, 0x06010602},
10644 -       {0x0000a184, 0x061f0600},
10645 -       {0x0000a188, 0x061d061e},
10646 -       {0x0000a18c, 0x07020703},
10647 -       {0x0000a190, 0x07000701},
10648 -       {0x0000a194, 0x00000000},
10649 -       {0x0000a198, 0x00000000},
10650 -       {0x0000a19c, 0x00000000},
10651 -       {0x0000a1a0, 0x00000000},
10652 -       {0x0000a1a4, 0x00000000},
10653 -       {0x0000a1a8, 0x00000000},
10654 -       {0x0000a1ac, 0x00000000},
10655 -       {0x0000a1b0, 0x00000000},
10656 -       {0x0000a1b4, 0x00000000},
10657 -       {0x0000a1b8, 0x00000000},
10658 -       {0x0000a1bc, 0x00000000},
10659 -       {0x0000a1c0, 0x00000000},
10660 -       {0x0000a1c4, 0x00000000},
10661 -       {0x0000a1c8, 0x00000000},
10662 -       {0x0000a1cc, 0x00000000},
10663 -       {0x0000a1d0, 0x00000000},
10664 -       {0x0000a1d4, 0x00000000},
10665 -       {0x0000a1d8, 0x00000000},
10666 -       {0x0000a1dc, 0x00000000},
10667 -       {0x0000a1e0, 0x00000000},
10668 -       {0x0000a1e4, 0x00000000},
10669 -       {0x0000a1e8, 0x00000000},
10670 -       {0x0000a1ec, 0x00000000},
10671 -       {0x0000a1f0, 0x00000396},
10672 -       {0x0000a1f4, 0x00000396},
10673 -       {0x0000a1f8, 0x00000396},
10674 -       {0x0000a1fc, 0x00000196},
10675 -       {0x0000b000, 0x00010000},
10676 -       {0x0000b004, 0x00030002},
10677 -       {0x0000b008, 0x00050004},
10678 -       {0x0000b00c, 0x00810080},
10679 -       {0x0000b010, 0x00830082},
10680 -       {0x0000b014, 0x01810180},
10681 -       {0x0000b018, 0x01830182},
10682 -       {0x0000b01c, 0x01850184},
10683 -       {0x0000b020, 0x02810280},
10684 -       {0x0000b024, 0x02830282},
10685 -       {0x0000b028, 0x02850284},
10686 -       {0x0000b02c, 0x02890288},
10687 -       {0x0000b030, 0x028b028a},
10688 -       {0x0000b034, 0x0388028c},
10689 -       {0x0000b038, 0x038a0389},
10690 -       {0x0000b03c, 0x038c038b},
10691 -       {0x0000b040, 0x0390038d},
10692 -       {0x0000b044, 0x03920391},
10693 -       {0x0000b048, 0x03940393},
10694 -       {0x0000b04c, 0x03960395},
10695 -       {0x0000b050, 0x00000000},
10696 -       {0x0000b054, 0x00000000},
10697 -       {0x0000b058, 0x00000000},
10698 -       {0x0000b05c, 0x00000000},
10699 -       {0x0000b060, 0x00000000},
10700 -       {0x0000b064, 0x00000000},
10701 -       {0x0000b068, 0x00000000},
10702 -       {0x0000b06c, 0x00000000},
10703 -       {0x0000b070, 0x00000000},
10704 -       {0x0000b074, 0x00000000},
10705 -       {0x0000b078, 0x00000000},
10706 -       {0x0000b07c, 0x00000000},
10707 -       {0x0000b080, 0x2a2d2f32},
10708 -       {0x0000b084, 0x21232328},
10709 -       {0x0000b088, 0x19191c1e},
10710 -       {0x0000b08c, 0x12141417},
10711 -       {0x0000b090, 0x07070e0e},
10712 -       {0x0000b094, 0x03030305},
10713 -       {0x0000b098, 0x00000003},
10714 -       {0x0000b09c, 0x00000000},
10715 -       {0x0000b0a0, 0x00000000},
10716 -       {0x0000b0a4, 0x00000000},
10717 -       {0x0000b0a8, 0x00000000},
10718 -       {0x0000b0ac, 0x00000000},
10719 -       {0x0000b0b0, 0x00000000},
10720 -       {0x0000b0b4, 0x00000000},
10721 -       {0x0000b0b8, 0x00000000},
10722 -       {0x0000b0bc, 0x00000000},
10723 -       {0x0000b0c0, 0x003f0020},
10724 -       {0x0000b0c4, 0x00400041},
10725 -       {0x0000b0c8, 0x0140005f},
10726 -       {0x0000b0cc, 0x0160015f},
10727 -       {0x0000b0d0, 0x017e017f},
10728 -       {0x0000b0d4, 0x02410242},
10729 -       {0x0000b0d8, 0x025f0240},
10730 -       {0x0000b0dc, 0x027f0260},
10731 -       {0x0000b0e0, 0x0341027e},
10732 -       {0x0000b0e4, 0x035f0340},
10733 -       {0x0000b0e8, 0x037f0360},
10734 -       {0x0000b0ec, 0x04400441},
10735 -       {0x0000b0f0, 0x0460045f},
10736 -       {0x0000b0f4, 0x0541047f},
10737 -       {0x0000b0f8, 0x055f0540},
10738 -       {0x0000b0fc, 0x057f0560},
10739 -       {0x0000b100, 0x06400641},
10740 -       {0x0000b104, 0x0660065f},
10741 -       {0x0000b108, 0x067e067f},
10742 -       {0x0000b10c, 0x07410742},
10743 -       {0x0000b110, 0x075f0740},
10744 -       {0x0000b114, 0x077f0760},
10745 -       {0x0000b118, 0x07800781},
10746 -       {0x0000b11c, 0x07a0079f},
10747 -       {0x0000b120, 0x07c107bf},
10748 -       {0x0000b124, 0x000007c0},
10749 -       {0x0000b128, 0x00000000},
10750 -       {0x0000b12c, 0x00000000},
10751 -       {0x0000b130, 0x00000000},
10752 -       {0x0000b134, 0x00000000},
10753 -       {0x0000b138, 0x00000000},
10754 -       {0x0000b13c, 0x00000000},
10755 -       {0x0000b140, 0x003f0020},
10756 -       {0x0000b144, 0x00400041},
10757 -       {0x0000b148, 0x0140005f},
10758 -       {0x0000b14c, 0x0160015f},
10759 -       {0x0000b150, 0x017e017f},
10760 -       {0x0000b154, 0x02410242},
10761 -       {0x0000b158, 0x025f0240},
10762 -       {0x0000b15c, 0x027f0260},
10763 -       {0x0000b160, 0x0341027e},
10764 -       {0x0000b164, 0x035f0340},
10765 -       {0x0000b168, 0x037f0360},
10766 -       {0x0000b16c, 0x04400441},
10767 -       {0x0000b170, 0x0460045f},
10768 -       {0x0000b174, 0x0541047f},
10769 -       {0x0000b178, 0x055f0540},
10770 -       {0x0000b17c, 0x057f0560},
10771 -       {0x0000b180, 0x06400641},
10772 -       {0x0000b184, 0x0660065f},
10773 -       {0x0000b188, 0x067e067f},
10774 -       {0x0000b18c, 0x07410742},
10775 -       {0x0000b190, 0x075f0740},
10776 -       {0x0000b194, 0x077f0760},
10777 -       {0x0000b198, 0x07800781},
10778 -       {0x0000b19c, 0x07a0079f},
10779 -       {0x0000b1a0, 0x07c107bf},
10780 -       {0x0000b1a4, 0x000007c0},
10781 -       {0x0000b1a8, 0x00000000},
10782 -       {0x0000b1ac, 0x00000000},
10783 -       {0x0000b1b0, 0x00000000},
10784 -       {0x0000b1b4, 0x00000000},
10785 -       {0x0000b1b8, 0x00000000},
10786 -       {0x0000b1bc, 0x00000000},
10787 -       {0x0000b1c0, 0x00000000},
10788 -       {0x0000b1c4, 0x00000000},
10789 -       {0x0000b1c8, 0x00000000},
10790 -       {0x0000b1cc, 0x00000000},
10791 -       {0x0000b1d0, 0x00000000},
10792 -       {0x0000b1d4, 0x00000000},
10793 -       {0x0000b1d8, 0x00000000},
10794 -       {0x0000b1dc, 0x00000000},
10795 -       {0x0000b1e0, 0x00000000},
10796 -       {0x0000b1e4, 0x00000000},
10797 -       {0x0000b1e8, 0x00000000},
10798 -       {0x0000b1ec, 0x00000000},
10799 -       {0x0000b1f0, 0x00000396},
10800 -       {0x0000b1f4, 0x00000396},
10801 -       {0x0000b1f8, 0x00000396},
10802 -       {0x0000b1fc, 0x00000196},
10803 -};
10804 -
10805  static const u32 ar9462_2p0_baseband_core_mix_rxgain[][2] = {
10806         /* Addr      allmodes  */
10807         {0x00009fd0, 0x0a2d6b93},
10808 --- a/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
10809 +++ b/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
10810 @@ -303,7 +303,7 @@ static const u32 ar9300_2p2_mac_postambl
10811         {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
10812         {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
10813         {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b},
10814 -       {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
10815 +       {0x00008120, 0x18f04800, 0x18f04800, 0x18f04810, 0x18f04810},
10816         {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
10817         {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
10818  };
10819 @@ -352,7 +352,7 @@ static const u32 ar9300_2p2_baseband_pos
10820         {0x0000a288, 0x00000110, 0x00000110, 0x00000110, 0x00000110},
10821         {0x0000a28c, 0x00022222, 0x00022222, 0x00022222, 0x00022222},
10822         {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
10823 -       {0x0000a2d0, 0x00041981, 0x00041981, 0x00041981, 0x00041982},
10824 +       {0x0000a2d0, 0x00041983, 0x00041983, 0x00041981, 0x00041982},
10825         {0x0000a2d8, 0x7999a83b, 0x7999a83b, 0x7999a83b, 0x7999a83b},
10826         {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
10827         {0x0000a830, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
10828 @@ -378,9 +378,9 @@ static const u32 ar9300_2p2_baseband_cor
10829         {0x00009814, 0x9280c00a},
10830         {0x00009818, 0x00000000},
10831         {0x0000981c, 0x00020028},
10832 -       {0x00009834, 0x6400a290},
10833 +       {0x00009834, 0x6400a190},
10834         {0x00009838, 0x0108ecff},
10835 -       {0x0000983c, 0x0d000600},
10836 +       {0x0000983c, 0x14000600},
10837         {0x00009880, 0x201fff00},
10838         {0x00009884, 0x00001042},
10839         {0x000098a4, 0x00200400},
10840 @@ -401,7 +401,7 @@ static const u32 ar9300_2p2_baseband_cor
10841         {0x00009d04, 0x40206c10},
10842         {0x00009d08, 0x009c4060},
10843         {0x00009d0c, 0x9883800a},
10844 -       {0x00009d10, 0x01834061},
10845 +       {0x00009d10, 0x01884061},
10846         {0x00009d14, 0x00c0040b},
10847         {0x00009d18, 0x00000000},
10848         {0x00009e08, 0x0038230c},
10849 @@ -459,7 +459,7 @@ static const u32 ar9300_2p2_baseband_cor
10850         {0x0000a3e8, 0x20202020},
10851         {0x0000a3ec, 0x20202020},
10852         {0x0000a3f0, 0x00000000},
10853 -       {0x0000a3f4, 0x00000246},
10854 +       {0x0000a3f4, 0x00000000},
10855         {0x0000a3f8, 0x0c9bd380},
10856         {0x0000a3fc, 0x000f0f01},
10857         {0x0000a400, 0x8fa91f01},
10858 @@ -534,107 +534,107 @@ static const u32 ar9300_2p2_baseband_cor
10859
10860  static const u32 ar9300Modes_high_power_tx_gain_table_2p2[][5] = {
10861         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
10862 -       {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
10863 -       {0x0000a2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
10864 -       {0x0000a2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
10865 +       {0x0000a2dc, 0x000cfff0, 0x000cfff0, 0x03aaa352, 0x03aaa352},
10866 +       {0x0000a2e0, 0x000f0000, 0x000f0000, 0x03ccc584, 0x03ccc584},
10867 +       {0x0000a2e4, 0x03f00000, 0x03f00000, 0x03f0f800, 0x03f0f800},
10868         {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
10869 -       {0x0000a410, 0x000050d8, 0x000050d8, 0x000050d9, 0x000050d9},
10870 -       {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000},
10871 -       {0x0000a504, 0x04002222, 0x04002222, 0x04000002, 0x04000002},
10872 -       {0x0000a508, 0x09002421, 0x09002421, 0x08000004, 0x08000004},
10873 -       {0x0000a50c, 0x0d002621, 0x0d002621, 0x0b000200, 0x0b000200},
10874 -       {0x0000a510, 0x13004620, 0x13004620, 0x0f000202, 0x0f000202},
10875 -       {0x0000a514, 0x19004a20, 0x19004a20, 0x11000400, 0x11000400},
10876 -       {0x0000a518, 0x1d004e20, 0x1d004e20, 0x15000402, 0x15000402},
10877 -       {0x0000a51c, 0x21005420, 0x21005420, 0x19000404, 0x19000404},
10878 -       {0x0000a520, 0x26005e20, 0x26005e20, 0x1b000603, 0x1b000603},
10879 -       {0x0000a524, 0x2b005e40, 0x2b005e40, 0x1f000a02, 0x1f000a02},
10880 -       {0x0000a528, 0x2f005e42, 0x2f005e42, 0x23000a04, 0x23000a04},
10881 -       {0x0000a52c, 0x33005e44, 0x33005e44, 0x26000a20, 0x26000a20},
10882 -       {0x0000a530, 0x38005e65, 0x38005e65, 0x2a000e20, 0x2a000e20},
10883 -       {0x0000a534, 0x3c005e69, 0x3c005e69, 0x2e000e22, 0x2e000e22},
10884 -       {0x0000a538, 0x40005e6b, 0x40005e6b, 0x31000e24, 0x31000e24},
10885 -       {0x0000a53c, 0x44005e6d, 0x44005e6d, 0x34001640, 0x34001640},
10886 -       {0x0000a540, 0x49005e72, 0x49005e72, 0x38001660, 0x38001660},
10887 -       {0x0000a544, 0x4e005eb2, 0x4e005eb2, 0x3b001861, 0x3b001861},
10888 -       {0x0000a548, 0x53005f12, 0x53005f12, 0x3e001a81, 0x3e001a81},
10889 -       {0x0000a54c, 0x59025eb2, 0x59025eb2, 0x42001a83, 0x42001a83},
10890 -       {0x0000a550, 0x5e025f12, 0x5e025f12, 0x44001c84, 0x44001c84},
10891 -       {0x0000a554, 0x61027f12, 0x61027f12, 0x48001ce3, 0x48001ce3},
10892 -       {0x0000a558, 0x6702bf12, 0x6702bf12, 0x4c001ce5, 0x4c001ce5},
10893 -       {0x0000a55c, 0x6b02bf14, 0x6b02bf14, 0x50001ce9, 0x50001ce9},
10894 -       {0x0000a560, 0x6f02bf16, 0x6f02bf16, 0x54001ceb, 0x54001ceb},
10895 -       {0x0000a564, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
10896 -       {0x0000a568, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
10897 -       {0x0000a56c, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
10898 -       {0x0000a570, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
10899 -       {0x0000a574, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
10900 -       {0x0000a578, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
10901 -       {0x0000a57c, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
10902 -       {0x0000a580, 0x00802220, 0x00802220, 0x00800000, 0x00800000},
10903 -       {0x0000a584, 0x04802222, 0x04802222, 0x04800002, 0x04800002},
10904 -       {0x0000a588, 0x09802421, 0x09802421, 0x08800004, 0x08800004},
10905 -       {0x0000a58c, 0x0d802621, 0x0d802621, 0x0b800200, 0x0b800200},
10906 -       {0x0000a590, 0x13804620, 0x13804620, 0x0f800202, 0x0f800202},
10907 -       {0x0000a594, 0x19804a20, 0x19804a20, 0x11800400, 0x11800400},
10908 -       {0x0000a598, 0x1d804e20, 0x1d804e20, 0x15800402, 0x15800402},
10909 -       {0x0000a59c, 0x21805420, 0x21805420, 0x19800404, 0x19800404},
10910 -       {0x0000a5a0, 0x26805e20, 0x26805e20, 0x1b800603, 0x1b800603},
10911 -       {0x0000a5a4, 0x2b805e40, 0x2b805e40, 0x1f800a02, 0x1f800a02},
10912 -       {0x0000a5a8, 0x2f805e42, 0x2f805e42, 0x23800a04, 0x23800a04},
10913 -       {0x0000a5ac, 0x33805e44, 0x33805e44, 0x26800a20, 0x26800a20},
10914 -       {0x0000a5b0, 0x38805e65, 0x38805e65, 0x2a800e20, 0x2a800e20},
10915 -       {0x0000a5b4, 0x3c805e69, 0x3c805e69, 0x2e800e22, 0x2e800e22},
10916 -       {0x0000a5b8, 0x40805e6b, 0x40805e6b, 0x31800e24, 0x31800e24},
10917 -       {0x0000a5bc, 0x44805e6d, 0x44805e6d, 0x34801640, 0x34801640},
10918 -       {0x0000a5c0, 0x49805e72, 0x49805e72, 0x38801660, 0x38801660},
10919 -       {0x0000a5c4, 0x4e805eb2, 0x4e805eb2, 0x3b801861, 0x3b801861},
10920 -       {0x0000a5c8, 0x53805f12, 0x53805f12, 0x3e801a81, 0x3e801a81},
10921 -       {0x0000a5cc, 0x59825eb2, 0x59825eb2, 0x42801a83, 0x42801a83},
10922 -       {0x0000a5d0, 0x5e825f12, 0x5e825f12, 0x44801c84, 0x44801c84},
10923 -       {0x0000a5d4, 0x61827f12, 0x61827f12, 0x48801ce3, 0x48801ce3},
10924 -       {0x0000a5d8, 0x6782bf12, 0x6782bf12, 0x4c801ce5, 0x4c801ce5},
10925 -       {0x0000a5dc, 0x6b82bf14, 0x6b82bf14, 0x50801ce9, 0x50801ce9},
10926 -       {0x0000a5e0, 0x6f82bf16, 0x6f82bf16, 0x54801ceb, 0x54801ceb},
10927 -       {0x0000a5e4, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
10928 -       {0x0000a5e8, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
10929 -       {0x0000a5ec, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
10930 -       {0x0000a5f0, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
10931 -       {0x0000a5f4, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
10932 -       {0x0000a5f8, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
10933 -       {0x0000a5fc, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
10934 +       {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
10935 +       {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
10936 +       {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
10937 +       {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004},
10938 +       {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
10939 +       {0x0000a510, 0x15000028, 0x15000028, 0x0f000202, 0x0f000202},
10940 +       {0x0000a514, 0x1b00002b, 0x1b00002b, 0x12000400, 0x12000400},
10941 +       {0x0000a518, 0x1f020028, 0x1f020028, 0x16000402, 0x16000402},
10942 +       {0x0000a51c, 0x2502002b, 0x2502002b, 0x19000404, 0x19000404},
10943 +       {0x0000a520, 0x2a04002a, 0x2a04002a, 0x1c000603, 0x1c000603},
10944 +       {0x0000a524, 0x2e06002a, 0x2e06002a, 0x21000a02, 0x21000a02},
10945 +       {0x0000a528, 0x3302202d, 0x3302202d, 0x25000a04, 0x25000a04},
10946 +       {0x0000a52c, 0x3804202c, 0x3804202c, 0x28000a20, 0x28000a20},
10947 +       {0x0000a530, 0x3c06202c, 0x3c06202c, 0x2c000e20, 0x2c000e20},
10948 +       {0x0000a534, 0x4108202d, 0x4108202d, 0x30000e22, 0x30000e22},
10949 +       {0x0000a538, 0x4506402d, 0x4506402d, 0x34000e24, 0x34000e24},
10950 +       {0x0000a53c, 0x4906222d, 0x4906222d, 0x38001640, 0x38001640},
10951 +       {0x0000a540, 0x4d062231, 0x4d062231, 0x3c001660, 0x3c001660},
10952 +       {0x0000a544, 0x50082231, 0x50082231, 0x3f001861, 0x3f001861},
10953 +       {0x0000a548, 0x5608422e, 0x5608422e, 0x43001a81, 0x43001a81},
10954 +       {0x0000a54c, 0x5e08442e, 0x5e08442e, 0x47001a83, 0x47001a83},
10955 +       {0x0000a550, 0x620a4431, 0x620a4431, 0x4a001c84, 0x4a001c84},
10956 +       {0x0000a554, 0x640a4432, 0x640a4432, 0x4e001ce3, 0x4e001ce3},
10957 +       {0x0000a558, 0x680a4434, 0x680a4434, 0x52001ce5, 0x52001ce5},
10958 +       {0x0000a55c, 0x6c0a6434, 0x6c0a6434, 0x56001ce9, 0x56001ce9},
10959 +       {0x0000a560, 0x6f0a6633, 0x6f0a6633, 0x5a001ceb, 0x5a001ceb},
10960 +       {0x0000a564, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
10961 +       {0x0000a568, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
10962 +       {0x0000a56c, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
10963 +       {0x0000a570, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
10964 +       {0x0000a574, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
10965 +       {0x0000a578, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
10966 +       {0x0000a57c, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
10967 +       {0x0000a580, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
10968 +       {0x0000a584, 0x06800003, 0x06800003, 0x04800002, 0x04800002},
10969 +       {0x0000a588, 0x0a800020, 0x0a800020, 0x08800004, 0x08800004},
10970 +       {0x0000a58c, 0x10800023, 0x10800023, 0x0b800200, 0x0b800200},
10971 +       {0x0000a590, 0x15800028, 0x15800028, 0x0f800202, 0x0f800202},
10972 +       {0x0000a594, 0x1b80002b, 0x1b80002b, 0x12800400, 0x12800400},
10973 +       {0x0000a598, 0x1f820028, 0x1f820028, 0x16800402, 0x16800402},
10974 +       {0x0000a59c, 0x2582002b, 0x2582002b, 0x19800404, 0x19800404},
10975 +       {0x0000a5a0, 0x2a84002a, 0x2a84002a, 0x1c800603, 0x1c800603},
10976 +       {0x0000a5a4, 0x2e86002a, 0x2e86002a, 0x21800a02, 0x21800a02},
10977 +       {0x0000a5a8, 0x3382202d, 0x3382202d, 0x25800a04, 0x25800a04},
10978 +       {0x0000a5ac, 0x3884202c, 0x3884202c, 0x28800a20, 0x28800a20},
10979 +       {0x0000a5b0, 0x3c86202c, 0x3c86202c, 0x2c800e20, 0x2c800e20},
10980 +       {0x0000a5b4, 0x4188202d, 0x4188202d, 0x30800e22, 0x30800e22},
10981 +       {0x0000a5b8, 0x4586402d, 0x4586402d, 0x34800e24, 0x34800e24},
10982 +       {0x0000a5bc, 0x4986222d, 0x4986222d, 0x38801640, 0x38801640},
10983 +       {0x0000a5c0, 0x4d862231, 0x4d862231, 0x3c801660, 0x3c801660},
10984 +       {0x0000a5c4, 0x50882231, 0x50882231, 0x3f801861, 0x3f801861},
10985 +       {0x0000a5c8, 0x5688422e, 0x5688422e, 0x43801a81, 0x43801a81},
10986 +       {0x0000a5cc, 0x5e88442e, 0x5e88442e, 0x47801a83, 0x47801a83},
10987 +       {0x0000a5d0, 0x628a4431, 0x628a4431, 0x4a801c84, 0x4a801c84},
10988 +       {0x0000a5d4, 0x648a4432, 0x648a4432, 0x4e801ce3, 0x4e801ce3},
10989 +       {0x0000a5d8, 0x688a4434, 0x688a4434, 0x52801ce5, 0x52801ce5},
10990 +       {0x0000a5dc, 0x6c8a6434, 0x6c8a6434, 0x56801ce9, 0x56801ce9},
10991 +       {0x0000a5e0, 0x6f8a6633, 0x6f8a6633, 0x5a801ceb, 0x5a801ceb},
10992 +       {0x0000a5e4, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
10993 +       {0x0000a5e8, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
10994 +       {0x0000a5ec, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
10995 +       {0x0000a5f0, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
10996 +       {0x0000a5f4, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
10997 +       {0x0000a5f8, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
10998 +       {0x0000a5fc, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
10999         {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
11000         {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
11001 -       {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
11002 -       {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
11003 -       {0x0000a610, 0x00804000, 0x00804000, 0x00000000, 0x00000000},
11004 -       {0x0000a614, 0x00804201, 0x00804201, 0x01404000, 0x01404000},
11005 -       {0x0000a618, 0x0280c802, 0x0280c802, 0x01404501, 0x01404501},
11006 -       {0x0000a61c, 0x0280ca03, 0x0280ca03, 0x02008501, 0x02008501},
11007 -       {0x0000a620, 0x04c15104, 0x04c15104, 0x0280ca03, 0x0280ca03},
11008 -       {0x0000a624, 0x04c15305, 0x04c15305, 0x03010c04, 0x03010c04},
11009 -       {0x0000a628, 0x04c15305, 0x04c15305, 0x04014c04, 0x04014c04},
11010 -       {0x0000a62c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
11011 -       {0x0000a630, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
11012 -       {0x0000a634, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
11013 -       {0x0000a638, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
11014 -       {0x0000a63c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
11015 -       {0x0000b2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
11016 -       {0x0000b2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
11017 -       {0x0000b2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
11018 +       {0x0000a608, 0x01804601, 0x01804601, 0x00000000, 0x00000000},
11019 +       {0x0000a60c, 0x01804601, 0x01804601, 0x00000000, 0x00000000},
11020 +       {0x0000a610, 0x01804601, 0x01804601, 0x00000000, 0x00000000},
11021 +       {0x0000a614, 0x01804601, 0x01804601, 0x01404000, 0x01404000},
11022 +       {0x0000a618, 0x01804601, 0x01804601, 0x01404501, 0x01404501},
11023 +       {0x0000a61c, 0x01804601, 0x01804601, 0x02008501, 0x02008501},
11024 +       {0x0000a620, 0x03408d02, 0x03408d02, 0x0280ca03, 0x0280ca03},
11025 +       {0x0000a624, 0x0300cc03, 0x0300cc03, 0x03010c04, 0x03010c04},
11026 +       {0x0000a628, 0x03410d04, 0x03410d04, 0x04014c04, 0x04014c04},
11027 +       {0x0000a62c, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
11028 +       {0x0000a630, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
11029 +       {0x0000a634, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
11030 +       {0x0000a638, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
11031 +       {0x0000a63c, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
11032 +       {0x0000b2dc, 0x000cfff0, 0x000cfff0, 0x03aaa352, 0x03aaa352},
11033 +       {0x0000b2e0, 0x000f0000, 0x000f0000, 0x03ccc584, 0x03ccc584},
11034 +       {0x0000b2e4, 0x03f00000, 0x03f00000, 0x03f0f800, 0x03f0f800},
11035         {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
11036 -       {0x0000c2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
11037 -       {0x0000c2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
11038 -       {0x0000c2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
11039 +       {0x0000c2dc, 0x000cfff0, 0x000cfff0, 0x03aaa352, 0x03aaa352},
11040 +       {0x0000c2e0, 0x000f0000, 0x000f0000, 0x03ccc584, 0x03ccc584},
11041 +       {0x0000c2e4, 0x03f00000, 0x03f00000, 0x03f0f800, 0x03f0f800},
11042         {0x0000c2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
11043         {0x00016044, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
11044 -       {0x00016048, 0x66480001, 0x66480001, 0x66480001, 0x66480001},
11045 +       {0x00016048, 0x61200001, 0x61200001, 0x66480001, 0x66480001},
11046         {0x00016068, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
11047         {0x00016444, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
11048 -       {0x00016448, 0x66480001, 0x66480001, 0x66480001, 0x66480001},
11049 +       {0x00016448, 0x61200001, 0x61200001, 0x66480001, 0x66480001},
11050         {0x00016468, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
11051         {0x00016844, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
11052 -       {0x00016848, 0x66480001, 0x66480001, 0x66480001, 0x66480001},
11053 +       {0x00016848, 0x61200001, 0x61200001, 0x66480001, 0x66480001},
11054         {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
11055  };
11056
11057 @@ -644,7 +644,7 @@ static const u32 ar9300Modes_high_ob_db_
11058         {0x0000a2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584},
11059         {0x0000a2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800},
11060         {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
11061 -       {0x0000a410, 0x000050d8, 0x000050d8, 0x000050d9, 0x000050d9},
11062 +       {0x0000a410, 0x000050d4, 0x000050d4, 0x000050d9, 0x000050d9},
11063         {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000},
11064         {0x0000a504, 0x04002222, 0x04002222, 0x04000002, 0x04000002},
11065         {0x0000a508, 0x09002421, 0x09002421, 0x08000004, 0x08000004},
11066 @@ -1086,8 +1086,8 @@ static const u32 ar9300Common_rx_gain_ta
11067         {0x0000b074, 0x00000000},
11068         {0x0000b078, 0x00000000},
11069         {0x0000b07c, 0x00000000},
11070 -       {0x0000b080, 0x2a2d2f32},
11071 -       {0x0000b084, 0x21232328},
11072 +       {0x0000b080, 0x23232323},
11073 +       {0x0000b084, 0x21232323},
11074         {0x0000b088, 0x19191c1e},
11075         {0x0000b08c, 0x12141417},
11076         {0x0000b090, 0x07070e0e},
11077 @@ -1385,9 +1385,9 @@ static const u32 ar9300_2p2_mac_core[][2
11078         {0x000081f8, 0x00000000},
11079         {0x000081fc, 0x00000000},
11080         {0x00008240, 0x00100000},
11081 -       {0x00008244, 0x0010f424},
11082 +       {0x00008244, 0x0010f400},
11083         {0x00008248, 0x00000800},
11084 -       {0x0000824c, 0x0001e848},
11085 +       {0x0000824c, 0x0001e800},
11086         {0x00008250, 0x00000000},
11087         {0x00008254, 0x00000000},
11088         {0x00008258, 0x00000000},
11089 @@ -1726,16 +1726,30 @@ static const u32 ar9300PciePhy_pll_on_cl
11090
11091  static const u32 ar9300PciePhy_clkreq_enable_L1_2p2[][2] = {
11092         /* Addr      allmodes  */
11093 -       {0x00004040, 0x08253e5e},
11094 +       {0x00004040, 0x0825365e},
11095         {0x00004040, 0x0008003b},
11096         {0x00004044, 0x00000000},
11097  };
11098
11099  static const u32 ar9300PciePhy_clkreq_disable_L1_2p2[][2] = {
11100         /* Addr      allmodes  */
11101 -       {0x00004040, 0x08213e5e},
11102 +       {0x00004040, 0x0821365e},
11103         {0x00004040, 0x0008003b},
11104         {0x00004044, 0x00000000},
11105  };
11106
11107 +static const u32 ar9300_2p2_baseband_core_txfir_coeff_japan_2484[][2] = {
11108 +       /* Addr      allmodes  */
11109 +       {0x0000a398, 0x00000000},
11110 +       {0x0000a39c, 0x6f7f0301},
11111 +       {0x0000a3a0, 0xca9228ee},
11112 +};
11113 +
11114 +static const u32 ar9300_2p2_baseband_postamble_dfs_channel[][3] = {
11115 +       /* Addr      5G          2G        */
11116 +       {0x00009824, 0x5ac668d0, 0x5ac668d0},
11117 +       {0x00009e0c, 0x6d4000e2, 0x6d4000e2},
11118 +       {0x00009e14, 0x37b9625e, 0x37b9625e},
11119 +};
11120 +
11121  #endif /* INITVALS_9003_2P2_H */
11122 --- /dev/null
11123 +++ b/drivers/net/wireless/ath/ath9k/ar9565_1p1_initvals.h
11124 @@ -0,0 +1,64 @@
11125 +/*
11126 + * Copyright (c) 2010-2011 Atheros Communications Inc.
11127 + * Copyright (c) 2011-2012 Qualcomm Atheros Inc.
11128 + *
11129 + * Permission to use, copy, modify, and/or distribute this software for any
11130 + * purpose with or without fee is hereby granted, provided that the above
11131 + * copyright notice and this permission notice appear in all copies.
11132 + *
11133 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11134 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11135 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11136 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
11137 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
11138 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
11139 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
11140 + */
11141 +
11142 +#ifndef INITVALS_9565_1P1_H
11143 +#define INITVALS_9565_1P1_H
11144 +
11145 +/* AR9565 1.1 */
11146 +
11147 +#define ar9565_1p1_mac_core ar9565_1p0_mac_core
11148 +
11149 +#define ar9565_1p1_mac_postamble ar9565_1p0_mac_postamble
11150 +
11151 +#define ar9565_1p1_baseband_core ar9565_1p0_baseband_core
11152 +
11153 +#define ar9565_1p1_baseband_postamble ar9565_1p0_baseband_postamble
11154 +
11155 +#define ar9565_1p1_radio_core ar9565_1p0_radio_core
11156 +
11157 +#define ar9565_1p1_soc_preamble ar9565_1p0_soc_preamble
11158 +
11159 +#define ar9565_1p1_soc_postamble ar9565_1p0_soc_postamble
11160 +
11161 +#define ar9565_1p1_Common_rx_gain_table ar9565_1p0_Common_rx_gain_table
11162 +
11163 +#define ar9565_1p1_Modes_lowest_ob_db_tx_gain_table ar9565_1p0_Modes_lowest_ob_db_tx_gain_table
11164 +
11165 +#define ar9565_1p1_pciephy_clkreq_disable_L1 ar9565_1p0_pciephy_clkreq_disable_L1
11166 +
11167 +#define ar9565_1p1_modes_fast_clock ar9565_1p0_modes_fast_clock
11168 +
11169 +#define ar9565_1p1_common_wo_xlna_rx_gain_table ar9565_1p0_common_wo_xlna_rx_gain_table
11170 +
11171 +#define ar9565_1p1_modes_low_ob_db_tx_gain_table ar9565_1p0_modes_low_ob_db_tx_gain_table
11172 +
11173 +#define ar9565_1p1_modes_high_ob_db_tx_gain_table ar9565_1p0_modes_high_ob_db_tx_gain_table
11174 +
11175 +#define ar9565_1p1_modes_high_power_tx_gain_table ar9565_1p0_modes_high_power_tx_gain_table
11176 +
11177 +#define ar9565_1p1_baseband_core_txfir_coeff_japan_2484 ar9565_1p0_baseband_core_txfir_coeff_japan_2484
11178 +
11179 +static const u32 ar9565_1p1_radio_postamble[][5] = {
11180 +       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
11181 +       {0x0001609c, 0x0b8ee524, 0x0b8ee524, 0x0b8ee524, 0x0b8ee524},
11182 +       {0x000160ac, 0xa4646c08, 0xa4646c08, 0x24645808, 0x24645808},
11183 +       {0x000160b0, 0x01d67f70, 0x01d67f70, 0x01d67f70, 0x01d67f70},
11184 +       {0x0001610c, 0x40000000, 0x40000000, 0x40000000, 0x40000000},
11185 +       {0x00016140, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
11186 +};
11187 +
11188 +#endif /* INITVALS_9565_1P1_H */
11189 --- a/drivers/net/wireless/ath/ath9k/ar9580_1p0_initvals.h
11190 +++ b/drivers/net/wireless/ath/ath9k/ar9580_1p0_initvals.h
11191 @@ -20,18 +20,34 @@
11192
11193  /* AR9580 1.0 */
11194
11195 +#define ar9580_1p0_soc_preamble ar9300_2p2_soc_preamble
11196 +
11197 +#define ar9580_1p0_soc_postamble ar9300_2p2_soc_postamble
11198 +
11199 +#define ar9580_1p0_radio_core ar9300_2p2_radio_core
11200 +
11201 +#define ar9580_1p0_mac_postamble ar9300_2p2_mac_postamble
11202 +
11203 +#define ar9580_1p0_wo_xlna_rx_gain_table ar9300Common_wo_xlna_rx_gain_table_2p2
11204 +
11205 +#define ar9580_1p0_type5_tx_gain_table ar9300Modes_type5_tx_gain_table_2p2
11206 +
11207 +#define ar9580_1p0_high_ob_db_tx_gain_table ar9300Modes_high_ob_db_tx_gain_table_2p2
11208 +
11209  #define ar9580_1p0_modes_fast_clock ar9300Modes_fast_clock_2p2
11210
11211 +#define ar9580_1p0_baseband_core_txfir_coeff_japan_2484 ar9300_2p2_baseband_core_txfir_coeff_japan_2484
11212 +
11213  static const u32 ar9580_1p0_radio_postamble[][5] = {
11214         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
11215         {0x0001609c, 0x0dd08f29, 0x0dd08f29, 0x0b283f31, 0x0b283f31},
11216         {0x000160ac, 0xa4653c00, 0xa4653c00, 0x24652800, 0x24652800},
11217         {0x000160b0, 0x03284f3e, 0x03284f3e, 0x05d08f20, 0x05d08f20},
11218 -       {0x0001610c, 0x08000000, 0x00000000, 0x00000000, 0x00000000},
11219 +       {0x0001610c, 0xc8000000, 0xc0000000, 0xc0000000, 0xc0000000},
11220         {0x00016140, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
11221 -       {0x0001650c, 0x08000000, 0x00000000, 0x00000000, 0x00000000},
11222 +       {0x0001650c, 0xc8000000, 0xc0000000, 0xc0000000, 0xc0000000},
11223         {0x00016540, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
11224 -       {0x0001690c, 0x08000000, 0x00000000, 0x00000000, 0x00000000},
11225 +       {0x0001690c, 0xc8000000, 0xc0000000, 0xc0000000, 0xc0000000},
11226         {0x00016940, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
11227  };
11228
11229 @@ -41,12 +57,10 @@ static const u32 ar9580_1p0_baseband_cor
11230         {0x00009804, 0xfd14e000},
11231         {0x00009808, 0x9c0a9f6b},
11232         {0x0000980c, 0x04900000},
11233 -       {0x00009814, 0x3280c00a},
11234 -       {0x00009818, 0x00000000},
11235         {0x0000981c, 0x00020028},
11236 -       {0x00009834, 0x6400a290},
11237 +       {0x00009834, 0x6400a190},
11238         {0x00009838, 0x0108ecff},
11239 -       {0x0000983c, 0x0d000600},
11240 +       {0x0000983c, 0x14000600},
11241         {0x00009880, 0x201fff00},
11242         {0x00009884, 0x00001042},
11243         {0x000098a4, 0x00200400},
11244 @@ -67,7 +81,7 @@ static const u32 ar9580_1p0_baseband_cor
11245         {0x00009d04, 0x40206c10},
11246         {0x00009d08, 0x009c4060},
11247         {0x00009d0c, 0x9883800a},
11248 -       {0x00009d10, 0x01834061},
11249 +       {0x00009d10, 0x01884061},
11250         {0x00009d14, 0x00c0040b},
11251         {0x00009d18, 0x00000000},
11252         {0x00009e08, 0x0038230c},
11253 @@ -198,8 +212,6 @@ static const u32 ar9580_1p0_baseband_cor
11254         {0x0000c420, 0x00000000},
11255  };
11256
11257 -#define ar9580_1p0_mac_postamble ar9300_2p2_mac_postamble
11258 -
11259  static const u32 ar9580_1p0_low_ob_db_tx_gain_table[][5] = {
11260         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
11261         {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
11262 @@ -306,7 +318,112 @@ static const u32 ar9580_1p0_low_ob_db_tx
11263         {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
11264  };
11265
11266 -#define ar9580_1p0_high_power_tx_gain_table ar9580_1p0_low_ob_db_tx_gain_table
11267 +static const u32 ar9580_1p0_high_power_tx_gain_table[][5] = {
11268 +       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
11269 +       {0x0000a2dc, 0x000cfff0, 0x000cfff0, 0x03aaa352, 0x03aaa352},
11270 +       {0x0000a2e0, 0x000f0000, 0x000f0000, 0x03ccc584, 0x03ccc584},
11271 +       {0x0000a2e4, 0x03f00000, 0x03f00000, 0x03f0f800, 0x03f0f800},
11272 +       {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
11273 +       {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
11274 +       {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
11275 +       {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
11276 +       {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004},
11277 +       {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
11278 +       {0x0000a510, 0x15000028, 0x15000028, 0x0f000202, 0x0f000202},
11279 +       {0x0000a514, 0x1b00002b, 0x1b00002b, 0x12000400, 0x12000400},
11280 +       {0x0000a518, 0x1f020028, 0x1f020028, 0x16000402, 0x16000402},
11281 +       {0x0000a51c, 0x2502002b, 0x2502002b, 0x19000404, 0x19000404},
11282 +       {0x0000a520, 0x2a04002a, 0x2a04002a, 0x1c000603, 0x1c000603},
11283 +       {0x0000a524, 0x2e06002a, 0x2e06002a, 0x21000a02, 0x21000a02},
11284 +       {0x0000a528, 0x3302202d, 0x3302202d, 0x25000a04, 0x25000a04},
11285 +       {0x0000a52c, 0x3804202c, 0x3804202c, 0x28000a20, 0x28000a20},
11286 +       {0x0000a530, 0x3c06202c, 0x3c06202c, 0x2c000e20, 0x2c000e20},
11287 +       {0x0000a534, 0x4108202d, 0x4108202d, 0x30000e22, 0x30000e22},
11288 +       {0x0000a538, 0x4506402d, 0x4506402d, 0x34000e24, 0x34000e24},
11289 +       {0x0000a53c, 0x4906222d, 0x4906222d, 0x38001640, 0x38001640},
11290 +       {0x0000a540, 0x4d062231, 0x4d062231, 0x3c001660, 0x3c001660},
11291 +       {0x0000a544, 0x50082231, 0x50082231, 0x3f001861, 0x3f001861},
11292 +       {0x0000a548, 0x5608422e, 0x5608422e, 0x43001a81, 0x43001a81},
11293 +       {0x0000a54c, 0x5e08442e, 0x5e08442e, 0x47001a83, 0x47001a83},
11294 +       {0x0000a550, 0x620a4431, 0x620a4431, 0x4a001c84, 0x4a001c84},
11295 +       {0x0000a554, 0x640a4432, 0x640a4432, 0x4e001ce3, 0x4e001ce3},
11296 +       {0x0000a558, 0x680a4434, 0x680a4434, 0x52001ce5, 0x52001ce5},
11297 +       {0x0000a55c, 0x6c0a6434, 0x6c0a6434, 0x56001ce9, 0x56001ce9},
11298 +       {0x0000a560, 0x6f0a6633, 0x6f0a6633, 0x5a001ceb, 0x5a001ceb},
11299 +       {0x0000a564, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
11300 +       {0x0000a568, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
11301 +       {0x0000a56c, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
11302 +       {0x0000a570, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
11303 +       {0x0000a574, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
11304 +       {0x0000a578, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
11305 +       {0x0000a57c, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
11306 +       {0x0000a580, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
11307 +       {0x0000a584, 0x06800003, 0x06800003, 0x04800002, 0x04800002},
11308 +       {0x0000a588, 0x0a800020, 0x0a800020, 0x08800004, 0x08800004},
11309 +       {0x0000a58c, 0x10800023, 0x10800023, 0x0b800200, 0x0b800200},
11310 +       {0x0000a590, 0x15800028, 0x15800028, 0x0f800202, 0x0f800202},
11311 +       {0x0000a594, 0x1b80002b, 0x1b80002b, 0x12800400, 0x12800400},
11312 +       {0x0000a598, 0x1f820028, 0x1f820028, 0x16800402, 0x16800402},
11313 +       {0x0000a59c, 0x2582002b, 0x2582002b, 0x19800404, 0x19800404},
11314 +       {0x0000a5a0, 0x2a84002a, 0x2a84002a, 0x1c800603, 0x1c800603},
11315 +       {0x0000a5a4, 0x2e86002a, 0x2e86002a, 0x21800a02, 0x21800a02},
11316 +       {0x0000a5a8, 0x3382202d, 0x3382202d, 0x25800a04, 0x25800a04},
11317 +       {0x0000a5ac, 0x3884202c, 0x3884202c, 0x28800a20, 0x28800a20},
11318 +       {0x0000a5b0, 0x3c86202c, 0x3c86202c, 0x2c800e20, 0x2c800e20},
11319 +       {0x0000a5b4, 0x4188202d, 0x4188202d, 0x30800e22, 0x30800e22},
11320 +       {0x0000a5b8, 0x4586402d, 0x4586402d, 0x34800e24, 0x34800e24},
11321 +       {0x0000a5bc, 0x4986222d, 0x4986222d, 0x38801640, 0x38801640},
11322 +       {0x0000a5c0, 0x4d862231, 0x4d862231, 0x3c801660, 0x3c801660},
11323 +       {0x0000a5c4, 0x50882231, 0x50882231, 0x3f801861, 0x3f801861},
11324 +       {0x0000a5c8, 0x5688422e, 0x5688422e, 0x43801a81, 0x43801a81},
11325 +       {0x0000a5cc, 0x5a88442e, 0x5a88442e, 0x47801a83, 0x47801a83},
11326 +       {0x0000a5d0, 0x5e8a4431, 0x5e8a4431, 0x4a801c84, 0x4a801c84},
11327 +       {0x0000a5d4, 0x648a4432, 0x648a4432, 0x4e801ce3, 0x4e801ce3},
11328 +       {0x0000a5d8, 0x688a4434, 0x688a4434, 0x52801ce5, 0x52801ce5},
11329 +       {0x0000a5dc, 0x6c8a6434, 0x6c8a6434, 0x56801ce9, 0x56801ce9},
11330 +       {0x0000a5e0, 0x6f8a6633, 0x6f8a6633, 0x5a801ceb, 0x5a801ceb},
11331 +       {0x0000a5e4, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
11332 +       {0x0000a5e8, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
11333 +       {0x0000a5ec, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
11334 +       {0x0000a5f0, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
11335 +       {0x0000a5f4, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
11336 +       {0x0000a5f8, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
11337 +       {0x0000a5fc, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
11338 +       {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
11339 +       {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
11340 +       {0x0000a608, 0x01804601, 0x01804601, 0x00000000, 0x00000000},
11341 +       {0x0000a60c, 0x01804601, 0x01804601, 0x00000000, 0x00000000},
11342 +       {0x0000a610, 0x01804601, 0x01804601, 0x00000000, 0x00000000},
11343 +       {0x0000a614, 0x01804601, 0x01804601, 0x01404000, 0x01404000},
11344 +       {0x0000a618, 0x01804601, 0x01804601, 0x01404501, 0x01404501},
11345 +       {0x0000a61c, 0x01804601, 0x01804601, 0x02008501, 0x02008501},
11346 +       {0x0000a620, 0x03408d02, 0x03408d02, 0x0280ca03, 0x0280ca03},
11347 +       {0x0000a624, 0x0300cc03, 0x0300cc03, 0x03010c04, 0x03010c04},
11348 +       {0x0000a628, 0x03410d04, 0x03410d04, 0x04014c04, 0x04014c04},
11349 +       {0x0000a62c, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
11350 +       {0x0000a630, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
11351 +       {0x0000a634, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
11352 +       {0x0000a638, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
11353 +       {0x0000a63c, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
11354 +       {0x0000b2dc, 0x000cfff0, 0x000cfff0, 0x03aaa352, 0x03aaa352},
11355 +       {0x0000b2e0, 0x000f0000, 0x000f0000, 0x03ccc584, 0x03ccc584},
11356 +       {0x0000b2e4, 0x03f00000, 0x03f00000, 0x03f0f800, 0x03f0f800},
11357 +       {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
11358 +       {0x0000c2dc, 0x000cfff0, 0x000cfff0, 0x03aaa352, 0x03aaa352},
11359 +       {0x0000c2e0, 0x000f0000, 0x000f0000, 0x03ccc584, 0x03ccc584},
11360 +       {0x0000c2e4, 0x03f00000, 0x03f00000, 0x03f0f800, 0x03f0f800},
11361 +       {0x0000c2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
11362 +       {0x00016044, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
11363 +       {0x00016048, 0x65240001, 0x65240001, 0x66480001, 0x66480001},
11364 +       {0x00016068, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
11365 +       {0x00016288, 0x05a2040a, 0x05a2040a, 0x05a20408, 0x05a20408},
11366 +       {0x00016444, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
11367 +       {0x00016448, 0x65240001, 0x65240001, 0x66480001, 0x66480001},
11368 +       {0x00016468, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
11369 +       {0x00016844, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
11370 +       {0x00016848, 0x65240001, 0x65240001, 0x66480001, 0x66480001},
11371 +       {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
11372 +};
11373
11374  static const u32 ar9580_1p0_lowest_ob_db_tx_gain_table[][5] = {
11375         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
11376 @@ -414,8 +531,6 @@ static const u32 ar9580_1p0_lowest_ob_db
11377         {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
11378  };
11379
11380 -#define ar9580_1p0_baseband_core_txfir_coeff_japan_2484 ar9462_2p0_baseband_core_txfir_coeff_japan_2484
11381 -
11382  static const u32 ar9580_1p0_mac_core[][2] = {
11383         /* Addr      allmodes  */
11384         {0x00000008, 0x00000000},
11385 @@ -679,14 +794,6 @@ static const u32 ar9580_1p0_mixed_ob_db_
11386         {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
11387  };
11388
11389 -#define ar9580_1p0_wo_xlna_rx_gain_table ar9300Common_wo_xlna_rx_gain_table_2p2
11390 -
11391 -#define ar9580_1p0_soc_postamble ar9300_2p2_soc_postamble
11392 -
11393 -#define ar9580_1p0_high_ob_db_tx_gain_table ar9300Modes_high_ob_db_tx_gain_table_2p2
11394 -
11395 -#define ar9580_1p0_type5_tx_gain_table ar9300Modes_type5_tx_gain_table_2p2
11396 -
11397  static const u32 ar9580_1p0_type6_tx_gain_table[][5] = {
11398         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
11399         {0x0000a2dc, 0x000cfff0, 0x000cfff0, 0x03aaa352, 0x03aaa352},
11400 @@ -761,165 +868,271 @@ static const u32 ar9580_1p0_type6_tx_gai
11401         {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
11402  };
11403
11404 -static const u32 ar9580_1p0_soc_preamble[][2] = {
11405 +static const u32 ar9580_1p0_rx_gain_table[][2] = {
11406         /* Addr      allmodes  */
11407 -       {0x000040a4, 0x00a0c1c9},
11408 -       {0x00007008, 0x00000000},
11409 -       {0x00007020, 0x00000000},
11410 -       {0x00007034, 0x00000002},
11411 -       {0x00007038, 0x000004c2},
11412 -       {0x00007048, 0x00000008},
11413 -};
11414 -
11415 -#define ar9580_1p0_rx_gain_table ar9462_common_rx_gain_table_2p0
11416 -
11417 -static const u32 ar9580_1p0_radio_core[][2] = {
11418 -       /* Addr      allmodes  */
11419 -       {0x00016000, 0x36db6db6},
11420 -       {0x00016004, 0x6db6db40},
11421 -       {0x00016008, 0x73f00000},
11422 -       {0x0001600c, 0x00000000},
11423 -       {0x00016040, 0x7f80fff8},
11424 -       {0x0001604c, 0x76d005b5},
11425 -       {0x00016050, 0x556cf031},
11426 -       {0x00016054, 0x13449440},
11427 -       {0x00016058, 0x0c51c92c},
11428 -       {0x0001605c, 0x3db7fffc},
11429 -       {0x00016060, 0xfffffffc},
11430 -       {0x00016064, 0x000f0278},
11431 -       {0x0001606c, 0x6db60000},
11432 -       {0x00016080, 0x00000000},
11433 -       {0x00016084, 0x0e48048c},
11434 -       {0x00016088, 0x54214514},
11435 -       {0x0001608c, 0x119f481e},
11436 -       {0x00016090, 0x24926490},
11437 -       {0x00016098, 0xd2888888},
11438 -       {0x000160a0, 0x0a108ffe},
11439 -       {0x000160a4, 0x812fc370},
11440 -       {0x000160a8, 0x423c8000},
11441 -       {0x000160b4, 0x92480080},
11442 -       {0x000160c0, 0x00adb6d0},
11443 -       {0x000160c4, 0x6db6db60},
11444 -       {0x000160c8, 0x6db6db6c},
11445 -       {0x000160cc, 0x01e6c000},
11446 -       {0x00016100, 0x3fffbe01},
11447 -       {0x00016104, 0xfff80000},
11448 -       {0x00016108, 0x00080010},
11449 -       {0x00016144, 0x02084080},
11450 -       {0x00016148, 0x00000000},
11451 -       {0x00016280, 0x058a0001},
11452 -       {0x00016284, 0x3d840208},
11453 -       {0x00016288, 0x05a20408},
11454 -       {0x0001628c, 0x00038c07},
11455 -       {0x00016290, 0x00000004},
11456 -       {0x00016294, 0x458aa14f},
11457 -       {0x00016380, 0x00000000},
11458 -       {0x00016384, 0x00000000},
11459 -       {0x00016388, 0x00800700},
11460 -       {0x0001638c, 0x00800700},
11461 -       {0x00016390, 0x00800700},
11462 -       {0x00016394, 0x00000000},
11463 -       {0x00016398, 0x00000000},
11464 -       {0x0001639c, 0x00000000},
11465 -       {0x000163a0, 0x00000001},
11466 -       {0x000163a4, 0x00000001},
11467 -       {0x000163a8, 0x00000000},
11468 -       {0x000163ac, 0x00000000},
11469 -       {0x000163b0, 0x00000000},
11470 -       {0x000163b4, 0x00000000},
11471 -       {0x000163b8, 0x00000000},
11472 -       {0x000163bc, 0x00000000},
11473 -       {0x000163c0, 0x000000a0},
11474 -       {0x000163c4, 0x000c0000},
11475 -       {0x000163c8, 0x14021402},
11476 -       {0x000163cc, 0x00001402},
11477 -       {0x000163d0, 0x00000000},
11478 -       {0x000163d4, 0x00000000},
11479 -       {0x00016400, 0x36db6db6},
11480 -       {0x00016404, 0x6db6db40},
11481 -       {0x00016408, 0x73f00000},
11482 -       {0x0001640c, 0x00000000},
11483 -       {0x00016440, 0x7f80fff8},
11484 -       {0x0001644c, 0x76d005b5},
11485 -       {0x00016450, 0x556cf031},
11486 -       {0x00016454, 0x13449440},
11487 -       {0x00016458, 0x0c51c92c},
11488 -       {0x0001645c, 0x3db7fffc},
11489 -       {0x00016460, 0xfffffffc},
11490 -       {0x00016464, 0x000f0278},
11491 -       {0x0001646c, 0x6db60000},
11492 -       {0x00016500, 0x3fffbe01},
11493 -       {0x00016504, 0xfff80000},
11494 -       {0x00016508, 0x00080010},
11495 -       {0x00016544, 0x02084080},
11496 -       {0x00016548, 0x00000000},
11497 -       {0x00016780, 0x00000000},
11498 -       {0x00016784, 0x00000000},
11499 -       {0x00016788, 0x00800700},
11500 -       {0x0001678c, 0x00800700},
11501 -       {0x00016790, 0x00800700},
11502 -       {0x00016794, 0x00000000},
11503 -       {0x00016798, 0x00000000},
11504 -       {0x0001679c, 0x00000000},
11505 -       {0x000167a0, 0x00000001},
11506 -       {0x000167a4, 0x00000001},
11507 -       {0x000167a8, 0x00000000},
11508 -       {0x000167ac, 0x00000000},
11509 -       {0x000167b0, 0x00000000},
11510 -       {0x000167b4, 0x00000000},
11511 -       {0x000167b8, 0x00000000},
11512 -       {0x000167bc, 0x00000000},
11513 -       {0x000167c0, 0x000000a0},
11514 -       {0x000167c4, 0x000c0000},
11515 -       {0x000167c8, 0x14021402},
11516 -       {0x000167cc, 0x00001402},
11517 -       {0x000167d0, 0x00000000},
11518 -       {0x000167d4, 0x00000000},
11519 -       {0x00016800, 0x36db6db6},
11520 -       {0x00016804, 0x6db6db40},
11521 -       {0x00016808, 0x73f00000},
11522 -       {0x0001680c, 0x00000000},
11523 -       {0x00016840, 0x7f80fff8},
11524 -       {0x0001684c, 0x76d005b5},
11525 -       {0x00016850, 0x556cf031},
11526 -       {0x00016854, 0x13449440},
11527 -       {0x00016858, 0x0c51c92c},
11528 -       {0x0001685c, 0x3db7fffc},
11529 -       {0x00016860, 0xfffffffc},
11530 -       {0x00016864, 0x000f0278},
11531 -       {0x0001686c, 0x6db60000},
11532 -       {0x00016900, 0x3fffbe01},
11533 -       {0x00016904, 0xfff80000},
11534 -       {0x00016908, 0x00080010},
11535 -       {0x00016944, 0x02084080},
11536 -       {0x00016948, 0x00000000},
11537 -       {0x00016b80, 0x00000000},
11538 -       {0x00016b84, 0x00000000},
11539 -       {0x00016b88, 0x00800700},
11540 -       {0x00016b8c, 0x00800700},
11541 -       {0x00016b90, 0x00800700},
11542 -       {0x00016b94, 0x00000000},
11543 -       {0x00016b98, 0x00000000},
11544 -       {0x00016b9c, 0x00000000},
11545 -       {0x00016ba0, 0x00000001},
11546 -       {0x00016ba4, 0x00000001},
11547 -       {0x00016ba8, 0x00000000},
11548 -       {0x00016bac, 0x00000000},
11549 -       {0x00016bb0, 0x00000000},
11550 -       {0x00016bb4, 0x00000000},
11551 -       {0x00016bb8, 0x00000000},
11552 -       {0x00016bbc, 0x00000000},
11553 -       {0x00016bc0, 0x000000a0},
11554 -       {0x00016bc4, 0x000c0000},
11555 -       {0x00016bc8, 0x14021402},
11556 -       {0x00016bcc, 0x00001402},
11557 -       {0x00016bd0, 0x00000000},
11558 -       {0x00016bd4, 0x00000000},
11559 +       {0x0000a000, 0x00010000},
11560 +       {0x0000a004, 0x00030002},
11561 +       {0x0000a008, 0x00050004},
11562 +       {0x0000a00c, 0x00810080},
11563 +       {0x0000a010, 0x00830082},
11564 +       {0x0000a014, 0x01810180},
11565 +       {0x0000a018, 0x01830182},
11566 +       {0x0000a01c, 0x01850184},
11567 +       {0x0000a020, 0x01890188},
11568 +       {0x0000a024, 0x018b018a},
11569 +       {0x0000a028, 0x018d018c},
11570 +       {0x0000a02c, 0x01910190},
11571 +       {0x0000a030, 0x01930192},
11572 +       {0x0000a034, 0x01950194},
11573 +       {0x0000a038, 0x038a0196},
11574 +       {0x0000a03c, 0x038c038b},
11575 +       {0x0000a040, 0x0390038d},
11576 +       {0x0000a044, 0x03920391},
11577 +       {0x0000a048, 0x03940393},
11578 +       {0x0000a04c, 0x03960395},
11579 +       {0x0000a050, 0x00000000},
11580 +       {0x0000a054, 0x00000000},
11581 +       {0x0000a058, 0x00000000},
11582 +       {0x0000a05c, 0x00000000},
11583 +       {0x0000a060, 0x00000000},
11584 +       {0x0000a064, 0x00000000},
11585 +       {0x0000a068, 0x00000000},
11586 +       {0x0000a06c, 0x00000000},
11587 +       {0x0000a070, 0x00000000},
11588 +       {0x0000a074, 0x00000000},
11589 +       {0x0000a078, 0x00000000},
11590 +       {0x0000a07c, 0x00000000},
11591 +       {0x0000a080, 0x22222229},
11592 +       {0x0000a084, 0x1d1d1d1d},
11593 +       {0x0000a088, 0x1d1d1d1d},
11594 +       {0x0000a08c, 0x1d1d1d1d},
11595 +       {0x0000a090, 0x171d1d1d},
11596 +       {0x0000a094, 0x11111717},
11597 +       {0x0000a098, 0x00030311},
11598 +       {0x0000a09c, 0x00000000},
11599 +       {0x0000a0a0, 0x00000000},
11600 +       {0x0000a0a4, 0x00000000},
11601 +       {0x0000a0a8, 0x00000000},
11602 +       {0x0000a0ac, 0x00000000},
11603 +       {0x0000a0b0, 0x00000000},
11604 +       {0x0000a0b4, 0x00000000},
11605 +       {0x0000a0b8, 0x00000000},
11606 +       {0x0000a0bc, 0x00000000},
11607 +       {0x0000a0c0, 0x001f0000},
11608 +       {0x0000a0c4, 0x01000101},
11609 +       {0x0000a0c8, 0x011e011f},
11610 +       {0x0000a0cc, 0x011c011d},
11611 +       {0x0000a0d0, 0x02030204},
11612 +       {0x0000a0d4, 0x02010202},
11613 +       {0x0000a0d8, 0x021f0200},
11614 +       {0x0000a0dc, 0x0302021e},
11615 +       {0x0000a0e0, 0x03000301},
11616 +       {0x0000a0e4, 0x031e031f},
11617 +       {0x0000a0e8, 0x0402031d},
11618 +       {0x0000a0ec, 0x04000401},
11619 +       {0x0000a0f0, 0x041e041f},
11620 +       {0x0000a0f4, 0x0502041d},
11621 +       {0x0000a0f8, 0x05000501},
11622 +       {0x0000a0fc, 0x051e051f},
11623 +       {0x0000a100, 0x06010602},
11624 +       {0x0000a104, 0x061f0600},
11625 +       {0x0000a108, 0x061d061e},
11626 +       {0x0000a10c, 0x07020703},
11627 +       {0x0000a110, 0x07000701},
11628 +       {0x0000a114, 0x00000000},
11629 +       {0x0000a118, 0x00000000},
11630 +       {0x0000a11c, 0x00000000},
11631 +       {0x0000a120, 0x00000000},
11632 +       {0x0000a124, 0x00000000},
11633 +       {0x0000a128, 0x00000000},
11634 +       {0x0000a12c, 0x00000000},
11635 +       {0x0000a130, 0x00000000},
11636 +       {0x0000a134, 0x00000000},
11637 +       {0x0000a138, 0x00000000},
11638 +       {0x0000a13c, 0x00000000},
11639 +       {0x0000a140, 0x001f0000},
11640 +       {0x0000a144, 0x01000101},
11641 +       {0x0000a148, 0x011e011f},
11642 +       {0x0000a14c, 0x011c011d},
11643 +       {0x0000a150, 0x02030204},
11644 +       {0x0000a154, 0x02010202},
11645 +       {0x0000a158, 0x021f0200},
11646 +       {0x0000a15c, 0x0302021e},
11647 +       {0x0000a160, 0x03000301},
11648 +       {0x0000a164, 0x031e031f},
11649 +       {0x0000a168, 0x0402031d},
11650 +       {0x0000a16c, 0x04000401},
11651 +       {0x0000a170, 0x041e041f},
11652 +       {0x0000a174, 0x0502041d},
11653 +       {0x0000a178, 0x05000501},
11654 +       {0x0000a17c, 0x051e051f},
11655 +       {0x0000a180, 0x06010602},
11656 +       {0x0000a184, 0x061f0600},
11657 +       {0x0000a188, 0x061d061e},
11658 +       {0x0000a18c, 0x07020703},
11659 +       {0x0000a190, 0x07000701},
11660 +       {0x0000a194, 0x00000000},
11661 +       {0x0000a198, 0x00000000},
11662 +       {0x0000a19c, 0x00000000},
11663 +       {0x0000a1a0, 0x00000000},
11664 +       {0x0000a1a4, 0x00000000},
11665 +       {0x0000a1a8, 0x00000000},
11666 +       {0x0000a1ac, 0x00000000},
11667 +       {0x0000a1b0, 0x00000000},
11668 +       {0x0000a1b4, 0x00000000},
11669 +       {0x0000a1b8, 0x00000000},
11670 +       {0x0000a1bc, 0x00000000},
11671 +       {0x0000a1c0, 0x00000000},
11672 +       {0x0000a1c4, 0x00000000},
11673 +       {0x0000a1c8, 0x00000000},
11674 +       {0x0000a1cc, 0x00000000},
11675 +       {0x0000a1d0, 0x00000000},
11676 +       {0x0000a1d4, 0x00000000},
11677 +       {0x0000a1d8, 0x00000000},
11678 +       {0x0000a1dc, 0x00000000},
11679 +       {0x0000a1e0, 0x00000000},
11680 +       {0x0000a1e4, 0x00000000},
11681 +       {0x0000a1e8, 0x00000000},
11682 +       {0x0000a1ec, 0x00000000},
11683 +       {0x0000a1f0, 0x00000396},
11684 +       {0x0000a1f4, 0x00000396},
11685 +       {0x0000a1f8, 0x00000396},
11686 +       {0x0000a1fc, 0x00000196},
11687 +       {0x0000b000, 0x00010000},
11688 +       {0x0000b004, 0x00030002},
11689 +       {0x0000b008, 0x00050004},
11690 +       {0x0000b00c, 0x00810080},
11691 +       {0x0000b010, 0x00830082},
11692 +       {0x0000b014, 0x01810180},
11693 +       {0x0000b018, 0x01830182},
11694 +       {0x0000b01c, 0x01850184},
11695 +       {0x0000b020, 0x02810280},
11696 +       {0x0000b024, 0x02830282},
11697 +       {0x0000b028, 0x02850284},
11698 +       {0x0000b02c, 0x02890288},
11699 +       {0x0000b030, 0x028b028a},
11700 +       {0x0000b034, 0x0388028c},
11701 +       {0x0000b038, 0x038a0389},
11702 +       {0x0000b03c, 0x038c038b},
11703 +       {0x0000b040, 0x0390038d},
11704 +       {0x0000b044, 0x03920391},
11705 +       {0x0000b048, 0x03940393},
11706 +       {0x0000b04c, 0x03960395},
11707 +       {0x0000b050, 0x00000000},
11708 +       {0x0000b054, 0x00000000},
11709 +       {0x0000b058, 0x00000000},
11710 +       {0x0000b05c, 0x00000000},
11711 +       {0x0000b060, 0x00000000},
11712 +       {0x0000b064, 0x00000000},
11713 +       {0x0000b068, 0x00000000},
11714 +       {0x0000b06c, 0x00000000},
11715 +       {0x0000b070, 0x00000000},
11716 +       {0x0000b074, 0x00000000},
11717 +       {0x0000b078, 0x00000000},
11718 +       {0x0000b07c, 0x00000000},
11719 +       {0x0000b080, 0x23232323},
11720 +       {0x0000b084, 0x21232323},
11721 +       {0x0000b088, 0x19191c1e},
11722 +       {0x0000b08c, 0x12141417},
11723 +       {0x0000b090, 0x07070e0e},
11724 +       {0x0000b094, 0x03030305},
11725 +       {0x0000b098, 0x00000003},
11726 +       {0x0000b09c, 0x00000000},
11727 +       {0x0000b0a0, 0x00000000},
11728 +       {0x0000b0a4, 0x00000000},
11729 +       {0x0000b0a8, 0x00000000},
11730 +       {0x0000b0ac, 0x00000000},
11731 +       {0x0000b0b0, 0x00000000},
11732 +       {0x0000b0b4, 0x00000000},
11733 +       {0x0000b0b8, 0x00000000},
11734 +       {0x0000b0bc, 0x00000000},
11735 +       {0x0000b0c0, 0x003f0020},
11736 +       {0x0000b0c4, 0x00400041},
11737 +       {0x0000b0c8, 0x0140005f},
11738 +       {0x0000b0cc, 0x0160015f},
11739 +       {0x0000b0d0, 0x017e017f},
11740 +       {0x0000b0d4, 0x02410242},
11741 +       {0x0000b0d8, 0x025f0240},
11742 +       {0x0000b0dc, 0x027f0260},
11743 +       {0x0000b0e0, 0x0341027e},
11744 +       {0x0000b0e4, 0x035f0340},
11745 +       {0x0000b0e8, 0x037f0360},
11746 +       {0x0000b0ec, 0x04400441},
11747 +       {0x0000b0f0, 0x0460045f},
11748 +       {0x0000b0f4, 0x0541047f},
11749 +       {0x0000b0f8, 0x055f0540},
11750 +       {0x0000b0fc, 0x057f0560},
11751 +       {0x0000b100, 0x06400641},
11752 +       {0x0000b104, 0x0660065f},
11753 +       {0x0000b108, 0x067e067f},
11754 +       {0x0000b10c, 0x07410742},
11755 +       {0x0000b110, 0x075f0740},
11756 +       {0x0000b114, 0x077f0760},
11757 +       {0x0000b118, 0x07800781},
11758 +       {0x0000b11c, 0x07a0079f},
11759 +       {0x0000b120, 0x07c107bf},
11760 +       {0x0000b124, 0x000007c0},
11761 +       {0x0000b128, 0x00000000},
11762 +       {0x0000b12c, 0x00000000},
11763 +       {0x0000b130, 0x00000000},
11764 +       {0x0000b134, 0x00000000},
11765 +       {0x0000b138, 0x00000000},
11766 +       {0x0000b13c, 0x00000000},
11767 +       {0x0000b140, 0x003f0020},
11768 +       {0x0000b144, 0x00400041},
11769 +       {0x0000b148, 0x0140005f},
11770 +       {0x0000b14c, 0x0160015f},
11771 +       {0x0000b150, 0x017e017f},
11772 +       {0x0000b154, 0x02410242},
11773 +       {0x0000b158, 0x025f0240},
11774 +       {0x0000b15c, 0x027f0260},
11775 +       {0x0000b160, 0x0341027e},
11776 +       {0x0000b164, 0x035f0340},
11777 +       {0x0000b168, 0x037f0360},
11778 +       {0x0000b16c, 0x04400441},
11779 +       {0x0000b170, 0x0460045f},
11780 +       {0x0000b174, 0x0541047f},
11781 +       {0x0000b178, 0x055f0540},
11782 +       {0x0000b17c, 0x057f0560},
11783 +       {0x0000b180, 0x06400641},
11784 +       {0x0000b184, 0x0660065f},
11785 +       {0x0000b188, 0x067e067f},
11786 +       {0x0000b18c, 0x07410742},
11787 +       {0x0000b190, 0x075f0740},
11788 +       {0x0000b194, 0x077f0760},
11789 +       {0x0000b198, 0x07800781},
11790 +       {0x0000b19c, 0x07a0079f},
11791 +       {0x0000b1a0, 0x07c107bf},
11792 +       {0x0000b1a4, 0x000007c0},
11793 +       {0x0000b1a8, 0x00000000},
11794 +       {0x0000b1ac, 0x00000000},
11795 +       {0x0000b1b0, 0x00000000},
11796 +       {0x0000b1b4, 0x00000000},
11797 +       {0x0000b1b8, 0x00000000},
11798 +       {0x0000b1bc, 0x00000000},
11799 +       {0x0000b1c0, 0x00000000},
11800 +       {0x0000b1c4, 0x00000000},
11801 +       {0x0000b1c8, 0x00000000},
11802 +       {0x0000b1cc, 0x00000000},
11803 +       {0x0000b1d0, 0x00000000},
11804 +       {0x0000b1d4, 0x00000000},
11805 +       {0x0000b1d8, 0x00000000},
11806 +       {0x0000b1dc, 0x00000000},
11807 +       {0x0000b1e0, 0x00000000},
11808 +       {0x0000b1e4, 0x00000000},
11809 +       {0x0000b1e8, 0x00000000},
11810 +       {0x0000b1ec, 0x00000000},
11811 +       {0x0000b1f0, 0x00000396},
11812 +       {0x0000b1f4, 0x00000396},
11813 +       {0x0000b1f8, 0x00000396},
11814 +       {0x0000b1fc, 0x00000196},
11815  };
11816
11817  static const u32 ar9580_1p0_baseband_postamble[][5] = {
11818         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
11819         {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a8011},
11820 +       {0x00009814, 0x3280c00a, 0x3280c00a, 0x3280c00a, 0x3280c00a},
11821 +       {0x00009818, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
11822         {0x00009820, 0x206a022e, 0x206a022e, 0x206a012e, 0x206a012e},
11823         {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0},
11824         {0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881},
11825 @@ -956,7 +1169,7 @@ static const u32 ar9580_1p0_baseband_pos
11826         {0x0000a288, 0x00000110, 0x00000110, 0x00000110, 0x00000110},
11827         {0x0000a28c, 0x00022222, 0x00022222, 0x00022222, 0x00022222},
11828         {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
11829 -       {0x0000a2d0, 0x00041981, 0x00041981, 0x00041981, 0x00041982},
11830 +       {0x0000a2d0, 0x00041983, 0x00041983, 0x00041981, 0x00041982},
11831         {0x0000a2d8, 0x7999a83b, 0x7999a83b, 0x7999a83b, 0x7999a83b},
11832         {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
11833         {0x0000a830, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
11834 @@ -994,4 +1207,13 @@ static const u32 ar9580_1p0_pcie_phy_pll
11835         {0x00004044, 0x00000000},
11836  };
11837
11838 +static const u32 ar9580_1p0_baseband_postamble_dfs_channel[][3] = {
11839 +       /* Addr      5G          2G        */
11840 +       {0x00009814, 0x3400c00f, 0x3400c00f},
11841 +       {0x00009824, 0x5ac668d0, 0x5ac668d0},
11842 +       {0x00009828, 0x06903080, 0x06903080},
11843 +       {0x00009e0c, 0x6d4000e2, 0x6d4000e2},
11844 +       {0x00009e14, 0x37b9625e, 0x37b9625e},
11845 +};
11846 +
11847  #endif /* INITVALS_9580_1P0_H */
11848 --- a/drivers/net/wireless/ath/ath9k/reg.h
11849 +++ b/drivers/net/wireless/ath/ath9k/reg.h
11850 @@ -809,6 +809,8 @@
11851  #define AR_SREV_REVISION_9462_21       3
11852  #define AR_SREV_VERSION_9565            0x2C0
11853  #define AR_SREV_REVISION_9565_10        0
11854 +#define AR_SREV_REVISION_9565_101       1
11855 +#define AR_SREV_REVISION_9565_11        2
11856  #define AR_SREV_VERSION_9550           0x400
11857
11858  #define AR_SREV_5416(_ah) \
11859 @@ -881,9 +883,6 @@
11860
11861  #define AR_SREV_9330(_ah) \
11862         (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9330))
11863 -#define AR_SREV_9330_10(_ah) \
11864 -       (AR_SREV_9330((_ah)) && \
11865 -        ((_ah)->hw_version.macRev == AR_SREV_REVISION_9330_10))
11866  #define AR_SREV_9330_11(_ah) \
11867         (AR_SREV_9330((_ah)) && \
11868          ((_ah)->hw_version.macRev == AR_SREV_REVISION_9330_11))
11869 @@ -927,10 +926,18 @@
11870
11871  #define AR_SREV_9565(_ah) \
11872         (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9565))
11873 -
11874  #define AR_SREV_9565_10(_ah) \
11875         (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9565) && \
11876          ((_ah)->hw_version.macRev == AR_SREV_REVISION_9565_10))
11877 +#define AR_SREV_9565_101(_ah) \
11878 +       (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9565) && \
11879 +        ((_ah)->hw_version.macRev == AR_SREV_REVISION_9565_101))
11880 +#define AR_SREV_9565_11(_ah) \
11881 +       (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9565) && \
11882 +        ((_ah)->hw_version.macRev == AR_SREV_REVISION_9565_11))
11883 +#define AR_SREV_9565_11_OR_LATER(_ah) \
11884 +       (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9565) && \
11885 +        ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9565_11))
11886
11887  #define AR_SREV_9550(_ah) \
11888         (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9550))
11889 --- a/drivers/net/wireless/ath/ath9k/ar9330_1p1_initvals.h
11890 +++ b/drivers/net/wireless/ath/ath9k/ar9330_1p1_initvals.h
11891 @@ -18,6 +18,10 @@
11892  #ifndef INITVALS_9330_1P1_H
11893  #define INITVALS_9330_1P1_H
11894
11895 +#define ar9331_1p1_baseband_core_txfir_coeff_japan_2484 ar9300_2p2_baseband_core_txfir_coeff_japan_2484
11896 +
11897 +#define ar9331_modes_high_power_tx_gain_1p1 ar9331_modes_lowest_ob_db_tx_gain_1p1
11898 +
11899  static const u32 ar9331_1p1_baseband_postamble[][5] = {
11900         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
11901         {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8005, 0xd00a8005},
11902 @@ -55,7 +59,7 @@ static const u32 ar9331_1p1_baseband_pos
11903         {0x0000a284, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
11904         {0x0000a288, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
11905         {0x0000a28c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
11906 -       {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
11907 +       {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00058d18, 0x00058d18},
11908         {0x0000a2d0, 0x00071982, 0x00071982, 0x00071982, 0x00071982},
11909         {0x0000a2d8, 0xf999a83a, 0xf999a83a, 0xf999a83a, 0xf999a83a},
11910         {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
11911 @@ -252,7 +256,7 @@ static const u32 ar9331_modes_low_ob_db_
11912         {0x0000a2e0, 0xffffcc84, 0xffffcc84, 0xffffcc84, 0xffffcc84},
11913         {0x0000a2e4, 0xfffff000, 0xfffff000, 0xfffff000, 0xfffff000},
11914         {0x0000a2e8, 0xfffe0000, 0xfffe0000, 0xfffe0000, 0xfffe0000},
11915 -       {0x0000a410, 0x000050d7, 0x000050d7, 0x000050d0, 0x000050d0},
11916 +       {0x0000a410, 0x000050d7, 0x000050d7, 0x000050d4, 0x000050d4},
11917         {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
11918         {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
11919         {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
11920 @@ -337,8 +341,6 @@ static const u32 ar9331_modes_low_ob_db_
11921         {0x00016284, 0x14d3f000, 0x14d3f000, 0x14d3f000, 0x14d3f000},
11922  };
11923
11924 -#define ar9331_1p1_baseband_core_txfir_coeff_japan_2484 ar9462_2p0_baseband_core_txfir_coeff_japan_2484
11925 -
11926  static const u32 ar9331_1p1_xtal_25M[][2] = {
11927         /* Addr      allmodes  */
11928         {0x00007038, 0x000002f8},
11929 @@ -373,17 +375,17 @@ static const u32 ar9331_1p1_radio_core[]
11930         {0x000160b4, 0x92480040},
11931         {0x000160c0, 0x006db6db},
11932         {0x000160c4, 0x0186db60},
11933 -       {0x000160c8, 0x6db4db6c},
11934 +       {0x000160c8, 0x6db6db6c},
11935         {0x000160cc, 0x6de6c300},
11936         {0x000160d0, 0x14500820},
11937         {0x00016100, 0x04cb0001},
11938         {0x00016104, 0xfff80015},
11939         {0x00016108, 0x00080010},
11940         {0x0001610c, 0x00170000},
11941 -       {0x00016140, 0x10800000},
11942 +       {0x00016140, 0x50804000},
11943         {0x00016144, 0x01884080},
11944         {0x00016148, 0x000080c0},
11945 -       {0x00016280, 0x01000015},
11946 +       {0x00016280, 0x01001015},
11947         {0x00016284, 0x14d20000},
11948         {0x00016288, 0x00318000},
11949         {0x0001628c, 0x50000000},
11950 @@ -622,12 +624,12 @@ static const u32 ar9331_1p1_baseband_cor
11951         {0x0000a370, 0x00000000},
11952         {0x0000a390, 0x00000001},
11953         {0x0000a394, 0x00000444},
11954 -       {0x0000a398, 0x001f0e0f},
11955 -       {0x0000a39c, 0x0075393f},
11956 -       {0x0000a3a0, 0xb79f6427},
11957 -       {0x0000a3a4, 0x00000000},
11958 -       {0x0000a3a8, 0xaaaaaaaa},
11959 -       {0x0000a3ac, 0x3c466478},
11960 +       {0x0000a398, 0x00000000},
11961 +       {0x0000a39c, 0x210d0401},
11962 +       {0x0000a3a0, 0xab9a7144},
11963 +       {0x0000a3a4, 0x00000011},
11964 +       {0x0000a3a8, 0x3c3c003d},
11965 +       {0x0000a3ac, 0x30310030},
11966         {0x0000a3c0, 0x20202020},
11967         {0x0000a3c4, 0x22222220},
11968         {0x0000a3c8, 0x20200020},
11969 @@ -686,100 +688,18 @@ static const u32 ar9331_1p1_baseband_cor
11970         {0x0000a7dc, 0x00000001},
11971  };
11972
11973 -static const u32 ar9331_modes_high_power_tx_gain_1p1[][5] = {
11974 +static const u32 ar9331_1p1_mac_postamble[][5] = {
11975         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
11976 -       {0x0000a2d8, 0x7999a83a, 0x7999a83a, 0x7999a83a, 0x7999a83a},
11977 -       {0x0000a2dc, 0xffff2a52, 0xffff2a52, 0xffff2a52, 0xffff2a52},
11978 -       {0x0000a2e0, 0xffffcc84, 0xffffcc84, 0xffffcc84, 0xffffcc84},
11979 -       {0x0000a2e4, 0xfffff000, 0xfffff000, 0xfffff000, 0xfffff000},
11980 -       {0x0000a2e8, 0xfffe0000, 0xfffe0000, 0xfffe0000, 0xfffe0000},
11981 -       {0x0000a410, 0x000050d7, 0x000050d7, 0x000050d0, 0x000050d0},
11982 -       {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
11983 -       {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
11984 -       {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
11985 -       {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
11986 -       {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
11987 -       {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
11988 -       {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
11989 -       {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
11990 -       {0x0000a520, 0x2f001f04, 0x2f001f04, 0x23000a00, 0x23000a00},
11991 -       {0x0000a524, 0x35001fc4, 0x35001fc4, 0x27000a02, 0x27000a02},
11992 -       {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2b000a04, 0x2b000a04},
11993 -       {0x0000a52c, 0x41023e85, 0x41023e85, 0x2d000a20, 0x2d000a20},
11994 -       {0x0000a530, 0x48023ec6, 0x48023ec6, 0x31000a22, 0x31000a22},
11995 -       {0x0000a534, 0x4d023f01, 0x4d023f01, 0x35000a24, 0x35000a24},
11996 -       {0x0000a538, 0x53023f4b, 0x53023f4b, 0x38000a43, 0x38000a43},
11997 -       {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x3b000e42, 0x3b000e42},
11998 -       {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x3f000e44, 0x3f000e44},
11999 -       {0x0000a544, 0x6502feca, 0x6502feca, 0x42000e64, 0x42000e64},
12000 -       {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x46000e66, 0x46000e66},
12001 -       {0x0000a54c, 0x7203feca, 0x7203feca, 0x4a000ea6, 0x4a000ea6},
12002 -       {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x4a000ea6, 0x4a000ea6},
12003 -       {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x4a000ea6, 0x4a000ea6},
12004 -       {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x4a000ea6, 0x4a000ea6},
12005 -       {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x4a000ea6, 0x4a000ea6},
12006 -       {0x0000a560, 0x900fff0b, 0x900fff0b, 0x4a000ea6, 0x4a000ea6},
12007 -       {0x0000a564, 0x960fffcb, 0x960fffcb, 0x4a000ea6, 0x4a000ea6},
12008 -       {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
12009 -       {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
12010 -       {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
12011 -       {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
12012 -       {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
12013 -       {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
12014 -       {0x0000a580, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
12015 -       {0x0000a584, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
12016 -       {0x0000a588, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
12017 -       {0x0000a58c, 0x11062202, 0x11062202, 0x0b000200, 0x0b000200},
12018 -       {0x0000a590, 0x17022e00, 0x17022e00, 0x0f000202, 0x0f000202},
12019 -       {0x0000a594, 0x1d000ec2, 0x1d000ec2, 0x11000400, 0x11000400},
12020 -       {0x0000a598, 0x25020ec0, 0x25020ec0, 0x15000402, 0x15000402},
12021 -       {0x0000a59c, 0x2b020ec3, 0x2b020ec3, 0x19000404, 0x19000404},
12022 -       {0x0000a5a0, 0x2f001f04, 0x2f001f04, 0x1b000603, 0x1b000603},
12023 -       {0x0000a5a4, 0x35001fc4, 0x35001fc4, 0x1f000a02, 0x1f000a02},
12024 -       {0x0000a5a8, 0x3c022f04, 0x3c022f04, 0x23000a04, 0x23000a04},
12025 -       {0x0000a5ac, 0x41023e85, 0x41023e85, 0x26000a20, 0x26000a20},
12026 -       {0x0000a5b0, 0x48023ec6, 0x48023ec6, 0x2a000e20, 0x2a000e20},
12027 -       {0x0000a5b4, 0x4d023f01, 0x4d023f01, 0x2e000e22, 0x2e000e22},
12028 -       {0x0000a5b8, 0x53023f4b, 0x53023f4b, 0x31000e24, 0x31000e24},
12029 -       {0x0000a5bc, 0x5a027f09, 0x5a027f09, 0x34001640, 0x34001640},
12030 -       {0x0000a5c0, 0x5f027fc9, 0x5f027fc9, 0x38001660, 0x38001660},
12031 -       {0x0000a5c4, 0x6502feca, 0x6502feca, 0x3b001861, 0x3b001861},
12032 -       {0x0000a5c8, 0x6b02ff4a, 0x6b02ff4a, 0x3e001a81, 0x3e001a81},
12033 -       {0x0000a5cc, 0x7203feca, 0x7203feca, 0x42001a83, 0x42001a83},
12034 -       {0x0000a5d0, 0x7703ff0b, 0x7703ff0b, 0x44001c84, 0x44001c84},
12035 -       {0x0000a5d4, 0x7d06ffcb, 0x7d06ffcb, 0x48001ce3, 0x48001ce3},
12036 -       {0x0000a5d8, 0x8407ff0b, 0x8407ff0b, 0x4c001ce5, 0x4c001ce5},
12037 -       {0x0000a5dc, 0x8907ffcb, 0x8907ffcb, 0x50001ce9, 0x50001ce9},
12038 -       {0x0000a5e0, 0x900fff0b, 0x900fff0b, 0x54001ceb, 0x54001ceb},
12039 -       {0x0000a5e4, 0x960fffcb, 0x960fffcb, 0x56001eec, 0x56001eec},
12040 -       {0x0000a5e8, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
12041 -       {0x0000a5ec, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
12042 -       {0x0000a5f0, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
12043 -       {0x0000a5f4, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
12044 -       {0x0000a5f8, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
12045 -       {0x0000a5fc, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
12046 -       {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
12047 -       {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
12048 -       {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
12049 -       {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
12050 -       {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
12051 -       {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000},
12052 -       {0x0000a618, 0x01404501, 0x01404501, 0x01404501, 0x01404501},
12053 -       {0x0000a61c, 0x02008802, 0x02008802, 0x02008802, 0x02008802},
12054 -       {0x0000a620, 0x0280c802, 0x0280c802, 0x0280c802, 0x0280c802},
12055 -       {0x0000a624, 0x03010a03, 0x03010a03, 0x03010a03, 0x03010a03},
12056 -       {0x0000a628, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
12057 -       {0x0000a62c, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
12058 -       {0x0000a630, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
12059 -       {0x0000a634, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
12060 -       {0x0000a638, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
12061 -       {0x0000a63c, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
12062 -       {0x00016044, 0x034922db, 0x034922db, 0x034922db, 0x034922db},
12063 -       {0x00016284, 0x14d3f000, 0x14d3f000, 0x14d3f000, 0x14d3f000},
12064 +       {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
12065 +       {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
12066 +       {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
12067 +       {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
12068 +       {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b},
12069 +       {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
12070 +       {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
12071 +       {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
12072  };
12073
12074 -#define ar9331_1p1_mac_postamble ar9300_2p2_mac_postamble
12075 -
12076  static const u32 ar9331_1p1_soc_preamble[][2] = {
12077         /* Addr      allmodes  */
12078         {0x00007020, 0x00000000},
12079 --- a/drivers/net/wireless/ath/ath9k/ar9330_1p2_initvals.h
12080 +++ b/drivers/net/wireless/ath/ath9k/ar9330_1p2_initvals.h
12081 @@ -18,6 +18,28 @@
12082  #ifndef INITVALS_9330_1P2_H
12083  #define INITVALS_9330_1P2_H
12084
12085 +#define ar9331_modes_high_power_tx_gain_1p2 ar9331_modes_high_ob_db_tx_gain_1p2
12086 +
12087 +#define ar9331_modes_low_ob_db_tx_gain_1p2 ar9331_modes_high_ob_db_tx_gain_1p2
12088 +
12089 +#define ar9331_modes_lowest_ob_db_tx_gain_1p2 ar9331_modes_high_ob_db_tx_gain_1p2
12090 +
12091 +#define ar9331_1p2_baseband_core_txfir_coeff_japan_2484 ar9331_1p1_baseband_core_txfir_coeff_japan_2484
12092 +
12093 +#define ar9331_1p2_xtal_25M ar9331_1p1_xtal_25M
12094 +
12095 +#define ar9331_1p2_xtal_40M ar9331_1p1_xtal_40M
12096 +
12097 +#define ar9331_1p2_soc_postamble ar9331_1p1_soc_postamble
12098 +
12099 +#define ar9331_1p2_mac_postamble ar9331_1p1_mac_postamble
12100 +
12101 +#define ar9331_1p2_soc_preamble ar9331_1p1_soc_preamble
12102 +
12103 +#define ar9331_1p2_mac_core ar9331_1p1_mac_core
12104 +
12105 +#define ar9331_common_wo_xlna_rx_gain_1p2 ar9331_common_wo_xlna_rx_gain_1p1
12106 +
12107  static const u32 ar9331_modes_high_ob_db_tx_gain_1p2[][5] = {
12108         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
12109         {0x0000a410, 0x000050d7, 0x000050d7, 0x000050d7, 0x000050d7},
12110 @@ -103,57 +125,6 @@ static const u32 ar9331_modes_high_ob_db
12111         {0x0000a63c, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
12112  };
12113
12114 -#define ar9331_modes_high_power_tx_gain_1p2 ar9331_modes_high_ob_db_tx_gain_1p2
12115 -
12116 -#define ar9331_modes_low_ob_db_tx_gain_1p2 ar9331_modes_high_power_tx_gain_1p2
12117 -
12118 -#define ar9331_modes_lowest_ob_db_tx_gain_1p2 ar9331_modes_low_ob_db_tx_gain_1p2
12119 -
12120 -static const u32 ar9331_1p2_baseband_postamble[][5] = {
12121 -       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
12122 -       {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8005, 0xd00a8005},
12123 -       {0x00009820, 0x206a002e, 0x206a002e, 0x206a002e, 0x206a002e},
12124 -       {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0},
12125 -       {0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881},
12126 -       {0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4},
12127 -       {0x00009830, 0x0000059c, 0x0000059c, 0x0000059c, 0x0000059c},
12128 -       {0x00009c00, 0x00000044, 0x00000044, 0x00000044, 0x00000044},
12129 -       {0x00009e00, 0x0372161e, 0x0372161e, 0x037216a4, 0x037216a4},
12130 -       {0x00009e04, 0x00182020, 0x00182020, 0x00182020, 0x00182020},
12131 -       {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2},
12132 -       {0x00009e10, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e},
12133 -       {0x00009e14, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e},
12134 -       {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
12135 -       {0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c},
12136 -       {0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce},
12137 -       {0x00009e2c, 0x0000001c, 0x0000001c, 0x00003221, 0x00003221},
12138 -       {0x00009e3c, 0xcf946222, 0xcf946222, 0xcf946222, 0xcf946222},
12139 -       {0x00009e44, 0x02321e27, 0x02321e27, 0x02282324, 0x02282324},
12140 -       {0x00009e48, 0x5030201a, 0x5030201a, 0x50302010, 0x50302010},
12141 -       {0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000},
12142 -       {0x0000a204, 0x00003fc0, 0x00003fc4, 0x00003fc4, 0x00003fc0},
12143 -       {0x0000a208, 0x00000104, 0x00000104, 0x00000004, 0x00000004},
12144 -       {0x0000a230, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b},
12145 -       {0x0000a234, 0x00000fff, 0x00000fff, 0x10000fff, 0x00000fff},
12146 -       {0x0000a238, 0xffb81018, 0xffb81018, 0xffb81018, 0xffb81018},
12147 -       {0x0000a250, 0x00000000, 0x00000000, 0x00000210, 0x00000108},
12148 -       {0x0000a254, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898},
12149 -       {0x0000a258, 0x02020002, 0x02020002, 0x02020002, 0x02020002},
12150 -       {0x0000a25c, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e},
12151 -       {0x0000a260, 0x3a021501, 0x3a021501, 0x3a021501, 0x3a021501},
12152 -       {0x0000a264, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e},
12153 -       {0x0000a280, 0x00000007, 0x00000007, 0x0000000b, 0x0000000b},
12154 -       {0x0000a284, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
12155 -       {0x0000a288, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
12156 -       {0x0000a28c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
12157 -       {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
12158 -       {0x0000a2d0, 0x00071981, 0x00071981, 0x00071981, 0x00071981},
12159 -       {0x0000a2d8, 0xf999a83a, 0xf999a83a, 0xf999a83a, 0xf999a83a},
12160 -       {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
12161 -       {0x0000ae04, 0x00802020, 0x00802020, 0x00802020, 0x00802020},
12162 -       {0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
12163 -};
12164 -
12165  static const u32 ar9331_1p2_radio_core[][2] = {
12166         /* Addr      allmodes  */
12167         {0x00016000, 0x36db6db6},
12168 @@ -219,24 +190,318 @@ static const u32 ar9331_1p2_radio_core[]
12169         {0x000163d4, 0x00000000},
12170  };
12171
12172 -#define ar9331_1p2_baseband_core_txfir_coeff_japan_2484 ar9331_1p1_baseband_core_txfir_coeff_japan_2484
12173 -
12174 -#define ar9331_1p2_xtal_25M ar9331_1p1_xtal_25M
12175 -
12176 -#define ar9331_1p2_xtal_40M ar9331_1p1_xtal_40M
12177 -
12178 -#define ar9331_1p2_baseband_core ar9331_1p1_baseband_core
12179 -
12180 -#define ar9331_1p2_soc_postamble ar9331_1p1_soc_postamble
12181 -
12182 -#define ar9331_1p2_mac_postamble ar9331_1p1_mac_postamble
12183 -
12184 -#define ar9331_1p2_soc_preamble ar9331_1p1_soc_preamble
12185 -
12186 -#define ar9331_1p2_mac_core ar9331_1p1_mac_core
12187 +static const u32 ar9331_1p2_baseband_core[][2] = {
12188 +       /* Addr      allmodes  */
12189 +       {0x00009800, 0xafe68e30},
12190 +       {0x00009804, 0xfd14e000},
12191 +       {0x00009808, 0x9c0a8f6b},
12192 +       {0x0000980c, 0x04800000},
12193 +       {0x00009814, 0x9280c00a},
12194 +       {0x00009818, 0x00000000},
12195 +       {0x0000981c, 0x00020028},
12196 +       {0x00009834, 0x5f3ca3de},
12197 +       {0x00009838, 0x0108ecff},
12198 +       {0x0000983c, 0x14750600},
12199 +       {0x00009880, 0x201fff00},
12200 +       {0x00009884, 0x00001042},
12201 +       {0x000098a4, 0x00200400},
12202 +       {0x000098b0, 0x32840bbe},
12203 +       {0x000098d0, 0x004b6a8e},
12204 +       {0x000098d4, 0x00000820},
12205 +       {0x000098dc, 0x00000000},
12206 +       {0x000098f0, 0x00000000},
12207 +       {0x000098f4, 0x00000000},
12208 +       {0x00009c04, 0x00000000},
12209 +       {0x00009c08, 0x03200000},
12210 +       {0x00009c0c, 0x00000000},
12211 +       {0x00009c10, 0x00000000},
12212 +       {0x00009c14, 0x00046384},
12213 +       {0x00009c18, 0x05b6b440},
12214 +       {0x00009c1c, 0x00b6b440},
12215 +       {0x00009d00, 0xc080a333},
12216 +       {0x00009d04, 0x40206c10},
12217 +       {0x00009d08, 0x009c4060},
12218 +       {0x00009d0c, 0x1883800a},
12219 +       {0x00009d10, 0x01834061},
12220 +       {0x00009d14, 0x00c00400},
12221 +       {0x00009d18, 0x00000000},
12222 +       {0x00009e08, 0x0038233c},
12223 +       {0x00009e24, 0x9927b515},
12224 +       {0x00009e28, 0x12ef0200},
12225 +       {0x00009e30, 0x06336f77},
12226 +       {0x00009e34, 0x6af6532f},
12227 +       {0x00009e38, 0x0cc80c00},
12228 +       {0x00009e40, 0x0d261820},
12229 +       {0x00009e4c, 0x00001004},
12230 +       {0x00009e50, 0x00ff03f1},
12231 +       {0x00009fc0, 0x803e4788},
12232 +       {0x00009fc4, 0x0001efb5},
12233 +       {0x00009fcc, 0x40000014},
12234 +       {0x0000a20c, 0x00000000},
12235 +       {0x0000a220, 0x00000000},
12236 +       {0x0000a224, 0x00000000},
12237 +       {0x0000a228, 0x10002310},
12238 +       {0x0000a23c, 0x00000000},
12239 +       {0x0000a244, 0x0c000000},
12240 +       {0x0000a2a0, 0x00000001},
12241 +       {0x0000a2c0, 0x00000001},
12242 +       {0x0000a2c8, 0x00000000},
12243 +       {0x0000a2cc, 0x18c43433},
12244 +       {0x0000a2d4, 0x00000000},
12245 +       {0x0000a2dc, 0x00000000},
12246 +       {0x0000a2e0, 0x00000000},
12247 +       {0x0000a2e4, 0x00000000},
12248 +       {0x0000a2e8, 0x00000000},
12249 +       {0x0000a2ec, 0x00000000},
12250 +       {0x0000a2f0, 0x00000000},
12251 +       {0x0000a2f4, 0x00000000},
12252 +       {0x0000a2f8, 0x00000000},
12253 +       {0x0000a344, 0x00000000},
12254 +       {0x0000a34c, 0x00000000},
12255 +       {0x0000a350, 0x0000a000},
12256 +       {0x0000a364, 0x00000000},
12257 +       {0x0000a370, 0x00000000},
12258 +       {0x0000a390, 0x00000001},
12259 +       {0x0000a394, 0x00000444},
12260 +       {0x0000a398, 0x001f0e0f},
12261 +       {0x0000a39c, 0x0075393f},
12262 +       {0x0000a3a0, 0xb79f6427},
12263 +       {0x0000a3a4, 0x00000000},
12264 +       {0x0000a3a8, 0xaaaaaaaa},
12265 +       {0x0000a3ac, 0x3c466478},
12266 +       {0x0000a3c0, 0x20202020},
12267 +       {0x0000a3c4, 0x22222220},
12268 +       {0x0000a3c8, 0x20200020},
12269 +       {0x0000a3cc, 0x20202020},
12270 +       {0x0000a3d0, 0x20202020},
12271 +       {0x0000a3d4, 0x20202020},
12272 +       {0x0000a3d8, 0x20202020},
12273 +       {0x0000a3dc, 0x20202020},
12274 +       {0x0000a3e0, 0x20202020},
12275 +       {0x0000a3e4, 0x20202020},
12276 +       {0x0000a3e8, 0x20202020},
12277 +       {0x0000a3ec, 0x20202020},
12278 +       {0x0000a3f0, 0x00000000},
12279 +       {0x0000a3f4, 0x00000006},
12280 +       {0x0000a3f8, 0x0cdbd380},
12281 +       {0x0000a3fc, 0x000f0f01},
12282 +       {0x0000a400, 0x8fa91f01},
12283 +       {0x0000a404, 0x00000000},
12284 +       {0x0000a408, 0x0e79e5c6},
12285 +       {0x0000a40c, 0x00820820},
12286 +       {0x0000a414, 0x1ce739ce},
12287 +       {0x0000a418, 0x2d001dce},
12288 +       {0x0000a41c, 0x1ce739ce},
12289 +       {0x0000a420, 0x000001ce},
12290 +       {0x0000a424, 0x1ce739ce},
12291 +       {0x0000a428, 0x000001ce},
12292 +       {0x0000a42c, 0x1ce739ce},
12293 +       {0x0000a430, 0x1ce739ce},
12294 +       {0x0000a434, 0x00000000},
12295 +       {0x0000a438, 0x00001801},
12296 +       {0x0000a43c, 0x00000000},
12297 +       {0x0000a440, 0x00000000},
12298 +       {0x0000a444, 0x00000000},
12299 +       {0x0000a448, 0x04000000},
12300 +       {0x0000a44c, 0x00000001},
12301 +       {0x0000a450, 0x00010000},
12302 +       {0x0000a458, 0x00000000},
12303 +       {0x0000a640, 0x00000000},
12304 +       {0x0000a644, 0x3fad9d74},
12305 +       {0x0000a648, 0x0048060a},
12306 +       {0x0000a64c, 0x00003c37},
12307 +       {0x0000a670, 0x03020100},
12308 +       {0x0000a674, 0x09080504},
12309 +       {0x0000a678, 0x0d0c0b0a},
12310 +       {0x0000a67c, 0x13121110},
12311 +       {0x0000a680, 0x31301514},
12312 +       {0x0000a684, 0x35343332},
12313 +       {0x0000a688, 0x00000036},
12314 +       {0x0000a690, 0x00000838},
12315 +       {0x0000a7c0, 0x00000000},
12316 +       {0x0000a7c4, 0xfffffffc},
12317 +       {0x0000a7c8, 0x00000000},
12318 +       {0x0000a7cc, 0x00000000},
12319 +       {0x0000a7d0, 0x00000000},
12320 +       {0x0000a7d4, 0x00000004},
12321 +       {0x0000a7dc, 0x00000001},
12322 +};
12323
12324 -#define ar9331_common_wo_xlna_rx_gain_1p2 ar9331_common_wo_xlna_rx_gain_1p1
12325 +static const u32 ar9331_1p2_baseband_postamble[][5] = {
12326 +       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
12327 +       {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8005, 0xd00a8005},
12328 +       {0x00009820, 0x206a002e, 0x206a002e, 0x206a002e, 0x206a002e},
12329 +       {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0},
12330 +       {0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881},
12331 +       {0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4},
12332 +       {0x00009830, 0x0000059c, 0x0000059c, 0x0000059c, 0x0000059c},
12333 +       {0x00009c00, 0x00000044, 0x00000044, 0x00000044, 0x00000044},
12334 +       {0x00009e00, 0x0372161e, 0x0372161e, 0x037216a4, 0x037216a4},
12335 +       {0x00009e04, 0x00182020, 0x00182020, 0x00182020, 0x00182020},
12336 +       {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2},
12337 +       {0x00009e10, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e},
12338 +       {0x00009e14, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e},
12339 +       {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
12340 +       {0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c},
12341 +       {0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce},
12342 +       {0x00009e2c, 0x0000001c, 0x0000001c, 0x00003221, 0x00003221},
12343 +       {0x00009e3c, 0xcf946222, 0xcf946222, 0xcf946222, 0xcf946222},
12344 +       {0x00009e44, 0x02321e27, 0x02321e27, 0x02282324, 0x02282324},
12345 +       {0x00009e48, 0x5030201a, 0x5030201a, 0x50302010, 0x50302010},
12346 +       {0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000},
12347 +       {0x0000a204, 0x00003fc0, 0x00003fc4, 0x00003fc4, 0x00003fc0},
12348 +       {0x0000a208, 0x00000104, 0x00000104, 0x00000004, 0x00000004},
12349 +       {0x0000a230, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b},
12350 +       {0x0000a234, 0x00000fff, 0x00000fff, 0x10000fff, 0x00000fff},
12351 +       {0x0000a238, 0xffb81018, 0xffb81018, 0xffb81018, 0xffb81018},
12352 +       {0x0000a250, 0x00000000, 0x00000000, 0x00000210, 0x00000108},
12353 +       {0x0000a254, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898},
12354 +       {0x0000a258, 0x02020002, 0x02020002, 0x02020002, 0x02020002},
12355 +       {0x0000a25c, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e},
12356 +       {0x0000a260, 0x3a021501, 0x3a021501, 0x3a021501, 0x3a021501},
12357 +       {0x0000a264, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e},
12358 +       {0x0000a280, 0x00000007, 0x00000007, 0x0000000b, 0x0000000b},
12359 +       {0x0000a284, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
12360 +       {0x0000a288, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
12361 +       {0x0000a28c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
12362 +       {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
12363 +       {0x0000a2d0, 0x00071981, 0x00071981, 0x00071981, 0x00071981},
12364 +       {0x0000a2d8, 0xf999a83a, 0xf999a83a, 0xf999a83a, 0xf999a83a},
12365 +       {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
12366 +       {0x0000ae04, 0x00802020, 0x00802020, 0x00802020, 0x00802020},
12367 +       {0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
12368 +};
12369
12370 -#define ar9331_common_rx_gain_1p2 ar9485_common_rx_gain_1_1
12371 +static const u32 ar9331_common_rx_gain_1p2[][2] = {
12372 +       /* Addr      allmodes  */
12373 +       {0x0000a000, 0x00010000},
12374 +       {0x0000a004, 0x00030002},
12375 +       {0x0000a008, 0x00050004},
12376 +       {0x0000a00c, 0x00810080},
12377 +       {0x0000a010, 0x01800082},
12378 +       {0x0000a014, 0x01820181},
12379 +       {0x0000a018, 0x01840183},
12380 +       {0x0000a01c, 0x01880185},
12381 +       {0x0000a020, 0x018a0189},
12382 +       {0x0000a024, 0x02850284},
12383 +       {0x0000a028, 0x02890288},
12384 +       {0x0000a02c, 0x03850384},
12385 +       {0x0000a030, 0x03890388},
12386 +       {0x0000a034, 0x038b038a},
12387 +       {0x0000a038, 0x038d038c},
12388 +       {0x0000a03c, 0x03910390},
12389 +       {0x0000a040, 0x03930392},
12390 +       {0x0000a044, 0x03950394},
12391 +       {0x0000a048, 0x00000396},
12392 +       {0x0000a04c, 0x00000000},
12393 +       {0x0000a050, 0x00000000},
12394 +       {0x0000a054, 0x00000000},
12395 +       {0x0000a058, 0x00000000},
12396 +       {0x0000a05c, 0x00000000},
12397 +       {0x0000a060, 0x00000000},
12398 +       {0x0000a064, 0x00000000},
12399 +       {0x0000a068, 0x00000000},
12400 +       {0x0000a06c, 0x00000000},
12401 +       {0x0000a070, 0x00000000},
12402 +       {0x0000a074, 0x00000000},
12403 +       {0x0000a078, 0x00000000},
12404 +       {0x0000a07c, 0x00000000},
12405 +       {0x0000a080, 0x28282828},
12406 +       {0x0000a084, 0x28282828},
12407 +       {0x0000a088, 0x28282828},
12408 +       {0x0000a08c, 0x28282828},
12409 +       {0x0000a090, 0x28282828},
12410 +       {0x0000a094, 0x21212128},
12411 +       {0x0000a098, 0x171c1c1c},
12412 +       {0x0000a09c, 0x02020212},
12413 +       {0x0000a0a0, 0x00000202},
12414 +       {0x0000a0a4, 0x00000000},
12415 +       {0x0000a0a8, 0x00000000},
12416 +       {0x0000a0ac, 0x00000000},
12417 +       {0x0000a0b0, 0x00000000},
12418 +       {0x0000a0b4, 0x00000000},
12419 +       {0x0000a0b8, 0x00000000},
12420 +       {0x0000a0bc, 0x00000000},
12421 +       {0x0000a0c0, 0x001f0000},
12422 +       {0x0000a0c4, 0x111f1100},
12423 +       {0x0000a0c8, 0x111d111e},
12424 +       {0x0000a0cc, 0x111b111c},
12425 +       {0x0000a0d0, 0x22032204},
12426 +       {0x0000a0d4, 0x22012202},
12427 +       {0x0000a0d8, 0x221f2200},
12428 +       {0x0000a0dc, 0x221d221e},
12429 +       {0x0000a0e0, 0x33013302},
12430 +       {0x0000a0e4, 0x331f3300},
12431 +       {0x0000a0e8, 0x4402331e},
12432 +       {0x0000a0ec, 0x44004401},
12433 +       {0x0000a0f0, 0x441e441f},
12434 +       {0x0000a0f4, 0x55015502},
12435 +       {0x0000a0f8, 0x551f5500},
12436 +       {0x0000a0fc, 0x6602551e},
12437 +       {0x0000a100, 0x66006601},
12438 +       {0x0000a104, 0x661e661f},
12439 +       {0x0000a108, 0x7703661d},
12440 +       {0x0000a10c, 0x77017702},
12441 +       {0x0000a110, 0x00007700},
12442 +       {0x0000a114, 0x00000000},
12443 +       {0x0000a118, 0x00000000},
12444 +       {0x0000a11c, 0x00000000},
12445 +       {0x0000a120, 0x00000000},
12446 +       {0x0000a124, 0x00000000},
12447 +       {0x0000a128, 0x00000000},
12448 +       {0x0000a12c, 0x00000000},
12449 +       {0x0000a130, 0x00000000},
12450 +       {0x0000a134, 0x00000000},
12451 +       {0x0000a138, 0x00000000},
12452 +       {0x0000a13c, 0x00000000},
12453 +       {0x0000a140, 0x001f0000},
12454 +       {0x0000a144, 0x111f1100},
12455 +       {0x0000a148, 0x111d111e},
12456 +       {0x0000a14c, 0x111b111c},
12457 +       {0x0000a150, 0x22032204},
12458 +       {0x0000a154, 0x22012202},
12459 +       {0x0000a158, 0x221f2200},
12460 +       {0x0000a15c, 0x221d221e},
12461 +       {0x0000a160, 0x33013302},
12462 +       {0x0000a164, 0x331f3300},
12463 +       {0x0000a168, 0x4402331e},
12464 +       {0x0000a16c, 0x44004401},
12465 +       {0x0000a170, 0x441e441f},
12466 +       {0x0000a174, 0x55015502},
12467 +       {0x0000a178, 0x551f5500},
12468 +       {0x0000a17c, 0x6602551e},
12469 +       {0x0000a180, 0x66006601},
12470 +       {0x0000a184, 0x661e661f},
12471 +       {0x0000a188, 0x7703661d},
12472 +       {0x0000a18c, 0x77017702},
12473 +       {0x0000a190, 0x00007700},
12474 +       {0x0000a194, 0x00000000},
12475 +       {0x0000a198, 0x00000000},
12476 +       {0x0000a19c, 0x00000000},
12477 +       {0x0000a1a0, 0x00000000},
12478 +       {0x0000a1a4, 0x00000000},
12479 +       {0x0000a1a8, 0x00000000},
12480 +       {0x0000a1ac, 0x00000000},
12481 +       {0x0000a1b0, 0x00000000},
12482 +       {0x0000a1b4, 0x00000000},
12483 +       {0x0000a1b8, 0x00000000},
12484 +       {0x0000a1bc, 0x00000000},
12485 +       {0x0000a1c0, 0x00000000},
12486 +       {0x0000a1c4, 0x00000000},
12487 +       {0x0000a1c8, 0x00000000},
12488 +       {0x0000a1cc, 0x00000000},
12489 +       {0x0000a1d0, 0x00000000},
12490 +       {0x0000a1d4, 0x00000000},
12491 +       {0x0000a1d8, 0x00000000},
12492 +       {0x0000a1dc, 0x00000000},
12493 +       {0x0000a1e0, 0x00000000},
12494 +       {0x0000a1e4, 0x00000000},
12495 +       {0x0000a1e8, 0x00000000},
12496 +       {0x0000a1ec, 0x00000000},
12497 +       {0x0000a1f0, 0x00000396},
12498 +       {0x0000a1f4, 0x00000396},
12499 +       {0x0000a1f8, 0x00000396},
12500 +       {0x0000a1fc, 0x00000296},
12501 +};
12502
12503  #endif /* INITVALS_9330_1P2_H */
12504 --- a/drivers/net/wireless/ath/ath9k/ar955x_1p0_initvals.h
12505 +++ b/drivers/net/wireless/ath/ath9k/ar955x_1p0_initvals.h
12506 @@ -20,6 +20,14 @@
12507
12508  /* AR955X 1.0 */
12509
12510 +#define ar955x_1p0_soc_postamble ar9300_2p2_soc_postamble
12511 +
12512 +#define ar955x_1p0_common_rx_gain_table ar9300Common_rx_gain_table_2p2
12513 +
12514 +#define ar955x_1p0_common_wo_xlna_rx_gain_table ar9300Common_wo_xlna_rx_gain_table_2p2
12515 +
12516 +#define ar955x_1p0_baseband_core_txfir_coeff_japan_2484 ar9300_2p2_baseband_core_txfir_coeff_japan_2484
12517 +
12518  static const u32 ar955x_1p0_radio_postamble[][5] = {
12519         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
12520         {0x00016098, 0xd2dd5554, 0xd2dd5554, 0xd28b3330, 0xd28b3330},
12521 @@ -37,13 +45,6 @@ static const u32 ar955x_1p0_radio_postam
12522         {0x00016940, 0x10804008, 0x10804008, 0x10804008, 0x10804008},
12523  };
12524
12525 -static const u32 ar955x_1p0_baseband_core_txfir_coeff_japan_2484[][2] = {
12526 -       /* Addr      allmodes  */
12527 -       {0x0000a398, 0x00000000},
12528 -       {0x0000a39c, 0x6f7f0301},
12529 -       {0x0000a3a0, 0xca9228ee},
12530 -};
12531 -
12532  static const u32 ar955x_1p0_baseband_postamble[][5] = {
12533         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
12534         {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a8011},
12535 @@ -473,266 +474,6 @@ static const u32 ar955x_1p0_mac_core[][2
12536         {0x000083d0, 0x8c7901ff},
12537  };
12538
12539 -static const u32 ar955x_1p0_common_rx_gain_table[][2] = {
12540 -       /* Addr      allmodes  */
12541 -       {0x0000a000, 0x00010000},
12542 -       {0x0000a004, 0x00030002},
12543 -       {0x0000a008, 0x00050004},
12544 -       {0x0000a00c, 0x00810080},
12545 -       {0x0000a010, 0x00830082},
12546 -       {0x0000a014, 0x01810180},
12547 -       {0x0000a018, 0x01830182},
12548 -       {0x0000a01c, 0x01850184},
12549 -       {0x0000a020, 0x01890188},
12550 -       {0x0000a024, 0x018b018a},
12551 -       {0x0000a028, 0x018d018c},
12552 -       {0x0000a02c, 0x01910190},
12553 -       {0x0000a030, 0x01930192},
12554 -       {0x0000a034, 0x01950194},
12555 -       {0x0000a038, 0x038a0196},
12556 -       {0x0000a03c, 0x038c038b},
12557 -       {0x0000a040, 0x0390038d},
12558 -       {0x0000a044, 0x03920391},
12559 -       {0x0000a048, 0x03940393},
12560 -       {0x0000a04c, 0x03960395},
12561 -       {0x0000a050, 0x00000000},
12562 -       {0x0000a054, 0x00000000},
12563 -       {0x0000a058, 0x00000000},
12564 -       {0x0000a05c, 0x00000000},
12565 -       {0x0000a060, 0x00000000},
12566 -       {0x0000a064, 0x00000000},
12567 -       {0x0000a068, 0x00000000},
12568 -       {0x0000a06c, 0x00000000},
12569 -       {0x0000a070, 0x00000000},
12570 -       {0x0000a074, 0x00000000},
12571 -       {0x0000a078, 0x00000000},
12572 -       {0x0000a07c, 0x00000000},
12573 -       {0x0000a080, 0x22222229},
12574 -       {0x0000a084, 0x1d1d1d1d},
12575 -       {0x0000a088, 0x1d1d1d1d},
12576 -       {0x0000a08c, 0x1d1d1d1d},
12577 -       {0x0000a090, 0x171d1d1d},
12578 -       {0x0000a094, 0x11111717},
12579 -       {0x0000a098, 0x00030311},
12580 -       {0x0000a09c, 0x00000000},
12581 -       {0x0000a0a0, 0x00000000},
12582 -       {0x0000a0a4, 0x00000000},
12583 -       {0x0000a0a8, 0x00000000},
12584 -       {0x0000a0ac, 0x00000000},
12585 -       {0x0000a0b0, 0x00000000},
12586 -       {0x0000a0b4, 0x00000000},
12587 -       {0x0000a0b8, 0x00000000},
12588 -       {0x0000a0bc, 0x00000000},
12589 -       {0x0000a0c0, 0x001f0000},
12590 -       {0x0000a0c4, 0x01000101},
12591 -       {0x0000a0c8, 0x011e011f},
12592 -       {0x0000a0cc, 0x011c011d},
12593 -       {0x0000a0d0, 0x02030204},
12594 -       {0x0000a0d4, 0x02010202},
12595 -       {0x0000a0d8, 0x021f0200},
12596 -       {0x0000a0dc, 0x0302021e},
12597 -       {0x0000a0e0, 0x03000301},
12598 -       {0x0000a0e4, 0x031e031f},
12599 -       {0x0000a0e8, 0x0402031d},
12600 -       {0x0000a0ec, 0x04000401},
12601 -       {0x0000a0f0, 0x041e041f},
12602 -       {0x0000a0f4, 0x0502041d},
12603 -       {0x0000a0f8, 0x05000501},
12604 -       {0x0000a0fc, 0x051e051f},
12605 -       {0x0000a100, 0x06010602},
12606 -       {0x0000a104, 0x061f0600},
12607 -       {0x0000a108, 0x061d061e},
12608 -       {0x0000a10c, 0x07020703},
12609 -       {0x0000a110, 0x07000701},
12610 -       {0x0000a114, 0x00000000},
12611 -       {0x0000a118, 0x00000000},
12612 -       {0x0000a11c, 0x00000000},
12613 -       {0x0000a120, 0x00000000},
12614 -       {0x0000a124, 0x00000000},
12615 -       {0x0000a128, 0x00000000},
12616 -       {0x0000a12c, 0x00000000},
12617 -       {0x0000a130, 0x00000000},
12618 -       {0x0000a134, 0x00000000},
12619 -       {0x0000a138, 0x00000000},
12620 -       {0x0000a13c, 0x00000000},
12621 -       {0x0000a140, 0x001f0000},
12622 -       {0x0000a144, 0x01000101},
12623 -       {0x0000a148, 0x011e011f},
12624 -       {0x0000a14c, 0x011c011d},
12625 -       {0x0000a150, 0x02030204},
12626 -       {0x0000a154, 0x02010202},
12627 -       {0x0000a158, 0x021f0200},
12628 -       {0x0000a15c, 0x0302021e},
12629 -       {0x0000a160, 0x03000301},
12630 -       {0x0000a164, 0x031e031f},
12631 -       {0x0000a168, 0x0402031d},
12632 -       {0x0000a16c, 0x04000401},
12633 -       {0x0000a170, 0x041e041f},
12634 -       {0x0000a174, 0x0502041d},
12635 -       {0x0000a178, 0x05000501},
12636 -       {0x0000a17c, 0x051e051f},
12637 -       {0x0000a180, 0x06010602},
12638 -       {0x0000a184, 0x061f0600},
12639 -       {0x0000a188, 0x061d061e},
12640 -       {0x0000a18c, 0x07020703},
12641 -       {0x0000a190, 0x07000701},
12642 -       {0x0000a194, 0x00000000},
12643 -       {0x0000a198, 0x00000000},
12644 -       {0x0000a19c, 0x00000000},
12645 -       {0x0000a1a0, 0x00000000},
12646 -       {0x0000a1a4, 0x00000000},
12647 -       {0x0000a1a8, 0x00000000},
12648 -       {0x0000a1ac, 0x00000000},
12649 -       {0x0000a1b0, 0x00000000},
12650 -       {0x0000a1b4, 0x00000000},
12651 -       {0x0000a1b8, 0x00000000},
12652 -       {0x0000a1bc, 0x00000000},
12653 -       {0x0000a1c0, 0x00000000},
12654 -       {0x0000a1c4, 0x00000000},
12655 -       {0x0000a1c8, 0x00000000},
12656 -       {0x0000a1cc, 0x00000000},
12657 -       {0x0000a1d0, 0x00000000},
12658 -       {0x0000a1d4, 0x00000000},
12659 -       {0x0000a1d8, 0x00000000},
12660 -       {0x0000a1dc, 0x00000000},
12661 -       {0x0000a1e0, 0x00000000},
12662 -       {0x0000a1e4, 0x00000000},
12663 -       {0x0000a1e8, 0x00000000},
12664 -       {0x0000a1ec, 0x00000000},
12665 -       {0x0000a1f0, 0x00000396},
12666 -       {0x0000a1f4, 0x00000396},
12667 -       {0x0000a1f8, 0x00000396},
12668 -       {0x0000a1fc, 0x00000196},
12669 -       {0x0000b000, 0x00010000},
12670 -       {0x0000b004, 0x00030002},
12671 -       {0x0000b008, 0x00050004},
12672 -       {0x0000b00c, 0x00810080},
12673 -       {0x0000b010, 0x00830082},
12674 -       {0x0000b014, 0x01810180},
12675 -       {0x0000b018, 0x01830182},
12676 -       {0x0000b01c, 0x01850184},
12677 -       {0x0000b020, 0x02810280},
12678 -       {0x0000b024, 0x02830282},
12679 -       {0x0000b028, 0x02850284},
12680 -       {0x0000b02c, 0x02890288},
12681 -       {0x0000b030, 0x028b028a},
12682 -       {0x0000b034, 0x0388028c},
12683 -       {0x0000b038, 0x038a0389},
12684 -       {0x0000b03c, 0x038c038b},
12685 -       {0x0000b040, 0x0390038d},
12686 -       {0x0000b044, 0x03920391},
12687 -       {0x0000b048, 0x03940393},
12688 -       {0x0000b04c, 0x03960395},
12689 -       {0x0000b050, 0x00000000},
12690 -       {0x0000b054, 0x00000000},
12691 -       {0x0000b058, 0x00000000},
12692 -       {0x0000b05c, 0x00000000},
12693 -       {0x0000b060, 0x00000000},
12694 -       {0x0000b064, 0x00000000},
12695 -       {0x0000b068, 0x00000000},
12696 -       {0x0000b06c, 0x00000000},
12697 -       {0x0000b070, 0x00000000},
12698 -       {0x0000b074, 0x00000000},
12699 -       {0x0000b078, 0x00000000},
12700 -       {0x0000b07c, 0x00000000},
12701 -       {0x0000b080, 0x23232323},
12702 -       {0x0000b084, 0x21232323},
12703 -       {0x0000b088, 0x19191c1e},
12704 -       {0x0000b08c, 0x12141417},
12705 -       {0x0000b090, 0x07070e0e},
12706 -       {0x0000b094, 0x03030305},
12707 -       {0x0000b098, 0x00000003},
12708 -       {0x0000b09c, 0x00000000},
12709 -       {0x0000b0a0, 0x00000000},
12710 -       {0x0000b0a4, 0x00000000},
12711 -       {0x0000b0a8, 0x00000000},
12712 -       {0x0000b0ac, 0x00000000},
12713 -       {0x0000b0b0, 0x00000000},
12714 -       {0x0000b0b4, 0x00000000},
12715 -       {0x0000b0b8, 0x00000000},
12716 -       {0x0000b0bc, 0x00000000},
12717 -       {0x0000b0c0, 0x003f0020},
12718 -       {0x0000b0c4, 0x00400041},
12719 -       {0x0000b0c8, 0x0140005f},
12720 -       {0x0000b0cc, 0x0160015f},
12721 -       {0x0000b0d0, 0x017e017f},
12722 -       {0x0000b0d4, 0x02410242},
12723 -       {0x0000b0d8, 0x025f0240},
12724 -       {0x0000b0dc, 0x027f0260},
12725 -       {0x0000b0e0, 0x0341027e},
12726 -       {0x0000b0e4, 0x035f0340},
12727 -       {0x0000b0e8, 0x037f0360},
12728 -       {0x0000b0ec, 0x04400441},
12729 -       {0x0000b0f0, 0x0460045f},
12730 -       {0x0000b0f4, 0x0541047f},
12731 -       {0x0000b0f8, 0x055f0540},
12732 -       {0x0000b0fc, 0x057f0560},
12733 -       {0x0000b100, 0x06400641},
12734 -       {0x0000b104, 0x0660065f},
12735 -       {0x0000b108, 0x067e067f},
12736 -       {0x0000b10c, 0x07410742},
12737 -       {0x0000b110, 0x075f0740},
12738 -       {0x0000b114, 0x077f0760},
12739 -       {0x0000b118, 0x07800781},
12740 -       {0x0000b11c, 0x07a0079f},
12741 -       {0x0000b120, 0x07c107bf},
12742 -       {0x0000b124, 0x000007c0},
12743 -       {0x0000b128, 0x00000000},
12744 -       {0x0000b12c, 0x00000000},
12745 -       {0x0000b130, 0x00000000},
12746 -       {0x0000b134, 0x00000000},
12747 -       {0x0000b138, 0x00000000},
12748 -       {0x0000b13c, 0x00000000},
12749 -       {0x0000b140, 0x003f0020},
12750 -       {0x0000b144, 0x00400041},
12751 -       {0x0000b148, 0x0140005f},
12752 -       {0x0000b14c, 0x0160015f},
12753 -       {0x0000b150, 0x017e017f},
12754 -       {0x0000b154, 0x02410242},
12755 -       {0x0000b158, 0x025f0240},
12756 -       {0x0000b15c, 0x027f0260},
12757 -       {0x0000b160, 0x0341027e},
12758 -       {0x0000b164, 0x035f0340},
12759 -       {0x0000b168, 0x037f0360},
12760 -       {0x0000b16c, 0x04400441},
12761 -       {0x0000b170, 0x0460045f},
12762 -       {0x0000b174, 0x0541047f},
12763 -       {0x0000b178, 0x055f0540},
12764 -       {0x0000b17c, 0x057f0560},
12765 -       {0x0000b180, 0x06400641},
12766 -       {0x0000b184, 0x0660065f},
12767 -       {0x0000b188, 0x067e067f},
12768 -       {0x0000b18c, 0x07410742},
12769 -       {0x0000b190, 0x075f0740},
12770 -       {0x0000b194, 0x077f0760},
12771 -       {0x0000b198, 0x07800781},
12772 -       {0x0000b19c, 0x07a0079f},
12773 -       {0x0000b1a0, 0x07c107bf},
12774 -       {0x0000b1a4, 0x000007c0},
12775 -       {0x0000b1a8, 0x00000000},
12776 -       {0x0000b1ac, 0x00000000},
12777 -       {0x0000b1b0, 0x00000000},
12778 -       {0x0000b1b4, 0x00000000},
12779 -       {0x0000b1b8, 0x00000000},
12780 -       {0x0000b1bc, 0x00000000},
12781 -       {0x0000b1c0, 0x00000000},
12782 -       {0x0000b1c4, 0x00000000},
12783 -       {0x0000b1c8, 0x00000000},
12784 -       {0x0000b1cc, 0x00000000},
12785 -       {0x0000b1d0, 0x00000000},
12786 -       {0x0000b1d4, 0x00000000},
12787 -       {0x0000b1d8, 0x00000000},
12788 -       {0x0000b1dc, 0x00000000},
12789 -       {0x0000b1e0, 0x00000000},
12790 -       {0x0000b1e4, 0x00000000},
12791 -       {0x0000b1e8, 0x00000000},
12792 -       {0x0000b1ec, 0x00000000},
12793 -       {0x0000b1f0, 0x00000396},
12794 -       {0x0000b1f4, 0x00000396},
12795 -       {0x0000b1f8, 0x00000396},
12796 -       {0x0000b1fc, 0x00000196},
12797 -};
12798 -
12799  static const u32 ar955x_1p0_baseband_core[][2] = {
12800         /* Addr      allmodes  */
12801         {0x00009800, 0xafe68e30},
12802 @@ -891,266 +632,6 @@ static const u32 ar955x_1p0_baseband_cor
12803         {0x0000c420, 0x00000000},
12804  };
12805
12806 -static const u32 ar955x_1p0_common_wo_xlna_rx_gain_table[][2] = {
12807 -       /* Addr      allmodes  */
12808 -       {0x0000a000, 0x00010000},
12809 -       {0x0000a004, 0x00030002},
12810 -       {0x0000a008, 0x00050004},
12811 -       {0x0000a00c, 0x00810080},
12812 -       {0x0000a010, 0x00830082},
12813 -       {0x0000a014, 0x01810180},
12814 -       {0x0000a018, 0x01830182},
12815 -       {0x0000a01c, 0x01850184},
12816 -       {0x0000a020, 0x01890188},
12817 -       {0x0000a024, 0x018b018a},
12818 -       {0x0000a028, 0x018d018c},
12819 -       {0x0000a02c, 0x03820190},
12820 -       {0x0000a030, 0x03840383},
12821 -       {0x0000a034, 0x03880385},
12822 -       {0x0000a038, 0x038a0389},
12823 -       {0x0000a03c, 0x038c038b},
12824 -       {0x0000a040, 0x0390038d},
12825 -       {0x0000a044, 0x03920391},
12826 -       {0x0000a048, 0x03940393},
12827 -       {0x0000a04c, 0x03960395},
12828 -       {0x0000a050, 0x00000000},
12829 -       {0x0000a054, 0x00000000},
12830 -       {0x0000a058, 0x00000000},
12831 -       {0x0000a05c, 0x00000000},
12832 -       {0x0000a060, 0x00000000},
12833 -       {0x0000a064, 0x00000000},
12834 -       {0x0000a068, 0x00000000},
12835 -       {0x0000a06c, 0x00000000},
12836 -       {0x0000a070, 0x00000000},
12837 -       {0x0000a074, 0x00000000},
12838 -       {0x0000a078, 0x00000000},
12839 -       {0x0000a07c, 0x00000000},
12840 -       {0x0000a080, 0x29292929},
12841 -       {0x0000a084, 0x29292929},
12842 -       {0x0000a088, 0x29292929},
12843 -       {0x0000a08c, 0x29292929},
12844 -       {0x0000a090, 0x22292929},
12845 -       {0x0000a094, 0x1d1d2222},
12846 -       {0x0000a098, 0x0c111117},
12847 -       {0x0000a09c, 0x00030303},
12848 -       {0x0000a0a0, 0x00000000},
12849 -       {0x0000a0a4, 0x00000000},
12850 -       {0x0000a0a8, 0x00000000},
12851 -       {0x0000a0ac, 0x00000000},
12852 -       {0x0000a0b0, 0x00000000},
12853 -       {0x0000a0b4, 0x00000000},
12854 -       {0x0000a0b8, 0x00000000},
12855 -       {0x0000a0bc, 0x00000000},
12856 -       {0x0000a0c0, 0x001f0000},
12857 -       {0x0000a0c4, 0x01000101},
12858 -       {0x0000a0c8, 0x011e011f},
12859 -       {0x0000a0cc, 0x011c011d},
12860 -       {0x0000a0d0, 0x02030204},
12861 -       {0x0000a0d4, 0x02010202},
12862 -       {0x0000a0d8, 0x021f0200},
12863 -       {0x0000a0dc, 0x0302021e},
12864 -       {0x0000a0e0, 0x03000301},
12865 -       {0x0000a0e4, 0x031e031f},
12866 -       {0x0000a0e8, 0x0402031d},
12867 -       {0x0000a0ec, 0x04000401},
12868 -       {0x0000a0f0, 0x041e041f},
12869 -       {0x0000a0f4, 0x0502041d},
12870 -       {0x0000a0f8, 0x05000501},
12871 -       {0x0000a0fc, 0x051e051f},
12872 -       {0x0000a100, 0x06010602},
12873 -       {0x0000a104, 0x061f0600},
12874 -       {0x0000a108, 0x061d061e},
12875 -       {0x0000a10c, 0x07020703},
12876 -       {0x0000a110, 0x07000701},
12877 -       {0x0000a114, 0x00000000},
12878 -       {0x0000a118, 0x00000000},
12879 -       {0x0000a11c, 0x00000000},
12880 -       {0x0000a120, 0x00000000},
12881 -       {0x0000a124, 0x00000000},
12882 -       {0x0000a128, 0x00000000},
12883 -       {0x0000a12c, 0x00000000},
12884 -       {0x0000a130, 0x00000000},
12885 -       {0x0000a134, 0x00000000},
12886 -       {0x0000a138, 0x00000000},
12887 -       {0x0000a13c, 0x00000000},
12888 -       {0x0000a140, 0x001f0000},
12889 -       {0x0000a144, 0x01000101},
12890 -       {0x0000a148, 0x011e011f},
12891 -       {0x0000a14c, 0x011c011d},
12892 -       {0x0000a150, 0x02030204},
12893 -       {0x0000a154, 0x02010202},
12894 -       {0x0000a158, 0x021f0200},
12895 -       {0x0000a15c, 0x0302021e},
12896 -       {0x0000a160, 0x03000301},
12897 -       {0x0000a164, 0x031e031f},
12898 -       {0x0000a168, 0x0402031d},
12899 -       {0x0000a16c, 0x04000401},
12900 -       {0x0000a170, 0x041e041f},
12901 -       {0x0000a174, 0x0502041d},
12902 -       {0x0000a178, 0x05000501},
12903 -       {0x0000a17c, 0x051e051f},
12904 -       {0x0000a180, 0x06010602},
12905 -       {0x0000a184, 0x061f0600},
12906 -       {0x0000a188, 0x061d061e},
12907 -       {0x0000a18c, 0x07020703},
12908 -       {0x0000a190, 0x07000701},
12909 -       {0x0000a194, 0x00000000},
12910 -       {0x0000a198, 0x00000000},
12911 -       {0x0000a19c, 0x00000000},
12912 -       {0x0000a1a0, 0x00000000},
12913 -       {0x0000a1a4, 0x00000000},
12914 -       {0x0000a1a8, 0x00000000},
12915 -       {0x0000a1ac, 0x00000000},
12916 -       {0x0000a1b0, 0x00000000},
12917 -       {0x0000a1b4, 0x00000000},
12918 -       {0x0000a1b8, 0x00000000},
12919 -       {0x0000a1bc, 0x00000000},
12920 -       {0x0000a1c0, 0x00000000},
12921 -       {0x0000a1c4, 0x00000000},
12922 -       {0x0000a1c8, 0x00000000},
12923 -       {0x0000a1cc, 0x00000000},
12924 -       {0x0000a1d0, 0x00000000},
12925 -       {0x0000a1d4, 0x00000000},
12926 -       {0x0000a1d8, 0x00000000},
12927 -       {0x0000a1dc, 0x00000000},
12928 -       {0x0000a1e0, 0x00000000},
12929 -       {0x0000a1e4, 0x00000000},
12930 -       {0x0000a1e8, 0x00000000},
12931 -       {0x0000a1ec, 0x00000000},
12932 -       {0x0000a1f0, 0x00000396},
12933 -       {0x0000a1f4, 0x00000396},
12934 -       {0x0000a1f8, 0x00000396},
12935 -       {0x0000a1fc, 0x00000196},
12936 -       {0x0000b000, 0x00010000},
12937 -       {0x0000b004, 0x00030002},
12938 -       {0x0000b008, 0x00050004},
12939 -       {0x0000b00c, 0x00810080},
12940 -       {0x0000b010, 0x00830082},
12941 -       {0x0000b014, 0x01810180},
12942 -       {0x0000b018, 0x01830182},
12943 -       {0x0000b01c, 0x01850184},
12944 -       {0x0000b020, 0x02810280},
12945 -       {0x0000b024, 0x02830282},
12946 -       {0x0000b028, 0x02850284},
12947 -       {0x0000b02c, 0x02890288},
12948 -       {0x0000b030, 0x028b028a},
12949 -       {0x0000b034, 0x0388028c},
12950 -       {0x0000b038, 0x038a0389},
12951 -       {0x0000b03c, 0x038c038b},
12952 -       {0x0000b040, 0x0390038d},
12953 -       {0x0000b044, 0x03920391},
12954 -       {0x0000b048, 0x03940393},
12955 -       {0x0000b04c, 0x03960395},
12956 -       {0x0000b050, 0x00000000},
12957 -       {0x0000b054, 0x00000000},
12958 -       {0x0000b058, 0x00000000},
12959 -       {0x0000b05c, 0x00000000},
12960 -       {0x0000b060, 0x00000000},
12961 -       {0x0000b064, 0x00000000},
12962 -       {0x0000b068, 0x00000000},
12963 -       {0x0000b06c, 0x00000000},
12964 -       {0x0000b070, 0x00000000},
12965 -       {0x0000b074, 0x00000000},
12966 -       {0x0000b078, 0x00000000},
12967 -       {0x0000b07c, 0x00000000},
12968 -       {0x0000b080, 0x32323232},
12969 -       {0x0000b084, 0x2f2f3232},
12970 -       {0x0000b088, 0x23282a2d},
12971 -       {0x0000b08c, 0x1c1e2123},
12972 -       {0x0000b090, 0x14171919},
12973 -       {0x0000b094, 0x0e0e1214},
12974 -       {0x0000b098, 0x03050707},
12975 -       {0x0000b09c, 0x00030303},
12976 -       {0x0000b0a0, 0x00000000},
12977 -       {0x0000b0a4, 0x00000000},
12978 -       {0x0000b0a8, 0x00000000},
12979 -       {0x0000b0ac, 0x00000000},
12980 -       {0x0000b0b0, 0x00000000},
12981 -       {0x0000b0b4, 0x00000000},
12982 -       {0x0000b0b8, 0x00000000},
12983 -       {0x0000b0bc, 0x00000000},
12984 -       {0x0000b0c0, 0x003f0020},
12985 -       {0x0000b0c4, 0x00400041},
12986 -       {0x0000b0c8, 0x0140005f},
12987 -       {0x0000b0cc, 0x0160015f},
12988 -       {0x0000b0d0, 0x017e017f},
12989 -       {0x0000b0d4, 0x02410242},
12990 -       {0x0000b0d8, 0x025f0240},
12991 -       {0x0000b0dc, 0x027f0260},
12992 -       {0x0000b0e0, 0x0341027e},
12993 -       {0x0000b0e4, 0x035f0340},
12994 -       {0x0000b0e8, 0x037f0360},
12995 -       {0x0000b0ec, 0x04400441},
12996 -       {0x0000b0f0, 0x0460045f},
12997 -       {0x0000b0f4, 0x0541047f},
12998 -       {0x0000b0f8, 0x055f0540},
12999 -       {0x0000b0fc, 0x057f0560},
13000 -       {0x0000b100, 0x06400641},
13001 -       {0x0000b104, 0x0660065f},
13002 -       {0x0000b108, 0x067e067f},
13003 -       {0x0000b10c, 0x07410742},
13004 -       {0x0000b110, 0x075f0740},
13005 -       {0x0000b114, 0x077f0760},
13006 -       {0x0000b118, 0x07800781},
13007 -       {0x0000b11c, 0x07a0079f},
13008 -       {0x0000b120, 0x07c107bf},
13009 -       {0x0000b124, 0x000007c0},
13010 -       {0x0000b128, 0x00000000},
13011 -       {0x0000b12c, 0x00000000},
13012 -       {0x0000b130, 0x00000000},
13013 -       {0x0000b134, 0x00000000},
13014 -       {0x0000b138, 0x00000000},
13015 -       {0x0000b13c, 0x00000000},
13016 -       {0x0000b140, 0x003f0020},
13017 -       {0x0000b144, 0x00400041},
13018 -       {0x0000b148, 0x0140005f},
13019 -       {0x0000b14c, 0x0160015f},
13020 -       {0x0000b150, 0x017e017f},
13021 -       {0x0000b154, 0x02410242},
13022 -       {0x0000b158, 0x025f0240},
13023 -       {0x0000b15c, 0x027f0260},
13024 -       {0x0000b160, 0x0341027e},
13025 -       {0x0000b164, 0x035f0340},
13026 -       {0x0000b168, 0x037f0360},
13027 -       {0x0000b16c, 0x04400441},
13028 -       {0x0000b170, 0x0460045f},
13029 -       {0x0000b174, 0x0541047f},
13030 -       {0x0000b178, 0x055f0540},
13031 -       {0x0000b17c, 0x057f0560},
13032 -       {0x0000b180, 0x06400641},
13033 -       {0x0000b184, 0x0660065f},
13034 -       {0x0000b188, 0x067e067f},
13035 -       {0x0000b18c, 0x07410742},
13036 -       {0x0000b190, 0x075f0740},
13037 -       {0x0000b194, 0x077f0760},
13038 -       {0x0000b198, 0x07800781},
13039 -       {0x0000b19c, 0x07a0079f},
13040 -       {0x0000b1a0, 0x07c107bf},
13041 -       {0x0000b1a4, 0x000007c0},
13042 -       {0x0000b1a8, 0x00000000},
13043 -       {0x0000b1ac, 0x00000000},
13044 -       {0x0000b1b0, 0x00000000},
13045 -       {0x0000b1b4, 0x00000000},
13046 -       {0x0000b1b8, 0x00000000},
13047 -       {0x0000b1bc, 0x00000000},
13048 -       {0x0000b1c0, 0x00000000},
13049 -       {0x0000b1c4, 0x00000000},
13050 -       {0x0000b1c8, 0x00000000},
13051 -       {0x0000b1cc, 0x00000000},
13052 -       {0x0000b1d0, 0x00000000},
13053 -       {0x0000b1d4, 0x00000000},
13054 -       {0x0000b1d8, 0x00000000},
13055 -       {0x0000b1dc, 0x00000000},
13056 -       {0x0000b1e0, 0x00000000},
13057 -       {0x0000b1e4, 0x00000000},
13058 -       {0x0000b1e8, 0x00000000},
13059 -       {0x0000b1ec, 0x00000000},
13060 -       {0x0000b1f0, 0x00000396},
13061 -       {0x0000b1f4, 0x00000396},
13062 -       {0x0000b1f8, 0x00000396},
13063 -       {0x0000b1fc, 0x00000196},
13064 -};
13065 -
13066  static const u32 ar955x_1p0_soc_preamble[][2] = {
13067         /* Addr      allmodes  */
13068         {0x00007000, 0x00000000},
13069 @@ -1263,11 +744,6 @@ static const u32 ar955x_1p0_modes_no_xpa
13070         {0x00016848, 0x66482401, 0x66482401, 0x66482401, 0x66482401, 0x66482401, 0x66482401, 0x66482401, 0x66482401},
13071  };
13072
13073 -static const u32 ar955x_1p0_soc_postamble[][5] = {
13074 -       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
13075 -       {0x00007010, 0x00000023, 0x00000023, 0x00000023, 0x00000023},
13076 -};
13077 -
13078  static const u32 ar955x_1p0_modes_fast_clock[][3] = {
13079         /* Addr      5G_HT20     5G_HT40   */
13080         {0x00001030, 0x00000268, 0x000004d0},
13081 --- a/drivers/net/wireless/ath/ath9k/ar9565_1p0_initvals.h
13082 +++ b/drivers/net/wireless/ath/ath9k/ar9565_1p0_initvals.h
13083 @@ -20,6 +20,12 @@
13084
13085  /* AR9565 1.0 */
13086
13087 +#define ar9565_1p0_mac_postamble ar9331_1p1_mac_postamble
13088 +
13089 +#define ar9565_1p0_Modes_lowest_ob_db_tx_gain_table ar9565_1p0_modes_low_ob_db_tx_gain_table
13090 +
13091 +#define ar9565_1p0_baseband_core_txfir_coeff_japan_2484 ar9300_2p2_baseband_core_txfir_coeff_japan_2484
13092 +
13093  static const u32 ar9565_1p0_mac_core[][2] = {
13094         /* Addr      allmodes  */
13095         {0x00000008, 0x00000000},
13096 @@ -182,18 +188,6 @@ static const u32 ar9565_1p0_mac_core[][2
13097         {0x000083d0, 0x800301ff},
13098  };
13099
13100 -static const u32 ar9565_1p0_mac_postamble[][5] = {
13101 -       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
13102 -       {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
13103 -       {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
13104 -       {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
13105 -       {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
13106 -       {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b},
13107 -       {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
13108 -       {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
13109 -       {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
13110 -};
13111 -
13112  static const u32 ar9565_1p0_baseband_core[][2] = {
13113         /* Addr      allmodes  */
13114         {0x00009800, 0xafe68e30},
13115 @@ -711,66 +705,6 @@ static const u32 ar9565_1p0_Common_rx_ga
13116         {0x0000b1fc, 0x00000196},
13117  };
13118
13119 -static const u32 ar9565_1p0_Modes_lowest_ob_db_tx_gain_table[][5] = {
13120 -       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
13121 -       {0x0000a2dc, 0xfc0a9380, 0xfc0a9380, 0xfdab5b52, 0xfdab5b52},
13122 -       {0x0000a2e0, 0xffecec00, 0xffecec00, 0xfd339c84, 0xfd339c84},
13123 -       {0x0000a2e4, 0xfc0f0000, 0xfc0f0000, 0xfec3e000, 0xfec3e000},
13124 -       {0x0000a2e8, 0xfc100000, 0xfc100000, 0xfffc0000, 0xfffc0000},
13125 -       {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
13126 -       {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
13127 -       {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
13128 -       {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004},
13129 -       {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
13130 -       {0x0000a510, 0x16000220, 0x16000220, 0x0f000202, 0x0f000202},
13131 -       {0x0000a514, 0x1c000223, 0x1c000223, 0x12000400, 0x12000400},
13132 -       {0x0000a518, 0x21020220, 0x21020220, 0x16000402, 0x16000402},
13133 -       {0x0000a51c, 0x27020223, 0x27020223, 0x19000404, 0x19000404},
13134 -       {0x0000a520, 0x2b022220, 0x2b022220, 0x1c000603, 0x1c000603},
13135 -       {0x0000a524, 0x2f022222, 0x2f022222, 0x21000a02, 0x21000a02},
13136 -       {0x0000a528, 0x34022225, 0x34022225, 0x25000a04, 0x25000a04},
13137 -       {0x0000a52c, 0x3a02222a, 0x3a02222a, 0x28000a20, 0x28000a20},
13138 -       {0x0000a530, 0x3e02222c, 0x3e02222c, 0x2c000e20, 0x2c000e20},
13139 -       {0x0000a534, 0x4202242a, 0x4202242a, 0x30000e22, 0x30000e22},
13140 -       {0x0000a538, 0x4702244a, 0x4702244a, 0x34000e24, 0x34000e24},
13141 -       {0x0000a53c, 0x4b02244c, 0x4b02244c, 0x38001640, 0x38001640},
13142 -       {0x0000a540, 0x4e02246c, 0x4e02246c, 0x3c001660, 0x3c001660},
13143 -       {0x0000a544, 0x5302266c, 0x5302266c, 0x3f001861, 0x3f001861},
13144 -       {0x0000a548, 0x5702286c, 0x5702286c, 0x43001a81, 0x43001a81},
13145 -       {0x0000a54c, 0x5c04286b, 0x5c04286b, 0x47001a83, 0x47001a83},
13146 -       {0x0000a550, 0x61042a6c, 0x61042a6c, 0x4a001c84, 0x4a001c84},
13147 -       {0x0000a554, 0x66062a6c, 0x66062a6c, 0x4e001ce3, 0x4e001ce3},
13148 -       {0x0000a558, 0x6b062e6c, 0x6b062e6c, 0x52001ce5, 0x52001ce5},
13149 -       {0x0000a55c, 0x7006308c, 0x7006308c, 0x56001ce9, 0x56001ce9},
13150 -       {0x0000a560, 0x730a308a, 0x730a308a, 0x5a001ceb, 0x5a001ceb},
13151 -       {0x0000a564, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
13152 -       {0x0000a568, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
13153 -       {0x0000a56c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
13154 -       {0x0000a570, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
13155 -       {0x0000a574, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
13156 -       {0x0000a578, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
13157 -       {0x0000a57c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
13158 -       {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
13159 -       {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
13160 -       {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
13161 -       {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
13162 -       {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
13163 -       {0x0000a614, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
13164 -       {0x0000a618, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
13165 -       {0x0000a61c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
13166 -       {0x0000a620, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
13167 -       {0x0000a624, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
13168 -       {0x0000a628, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
13169 -       {0x0000a62c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
13170 -       {0x0000a630, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
13171 -       {0x0000a634, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
13172 -       {0x0000a638, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
13173 -       {0x0000a63c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
13174 -       {0x00016044, 0x012482d4, 0x012482d4, 0x012482d4, 0x012482d4},
13175 -       {0x00016048, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
13176 -       {0x00016054, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
13177 -};
13178 -
13179  static const u32 ar9565_1p0_pciephy_clkreq_disable_L1[][2] = {
13180         /* Addr      allmodes  */
13181         {0x00018c00, 0x18212ede},
13182 @@ -1231,11 +1165,4 @@ static const u32 ar9565_1p0_modes_high_p
13183         {0x00016054, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
13184  };
13185
13186 -static const u32 ar9565_1p0_baseband_core_txfir_coeff_japan_2484[][2] = {
13187 -       /* Addr      allmodes  */
13188 -       {0x0000a398, 0x00000000},
13189 -       {0x0000a39c, 0x6f7f0301},
13190 -       {0x0000a3a0, 0xca9228ee},
13191 -};
13192 -
13193  #endif /* INITVALS_9565_1P0_H */
13194 --- a/include/linux/ath9k_platform.h
13195 +++ b/include/linux/ath9k_platform.h
13196 @@ -32,6 +32,8 @@ struct ath9k_platform_data {
13197         u32 gpio_val;
13198
13199         bool is_clk_25mhz;
13200 +       bool tx_gain_buffalo;
13201 +
13202         int (*get_mac_revision)(void);
13203         int (*external_reset)(void);
13204  };
13205 --- /dev/null
13206 +++ b/drivers/net/wireless/ath/ath9k/ar9003_buffalo_initvals.h
13207 @@ -0,0 +1,126 @@
13208 +/*
13209 + * Copyright (c) 2013 Qualcomm Atheros Inc.
13210 + *
13211 + * Permission to use, copy, modify, and/or distribute this software for any
13212 + * purpose with or without fee is hereby granted, provided that the above
13213 + * copyright notice and this permission notice appear in all copies.
13214 + *
13215 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13216 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13217 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13218 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13219 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13220 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
13221 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
13222 + */
13223 +
13224 +#ifndef INITVALS_9003_BUFFALO_H
13225 +#define INITVALS_9003_BUFFALO_H
13226 +
13227 +static const u32 ar9300Modes_high_power_tx_gain_table_buffalo[][5] = {
13228 +       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
13229 +       {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
13230 +       {0x0000a2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
13231 +       {0x0000a2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
13232 +       {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
13233 +       {0x0000a410, 0x000050d8, 0x000050d8, 0x000050d9, 0x000050d9},
13234 +       {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000},
13235 +       {0x0000a504, 0x04002222, 0x04002222, 0x04000002, 0x04000002},
13236 +       {0x0000a508, 0x09002421, 0x09002421, 0x08000004, 0x08000004},
13237 +       {0x0000a50c, 0x0d002621, 0x0d002621, 0x0b000200, 0x0b000200},
13238 +       {0x0000a510, 0x13004620, 0x13004620, 0x0f000202, 0x0f000202},
13239 +       {0x0000a514, 0x19004a20, 0x19004a20, 0x11000400, 0x11000400},
13240 +       {0x0000a518, 0x1d004e20, 0x1d004e20, 0x15000402, 0x15000402},
13241 +       {0x0000a51c, 0x21005420, 0x21005420, 0x19000404, 0x19000404},
13242 +       {0x0000a520, 0x26005e20, 0x26005e20, 0x1b000603, 0x1b000603},
13243 +       {0x0000a524, 0x2b005e40, 0x2b005e40, 0x1f000a02, 0x1f000a02},
13244 +       {0x0000a528, 0x2f005e42, 0x2f005e42, 0x23000a04, 0x23000a04},
13245 +       {0x0000a52c, 0x33005e44, 0x33005e44, 0x26000a20, 0x26000a20},
13246 +       {0x0000a530, 0x38005e65, 0x38005e65, 0x2a000e20, 0x2a000e20},
13247 +       {0x0000a534, 0x3c005e69, 0x3c005e69, 0x2e000e22, 0x2e000e22},
13248 +       {0x0000a538, 0x40005e6b, 0x40005e6b, 0x31000e24, 0x31000e24},
13249 +       {0x0000a53c, 0x44005e6d, 0x44005e6d, 0x34001640, 0x34001640},
13250 +       {0x0000a540, 0x49005e72, 0x49005e72, 0x38001660, 0x38001660},
13251 +       {0x0000a544, 0x4e005eb2, 0x4e005eb2, 0x3b001861, 0x3b001861},
13252 +       {0x0000a548, 0x53005f12, 0x53005f12, 0x3e001a81, 0x3e001a81},
13253 +       {0x0000a54c, 0x59025eb2, 0x59025eb2, 0x42001a83, 0x42001a83},
13254 +       {0x0000a550, 0x5e025f12, 0x5e025f12, 0x44001c84, 0x44001c84},
13255 +       {0x0000a554, 0x61027f12, 0x61027f12, 0x48001ce3, 0x48001ce3},
13256 +       {0x0000a558, 0x6702bf12, 0x6702bf12, 0x4c001ce5, 0x4c001ce5},
13257 +       {0x0000a55c, 0x6b02bf14, 0x6b02bf14, 0x50001ce9, 0x50001ce9},
13258 +       {0x0000a560, 0x6f02bf16, 0x6f02bf16, 0x54001ceb, 0x54001ceb},
13259 +       {0x0000a564, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
13260 +       {0x0000a568, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
13261 +       {0x0000a56c, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
13262 +       {0x0000a570, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
13263 +       {0x0000a574, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
13264 +       {0x0000a578, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
13265 +       {0x0000a57c, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
13266 +       {0x0000a580, 0x00802220, 0x00802220, 0x00800000, 0x00800000},
13267 +       {0x0000a584, 0x04802222, 0x04802222, 0x04800002, 0x04800002},
13268 +       {0x0000a588, 0x09802421, 0x09802421, 0x08800004, 0x08800004},
13269 +       {0x0000a58c, 0x0d802621, 0x0d802621, 0x0b800200, 0x0b800200},
13270 +       {0x0000a590, 0x13804620, 0x13804620, 0x0f800202, 0x0f800202},
13271 +       {0x0000a594, 0x19804a20, 0x19804a20, 0x11800400, 0x11800400},
13272 +       {0x0000a598, 0x1d804e20, 0x1d804e20, 0x15800402, 0x15800402},
13273 +       {0x0000a59c, 0x21805420, 0x21805420, 0x19800404, 0x19800404},
13274 +       {0x0000a5a0, 0x26805e20, 0x26805e20, 0x1b800603, 0x1b800603},
13275 +       {0x0000a5a4, 0x2b805e40, 0x2b805e40, 0x1f800a02, 0x1f800a02},
13276 +       {0x0000a5a8, 0x2f805e42, 0x2f805e42, 0x23800a04, 0x23800a04},
13277 +       {0x0000a5ac, 0x33805e44, 0x33805e44, 0x26800a20, 0x26800a20},
13278 +       {0x0000a5b0, 0x38805e65, 0x38805e65, 0x2a800e20, 0x2a800e20},
13279 +       {0x0000a5b4, 0x3c805e69, 0x3c805e69, 0x2e800e22, 0x2e800e22},
13280 +       {0x0000a5b8, 0x40805e6b, 0x40805e6b, 0x31800e24, 0x31800e24},
13281 +       {0x0000a5bc, 0x44805e6d, 0x44805e6d, 0x34801640, 0x34801640},
13282 +       {0x0000a5c0, 0x49805e72, 0x49805e72, 0x38801660, 0x38801660},
13283 +       {0x0000a5c4, 0x4e805eb2, 0x4e805eb2, 0x3b801861, 0x3b801861},
13284 +       {0x0000a5c8, 0x53805f12, 0x53805f12, 0x3e801a81, 0x3e801a81},
13285 +       {0x0000a5cc, 0x59825eb2, 0x59825eb2, 0x42801a83, 0x42801a83},
13286 +       {0x0000a5d0, 0x5e825f12, 0x5e825f12, 0x44801c84, 0x44801c84},
13287 +       {0x0000a5d4, 0x61827f12, 0x61827f12, 0x48801ce3, 0x48801ce3},
13288 +       {0x0000a5d8, 0x6782bf12, 0x6782bf12, 0x4c801ce5, 0x4c801ce5},
13289 +       {0x0000a5dc, 0x6b82bf14, 0x6b82bf14, 0x50801ce9, 0x50801ce9},
13290 +       {0x0000a5e0, 0x6f82bf16, 0x6f82bf16, 0x54801ceb, 0x54801ceb},
13291 +       {0x0000a5e4, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
13292 +       {0x0000a5e8, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
13293 +       {0x0000a5ec, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
13294 +       {0x0000a5f0, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
13295 +       {0x0000a5f4, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
13296 +       {0x0000a5f8, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
13297 +       {0x0000a5fc, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
13298 +       {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
13299 +       {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
13300 +       {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
13301 +       {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
13302 +       {0x0000a610, 0x00804000, 0x00804000, 0x00000000, 0x00000000},
13303 +       {0x0000a614, 0x00804201, 0x00804201, 0x01404000, 0x01404000},
13304 +       {0x0000a618, 0x0280c802, 0x0280c802, 0x01404501, 0x01404501},
13305 +       {0x0000a61c, 0x0280ca03, 0x0280ca03, 0x02008501, 0x02008501},
13306 +       {0x0000a620, 0x04c15104, 0x04c15104, 0x0280ca03, 0x0280ca03},
13307 +       {0x0000a624, 0x04c15305, 0x04c15305, 0x03010c04, 0x03010c04},
13308 +       {0x0000a628, 0x04c15305, 0x04c15305, 0x04014c04, 0x04014c04},
13309 +       {0x0000a62c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
13310 +       {0x0000a630, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
13311 +       {0x0000a634, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
13312 +       {0x0000a638, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
13313 +       {0x0000a63c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
13314 +       {0x0000b2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
13315 +       {0x0000b2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
13316 +       {0x0000b2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
13317 +       {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
13318 +       {0x0000c2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
13319 +       {0x0000c2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
13320 +       {0x0000c2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
13321 +       {0x0000c2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
13322 +       {0x00016044, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
13323 +       {0x00016048, 0x66480001, 0x66480001, 0x66480001, 0x66480001},
13324 +       {0x00016068, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
13325 +       {0x00016444, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
13326 +       {0x00016448, 0x66480001, 0x66480001, 0x66480001, 0x66480001},
13327 +       {0x00016468, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
13328 +       {0x00016844, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
13329 +       {0x00016848, 0x66480001, 0x66480001, 0x66480001, 0x66480001},
13330 +       {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
13331 +};
13332 +
13333 +#endif /* INITVALS_9003_BUFFALO_H */
13334 --- a/drivers/net/wireless/ath/ath9k/ar9002_mac.c
13335 +++ b/drivers/net/wireless/ath/ath9k/ar9002_mac.c
13336 @@ -29,7 +29,8 @@ static void ar9002_hw_set_desc_link(void
13337         ((struct ath_desc*) ds)->ds_link = ds_link;
13338  }
13339
13340 -static bool ar9002_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
13341 +static bool ar9002_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked,
13342 +                             u32 *sync_cause_p)
13343  {
13344         u32 isr = 0;
13345         u32 mask2 = 0;
13346 @@ -76,9 +77,16 @@ static bool ar9002_hw_get_isr(struct ath
13347                                 mask2 |= ATH9K_INT_CST;
13348                         if (isr2 & AR_ISR_S2_TSFOOR)
13349                                 mask2 |= ATH9K_INT_TSFOOR;
13350 +
13351 +                       if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
13352 +                               REG_WRITE(ah, AR_ISR_S2, isr2);
13353 +                               isr &= ~AR_ISR_BCNMISC;
13354 +                       }
13355                 }
13356
13357 -               isr = REG_READ(ah, AR_ISR_RAC);
13358 +               if (pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)
13359 +                       isr = REG_READ(ah, AR_ISR_RAC);
13360 +
13361                 if (isr == 0xffffffff) {
13362                         *masked = 0;
13363                         return false;
13364 @@ -97,11 +105,23 @@ static bool ar9002_hw_get_isr(struct ath
13365
13366                         *masked |= ATH9K_INT_TX;
13367
13368 -                       s0_s = REG_READ(ah, AR_ISR_S0_S);
13369 +                       if (pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED) {
13370 +                               s0_s = REG_READ(ah, AR_ISR_S0_S);
13371 +                               s1_s = REG_READ(ah, AR_ISR_S1_S);
13372 +                       } else {
13373 +                               s0_s = REG_READ(ah, AR_ISR_S0);
13374 +                               REG_WRITE(ah, AR_ISR_S0, s0_s);
13375 +                               s1_s = REG_READ(ah, AR_ISR_S1);
13376 +                               REG_WRITE(ah, AR_ISR_S1, s1_s);
13377 +
13378 +                               isr &= ~(AR_ISR_TXOK |
13379 +                                        AR_ISR_TXDESC |
13380 +                                        AR_ISR_TXERR |
13381 +                                        AR_ISR_TXEOL);
13382 +                       }
13383 +
13384                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
13385                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
13386 -
13387 -                       s1_s = REG_READ(ah, AR_ISR_S1_S);
13388                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
13389                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
13390                 }
13391 @@ -114,13 +134,23 @@ static bool ar9002_hw_get_isr(struct ath
13392                 *masked |= mask2;
13393         }
13394
13395 +       if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
13396 +               REG_WRITE(ah, AR_ISR, isr);
13397 +               REG_READ(ah, AR_ISR);
13398 +       }
13399 +
13400         if (AR_SREV_9100(ah))
13401                 return true;
13402
13403         if (isr & AR_ISR_GENTMR) {
13404                 u32 s5_s;
13405
13406 -               s5_s = REG_READ(ah, AR_ISR_S5_S);
13407 +               if (pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED) {
13408 +                       s5_s = REG_READ(ah, AR_ISR_S5_S);
13409 +               } else {
13410 +                       s5_s = REG_READ(ah, AR_ISR_S5);
13411 +               }
13412 +
13413                 ah->intr_gen_timer_trigger =
13414                                 MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
13415
13416 @@ -133,10 +163,16 @@ static bool ar9002_hw_get_isr(struct ath
13417                 if ((s5_s & AR_ISR_S5_TIM_TIMER) &&
13418                     !(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
13419                         *masked |= ATH9K_INT_TIM_TIMER;
13420 +
13421 +               if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
13422 +                       REG_WRITE(ah, AR_ISR_S5, s5_s);
13423 +                       isr &= ~AR_ISR_GENTMR;
13424 +               }
13425         }
13426
13427         if (sync_cause) {
13428 -               ath9k_debug_sync_cause(common, sync_cause);
13429 +               if (sync_cause_p)
13430 +                       *sync_cause_p = sync_cause;
13431                 fatal_int =
13432                         (sync_cause &
13433                          (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
13434 --- a/drivers/net/wireless/ath/ath9k/antenna.c
13435 +++ b/drivers/net/wireless/ath/ath9k/antenna.c
13436 @@ -724,14 +724,14 @@ void ath_ant_comb_scan(struct ath_softc
13437         struct ath_ant_comb *antcomb = &sc->ant_comb;
13438         int alt_ratio = 0, alt_rssi_avg = 0, main_rssi_avg = 0, curr_alt_set;
13439         int curr_main_set;
13440 -       int main_rssi = rs->rs_rssi_ctl0;
13441 -       int alt_rssi = rs->rs_rssi_ctl1;
13442 +       int main_rssi = rs->rs_rssi_ctl[0];
13443 +       int alt_rssi = rs->rs_rssi_ctl[1];
13444         int rx_ant_conf,  main_ant_conf;
13445         bool short_scan = false, ret;
13446
13447 -       rx_ant_conf = (rs->rs_rssi_ctl2 >> ATH_ANT_RX_CURRENT_SHIFT) &
13448 +       rx_ant_conf = (rs->rs_rssi_ctl[2] >> ATH_ANT_RX_CURRENT_SHIFT) &
13449                        ATH_ANT_RX_MASK;
13450 -       main_ant_conf = (rs->rs_rssi_ctl2 >> ATH_ANT_RX_MAIN_SHIFT) &
13451 +       main_ant_conf = (rs->rs_rssi_ctl[2] >> ATH_ANT_RX_MAIN_SHIFT) &
13452                          ATH_ANT_RX_MASK;
13453
13454         if (alt_rssi >= antcomb->low_rssi_thresh) {
13455 --- a/drivers/net/wireless/ath/ath9k/ar9002_hw.c
13456 +++ b/drivers/net/wireless/ath/ath9k/ar9002_hw.c
13457 @@ -32,12 +32,8 @@ static int ar9002_hw_init_mode_regs(stru
13458                 return 0;
13459         }
13460
13461 -       if (ah->config.pcie_clock_req)
13462 -               INIT_INI_ARRAY(&ah->iniPcieSerdes,
13463 -                          ar9280PciePhy_clkreq_off_L1_9280);
13464 -       else
13465 -               INIT_INI_ARRAY(&ah->iniPcieSerdes,
13466 -                          ar9280PciePhy_clkreq_always_on_L1_9280);
13467 +       INIT_INI_ARRAY(&ah->iniPcieSerdes,
13468 +                      ar9280PciePhy_clkreq_always_on_L1_9280);
13469
13470         if (AR_SREV_9287_11_OR_LATER(ah)) {
13471                 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1);
13472 --- a/drivers/net/wireless/ath/ath9k/ar9002_phy.c
13473 +++ b/drivers/net/wireless/ath/ath9k/ar9002_phy.c
13474 @@ -201,7 +201,6 @@ static void ar9002_hw_spur_mitigate(stru
13475         ath9k_hw_get_channel_centers(ah, chan, &centers);
13476         freq = centers.synth_center;
13477
13478 -       ah->config.spurmode = SPUR_ENABLE_EEPROM;
13479         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
13480                 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
13481
13482 --- a/drivers/net/wireless/ath/ath9k/ar9003_mac.c
13483 +++ b/drivers/net/wireless/ath/ath9k/ar9003_mac.c
13484 @@ -175,7 +175,8 @@ static void ar9003_hw_set_desc_link(void
13485         ads->ctl10 |= ar9003_calc_ptr_chksum(ads);
13486  }
13487
13488 -static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
13489 +static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked,
13490 +                             u32 *sync_cause_p)
13491  {
13492         u32 isr = 0;
13493         u32 mask2 = 0;
13494 @@ -310,7 +311,8 @@ static bool ar9003_hw_get_isr(struct ath
13495                 ar9003_mci_get_isr(ah, masked);
13496
13497         if (sync_cause) {
13498 -               ath9k_debug_sync_cause(common, sync_cause);
13499 +               if (sync_cause_p)
13500 +                       *sync_cause_p = sync_cause;
13501                 fatal_int =
13502                         (sync_cause &
13503                          (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
13504 @@ -476,12 +478,12 @@ int ath9k_hw_process_rxdesc_edma(struct
13505
13506         /* XXX: Keycache */
13507         rxs->rs_rssi = MS(rxsp->status5, AR_RxRSSICombined);
13508 -       rxs->rs_rssi_ctl0 = MS(rxsp->status1, AR_RxRSSIAnt00);
13509 -       rxs->rs_rssi_ctl1 = MS(rxsp->status1, AR_RxRSSIAnt01);
13510 -       rxs->rs_rssi_ctl2 = MS(rxsp->status1, AR_RxRSSIAnt02);
13511 -       rxs->rs_rssi_ext0 = MS(rxsp->status5, AR_RxRSSIAnt10);
13512 -       rxs->rs_rssi_ext1 = MS(rxsp->status5, AR_RxRSSIAnt11);
13513 -       rxs->rs_rssi_ext2 = MS(rxsp->status5, AR_RxRSSIAnt12);
13514 +       rxs->rs_rssi_ctl[0] = MS(rxsp->status1, AR_RxRSSIAnt00);
13515 +       rxs->rs_rssi_ctl[1] = MS(rxsp->status1, AR_RxRSSIAnt01);
13516 +       rxs->rs_rssi_ctl[2] = MS(rxsp->status1, AR_RxRSSIAnt02);
13517 +       rxs->rs_rssi_ext[0] = MS(rxsp->status5, AR_RxRSSIAnt10);
13518 +       rxs->rs_rssi_ext[1] = MS(rxsp->status5, AR_RxRSSIAnt11);
13519 +       rxs->rs_rssi_ext[2] = MS(rxsp->status5, AR_RxRSSIAnt12);
13520
13521         if (rxsp->status11 & AR_RxKeyIdxValid)
13522                 rxs->rs_keyix = MS(rxsp->status11, AR_KeyIdx);
13523 --- a/drivers/net/wireless/ath/ath9k/beacon.c
13524 +++ b/drivers/net/wireless/ath/ath9k/beacon.c
13525 @@ -274,18 +274,19 @@ static int ath9k_beacon_choose_slot(stru
13526         return slot;
13527  }
13528
13529 -void ath9k_set_tsfadjust(struct ath_softc *sc, struct ieee80211_vif *vif)
13530 +static void ath9k_set_tsfadjust(struct ath_softc *sc, struct ieee80211_vif *vif)
13531  {
13532         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
13533         struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
13534         struct ath_vif *avp = (void *)vif->drv_priv;
13535 -       u64 tsfadjust;
13536 +       u32 tsfadjust;
13537
13538         if (avp->av_bslot == 0)
13539                 return;
13540
13541 -       tsfadjust = cur_conf->beacon_interval * avp->av_bslot / ATH_BCBUF;
13542 -       avp->tsf_adjust = cpu_to_le64(TU_TO_USEC(tsfadjust));
13543 +       tsfadjust = cur_conf->beacon_interval * avp->av_bslot;
13544 +       tsfadjust = TU_TO_USEC(tsfadjust) / ATH_BCBUF;
13545 +       avp->tsf_adjust = cpu_to_le64(tsfadjust);
13546
13547         ath_dbg(common, CONFIG, "tsfadjust is: %llu for bslot: %d\n",
13548                 (unsigned long long)tsfadjust, avp->av_bslot);
13549 @@ -431,6 +432,33 @@ static void ath9k_beacon_init(struct ath
13550         ath9k_hw_enable_interrupts(ah);
13551  }
13552
13553 +/* Calculate the modulo of a 64 bit TSF snapshot with a TU divisor */
13554 +static u32 ath9k_mod_tsf64_tu(u64 tsf, u32 div_tu)
13555 +{
13556 +       u32 tsf_mod, tsf_hi, tsf_lo, mod_hi, mod_lo;
13557 +
13558 +       tsf_mod = tsf & (BIT(10) - 1);
13559 +       tsf_hi = tsf >> 32;
13560 +       tsf_lo = ((u32) tsf) >> 10;
13561 +
13562 +       mod_hi = tsf_hi % div_tu;
13563 +       mod_lo = ((mod_hi << 22) + tsf_lo) % div_tu;
13564 +
13565 +       return (mod_lo << 10) | tsf_mod;
13566 +}
13567 +
13568 +static u32 ath9k_get_next_tbtt(struct ath_softc *sc, u64 tsf,
13569 +                              unsigned int interval)
13570 +{
13571 +       struct ath_hw *ah = sc->sc_ah;
13572 +       unsigned int offset;
13573 +
13574 +       tsf += TU_TO_USEC(FUDGE + ah->config.sw_beacon_response_time);
13575 +       offset = ath9k_mod_tsf64_tu(tsf, interval);
13576 +
13577 +       return (u32) tsf + TU_TO_USEC(interval) - offset;
13578 +}
13579 +
13580  /*
13581   * For multi-bss ap support beacons are either staggered evenly over N slots or
13582   * burst together.  For the former arrange for the SWBA to be delivered for each
13583 @@ -446,7 +474,8 @@ static void ath9k_beacon_config_ap(struc
13584         /* NB: the beacon interval is kept internally in TU's */
13585         intval = TU_TO_USEC(conf->beacon_interval);
13586         intval /= ATH_BCBUF;
13587 -       nexttbtt = intval;
13588 +       nexttbtt = ath9k_get_next_tbtt(sc, ath9k_hw_gettsf64(ah),
13589 +                                      conf->beacon_interval);
13590
13591         if (conf->enable_beacon)
13592                 ah->imask |= ATH9K_INT_SWBA;
13593 @@ -458,7 +487,7 @@ static void ath9k_beacon_config_ap(struc
13594                 (conf->enable_beacon) ? "Enable" : "Disable",
13595                 nexttbtt, intval, conf->beacon_interval);
13596
13597 -       ath9k_beacon_init(sc, nexttbtt, intval, true);
13598 +       ath9k_beacon_init(sc, nexttbtt, intval, false);
13599  }
13600
13601  /*
13602 @@ -475,11 +504,9 @@ static void ath9k_beacon_config_sta(stru
13603         struct ath_hw *ah = sc->sc_ah;
13604         struct ath_common *common = ath9k_hw_common(ah);
13605         struct ath9k_beacon_state bs;
13606 -       int dtimperiod, dtimcount, sleepduration;
13607 -       int cfpperiod, cfpcount;
13608 -       u32 nexttbtt = 0, intval, tsftu;
13609 +       int dtim_intval, sleepduration;
13610 +       u32 nexttbtt = 0, intval;
13611         u64 tsf;
13612 -       int num_beacons, offset, dtim_dec_count, cfp_dec_count;
13613
13614         /* No need to configure beacon if we are not associated */
13615         if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
13616 @@ -492,53 +519,25 @@ static void ath9k_beacon_config_sta(stru
13617         intval = conf->beacon_interval;
13618
13619         /*
13620 -        * Setup dtim and cfp parameters according to
13621 +        * Setup dtim parameters according to
13622          * last beacon we received (which may be none).
13623          */
13624 -       dtimperiod = conf->dtim_period;
13625 -       dtimcount = conf->dtim_count;
13626 -       if (dtimcount >= dtimperiod)    /* NB: sanity check */
13627 -               dtimcount = 0;
13628 -       cfpperiod = 1;                  /* NB: no PCF support yet */
13629 -       cfpcount = 0;
13630 -
13631 +       dtim_intval = intval * conf->dtim_period;
13632         sleepduration = conf->listen_interval * intval;
13633
13634         /*
13635          * Pull nexttbtt forward to reflect the current
13636 -        * TSF and calculate dtim+cfp state for the result.
13637 +        * TSF and calculate dtim state for the result.
13638          */
13639         tsf = ath9k_hw_gettsf64(ah);
13640 -       tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE;
13641 +       nexttbtt = ath9k_get_next_tbtt(sc, tsf, intval);
13642
13643 -       num_beacons = tsftu / intval + 1;
13644 -       offset = tsftu % intval;
13645 -       nexttbtt = tsftu - offset;
13646 -       if (offset)
13647 -               nexttbtt += intval;
13648 -
13649 -       /* DTIM Beacon every dtimperiod Beacon */
13650 -       dtim_dec_count = num_beacons % dtimperiod;
13651 -       /* CFP every cfpperiod DTIM Beacon */
13652 -       cfp_dec_count = (num_beacons / dtimperiod) % cfpperiod;
13653 -       if (dtim_dec_count)
13654 -               cfp_dec_count++;
13655 -
13656 -       dtimcount -= dtim_dec_count;
13657 -       if (dtimcount < 0)
13658 -               dtimcount += dtimperiod;
13659 -
13660 -       cfpcount -= cfp_dec_count;
13661 -       if (cfpcount < 0)
13662 -               cfpcount += cfpperiod;
13663 -
13664 -       bs.bs_intval = intval;
13665 +       bs.bs_intval = TU_TO_USEC(intval);
13666 +       bs.bs_dtimperiod = conf->dtim_period * bs.bs_intval;
13667         bs.bs_nexttbtt = nexttbtt;
13668 -       bs.bs_dtimperiod = dtimperiod*intval;
13669 -       bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval;
13670 -       bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod;
13671 -       bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod;
13672 -       bs.bs_cfpmaxduration = 0;
13673 +       bs.bs_nextdtim = nexttbtt;
13674 +       if (conf->dtim_period > 1)
13675 +               bs.bs_nextdtim = ath9k_get_next_tbtt(sc, tsf, dtim_intval);
13676
13677         /*
13678          * Calculate the number of consecutive beacons to miss* before taking
13679 @@ -566,18 +565,16 @@ static void ath9k_beacon_config_sta(stru
13680          * XXX fixed at 100ms
13681          */
13682
13683 -       bs.bs_sleepduration = roundup(IEEE80211_MS_TO_TU(100), sleepduration);
13684 +       bs.bs_sleepduration = TU_TO_USEC(roundup(IEEE80211_MS_TO_TU(100),
13685 +                                                sleepduration));
13686         if (bs.bs_sleepduration > bs.bs_dtimperiod)
13687                 bs.bs_sleepduration = bs.bs_dtimperiod;
13688
13689         /* TSF out of range threshold fixed at 1 second */
13690         bs.bs_tsfoor_threshold = ATH9K_TSFOOR_THRESHOLD;
13691
13692 -       ath_dbg(common, BEACON, "tsf: %llu tsftu: %u\n", tsf, tsftu);
13693 -       ath_dbg(common, BEACON,
13694 -               "bmiss: %u sleep: %u cfp-period: %u maxdur: %u next: %u\n",
13695 -               bs.bs_bmissthreshold, bs.bs_sleepduration,
13696 -               bs.bs_cfpperiod, bs.bs_cfpmaxduration, bs.bs_cfpnext);
13697 +       ath_dbg(common, BEACON, "bmiss: %u sleep: %u\n",
13698 +               bs.bs_bmissthreshold, bs.bs_sleepduration);
13699
13700         /* Set the computed STA beacon timers */
13701
13702 @@ -600,25 +597,11 @@ static void ath9k_beacon_config_adhoc(st
13703
13704         intval = TU_TO_USEC(conf->beacon_interval);
13705
13706 -       if (conf->ibss_creator) {
13707 +       if (conf->ibss_creator)
13708                 nexttbtt = intval;
13709 -       } else {
13710 -               u32 tbtt, offset, tsftu;
13711 -               u64 tsf;
13712 -
13713 -               /*
13714 -                * Pull nexttbtt forward to reflect the current
13715 -                * sync'd TSF.
13716 -                */
13717 -               tsf = ath9k_hw_gettsf64(ah);
13718 -               tsftu = TSF_TO_TU(tsf >> 32, tsf) + FUDGE;
13719 -               offset = tsftu % conf->beacon_interval;
13720 -               tbtt = tsftu - offset;
13721 -               if (offset)
13722 -                       tbtt += conf->beacon_interval;
13723 -
13724 -               nexttbtt = TU_TO_USEC(tbtt);
13725 -       }
13726 +       else
13727 +               nexttbtt = ath9k_get_next_tbtt(sc, ath9k_hw_gettsf64(ah),
13728 +                                              conf->beacon_interval);
13729
13730         if (conf->enable_beacon)
13731                 ah->imask |= ATH9K_INT_SWBA;
13732 @@ -640,7 +623,8 @@ static void ath9k_beacon_config_adhoc(st
13733                 set_bit(SC_OP_BEACONS, &sc->sc_flags);
13734  }
13735
13736 -bool ath9k_allow_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif)
13737 +static bool ath9k_allow_beacon_config(struct ath_softc *sc,
13738 +                                     struct ieee80211_vif *vif)
13739  {
13740         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
13741         struct ath_vif *avp = (void *)vif->drv_priv;
13742 @@ -711,12 +695,17 @@ void ath9k_beacon_config(struct ath_soft
13743         unsigned long flags;
13744         bool skip_beacon = false;
13745
13746 +       if (vif->type == NL80211_IFTYPE_AP)
13747 +               ath9k_set_tsfadjust(sc, vif);
13748 +
13749 +       if (!ath9k_allow_beacon_config(sc, vif))
13750 +               return;
13751 +
13752         if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION) {
13753                 ath9k_cache_beacon_config(sc, bss_conf);
13754                 ath9k_set_beacon(sc);
13755                 set_bit(SC_OP_BEACONS, &sc->sc_flags);
13756                 return;
13757 -
13758         }
13759
13760         /*
13761 --- a/drivers/net/wireless/ath/ath9k/btcoex.c
13762 +++ b/drivers/net/wireless/ath/ath9k/btcoex.c
13763 @@ -66,7 +66,6 @@ void ath9k_hw_init_btcoex_hw(struct ath_
13764                 .bt_first_slot_time = 5,
13765                 .bt_hold_rx_clear = true,
13766         };
13767 -       u32 i, idx;
13768         bool rxclear_polarity = ath_bt_config.bt_rxclear_polarity;
13769
13770         if (AR_SREV_9300_20_OR_LATER(ah))
13771 @@ -88,11 +87,6 @@ void ath9k_hw_init_btcoex_hw(struct ath_
13772                 SM(ath_bt_config.bt_hold_rx_clear, AR_BT_HOLD_RX_CLEAR) |
13773                 SM(ATH_BTCOEX_BMISS_THRESH, AR_BT_BCN_MISS_THRESH) |
13774                 AR_BT_DISABLE_BT_ANT;
13775 -
13776 -       for (i = 0; i < 32; i++) {
13777 -               idx = (debruijn32 << i) >> 27;
13778 -               ah->hw_gen_timers.gen_timer_index[idx] = i;
13779 -       }
13780  }
13781  EXPORT_SYMBOL(ath9k_hw_init_btcoex_hw);
13782
13783 --- a/drivers/net/wireless/ath/ath9k/dfs.c
13784 +++ b/drivers/net/wireless/ath/ath9k/dfs.c
13785 @@ -158,8 +158,8 @@ void ath9k_dfs_process_phyerr(struct ath
13786                 return;
13787         }
13788
13789 -       ard.rssi = rs->rs_rssi_ctl0;
13790 -       ard.ext_rssi = rs->rs_rssi_ext0;
13791 +       ard.rssi = rs->rs_rssi_ctl[0];
13792 +       ard.ext_rssi = rs->rs_rssi_ext[0];
13793
13794         /*
13795          * hardware stores this as 8 bit signed value.
13796 --- a/drivers/net/wireless/ath/ath9k/eeprom_4k.c
13797 +++ b/drivers/net/wireless/ath/ath9k/eeprom_4k.c
13798 @@ -1085,31 +1085,7 @@ static void ath9k_hw_4k_set_board_values
13799
13800  static u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
13801  {
13802 -#define EEP_MAP4K_SPURCHAN \
13803 -       (ah->eeprom.map4k.modalHeader.spurChans[i].spurChan)
13804 -       struct ath_common *common = ath9k_hw_common(ah);
13805 -
13806 -       u16 spur_val = AR_NO_SPUR;
13807 -
13808 -       ath_dbg(common, ANI, "Getting spur idx:%d is2Ghz:%d val:%x\n",
13809 -               i, is2GHz, ah->config.spurchans[i][is2GHz]);
13810 -
13811 -       switch (ah->config.spurmode) {
13812 -       case SPUR_DISABLE:
13813 -               break;
13814 -       case SPUR_ENABLE_IOCTL:
13815 -               spur_val = ah->config.spurchans[i][is2GHz];
13816 -               ath_dbg(common, ANI, "Getting spur val from new loc. %d\n",
13817 -                       spur_val);
13818 -               break;
13819 -       case SPUR_ENABLE_EEPROM:
13820 -               spur_val = EEP_MAP4K_SPURCHAN;
13821 -               break;
13822 -       }
13823 -
13824 -       return spur_val;
13825 -
13826 -#undef EEP_MAP4K_SPURCHAN
13827 +       return ah->eeprom.map4k.modalHeader.spurChans[i].spurChan;
13828  }
13829
13830  const struct eeprom_ops eep_4k_ops = {
13831 --- a/drivers/net/wireless/ath/ath9k/eeprom_9287.c
13832 +++ b/drivers/net/wireless/ath/ath9k/eeprom_9287.c
13833 @@ -1004,31 +1004,7 @@ static void ath9k_hw_ar9287_set_board_va
13834  static u16 ath9k_hw_ar9287_get_spur_channel(struct ath_hw *ah,
13835                                             u16 i, bool is2GHz)
13836  {
13837 -#define EEP_MAP9287_SPURCHAN \
13838 -       (ah->eeprom.map9287.modalHeader.spurChans[i].spurChan)
13839 -
13840 -       struct ath_common *common = ath9k_hw_common(ah);
13841 -       u16 spur_val = AR_NO_SPUR;
13842 -
13843 -       ath_dbg(common, ANI, "Getting spur idx:%d is2Ghz:%d val:%x\n",
13844 -               i, is2GHz, ah->config.spurchans[i][is2GHz]);
13845 -
13846 -       switch (ah->config.spurmode) {
13847 -       case SPUR_DISABLE:
13848 -               break;
13849 -       case SPUR_ENABLE_IOCTL:
13850 -               spur_val = ah->config.spurchans[i][is2GHz];
13851 -               ath_dbg(common, ANI, "Getting spur val from new loc. %d\n",
13852 -                       spur_val);
13853 -               break;
13854 -       case SPUR_ENABLE_EEPROM:
13855 -               spur_val = EEP_MAP9287_SPURCHAN;
13856 -               break;
13857 -       }
13858 -
13859 -       return spur_val;
13860 -
13861 -#undef EEP_MAP9287_SPURCHAN
13862 +       return ah->eeprom.map9287.modalHeader.spurChans[i].spurChan;
13863  }
13864
13865  const struct eeprom_ops eep_ar9287_ops = {
13866 --- a/drivers/net/wireless/ath/ath9k/eeprom_def.c
13867 +++ b/drivers/net/wireless/ath/ath9k/eeprom_def.c
13868 @@ -1348,31 +1348,7 @@ static void ath9k_hw_def_set_txpower(str
13869
13870  static u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
13871  {
13872 -#define EEP_DEF_SPURCHAN \
13873 -       (ah->eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan)
13874 -       struct ath_common *common = ath9k_hw_common(ah);
13875 -
13876 -       u16 spur_val = AR_NO_SPUR;
13877 -
13878 -       ath_dbg(common, ANI, "Getting spur idx:%d is2Ghz:%d val:%x\n",
13879 -               i, is2GHz, ah->config.spurchans[i][is2GHz]);
13880 -
13881 -       switch (ah->config.spurmode) {
13882 -       case SPUR_DISABLE:
13883 -               break;
13884 -       case SPUR_ENABLE_IOCTL:
13885 -               spur_val = ah->config.spurchans[i][is2GHz];
13886 -               ath_dbg(common, ANI, "Getting spur val from new loc. %d\n",
13887 -                       spur_val);
13888 -               break;
13889 -       case SPUR_ENABLE_EEPROM:
13890 -               spur_val = EEP_DEF_SPURCHAN;
13891 -               break;
13892 -       }
13893 -
13894 -       return spur_val;
13895 -
13896 -#undef EEP_DEF_SPURCHAN
13897 +       return ah->eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan;
13898  }
13899
13900  const struct eeprom_ops eep_def_ops = {
13901 --- a/drivers/net/wireless/ath/ath9k/gpio.c
13902 +++ b/drivers/net/wireless/ath/ath9k/gpio.c
13903 @@ -157,36 +157,6 @@ static void ath_detect_bt_priority(struc
13904         }
13905  }
13906
13907 -static void ath9k_gen_timer_start(struct ath_hw *ah,
13908 -                                 struct ath_gen_timer *timer,
13909 -                                 u32 trig_timeout,
13910 -                                 u32 timer_period)
13911 -{
13912 -       ath9k_hw_gen_timer_start(ah, timer, trig_timeout, timer_period);
13913 -
13914 -       if ((ah->imask & ATH9K_INT_GENTIMER) == 0) {
13915 -               ath9k_hw_disable_interrupts(ah);
13916 -               ah->imask |= ATH9K_INT_GENTIMER;
13917 -               ath9k_hw_set_interrupts(ah);
13918 -               ath9k_hw_enable_interrupts(ah);
13919 -       }
13920 -}
13921 -
13922 -static void ath9k_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
13923 -{
13924 -       struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
13925 -
13926 -       ath9k_hw_gen_timer_stop(ah, timer);
13927 -
13928 -       /* if no timer is enabled, turn off interrupt mask */
13929 -       if (timer_table->timer_mask.val == 0) {
13930 -               ath9k_hw_disable_interrupts(ah);
13931 -               ah->imask &= ~ATH9K_INT_GENTIMER;
13932 -               ath9k_hw_set_interrupts(ah);
13933 -               ath9k_hw_enable_interrupts(ah);
13934 -       }
13935 -}
13936 -
13937  static void ath_mci_ftp_adjust(struct ath_softc *sc)
13938  {
13939         struct ath_btcoex *btcoex = &sc->btcoex;
13940 @@ -257,19 +227,9 @@ static void ath_btcoex_period_timer(unsi
13941
13942         spin_unlock_bh(&btcoex->btcoex_lock);
13943
13944 -       /*
13945 -        * btcoex_period is in msec while (btocex/btscan_)no_stomp are in usec,
13946 -        * ensure that we properly convert btcoex_period to usec
13947 -        * for any comparision with (btcoex/btscan_)no_stomp.
13948 -        */
13949 -       if (btcoex->btcoex_period * 1000 != btcoex->btcoex_no_stomp) {
13950 -               if (btcoex->hw_timer_enabled)
13951 -                       ath9k_gen_timer_stop(ah, btcoex->no_stomp_timer);
13952 -
13953 -               ath9k_gen_timer_start(ah, btcoex->no_stomp_timer, timer_period,
13954 -                                     timer_period * 10);
13955 -               btcoex->hw_timer_enabled = true;
13956 -       }
13957 +       if (btcoex->btcoex_period != btcoex->btcoex_no_stomp)
13958 +               mod_timer(&btcoex->no_stomp_timer,
13959 +                        jiffies + msecs_to_jiffies(timer_period));
13960
13961         ath9k_ps_restore(sc);
13962
13963 @@ -282,7 +242,7 @@ skip_hw_wakeup:
13964   * Generic tsf based hw timer which configures weight
13965   * registers to time slice between wlan and bt traffic
13966   */
13967 -static void ath_btcoex_no_stomp_timer(void *arg)
13968 +static void ath_btcoex_no_stomp_timer(unsigned long arg)
13969  {
13970         struct ath_softc *sc = (struct ath_softc *)arg;
13971         struct ath_hw *ah = sc->sc_ah;
13972 @@ -311,24 +271,18 @@ static int ath_init_btcoex_timer(struct
13973         struct ath_btcoex *btcoex = &sc->btcoex;
13974
13975         btcoex->btcoex_period = ATH_BTCOEX_DEF_BT_PERIOD;
13976 -       btcoex->btcoex_no_stomp = (100 - ATH_BTCOEX_DEF_DUTY_CYCLE) * 1000 *
13977 +       btcoex->btcoex_no_stomp = (100 - ATH_BTCOEX_DEF_DUTY_CYCLE) *
13978                 btcoex->btcoex_period / 100;
13979 -       btcoex->btscan_no_stomp = (100 - ATH_BTCOEX_BTSCAN_DUTY_CYCLE) * 1000 *
13980 +       btcoex->btscan_no_stomp = (100 - ATH_BTCOEX_BTSCAN_DUTY_CYCLE) *
13981                                    btcoex->btcoex_period / 100;
13982
13983         setup_timer(&btcoex->period_timer, ath_btcoex_period_timer,
13984                         (unsigned long) sc);
13985 +       setup_timer(&btcoex->no_stomp_timer, ath_btcoex_no_stomp_timer,
13986 +                       (unsigned long) sc);
13987
13988         spin_lock_init(&btcoex->btcoex_lock);
13989
13990 -       btcoex->no_stomp_timer = ath_gen_timer_alloc(sc->sc_ah,
13991 -                       ath_btcoex_no_stomp_timer,
13992 -                       ath_btcoex_no_stomp_timer,
13993 -                       (void *) sc, AR_FIRST_NDP_TIMER);
13994 -
13995 -       if (!btcoex->no_stomp_timer)
13996 -               return -ENOMEM;
13997 -
13998         return 0;
13999  }
14000
14001 @@ -343,10 +297,7 @@ void ath9k_btcoex_timer_resume(struct at
14002         ath_dbg(ath9k_hw_common(ah), BTCOEX, "Starting btcoex timers\n");
14003
14004         /* make sure duty cycle timer is also stopped when resuming */
14005 -       if (btcoex->hw_timer_enabled) {
14006 -               ath9k_gen_timer_stop(sc->sc_ah, btcoex->no_stomp_timer);
14007 -               btcoex->hw_timer_enabled = false;
14008 -       }
14009 +       del_timer_sync(&btcoex->no_stomp_timer);
14010
14011         btcoex->bt_priority_cnt = 0;
14012         btcoex->bt_priority_time = jiffies;
14013 @@ -363,24 +314,16 @@ void ath9k_btcoex_timer_resume(struct at
14014  void ath9k_btcoex_timer_pause(struct ath_softc *sc)
14015  {
14016         struct ath_btcoex *btcoex = &sc->btcoex;
14017 -       struct ath_hw *ah = sc->sc_ah;
14018
14019         del_timer_sync(&btcoex->period_timer);
14020 -
14021 -       if (btcoex->hw_timer_enabled) {
14022 -               ath9k_gen_timer_stop(ah, btcoex->no_stomp_timer);
14023 -               btcoex->hw_timer_enabled = false;
14024 -       }
14025 +       del_timer_sync(&btcoex->no_stomp_timer);
14026  }
14027
14028  void ath9k_btcoex_stop_gen_timer(struct ath_softc *sc)
14029  {
14030         struct ath_btcoex *btcoex = &sc->btcoex;
14031
14032 -       if (btcoex->hw_timer_enabled) {
14033 -               ath9k_gen_timer_stop(sc->sc_ah, btcoex->no_stomp_timer);
14034 -               btcoex->hw_timer_enabled = false;
14035 -       }
14036 +       del_timer_sync(&btcoex->no_stomp_timer);
14037  }
14038
14039  u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc, u32 max_4ms_framelen)
14040 @@ -400,12 +343,6 @@ u16 ath9k_btcoex_aggr_limit(struct ath_s
14041
14042  void ath9k_btcoex_handle_interrupt(struct ath_softc *sc, u32 status)
14043  {
14044 -       struct ath_hw *ah = sc->sc_ah;
14045 -
14046 -       if (ath9k_hw_get_btcoex_scheme(ah) == ATH_BTCOEX_CFG_3WIRE)
14047 -               if (status & ATH9K_INT_GENTIMER)
14048 -                       ath_gen_timer_isr(sc->sc_ah);
14049 -
14050         if (status & ATH9K_INT_MCI)
14051                 ath_mci_intr(sc);
14052  }
14053 @@ -447,10 +384,6 @@ void ath9k_deinit_btcoex(struct ath_soft
14054  {
14055         struct ath_hw *ah = sc->sc_ah;
14056
14057 -        if ((sc->btcoex.no_stomp_timer) &&
14058 -           ath9k_hw_get_btcoex_scheme(sc->sc_ah) == ATH_BTCOEX_CFG_3WIRE)
14059 -               ath_gen_timer_free(sc->sc_ah, sc->btcoex.no_stomp_timer);
14060 -
14061         if (ath9k_hw_mci_is_enabled(ah))
14062                 ath_mci_cleanup(sc);
14063  }
14064 --- a/drivers/net/wireless/ath/ath9k/htc_drv_beacon.c
14065 +++ b/drivers/net/wireless/ath/ath9k/htc_drv_beacon.c
14066 @@ -70,11 +70,11 @@ static void ath9k_htc_beacon_config_sta(
14067         struct ath9k_beacon_state bs;
14068         enum ath9k_int imask = 0;
14069         int dtimperiod, dtimcount, sleepduration;
14070 -       int cfpperiod, cfpcount, bmiss_timeout;
14071 +       int bmiss_timeout;
14072         u32 nexttbtt = 0, intval, tsftu;
14073         __be32 htc_imask = 0;
14074         u64 tsf;
14075 -       int num_beacons, offset, dtim_dec_count, cfp_dec_count;
14076 +       int num_beacons, offset, dtim_dec_count;
14077         int ret __attribute__ ((unused));
14078         u8 cmd_rsp;
14079
14080 @@ -84,7 +84,7 @@ static void ath9k_htc_beacon_config_sta(
14081         bmiss_timeout = (ATH_DEFAULT_BMISS_LIMIT * bss_conf->beacon_interval);
14082
14083         /*
14084 -        * Setup dtim and cfp parameters according to
14085 +        * Setup dtim parameters according to
14086          * last beacon we received (which may be none).
14087          */
14088         dtimperiod = bss_conf->dtim_period;
14089 @@ -93,8 +93,6 @@ static void ath9k_htc_beacon_config_sta(
14090         dtimcount = 1;
14091         if (dtimcount >= dtimperiod)    /* NB: sanity check */
14092                 dtimcount = 0;
14093 -       cfpperiod = 1;                  /* NB: no PCF support yet */
14094 -       cfpcount = 0;
14095
14096         sleepduration = intval;
14097         if (sleepduration <= 0)
14098 @@ -102,7 +100,7 @@ static void ath9k_htc_beacon_config_sta(
14099
14100         /*
14101          * Pull nexttbtt forward to reflect the current
14102 -        * TSF and calculate dtim+cfp state for the result.
14103 +        * TSF and calculate dtim state for the result.
14104          */
14105         tsf = ath9k_hw_gettsf64(priv->ah);
14106         tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE;
14107 @@ -115,26 +113,14 @@ static void ath9k_htc_beacon_config_sta(
14108
14109         /* DTIM Beacon every dtimperiod Beacon */
14110         dtim_dec_count = num_beacons % dtimperiod;
14111 -       /* CFP every cfpperiod DTIM Beacon */
14112 -       cfp_dec_count = (num_beacons / dtimperiod) % cfpperiod;
14113 -       if (dtim_dec_count)
14114 -               cfp_dec_count++;
14115 -
14116         dtimcount -= dtim_dec_count;
14117         if (dtimcount < 0)
14118                 dtimcount += dtimperiod;
14119
14120 -       cfpcount -= cfp_dec_count;
14121 -       if (cfpcount < 0)
14122 -               cfpcount += cfpperiod;
14123 -
14124 -       bs.bs_intval = intval;
14125 -       bs.bs_nexttbtt = nexttbtt;
14126 -       bs.bs_dtimperiod = dtimperiod*intval;
14127 -       bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval;
14128 -       bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod;
14129 -       bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod;
14130 -       bs.bs_cfpmaxduration = 0;
14131 +       bs.bs_intval = TU_TO_USEC(intval);
14132 +       bs.bs_nexttbtt = TU_TO_USEC(nexttbtt);
14133 +       bs.bs_dtimperiod = dtimperiod * bs.bs_intval;
14134 +       bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount * bs.bs_intval;
14135
14136         /*
14137          * Calculate the number of consecutive beacons to miss* before taking
14138 @@ -161,7 +147,8 @@ static void ath9k_htc_beacon_config_sta(
14139          * XXX fixed at 100ms
14140          */
14141
14142 -       bs.bs_sleepduration = roundup(IEEE80211_MS_TO_TU(100), sleepduration);
14143 +       bs.bs_sleepduration = TU_TO_USEC(roundup(IEEE80211_MS_TO_TU(100),
14144 +                                                sleepduration));
14145         if (bs.bs_sleepduration > bs.bs_dtimperiod)
14146                 bs.bs_sleepduration = bs.bs_dtimperiod;
14147
14148 @@ -170,10 +157,8 @@ static void ath9k_htc_beacon_config_sta(
14149
14150         ath_dbg(common, CONFIG, "intval: %u tsf: %llu tsftu: %u\n",
14151                 intval, tsf, tsftu);
14152 -       ath_dbg(common, CONFIG,
14153 -               "bmiss: %u sleep: %u cfp-period: %u maxdur: %u next: %u\n",
14154 -               bs.bs_bmissthreshold, bs.bs_sleepduration,
14155 -               bs.bs_cfpperiod, bs.bs_cfpmaxduration, bs.bs_cfpnext);
14156 +       ath_dbg(common, CONFIG, "bmiss: %u sleep: %u\n",
14157 +               bs.bs_bmissthreshold, bs.bs_sleepduration);
14158
14159         /* Set the computed STA beacon timers */
14160
14161 --- a/drivers/net/wireless/ath/ath9k/mac.c
14162 +++ b/drivers/net/wireless/ath/ath9k/mac.c
14163 @@ -481,8 +481,7 @@ bool ath9k_hw_resettxqueue(struct ath_hw
14164                             | AR_Q_MISC_CBR_INCR_DIS0);
14165                 value = (qi->tqi_readyTime -
14166                          (ah->config.sw_beacon_response_time -
14167 -                         ah->config.dma_beacon_response_time) -
14168 -                        ah->config.additional_swba_backoff) * 1024;
14169 +                         ah->config.dma_beacon_response_time)) * 1024;
14170                 REG_WRITE(ah, AR_QRDYTIMECFG(q),
14171                           value | AR_Q_RDYTIMECFG_EN);
14172                 REG_SET_BIT(ah, AR_DMISC(q),
14173 @@ -550,25 +549,25 @@ int ath9k_hw_rxprocdesc(struct ath_hw *a
14174
14175         if (ads.ds_rxstatus8 & AR_PostDelimCRCErr) {
14176                 rs->rs_rssi = ATH9K_RSSI_BAD;
14177 -               rs->rs_rssi_ctl0 = ATH9K_RSSI_BAD;
14178 -               rs->rs_rssi_ctl1 = ATH9K_RSSI_BAD;
14179 -               rs->rs_rssi_ctl2 = ATH9K_RSSI_BAD;
14180 -               rs->rs_rssi_ext0 = ATH9K_RSSI_BAD;
14181 -               rs->rs_rssi_ext1 = ATH9K_RSSI_BAD;
14182 -               rs->rs_rssi_ext2 = ATH9K_RSSI_BAD;
14183 +               rs->rs_rssi_ctl[0] = ATH9K_RSSI_BAD;
14184 +               rs->rs_rssi_ctl[1] = ATH9K_RSSI_BAD;
14185 +               rs->rs_rssi_ctl[2] = ATH9K_RSSI_BAD;
14186 +               rs->rs_rssi_ext[0] = ATH9K_RSSI_BAD;
14187 +               rs->rs_rssi_ext[1] = ATH9K_RSSI_BAD;
14188 +               rs->rs_rssi_ext[2] = ATH9K_RSSI_BAD;
14189         } else {
14190                 rs->rs_rssi = MS(ads.ds_rxstatus4, AR_RxRSSICombined);
14191 -               rs->rs_rssi_ctl0 = MS(ads.ds_rxstatus0,
14192 +               rs->rs_rssi_ctl[0] = MS(ads.ds_rxstatus0,
14193                                                 AR_RxRSSIAnt00);
14194 -               rs->rs_rssi_ctl1 = MS(ads.ds_rxstatus0,
14195 +               rs->rs_rssi_ctl[1] = MS(ads.ds_rxstatus0,
14196                                                 AR_RxRSSIAnt01);
14197 -               rs->rs_rssi_ctl2 = MS(ads.ds_rxstatus0,
14198 +               rs->rs_rssi_ctl[2] = MS(ads.ds_rxstatus0,
14199                                                 AR_RxRSSIAnt02);
14200 -               rs->rs_rssi_ext0 = MS(ads.ds_rxstatus4,
14201 +               rs->rs_rssi_ext[0] = MS(ads.ds_rxstatus4,
14202                                                 AR_RxRSSIAnt10);
14203 -               rs->rs_rssi_ext1 = MS(ads.ds_rxstatus4,
14204 +               rs->rs_rssi_ext[1] = MS(ads.ds_rxstatus4,
14205                                                 AR_RxRSSIAnt11);
14206 -               rs->rs_rssi_ext2 = MS(ads.ds_rxstatus4,
14207 +               rs->rs_rssi_ext[2] = MS(ads.ds_rxstatus4,
14208                                                 AR_RxRSSIAnt12);
14209         }
14210         if (ads.ds_rxstatus8 & AR_RxKeyIdxValid)
14211 --- a/drivers/net/wireless/ath/ath9k/mac.h
14212 +++ b/drivers/net/wireless/ath/ath9k/mac.h
14213 @@ -133,12 +133,8 @@ struct ath_rx_status {
14214         u8 rs_rate;
14215         u8 rs_antenna;
14216         u8 rs_more;
14217 -       int8_t rs_rssi_ctl0;
14218 -       int8_t rs_rssi_ctl1;
14219 -       int8_t rs_rssi_ctl2;
14220 -       int8_t rs_rssi_ext0;
14221 -       int8_t rs_rssi_ext1;
14222 -       int8_t rs_rssi_ext2;
14223 +       int8_t rs_rssi_ctl[3];
14224 +       int8_t rs_rssi_ext[3];
14225         u8 rs_isaggr;
14226         u8 rs_firstaggr;
14227         u8 rs_moreaggr;
14228 --- a/drivers/net/wireless/ath/ath9k/mci.c
14229 +++ b/drivers/net/wireless/ath/ath9k/mci.c
14230 @@ -200,7 +200,7 @@ skip_tuning:
14231         if (btcoex->duty_cycle > ATH_MCI_MAX_DUTY_CYCLE)
14232                 btcoex->duty_cycle = ATH_MCI_MAX_DUTY_CYCLE;
14233
14234 -       btcoex->btcoex_no_stomp =  btcoex->btcoex_period * 1000 *
14235 +       btcoex->btcoex_no_stomp =  btcoex->btcoex_period *
14236                 (100 - btcoex->duty_cycle) / 100;
14237
14238         ath9k_hw_btcoex_enable(sc->sc_ah);
14239 --- a/drivers/net/wireless/ath/ath9k/recv.c
14240 +++ b/drivers/net/wireless/ath/ath9k/recv.c
14241 @@ -15,7 +15,6 @@
14242   */
14243
14244  #include <linux/dma-mapping.h>
14245 -#include <linux/relay.h>
14246  #include "ath9k.h"
14247  #include "ar9003_mac.h"
14248
14249 @@ -906,6 +905,7 @@ static void ath9k_process_rssi(struct at
14250         struct ath_hw *ah = common->ah;
14251         int last_rssi;
14252         int rssi = rx_stats->rs_rssi;
14253 +       int i, j;
14254
14255         /*
14256          * RSSI is not available for subframes in an A-MPDU.
14257 @@ -924,6 +924,20 @@ static void ath9k_process_rssi(struct at
14258                 return;
14259         }
14260
14261 +       for (i = 0, j = 0; i < ARRAY_SIZE(rx_stats->rs_rssi_ctl); i++) {
14262 +               s8 rssi;
14263 +
14264 +               if (!(ah->rxchainmask & BIT(i)))
14265 +                       continue;
14266 +
14267 +               rssi = rx_stats->rs_rssi_ctl[i];
14268 +               if (rssi != ATH9K_RSSI_BAD) {
14269 +                   rxs->chains |= BIT(j);
14270 +                   rxs->chain_signal[j] = ah->noise + rssi;
14271 +               }
14272 +               j++;
14273 +       }
14274 +
14275         /*
14276          * Update Beacon RSSI, this is used by ANI.
14277          */
14278 @@ -960,186 +974,6 @@ static void ath9k_process_tsf(struct ath
14279                 rxs->mactime += 0x100000000ULL;
14280  }
14281
14282 -#ifdef CPTCFG_ATH9K_DEBUGFS
14283 -static s8 fix_rssi_inv_only(u8 rssi_val)
14284 -{
14285 -       if (rssi_val == 128)
14286 -               rssi_val = 0;
14287 -       return (s8) rssi_val;
14288 -}
14289 -#endif
14290 -
14291 -/* returns 1 if this was a spectral frame, even if not handled. */
14292 -static int ath_process_fft(struct ath_softc *sc, struct ieee80211_hdr *hdr,
14293 -                          struct ath_rx_status *rs, u64 tsf)
14294 -{
14295 -#ifdef CPTCFG_ATH9K_DEBUGFS
14296 -       struct ath_hw *ah = sc->sc_ah;
14297 -       u8 num_bins, *bins, *vdata = (u8 *)hdr;
14298 -       struct fft_sample_ht20 fft_sample_20;
14299 -       struct fft_sample_ht20_40 fft_sample_40;
14300 -       struct fft_sample_tlv *tlv;
14301 -       struct ath_radar_info *radar_info;
14302 -       int len = rs->rs_datalen;
14303 -       int dc_pos;
14304 -       u16 fft_len, length, freq = ah->curchan->chan->center_freq;
14305 -       enum nl80211_channel_type chan_type;
14306 -
14307 -       /* AR9280 and before report via ATH9K_PHYERR_RADAR, AR93xx and newer
14308 -        * via ATH9K_PHYERR_SPECTRAL. Haven't seen ATH9K_PHYERR_FALSE_RADAR_EXT
14309 -        * yet, but this is supposed to be possible as well.
14310 -        */
14311 -       if (rs->rs_phyerr != ATH9K_PHYERR_RADAR &&
14312 -           rs->rs_phyerr != ATH9K_PHYERR_FALSE_RADAR_EXT &&
14313 -           rs->rs_phyerr != ATH9K_PHYERR_SPECTRAL)
14314 -               return 0;
14315 -
14316 -       /* check if spectral scan bit is set. This does not have to be checked
14317 -        * if received through a SPECTRAL phy error, but shouldn't hurt.
14318 -        */
14319 -       radar_info = ((struct ath_radar_info *)&vdata[len]) - 1;
14320 -       if (!(radar_info->pulse_bw_info & SPECTRAL_SCAN_BITMASK))
14321 -               return 0;
14322 -
14323 -       chan_type = cfg80211_get_chandef_type(&sc->hw->conf.chandef);
14324 -       if ((chan_type == NL80211_CHAN_HT40MINUS) ||
14325 -           (chan_type == NL80211_CHAN_HT40PLUS)) {
14326 -               fft_len = SPECTRAL_HT20_40_TOTAL_DATA_LEN;
14327 -               num_bins = SPECTRAL_HT20_40_NUM_BINS;
14328 -               bins = (u8 *)fft_sample_40.data;
14329 -       } else {
14330 -               fft_len = SPECTRAL_HT20_TOTAL_DATA_LEN;
14331 -               num_bins = SPECTRAL_HT20_NUM_BINS;
14332 -               bins = (u8 *)fft_sample_20.data;
14333 -       }
14334 -
14335 -       /* Variation in the data length is possible and will be fixed later */
14336 -       if ((len > fft_len + 2) || (len < fft_len - 1))
14337 -               return 1;
14338 -
14339 -       switch (len - fft_len) {
14340 -       case 0:
14341 -               /* length correct, nothing to do. */
14342 -               memcpy(bins, vdata, num_bins);
14343 -               break;
14344 -       case -1:
14345 -               /* first byte missing, duplicate it. */
14346 -               memcpy(&bins[1], vdata, num_bins - 1);
14347 -               bins[0] = vdata[0];
14348 -               break;
14349 -       case 2:
14350 -               /* MAC added 2 extra bytes at bin 30 and 32, remove them. */
14351 -               memcpy(bins, vdata, 30);
14352 -               bins[30] = vdata[31];
14353 -               memcpy(&bins[31], &vdata[33], num_bins - 31);
14354 -               break;
14355 -       case 1:
14356 -               /* MAC added 2 extra bytes AND first byte is missing. */
14357 -               bins[0] = vdata[0];
14358 -               memcpy(&bins[1], vdata, 30);
14359 -               bins[31] = vdata[31];
14360 -               memcpy(&bins[32], &vdata[33], num_bins - 32);
14361 -               break;
14362 -       default:
14363 -               return 1;
14364 -       }
14365 -
14366 -       /* DC value (value in the middle) is the blind spot of the spectral
14367 -        * sample and invalid, interpolate it.
14368 -        */
14369 -       dc_pos = num_bins / 2;
14370 -       bins[dc_pos] = (bins[dc_pos + 1] + bins[dc_pos - 1]) / 2;
14371 -
14372 -       if ((chan_type == NL80211_CHAN_HT40MINUS) ||
14373 -           (chan_type == NL80211_CHAN_HT40PLUS)) {
14374 -               s8 lower_rssi, upper_rssi;
14375 -               s16 ext_nf;
14376 -               u8 lower_max_index, upper_max_index;
14377 -               u8 lower_bitmap_w, upper_bitmap_w;
14378 -               u16 lower_mag, upper_mag;
14379 -               struct ath9k_hw_cal_data *caldata = ah->caldata;
14380 -               struct ath_ht20_40_mag_info *mag_info;
14381 -
14382 -               if (caldata)
14383 -                       ext_nf = ath9k_hw_getchan_noise(ah, ah->curchan,
14384 -                                       caldata->nfCalHist[3].privNF);
14385 -               else
14386 -                       ext_nf = ATH_DEFAULT_NOISE_FLOOR;
14387 -
14388 -               length = sizeof(fft_sample_40) - sizeof(struct fft_sample_tlv);
14389 -               fft_sample_40.tlv.type = ATH_FFT_SAMPLE_HT20_40;
14390 -               fft_sample_40.tlv.length = __cpu_to_be16(length);
14391 -               fft_sample_40.freq = __cpu_to_be16(freq);
14392 -               fft_sample_40.channel_type = chan_type;
14393 -
14394 -               if (chan_type == NL80211_CHAN_HT40PLUS) {
14395 -                       lower_rssi = fix_rssi_inv_only(rs->rs_rssi_ctl0);
14396 -                       upper_rssi = fix_rssi_inv_only(rs->rs_rssi_ext0);
14397 -
14398 -                       fft_sample_40.lower_noise = ah->noise;
14399 -                       fft_sample_40.upper_noise = ext_nf;
14400 -               } else {
14401 -                       lower_rssi = fix_rssi_inv_only(rs->rs_rssi_ext0);
14402 -                       upper_rssi = fix_rssi_inv_only(rs->rs_rssi_ctl0);
14403 -
14404 -                       fft_sample_40.lower_noise = ext_nf;
14405 -                       fft_sample_40.upper_noise = ah->noise;
14406 -               }
14407 -               fft_sample_40.lower_rssi = lower_rssi;
14408 -               fft_sample_40.upper_rssi = upper_rssi;
14409 -
14410 -               mag_info = ((struct ath_ht20_40_mag_info *)radar_info) - 1;
14411 -               lower_mag = spectral_max_magnitude(mag_info->lower_bins);
14412 -               upper_mag = spectral_max_magnitude(mag_info->upper_bins);
14413 -               fft_sample_40.lower_max_magnitude = __cpu_to_be16(lower_mag);
14414 -               fft_sample_40.upper_max_magnitude = __cpu_to_be16(upper_mag);
14415 -               lower_max_index = spectral_max_index(mag_info->lower_bins);
14416 -               upper_max_index = spectral_max_index(mag_info->upper_bins);
14417 -               fft_sample_40.lower_max_index = lower_max_index;
14418 -               fft_sample_40.upper_max_index = upper_max_index;
14419 -               lower_bitmap_w = spectral_bitmap_weight(mag_info->lower_bins);
14420 -               upper_bitmap_w = spectral_bitmap_weight(mag_info->upper_bins);
14421 -               fft_sample_40.lower_bitmap_weight = lower_bitmap_w;
14422 -               fft_sample_40.upper_bitmap_weight = upper_bitmap_w;
14423 -               fft_sample_40.max_exp = mag_info->max_exp & 0xf;
14424 -
14425 -               fft_sample_40.tsf = __cpu_to_be64(tsf);
14426 -
14427 -               tlv = (struct fft_sample_tlv *)&fft_sample_40;
14428 -       } else {
14429 -               u8 max_index, bitmap_w;
14430 -               u16 magnitude;
14431 -               struct ath_ht20_mag_info *mag_info;
14432 -
14433 -               length = sizeof(fft_sample_20) - sizeof(struct fft_sample_tlv);
14434 -               fft_sample_20.tlv.type = ATH_FFT_SAMPLE_HT20;
14435 -               fft_sample_20.tlv.length = __cpu_to_be16(length);
14436 -               fft_sample_20.freq = __cpu_to_be16(freq);
14437 -
14438 -               fft_sample_20.rssi = fix_rssi_inv_only(rs->rs_rssi_ctl0);
14439 -               fft_sample_20.noise = ah->noise;
14440 -
14441 -               mag_info = ((struct ath_ht20_mag_info *)radar_info) - 1;
14442 -               magnitude = spectral_max_magnitude(mag_info->all_bins);
14443 -               fft_sample_20.max_magnitude = __cpu_to_be16(magnitude);
14444 -               max_index = spectral_max_index(mag_info->all_bins);
14445 -               fft_sample_20.max_index = max_index;
14446 -               bitmap_w = spectral_bitmap_weight(mag_info->all_bins);
14447 -               fft_sample_20.bitmap_weight = bitmap_w;
14448 -               fft_sample_20.max_exp = mag_info->max_exp & 0xf;
14449 -
14450 -               fft_sample_20.tsf = __cpu_to_be64(tsf);
14451 -
14452 -               tlv = (struct fft_sample_tlv *)&fft_sample_20;
14453 -       }
14454 -
14455 -       ath_debug_send_fft_sample(sc, tlv);
14456 -       return 1;
14457 -#else
14458 -       return 0;
14459 -#endif
14460 -}
14461 -
14462  static bool ath9k_is_mybeacon(struct ath_softc *sc, struct ieee80211_hdr *hdr)
14463  {
14464         struct ath_hw *ah = sc->sc_ah;
14465 --- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
14466 +++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
14467 @@ -270,10 +270,20 @@ struct cal_ctl_data_5g {
14468         u8 ctlEdges[AR9300_NUM_BAND_EDGES_5G];
14469  } __packed;
14470
14471 +#define MAX_BASE_EXTENSION_FUTURE 2
14472 +
14473  struct ar9300_BaseExtension_1 {
14474         u8 ant_div_control;
14475 -       u8 future[3];
14476 -       u8 tempslopextension[8];
14477 +       u8 future[MAX_BASE_EXTENSION_FUTURE];
14478 +       /*
14479 +        * misc_enable:
14480 +        *
14481 +        * BIT 0   - TX Gain Cap enable.
14482 +        * BIT 1   - Uncompressed Checksum enable.
14483 +        * BIT 2/3 - MinCCApwr enable 2g/5g.
14484 +        */
14485 +       u8 misc_enable;
14486 +       int8_t tempslopextension[8];
14487         int8_t quick_drop_low;
14488         int8_t quick_drop_high;
14489  } __packed;
14490 --- a/drivers/net/wireless/ath/ath9k/debug.h
14491 +++ b/drivers/net/wireless/ath/ath9k/debug.h
14492 @@ -292,11 +292,11 @@ void ath9k_sta_add_debugfs(struct ieee80
14493                            struct ieee80211_vif *vif,
14494                            struct ieee80211_sta *sta,
14495                            struct dentry *dir);
14496 -void ath_debug_send_fft_sample(struct ath_softc *sc,
14497 -                              struct fft_sample_tlv *fft_sample);
14498  void ath9k_debug_stat_ant(struct ath_softc *sc,
14499                           struct ath_hw_antcomb_conf *div_ant_conf,
14500                           int main_rssi_avg, int alt_rssi_avg);
14501 +void ath9k_debug_sync_cause(struct ath_softc *sc, u32 sync_cause);
14502 +
14503  #else
14504
14505  #define RX_STAT_INC(c) /* NOP */
14506 @@ -331,6 +331,11 @@ static inline void ath9k_debug_stat_ant(
14507
14508  }
14509
14510 +static inline void
14511 +ath9k_debug_sync_cause(struct ath_softc *sc, u32 sync_cause)
14512 +{
14513 +}
14514 +
14515  #endif /* CPTCFG_ATH9K_DEBUGFS */
14516
14517  #endif /* DEBUG_H */
14518 --- /dev/null
14519 +++ b/drivers/net/wireless/ath/ath9k/spectral.c
14520 @@ -0,0 +1,543 @@
14521 +/*
14522 + * Copyright (c) 2013 Qualcomm Atheros, Inc.
14523 + *
14524 + * Permission to use, copy, modify, and/or distribute this software for any
14525 + * purpose with or without fee is hereby granted, provided that the above
14526 + * copyright notice and this permission notice appear in all copies.
14527 + *
14528 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14529 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14530 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14531 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14532 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14533 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14534 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
14535 + */
14536 +
14537 +#include <linux/relay.h>
14538 +#include "ath9k.h"
14539 +
14540 +static s8 fix_rssi_inv_only(u8 rssi_val)
14541 +{
14542 +       if (rssi_val == 128)
14543 +               rssi_val = 0;
14544 +       return (s8) rssi_val;
14545 +}
14546 +
14547 +static void ath_debug_send_fft_sample(struct ath_softc *sc,
14548 +                                     struct fft_sample_tlv *fft_sample_tlv)
14549 +{
14550 +       int length;
14551 +       if (!sc->rfs_chan_spec_scan)
14552 +               return;
14553 +
14554 +       length = __be16_to_cpu(fft_sample_tlv->length) +
14555 +                sizeof(*fft_sample_tlv);
14556 +       relay_write(sc->rfs_chan_spec_scan, fft_sample_tlv, length);
14557 +}
14558 +
14559 +/* returns 1 if this was a spectral frame, even if not handled. */
14560 +int ath_process_fft(struct ath_softc *sc, struct ieee80211_hdr *hdr,
14561 +                   struct ath_rx_status *rs, u64 tsf)
14562 +{
14563 +       struct ath_hw *ah = sc->sc_ah;
14564 +       u8 num_bins, *bins, *vdata = (u8 *)hdr;
14565 +       struct fft_sample_ht20 fft_sample_20;
14566 +       struct fft_sample_ht20_40 fft_sample_40;
14567 +       struct fft_sample_tlv *tlv;
14568 +       struct ath_radar_info *radar_info;
14569 +       int len = rs->rs_datalen;
14570 +       int dc_pos;
14571 +       u16 fft_len, length, freq = ah->curchan->chan->center_freq;
14572 +       enum nl80211_channel_type chan_type;
14573 +
14574 +       /* AR9280 and before report via ATH9K_PHYERR_RADAR, AR93xx and newer
14575 +        * via ATH9K_PHYERR_SPECTRAL. Haven't seen ATH9K_PHYERR_FALSE_RADAR_EXT
14576 +        * yet, but this is supposed to be possible as well.
14577 +        */
14578 +       if (rs->rs_phyerr != ATH9K_PHYERR_RADAR &&
14579 +           rs->rs_phyerr != ATH9K_PHYERR_FALSE_RADAR_EXT &&
14580 +           rs->rs_phyerr != ATH9K_PHYERR_SPECTRAL)
14581 +               return 0;
14582 +
14583 +       /* check if spectral scan bit is set. This does not have to be checked
14584 +        * if received through a SPECTRAL phy error, but shouldn't hurt.
14585 +        */
14586 +       radar_info = ((struct ath_radar_info *)&vdata[len]) - 1;
14587 +       if (!(radar_info->pulse_bw_info & SPECTRAL_SCAN_BITMASK))
14588 +               return 0;
14589 +
14590 +       chan_type = cfg80211_get_chandef_type(&sc->hw->conf.chandef);
14591 +       if ((chan_type == NL80211_CHAN_HT40MINUS) ||
14592 +           (chan_type == NL80211_CHAN_HT40PLUS)) {
14593 +               fft_len = SPECTRAL_HT20_40_TOTAL_DATA_LEN;
14594 +               num_bins = SPECTRAL_HT20_40_NUM_BINS;
14595 +               bins = (u8 *)fft_sample_40.data;
14596 +       } else {
14597 +               fft_len = SPECTRAL_HT20_TOTAL_DATA_LEN;
14598 +               num_bins = SPECTRAL_HT20_NUM_BINS;
14599 +               bins = (u8 *)fft_sample_20.data;
14600 +       }
14601 +
14602 +       /* Variation in the data length is possible and will be fixed later */
14603 +       if ((len > fft_len + 2) || (len < fft_len - 1))
14604 +               return 1;
14605 +
14606 +       switch (len - fft_len) {
14607 +       case 0:
14608 +               /* length correct, nothing to do. */
14609 +               memcpy(bins, vdata, num_bins);
14610 +               break;
14611 +       case -1:
14612 +               /* first byte missing, duplicate it. */
14613 +               memcpy(&bins[1], vdata, num_bins - 1);
14614 +               bins[0] = vdata[0];
14615 +               break;
14616 +       case 2:
14617 +               /* MAC added 2 extra bytes at bin 30 and 32, remove them. */
14618 +               memcpy(bins, vdata, 30);
14619 +               bins[30] = vdata[31];
14620 +               memcpy(&bins[31], &vdata[33], num_bins - 31);
14621 +               break;
14622 +       case 1:
14623 +               /* MAC added 2 extra bytes AND first byte is missing. */
14624 +               bins[0] = vdata[0];
14625 +               memcpy(&bins[1], vdata, 30);
14626 +               bins[31] = vdata[31];
14627 +               memcpy(&bins[32], &vdata[33], num_bins - 32);
14628 +               break;
14629 +       default:
14630 +               return 1;
14631 +       }
14632 +
14633 +       /* DC value (value in the middle) is the blind spot of the spectral
14634 +        * sample and invalid, interpolate it.
14635 +        */
14636 +       dc_pos = num_bins / 2;
14637 +       bins[dc_pos] = (bins[dc_pos + 1] + bins[dc_pos - 1]) / 2;
14638 +
14639 +       if ((chan_type == NL80211_CHAN_HT40MINUS) ||
14640 +           (chan_type == NL80211_CHAN_HT40PLUS)) {
14641 +               s8 lower_rssi, upper_rssi;
14642 +               s16 ext_nf;
14643 +               u8 lower_max_index, upper_max_index;
14644 +               u8 lower_bitmap_w, upper_bitmap_w;
14645 +               u16 lower_mag, upper_mag;
14646 +               struct ath9k_hw_cal_data *caldata = ah->caldata;
14647 +               struct ath_ht20_40_mag_info *mag_info;
14648 +
14649 +               if (caldata)
14650 +                       ext_nf = ath9k_hw_getchan_noise(ah, ah->curchan,
14651 +                                       caldata->nfCalHist[3].privNF);
14652 +               else
14653 +                       ext_nf = ATH_DEFAULT_NOISE_FLOOR;
14654 +
14655 +               length = sizeof(fft_sample_40) - sizeof(struct fft_sample_tlv);
14656 +               fft_sample_40.tlv.type = ATH_FFT_SAMPLE_HT20_40;
14657 +               fft_sample_40.tlv.length = __cpu_to_be16(length);
14658 +               fft_sample_40.freq = __cpu_to_be16(freq);
14659 +               fft_sample_40.channel_type = chan_type;
14660 +
14661 +               if (chan_type == NL80211_CHAN_HT40PLUS) {
14662 +                       lower_rssi = fix_rssi_inv_only(rs->rs_rssi_ctl[0]);
14663 +                       upper_rssi = fix_rssi_inv_only(rs->rs_rssi_ext[0]);
14664 +
14665 +                       fft_sample_40.lower_noise = ah->noise;
14666 +                       fft_sample_40.upper_noise = ext_nf;
14667 +               } else {
14668 +                       lower_rssi = fix_rssi_inv_only(rs->rs_rssi_ext[0]);
14669 +                       upper_rssi = fix_rssi_inv_only(rs->rs_rssi_ctl[0]);
14670 +
14671 +                       fft_sample_40.lower_noise = ext_nf;
14672 +                       fft_sample_40.upper_noise = ah->noise;
14673 +               }
14674 +               fft_sample_40.lower_rssi = lower_rssi;
14675 +               fft_sample_40.upper_rssi = upper_rssi;
14676 +
14677 +               mag_info = ((struct ath_ht20_40_mag_info *)radar_info) - 1;
14678 +               lower_mag = spectral_max_magnitude(mag_info->lower_bins);
14679 +               upper_mag = spectral_max_magnitude(mag_info->upper_bins);
14680 +               fft_sample_40.lower_max_magnitude = __cpu_to_be16(lower_mag);
14681 +               fft_sample_40.upper_max_magnitude = __cpu_to_be16(upper_mag);
14682 +               lower_max_index = spectral_max_index(mag_info->lower_bins);
14683 +               upper_max_index = spectral_max_index(mag_info->upper_bins);
14684 +               fft_sample_40.lower_max_index = lower_max_index;
14685 +               fft_sample_40.upper_max_index = upper_max_index;
14686 +               lower_bitmap_w = spectral_bitmap_weight(mag_info->lower_bins);
14687 +               upper_bitmap_w = spectral_bitmap_weight(mag_info->upper_bins);
14688 +               fft_sample_40.lower_bitmap_weight = lower_bitmap_w;
14689 +               fft_sample_40.upper_bitmap_weight = upper_bitmap_w;
14690 +               fft_sample_40.max_exp = mag_info->max_exp & 0xf;
14691 +
14692 +               fft_sample_40.tsf = __cpu_to_be64(tsf);
14693 +
14694 +               tlv = (struct fft_sample_tlv *)&fft_sample_40;
14695 +       } else {
14696 +               u8 max_index, bitmap_w;
14697 +               u16 magnitude;
14698 +               struct ath_ht20_mag_info *mag_info;
14699 +
14700 +               length = sizeof(fft_sample_20) - sizeof(struct fft_sample_tlv);
14701 +               fft_sample_20.tlv.type = ATH_FFT_SAMPLE_HT20;
14702 +               fft_sample_20.tlv.length = __cpu_to_be16(length);
14703 +               fft_sample_20.freq = __cpu_to_be16(freq);
14704 +
14705 +               fft_sample_20.rssi = fix_rssi_inv_only(rs->rs_rssi_ctl[0]);
14706 +               fft_sample_20.noise = ah->noise;
14707 +
14708 +               mag_info = ((struct ath_ht20_mag_info *)radar_info) - 1;
14709 +               magnitude = spectral_max_magnitude(mag_info->all_bins);
14710 +               fft_sample_20.max_magnitude = __cpu_to_be16(magnitude);
14711 +               max_index = spectral_max_index(mag_info->all_bins);
14712 +               fft_sample_20.max_index = max_index;
14713 +               bitmap_w = spectral_bitmap_weight(mag_info->all_bins);
14714 +               fft_sample_20.bitmap_weight = bitmap_w;
14715 +               fft_sample_20.max_exp = mag_info->max_exp & 0xf;
14716 +
14717 +               fft_sample_20.tsf = __cpu_to_be64(tsf);
14718 +
14719 +               tlv = (struct fft_sample_tlv *)&fft_sample_20;
14720 +       }
14721 +
14722 +       ath_debug_send_fft_sample(sc, tlv);
14723 +
14724 +       return 1;
14725 +}
14726 +
14727 +/*********************/
14728 +/* spectral_scan_ctl */
14729 +/*********************/
14730 +
14731 +static ssize_t read_file_spec_scan_ctl(struct file *file, char __user *user_buf,
14732 +                                      size_t count, loff_t *ppos)
14733 +{
14734 +       struct ath_softc *sc = file->private_data;
14735 +       char *mode = "";
14736 +       unsigned int len;
14737 +
14738 +       switch (sc->spectral_mode) {
14739 +       case SPECTRAL_DISABLED:
14740 +               mode = "disable";
14741 +               break;
14742 +       case SPECTRAL_BACKGROUND:
14743 +               mode = "background";
14744 +               break;
14745 +       case SPECTRAL_CHANSCAN:
14746 +               mode = "chanscan";
14747 +               break;
14748 +       case SPECTRAL_MANUAL:
14749 +               mode = "manual";
14750 +               break;
14751 +       }
14752 +       len = strlen(mode);
14753 +       return simple_read_from_buffer(user_buf, count, ppos, mode, len);
14754 +}
14755 +
14756 +static ssize_t write_file_spec_scan_ctl(struct file *file,
14757 +                                       const char __user *user_buf,
14758 +                                       size_t count, loff_t *ppos)
14759 +{
14760 +       struct ath_softc *sc = file->private_data;
14761 +       struct ath_common *common = ath9k_hw_common(sc->sc_ah);
14762 +       char buf[32];
14763 +       ssize_t len;
14764 +
14765 +       if (config_enabled(CPTCFG_ATH9K_TX99))
14766 +               return -EOPNOTSUPP;
14767 +
14768 +       len = min(count, sizeof(buf) - 1);
14769 +       if (copy_from_user(buf, user_buf, len))
14770 +               return -EFAULT;
14771 +
14772 +       buf[len] = '\0';
14773 +
14774 +       if (strncmp("trigger", buf, 7) == 0) {
14775 +               ath9k_spectral_scan_trigger(sc->hw);
14776 +       } else if (strncmp("background", buf, 9) == 0) {
14777 +               ath9k_spectral_scan_config(sc->hw, SPECTRAL_BACKGROUND);
14778 +               ath_dbg(common, CONFIG, "spectral scan: background mode enabled\n");
14779 +       } else if (strncmp("chanscan", buf, 8) == 0) {
14780 +               ath9k_spectral_scan_config(sc->hw, SPECTRAL_CHANSCAN);
14781 +               ath_dbg(common, CONFIG, "spectral scan: channel scan mode enabled\n");
14782 +       } else if (strncmp("manual", buf, 6) == 0) {
14783 +               ath9k_spectral_scan_config(sc->hw, SPECTRAL_MANUAL);
14784 +               ath_dbg(common, CONFIG, "spectral scan: manual mode enabled\n");
14785 +       } else if (strncmp("disable", buf, 7) == 0) {
14786 +               ath9k_spectral_scan_config(sc->hw, SPECTRAL_DISABLED);
14787 +               ath_dbg(common, CONFIG, "spectral scan: disabled\n");
14788 +       } else {
14789 +               return -EINVAL;
14790 +       }
14791 +
14792 +       return count;
14793 +}
14794 +
14795 +static const struct file_operations fops_spec_scan_ctl = {
14796 +       .read = read_file_spec_scan_ctl,
14797 +       .write = write_file_spec_scan_ctl,
14798 +       .open = simple_open,
14799 +       .owner = THIS_MODULE,
14800 +       .llseek = default_llseek,
14801 +};
14802 +
14803 +/*************************/
14804 +/* spectral_short_repeat */
14805 +/*************************/
14806 +
14807 +static ssize_t read_file_spectral_short_repeat(struct file *file,
14808 +                                              char __user *user_buf,
14809 +                                              size_t count, loff_t *ppos)
14810 +{
14811 +       struct ath_softc *sc = file->private_data;
14812 +       char buf[32];
14813 +       unsigned int len;
14814 +
14815 +       len = sprintf(buf, "%d\n", sc->spec_config.short_repeat);
14816 +       return simple_read_from_buffer(user_buf, count, ppos, buf, len);
14817 +}
14818 +
14819 +static ssize_t write_file_spectral_short_repeat(struct file *file,
14820 +                                               const char __user *user_buf,
14821 +                                               size_t count, loff_t *ppos)
14822 +{
14823 +       struct ath_softc *sc = file->private_data;
14824 +       unsigned long val;
14825 +       char buf[32];
14826 +       ssize_t len;
14827 +
14828 +       len = min(count, sizeof(buf) - 1);
14829 +       if (copy_from_user(buf, user_buf, len))
14830 +               return -EFAULT;
14831 +
14832 +       buf[len] = '\0';
14833 +       if (kstrtoul(buf, 0, &val))
14834 +               return -EINVAL;
14835 +
14836 +       if (val < 0 || val > 1)
14837 +               return -EINVAL;
14838 +
14839 +       sc->spec_config.short_repeat = val;
14840 +       return count;
14841 +}
14842 +
14843 +static const struct file_operations fops_spectral_short_repeat = {
14844 +       .read = read_file_spectral_short_repeat,
14845 +       .write = write_file_spectral_short_repeat,
14846 +       .open = simple_open,
14847 +       .owner = THIS_MODULE,
14848 +       .llseek = default_llseek,
14849 +};
14850 +
14851 +/******************/
14852 +/* spectral_count */
14853 +/******************/
14854 +
14855 +static ssize_t read_file_spectral_count(struct file *file,
14856 +                                       char __user *user_buf,
14857 +                                       size_t count, loff_t *ppos)
14858 +{
14859 +       struct ath_softc *sc = file->private_data;
14860 +       char buf[32];
14861 +       unsigned int len;
14862 +
14863 +       len = sprintf(buf, "%d\n", sc->spec_config.count);
14864 +       return simple_read_from_buffer(user_buf, count, ppos, buf, len);
14865 +}
14866 +
14867 +static ssize_t write_file_spectral_count(struct file *file,
14868 +                                        const char __user *user_buf,
14869 +                                        size_t count, loff_t *ppos)
14870 +{
14871 +       struct ath_softc *sc = file->private_data;
14872 +       unsigned long val;
14873 +       char buf[32];
14874 +       ssize_t len;
14875 +
14876 +       len = min(count, sizeof(buf) - 1);
14877 +       if (copy_from_user(buf, user_buf, len))
14878 +               return -EFAULT;
14879 +
14880 +       buf[len] = '\0';
14881 +       if (kstrtoul(buf, 0, &val))
14882 +               return -EINVAL;
14883 +
14884 +       if (val < 0 || val > 255)
14885 +               return -EINVAL;
14886 +
14887 +       sc->spec_config.count = val;
14888 +       return count;
14889 +}
14890 +
14891 +static const struct file_operations fops_spectral_count = {
14892 +       .read = read_file_spectral_count,
14893 +       .write = write_file_spectral_count,
14894 +       .open = simple_open,
14895 +       .owner = THIS_MODULE,
14896 +       .llseek = default_llseek,
14897 +};
14898 +
14899 +/*******************/
14900 +/* spectral_period */
14901 +/*******************/
14902 +
14903 +static ssize_t read_file_spectral_period(struct file *file,
14904 +                                        char __user *user_buf,
14905 +                                        size_t count, loff_t *ppos)
14906 +{
14907 +       struct ath_softc *sc = file->private_data;
14908 +       char buf[32];
14909 +       unsigned int len;
14910 +
14911 +       len = sprintf(buf, "%d\n", sc->spec_config.period);
14912 +       return simple_read_from_buffer(user_buf, count, ppos, buf, len);
14913 +}
14914 +
14915 +static ssize_t write_file_spectral_period(struct file *file,
14916 +                                         const char __user *user_buf,
14917 +                                         size_t count, loff_t *ppos)
14918 +{
14919 +       struct ath_softc *sc = file->private_data;
14920 +       unsigned long val;
14921 +       char buf[32];
14922 +       ssize_t len;
14923 +
14924 +       len = min(count, sizeof(buf) - 1);
14925 +       if (copy_from_user(buf, user_buf, len))
14926 +               return -EFAULT;
14927 +
14928 +       buf[len] = '\0';
14929 +       if (kstrtoul(buf, 0, &val))
14930 +               return -EINVAL;
14931 +
14932 +       if (val < 0 || val > 255)
14933 +               return -EINVAL;
14934 +
14935 +       sc->spec_config.period = val;
14936 +       return count;
14937 +}
14938 +
14939 +static const struct file_operations fops_spectral_period = {
14940 +       .read = read_file_spectral_period,
14941 +       .write = write_file_spectral_period,
14942 +       .open = simple_open,
14943 +       .owner = THIS_MODULE,
14944 +       .llseek = default_llseek,
14945 +};
14946 +
14947 +/***********************/
14948 +/* spectral_fft_period */
14949 +/***********************/
14950 +
14951 +static ssize_t read_file_spectral_fft_period(struct file *file,
14952 +                                            char __user *user_buf,
14953 +                                            size_t count, loff_t *ppos)
14954 +{
14955 +       struct ath_softc *sc = file->private_data;
14956 +       char buf[32];
14957 +       unsigned int len;
14958 +
14959 +       len = sprintf(buf, "%d\n", sc->spec_config.fft_period);
14960 +       return simple_read_from_buffer(user_buf, count, ppos, buf, len);
14961 +}
14962 +
14963 +static ssize_t write_file_spectral_fft_period(struct file *file,
14964 +                                             const char __user *user_buf,
14965 +                                             size_t count, loff_t *ppos)
14966 +{
14967 +       struct ath_softc *sc = file->private_data;
14968 +       unsigned long val;
14969 +       char buf[32];
14970 +       ssize_t len;
14971 +
14972 +       len = min(count, sizeof(buf) - 1);
14973 +       if (copy_from_user(buf, user_buf, len))
14974 +               return -EFAULT;
14975 +
14976 +       buf[len] = '\0';
14977 +       if (kstrtoul(buf, 0, &val))
14978 +               return -EINVAL;
14979 +
14980 +       if (val < 0 || val > 15)
14981 +               return -EINVAL;
14982 +
14983 +       sc->spec_config.fft_period = val;
14984 +       return count;
14985 +}
14986 +
14987 +static const struct file_operations fops_spectral_fft_period = {
14988 +       .read = read_file_spectral_fft_period,
14989 +       .write = write_file_spectral_fft_period,
14990 +       .open = simple_open,
14991 +       .owner = THIS_MODULE,
14992 +       .llseek = default_llseek,
14993 +};
14994 +
14995 +/*******************/
14996 +/* Relay interface */
14997 +/*******************/
14998 +
14999 +static struct dentry *create_buf_file_handler(const char *filename,
15000 +                                             struct dentry *parent,
15001 +                                             umode_t mode,
15002 +                                             struct rchan_buf *buf,
15003 +                                             int *is_global)
15004 +{
15005 +       struct dentry *buf_file;
15006 +
15007 +       buf_file = debugfs_create_file(filename, mode, parent, buf,
15008 +                                      &relay_file_operations);
15009 +       *is_global = 1;
15010 +       return buf_file;
15011 +}
15012 +
15013 +static int remove_buf_file_handler(struct dentry *dentry)
15014 +{
15015 +       debugfs_remove(dentry);
15016 +
15017 +       return 0;
15018 +}
15019 +
15020 +struct rchan_callbacks rfs_spec_scan_cb = {
15021 +       .create_buf_file = create_buf_file_handler,
15022 +       .remove_buf_file = remove_buf_file_handler,
15023 +};
15024 +
15025 +/*********************/
15026 +/* Debug Init/Deinit */
15027 +/*********************/
15028 +
15029 +void ath9k_spectral_deinit_debug(struct ath_softc *sc)
15030 +{
15031 +       if (config_enabled(CPTCFG_ATH9K_DEBUGFS) && sc->rfs_chan_spec_scan) {
15032 +               relay_close(sc->rfs_chan_spec_scan);
15033 +               sc->rfs_chan_spec_scan = NULL;
15034 +       }
15035 +}
15036 +
15037 +void ath9k_spectral_init_debug(struct ath_softc *sc)
15038 +{
15039 +       sc->rfs_chan_spec_scan = relay_open("spectral_scan",
15040 +                                           sc->debug.debugfs_phy,
15041 +                                           1024, 256, &rfs_spec_scan_cb,
15042 +                                           NULL);
15043 +       debugfs_create_file("spectral_scan_ctl",
15044 +                           S_IRUSR | S_IWUSR,
15045 +                           sc->debug.debugfs_phy, sc,
15046 +                           &fops_spec_scan_ctl);
15047 +       debugfs_create_file("spectral_short_repeat",
15048 +                           S_IRUSR | S_IWUSR,
15049 +                           sc->debug.debugfs_phy, sc,
15050 +                           &fops_spectral_short_repeat);
15051 +       debugfs_create_file("spectral_count",
15052 +                           S_IRUSR | S_IWUSR,
15053 +                           sc->debug.debugfs_phy, sc,
15054 +                           &fops_spectral_count);
15055 +       debugfs_create_file("spectral_period",
15056 +                           S_IRUSR | S_IWUSR,
15057 +                           sc->debug.debugfs_phy, sc,
15058 +                           &fops_spectral_period);
15059 +       debugfs_create_file("spectral_fft_period",
15060 +                           S_IRUSR | S_IWUSR,
15061 +                           sc->debug.debugfs_phy, sc,
15062 +                           &fops_spectral_fft_period);
15063 +}
15064 --- /dev/null
15065 +++ b/drivers/net/wireless/ath/ath9k/spectral.h
15066 @@ -0,0 +1,212 @@
15067 +/*
15068 + * Copyright (c) 2013 Qualcomm Atheros, Inc.
15069 + *
15070 + * Permission to use, copy, modify, and/or distribute this software for any
15071 + * purpose with or without fee is hereby granted, provided that the above
15072 + * copyright notice and this permission notice appear in all copies.
15073 + *
15074 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
15075 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
15076 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15077 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15078 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15079 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15080 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15081 + */
15082 +
15083 +#ifndef SPECTRAL_H
15084 +#define SPECTRAL_H
15085 +
15086 +/* enum spectral_mode:
15087 + *
15088 + * @SPECTRAL_DISABLED: spectral mode is disabled
15089 + * @SPECTRAL_BACKGROUND: hardware sends samples when it is not busy with
15090 + *     something else.
15091 + * @SPECTRAL_MANUAL: spectral scan is enabled, triggering for samples
15092 + *     is performed manually.
15093 + * @SPECTRAL_CHANSCAN: Like manual, but also triggered when changing channels
15094 + *     during a channel scan.
15095 + */
15096 +enum spectral_mode {
15097 +       SPECTRAL_DISABLED = 0,
15098 +       SPECTRAL_BACKGROUND,
15099 +       SPECTRAL_MANUAL,
15100 +       SPECTRAL_CHANSCAN,
15101 +};
15102 +
15103 +#define SPECTRAL_SCAN_BITMASK          0x10
15104 +/* Radar info packet format, used for DFS and spectral formats. */
15105 +struct ath_radar_info {
15106 +       u8 pulse_length_pri;
15107 +       u8 pulse_length_ext;
15108 +       u8 pulse_bw_info;
15109 +} __packed;
15110 +
15111 +/* The HT20 spectral data has 4 bytes of additional information at it's end.
15112 + *
15113 + * [7:0]: all bins {max_magnitude[1:0], bitmap_weight[5:0]}
15114 + * [7:0]: all bins  max_magnitude[9:2]
15115 + * [7:0]: all bins {max_index[5:0], max_magnitude[11:10]}
15116 + * [3:0]: max_exp (shift amount to size max bin to 8-bit unsigned)
15117 + */
15118 +struct ath_ht20_mag_info {
15119 +       u8 all_bins[3];
15120 +       u8 max_exp;
15121 +} __packed;
15122 +
15123 +#define SPECTRAL_HT20_NUM_BINS         56
15124 +
15125 +/* WARNING: don't actually use this struct! MAC may vary the amount of
15126 + * data by -1/+2. This struct is for reference only.
15127 + */
15128 +struct ath_ht20_fft_packet {
15129 +       u8 data[SPECTRAL_HT20_NUM_BINS];
15130 +       struct ath_ht20_mag_info mag_info;
15131 +       struct ath_radar_info radar_info;
15132 +} __packed;
15133 +
15134 +#define SPECTRAL_HT20_TOTAL_DATA_LEN   (sizeof(struct ath_ht20_fft_packet))
15135 +
15136 +/* Dynamic 20/40 mode:
15137 + *
15138 + * [7:0]: lower bins {max_magnitude[1:0], bitmap_weight[5:0]}
15139 + * [7:0]: lower bins  max_magnitude[9:2]
15140 + * [7:0]: lower bins {max_index[5:0], max_magnitude[11:10]}
15141 + * [7:0]: upper bins {max_magnitude[1:0], bitmap_weight[5:0]}
15142 + * [7:0]: upper bins  max_magnitude[9:2]
15143 + * [7:0]: upper bins {max_index[5:0], max_magnitude[11:10]}
15144 + * [3:0]: max_exp (shift amount to size max bin to 8-bit unsigned)
15145 + */
15146 +struct ath_ht20_40_mag_info {
15147 +       u8 lower_bins[3];
15148 +       u8 upper_bins[3];
15149 +       u8 max_exp;
15150 +} __packed;
15151 +
15152 +#define SPECTRAL_HT20_40_NUM_BINS              128
15153 +
15154 +/* WARNING: don't actually use this struct! MAC may vary the amount of
15155 + * data. This struct is for reference only.
15156 + */
15157 +struct ath_ht20_40_fft_packet {
15158 +       u8 data[SPECTRAL_HT20_40_NUM_BINS];
15159 +       struct ath_ht20_40_mag_info mag_info;
15160 +       struct ath_radar_info radar_info;
15161 +} __packed;
15162 +
15163 +
15164 +#define SPECTRAL_HT20_40_TOTAL_DATA_LEN        (sizeof(struct ath_ht20_40_fft_packet))
15165 +
15166 +/* grabs the max magnitude from the all/upper/lower bins */
15167 +static inline u16 spectral_max_magnitude(u8 *bins)
15168 +{
15169 +       return (bins[0] & 0xc0) >> 6 |
15170 +              (bins[1] & 0xff) << 2 |
15171 +              (bins[2] & 0x03) << 10;
15172 +}
15173 +
15174 +/* return the max magnitude from the all/upper/lower bins */
15175 +static inline u8 spectral_max_index(u8 *bins)
15176 +{
15177 +       s8 m = (bins[2] & 0xfc) >> 2;
15178 +
15179 +       /* TODO: this still doesn't always report the right values ... */
15180 +       if (m > 32)
15181 +               m |= 0xe0;
15182 +       else
15183 +               m &= ~0xe0;
15184 +
15185 +       return m + 29;
15186 +}
15187 +
15188 +/* return the bitmap weight from the all/upper/lower bins */
15189 +static inline u8 spectral_bitmap_weight(u8 *bins)
15190 +{
15191 +       return bins[0] & 0x3f;
15192 +}
15193 +
15194 +/* FFT sample format given to userspace via debugfs.
15195 + *
15196 + * Please keep the type/length at the front position and change
15197 + * other fields after adding another sample type
15198 + *
15199 + * TODO: this might need rework when switching to nl80211-based
15200 + * interface.
15201 + */
15202 +enum ath_fft_sample_type {
15203 +       ATH_FFT_SAMPLE_HT20 = 1,
15204 +       ATH_FFT_SAMPLE_HT20_40,
15205 +};
15206 +
15207 +struct fft_sample_tlv {
15208 +       u8 type;        /* see ath_fft_sample */
15209 +       __be16 length;
15210 +       /* type dependent data follows */
15211 +} __packed;
15212 +
15213 +struct fft_sample_ht20 {
15214 +       struct fft_sample_tlv tlv;
15215 +
15216 +       u8 max_exp;
15217 +
15218 +       __be16 freq;
15219 +       s8 rssi;
15220 +       s8 noise;
15221 +
15222 +       __be16 max_magnitude;
15223 +       u8 max_index;
15224 +       u8 bitmap_weight;
15225 +
15226 +       __be64 tsf;
15227 +
15228 +       u8 data[SPECTRAL_HT20_NUM_BINS];
15229 +} __packed;
15230 +
15231 +struct fft_sample_ht20_40 {
15232 +       struct fft_sample_tlv tlv;
15233 +
15234 +       u8 channel_type;
15235 +       __be16 freq;
15236 +
15237 +       s8 lower_rssi;
15238 +       s8 upper_rssi;
15239 +
15240 +       __be64 tsf;
15241 +
15242 +       s8 lower_noise;
15243 +       s8 upper_noise;
15244 +
15245 +       __be16 lower_max_magnitude;
15246 +       __be16 upper_max_magnitude;
15247 +
15248 +       u8 lower_max_index;
15249 +       u8 upper_max_index;
15250 +
15251 +       u8 lower_bitmap_weight;
15252 +       u8 upper_bitmap_weight;
15253 +
15254 +       u8 max_exp;
15255 +
15256 +       u8 data[SPECTRAL_HT20_40_NUM_BINS];
15257 +} __packed;
15258 +
15259 +void ath9k_spectral_init_debug(struct ath_softc *sc);
15260 +void ath9k_spectral_deinit_debug(struct ath_softc *sc);
15261 +
15262 +void ath9k_spectral_scan_trigger(struct ieee80211_hw *hw);
15263 +int ath9k_spectral_scan_config(struct ieee80211_hw *hw,
15264 +                              enum spectral_mode spectral_mode);
15265 +
15266 +#ifdef CPTCFG_ATH9K_DEBUGFS
15267 +int ath_process_fft(struct ath_softc *sc, struct ieee80211_hdr *hdr,
15268 +                   struct ath_rx_status *rs, u64 tsf);
15269 +#else
15270 +static inline int ath_process_fft(struct ath_softc *sc,
15271 +                                 struct ieee80211_hdr *hdr,
15272 +                                 struct ath_rx_status *rs, u64 tsf)
15273 +{
15274 +       return 0;
15275 +}
15276 +#endif /* CPTCFG_ATH9K_DEBUGFS */
15277 +
15278 +#endif /* SPECTRAL_H */
15279 --- a/include/net/mac80211.h
15280 +++ b/include/net/mac80211.h
15281 @@ -1566,6 +1566,9 @@ enum ieee80211_hw_flags {
15282   * @extra_tx_headroom: headroom to reserve in each transmit skb
15283   *     for use by the driver (e.g. for transmit headers.)
15284   *
15285 + * @extra_beacon_tailroom: tailroom to reserve in each beacon tx skb.
15286 + *     Can be used by drivers to add extra IEs.
15287 + *
15288   * @channel_change_time: time (in microseconds) it takes to change channels.
15289   *
15290   * @max_signal: Maximum value for signal (rssi) in RX information, used
15291 @@ -1644,6 +1647,7 @@ struct ieee80211_hw {
15292         void *priv;
15293         u32 flags;
15294         unsigned int extra_tx_headroom;
15295 +       unsigned int extra_beacon_tailroom;
15296         int channel_change_time;
15297         int vif_data_size;
15298         int sta_data_size;
15299 @@ -4595,4 +4599,49 @@ bool ieee80211_tx_prepare_skb(struct iee
15300                               struct ieee80211_vif *vif, struct sk_buff *skb,
15301                               int band, struct ieee80211_sta **sta);
15302
15303 +/**
15304 + * struct ieee80211_noa_data - holds temporary data for tracking P2P NoA state
15305 + *
15306 + * @next_tsf: TSF timestamp of the next absent state change
15307 + * @has_next_tsf: next absent state change event pending
15308 + *
15309 + * @absent: descriptor bitmask, set if GO is currently absent
15310 + *
15311 + * private:
15312 + *
15313 + * @count: count fields from the NoA descriptors
15314 + * @desc: adjusted data from the NoA
15315 + */
15316 +struct ieee80211_noa_data {
15317 +       u32 next_tsf;
15318 +       bool has_next_tsf;
15319 +
15320 +       u8 absent;
15321 +
15322 +       u8 count[IEEE80211_P2P_NOA_DESC_MAX];
15323 +       struct {
15324 +               u32 start;
15325 +               u32 duration;
15326 +               u32 interval;
15327 +       } desc[IEEE80211_P2P_NOA_DESC_MAX];
15328 +};
15329 +
15330 +/**
15331 + * ieee80211_parse_p2p_noa - initialize NoA tracking data from P2P IE
15332 + *
15333 + * @attr: P2P NoA IE
15334 + * @data: NoA tracking data
15335 + * @tsf: current TSF timestamp
15336 + */
15337 +int ieee80211_parse_p2p_noa(const struct ieee80211_p2p_noa_attr *attr,
15338 +                           struct ieee80211_noa_data *data, u32 tsf);
15339 +
15340 +/**
15341 + * ieee80211_update_p2p_noa - get next pending P2P GO absent state change
15342 + *
15343 + * @data: NoA tracking data
15344 + * @tsf: current TSF timestamp
15345 + */
15346 +void ieee80211_update_p2p_noa(struct ieee80211_noa_data *data, u32 tsf);
15347 +
15348  #endif /* MAC80211_H */
15349 --- a/drivers/net/wireless/ath/ath9k/hw-ops.h
15350 +++ b/drivers/net/wireless/ath/ath9k/hw-ops.h
15351 @@ -49,9 +49,10 @@ static inline bool ath9k_hw_calibrate(st
15352         return ath9k_hw_ops(ah)->calibrate(ah, chan, rxchainmask, longcal);
15353  }
15354
15355 -static inline bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
15356 +static inline bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked,
15357 +                                  u32 *sync_cause_p)
15358  {
15359 -       return ath9k_hw_ops(ah)->get_isr(ah, masked);
15360 +       return ath9k_hw_ops(ah)->get_isr(ah, masked, sync_cause_p);
15361  }
15362
15363  static inline void ath9k_hw_set_txdesc(struct ath_hw *ah, void *ds,