package/kernel/mac80211/patches/300-pending_work.patch

   1 --- a/drivers/net/wireless/ath/ath10k/mac.c
   2 +++ b/drivers/net/wireless/ath/ath10k/mac.c
   3 @@ -1351,12 +1351,12 @@ static int ath10k_update_channel_list(st
   4                         ch->allow_vht = true;
   5
   6                         ch->allow_ibss =
   7 -                               !(channel->flags & IEEE80211_CHAN_NO_IBSS);
   8 +                               !(channel->flags & IEEE80211_CHAN_NO_IR);
   9
  10                         ch->ht40plus =
  11                                 !(channel->flags & IEEE80211_CHAN_NO_HT40PLUS);
  12
  13 -                       passive = channel->flags & IEEE80211_CHAN_PASSIVE_SCAN;
  14 +                       passive = channel->flags & IEEE80211_CHAN_NO_IR;
  15                         ch->passive = passive;
  16
  17                         ch->freq = channel->center_freq;
  18 --- a/drivers/net/wireless/ath/ath9k/Kconfig
  19 +++ b/drivers/net/wireless/ath/ath9k/Kconfig
  20 @@ -90,7 +90,7 @@ config ATH9K_DFS_CERTIFIED
  21
  22  config ATH9K_TX99
  23         bool "Atheros ath9k TX99 testing support"
  24 -       depends on CFG80211_CERTIFICATION_ONUS
  25 +       depends on ATH9K_DEBUGFS && CFG80211_CERTIFICATION_ONUS
  26         default n
  27         ---help---
  28           Say N. This should only be enabled on systems undergoing
  29 @@ -108,6 +108,14 @@ config ATH9K_TX99
  30           be evaluated to meet the RF exposure limits set forth in the
  31           governmental SAR regulations.
  32
  33 +config ATH9K_WOW
  34 +       bool "Wake on Wireless LAN support (EXPERIMENTAL)"
  35 +       depends on ATH9K && PM
  36 +       default n
  37 +       ---help---
  38 +         This option enables Wake on Wireless LAN support for certain cards.
  39 +         Currently, AR9462 is supported.
  40 +
  41  config ATH9K_LEGACY_RATE_CONTROL
  42         bool "Atheros ath9k rate control"
  43         depends on ATH9K
  44 --- a/drivers/net/wireless/ath/ath9k/Makefile
  45 +++ b/drivers/net/wireless/ath/ath9k/Makefile
  46 @@ -11,11 +11,13 @@ ath9k-$(CPTCFG_ATH9K_BTCOEX_SUPPORT) +=
  47  ath9k-$(CPTCFG_ATH9K_LEGACY_RATE_CONTROL) += rc.o
  48  ath9k-$(CPTCFG_ATH9K_PCI) += pci.o
  49  ath9k-$(CPTCFG_ATH9K_AHB) += ahb.o
  50 -ath9k-$(CPTCFG_ATH9K_DEBUGFS) += debug.o
  51  ath9k-$(CPTCFG_ATH9K_DFS_DEBUGFS) += dfs_debug.o
  52 -ath9k-$(CPTCFG_ATH9K_DFS_CERTIFIED) += \
  53 -               dfs.o
  54 -ath9k-$(CONFIG_PM_SLEEP) += wow.o
  55 +ath9k-$(CPTCFG_ATH9K_DFS_CERTIFIED) += dfs.o
  56 +ath9k-$(CPTCFG_ATH9K_TX99) += tx99.o
  57 +ath9k-$(CPTCFG_ATH9K_WOW) += wow.o
  58 +
  59 +ath9k-$(CPTCFG_ATH9K_DEBUGFS) += debug.o \
  60 +                                spectral.o
  61
  62  obj-$(CPTCFG_ATH9K) += ath9k.o
  63
  64 @@ -41,6 +43,8 @@ ath9k_hw-y:=  \
  65                 ar9003_eeprom.o \
  66                 ar9003_paprd.o
  67
  68 +ath9k_hw-$(CPTCFG_ATH9K_WOW) += ar9003_wow.o
  69 +
  70  ath9k_hw-$(CPTCFG_ATH9K_BTCOEX_SUPPORT) += btcoex.o \
  71                                            ar9003_mci.o
  72  obj-$(CPTCFG_ATH9K_HW) += ath9k_hw.o
  73 --- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c
  74 +++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
  75 @@ -17,6 +17,7 @@
  76  #include "hw.h"
  77  #include "ar9003_mac.h"
  78  #include "ar9003_2p2_initvals.h"
  79 +#include "ar9003_buffalo_initvals.h"
  80  #include "ar9485_initvals.h"
  81  #include "ar9340_initvals.h"
  82  #include "ar9330_1p1_initvals.h"
  83 @@ -26,6 +27,7 @@
  84  #include "ar9462_2p0_initvals.h"
  85  #include "ar9462_2p1_initvals.h"
  86  #include "ar9565_1p0_initvals.h"
  87 +#include "ar9565_1p1_initvals.h"
  88
  89  /* General hardware code for the AR9003 hadware family */
  90
  91 @@ -148,7 +150,11 @@ static void ar9003_hw_init_mode_regs(str
  92                                 ar9340Modes_high_ob_db_tx_gain_table_1p0);
  93
  94                 INIT_INI_ARRAY(&ah->iniModesFastClock,
  95 -                               ar9340Modes_fast_clock_1p0);
  96 +                              ar9340Modes_fast_clock_1p0);
  97 +               INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
  98 +                              ar9340_1p0_baseband_core_txfir_coeff_japan_2484);
  99 +               INIT_INI_ARRAY(&ah->ini_dfs,
 100 +                              ar9340_1p0_baseband_postamble_dfs_channel);
 101
 102                 if (!ah->is_clk_25mhz)
 103                         INIT_INI_ARRAY(&ah->iniAdditional,
 104 @@ -187,17 +193,17 @@ static void ar9003_hw_init_mode_regs(str
 105                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 106                                ar9485_1_1_baseband_core_txfir_coeff_japan_2484);
 107
 108 -               /* Load PCIE SERDES settings from INI */
 109 -
 110 -               /* Awake Setting */
 111 -
 112 -               INIT_INI_ARRAY(&ah->iniPcieSerdes,
 113 -                               ar9485_1_1_pcie_phy_clkreq_disable_L1);
 114 -
 115 -               /* Sleep Setting */
 116 -
 117 -               INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 118 -                               ar9485_1_1_pcie_phy_clkreq_disable_L1);
 119 +               if (ah->config.no_pll_pwrsave) {
 120 +                       INIT_INI_ARRAY(&ah->iniPcieSerdes,
 121 +                                      ar9485_1_1_pcie_phy_clkreq_disable_L1);
 122 +                       INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 123 +                                      ar9485_1_1_pcie_phy_clkreq_disable_L1);
 124 +               } else {
 125 +                       INIT_INI_ARRAY(&ah->iniPcieSerdes,
 126 +                                      ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1);
 127 +                       INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 128 +                                      ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1);
 129 +               }
 130         } else if (AR_SREV_9462_21(ah)) {
 131                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 132                                ar9462_2p1_mac_core);
 133 @@ -223,6 +229,10 @@ static void ar9003_hw_init_mode_regs(str
 134                                ar9462_2p1_modes_fast_clock);
 135                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 136                                ar9462_2p1_baseband_core_txfir_coeff_japan_2484);
 137 +               INIT_INI_ARRAY(&ah->iniPcieSerdes,
 138 +                              ar9462_2p1_pciephy_clkreq_disable_L1);
 139 +               INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 140 +                              ar9462_2p1_pciephy_clkreq_disable_L1);
 141         } else if (AR_SREV_9462_20(ah)) {
 142
 143                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core);
 144 @@ -247,18 +257,18 @@ static void ar9003_hw_init_mode_regs(str
 145                                 ar9462_2p0_soc_postamble);
 146
 147                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 148 -                               ar9462_common_rx_gain_table_2p0);
 149 +                               ar9462_2p0_common_rx_gain);
 150
 151                 /* Awake -> Sleep Setting */
 152                 INIT_INI_ARRAY(&ah->iniPcieSerdes,
 153 -                              ar9462_pciephy_clkreq_disable_L1_2p0);
 154 +                              ar9462_2p0_pciephy_clkreq_disable_L1);
 155                 /* Sleep -> Awake Setting */
 156                 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 157 -                              ar9462_pciephy_clkreq_disable_L1_2p0);
 158 +                              ar9462_2p0_pciephy_clkreq_disable_L1);
 159
 160                 /* Fast clock modal settings */
 161                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 162 -                               ar9462_modes_fast_clock_2p0);
 163 +                               ar9462_2p0_modes_fast_clock);
 164
 165                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 166                                ar9462_2p0_baseband_core_txfir_coeff_japan_2484);
 167 @@ -330,7 +340,46 @@ static void ar9003_hw_init_mode_regs(str
 168                                 ar9580_1p0_low_ob_db_tx_gain_table);
 169
 170                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 171 -                               ar9580_1p0_modes_fast_clock);
 172 +                              ar9580_1p0_modes_fast_clock);
 173 +               INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 174 +                              ar9580_1p0_baseband_core_txfir_coeff_japan_2484);
 175 +               INIT_INI_ARRAY(&ah->ini_dfs,
 176 +                              ar9580_1p0_baseband_postamble_dfs_channel);
 177 +       } else if (AR_SREV_9565_11_OR_LATER(ah)) {
 178 +               INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 179 +                              ar9565_1p1_mac_core);
 180 +               INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 181 +                              ar9565_1p1_mac_postamble);
 182 +
 183 +               INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 184 +                              ar9565_1p1_baseband_core);
 185 +               INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 186 +                              ar9565_1p1_baseband_postamble);
 187 +
 188 +               INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 189 +                              ar9565_1p1_radio_core);
 190 +               INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 191 +                              ar9565_1p1_radio_postamble);
 192 +
 193 +               INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 194 +                              ar9565_1p1_soc_preamble);
 195 +               INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 196 +                              ar9565_1p1_soc_postamble);
 197 +
 198 +               INIT_INI_ARRAY(&ah->iniModesRxGain,
 199 +                              ar9565_1p1_Common_rx_gain_table);
 200 +               INIT_INI_ARRAY(&ah->iniModesTxGain,
 201 +                              ar9565_1p1_Modes_lowest_ob_db_tx_gain_table);
 202 +
 203 +               INIT_INI_ARRAY(&ah->iniPcieSerdes,
 204 +                              ar9565_1p1_pciephy_clkreq_disable_L1);
 205 +               INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 206 +                              ar9565_1p1_pciephy_clkreq_disable_L1);
 207 +
 208 +               INIT_INI_ARRAY(&ah->iniModesFastClock,
 209 +                               ar9565_1p1_modes_fast_clock);
 210 +               INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 211 +                              ar9565_1p1_baseband_core_txfir_coeff_japan_2484);
 212         } else if (AR_SREV_9565(ah)) {
 213                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 214                                ar9565_1p0_mac_core);
 215 @@ -411,7 +460,11 @@ static void ar9003_hw_init_mode_regs(str
 216
 217                 /* Fast clock modal settings */
 218                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 219 -                               ar9300Modes_fast_clock_2p2);
 220 +                              ar9300Modes_fast_clock_2p2);
 221 +               INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 222 +                              ar9300_2p2_baseband_core_txfir_coeff_japan_2484);
 223 +               INIT_INI_ARRAY(&ah->ini_dfs,
 224 +                              ar9300_2p2_baseband_postamble_dfs_channel);
 225         }
 226  }
 227
 228 @@ -440,7 +493,10 @@ static void ar9003_tx_gain_table_mode0(s
 229                         ar9462_2p1_modes_low_ob_db_tx_gain);
 230         else if (AR_SREV_9462_20(ah))
 231                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 232 -                       ar9462_modes_low_ob_db_tx_gain_table_2p0);
 233 +                       ar9462_2p0_modes_low_ob_db_tx_gain);
 234 +       else if (AR_SREV_9565_11(ah))
 235 +               INIT_INI_ARRAY(&ah->iniModesTxGain,
 236 +                              ar9565_1p1_modes_low_ob_db_tx_gain_table);
 237         else if (AR_SREV_9565(ah))
 238                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 239                                ar9565_1p0_modes_low_ob_db_tx_gain_table);
 240 @@ -474,7 +530,10 @@ static void ar9003_tx_gain_table_mode1(s
 241                         ar9462_2p1_modes_high_ob_db_tx_gain);
 242         else if (AR_SREV_9462_20(ah))
 243                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 244 -                       ar9462_modes_high_ob_db_tx_gain_table_2p0);
 245 +                       ar9462_2p0_modes_high_ob_db_tx_gain);
 246 +       else if (AR_SREV_9565_11(ah))
 247 +               INIT_INI_ARRAY(&ah->iniModesTxGain,
 248 +                              ar9565_1p1_modes_high_ob_db_tx_gain_table);
 249         else if (AR_SREV_9565(ah))
 250                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 251                                ar9565_1p0_modes_high_ob_db_tx_gain_table);
 252 @@ -500,6 +559,9 @@ static void ar9003_tx_gain_table_mode2(s
 253         else if (AR_SREV_9580(ah))
 254                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 255                         ar9580_1p0_low_ob_db_tx_gain_table);
 256 +       else if (AR_SREV_9565_11(ah))
 257 +               INIT_INI_ARRAY(&ah->iniModesTxGain,
 258 +                              ar9565_1p1_modes_low_ob_db_tx_gain_table);
 259         else if (AR_SREV_9565(ah))
 260                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 261                                ar9565_1p0_modes_low_ob_db_tx_gain_table);
 262 @@ -525,12 +587,20 @@ static void ar9003_tx_gain_table_mode3(s
 263         else if (AR_SREV_9580(ah))
 264                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 265                         ar9580_1p0_high_power_tx_gain_table);
 266 +       else if (AR_SREV_9565_11(ah))
 267 +               INIT_INI_ARRAY(&ah->iniModesTxGain,
 268 +                              ar9565_1p1_modes_high_power_tx_gain_table);
 269         else if (AR_SREV_9565(ah))
 270                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 271                                ar9565_1p0_modes_high_power_tx_gain_table);
 272 -       else
 273 -               INIT_INI_ARRAY(&ah->iniModesTxGain,
 274 -                       ar9300Modes_high_power_tx_gain_table_2p2);
 275 +       else {
 276 +               if (ah->config.tx_gain_buffalo)
 277 +                       INIT_INI_ARRAY(&ah->iniModesTxGain,
 278 +                                      ar9300Modes_high_power_tx_gain_table_buffalo);
 279 +               else
 280 +                       INIT_INI_ARRAY(&ah->iniModesTxGain,
 281 +                                      ar9300Modes_high_power_tx_gain_table_2p2);
 282 +       }
 283  }
 284
 285  static void ar9003_tx_gain_table_mode4(struct ath_hw *ah)
 286 @@ -546,7 +616,7 @@ static void ar9003_tx_gain_table_mode4(s
 287                        ar9462_2p1_modes_mix_ob_db_tx_gain);
 288         else if (AR_SREV_9462_20(ah))
 289                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 290 -                      ar9462_modes_mix_ob_db_tx_gain_table_2p0);
 291 +                      ar9462_2p0_modes_mix_ob_db_tx_gain);
 292         else
 293                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 294                         ar9300Modes_mixed_ob_db_tx_gain_table_2p2);
 295 @@ -581,6 +651,13 @@ static void ar9003_tx_gain_table_mode6(s
 296                         ar9580_1p0_type6_tx_gain_table);
 297  }
 298
 299 +static void ar9003_tx_gain_table_mode7(struct ath_hw *ah)
 300 +{
 301 +       if (AR_SREV_9340(ah))
 302 +               INIT_INI_ARRAY(&ah->iniModesTxGain,
 303 +                              ar9340_cus227_tx_gain_table_1p0);
 304 +}
 305 +
 306  typedef void (*ath_txgain_tab)(struct ath_hw *ah);
 307
 308  static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
 309 @@ -593,6 +670,7 @@ static void ar9003_tx_gain_table_apply(s
 310                 ar9003_tx_gain_table_mode4,
 311                 ar9003_tx_gain_table_mode5,
 312                 ar9003_tx_gain_table_mode6,
 313 +               ar9003_tx_gain_table_mode7,
 314         };
 315         int idx = ar9003_hw_get_tx_gain_idx(ah);
 316
 317 @@ -629,7 +707,10 @@ static void ar9003_rx_gain_table_mode0(s
 318                                 ar9462_2p1_common_rx_gain);
 319         else if (AR_SREV_9462_20(ah))
 320                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 321 -                               ar9462_common_rx_gain_table_2p0);
 322 +                               ar9462_2p0_common_rx_gain);
 323 +       else if (AR_SREV_9565_11(ah))
 324 +               INIT_INI_ARRAY(&ah->iniModesRxGain,
 325 +                              ar9565_1p1_Common_rx_gain_table);
 326         else if (AR_SREV_9565(ah))
 327                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 328                                ar9565_1p0_Common_rx_gain_table);
 329 @@ -657,7 +738,7 @@ static void ar9003_rx_gain_table_mode1(s
 330                         ar9462_2p1_common_wo_xlna_rx_gain);
 331         else if (AR_SREV_9462_20(ah))
 332                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 333 -                       ar9462_common_wo_xlna_rx_gain_table_2p0);
 334 +                       ar9462_2p0_common_wo_xlna_rx_gain);
 335         else if (AR_SREV_9550(ah)) {
 336                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 337                         ar955x_1p0_common_wo_xlna_rx_gain_table);
 338 @@ -666,6 +747,9 @@ static void ar9003_rx_gain_table_mode1(s
 339         } else if (AR_SREV_9580(ah))
 340                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 341                         ar9580_1p0_wo_xlna_rx_gain_table);
 342 +       else if (AR_SREV_9565_11(ah))
 343 +               INIT_INI_ARRAY(&ah->iniModesRxGain,
 344 +                              ar9565_1p1_common_wo_xlna_rx_gain_table);
 345         else if (AR_SREV_9565(ah))
 346                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 347                                ar9565_1p0_common_wo_xlna_rx_gain_table);
 348 @@ -687,7 +771,7 @@ static void ar9003_rx_gain_table_mode2(s
 349                                ar9462_2p1_baseband_postamble_5g_xlna);
 350         } else if (AR_SREV_9462_20(ah)) {
 351                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 352 -                              ar9462_common_mixed_rx_gain_table_2p0);
 353 +                              ar9462_2p0_common_mixed_rx_gain);
 354                 INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_core,
 355                                ar9462_2p0_baseband_core_mix_rxgain);
 356                 INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
 357 @@ -701,12 +785,12 @@ static void ar9003_rx_gain_table_mode3(s
 358  {
 359         if (AR_SREV_9462_21(ah)) {
 360                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 361 -                              ar9462_2p1_common_5g_xlna_only_rx_gain);
 362 +                              ar9462_2p1_common_5g_xlna_only_rxgain);
 363                 INIT_INI_ARRAY(&ah->ini_modes_rxgain_5g_xlna,
 364                                ar9462_2p1_baseband_postamble_5g_xlna);
 365         } else if (AR_SREV_9462_20(ah)) {
 366                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 367 -                              ar9462_2p0_5g_xlna_only_rxgain);
 368 +                              ar9462_2p0_common_5g_xlna_only_rxgain);
 369                 INIT_INI_ARRAY(&ah->ini_modes_rxgain_5g_xlna,
 370                                ar9462_2p0_baseband_postamble_5g_xlna);
 371         }
 372 @@ -750,6 +834,9 @@ static void ar9003_hw_init_mode_gain_reg
 373  static void ar9003_hw_configpcipowersave(struct ath_hw *ah,
 374                                          bool power_off)
 375  {
 376 +       unsigned int i;
 377 +       struct ar5416IniArray *array;
 378 +
 379         /*
 380          * Increase L1 Entry Latency. Some WB222 boards don't have
 381          * this change in eeprom/OTP.
 382 @@ -775,18 +862,13 @@ static void ar9003_hw_configpcipowersave
 383          * Configire PCIE after Ini init. SERDES values now come from ini file
 384          * This enables PCIe low power mode.
 385          */
 386 -       if (ah->config.pcieSerDesWrite) {
 387 -               unsigned int i;
 388 -               struct ar5416IniArray *array;
 389 -
 390 -               array = power_off ? &ah->iniPcieSerdes :
 391 -                                   &ah->iniPcieSerdesLowPower;
 392 -
 393 -               for (i = 0; i < array->ia_rows; i++) {
 394 -                       REG_WRITE(ah,
 395 -                                 INI_RA(array, i, 0),
 396 -                                 INI_RA(array, i, 1));
 397 -               }
 398 +       array = power_off ? &ah->iniPcieSerdes :
 399 +               &ah->iniPcieSerdesLowPower;
 400 +
 401 +       for (i = 0; i < array->ia_rows; i++) {
 402 +               REG_WRITE(ah,
 403 +                         INI_RA(array, i, 0),
 404 +                         INI_RA(array, i, 1));
 405         }
 406  }
 407
 408 --- a/drivers/net/wireless/ath/ath9k/ar9340_initvals.h
 409 +++ b/drivers/net/wireless/ath/ath9k/ar9340_initvals.h
 410 @@ -18,6 +18,20 @@
 411  #ifndef INITVALS_9340_H
 412  #define INITVALS_9340_H
 413
 414 +#define ar9340_1p0_mac_postamble ar9300_2p2_mac_postamble
 415 +
 416 +#define ar9340_1p0_soc_postamble ar9300_2p2_soc_postamble
 417 +
 418 +#define ar9340Modes_fast_clock_1p0 ar9300Modes_fast_clock_2p2
 419 +
 420 +#define ar9340Common_rx_gain_table_1p0 ar9300Common_rx_gain_table_2p2
 421 +
 422 +#define ar9340Common_wo_xlna_rx_gain_table_1p0 ar9300Common_wo_xlna_rx_gain_table_2p2
 423 +
 424 +#define ar9340_1p0_baseband_core_txfir_coeff_japan_2484 ar9300_2p2_baseband_core_txfir_coeff_japan_2484
 425 +
 426 +#define ar9340_1p0_baseband_postamble_dfs_channel ar9300_2p2_baseband_postamble_dfs_channel
 427 +
 428  static const u32 ar9340_1p0_radio_postamble[][5] = {
 429         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
 430         {0x000160ac, 0xa4646800, 0xa4646800, 0xa4646800, 0xa4646800},
 431 @@ -100,8 +114,6 @@ static const u32 ar9340Modes_lowest_ob_d
 432         {0x00016448, 0x24925266, 0x24925266, 0x24925266, 0x24925266},
 433  };
 434
 435 -#define ar9340Modes_fast_clock_1p0 ar9300Modes_fast_clock_2p2
 436 -
 437  static const u32 ar9340_1p0_radio_core[][2] = {
 438         /* Addr      allmodes  */
 439         {0x00016000, 0x36db6db6},
 440 @@ -215,16 +227,12 @@ static const u32 ar9340_1p0_radio_core_4
 441         {0x0000824c, 0x0001e800},
 442  };
 443
 444 -#define ar9340_1p0_mac_postamble ar9300_2p2_mac_postamble
 445 -
 446 -#define ar9340_1p0_soc_postamble ar9300_2p2_soc_postamble
 447 -
 448  static const u32 ar9340_1p0_baseband_postamble[][5] = {
 449         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
 450         {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a8011},
 451         {0x00009820, 0x206a022e, 0x206a022e, 0x206a022e, 0x206a022e},
 452         {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0},
 453 -       {0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881},
 454 +       {0x00009828, 0x06903081, 0x06903081, 0x09103881, 0x09103881},
 455         {0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4},
 456         {0x00009830, 0x0000059c, 0x0000059c, 0x0000119c, 0x0000119c},
 457         {0x00009c00, 0x000000c4, 0x000000c4, 0x000000c4, 0x000000c4},
 458 @@ -340,9 +348,9 @@ static const u32 ar9340_1p0_baseband_cor
 459         {0x0000a370, 0x00000000},
 460         {0x0000a390, 0x00000001},
 461         {0x0000a394, 0x00000444},
 462 -       {0x0000a398, 0x001f0e0f},
 463 -       {0x0000a39c, 0x0075393f},
 464 -       {0x0000a3a0, 0xb79f6427},
 465 +       {0x0000a398, 0x00000000},
 466 +       {0x0000a39c, 0x210d0401},
 467 +       {0x0000a3a0, 0xab9a7144},
 468         {0x0000a3a4, 0x00000000},
 469         {0x0000a3a8, 0xaaaaaaaa},
 470         {0x0000a3ac, 0x3c466478},
 471 @@ -714,266 +722,6 @@ static const u32 ar9340Modes_ub124_tx_ga
 472         {0x0000b2e8, 0xfffe0000, 0xfffe0000, 0xfffc0000, 0xfffc0000},
 473  };
 474
 475 -static const u32 ar9340Common_rx_gain_table_1p0[][2] = {
 476 -       /* Addr      allmodes  */
 477 -       {0x0000a000, 0x00010000},
 478 -       {0x0000a004, 0x00030002},
 479 -       {0x0000a008, 0x00050004},
 480 -       {0x0000a00c, 0x00810080},
 481 -       {0x0000a010, 0x00830082},
 482 -       {0x0000a014, 0x01810180},
 483 -       {0x0000a018, 0x01830182},
 484 -       {0x0000a01c, 0x01850184},
 485 -       {0x0000a020, 0x01890188},
 486 -       {0x0000a024, 0x018b018a},
 487 -       {0x0000a028, 0x018d018c},
 488 -       {0x0000a02c, 0x01910190},
 489 -       {0x0000a030, 0x01930192},
 490 -       {0x0000a034, 0x01950194},
 491 -       {0x0000a038, 0x038a0196},
 492 -       {0x0000a03c, 0x038c038b},
 493 -       {0x0000a040, 0x0390038d},
 494 -       {0x0000a044, 0x03920391},
 495 -       {0x0000a048, 0x03940393},
 496 -       {0x0000a04c, 0x03960395},
 497 -       {0x0000a050, 0x00000000},
 498 -       {0x0000a054, 0x00000000},
 499 -       {0x0000a058, 0x00000000},
 500 -       {0x0000a05c, 0x00000000},
 501 -       {0x0000a060, 0x00000000},
 502 -       {0x0000a064, 0x00000000},
 503 -       {0x0000a068, 0x00000000},
 504 -       {0x0000a06c, 0x00000000},
 505 -       {0x0000a070, 0x00000000},
 506 -       {0x0000a074, 0x00000000},
 507 -       {0x0000a078, 0x00000000},
 508 -       {0x0000a07c, 0x00000000},
 509 -       {0x0000a080, 0x22222229},
 510 -       {0x0000a084, 0x1d1d1d1d},
 511 -       {0x0000a088, 0x1d1d1d1d},
 512 -       {0x0000a08c, 0x1d1d1d1d},
 513 -       {0x0000a090, 0x171d1d1d},
 514 -       {0x0000a094, 0x11111717},
 515 -       {0x0000a098, 0x00030311},
 516 -       {0x0000a09c, 0x00000000},
 517 -       {0x0000a0a0, 0x00000000},
 518 -       {0x0000a0a4, 0x00000000},
 519 -       {0x0000a0a8, 0x00000000},
 520 -       {0x0000a0ac, 0x00000000},
 521 -       {0x0000a0b0, 0x00000000},
 522 -       {0x0000a0b4, 0x00000000},
 523 -       {0x0000a0b8, 0x00000000},
 524 -       {0x0000a0bc, 0x00000000},
 525 -       {0x0000a0c0, 0x001f0000},
 526 -       {0x0000a0c4, 0x01000101},
 527 -       {0x0000a0c8, 0x011e011f},
 528 -       {0x0000a0cc, 0x011c011d},
 529 -       {0x0000a0d0, 0x02030204},
 530 -       {0x0000a0d4, 0x02010202},
 531 -       {0x0000a0d8, 0x021f0200},
 532 -       {0x0000a0dc, 0x0302021e},
 533 -       {0x0000a0e0, 0x03000301},
 534 -       {0x0000a0e4, 0x031e031f},
 535 -       {0x0000a0e8, 0x0402031d},
 536 -       {0x0000a0ec, 0x04000401},
 537 -       {0x0000a0f0, 0x041e041f},
 538 -       {0x0000a0f4, 0x0502041d},
 539 -       {0x0000a0f8, 0x05000501},
 540 -       {0x0000a0fc, 0x051e051f},
 541 -       {0x0000a100, 0x06010602},
 542 -       {0x0000a104, 0x061f0600},
 543 -       {0x0000a108, 0x061d061e},
 544 -       {0x0000a10c, 0x07020703},
 545 -       {0x0000a110, 0x07000701},
 546 -       {0x0000a114, 0x00000000},
 547 -       {0x0000a118, 0x00000000},
 548 -       {0x0000a11c, 0x00000000},
 549 -       {0x0000a120, 0x00000000},
 550 -       {0x0000a124, 0x00000000},
 551 -       {0x0000a128, 0x00000000},
 552 -       {0x0000a12c, 0x00000000},
 553 -       {0x0000a130, 0x00000000},
 554 -       {0x0000a134, 0x00000000},
 555 -       {0x0000a138, 0x00000000},
 556 -       {0x0000a13c, 0x00000000},
 557 -       {0x0000a140, 0x001f0000},
 558 -       {0x0000a144, 0x01000101},
 559 -       {0x0000a148, 0x011e011f},
 560 -       {0x0000a14c, 0x011c011d},
 561 -       {0x0000a150, 0x02030204},
 562 -       {0x0000a154, 0x02010202},
 563 -       {0x0000a158, 0x021f0200},
 564 -       {0x0000a15c, 0x0302021e},
 565 -       {0x0000a160, 0x03000301},
 566 -       {0x0000a164, 0x031e031f},
 567 -       {0x0000a168, 0x0402031d},
 568 -       {0x0000a16c, 0x04000401},
 569 -       {0x0000a170, 0x041e041f},
 570 -       {0x0000a174, 0x0502041d},
 571 -       {0x0000a178, 0x05000501},
 572 -       {0x0000a17c, 0x051e051f},
 573 -       {0x0000a180, 0x06010602},
 574 -       {0x0000a184, 0x061f0600},
 575 -       {0x0000a188, 0x061d061e},
 576 -       {0x0000a18c, 0x07020703},
 577 -       {0x0000a190, 0x07000701},
 578 -       {0x0000a194, 0x00000000},
 579 -       {0x0000a198, 0x00000000},
 580 -       {0x0000a19c, 0x00000000},
 581 -       {0x0000a1a0, 0x00000000},
 582 -       {0x0000a1a4, 0x00000000},
 583 -       {0x0000a1a8, 0x00000000},
 584 -       {0x0000a1ac, 0x00000000},
 585 -       {0x0000a1b0, 0x00000000},
 586 -       {0x0000a1b4, 0x00000000},
 587 -       {0x0000a1b8, 0x00000000},
 588 -       {0x0000a1bc, 0x00000000},
 589 -       {0x0000a1c0, 0x00000000},
 590 -       {0x0000a1c4, 0x00000000},
 591 -       {0x0000a1c8, 0x00000000},
 592 -       {0x0000a1cc, 0x00000000},
 593 -       {0x0000a1d0, 0x00000000},
 594 -       {0x0000a1d4, 0x00000000},
 595 -       {0x0000a1d8, 0x00000000},
 596 -       {0x0000a1dc, 0x00000000},
 597 -       {0x0000a1e0, 0x00000000},
 598 -       {0x0000a1e4, 0x00000000},
 599 -       {0x0000a1e8, 0x00000000},
 600 -       {0x0000a1ec, 0x00000000},
 601 -       {0x0000a1f0, 0x00000396},
 602 -       {0x0000a1f4, 0x00000396},
 603 -       {0x0000a1f8, 0x00000396},
 604 -       {0x0000a1fc, 0x00000196},
 605 -       {0x0000b000, 0x00010000},
 606 -       {0x0000b004, 0x00030002},
 607 -       {0x0000b008, 0x00050004},
 608 -       {0x0000b00c, 0x00810080},
 609 -       {0x0000b010, 0x00830082},
 610 -       {0x0000b014, 0x01810180},
 611 -       {0x0000b018, 0x01830182},
 612 -       {0x0000b01c, 0x01850184},
 613 -       {0x0000b020, 0x02810280},
 614 -       {0x0000b024, 0x02830282},
 615 -       {0x0000b028, 0x02850284},
 616 -       {0x0000b02c, 0x02890288},
 617 -       {0x0000b030, 0x028b028a},
 618 -       {0x0000b034, 0x0388028c},
 619 -       {0x0000b038, 0x038a0389},
 620 -       {0x0000b03c, 0x038c038b},
 621 -       {0x0000b040, 0x0390038d},
 622 -       {0x0000b044, 0x03920391},
 623 -       {0x0000b048, 0x03940393},
 624 -       {0x0000b04c, 0x03960395},
 625 -       {0x0000b050, 0x00000000},
 626 -       {0x0000b054, 0x00000000},
 627 -       {0x0000b058, 0x00000000},
 628 -       {0x0000b05c, 0x00000000},
 629 -       {0x0000b060, 0x00000000},
 630 -       {0x0000b064, 0x00000000},
 631 -       {0x0000b068, 0x00000000},
 632 -       {0x0000b06c, 0x00000000},
 633 -       {0x0000b070, 0x00000000},
 634 -       {0x0000b074, 0x00000000},
 635 -       {0x0000b078, 0x00000000},
 636 -       {0x0000b07c, 0x00000000},
 637 -       {0x0000b080, 0x23232323},
 638 -       {0x0000b084, 0x21232323},
 639 -       {0x0000b088, 0x19191c1e},
 640 -       {0x0000b08c, 0x12141417},
 641 -       {0x0000b090, 0x07070e0e},
 642 -       {0x0000b094, 0x03030305},
 643 -       {0x0000b098, 0x00000003},
 644 -       {0x0000b09c, 0x00000000},
 645 -       {0x0000b0a0, 0x00000000},
 646 -       {0x0000b0a4, 0x00000000},
 647 -       {0x0000b0a8, 0x00000000},
 648 -       {0x0000b0ac, 0x00000000},
 649 -       {0x0000b0b0, 0x00000000},
 650 -       {0x0000b0b4, 0x00000000},
 651 -       {0x0000b0b8, 0x00000000},
 652 -       {0x0000b0bc, 0x00000000},
 653 -       {0x0000b0c0, 0x003f0020},
 654 -       {0x0000b0c4, 0x00400041},
 655 -       {0x0000b0c8, 0x0140005f},
 656 -       {0x0000b0cc, 0x0160015f},
 657 -       {0x0000b0d0, 0x017e017f},
 658 -       {0x0000b0d4, 0x02410242},
 659 -       {0x0000b0d8, 0x025f0240},
 660 -       {0x0000b0dc, 0x027f0260},
 661 -       {0x0000b0e0, 0x0341027e},
 662 -       {0x0000b0e4, 0x035f0340},
 663 -       {0x0000b0e8, 0x037f0360},
 664 -       {0x0000b0ec, 0x04400441},
 665 -       {0x0000b0f0, 0x0460045f},
 666 -       {0x0000b0f4, 0x0541047f},
 667 -       {0x0000b0f8, 0x055f0540},
 668 -       {0x0000b0fc, 0x057f0560},
 669 -       {0x0000b100, 0x06400641},
 670 -       {0x0000b104, 0x0660065f},
 671 -       {0x0000b108, 0x067e067f},
 672 -       {0x0000b10c, 0x07410742},
 673 -       {0x0000b110, 0x075f0740},
 674 -       {0x0000b114, 0x077f0760},
 675 -       {0x0000b118, 0x07800781},
 676 -       {0x0000b11c, 0x07a0079f},
 677 -       {0x0000b120, 0x07c107bf},
 678 -       {0x0000b124, 0x000007c0},
 679 -       {0x0000b128, 0x00000000},
 680 -       {0x0000b12c, 0x00000000},
 681 -       {0x0000b130, 0x00000000},
 682 -       {0x0000b134, 0x00000000},
 683 -       {0x0000b138, 0x00000000},
 684 -       {0x0000b13c, 0x00000000},
 685 -       {0x0000b140, 0x003f0020},
 686 -       {0x0000b144, 0x00400041},
 687 -       {0x0000b148, 0x0140005f},
 688 -       {0x0000b14c, 0x0160015f},
 689 -       {0x0000b150, 0x017e017f},
 690 -       {0x0000b154, 0x02410242},
 691 -       {0x0000b158, 0x025f0240},
 692 -       {0x0000b15c, 0x027f0260},
 693 -       {0x0000b160, 0x0341027e},
 694 -       {0x0000b164, 0x035f0340},
 695 -       {0x0000b168, 0x037f0360},
 696 -       {0x0000b16c, 0x04400441},
 697 -       {0x0000b170, 0x0460045f},
 698 -       {0x0000b174, 0x0541047f},
 699 -       {0x0000b178, 0x055f0540},
 700 -       {0x0000b17c, 0x057f0560},
 701 -       {0x0000b180, 0x06400641},
 702 -       {0x0000b184, 0x0660065f},
 703 -       {0x0000b188, 0x067e067f},
 704 -       {0x0000b18c, 0x07410742},
 705 -       {0x0000b190, 0x075f0740},
 706 -       {0x0000b194, 0x077f0760},
 707 -       {0x0000b198, 0x07800781},
 708 -       {0x0000b19c, 0x07a0079f},
 709 -       {0x0000b1a0, 0x07c107bf},
 710 -       {0x0000b1a4, 0x000007c0},
 711 -       {0x0000b1a8, 0x00000000},
 712 -       {0x0000b1ac, 0x00000000},
 713 -       {0x0000b1b0, 0x00000000},
 714 -       {0x0000b1b4, 0x00000000},
 715 -       {0x0000b1b8, 0x00000000},
 716 -       {0x0000b1bc, 0x00000000},
 717 -       {0x0000b1c0, 0x00000000},
 718 -       {0x0000b1c4, 0x00000000},
 719 -       {0x0000b1c8, 0x00000000},
 720 -       {0x0000b1cc, 0x00000000},
 721 -       {0x0000b1d0, 0x00000000},
 722 -       {0x0000b1d4, 0x00000000},
 723 -       {0x0000b1d8, 0x00000000},
 724 -       {0x0000b1dc, 0x00000000},
 725 -       {0x0000b1e0, 0x00000000},
 726 -       {0x0000b1e4, 0x00000000},
 727 -       {0x0000b1e8, 0x00000000},
 728 -       {0x0000b1ec, 0x00000000},
 729 -       {0x0000b1f0, 0x00000396},
 730 -       {0x0000b1f4, 0x00000396},
 731 -       {0x0000b1f8, 0x00000396},
 732 -       {0x0000b1fc, 0x00000196},
 733 -};
 734 -
 735  static const u32 ar9340Modes_low_ob_db_tx_gain_table_1p0[][5] = {
 736         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
 737         {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
 738 @@ -1437,8 +1185,6 @@ static const u32 ar9340_1p0_mac_core[][2
 739         {0x000083d0, 0x000101ff},
 740  };
 741
 742 -#define ar9340Common_wo_xlna_rx_gain_table_1p0 ar9300Common_wo_xlna_rx_gain_table_2p2
 743 -
 744  static const u32 ar9340_1p0_soc_preamble[][2] = {
 745         /* Addr      allmodes  */
 746         {0x00007008, 0x00000000},
 747 @@ -1447,4 +1193,106 @@ static const u32 ar9340_1p0_soc_preamble
 748         {0x00007038, 0x000004c2},
 749  };
 750
 751 +static const u32 ar9340_cus227_tx_gain_table_1p0[][5] = {
 752 +       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
 753 +       {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
 754 +       {0x0000a2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
 755 +       {0x0000a2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
 756 +       {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
 757 +       {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
 758 +       {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
 759 +       {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
 760 +       {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004},
 761 +       {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
 762 +       {0x0000a510, 0x16000220, 0x16000220, 0x0f000202, 0x0f000202},
 763 +       {0x0000a514, 0x1c000223, 0x1c000223, 0x11000400, 0x11000400},
 764 +       {0x0000a518, 0x21002220, 0x21002220, 0x15000402, 0x15000402},
 765 +       {0x0000a51c, 0x27002223, 0x27002223, 0x19000404, 0x19000404},
 766 +       {0x0000a520, 0x2c022220, 0x2c022220, 0x1b000603, 0x1b000603},
 767 +       {0x0000a524, 0x30022222, 0x30022222, 0x1f000a02, 0x1f000a02},
 768 +       {0x0000a528, 0x35022225, 0x35022225, 0x23000a04, 0x23000a04},
 769 +       {0x0000a52c, 0x3b02222a, 0x3b02222a, 0x26000a20, 0x26000a20},
 770 +       {0x0000a530, 0x3f02222c, 0x3f02222c, 0x2a000e20, 0x2a000e20},
 771 +       {0x0000a534, 0x4202242a, 0x4202242a, 0x2e000e22, 0x2e000e22},
 772 +       {0x0000a538, 0x4702244a, 0x4702244a, 0x31000e24, 0x31000e24},
 773 +       {0x0000a53c, 0x4b02244c, 0x4b02244c, 0x34001640, 0x34001640},
 774 +       {0x0000a540, 0x4e02246c, 0x4e02246c, 0x38001660, 0x38001660},
 775 +       {0x0000a544, 0x5302266c, 0x5302266c, 0x3b001861, 0x3b001861},
 776 +       {0x0000a548, 0x5702286c, 0x5702286c, 0x3e001a81, 0x3e001a81},
 777 +       {0x0000a54c, 0x5c02486b, 0x5c02486b, 0x42001a83, 0x42001a83},
 778 +       {0x0000a550, 0x61024a6c, 0x61024a6c, 0x44001c84, 0x44001c84},
 779 +       {0x0000a554, 0x66026a6c, 0x66026a6c, 0x48001ce3, 0x48001ce3},
 780 +       {0x0000a558, 0x6b026e6c, 0x6b026e6c, 0x4c001ce5, 0x4c001ce5},
 781 +       {0x0000a55c, 0x7002708c, 0x7002708c, 0x50001ce9, 0x50001ce9},
 782 +       {0x0000a560, 0x7302b08a, 0x7302b08a, 0x54001ceb, 0x54001ceb},
 783 +       {0x0000a564, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
 784 +       {0x0000a568, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
 785 +       {0x0000a56c, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
 786 +       {0x0000a570, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
 787 +       {0x0000a574, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
 788 +       {0x0000a578, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
 789 +       {0x0000a57c, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
 790 +       {0x0000a580, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
 791 +       {0x0000a584, 0x06800003, 0x06800003, 0x04800002, 0x04800002},
 792 +       {0x0000a588, 0x0a800020, 0x0a800020, 0x08800004, 0x08800004},
 793 +       {0x0000a58c, 0x10800023, 0x10800023, 0x0b800200, 0x0b800200},
 794 +       {0x0000a590, 0x16800220, 0x16800220, 0x0f800202, 0x0f800202},
 795 +       {0x0000a594, 0x1c800223, 0x1c800223, 0x11800400, 0x11800400},
 796 +       {0x0000a598, 0x21820220, 0x21820220, 0x15800402, 0x15800402},
 797 +       {0x0000a59c, 0x27820223, 0x27820223, 0x19800404, 0x19800404},
 798 +       {0x0000a5a0, 0x2b822220, 0x2b822220, 0x1b800603, 0x1b800603},
 799 +       {0x0000a5a4, 0x2f822222, 0x2f822222, 0x1f800a02, 0x1f800a02},
 800 +       {0x0000a5a8, 0x34822225, 0x34822225, 0x23800a04, 0x23800a04},
 801 +       {0x0000a5ac, 0x3a82222a, 0x3a82222a, 0x26800a20, 0x26800a20},
 802 +       {0x0000a5b0, 0x3e82222c, 0x3e82222c, 0x2a800e20, 0x2a800e20},
 803 +       {0x0000a5b4, 0x4282242a, 0x4282242a, 0x2e800e22, 0x2e800e22},
 804 +       {0x0000a5b8, 0x4782244a, 0x4782244a, 0x31800e24, 0x31800e24},
 805 +       {0x0000a5bc, 0x4b82244c, 0x4b82244c, 0x34801640, 0x34801640},
 806 +       {0x0000a5c0, 0x4e82246c, 0x4e82246c, 0x38801660, 0x38801660},
 807 +       {0x0000a5c4, 0x5382266c, 0x5382266c, 0x3b801861, 0x3b801861},
 808 +       {0x0000a5c8, 0x5782286c, 0x5782286c, 0x3e801a81, 0x3e801a81},
 809 +       {0x0000a5cc, 0x5c84286b, 0x5c84286b, 0x42801a83, 0x42801a83},
 810 +       {0x0000a5d0, 0x61842a6c, 0x61842a6c, 0x44801c84, 0x44801c84},
 811 +       {0x0000a5d4, 0x66862a6c, 0x66862a6c, 0x48801ce3, 0x48801ce3},
 812 +       {0x0000a5d8, 0x6b862e6c, 0x6b862e6c, 0x4c801ce5, 0x4c801ce5},
 813 +       {0x0000a5dc, 0x7086308c, 0x7086308c, 0x50801ce9, 0x50801ce9},
 814 +       {0x0000a5e0, 0x738a308a, 0x738a308a, 0x54801ceb, 0x54801ceb},
 815 +       {0x0000a5e4, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
 816 +       {0x0000a5e8, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
 817 +       {0x0000a5ec, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
 818 +       {0x0000a5f0, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
 819 +       {0x0000a5f4, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
 820 +       {0x0000a5f8, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
 821 +       {0x0000a5fc, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
 822 +       {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
 823 +       {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
 824 +       {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
 825 +       {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
 826 +       {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
 827 +       {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000},
 828 +       {0x0000a618, 0x01404501, 0x01404501, 0x01404501, 0x01404501},
 829 +       {0x0000a61c, 0x02008802, 0x02008802, 0x02008501, 0x02008501},
 830 +       {0x0000a620, 0x0300cc03, 0x0300cc03, 0x0280ca03, 0x0280ca03},
 831 +       {0x0000a624, 0x0300cc03, 0x0300cc03, 0x03010c04, 0x03010c04},
 832 +       {0x0000a628, 0x0300cc03, 0x0300cc03, 0x04014c04, 0x04014c04},
 833 +       {0x0000a62c, 0x03810c03, 0x03810c03, 0x04015005, 0x04015005},
 834 +       {0x0000a630, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
 835 +       {0x0000a634, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
 836 +       {0x0000a638, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
 837 +       {0x0000a63c, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
 838 +       {0x0000b2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
 839 +       {0x0000b2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
 840 +       {0x0000b2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
 841 +       {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
 842 +       {0x00016044, 0x056db2db, 0x056db2db, 0x03b6d2e4, 0x03b6d2e4},
 843 +       {0x00016048, 0x24925666, 0x24925666, 0x8e481266, 0x8e481266},
 844 +       {0x00016280, 0x01000015, 0x01000015, 0x01001015, 0x01001015},
 845 +       {0x00016288, 0x30318000, 0x30318000, 0x00318000, 0x00318000},
 846 +       {0x00016444, 0x056db2db, 0x056db2db, 0x03b6d2e4, 0x03b6d2e4},
 847 +       {0x00016448, 0x24925666, 0x24925666, 0x8e481266, 0x8e481266},
 848 +       {0x0000a3a4, 0x00000011, 0x00000011, 0x00000011, 0x00000011},
 849 +       {0x0000a3a8, 0x3c3c3c3c, 0x3c3c3c3c, 0x3c3c3c3c, 0x3c3c3c3c},
 850 +       {0x0000a3ac, 0x30303030, 0x30303030, 0x30303030, 0x30303030},
 851 +};
 852 +
 853  #endif /* INITVALS_9340_H */
 854 --- a/drivers/net/wireless/ath/ath9k/ath9k.h
 855 +++ b/drivers/net/wireless/ath/ath9k/ath9k.h
 856 @@ -27,40 +27,15 @@
 857  #include "common.h"
 858  #include "mci.h"
 859  #include "dfs.h"
 860 -
 861 -/*
 862 - * Header for the ath9k.ko driver core *only* -- hw code nor any other driver
 863 - * should rely on this file or its contents.
 864 - */
 865 +#include "spectral.h"
 866
 867  struct ath_node;
 868 +struct ath_rate_table;
 869
 870 -/* Macro to expand scalars to 64-bit objects */
 871 -
 872 -#define        ito64(x) (sizeof(x) == 1) ?                     \
 873 -       (((unsigned long long int)(x)) & (0xff)) :      \
 874 -       (sizeof(x) == 2) ?                              \
 875 -       (((unsigned long long int)(x)) & 0xffff) :      \
 876 -       ((sizeof(x) == 4) ?                             \
 877 -        (((unsigned long long int)(x)) & 0xffffffff) : \
 878 -        (unsigned long long int)(x))
 879 -
 880 -/* increment with wrap-around */
 881 -#define INCR(_l, _sz)   do {                   \
 882 -               (_l)++;                         \
 883 -               (_l) &= ((_sz) - 1);            \
 884 -       } while (0)
 885 -
 886 -/* decrement with wrap-around */
 887 -#define DECR(_l,  _sz)  do {                   \
 888 -               (_l)--;                         \
 889 -               (_l) &= ((_sz) - 1);            \
 890 -       } while (0)
 891 -
 892 -#define TSF_TO_TU(_h,_l) \
 893 -       ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
 894 -
 895 -#define        ATH_TXQ_SETUP(sc, i)        ((sc)->tx.txqsetup & (1<<i))
 896 +extern struct ieee80211_ops ath9k_ops;
 897 +extern int ath9k_modparam_nohwcrypt;
 898 +extern int led_blink;
 899 +extern bool is_ath9k_unloaded;
 900
 901  struct ath_config {
 902         u16 txpowlimit;
 903 @@ -70,6 +45,17 @@ struct ath_config {
 904  /* Descriptor Management */
 905  /*************************/
 906
 907 +#define ATH_TXSTATUS_RING_SIZE 512
 908 +
 909 +/* Macro to expand scalars to 64-bit objects */
 910 +#define        ito64(x) (sizeof(x) == 1) ?                     \
 911 +       (((unsigned long long int)(x)) & (0xff)) :      \
 912 +       (sizeof(x) == 2) ?                              \
 913 +       (((unsigned long long int)(x)) & 0xffff) :      \
 914 +       ((sizeof(x) == 4) ?                             \
 915 +        (((unsigned long long int)(x)) & 0xffffffff) : \
 916 +        (unsigned long long int)(x))
 917 +
 918  #define ATH_TXBUF_RESET(_bf) do {                              \
 919                 (_bf)->bf_lastbf = NULL;                        \
 920                 (_bf)->bf_next = NULL;                          \
 921 @@ -77,23 +63,6 @@ struct ath_config {
 922                        sizeof(struct ath_buf_state));           \
 923         } while (0)
 924
 925 -/**
 926 - * enum buffer_type - Buffer type flags
 927 - *
 928 - * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX)
 929 - * @BUF_AGGR: Indicates whether the buffer can be aggregated
 930 - *     (used in aggregation scheduling)
 931 - */
 932 -enum buffer_type {
 933 -       BUF_AMPDU               = BIT(0),
 934 -       BUF_AGGR                = BIT(1),
 935 -};
 936 -
 937 -#define bf_isampdu(bf)         (bf->bf_state.bf_type & BUF_AMPDU)
 938 -#define bf_isaggr(bf)          (bf->bf_state.bf_type & BUF_AGGR)
 939 -
 940 -#define ATH_TXSTATUS_RING_SIZE 512
 941 -
 942  #define        DS2PHYS(_dd, _ds)                                               \
 943         ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
 944  #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
 945 @@ -113,11 +82,20 @@ int ath_descdma_setup(struct ath_softc *
 946  /* RX / TX */
 947  /***********/
 948
 949 +#define        ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i))
 950 +
 951 +/* increment with wrap-around */
 952 +#define INCR(_l, _sz)   do {                   \
 953 +               (_l)++;                         \
 954 +               (_l) &= ((_sz) - 1);            \
 955 +       } while (0)
 956 +
 957  #define ATH_RXBUF               512
 958  #define ATH_TXBUF               512
 959  #define ATH_TXBUF_RESERVE       5
 960  #define ATH_MAX_QDEPTH          (ATH_TXBUF / 4 - ATH_TXBUF_RESERVE)
 961  #define ATH_TXMAXTRY            13
 962 +#define ATH_MAX_SW_RETRIES      30
 963
 964  #define TID_TO_WME_AC(_tid)                            \
 965         ((((_tid) == 0) || ((_tid) == 3)) ? IEEE80211_AC_BE :   \
 966 @@ -133,6 +111,9 @@ int ath_descdma_setup(struct ath_softc *
 967  #define ATH_AGGR_MIN_QDEPTH        2
 968  /* minimum h/w qdepth for non-aggregated traffic */
 969  #define ATH_NON_AGGR_MIN_QDEPTH    8
 970 +#define ATH_TX_COMPLETE_POLL_INT   1000
 971 +#define ATH_TXFIFO_DEPTH           8
 972 +#define ATH_TX_ERROR               0x01
 973
 974  #define IEEE80211_SEQ_SEQ_SHIFT    4
 975  #define IEEE80211_SEQ_MAX          4096
 976 @@ -167,9 +148,6 @@ int ath_descdma_setup(struct ath_softc *
 977
 978  #define IS_CCK_RATE(rate) ((rate >= 0x18) && (rate <= 0x1e))
 979
 980 -#define ATH_TX_COMPLETE_POLL_INT       1000
 981 -
 982 -#define ATH_TXFIFO_DEPTH 8
 983  struct ath_txq {
 984         int mac80211_qnum; /* mac80211 queue number, -1 means not mac80211 Q */
 985         u32 axq_qnum; /* ath9k hardware queue number */
 986 @@ -214,6 +192,21 @@ struct ath_rxbuf {
 987         dma_addr_t bf_buf_addr;
 988  };
 989
 990 +/**
 991 + * enum buffer_type - Buffer type flags
 992 + *
 993 + * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX)
 994 + * @BUF_AGGR: Indicates whether the buffer can be aggregated
 995 + *     (used in aggregation scheduling)
 996 + */
 997 +enum buffer_type {
 998 +       BUF_AMPDU               = BIT(0),
 999 +       BUF_AGGR                = BIT(1),
1000 +};
1001 +
1002 +#define bf_isampdu(bf)         (bf->bf_state.bf_type & BUF_AMPDU)
1003 +#define bf_isaggr(bf)          (bf->bf_state.bf_type & BUF_AGGR)
1004 +
1005  struct ath_buf_state {
1006         u8 bf_type;
1007         u8 bfs_paprd;
1008 @@ -278,7 +271,6 @@ struct ath_tx_control {
1009         struct ieee80211_sta *sta;
1010  };
1011
1012 -#define ATH_TX_ERROR        0x01
1013
1014  /**
1015   * @txq_map:  Index is mac80211 queue number.  This is
1016 @@ -372,6 +364,22 @@ struct ath_vif {
1017         struct ath_buf *av_bcbuf;
1018  };
1019
1020 +struct ath9k_vif_iter_data {
1021 +       u8 hw_macaddr[ETH_ALEN]; /* address of the first vif */
1022 +       u8 mask[ETH_ALEN]; /* bssid mask */
1023 +       bool has_hw_macaddr;
1024 +
1025 +       int naps;      /* number of AP vifs */
1026 +       int nmeshes;   /* number of mesh vifs */
1027 +       int nstations; /* number of station vifs */
1028 +       int nwds;      /* number of WDS vifs */
1029 +       int nadhocs;   /* number of adhoc vifs */
1030 +};
1031 +
1032 +void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
1033 +                              struct ieee80211_vif *vif,
1034 +                              struct ath9k_vif_iter_data *iter_data);
1035 +
1036  /*******************/
1037  /* Beacon Handling */
1038  /*******************/
1039 @@ -387,6 +395,9 @@ struct ath_vif {
1040  #define ATH_DEFAULT_BMISS_LIMIT        10
1041  #define IEEE80211_MS_TO_TU(x)           (((x) * 1000) / 1024)
1042
1043 +#define TSF_TO_TU(_h,_l) \
1044 +       ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
1045 +
1046  struct ath_beacon_config {
1047         int beacon_interval;
1048         u16 listen_interval;
1049 @@ -420,12 +431,10 @@ struct ath_beacon {
1050  };
1051
1052  void ath9k_beacon_tasklet(unsigned long data);
1053 -bool ath9k_allow_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif);
1054  void ath9k_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif,
1055                          u32 changed);
1056  void ath9k_beacon_assign_slot(struct ath_softc *sc, struct ieee80211_vif *vif);
1057  void ath9k_beacon_remove_slot(struct ath_softc *sc, struct ieee80211_vif *vif);
1058 -void ath9k_set_tsfadjust(struct ath_softc *sc, struct ieee80211_vif *vif);
1059  void ath9k_set_beacon(struct ath_softc *sc);
1060  bool ath9k_csa_is_finished(struct ath_softc *sc);
1061
1062 @@ -440,10 +449,9 @@ bool ath9k_csa_is_finished(struct ath_so
1063  #define ATH_LONG_CALINTERVAL_INT  1000    /* 1000 ms */
1064  #define ATH_LONG_CALINTERVAL      30000   /* 30 seconds */
1065  #define ATH_RESTART_CALINTERVAL   1200000 /* 20 minutes */
1066 -#define ATH_ANI_MAX_SKIP_COUNT  10
1067 -
1068 -#define ATH_PAPRD_TIMEOUT      100 /* msecs */
1069 -#define ATH_PLL_WORK_INTERVAL   100
1070 +#define ATH_ANI_MAX_SKIP_COUNT    10
1071 +#define ATH_PAPRD_TIMEOUT         100 /* msecs */
1072 +#define ATH_PLL_WORK_INTERVAL     100
1073
1074  void ath_tx_complete_poll_work(struct work_struct *work);
1075  void ath_reset_work(struct work_struct *work);
1076 @@ -459,6 +467,7 @@ void ath_check_ani(struct ath_softc *sc)
1077  int ath_update_survey_stats(struct ath_softc *sc);
1078  void ath_update_survey_nf(struct ath_softc *sc, int channel);
1079  void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type);
1080 +void ath_ps_full_sleep(unsigned long data);
1081
1082  /**********/
1083  /* BTCOEX */
1084 @@ -476,20 +485,19 @@ enum bt_op_flags {
1085  };
1086
1087  struct ath_btcoex {
1088 -       bool hw_timer_enabled;
1089         spinlock_t btcoex_lock;
1090         struct timer_list period_timer; /* Timer for BT period */
1091 +       struct timer_list no_stomp_timer;
1092         u32 bt_priority_cnt;
1093         unsigned long bt_priority_time;
1094         unsigned long op_flags;
1095         int bt_stomp_type; /* Types of BT stomping */
1096 -       u32 btcoex_no_stomp; /* in usec */
1097 +       u32 btcoex_no_stomp; /* in msec */
1098         u32 btcoex_period; /* in msec */
1099 -       u32 btscan_no_stomp; /* in usec */
1100 +       u32 btscan_no_stomp; /* in msec */
1101         u32 duty_cycle;
1102         u32 bt_wait_time;
1103         int rssi_count;
1104 -       struct ath_gen_timer *no_stomp_timer; /* Timer for no BT stomping */
1105         struct ath_mci_profile mci;
1106         u8 stomp_audio;
1107  };
1108 @@ -537,12 +545,6 @@ static inline int ath9k_dump_btcoex(stru
1109  }
1110  #endif /* CPTCFG_ATH9K_BTCOEX_SUPPORT */
1111
1112 -struct ath9k_wow_pattern {
1113 -       u8 pattern_bytes[MAX_PATTERN_SIZE];
1114 -       u8 mask_bytes[MAX_PATTERN_SIZE];
1115 -       u32 pattern_len;
1116 -};
1117 -
1118  /********************/
1119  /*   LED Control    */
1120  /********************/
1121 @@ -570,6 +572,40 @@ static inline void ath_fill_led_pin(stru
1122  }
1123  #endif
1124
1125 +/************************/
1126 +/* Wake on Wireless LAN */
1127 +/************************/
1128 +
1129 +struct ath9k_wow_pattern {
1130 +       u8 pattern_bytes[MAX_PATTERN_SIZE];
1131 +       u8 mask_bytes[MAX_PATTERN_SIZE];
1132 +       u32 pattern_len;
1133 +};
1134 +
1135 +#ifdef CPTCFG_ATH9K_WOW
1136 +void ath9k_init_wow(struct ieee80211_hw *hw);
1137 +int ath9k_suspend(struct ieee80211_hw *hw,
1138 +                 struct cfg80211_wowlan *wowlan);
1139 +int ath9k_resume(struct ieee80211_hw *hw);
1140 +void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled);
1141 +#else
1142 +static inline void ath9k_init_wow(struct ieee80211_hw *hw)
1143 +{
1144 +}
1145 +static inline int ath9k_suspend(struct ieee80211_hw *hw,
1146 +                               struct cfg80211_wowlan *wowlan)
1147 +{
1148 +       return 0;
1149 +}
1150 +static inline int ath9k_resume(struct ieee80211_hw *hw)
1151 +{
1152 +       return 0;
1153 +}
1154 +static inline void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled)
1155 +{
1156 +}
1157 +#endif /* CONFIG_ATH9K_WOW */
1158 +
1159  /*******************************/
1160  /* Antenna diversity/combining */
1161  /*******************************/
1162 @@ -632,28 +668,24 @@ void ath_ant_comb_scan(struct ath_softc
1163  /* Main driver core */
1164  /********************/
1165
1166 -#define ATH9K_PCI_CUS198      0x0001
1167 -#define ATH9K_PCI_CUS230      0x0002
1168 -#define ATH9K_PCI_CUS217      0x0004
1169 -#define ATH9K_PCI_CUS252      0x0008
1170 -#define ATH9K_PCI_WOW         0x0010
1171 -#define ATH9K_PCI_BT_ANT_DIV  0x0020
1172 -#define ATH9K_PCI_D3_L1_WAR   0x0040
1173 -#define ATH9K_PCI_AR9565_1ANT 0x0080
1174 -#define ATH9K_PCI_AR9565_2ANT 0x0100
1175 +#define ATH9K_PCI_CUS198          0x0001
1176 +#define ATH9K_PCI_CUS230          0x0002
1177 +#define ATH9K_PCI_CUS217          0x0004
1178 +#define ATH9K_PCI_CUS252          0x0008
1179 +#define ATH9K_PCI_WOW             0x0010
1180 +#define ATH9K_PCI_BT_ANT_DIV      0x0020
1181 +#define ATH9K_PCI_D3_L1_WAR       0x0040
1182 +#define ATH9K_PCI_AR9565_1ANT     0x0080
1183 +#define ATH9K_PCI_AR9565_2ANT     0x0100
1184 +#define ATH9K_PCI_NO_PLL_PWRSAVE  0x0200
1185
1186  /*
1187   * Default cache line size, in bytes.
1188   * Used when PCI device not fully initialized by bootrom/BIOS
1189  */
1190  #define DEFAULT_CACHELINE       32
1191 -#define ATH_REGCLASSIDS_MAX     10
1192  #define ATH_CABQ_READY_TIME     80      /* % of beacon interval */
1193 -#define ATH_MAX_SW_RETRIES      30
1194 -#define ATH_CHAN_MAX            255
1195 -
1196  #define ATH_TXPOWER_MAX         100     /* .5 dBm units */
1197 -#define ATH_RATE_DUMMY_MARKER   0
1198
1199  enum sc_op_flags {
1200         SC_OP_INVALID,
1201 @@ -672,37 +704,6 @@ enum sc_op_flags {
1202  #define PS_BEACON_SYNC            BIT(4)
1203  #define PS_WAIT_FOR_ANI           BIT(5)
1204
1205 -struct ath_rate_table;
1206 -
1207 -struct ath9k_vif_iter_data {
1208 -       u8 hw_macaddr[ETH_ALEN]; /* address of the first vif */
1209 -       u8 mask[ETH_ALEN]; /* bssid mask */
1210 -       bool has_hw_macaddr;
1211 -
1212 -       int naps;      /* number of AP vifs */
1213 -       int nmeshes;   /* number of mesh vifs */
1214 -       int nstations; /* number of station vifs */
1215 -       int nwds;      /* number of WDS vifs */
1216 -       int nadhocs;   /* number of adhoc vifs */
1217 -};
1218 -
1219 -/* enum spectral_mode:
1220 - *
1221 - * @SPECTRAL_DISABLED: spectral mode is disabled
1222 - * @SPECTRAL_BACKGROUND: hardware sends samples when it is not busy with
1223 - *     something else.
1224 - * @SPECTRAL_MANUAL: spectral scan is enabled, triggering for samples
1225 - *     is performed manually.
1226 - * @SPECTRAL_CHANSCAN: Like manual, but also triggered when changing channels
1227 - *     during a channel scan.
1228 - */
1229 -enum spectral_mode {
1230 -       SPECTRAL_DISABLED = 0,
1231 -       SPECTRAL_BACKGROUND,
1232 -       SPECTRAL_MANUAL,
1233 -       SPECTRAL_CHANSCAN,
1234 -};
1235 -
1236  struct ath_softc {
1237         struct ieee80211_hw *hw;
1238         struct device *dev;
1239 @@ -723,6 +724,7 @@ struct ath_softc {
1240         struct work_struct hw_check_work;
1241         struct work_struct hw_reset_work;
1242         struct completion paprd_complete;
1243 +       wait_queue_head_t tx_wait;
1244
1245         unsigned int hw_busy_count;
1246         unsigned long sc_flags;
1247 @@ -759,6 +761,7 @@ struct ath_softc {
1248         struct delayed_work tx_complete_work;
1249         struct delayed_work hw_pll_work;
1250         struct timer_list rx_poll_timer;
1251 +       struct timer_list sleep_timer;
1252
1253  #ifdef CPTCFG_ATH9K_BTCOEX_SUPPORT
1254         struct ath_btcoex btcoex;
1255 @@ -783,199 +786,54 @@ struct ath_softc {
1256         bool tx99_state;
1257         s16 tx99_power;
1258
1259 -#ifdef CONFIG_PM_SLEEP
1260 +#ifdef CONFIG_ATH9K_WOW
1261         atomic_t wow_got_bmiss_intr;
1262         atomic_t wow_sleep_proc_intr; /* in the middle of WoW sleep ? */
1263         u32 wow_intr_before_sleep;
1264  #endif
1265  };
1266
1267 -#define SPECTRAL_SCAN_BITMASK          0x10
1268 -/* Radar info packet format, used for DFS and spectral formats. */
1269 -struct ath_radar_info {
1270 -       u8 pulse_length_pri;
1271 -       u8 pulse_length_ext;
1272 -       u8 pulse_bw_info;
1273 -} __packed;
1274 -
1275 -/* The HT20 spectral data has 4 bytes of additional information at it's end.
1276 - *
1277 - * [7:0]: all bins {max_magnitude[1:0], bitmap_weight[5:0]}
1278 - * [7:0]: all bins  max_magnitude[9:2]
1279 - * [7:0]: all bins {max_index[5:0], max_magnitude[11:10]}
1280 - * [3:0]: max_exp (shift amount to size max bin to 8-bit unsigned)
1281 - */
1282 -struct ath_ht20_mag_info {
1283 -       u8 all_bins[3];
1284 -       u8 max_exp;
1285 -} __packed;
1286 -
1287 -#define SPECTRAL_HT20_NUM_BINS         56
1288 -
1289 -/* WARNING: don't actually use this struct! MAC may vary the amount of
1290 - * data by -1/+2. This struct is for reference only.
1291 - */
1292 -struct ath_ht20_fft_packet {
1293 -       u8 data[SPECTRAL_HT20_NUM_BINS];
1294 -       struct ath_ht20_mag_info mag_info;
1295 -       struct ath_radar_info radar_info;
1296 -} __packed;
1297 -
1298 -#define SPECTRAL_HT20_TOTAL_DATA_LEN   (sizeof(struct ath_ht20_fft_packet))
1299 -
1300 -/* Dynamic 20/40 mode:
1301 - *
1302 - * [7:0]: lower bins {max_magnitude[1:0], bitmap_weight[5:0]}
1303 - * [7:0]: lower bins  max_magnitude[9:2]
1304 - * [7:0]: lower bins {max_index[5:0], max_magnitude[11:10]}
1305 - * [7:0]: upper bins {max_magnitude[1:0], bitmap_weight[5:0]}
1306 - * [7:0]: upper bins  max_magnitude[9:2]
1307 - * [7:0]: upper bins {max_index[5:0], max_magnitude[11:10]}
1308 - * [3:0]: max_exp (shift amount to size max bin to 8-bit unsigned)
1309 - */
1310 -struct ath_ht20_40_mag_info {
1311 -       u8 lower_bins[3];
1312 -       u8 upper_bins[3];
1313 -       u8 max_exp;
1314 -} __packed;
1315 -
1316 -#define SPECTRAL_HT20_40_NUM_BINS              128
1317 -
1318 -/* WARNING: don't actually use this struct! MAC may vary the amount of
1319 - * data. This struct is for reference only.
1320 - */
1321 -struct ath_ht20_40_fft_packet {
1322 -       u8 data[SPECTRAL_HT20_40_NUM_BINS];
1323 -       struct ath_ht20_40_mag_info mag_info;
1324 -       struct ath_radar_info radar_info;
1325 -} __packed;
1326 -
1327 -
1328 -#define SPECTRAL_HT20_40_TOTAL_DATA_LEN        (sizeof(struct ath_ht20_40_fft_packet))
1329 -
1330 -/* grabs the max magnitude from the all/upper/lower bins */
1331 -static inline u16 spectral_max_magnitude(u8 *bins)
1332 -{
1333 -       return (bins[0] & 0xc0) >> 6 |
1334 -              (bins[1] & 0xff) << 2 |
1335 -              (bins[2] & 0x03) << 10;
1336 -}
1337 +/********/
1338 +/* TX99 */
1339 +/********/
1340
1341 -/* return the max magnitude from the all/upper/lower bins */
1342 -static inline u8 spectral_max_index(u8 *bins)
1343 +#ifdef CONFIG_ATH9K_TX99
1344 +void ath9k_tx99_init_debug(struct ath_softc *sc);
1345 +int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb,
1346 +                   struct ath_tx_control *txctl);
1347 +#else
1348 +static inline void ath9k_tx99_init_debug(struct ath_softc *sc)
1349  {
1350 -       s8 m = (bins[2] & 0xfc) >> 2;
1351 -
1352 -       /* TODO: this still doesn't always report the right values ... */
1353 -       if (m > 32)
1354 -               m |= 0xe0;
1355 -       else
1356 -               m &= ~0xe0;
1357 -
1358 -       return m + 29;
1359  }
1360 -
1361 -/* return the bitmap weight from the all/upper/lower bins */
1362 -static inline u8 spectral_bitmap_weight(u8 *bins)
1363 +static inline int ath9k_tx99_send(struct ath_softc *sc,
1364 +                                 struct sk_buff *skb,
1365 +                                 struct ath_tx_control *txctl)
1366  {
1367 -       return bins[0] & 0x3f;
1368 +       return 0;
1369  }
1370 -
1371 -/* FFT sample format given to userspace via debugfs.
1372 - *
1373 - * Please keep the type/length at the front position and change
1374 - * other fields after adding another sample type
1375 - *
1376 - * TODO: this might need rework when switching to nl80211-based
1377 - * interface.
1378 - */
1379 -enum ath_fft_sample_type {
1380 -       ATH_FFT_SAMPLE_HT20 = 1,
1381 -       ATH_FFT_SAMPLE_HT20_40,
1382 -};
1383 -
1384 -struct fft_sample_tlv {
1385 -       u8 type;        /* see ath_fft_sample */
1386 -       __be16 length;
1387 -       /* type dependent data follows */
1388 -} __packed;
1389 -
1390 -struct fft_sample_ht20 {
1391 -       struct fft_sample_tlv tlv;
1392 -
1393 -       u8 max_exp;
1394 -
1395 -       __be16 freq;
1396 -       s8 rssi;
1397 -       s8 noise;
1398 -
1399 -       __be16 max_magnitude;
1400 -       u8 max_index;
1401 -       u8 bitmap_weight;
1402 -
1403 -       __be64 tsf;
1404 -
1405 -       u8 data[SPECTRAL_HT20_NUM_BINS];
1406 -} __packed;
1407 -
1408 -struct fft_sample_ht20_40 {
1409 -       struct fft_sample_tlv tlv;
1410 -
1411 -       u8 channel_type;
1412 -       __be16 freq;
1413 -
1414 -       s8 lower_rssi;
1415 -       s8 upper_rssi;
1416 -
1417 -       __be64 tsf;
1418 -
1419 -       s8 lower_noise;
1420 -       s8 upper_noise;
1421 -
1422 -       __be16 lower_max_magnitude;
1423 -       __be16 upper_max_magnitude;
1424 -
1425 -       u8 lower_max_index;
1426 -       u8 upper_max_index;
1427 -
1428 -       u8 lower_bitmap_weight;
1429 -       u8 upper_bitmap_weight;
1430 -
1431 -       u8 max_exp;
1432 -
1433 -       u8 data[SPECTRAL_HT20_40_NUM_BINS];
1434 -} __packed;
1435 -
1436 -int ath9k_tx99_init(struct ath_softc *sc);
1437 -void ath9k_tx99_deinit(struct ath_softc *sc);
1438 -int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb,
1439 -                   struct ath_tx_control *txctl);
1440 -
1441 -void ath9k_tasklet(unsigned long data);
1442 -int ath_cabq_update(struct ath_softc *);
1443 +#endif /* CONFIG_ATH9K_TX99 */
1444
1445  static inline void ath_read_cachesize(struct ath_common *common, int *csz)
1446  {
1447         common->bus_ops->read_cachesize(common, csz);
1448  }
1449
1450 -extern struct ieee80211_ops ath9k_ops;
1451 -extern int ath9k_modparam_nohwcrypt;
1452 -extern int led_blink;
1453 -extern bool is_ath9k_unloaded;
1454 -
1455 +void ath9k_tasklet(unsigned long data);
1456 +int ath_cabq_update(struct ath_softc *);
1457  u8 ath9k_parse_mpdudensity(u8 mpdudensity);
1458  irqreturn_t ath_isr(int irq, void *dev);
1459 +int ath_reset(struct ath_softc *sc);
1460 +void ath_cancel_work(struct ath_softc *sc);
1461 +void ath_restart_work(struct ath_softc *sc);
1462  int ath9k_init_device(u16 devid, struct ath_softc *sc,
1463                     const struct ath_bus_ops *bus_ops);
1464  void ath9k_deinit_device(struct ath_softc *sc);
1465 -void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw);
1466  void ath9k_reload_chainmask_settings(struct ath_softc *sc);
1467 -
1468 -void ath9k_spectral_scan_trigger(struct ieee80211_hw *hw);
1469 -int ath9k_spectral_scan_config(struct ieee80211_hw *hw,
1470 -                              enum spectral_mode spectral_mode);
1471 -
1472 +u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate);
1473 +void ath_start_rfkill_poll(struct ath_softc *sc);
1474 +void ath9k_rfkill_poll_state(struct ieee80211_hw *hw);
1475 +void ath9k_ps_wakeup(struct ath_softc *sc);
1476 +void ath9k_ps_restore(struct ath_softc *sc);
1477
1478  #ifdef CPTCFG_ATH9K_PCI
1479  int ath_pci_init(void);
1480 @@ -993,15 +851,4 @@ static inline int ath_ahb_init(void) { r
1481  static inline void ath_ahb_exit(void) {};
1482  #endif
1483
1484 -void ath9k_ps_wakeup(struct ath_softc *sc);
1485 -void ath9k_ps_restore(struct ath_softc *sc);
1486 -
1487 -u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate);
1488 -
1489 -void ath_start_rfkill_poll(struct ath_softc *sc);
1490 -extern void ath9k_rfkill_poll_state(struct ieee80211_hw *hw);
1491 -void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
1492 -                              struct ieee80211_vif *vif,
1493 -                              struct ath9k_vif_iter_data *iter_data);
1494 -
1495  #endif /* ATH9K_H */
1496 --- a/drivers/net/wireless/ath/ath9k/debug.c
1497 +++ b/drivers/net/wireless/ath/ath9k/debug.c
1498 @@ -17,7 +17,6 @@
1499  #include <linux/slab.h>
1500  #include <linux/vmalloc.h>
1501  #include <linux/export.h>
1502 -#include <linux/relay.h>
1503  #include <asm/unaligned.h>
1504
1505  #include "ath9k.h"
1506 @@ -27,6 +26,47 @@
1507  #define REG_READ_D(_ah, _reg) \
1508         ath9k_hw_common(_ah)->ops->read((_ah), (_reg))
1509
1510 +void ath9k_debug_sync_cause(struct ath_softc *sc, u32 sync_cause)
1511 +{
1512 +       if (sync_cause)
1513 +               sc->debug.stats.istats.sync_cause_all++;
1514 +       if (sync_cause & AR_INTR_SYNC_RTC_IRQ)
1515 +               sc->debug.stats.istats.sync_rtc_irq++;
1516 +       if (sync_cause & AR_INTR_SYNC_MAC_IRQ)
1517 +               sc->debug.stats.istats.sync_mac_irq++;
1518 +       if (sync_cause & AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS)
1519 +               sc->debug.stats.istats.eeprom_illegal_access++;
1520 +       if (sync_cause & AR_INTR_SYNC_APB_TIMEOUT)
1521 +               sc->debug.stats.istats.apb_timeout++;
1522 +       if (sync_cause & AR_INTR_SYNC_PCI_MODE_CONFLICT)
1523 +               sc->debug.stats.istats.pci_mode_conflict++;
1524 +       if (sync_cause & AR_INTR_SYNC_HOST1_FATAL)
1525 +               sc->debug.stats.istats.host1_fatal++;
1526 +       if (sync_cause & AR_INTR_SYNC_HOST1_PERR)
1527 +               sc->debug.stats.istats.host1_perr++;
1528 +       if (sync_cause & AR_INTR_SYNC_TRCV_FIFO_PERR)
1529 +               sc->debug.stats.istats.trcv_fifo_perr++;
1530 +       if (sync_cause & AR_INTR_SYNC_RADM_CPL_EP)
1531 +               sc->debug.stats.istats.radm_cpl_ep++;
1532 +       if (sync_cause & AR_INTR_SYNC_RADM_CPL_DLLP_ABORT)
1533 +               sc->debug.stats.istats.radm_cpl_dllp_abort++;
1534 +       if (sync_cause & AR_INTR_SYNC_RADM_CPL_TLP_ABORT)
1535 +               sc->debug.stats.istats.radm_cpl_tlp_abort++;
1536 +       if (sync_cause & AR_INTR_SYNC_RADM_CPL_ECRC_ERR)
1537 +               sc->debug.stats.istats.radm_cpl_ecrc_err++;
1538 +       if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT)
1539 +               sc->debug.stats.istats.radm_cpl_timeout++;
1540 +       if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT)
1541 +               sc->debug.stats.istats.local_timeout++;
1542 +       if (sync_cause & AR_INTR_SYNC_PM_ACCESS)
1543 +               sc->debug.stats.istats.pm_access++;
1544 +       if (sync_cause & AR_INTR_SYNC_MAC_AWAKE)
1545 +               sc->debug.stats.istats.mac_awake++;
1546 +       if (sync_cause & AR_INTR_SYNC_MAC_ASLEEP)
1547 +               sc->debug.stats.istats.mac_asleep++;
1548 +       if (sync_cause & AR_INTR_SYNC_MAC_SLEEP_ACCESS)
1549 +               sc->debug.stats.istats.mac_sleep_access++;
1550 +}
1551
1552  static ssize_t ath9k_debugfs_read_buf(struct file *file, char __user *user_buf,
1553                                       size_t count, loff_t *ppos)
1554 @@ -1016,297 +1056,6 @@ static const struct file_operations fops
1555         .llseek = default_llseek,
1556  };
1557
1558 -static ssize_t read_file_spec_scan_ctl(struct file *file, char __user *user_buf,
1559 -                                      size_t count, loff_t *ppos)
1560 -{
1561 -       struct ath_softc *sc = file->private_data;
1562 -       char *mode = "";
1563 -       unsigned int len;
1564 -
1565 -       switch (sc->spectral_mode) {
1566 -       case SPECTRAL_DISABLED:
1567 -               mode = "disable";
1568 -               break;
1569 -       case SPECTRAL_BACKGROUND:
1570 -               mode = "background";
1571 -               break;
1572 -       case SPECTRAL_CHANSCAN:
1573 -               mode = "chanscan";
1574 -               break;
1575 -       case SPECTRAL_MANUAL:
1576 -               mode = "manual";
1577 -               break;
1578 -       }
1579 -       len = strlen(mode);
1580 -       return simple_read_from_buffer(user_buf, count, ppos, mode, len);
1581 -}
1582 -
1583 -static ssize_t write_file_spec_scan_ctl(struct file *file,
1584 -                                       const char __user *user_buf,
1585 -                                       size_t count, loff_t *ppos)
1586 -{
1587 -       struct ath_softc *sc = file->private_data;
1588 -       struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1589 -       char buf[32];
1590 -       ssize_t len;
1591 -
1592 -       if (config_enabled(CPTCFG_ATH9K_TX99))
1593 -               return -EOPNOTSUPP;
1594 -
1595 -       len = min(count, sizeof(buf) - 1);
1596 -       if (copy_from_user(buf, user_buf, len))
1597 -               return -EFAULT;
1598 -
1599 -       buf[len] = '\0';
1600 -
1601 -       if (strncmp("trigger", buf, 7) == 0) {
1602 -               ath9k_spectral_scan_trigger(sc->hw);
1603 -       } else if (strncmp("background", buf, 9) == 0) {
1604 -               ath9k_spectral_scan_config(sc->hw, SPECTRAL_BACKGROUND);
1605 -               ath_dbg(common, CONFIG, "spectral scan: background mode enabled\n");
1606 -       } else if (strncmp("chanscan", buf, 8) == 0) {
1607 -               ath9k_spectral_scan_config(sc->hw, SPECTRAL_CHANSCAN);
1608 -               ath_dbg(common, CONFIG, "spectral scan: channel scan mode enabled\n");
1609 -       } else if (strncmp("manual", buf, 6) == 0) {
1610 -               ath9k_spectral_scan_config(sc->hw, SPECTRAL_MANUAL);
1611 -               ath_dbg(common, CONFIG, "spectral scan: manual mode enabled\n");
1612 -       } else if (strncmp("disable", buf, 7) == 0) {
1613 -               ath9k_spectral_scan_config(sc->hw, SPECTRAL_DISABLED);
1614 -               ath_dbg(common, CONFIG, "spectral scan: disabled\n");
1615 -       } else {
1616 -               return -EINVAL;
1617 -       }
1618 -
1619 -       return count;
1620 -}
1621 -
1622 -static const struct file_operations fops_spec_scan_ctl = {
1623 -       .read = read_file_spec_scan_ctl,
1624 -       .write = write_file_spec_scan_ctl,
1625 -       .open = simple_open,
1626 -       .owner = THIS_MODULE,
1627 -       .llseek = default_llseek,
1628 -};
1629 -
1630 -static ssize_t read_file_spectral_short_repeat(struct file *file,
1631 -                                              char __user *user_buf,
1632 -                                              size_t count, loff_t *ppos)
1633 -{
1634 -       struct ath_softc *sc = file->private_data;
1635 -       char buf[32];
1636 -       unsigned int len;
1637 -
1638 -       len = sprintf(buf, "%d\n", sc->spec_config.short_repeat);
1639 -       return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1640 -}
1641 -
1642 -static ssize_t write_file_spectral_short_repeat(struct file *file,
1643 -                                               const char __user *user_buf,
1644 -                                               size_t count, loff_t *ppos)
1645 -{
1646 -       struct ath_softc *sc = file->private_data;
1647 -       unsigned long val;
1648 -       char buf[32];
1649 -       ssize_t len;
1650 -
1651 -       len = min(count, sizeof(buf) - 1);
1652 -       if (copy_from_user(buf, user_buf, len))
1653 -               return -EFAULT;
1654 -
1655 -       buf[len] = '\0';
1656 -       if (kstrtoul(buf, 0, &val))
1657 -               return -EINVAL;
1658 -
1659 -       if (val < 0 || val > 1)
1660 -               return -EINVAL;
1661 -
1662 -       sc->spec_config.short_repeat = val;
1663 -       return count;
1664 -}
1665 -
1666 -static const struct file_operations fops_spectral_short_repeat = {
1667 -       .read = read_file_spectral_short_repeat,
1668 -       .write = write_file_spectral_short_repeat,
1669 -       .open = simple_open,
1670 -       .owner = THIS_MODULE,
1671 -       .llseek = default_llseek,
1672 -};
1673 -
1674 -static ssize_t read_file_spectral_count(struct file *file,
1675 -                                       char __user *user_buf,
1676 -                                       size_t count, loff_t *ppos)
1677 -{
1678 -       struct ath_softc *sc = file->private_data;
1679 -       char buf[32];
1680 -       unsigned int len;
1681 -
1682 -       len = sprintf(buf, "%d\n", sc->spec_config.count);
1683 -       return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1684 -}
1685 -
1686 -static ssize_t write_file_spectral_count(struct file *file,
1687 -                                        const char __user *user_buf,
1688 -                                        size_t count, loff_t *ppos)
1689 -{
1690 -       struct ath_softc *sc = file->private_data;
1691 -       unsigned long val;
1692 -       char buf[32];
1693 -       ssize_t len;
1694 -
1695 -       len = min(count, sizeof(buf) - 1);
1696 -       if (copy_from_user(buf, user_buf, len))
1697 -               return -EFAULT;
1698 -
1699 -       buf[len] = '\0';
1700 -       if (kstrtoul(buf, 0, &val))
1701 -               return -EINVAL;
1702 -
1703 -       if (val < 0 || val > 255)
1704 -               return -EINVAL;
1705 -
1706 -       sc->spec_config.count = val;
1707 -       return count;
1708 -}
1709 -
1710 -static const struct file_operations fops_spectral_count = {
1711 -       .read = read_file_spectral_count,
1712 -       .write = write_file_spectral_count,
1713 -       .open = simple_open,
1714 -       .owner = THIS_MODULE,
1715 -       .llseek = default_llseek,
1716 -};
1717 -
1718 -static ssize_t read_file_spectral_period(struct file *file,
1719 -                                        char __user *user_buf,
1720 -                                        size_t count, loff_t *ppos)
1721 -{
1722 -       struct ath_softc *sc = file->private_data;
1723 -       char buf[32];
1724 -       unsigned int len;
1725 -
1726 -       len = sprintf(buf, "%d\n", sc->spec_config.period);
1727 -       return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1728 -}
1729 -
1730 -static ssize_t write_file_spectral_period(struct file *file,
1731 -                                         const char __user *user_buf,
1732 -                                         size_t count, loff_t *ppos)
1733 -{
1734 -       struct ath_softc *sc = file->private_data;
1735 -       unsigned long val;
1736 -       char buf[32];
1737 -       ssize_t len;
1738 -
1739 -       len = min(count, sizeof(buf) - 1);
1740 -       if (copy_from_user(buf, user_buf, len))
1741 -               return -EFAULT;
1742 -
1743 -       buf[len] = '\0';
1744 -       if (kstrtoul(buf, 0, &val))
1745 -               return -EINVAL;
1746 -
1747 -       if (val < 0 || val > 255)
1748 -               return -EINVAL;
1749 -
1750 -       sc->spec_config.period = val;
1751 -       return count;
1752 -}
1753 -
1754 -static const struct file_operations fops_spectral_period = {
1755 -       .read = read_file_spectral_period,
1756 -       .write = write_file_spectral_period,
1757 -       .open = simple_open,
1758 -       .owner = THIS_MODULE,
1759 -       .llseek = default_llseek,
1760 -};
1761 -
1762 -static ssize_t read_file_spectral_fft_period(struct file *file,
1763 -                                            char __user *user_buf,
1764 -                                            size_t count, loff_t *ppos)
1765 -{
1766 -       struct ath_softc *sc = file->private_data;
1767 -       char buf[32];
1768 -       unsigned int len;
1769 -
1770 -       len = sprintf(buf, "%d\n", sc->spec_config.fft_period);
1771 -       return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1772 -}
1773 -
1774 -static ssize_t write_file_spectral_fft_period(struct file *file,
1775 -                                             const char __user *user_buf,
1776 -                                             size_t count, loff_t *ppos)
1777 -{
1778 -       struct ath_softc *sc = file->private_data;
1779 -       unsigned long val;
1780 -       char buf[32];
1781 -       ssize_t len;
1782 -
1783 -       len = min(count, sizeof(buf) - 1);
1784 -       if (copy_from_user(buf, user_buf, len))
1785 -               return -EFAULT;
1786 -
1787 -       buf[len] = '\0';
1788 -       if (kstrtoul(buf, 0, &val))
1789 -               return -EINVAL;
1790 -
1791 -       if (val < 0 || val > 15)
1792 -               return -EINVAL;
1793 -
1794 -       sc->spec_config.fft_period = val;
1795 -       return count;
1796 -}
1797 -
1798 -static const struct file_operations fops_spectral_fft_period = {
1799 -       .read = read_file_spectral_fft_period,
1800 -       .write = write_file_spectral_fft_period,
1801 -       .open = simple_open,
1802 -       .owner = THIS_MODULE,
1803 -       .llseek = default_llseek,
1804 -};
1805 -
1806 -static struct dentry *create_buf_file_handler(const char *filename,
1807 -                                             struct dentry *parent,
1808 -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,3,0))
1809 -                                             umode_t mode,
1810 -#else
1811 -                                             int mode,
1812 -#endif
1813 -                                             struct rchan_buf *buf,
1814 -                                             int *is_global)
1815 -{
1816 -       struct dentry *buf_file;
1817 -
1818 -       buf_file = debugfs_create_file(filename, mode, parent, buf,
1819 -                                      &relay_file_operations);
1820 -       *is_global = 1;
1821 -       return buf_file;
1822 -}
1823 -
1824 -static int remove_buf_file_handler(struct dentry *dentry)
1825 -{
1826 -       debugfs_remove(dentry);
1827 -
1828 -       return 0;
1829 -}
1830 -
1831 -void ath_debug_send_fft_sample(struct ath_softc *sc,
1832 -                              struct fft_sample_tlv *fft_sample_tlv)
1833 -{
1834 -       int length;
1835 -       if (!sc->rfs_chan_spec_scan)
1836 -               return;
1837 -
1838 -       length = __be16_to_cpu(fft_sample_tlv->length) +
1839 -                sizeof(*fft_sample_tlv);
1840 -       relay_write(sc->rfs_chan_spec_scan, fft_sample_tlv, length);
1841 -}
1842 -
1843 -static struct rchan_callbacks rfs_spec_scan_cb = {
1844 -       .create_buf_file = create_buf_file_handler,
1845 -       .remove_buf_file = remove_buf_file_handler,
1846 -};
1847 -
1848 -
1849  static ssize_t read_file_regidx(struct file *file, char __user *user_buf,
1850                                  size_t count, loff_t *ppos)
1851  {
1852 @@ -1776,117 +1525,9 @@ void ath9k_get_et_stats(struct ieee80211
1853
1854  void ath9k_deinit_debug(struct ath_softc *sc)
1855  {
1856 -       if (config_enabled(CPTCFG_ATH9K_DEBUGFS) && sc->rfs_chan_spec_scan) {
1857 -               relay_close(sc->rfs_chan_spec_scan);
1858 -               sc->rfs_chan_spec_scan = NULL;
1859 -       }
1860 +       ath9k_spectral_deinit_debug(sc);
1861  }
1862
1863 -static ssize_t read_file_tx99(struct file *file, char __user *user_buf,
1864 -                             size_t count, loff_t *ppos)
1865 -{
1866 -       struct ath_softc *sc = file->private_data;
1867 -       char buf[3];
1868 -       unsigned int len;
1869 -
1870 -       len = sprintf(buf, "%d\n", sc->tx99_state);
1871 -       return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1872 -}
1873 -
1874 -static ssize_t write_file_tx99(struct file *file, const char __user *user_buf,
1875 -                              size_t count, loff_t *ppos)
1876 -{
1877 -       struct ath_softc *sc = file->private_data;
1878 -       struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1879 -       char buf[32];
1880 -       bool start;
1881 -       ssize_t len;
1882 -       int r;
1883 -
1884 -       if (sc->nvifs > 1)
1885 -               return -EOPNOTSUPP;
1886 -
1887 -       len = min(count, sizeof(buf) - 1);
1888 -       if (copy_from_user(buf, user_buf, len))
1889 -               return -EFAULT;
1890 -
1891 -       if (strtobool(buf, &start))
1892 -               return -EINVAL;
1893 -
1894 -       if (start == sc->tx99_state) {
1895 -               if (!start)
1896 -                       return count;
1897 -               ath_dbg(common, XMIT, "Resetting TX99\n");
1898 -               ath9k_tx99_deinit(sc);
1899 -       }
1900 -
1901 -       if (!start) {
1902 -               ath9k_tx99_deinit(sc);
1903 -               return count;
1904 -       }
1905 -
1906 -       r = ath9k_tx99_init(sc);
1907 -       if (r)
1908 -               return r;
1909 -
1910 -       return count;
1911 -}
1912 -
1913 -static const struct file_operations fops_tx99 = {
1914 -       .read = read_file_tx99,
1915 -       .write = write_file_tx99,
1916 -       .open = simple_open,
1917 -       .owner = THIS_MODULE,
1918 -       .llseek = default_llseek,
1919 -};
1920 -
1921 -static ssize_t read_file_tx99_power(struct file *file,
1922 -                                   char __user *user_buf,
1923 -                                   size_t count, loff_t *ppos)
1924 -{
1925 -       struct ath_softc *sc = file->private_data;
1926 -       char buf[32];
1927 -       unsigned int len;
1928 -
1929 -       len = sprintf(buf, "%d (%d dBm)\n",
1930 -                     sc->tx99_power,
1931 -                     sc->tx99_power / 2);
1932 -
1933 -       return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1934 -}
1935 -
1936 -static ssize_t write_file_tx99_power(struct file *file,
1937 -                                    const char __user *user_buf,
1938 -                                    size_t count, loff_t *ppos)
1939 -{
1940 -       struct ath_softc *sc = file->private_data;
1941 -       int r;
1942 -       u8 tx_power;
1943 -
1944 -       r = kstrtou8_from_user(user_buf, count, 0, &tx_power);
1945 -       if (r)
1946 -               return r;
1947 -
1948 -       if (tx_power > MAX_RATE_POWER)
1949 -               return -EINVAL;
1950 -
1951 -       sc->tx99_power = tx_power;
1952 -
1953 -       ath9k_ps_wakeup(sc);
1954 -       ath9k_hw_tx99_set_txpower(sc->sc_ah, sc->tx99_power);
1955 -       ath9k_ps_restore(sc);
1956 -
1957 -       return count;
1958 -}
1959 -
1960 -static const struct file_operations fops_tx99_power = {
1961 -       .read = read_file_tx99_power,
1962 -       .write = write_file_tx99_power,
1963 -       .open = simple_open,
1964 -       .owner = THIS_MODULE,
1965 -       .llseek = default_llseek,
1966 -};
1967 -
1968  int ath9k_init_debug(struct ath_hw *ah)
1969  {
1970         struct ath_common *common = ath9k_hw_common(ah);
1971 @@ -1903,6 +1544,8 @@ int ath9k_init_debug(struct ath_hw *ah)
1972  #endif
1973
1974         ath9k_dfs_init_debug(sc);
1975 +       ath9k_tx99_init_debug(sc);
1976 +       ath9k_spectral_init_debug(sc);
1977
1978         debugfs_create_file("dma", S_IRUSR, sc->debug.debugfs_phy, sc,
1979                             &fops_dma);
1980 @@ -1949,23 +1592,6 @@ int ath9k_init_debug(struct ath_hw *ah)
1981                             &fops_base_eeprom);
1982         debugfs_create_file("modal_eeprom", S_IRUSR, sc->debug.debugfs_phy, sc,
1983                             &fops_modal_eeprom);
1984 -       sc->rfs_chan_spec_scan = relay_open("spectral_scan",
1985 -                                           sc->debug.debugfs_phy,
1986 -                                           1024, 256, &rfs_spec_scan_cb,
1987 -                                           NULL);
1988 -       debugfs_create_file("spectral_scan_ctl", S_IRUSR | S_IWUSR,
1989 -                           sc->debug.debugfs_phy, sc,
1990 -                           &fops_spec_scan_ctl);
1991 -       debugfs_create_file("spectral_short_repeat", S_IRUSR | S_IWUSR,
1992 -                           sc->debug.debugfs_phy, sc,
1993 -                           &fops_spectral_short_repeat);
1994 -       debugfs_create_file("spectral_count", S_IRUSR | S_IWUSR,
1995 -                           sc->debug.debugfs_phy, sc, &fops_spectral_count);
1996 -       debugfs_create_file("spectral_period", S_IRUSR | S_IWUSR,
1997 -                           sc->debug.debugfs_phy, sc, &fops_spectral_period);
1998 -       debugfs_create_file("spectral_fft_period", S_IRUSR | S_IWUSR,
1999 -                           sc->debug.debugfs_phy, sc,
2000 -                           &fops_spectral_fft_period);
2001         debugfs_create_u32("gpio_mask", S_IRUSR | S_IWUSR,
2002                            sc->debug.debugfs_phy, &sc->sc_ah->gpio_mask);
2003         debugfs_create_u32("gpio_val", S_IRUSR | S_IWUSR,
2004 @@ -1978,15 +1604,6 @@ int ath9k_init_debug(struct ath_hw *ah)
2005         debugfs_create_file("btcoex", S_IRUSR, sc->debug.debugfs_phy, sc,
2006                             &fops_btcoex);
2007  #endif
2008 -       if (config_enabled(CPTCFG_ATH9K_TX99) &&
2009 -           AR_SREV_9300_20_OR_LATER(ah)) {
2010 -               debugfs_create_file("tx99", S_IRUSR | S_IWUSR,
2011 -                                   sc->debug.debugfs_phy, sc,
2012 -                                   &fops_tx99);
2013 -               debugfs_create_file("tx99_power", S_IRUSR | S_IWUSR,
2014 -                                   sc->debug.debugfs_phy, sc,
2015 -                                   &fops_tx99_power);
2016 -       }
2017
2018         return 0;
2019  }
2020 --- a/drivers/net/wireless/ath/ath9k/hw.c
2021 +++ b/drivers/net/wireless/ath/ath9k/hw.c
2022 @@ -17,6 +17,8 @@
2023  #include <linux/io.h>
2024  #include <linux/slab.h>
2025  #include <linux/module.h>
2026 +#include <linux/time.h>
2027 +#include <linux/bitops.h>
2028  #include <asm/unaligned.h>
2029
2030  #include "hw.h"
2031 @@ -83,48 +85,6 @@ static void ath9k_hw_ani_cache_ini_regs(
2032
2033  #ifdef CPTCFG_ATH9K_DEBUGFS
2034
2035 -void ath9k_debug_sync_cause(struct ath_common *common, u32 sync_cause)
2036 -{
2037 -       struct ath_softc *sc = common->priv;
2038 -       if (sync_cause)
2039 -               sc->debug.stats.istats.sync_cause_all++;
2040 -       if (sync_cause & AR_INTR_SYNC_RTC_IRQ)
2041 -               sc->debug.stats.istats.sync_rtc_irq++;
2042 -       if (sync_cause & AR_INTR_SYNC_MAC_IRQ)
2043 -               sc->debug.stats.istats.sync_mac_irq++;
2044 -       if (sync_cause & AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS)
2045 -               sc->debug.stats.istats.eeprom_illegal_access++;
2046 -       if (sync_cause & AR_INTR_SYNC_APB_TIMEOUT)
2047 -               sc->debug.stats.istats.apb_timeout++;
2048 -       if (sync_cause & AR_INTR_SYNC_PCI_MODE_CONFLICT)
2049 -               sc->debug.stats.istats.pci_mode_conflict++;
2050 -       if (sync_cause & AR_INTR_SYNC_HOST1_FATAL)
2051 -               sc->debug.stats.istats.host1_fatal++;
2052 -       if (sync_cause & AR_INTR_SYNC_HOST1_PERR)
2053 -               sc->debug.stats.istats.host1_perr++;
2054 -       if (sync_cause & AR_INTR_SYNC_TRCV_FIFO_PERR)
2055 -               sc->debug.stats.istats.trcv_fifo_perr++;
2056 -       if (sync_cause & AR_INTR_SYNC_RADM_CPL_EP)
2057 -               sc->debug.stats.istats.radm_cpl_ep++;
2058 -       if (sync_cause & AR_INTR_SYNC_RADM_CPL_DLLP_ABORT)
2059 -               sc->debug.stats.istats.radm_cpl_dllp_abort++;
2060 -       if (sync_cause & AR_INTR_SYNC_RADM_CPL_TLP_ABORT)
2061 -               sc->debug.stats.istats.radm_cpl_tlp_abort++;
2062 -       if (sync_cause & AR_INTR_SYNC_RADM_CPL_ECRC_ERR)
2063 -               sc->debug.stats.istats.radm_cpl_ecrc_err++;
2064 -       if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT)
2065 -               sc->debug.stats.istats.radm_cpl_timeout++;
2066 -       if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT)
2067 -               sc->debug.stats.istats.local_timeout++;
2068 -       if (sync_cause & AR_INTR_SYNC_PM_ACCESS)
2069 -               sc->debug.stats.istats.pm_access++;
2070 -       if (sync_cause & AR_INTR_SYNC_MAC_AWAKE)
2071 -               sc->debug.stats.istats.mac_awake++;
2072 -       if (sync_cause & AR_INTR_SYNC_MAC_ASLEEP)
2073 -               sc->debug.stats.istats.mac_asleep++;
2074 -       if (sync_cause & AR_INTR_SYNC_MAC_SLEEP_ACCESS)
2075 -               sc->debug.stats.istats.mac_sleep_access++;
2076 -}
2077  #endif
2078
2079
2080 @@ -438,23 +398,13 @@ static bool ath9k_hw_chip_test(struct at
2081
2082  static void ath9k_hw_init_config(struct ath_hw *ah)
2083  {
2084 -       int i;
2085 -
2086         ah->config.dma_beacon_response_time = 1;
2087         ah->config.sw_beacon_response_time = 6;
2088 -       ah->config.additional_swba_backoff = 0;
2089         ah->config.ack_6mb = 0x0;
2090         ah->config.cwm_ignore_extcca = 0;
2091 -       ah->config.pcie_clock_req = 0;
2092         ah->config.analog_shiftreg = 1;
2093
2094 -       for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2095 -               ah->config.spurchans[i][0] = AR_NO_SPUR;
2096 -               ah->config.spurchans[i][1] = AR_NO_SPUR;
2097 -       }
2098 -
2099         ah->config.rx_intr_mitigation = true;
2100 -       ah->config.pcieSerDesWrite = true;
2101
2102         /*
2103          * We need this for PCI devices only (Cardbus, PCI, miniPCI)
2104 @@ -486,7 +436,6 @@ static void ath9k_hw_init_defaults(struc
2105         ah->hw_version.magic = AR5416_MAGIC;
2106         ah->hw_version.subvendorid = 0;
2107
2108 -       ah->atim_window = 0;
2109         ah->sta_id1_defaults =
2110                 AR_STA_ID1_CRPT_MIC_ENABLE |
2111                 AR_STA_ID1_MCAST_KSRCH;
2112 @@ -549,11 +498,11 @@ static int ath9k_hw_post_init(struct ath
2113          * EEPROM needs to be initialized before we do this.
2114          * This is required for regulatory compliance.
2115          */
2116 -       if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
2117 +       if (AR_SREV_9300_20_OR_LATER(ah)) {
2118                 u16 regdmn = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
2119                 if ((regdmn & 0xF0) == CTL_FCC) {
2120 -                       ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9462_FCC_2GHZ;
2121 -                       ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9462_FCC_5GHZ;
2122 +                       ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ;
2123 +                       ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ;
2124                 }
2125         }
2126
2127 @@ -1282,6 +1231,42 @@ void ath9k_hw_get_delta_slope_vals(struc
2128         *coef_exponent = coef_exp - 16;
2129  }
2130
2131 +/* AR9330 WAR:
2132 + * call external reset function to reset WMAC if:
2133 + * - doing a cold reset
2134 + * - we have pending frames in the TX queues.
2135 + */
2136 +static bool ath9k_hw_ar9330_reset_war(struct ath_hw *ah, int type)
2137 +{
2138 +       int i, npend = 0;
2139 +
2140 +       for (i = 0; i < AR_NUM_QCU; i++) {
2141 +               npend = ath9k_hw_numtxpending(ah, i);
2142 +               if (npend)
2143 +                       break;
2144 +       }
2145 +
2146 +       if (ah->external_reset &&
2147 +           (npend || type == ATH9K_RESET_COLD)) {
2148 +               int reset_err = 0;
2149 +
2150 +               ath_dbg(ath9k_hw_common(ah), RESET,
2151 +                       "reset MAC via external reset\n");
2152 +
2153 +               reset_err = ah->external_reset();
2154 +               if (reset_err) {
2155 +                       ath_err(ath9k_hw_common(ah),
2156 +                               "External reset failed, err=%d\n",
2157 +                               reset_err);
2158 +                       return false;
2159 +               }
2160 +
2161 +               REG_WRITE(ah, AR_RTC_RESET, 1);
2162 +       }
2163 +
2164 +       return true;
2165 +}
2166 +
2167  static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
2168  {
2169         u32 rst_flags;
2170 @@ -1332,38 +1317,8 @@ static bool ath9k_hw_set_reset(struct at
2171         }
2172
2173         if (AR_SREV_9330(ah)) {
2174 -               int npend = 0;
2175 -               int i;
2176 -
2177 -               /* AR9330 WAR:
2178 -                * call external reset function to reset WMAC if:
2179 -                * - doing a cold reset
2180 -                * - we have pending frames in the TX queues
2181 -                */
2182 -
2183 -               for (i = 0; i < AR_NUM_QCU; i++) {
2184 -                       npend = ath9k_hw_numtxpending(ah, i);
2185 -                       if (npend)
2186 -                               break;
2187 -               }
2188 -
2189 -               if (ah->external_reset &&
2190 -                   (npend || type == ATH9K_RESET_COLD)) {
2191 -                       int reset_err = 0;
2192 -
2193 -                       ath_dbg(ath9k_hw_common(ah), RESET,
2194 -                               "reset MAC via external reset\n");
2195 -
2196 -                       reset_err = ah->external_reset();
2197 -                       if (reset_err) {
2198 -                               ath_err(ath9k_hw_common(ah),
2199 -                                       "External reset failed, err=%d\n",
2200 -                                       reset_err);
2201 -                               return false;
2202 -                       }
2203 -
2204 -                       REG_WRITE(ah, AR_RTC_RESET, 1);
2205 -               }
2206 +               if (!ath9k_hw_ar9330_reset_war(ah, type))
2207 +                       return false;
2208         }
2209
2210         if (ath9k_hw_mci_is_enabled(ah))
2211 @@ -1373,7 +1328,12 @@ static bool ath9k_hw_set_reset(struct at
2212
2213         REGWRITE_BUFFER_FLUSH(ah);
2214
2215 -       udelay(50);
2216 +       if (AR_SREV_9300_20_OR_LATER(ah))
2217 +               udelay(50);
2218 +       else if (AR_SREV_9100(ah))
2219 +               udelay(10000);
2220 +       else
2221 +               udelay(100);
2222
2223         REG_WRITE(ah, AR_RTC_RC, 0);
2224         if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
2225 @@ -1409,8 +1369,7 @@ static bool ath9k_hw_set_reset_power_on(
2226
2227         REGWRITE_BUFFER_FLUSH(ah);
2228
2229 -       if (!AR_SREV_9300_20_OR_LATER(ah))
2230 -               udelay(2);
2231 +       udelay(2);
2232
2233         if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
2234                 REG_WRITE(ah, AR_RC, 0);
2235 @@ -1502,8 +1461,9 @@ static bool ath9k_hw_channel_change(stru
2236         int r;
2237
2238         if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) {
2239 -               band_switch = IS_CHAN_5GHZ(ah->curchan) != IS_CHAN_5GHZ(chan);
2240 -               mode_diff = (chan->channelFlags != ah->curchan->channelFlags);
2241 +               u32 flags_diff = chan->channelFlags ^ ah->curchan->channelFlags;
2242 +               band_switch = !!(flags_diff & CHANNEL_5GHZ);
2243 +               mode_diff = !!(flags_diff & ~CHANNEL_HT);
2244         }
2245
2246         for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
2247 @@ -1815,7 +1775,7 @@ static int ath9k_hw_do_fastcc(struct ath
2248          * If cross-band fcc is not supoprted, bail out if channelFlags differ.
2249          */
2250         if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) &&
2251 -           chan->channelFlags != ah->curchan->channelFlags)
2252 +           ((chan->channelFlags ^ ah->curchan->channelFlags) & ~CHANNEL_HT))
2253                 goto fail;
2254
2255         if (!ath9k_hw_check_alive(ah))
2256 @@ -1856,10 +1816,12 @@ int ath9k_hw_reset(struct ath_hw *ah, st
2257                    struct ath9k_hw_cal_data *caldata, bool fastcc)
2258  {
2259         struct ath_common *common = ath9k_hw_common(ah);
2260 +       struct timespec ts;
2261         u32 saveLedState;
2262         u32 saveDefAntenna;
2263         u32 macStaId1;
2264         u64 tsf = 0;
2265 +       s64 usec = 0;
2266         int r;
2267         bool start_mci_reset = false;
2268         bool save_fullsleep = ah->chip_fullsleep;
2269 @@ -1902,10 +1864,10 @@ int ath9k_hw_reset(struct ath_hw *ah, st
2270
2271         macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2272
2273 -       /* For chips on which RTC reset is done, save TSF before it gets cleared */
2274 -       if (AR_SREV_9100(ah) ||
2275 -           (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)))
2276 -               tsf = ath9k_hw_gettsf64(ah);
2277 +       /* Save TSF before chip reset, a cold reset clears it */
2278 +       tsf = ath9k_hw_gettsf64(ah);
2279 +       getrawmonotonic(&ts);
2280 +       usec = ts.tv_sec * 1000 + ts.tv_nsec / 1000;
2281
2282         saveLedState = REG_READ(ah, AR_CFG_LED) &
2283                 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2284 @@ -1938,8 +1900,9 @@ int ath9k_hw_reset(struct ath_hw *ah, st
2285         }
2286
2287         /* Restore TSF */
2288 -       if (tsf)
2289 -               ath9k_hw_settsf64(ah, tsf);
2290 +       getrawmonotonic(&ts);
2291 +       usec = ts.tv_sec * 1000 + ts.tv_nsec / 1000 - usec;
2292 +       ath9k_hw_settsf64(ah, tsf + usec);
2293
2294         if (AR_SREV_9280_20_OR_LATER(ah))
2295                 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
2296 @@ -2261,9 +2224,6 @@ void ath9k_hw_beaconinit(struct ath_hw *
2297         case NL80211_IFTYPE_ADHOC:
2298                 REG_SET_BIT(ah, AR_TXCFG,
2299                             AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2300 -               REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon +
2301 -                         TU_TO_USEC(ah->atim_window ? ah->atim_window : 1));
2302 -               flags |= AR_NDP_TIMER_EN;
2303         case NL80211_IFTYPE_MESH_POINT:
2304         case NL80211_IFTYPE_AP:
2305                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
2306 @@ -2284,7 +2244,6 @@ void ath9k_hw_beaconinit(struct ath_hw *
2307         REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
2308         REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
2309         REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
2310 -       REG_WRITE(ah, AR_NDP_PERIOD, beacon_period);
2311
2312         REGWRITE_BUFFER_FLUSH(ah);
2313
2314 @@ -2301,12 +2260,9 @@ void ath9k_hw_set_sta_beacon_timers(stru
2315
2316         ENABLE_REGWRITE_BUFFER(ah);
2317
2318 -       REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
2319 -
2320 -       REG_WRITE(ah, AR_BEACON_PERIOD,
2321 -                 TU_TO_USEC(bs->bs_intval));
2322 -       REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
2323 -                 TU_TO_USEC(bs->bs_intval));
2324 +       REG_WRITE(ah, AR_NEXT_TBTT_TIMER, bs->bs_nexttbtt);
2325 +       REG_WRITE(ah, AR_BEACON_PERIOD, bs->bs_intval);
2326 +       REG_WRITE(ah, AR_DMA_BEACON_PERIOD, bs->bs_intval);
2327
2328         REGWRITE_BUFFER_FLUSH(ah);
2329
2330 @@ -2334,9 +2290,8 @@ void ath9k_hw_set_sta_beacon_timers(stru
2331
2332         ENABLE_REGWRITE_BUFFER(ah);
2333
2334 -       REG_WRITE(ah, AR_NEXT_DTIM,
2335 -                 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
2336 -       REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
2337 +       REG_WRITE(ah, AR_NEXT_DTIM, bs->bs_nextdtim - SLEEP_SLOP);
2338 +       REG_WRITE(ah, AR_NEXT_TIM, nextTbtt - SLEEP_SLOP);
2339
2340         REG_WRITE(ah, AR_SLEEP1,
2341                   SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
2342 @@ -2350,8 +2305,8 @@ void ath9k_hw_set_sta_beacon_timers(stru
2343         REG_WRITE(ah, AR_SLEEP2,
2344                   SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
2345
2346 -       REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
2347 -       REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
2348 +       REG_WRITE(ah, AR_TIM_PERIOD, beaconintval);
2349 +       REG_WRITE(ah, AR_DTIM_PERIOD, dtimperiod);
2350
2351         REGWRITE_BUFFER_FLUSH(ah);
2352
2353 @@ -2987,20 +2942,6 @@ static const struct ath_gen_timer_config
2354
2355  /* HW generic timer primitives */
2356
2357 -/* compute and clear index of rightmost 1 */
2358 -static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2359 -{
2360 -       u32 b;
2361 -
2362 -       b = *mask;
2363 -       b &= (0-b);
2364 -       *mask &= ~b;
2365 -       b *= debruijn32;
2366 -       b >>= 27;
2367 -
2368 -       return timer_table->gen_timer_index[b];
2369 -}
2370 -
2371  u32 ath9k_hw_gettsf32(struct ath_hw *ah)
2372  {
2373         return REG_READ(ah, AR_TSF_L32);
2374 @@ -3016,6 +2957,10 @@ struct ath_gen_timer *ath_gen_timer_allo
2375         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2376         struct ath_gen_timer *timer;
2377
2378 +       if ((timer_index < AR_FIRST_NDP_TIMER) ||
2379 +               (timer_index >= ATH_MAX_GEN_TIMER))
2380 +               return NULL;
2381 +
2382         timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2383         if (timer == NULL)
2384                 return NULL;
2385 @@ -3033,23 +2978,13 @@ EXPORT_SYMBOL(ath_gen_timer_alloc);
2386
2387  void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2388                               struct ath_gen_timer *timer,
2389 -                             u32 trig_timeout,
2390 +                             u32 timer_next,
2391                               u32 timer_period)
2392  {
2393         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2394 -       u32 tsf, timer_next;
2395 -
2396 -       BUG_ON(!timer_period);
2397 -
2398 -       set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2399 +       u32 mask = 0;
2400
2401 -       tsf = ath9k_hw_gettsf32(ah);
2402 -
2403 -       timer_next = tsf + trig_timeout;
2404 -
2405 -       ath_dbg(ath9k_hw_common(ah), BTCOEX,
2406 -               "current tsf %x period %x timer_next %x\n",
2407 -               tsf, timer_period, timer_next);
2408 +       timer_table->timer_mask |= BIT(timer->index);
2409
2410         /*
2411          * Program generic timer registers
2412 @@ -3075,10 +3010,19 @@ void ath9k_hw_gen_timer_start(struct ath
2413                                        (1 << timer->index));
2414         }
2415
2416 -       /* Enable both trigger and thresh interrupt masks */
2417 -       REG_SET_BIT(ah, AR_IMR_S5,
2418 -               (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2419 -               SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2420 +       if (timer->trigger)
2421 +               mask |= SM(AR_GENTMR_BIT(timer->index),
2422 +                          AR_IMR_S5_GENTIMER_TRIG);
2423 +       if (timer->overflow)
2424 +               mask |= SM(AR_GENTMR_BIT(timer->index),
2425 +                          AR_IMR_S5_GENTIMER_THRESH);
2426 +
2427 +       REG_SET_BIT(ah, AR_IMR_S5, mask);
2428 +
2429 +       if ((ah->imask & ATH9K_INT_GENTIMER) == 0) {
2430 +               ah->imask |= ATH9K_INT_GENTIMER;
2431 +               ath9k_hw_set_interrupts(ah);
2432 +       }
2433  }
2434  EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
2435
2436 @@ -3086,11 +3030,6 @@ void ath9k_hw_gen_timer_stop(struct ath_
2437  {
2438         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2439
2440 -       if ((timer->index < AR_FIRST_NDP_TIMER) ||
2441 -               (timer->index >= ATH_MAX_GEN_TIMER)) {
2442 -               return;
2443 -       }
2444 -
2445         /* Clear generic timer enable bits. */
2446         REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2447                         gen_tmr_configuration[timer->index].mode_mask);
2448 @@ -3110,7 +3049,12 @@ void ath9k_hw_gen_timer_stop(struct ath_
2449                 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2450                 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2451
2452 -       clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
2453 +       timer_table->timer_mask &= ~BIT(timer->index);
2454 +
2455 +       if (timer_table->timer_mask == 0) {
2456 +               ah->imask &= ~ATH9K_INT_GENTIMER;
2457 +               ath9k_hw_set_interrupts(ah);
2458 +       }
2459  }
2460  EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
2461
2462 @@ -3131,32 +3075,32 @@ void ath_gen_timer_isr(struct ath_hw *ah
2463  {
2464         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2465         struct ath_gen_timer *timer;
2466 -       struct ath_common *common = ath9k_hw_common(ah);
2467 -       u32 trigger_mask, thresh_mask, index;
2468 +       unsigned long trigger_mask, thresh_mask;
2469 +       unsigned int index;
2470
2471         /* get hardware generic timer interrupt status */
2472         trigger_mask = ah->intr_gen_timer_trigger;
2473         thresh_mask = ah->intr_gen_timer_thresh;
2474 -       trigger_mask &= timer_table->timer_mask.val;
2475 -       thresh_mask &= timer_table->timer_mask.val;
2476 +       trigger_mask &= timer_table->timer_mask;
2477 +       thresh_mask &= timer_table->timer_mask;
2478
2479         trigger_mask &= ~thresh_mask;
2480
2481 -       while (thresh_mask) {
2482 -               index = rightmost_index(timer_table, &thresh_mask);
2483 +       for_each_set_bit(index, &thresh_mask, ARRAY_SIZE(timer_table->timers)) {
2484                 timer = timer_table->timers[index];
2485 -               BUG_ON(!timer);
2486 -               ath_dbg(common, BTCOEX, "TSF overflow for Gen timer %d\n",
2487 -                       index);
2488 +               if (!timer)
2489 +                   continue;
2490 +               if (!timer->overflow)
2491 +                   continue;
2492                 timer->overflow(timer->arg);
2493         }
2494
2495 -       while (trigger_mask) {
2496 -               index = rightmost_index(timer_table, &trigger_mask);
2497 +       for_each_set_bit(index, &trigger_mask, ARRAY_SIZE(timer_table->timers)) {
2498                 timer = timer_table->timers[index];
2499 -               BUG_ON(!timer);
2500 -               ath_dbg(common, BTCOEX,
2501 -                       "Gen timer[%d] trigger\n", index);
2502 +               if (!timer)
2503 +                   continue;
2504 +               if (!timer->trigger)
2505 +                   continue;
2506                 timer->trigger(timer->arg);
2507         }
2508  }
2509 --- a/drivers/net/wireless/ath/ath9k/hw.h
2510 +++ b/drivers/net/wireless/ath/ath9k/hw.h
2511 @@ -168,7 +168,7 @@
2512  #define CAB_TIMEOUT_VAL             10
2513  #define BEACON_TIMEOUT_VAL          10
2514  #define MIN_BEACON_TIMEOUT_VAL      1
2515 -#define SLEEP_SLOP                  3
2516 +#define SLEEP_SLOP                  TU_TO_USEC(3)
2517
2518  #define INIT_CONFIG_STATUS          0x00000000
2519  #define INIT_RSSI_THR               0x00000700
2520 @@ -280,11 +280,8 @@ struct ath9k_hw_capabilities {
2521  struct ath9k_ops_config {
2522         int dma_beacon_response_time;
2523         int sw_beacon_response_time;
2524 -       int additional_swba_backoff;
2525         int ack_6mb;
2526         u32 cwm_ignore_extcca;
2527 -       bool pcieSerDesWrite;
2528 -       u8 pcie_clock_req;
2529         u32 pcie_waen;
2530         u8 analog_shiftreg;
2531         u32 ofdm_trig_low;
2532 @@ -295,18 +292,11 @@ struct ath9k_ops_config {
2533         int serialize_regmode;
2534         bool rx_intr_mitigation;
2535         bool tx_intr_mitigation;
2536 -#define SPUR_DISABLE           0
2537 -#define SPUR_ENABLE_IOCTL      1
2538 -#define SPUR_ENABLE_EEPROM     2
2539 -#define AR_SPUR_5413_1         1640
2540 -#define AR_SPUR_5413_2         1200
2541  #define AR_NO_SPUR             0x8000
2542  #define AR_BASE_FREQ_2GHZ      2300
2543  #define AR_BASE_FREQ_5GHZ      4900
2544  #define AR_SPUR_FEEQ_BOUND_HT40 19
2545  #define AR_SPUR_FEEQ_BOUND_HT20 10
2546 -       int spurmode;
2547 -       u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
2548         u8 max_txtrig_level;
2549         u16 ani_poll_interval; /* ANI poll interval in ms */
2550
2551 @@ -316,6 +306,8 @@ struct ath9k_ops_config {
2552         u32 ant_ctrl_comm2g_switch_enable;
2553         bool xatten_margin_cfg;
2554         bool alt_mingainidx;
2555 +       bool no_pll_pwrsave;
2556 +       bool tx_gain_buffalo;
2557  };
2558
2559  enum ath9k_int {
2560 @@ -459,10 +451,6 @@ struct ath9k_beacon_state {
2561         u32 bs_intval;
2562  #define ATH9K_TSFOOR_THRESHOLD    0x00004240 /* 16k us */
2563         u32 bs_dtimperiod;
2564 -       u16 bs_cfpperiod;
2565 -       u16 bs_cfpmaxduration;
2566 -       u32 bs_cfpnext;
2567 -       u16 bs_timoffset;
2568         u16 bs_bmissthreshold;
2569         u32 bs_sleepduration;
2570         u32 bs_tsfoor_threshold;
2571 @@ -498,12 +486,6 @@ struct ath9k_hw_version {
2572
2573  #define AR_GENTMR_BIT(_index)  (1 << (_index))
2574
2575 -/*
2576 - * Using de Bruijin sequence to look up 1's index in a 32 bit number
2577 - * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
2578 - */
2579 -#define debruijn32 0x077CB531U
2580 -
2581  struct ath_gen_timer_configuration {
2582         u32 next_addr;
2583         u32 period_addr;
2584 @@ -519,12 +501,8 @@ struct ath_gen_timer {
2585  };
2586
2587  struct ath_gen_timer_table {
2588 -       u32 gen_timer_index[32];
2589         struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
2590 -       union {
2591 -               unsigned long timer_bits;
2592 -               u16 val;
2593 -       } timer_mask;
2594 +       u16 timer_mask;
2595  };
2596
2597  struct ath_hw_antcomb_conf {
2598 @@ -689,7 +667,8 @@ struct ath_hw_ops {
2599                           struct ath9k_channel *chan,
2600                           u8 rxchainmask,
2601                           bool longcal);
2602 -       bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked);
2603 +       bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked,
2604 +                       u32 *sync_cause_p);
2605         void (*set_txdesc)(struct ath_hw *ah, void *ds,
2606                            struct ath_tx_info *i);
2607         int (*proc_txdesc)(struct ath_hw *ah, void *ds,
2608 @@ -785,7 +764,6 @@ struct ath_hw {
2609         u32 txurn_interrupt_mask;
2610         atomic_t intr_ref_cnt;
2611         bool chip_fullsleep;
2612 -       u32 atim_window;
2613         u32 modes_index;
2614
2615         /* Calibration */
2616 @@ -864,6 +842,7 @@ struct ath_hw {
2617         u32 gpio_mask;
2618         u32 gpio_val;
2619
2620 +       struct ar5416IniArray ini_dfs;
2621         struct ar5416IniArray iniModes;
2622         struct ar5416IniArray iniCommon;
2623         struct ar5416IniArray iniBB_RfGain;
2624 @@ -920,7 +899,7 @@ struct ath_hw {
2625         /* Enterprise mode cap */
2626         u32 ent_mode;
2627
2628 -#ifdef CONFIG_PM_SLEEP
2629 +#ifdef CONFIG_ATH9K_WOW
2630         u32 wow_event_mask;
2631  #endif
2632         bool is_clk_25mhz;
2633 @@ -1016,13 +995,6 @@ bool ath9k_hw_check_alive(struct ath_hw
2634
2635  bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
2636
2637 -#ifdef CPTCFG_ATH9K_DEBUGFS
2638 -void ath9k_debug_sync_cause(struct ath_common *common, u32 sync_cause);
2639 -#else
2640 -static inline void ath9k_debug_sync_cause(struct ath_common *common,
2641 -                                         u32 sync_cause) {}
2642 -#endif
2643 -
2644  /* Generic hw timer primitives */
2645  struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2646                                           void (*trigger)(void *),
2647 @@ -1126,7 +1098,7 @@ ath9k_hw_get_btcoex_scheme(struct ath_hw
2648  #endif /* CPTCFG_ATH9K_BTCOEX_SUPPORT */
2649
2650
2651 -#ifdef CONFIG_PM_SLEEP
2652 +#ifdef CONFIG_ATH9K_WOW
2653  const char *ath9k_hw_wow_event_to_string(u32 wow_event);
2654  void ath9k_hw_wow_apply_pattern(struct ath_hw *ah, u8 *user_pattern,
2655                                 u8 *user_mask, int pattern_count,
2656 --- a/drivers/net/wireless/ath/ath9k/init.c
2657 +++ b/drivers/net/wireless/ath/ath9k/init.c
2658 @@ -470,7 +470,6 @@ static int ath9k_init_queues(struct ath_
2659
2660         sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah);
2661         sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
2662 -
2663         ath_cabq_update(sc);
2664
2665         sc->tx.uapsdq = ath_txq_setup(sc, ATH9K_TX_QUEUE_UAPSD, 0);
2666 @@ -554,7 +553,7 @@ static void ath9k_init_misc(struct ath_s
2667         sc->spec_config.fft_period = 0xF;
2668  }
2669
2670 -static void ath9k_init_platform(struct ath_softc *sc)
2671 +static void ath9k_init_pcoem_platform(struct ath_softc *sc)
2672  {
2673         struct ath_hw *ah = sc->sc_ah;
2674         struct ath9k_hw_capabilities *pCap = &ah->caps;
2675 @@ -609,6 +608,11 @@ static void ath9k_init_platform(struct a
2676                 ah->config.pcie_waen = 0x0040473b;
2677                 ath_info(common, "Enable WAR for ASPM D3/L1\n");
2678         }
2679 +
2680 +       if (sc->driver_data & ATH9K_PCI_NO_PLL_PWRSAVE) {
2681 +               ah->config.no_pll_pwrsave = true;
2682 +               ath_info(common, "Disable PLL PowerSave\n");
2683 +       }
2684  }
2685
2686  static void ath9k_eeprom_request_cb(const struct firmware *eeprom_blob,
2687 @@ -656,6 +660,27 @@ static void ath9k_eeprom_release(struct
2688         release_firmware(sc->sc_ah->eeprom_blob);
2689  }
2690
2691 +static int ath9k_init_soc_platform(struct ath_softc *sc)
2692 +{
2693 +       struct ath9k_platform_data *pdata = sc->dev->platform_data;
2694 +       struct ath_hw *ah = sc->sc_ah;
2695 +       int ret = 0;
2696 +
2697 +       if (!pdata)
2698 +               return 0;
2699 +
2700 +       if (pdata->eeprom_name) {
2701 +               ret = ath9k_eeprom_request(sc, pdata->eeprom_name);
2702 +               if (ret)
2703 +                       return ret;
2704 +       }
2705 +
2706 +       if (pdata->tx_gain_buffalo)
2707 +               ah->config.tx_gain_buffalo = true;
2708 +
2709 +       return ret;
2710 +}
2711 +
2712  static int ath9k_init_softc(u16 devid, struct ath_softc *sc,
2713                             const struct ath_bus_ops *bus_ops)
2714  {
2715 @@ -676,13 +701,13 @@ static int ath9k_init_softc(u16 devid, s
2716         ah->reg_ops.read = ath9k_ioread32;
2717         ah->reg_ops.write = ath9k_iowrite32;
2718         ah->reg_ops.rmw = ath9k_reg_rmw;
2719 -       atomic_set(&ah->intr_ref_cnt, -1);
2720         sc->sc_ah = ah;
2721         pCap = &ah->caps;
2722
2723         common = ath9k_hw_common(ah);
2724         sc->dfs_detector = dfs_pattern_detector_init(common, NL80211_DFS_UNSET);
2725         sc->tx99_power = MAX_RATE_POWER + 1;
2726 +       init_waitqueue_head(&sc->tx_wait);
2727
2728         if (!pdata) {
2729                 ah->ah_flags |= AH_USE_EEPROM;
2730 @@ -708,7 +733,11 @@ static int ath9k_init_softc(u16 devid, s
2731         /*
2732          * Platform quirks.
2733          */
2734 -       ath9k_init_platform(sc);
2735 +       ath9k_init_pcoem_platform(sc);
2736 +
2737 +       ret = ath9k_init_soc_platform(sc);
2738 +       if (ret)
2739 +               return ret;
2740
2741         /*
2742          * Enable WLAN/BT RX Antenna diversity only when:
2743 @@ -722,7 +751,6 @@ static int ath9k_init_softc(u16 devid, s
2744                 common->bt_ant_diversity = 1;
2745
2746         spin_lock_init(&common->cc_lock);
2747 -
2748         spin_lock_init(&sc->sc_serial_rw);
2749         spin_lock_init(&sc->sc_pm_lock);
2750         mutex_init(&sc->mutex);
2751 @@ -730,6 +758,7 @@ static int ath9k_init_softc(u16 devid, s
2752         tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
2753                      (unsigned long)sc);
2754
2755 +       setup_timer(&sc->sleep_timer, ath_ps_full_sleep, (unsigned long)sc);
2756         INIT_WORK(&sc->hw_reset_work, ath_reset_work);
2757         INIT_WORK(&sc->hw_check_work, ath_hw_check);
2758         INIT_WORK(&sc->paprd_work, ath_paprd_calibrate);
2759 @@ -743,12 +772,6 @@ static int ath9k_init_softc(u16 devid, s
2760         ath_read_cachesize(common, &csz);
2761         common->cachelsz = csz << 2; /* convert to bytes */
2762
2763 -       if (pdata && pdata->eeprom_name) {
2764 -               ret = ath9k_eeprom_request(sc, pdata->eeprom_name);
2765 -               if (ret)
2766 -                       return ret;
2767 -       }
2768 -
2769         /* Initializes the hardware for all supported chipsets */
2770         ret = ath9k_hw_init(ah);
2771         if (ret)
2772 @@ -845,7 +868,8 @@ static const struct ieee80211_iface_limi
2773  };
2774
2775  static const struct ieee80211_iface_limit if_dfs_limits[] = {
2776 -       { .max = 1,     .types = BIT(NL80211_IFTYPE_AP) },
2777 +       { .max = 1,     .types = BIT(NL80211_IFTYPE_AP) |
2778 +                                BIT(NL80211_IFTYPE_ADHOC) },
2779  };
2780
2781  static const struct ieee80211_iface_combination if_comb[] = {
2782 @@ -862,21 +886,12 @@ static const struct ieee80211_iface_comb
2783                 .max_interfaces = 1,
2784                 .num_different_channels = 1,
2785                 .beacon_int_infra_match = true,
2786 -               .radar_detect_widths =  BIT(NL80211_CHAN_NO_HT) |
2787 -                                       BIT(NL80211_CHAN_HT20),
2788 +               .radar_detect_widths =  BIT(NL80211_CHAN_WIDTH_20_NOHT) |
2789 +                                       BIT(NL80211_CHAN_WIDTH_20),
2790         }
2791  };
2792
2793 -#ifdef CONFIG_PM
2794 -static const struct wiphy_wowlan_support ath9k_wowlan_support = {
2795 -       .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT,
2796 -       .n_patterns = MAX_NUM_USER_PATTERN,
2797 -       .pattern_min_len = 1,
2798 -       .pattern_max_len = MAX_PATTERN_SIZE,
2799 -};
2800 -#endif
2801 -
2802 -void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
2803 +static void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
2804  {
2805         struct ath_hw *ah = sc->sc_ah;
2806         struct ath_common *common = ath9k_hw_common(ah);
2807 @@ -925,16 +940,6 @@ void ath9k_set_hw_capab(struct ath_softc
2808         hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_5_10_MHZ;
2809         hw->wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH;
2810
2811 -#ifdef CONFIG_PM_SLEEP
2812 -       if ((ah->caps.hw_caps & ATH9K_HW_WOW_DEVICE_CAPABLE) &&
2813 -           (sc->driver_data & ATH9K_PCI_WOW) &&
2814 -           device_can_wakeup(sc->dev))
2815 -               hw->wiphy->wowlan = &ath9k_wowlan_support;
2816 -
2817 -       atomic_set(&sc->wow_sleep_proc_intr, -1);
2818 -       atomic_set(&sc->wow_got_bmiss_intr, -1);
2819 -#endif
2820 -
2821         hw->queues = 4;
2822         hw->max_rates = 4;
2823         hw->channel_change_time = 5000;
2824 @@ -960,6 +965,7 @@ void ath9k_set_hw_capab(struct ath_softc
2825                 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
2826                         &sc->sbands[IEEE80211_BAND_5GHZ];
2827
2828 +       ath9k_init_wow(hw);
2829         ath9k_reload_chainmask_settings(sc);
2830
2831         SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
2832 @@ -1058,6 +1064,7 @@ static void ath9k_deinit_softc(struct at
2833                 if (ATH_TXQ_SETUP(sc, i))
2834                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
2835
2836 +       del_timer_sync(&sc->sleep_timer);
2837         ath9k_hw_deinit(sc->sc_ah);
2838         if (sc->dfs_detector != NULL)
2839                 sc->dfs_detector->exit(sc->dfs_detector);
2840 --- a/drivers/net/wireless/ath/ath9k/main.c
2841 +++ b/drivers/net/wireless/ath/ath9k/main.c
2842 @@ -82,6 +82,22 @@ static bool ath9k_setpower(struct ath_so
2843         return ret;
2844  }
2845
2846 +void ath_ps_full_sleep(unsigned long data)
2847 +{
2848 +       struct ath_softc *sc = (struct ath_softc *) data;
2849 +       struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2850 +       bool reset;
2851 +
2852 +       spin_lock(&common->cc_lock);
2853 +       ath_hw_cycle_counters_update(common);
2854 +       spin_unlock(&common->cc_lock);
2855 +
2856 +       ath9k_hw_setrxabort(sc->sc_ah, 1);
2857 +       ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
2858 +
2859 +       ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
2860 +}
2861 +
2862  void ath9k_ps_wakeup(struct ath_softc *sc)
2863  {
2864         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2865 @@ -92,6 +108,7 @@ void ath9k_ps_wakeup(struct ath_softc *s
2866         if (++sc->ps_usecount != 1)
2867                 goto unlock;
2868
2869 +       del_timer_sync(&sc->sleep_timer);
2870         power_mode = sc->sc_ah->power_mode;
2871         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
2872
2873 @@ -117,17 +134,17 @@ void ath9k_ps_restore(struct ath_softc *
2874         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2875         enum ath9k_power_mode mode;
2876         unsigned long flags;
2877 -       bool reset;
2878
2879         spin_lock_irqsave(&sc->sc_pm_lock, flags);
2880         if (--sc->ps_usecount != 0)
2881                 goto unlock;
2882
2883         if (sc->ps_idle) {
2884 -               ath9k_hw_setrxabort(sc->sc_ah, 1);
2885 -               ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
2886 -               mode = ATH9K_PM_FULL_SLEEP;
2887 -       } else if (sc->ps_enabled &&
2888 +               mod_timer(&sc->sleep_timer, jiffies + HZ / 10);
2889 +               goto unlock;
2890 +       }
2891 +
2892 +       if (sc->ps_enabled &&
2893                    !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
2894                                      PS_WAIT_FOR_CAB |
2895                                      PS_WAIT_FOR_PSPOLL_DATA |
2896 @@ -163,13 +180,13 @@ static void __ath_cancel_work(struct ath
2897  #endif
2898  }
2899
2900 -static void ath_cancel_work(struct ath_softc *sc)
2901 +void ath_cancel_work(struct ath_softc *sc)
2902  {
2903         __ath_cancel_work(sc);
2904         cancel_work_sync(&sc->hw_reset_work);
2905  }
2906
2907 -static void ath_restart_work(struct ath_softc *sc)
2908 +void ath_restart_work(struct ath_softc *sc)
2909  {
2910         ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
2911
2912 @@ -487,8 +504,13 @@ void ath9k_tasklet(unsigned long data)
2913                         ath_tx_edma_tasklet(sc);
2914                 else
2915                         ath_tx_tasklet(sc);
2916 +
2917 +               wake_up(&sc->tx_wait);
2918         }
2919
2920 +       if (status & ATH9K_INT_GENTIMER)
2921 +               ath_gen_timer_isr(sc->sc_ah);
2922 +
2923         ath9k_btcoex_handle_interrupt(sc, status);
2924
2925         /* re-enable hardware interrupt */
2926 @@ -519,6 +541,7 @@ irqreturn_t ath_isr(int irq, void *dev)
2927         struct ath_hw *ah = sc->sc_ah;
2928         struct ath_common *common = ath9k_hw_common(ah);
2929         enum ath9k_int status;
2930 +       u32 sync_cause;
2931         bool sched = false;
2932
2933         /*
2934 @@ -545,7 +568,8 @@ irqreturn_t ath_isr(int irq, void *dev)
2935          * bits we haven't explicitly enabled so we mask the
2936          * value to insure we only process bits we requested.
2937          */
2938 -       ath9k_hw_getisr(ah, &status);   /* NB: clears ISR too */
2939 +       ath9k_hw_getisr(ah, &status, &sync_cause); /* NB: clears ISR too */
2940 +       ath9k_debug_sync_cause(sc, sync_cause);
2941         status &= ah->imask;    /* discard unasked-for bits */
2942
2943         /*
2944 @@ -579,7 +603,8 @@ irqreturn_t ath_isr(int irq, void *dev)
2945
2946                 goto chip_reset;
2947         }
2948 -#ifdef CONFIG_PM_SLEEP
2949 +
2950 +#ifdef CONFIG_ATH9K_WOW
2951         if (status & ATH9K_INT_BMISS) {
2952                 if (atomic_read(&sc->wow_sleep_proc_intr) == 0) {
2953                         ath_dbg(common, ANY, "during WoW we got a BMISS\n");
2954 @@ -588,6 +613,8 @@ irqreturn_t ath_isr(int irq, void *dev)
2955                 }
2956         }
2957  #endif
2958 +
2959 +
2960         if (status & ATH9K_INT_SWBA)
2961                 tasklet_schedule(&sc->bcon_tasklet);
2962
2963 @@ -627,7 +654,7 @@ chip_reset:
2964  #undef SCHED_INTR
2965  }
2966
2967 -static int ath_reset(struct ath_softc *sc)
2968 +int ath_reset(struct ath_softc *sc)
2969  {
2970         int r;
2971
2972 @@ -735,6 +762,8 @@ static int ath9k_start(struct ieee80211_
2973          */
2974         ath9k_cmn_init_crypto(sc->sc_ah);
2975
2976 +       ath9k_hw_reset_tsf(ah);
2977 +
2978         spin_unlock_bh(&sc->sc_pcu_lock);
2979
2980         mutex_unlock(&sc->mutex);
2981 @@ -1635,13 +1664,8 @@ static void ath9k_bss_info_changed(struc
2982         }
2983
2984         if ((changed & BSS_CHANGED_BEACON_ENABLED) ||
2985 -           (changed & BSS_CHANGED_BEACON_INT)) {
2986 -               if (ah->opmode == NL80211_IFTYPE_AP &&
2987 -                   bss_conf->enable_beacon)
2988 -                       ath9k_set_tsfadjust(sc, vif);
2989 -               if (ath9k_allow_beacon_config(sc, vif))
2990 -                       ath9k_beacon_config(sc, vif, changed);
2991 -       }
2992 +           (changed & BSS_CHANGED_BEACON_INT))
2993 +               ath9k_beacon_config(sc, vif, changed);
2994
2995         if (changed & BSS_CHANGED_ERP_SLOT) {
2996                 if (bss_conf->use_short_slot)
2997 @@ -1817,13 +1841,31 @@ static void ath9k_set_coverage_class(str
2998         mutex_unlock(&sc->mutex);
2999  }
3000
3001 +static bool ath9k_has_tx_pending(struct ath_softc *sc)
3002 +{
3003 +       int i, npend;
3004 +
3005 +       for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
3006 +               if (!ATH_TXQ_SETUP(sc, i))
3007 +                       continue;
3008 +
3009 +               if (!sc->tx.txq[i].axq_depth)
3010 +                       continue;
3011 +
3012 +               npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
3013 +               if (npend)
3014 +                       break;
3015 +       }
3016 +
3017 +       return !!npend;
3018 +}
3019 +
3020  static void ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop)
3021  {
3022         struct ath_softc *sc = hw->priv;
3023         struct ath_hw *ah = sc->sc_ah;
3024         struct ath_common *common = ath9k_hw_common(ah);
3025 -       int timeout = 200; /* ms */
3026 -       int i, j;
3027 +       int timeout = HZ / 5; /* 200 ms */
3028         bool drain_txq;
3029
3030         mutex_lock(&sc->mutex);
3031 @@ -1841,25 +1883,9 @@ static void ath9k_flush(struct ieee80211
3032                 return;
3033         }
3034
3035 -       for (j = 0; j < timeout; j++) {
3036 -               bool npend = false;
3037 -
3038 -               if (j)
3039 -                       usleep_range(1000, 2000);
3040 -
3041 -               for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
3042 -                       if (!ATH_TXQ_SETUP(sc, i))
3043 -                               continue;
3044 -
3045 -                       npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
3046 -
3047 -                       if (npend)
3048 -                               break;
3049 -               }
3050 -
3051 -               if (!npend)
3052 -                   break;
3053 -       }
3054 +       if (wait_event_timeout(sc->tx_wait, !ath9k_has_tx_pending(sc),
3055 +                              timeout) > 0)
3056 +               drop = false;
3057
3058         if (drop) {
3059                 ath9k_ps_wakeup(sc);
3060 @@ -2021,333 +2047,6 @@ static int ath9k_get_antenna(struct ieee
3061         return 0;
3062  }
3063
3064 -#ifdef CONFIG_PM_SLEEP
3065 -
3066 -static void ath9k_wow_map_triggers(struct ath_softc *sc,
3067 -                                  struct cfg80211_wowlan *wowlan,
3068 -                                  u32 *wow_triggers)
3069 -{
3070 -       if (wowlan->disconnect)
3071 -               *wow_triggers |= AH_WOW_LINK_CHANGE |
3072 -                                AH_WOW_BEACON_MISS;
3073 -       if (wowlan->magic_pkt)
3074 -               *wow_triggers |= AH_WOW_MAGIC_PATTERN_EN;
3075 -
3076 -       if (wowlan->n_patterns)
3077 -               *wow_triggers |= AH_WOW_USER_PATTERN_EN;
3078 -
3079 -       sc->wow_enabled = *wow_triggers;
3080 -
3081 -}
3082 -
3083 -static void ath9k_wow_add_disassoc_deauth_pattern(struct ath_softc *sc)
3084 -{
3085 -       struct ath_hw *ah = sc->sc_ah;
3086 -       struct ath_common *common = ath9k_hw_common(ah);
3087 -       int pattern_count = 0;
3088 -       int i, byte_cnt;
3089 -       u8 dis_deauth_pattern[MAX_PATTERN_SIZE];
3090 -       u8 dis_deauth_mask[MAX_PATTERN_SIZE];
3091 -
3092 -       memset(dis_deauth_pattern, 0, MAX_PATTERN_SIZE);
3093 -       memset(dis_deauth_mask, 0, MAX_PATTERN_SIZE);
3094 -
3095 -       /*
3096 -        * Create Dissassociate / Deauthenticate packet filter
3097 -        *
3098 -        *     2 bytes        2 byte    6 bytes   6 bytes  6 bytes
3099 -        *  +--------------+----------+---------+--------+--------+----
3100 -        *  + Frame Control+ Duration +   DA    +  SA    +  BSSID +
3101 -        *  +--------------+----------+---------+--------+--------+----
3102 -        *
3103 -        * The above is the management frame format for disassociate/
3104 -        * deauthenticate pattern, from this we need to match the first byte
3105 -        * of 'Frame Control' and DA, SA, and BSSID fields
3106 -        * (skipping 2nd byte of FC and Duration feild.
3107 -        *
3108 -        * Disassociate pattern
3109 -        * --------------------
3110 -        * Frame control = 00 00 1010
3111 -        * DA, SA, BSSID = x:x:x:x:x:x
3112 -        * Pattern will be A0000000 | x:x:x:x:x:x | x:x:x:x:x:x
3113 -        *                          | x:x:x:x:x:x  -- 22 bytes
3114 -        *
3115 -        * Deauthenticate pattern
3116 -        * ----------------------
3117 -        * Frame control = 00 00 1100
3118 -        * DA, SA, BSSID = x:x:x:x:x:x
3119 -        * Pattern will be C0000000 | x:x:x:x:x:x | x:x:x:x:x:x
3120 -        *                          | x:x:x:x:x:x  -- 22 bytes
3121 -        */
3122 -
3123 -       /* Create Disassociate Pattern first */
3124 -
3125 -       byte_cnt = 0;
3126 -
3127 -       /* Fill out the mask with all FF's */
3128 -
3129 -       for (i = 0; i < MAX_PATTERN_MASK_SIZE; i++)
3130 -               dis_deauth_mask[i] = 0xff;
3131 -
3132 -       /* copy the first byte of frame control field */
3133 -       dis_deauth_pattern[byte_cnt] = 0xa0;
3134 -       byte_cnt++;
3135 -
3136 -       /* skip 2nd byte of frame control and Duration field */
3137 -       byte_cnt += 3;
3138 -
3139 -       /*
3140 -        * need not match the destination mac address, it can be a broadcast
3141 -        * mac address or an unicast to this station
3142 -        */
3143 -       byte_cnt += 6;
3144 -
3145 -       /* copy the source mac address */
3146 -       memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
3147 -
3148 -       byte_cnt += 6;
3149 -
3150 -       /* copy the bssid, its same as the source mac address */
3151 -
3152 -       memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
3153 -
3154 -       /* Create Disassociate pattern mask */
3155 -
3156 -       dis_deauth_mask[0] = 0xfe;
3157 -       dis_deauth_mask[1] = 0x03;
3158 -       dis_deauth_mask[2] = 0xc0;
3159 -
3160 -       ath_dbg(common, WOW, "Adding disassoc/deauth patterns for WoW\n");
3161 -
3162 -       ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
3163 -                                  pattern_count, byte_cnt);
3164 -
3165 -       pattern_count++;
3166 -       /*
3167 -        * for de-authenticate pattern, only the first byte of the frame
3168 -        * control field gets changed from 0xA0 to 0xC0
3169 -        */
3170 -       dis_deauth_pattern[0] = 0xC0;
3171 -
3172 -       ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
3173 -                                  pattern_count, byte_cnt);
3174 -
3175 -}
3176 -
3177 -static void ath9k_wow_add_pattern(struct ath_softc *sc,
3178 -                                 struct cfg80211_wowlan *wowlan)
3179 -{
3180 -       struct ath_hw *ah = sc->sc_ah;
3181 -       struct ath9k_wow_pattern *wow_pattern = NULL;
3182 -       struct cfg80211_pkt_pattern *patterns = wowlan->patterns;
3183 -       int mask_len;
3184 -       s8 i = 0;
3185 -
3186 -       if (!wowlan->n_patterns)
3187 -               return;
3188 -
3189 -       /*
3190 -        * Add the new user configured patterns
3191 -        */
3192 -       for (i = 0; i < wowlan->n_patterns; i++) {
3193 -
3194 -               wow_pattern = kzalloc(sizeof(*wow_pattern), GFP_KERNEL);
3195 -
3196 -               if (!wow_pattern)
3197 -                       return;
3198 -
3199 -               /*
3200 -                * TODO: convert the generic user space pattern to
3201 -                * appropriate chip specific/802.11 pattern.
3202 -                */
3203 -
3204 -               mask_len = DIV_ROUND_UP(wowlan->patterns[i].pattern_len, 8);
3205 -               memset(wow_pattern->pattern_bytes, 0, MAX_PATTERN_SIZE);
3206 -               memset(wow_pattern->mask_bytes, 0, MAX_PATTERN_SIZE);
3207 -               memcpy(wow_pattern->pattern_bytes, patterns[i].pattern,
3208 -                      patterns[i].pattern_len);
3209 -               memcpy(wow_pattern->mask_bytes, patterns[i].mask, mask_len);
3210 -               wow_pattern->pattern_len = patterns[i].pattern_len;
3211 -
3212 -               /*
3213 -                * just need to take care of deauth and disssoc pattern,
3214 -                * make sure we don't overwrite them.
3215 -                */
3216 -
3217 -               ath9k_hw_wow_apply_pattern(ah, wow_pattern->pattern_bytes,
3218 -                                          wow_pattern->mask_bytes,
3219 -                                          i + 2,
3220 -                                          wow_pattern->pattern_len);
3221 -               kfree(wow_pattern);
3222 -
3223 -       }
3224 -
3225 -}
3226 -
3227 -static int ath9k_suspend(struct ieee80211_hw *hw,
3228 -                        struct cfg80211_wowlan *wowlan)
3229 -{
3230 -       struct ath_softc *sc = hw->priv;
3231 -       struct ath_hw *ah = sc->sc_ah;
3232 -       struct ath_common *common = ath9k_hw_common(ah);
3233 -       u32 wow_triggers_enabled = 0;
3234 -       int ret = 0;
3235 -
3236 -       mutex_lock(&sc->mutex);
3237 -
3238 -       ath_cancel_work(sc);
3239 -       ath_stop_ani(sc);
3240 -       del_timer_sync(&sc->rx_poll_timer);
3241 -
3242 -       if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
3243 -               ath_dbg(common, ANY, "Device not present\n");
3244 -               ret = -EINVAL;
3245 -               goto fail_wow;
3246 -       }
3247 -
3248 -       if (WARN_ON(!wowlan)) {
3249 -               ath_dbg(common, WOW, "None of the WoW triggers enabled\n");
3250 -               ret = -EINVAL;
3251 -               goto fail_wow;
3252 -       }
3253 -
3254 -       if (!device_can_wakeup(sc->dev)) {
3255 -               ath_dbg(common, WOW, "device_can_wakeup failed, WoW is not enabled\n");
3256 -               ret = 1;
3257 -               goto fail_wow;
3258 -       }
3259 -
3260 -       /*
3261 -        * none of the sta vifs are associated
3262 -        * and we are not currently handling multivif
3263 -        * cases, for instance we have to seperately
3264 -        * configure 'keep alive frame' for each
3265 -        * STA.
3266 -        */
3267 -
3268 -       if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
3269 -               ath_dbg(common, WOW, "None of the STA vifs are associated\n");
3270 -               ret = 1;
3271 -               goto fail_wow;
3272 -       }
3273 -
3274 -       if (sc->nvifs > 1) {
3275 -               ath_dbg(common, WOW, "WoW for multivif is not yet supported\n");
3276 -               ret = 1;
3277 -               goto fail_wow;
3278 -       }
3279 -
3280 -       ath9k_wow_map_triggers(sc, wowlan, &wow_triggers_enabled);
3281 -
3282 -       ath_dbg(common, WOW, "WoW triggers enabled 0x%x\n",
3283 -               wow_triggers_enabled);
3284 -
3285 -       ath9k_ps_wakeup(sc);
3286 -
3287 -       ath9k_stop_btcoex(sc);
3288 -
3289 -       /*
3290 -        * Enable wake up on recieving disassoc/deauth
3291 -        * frame by default.
3292 -        */
3293 -       ath9k_wow_add_disassoc_deauth_pattern(sc);
3294 -
3295 -       if (wow_triggers_enabled & AH_WOW_USER_PATTERN_EN)
3296 -               ath9k_wow_add_pattern(sc, wowlan);
3297 -
3298 -       spin_lock_bh(&sc->sc_pcu_lock);
3299 -       /*
3300 -        * To avoid false wake, we enable beacon miss interrupt only
3301 -        * when we go to sleep. We save the current interrupt mask
3302 -        * so we can restore it after the system wakes up
3303 -        */
3304 -       sc->wow_intr_before_sleep = ah->imask;
3305 -       ah->imask &= ~ATH9K_INT_GLOBAL;
3306 -       ath9k_hw_disable_interrupts(ah);
3307 -       ah->imask = ATH9K_INT_BMISS | ATH9K_INT_GLOBAL;
3308 -       ath9k_hw_set_interrupts(ah);
3309 -       ath9k_hw_enable_interrupts(ah);
3310 -
3311 -       spin_unlock_bh(&sc->sc_pcu_lock);
3312 -
3313 -       /*
3314 -        * we can now sync irq and kill any running tasklets, since we already
3315 -        * disabled interrupts and not holding a spin lock
3316 -        */
3317 -       synchronize_irq(sc->irq);
3318 -       tasklet_kill(&sc->intr_tq);
3319 -
3320 -       ath9k_hw_wow_enable(ah, wow_triggers_enabled);
3321 -
3322 -       ath9k_ps_restore(sc);
3323 -       ath_dbg(common, ANY, "WoW enabled in ath9k\n");
3324 -       atomic_inc(&sc->wow_sleep_proc_intr);
3325 -
3326 -fail_wow:
3327 -       mutex_unlock(&sc->mutex);
3328 -       return ret;
3329 -}
3330 -
3331 -static int ath9k_resume(struct ieee80211_hw *hw)
3332 -{
3333 -       struct ath_softc *sc = hw->priv;
3334 -       struct ath_hw *ah = sc->sc_ah;
3335 -       struct ath_common *common = ath9k_hw_common(ah);
3336 -       u32 wow_status;
3337 -
3338 -       mutex_lock(&sc->mutex);
3339 -
3340 -       ath9k_ps_wakeup(sc);
3341 -
3342 -       spin_lock_bh(&sc->sc_pcu_lock);
3343 -
3344 -       ath9k_hw_disable_interrupts(ah);
3345 -       ah->imask = sc->wow_intr_before_sleep;
3346 -       ath9k_hw_set_interrupts(ah);
3347 -       ath9k_hw_enable_interrupts(ah);
3348 -
3349 -       spin_unlock_bh(&sc->sc_pcu_lock);
3350 -
3351 -       wow_status = ath9k_hw_wow_wakeup(ah);
3352 -
3353 -       if (atomic_read(&sc->wow_got_bmiss_intr) == 0) {
3354 -               /*
3355 -                * some devices may not pick beacon miss
3356 -                * as the reason they woke up so we add
3357 -                * that here for that shortcoming.
3358 -                */
3359 -               wow_status |= AH_WOW_BEACON_MISS;
3360 -               atomic_dec(&sc->wow_got_bmiss_intr);
3361 -               ath_dbg(common, ANY, "Beacon miss interrupt picked up during WoW sleep\n");
3362 -       }
3363 -
3364 -       atomic_dec(&sc->wow_sleep_proc_intr);
3365 -
3366 -       if (wow_status) {
3367 -               ath_dbg(common, ANY, "Waking up due to WoW triggers %s with WoW status = %x\n",
3368 -                       ath9k_hw_wow_event_to_string(wow_status), wow_status);
3369 -       }
3370 -
3371 -       ath_restart_work(sc);
3372 -       ath9k_start_btcoex(sc);
3373 -
3374 -       ath9k_ps_restore(sc);
3375 -       mutex_unlock(&sc->mutex);
3376 -
3377 -       return 0;
3378 -}
3379 -
3380 -static void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled)
3381 -{
3382 -       struct ath_softc *sc = hw->priv;
3383 -
3384 -       mutex_lock(&sc->mutex);
3385 -       device_init_wakeup(sc->dev, 1);
3386 -       device_set_wakeup_enable(sc->dev, enabled);
3387 -       mutex_unlock(&sc->mutex);
3388 -}
3389 -
3390 -#endif
3391  static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
3392  {
3393         struct ath_softc *sc = hw->priv;
3394 @@ -2373,134 +2072,6 @@ static void ath9k_channel_switch_beacon(
3395         sc->csa_vif = vif;
3396  }
3397
3398 -static void ath9k_tx99_stop(struct ath_softc *sc)
3399 -{
3400 -       struct ath_hw *ah = sc->sc_ah;
3401 -       struct ath_common *common = ath9k_hw_common(ah);
3402 -
3403 -       ath_drain_all_txq(sc);
3404 -       ath_startrecv(sc);
3405 -
3406 -       ath9k_hw_set_interrupts(ah);
3407 -       ath9k_hw_enable_interrupts(ah);
3408 -
3409 -       ieee80211_wake_queues(sc->hw);
3410 -
3411 -       kfree_skb(sc->tx99_skb);
3412 -       sc->tx99_skb = NULL;
3413 -       sc->tx99_state = false;
3414 -
3415 -       ath9k_hw_tx99_stop(sc->sc_ah);
3416 -       ath_dbg(common, XMIT, "TX99 stopped\n");
3417 -}
3418 -
3419 -static struct sk_buff *ath9k_build_tx99_skb(struct ath_softc *sc)
3420 -{
3421 -       static u8 PN9Data[] = {0xff, 0x87, 0xb8, 0x59, 0xb7, 0xa1, 0xcc, 0x24,
3422 -                              0x57, 0x5e, 0x4b, 0x9c, 0x0e, 0xe9, 0xea, 0x50,
3423 -                              0x2a, 0xbe, 0xb4, 0x1b, 0xb6, 0xb0, 0x5d, 0xf1,
3424 -                              0xe6, 0x9a, 0xe3, 0x45, 0xfd, 0x2c, 0x53, 0x18,
3425 -                              0x0c, 0xca, 0xc9, 0xfb, 0x49, 0x37, 0xe5, 0xa8,
3426 -                              0x51, 0x3b, 0x2f, 0x61, 0xaa, 0x72, 0x18, 0x84,
3427 -                              0x02, 0x23, 0x23, 0xab, 0x63, 0x89, 0x51, 0xb3,
3428 -                              0xe7, 0x8b, 0x72, 0x90, 0x4c, 0xe8, 0xfb, 0xc0};
3429 -       u32 len = 1200;
3430 -       struct ieee80211_hw *hw = sc->hw;
3431 -       struct ieee80211_hdr *hdr;
3432 -       struct ieee80211_tx_info *tx_info;
3433 -       struct sk_buff *skb;
3434 -
3435 -       skb = alloc_skb(len, GFP_KERNEL);
3436 -       if (!skb)
3437 -               return NULL;
3438 -
3439 -       skb_put(skb, len);
3440 -
3441 -       memset(skb->data, 0, len);
3442 -
3443 -       hdr = (struct ieee80211_hdr *)skb->data;
3444 -       hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_DATA);
3445 -       hdr->duration_id = 0;
3446 -
3447 -       memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN);
3448 -       memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN);
3449 -       memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);
3450 -
3451 -       hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
3452 -
3453 -       tx_info = IEEE80211_SKB_CB(skb);
3454 -       memset(tx_info, 0, sizeof(*tx_info));
3455 -       tx_info->band = hw->conf.chandef.chan->band;
3456 -       tx_info->flags = IEEE80211_TX_CTL_NO_ACK;
3457 -       tx_info->control.vif = sc->tx99_vif;
3458 -
3459 -       memcpy(skb->data + sizeof(*hdr), PN9Data, sizeof(PN9Data));
3460 -
3461 -       return skb;
3462 -}
3463 -
3464 -void ath9k_tx99_deinit(struct ath_softc *sc)
3465 -{
3466 -       ath_reset(sc);
3467 -
3468 -       ath9k_ps_wakeup(sc);
3469 -       ath9k_tx99_stop(sc);
3470 -       ath9k_ps_restore(sc);
3471 -}
3472 -
3473 -int ath9k_tx99_init(struct ath_softc *sc)
3474 -{
3475 -       struct ieee80211_hw *hw = sc->hw;
3476 -       struct ath_hw *ah = sc->sc_ah;
3477 -       struct ath_common *common = ath9k_hw_common(ah);
3478 -       struct ath_tx_control txctl;
3479 -       int r;
3480 -
3481 -       if (sc->sc_flags & SC_OP_INVALID) {
3482 -               ath_err(common,
3483 -                       "driver is in invalid state unable to use TX99");
3484 -               return -EINVAL;
3485 -       }
3486 -
3487 -       sc->tx99_skb = ath9k_build_tx99_skb(sc);
3488 -       if (!sc->tx99_skb)
3489 -               return -ENOMEM;
3490 -
3491 -       memset(&txctl, 0, sizeof(txctl));
3492 -       txctl.txq = sc->tx.txq_map[IEEE80211_AC_VO];
3493 -
3494 -       ath_reset(sc);
3495 -
3496 -       ath9k_ps_wakeup(sc);
3497 -
3498 -       ath9k_hw_disable_interrupts(ah);
3499 -       atomic_set(&ah->intr_ref_cnt, -1);
3500 -       ath_drain_all_txq(sc);
3501 -       ath_stoprecv(sc);
3502 -
3503 -       sc->tx99_state = true;
3504 -
3505 -       ieee80211_stop_queues(hw);
3506 -
3507 -       if (sc->tx99_power == MAX_RATE_POWER + 1)
3508 -               sc->tx99_power = MAX_RATE_POWER;
3509 -
3510 -       ath9k_hw_tx99_set_txpower(ah, sc->tx99_power);
3511 -       r = ath9k_tx99_send(sc, sc->tx99_skb, &txctl);
3512 -       if (r) {
3513 -               ath_dbg(common, XMIT, "Failed to xmit TX99 skb\n");
3514 -               return r;
3515 -       }
3516 -
3517 -       ath_dbg(common, XMIT, "TX99 xmit started using %d ( %ddBm)\n",
3518 -               sc->tx99_power,
3519 -               sc->tx99_power / 2);
3520 -
3521 -       /* We leave the harware awake as it will be chugging on */
3522 -
3523 -       return 0;
3524 -}
3525 -
3526  struct ieee80211_ops ath9k_ops = {
3527         .tx                 = ath9k_tx,
3528         .start              = ath9k_start,
3529 @@ -2531,7 +2102,7 @@ struct ieee80211_ops ath9k_ops = {
3530         .set_antenna        = ath9k_set_antenna,
3531         .get_antenna        = ath9k_get_antenna,
3532
3533 -#ifdef CONFIG_PM_SLEEP
3534 +#ifdef CONFIG_ATH9K_WOW
3535         .suspend            = ath9k_suspend,
3536         .resume             = ath9k_resume,
3537         .set_wakeup         = ath9k_set_wakeup,
3538 --- a/drivers/net/wireless/ath/ath9k/wow.c
3539 +++ b/drivers/net/wireless/ath/ath9k/wow.c
3540 @@ -1,5 +1,5 @@
3541  /*
3542 - * Copyright (c) 2012 Qualcomm Atheros, Inc.
3543 + * Copyright (c) 2013 Qualcomm Atheros, Inc.
3544   *
3545   * Permission to use, copy, modify, and/or distribute this software for any
3546   * purpose with or without fee is hereby granted, provided that the above
3547 @@ -14,409 +14,348 @@
3548   * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
3549   */
3550
3551 -#include <linux/export.h>
3552  #include "ath9k.h"
3553 -#include "reg.h"
3554 -#include "hw-ops.h"
3555
3556 -const char *ath9k_hw_wow_event_to_string(u32 wow_event)
3557 +static const struct wiphy_wowlan_support ath9k_wowlan_support = {
3558 +       .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT,
3559 +       .n_patterns = MAX_NUM_USER_PATTERN,
3560 +       .pattern_min_len = 1,
3561 +       .pattern_max_len = MAX_PATTERN_SIZE,
3562 +};
3563 +
3564 +static void ath9k_wow_map_triggers(struct ath_softc *sc,
3565 +                                  struct cfg80211_wowlan *wowlan,
3566 +                                  u32 *wow_triggers)
3567  {
3568 -       if (wow_event & AH_WOW_MAGIC_PATTERN_EN)
3569 -               return "Magic pattern";
3570 -       if (wow_event & AH_WOW_USER_PATTERN_EN)
3571 -               return "User pattern";
3572 -       if (wow_event & AH_WOW_LINK_CHANGE)
3573 -               return "Link change";
3574 -       if (wow_event & AH_WOW_BEACON_MISS)
3575 -               return "Beacon miss";
3576 +       if (wowlan->disconnect)
3577 +               *wow_triggers |= AH_WOW_LINK_CHANGE |
3578 +                                AH_WOW_BEACON_MISS;
3579 +       if (wowlan->magic_pkt)
3580 +               *wow_triggers |= AH_WOW_MAGIC_PATTERN_EN;
3581 +
3582 +       if (wowlan->n_patterns)
3583 +               *wow_triggers |= AH_WOW_USER_PATTERN_EN;
3584 +
3585 +       sc->wow_enabled = *wow_triggers;
3586
3587 -       return  "unknown reason";
3588  }
3589 -EXPORT_SYMBOL(ath9k_hw_wow_event_to_string);
3590
3591 -static void ath9k_hw_set_powermode_wow_sleep(struct ath_hw *ah)
3592 +static void ath9k_wow_add_disassoc_deauth_pattern(struct ath_softc *sc)
3593  {
3594 +       struct ath_hw *ah = sc->sc_ah;
3595         struct ath_common *common = ath9k_hw_common(ah);
3596 +       int pattern_count = 0;
3597 +       int i, byte_cnt;
3598 +       u8 dis_deauth_pattern[MAX_PATTERN_SIZE];
3599 +       u8 dis_deauth_mask[MAX_PATTERN_SIZE];
3600
3601 -       REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
3602 +       memset(dis_deauth_pattern, 0, MAX_PATTERN_SIZE);
3603 +       memset(dis_deauth_mask, 0, MAX_PATTERN_SIZE);
3604
3605 -       /* set rx disable bit */
3606 -       REG_WRITE(ah, AR_CR, AR_CR_RXD);
3607 +       /*
3608 +        * Create Dissassociate / Deauthenticate packet filter
3609 +        *
3610 +        *     2 bytes        2 byte    6 bytes   6 bytes  6 bytes
3611 +        *  +--------------+----------+---------+--------+--------+----
3612 +        *  + Frame Control+ Duration +   DA    +  SA    +  BSSID +
3613 +        *  +--------------+----------+---------+--------+--------+----
3614 +        *
3615 +        * The above is the management frame format for disassociate/
3616 +        * deauthenticate pattern, from this we need to match the first byte
3617 +        * of 'Frame Control' and DA, SA, and BSSID fields
3618 +        * (skipping 2nd byte of FC and Duration feild.
3619 +        *
3620 +        * Disassociate pattern
3621 +        * --------------------
3622 +        * Frame control = 00 00 1010
3623 +        * DA, SA, BSSID = x:x:x:x:x:x
3624 +        * Pattern will be A0000000 | x:x:x:x:x:x | x:x:x:x:x:x
3625 +        *                          | x:x:x:x:x:x  -- 22 bytes
3626 +        *
3627 +        * Deauthenticate pattern
3628 +        * ----------------------
3629 +        * Frame control = 00 00 1100
3630 +        * DA, SA, BSSID = x:x:x:x:x:x
3631 +        * Pattern will be C0000000 | x:x:x:x:x:x | x:x:x:x:x:x
3632 +        *                          | x:x:x:x:x:x  -- 22 bytes
3633 +        */
3634
3635 -       if (!ath9k_hw_wait(ah, AR_CR, AR_CR_RXE, 0, AH_WAIT_TIMEOUT)) {
3636 -               ath_err(common, "Failed to stop Rx DMA in 10ms AR_CR=0x%08x AR_DIAG_SW=0x%08x\n",
3637 -                       REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW));
3638 -               return;
3639 -       }
3640 +       /* Create Disassociate Pattern first */
3641
3642 -       REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_ON_INT);
3643 -}
3644 +       byte_cnt = 0;
3645
3646 -static void ath9k_wow_create_keep_alive_pattern(struct ath_hw *ah)
3647 -{
3648 -       struct ath_common *common = ath9k_hw_common(ah);
3649 -       u8 sta_mac_addr[ETH_ALEN], ap_mac_addr[ETH_ALEN];
3650 -       u32 ctl[13] = {0};
3651 -       u32 data_word[KAL_NUM_DATA_WORDS];
3652 -       u8 i;
3653 -       u32 wow_ka_data_word0;
3654 -
3655 -       memcpy(sta_mac_addr, common->macaddr, ETH_ALEN);
3656 -       memcpy(ap_mac_addr, common->curbssid, ETH_ALEN);
3657 -
3658 -       /* set the transmit buffer */
3659 -       ctl[0] = (KAL_FRAME_LEN | (MAX_RATE_POWER << 16));
3660 -       ctl[1] = 0;
3661 -       ctl[3] = 0xb;   /* OFDM_6M hardware value for this rate */
3662 -       ctl[4] = 0;
3663 -       ctl[7] = (ah->txchainmask) << 2;
3664 -       ctl[2] = 0xf << 16; /* tx_tries 0 */
3665 -
3666 -       for (i = 0; i < KAL_NUM_DESC_WORDS; i++)
3667 -               REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + i * 4), ctl[i]);
3668 -
3669 -       REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + i * 4), ctl[i]);
3670 -
3671 -       data_word[0] = (KAL_FRAME_TYPE << 2) | (KAL_FRAME_SUB_TYPE << 4) |
3672 -                      (KAL_TO_DS << 8) | (KAL_DURATION_ID << 16);
3673 -       data_word[1] = (ap_mac_addr[3] << 24) | (ap_mac_addr[2] << 16) |
3674 -                      (ap_mac_addr[1] << 8) | (ap_mac_addr[0]);
3675 -       data_word[2] = (sta_mac_addr[1] << 24) | (sta_mac_addr[0] << 16) |
3676 -                      (ap_mac_addr[5] << 8) | (ap_mac_addr[4]);
3677 -       data_word[3] = (sta_mac_addr[5] << 24) | (sta_mac_addr[4] << 16) |
3678 -                      (sta_mac_addr[3] << 8) | (sta_mac_addr[2]);
3679 -       data_word[4] = (ap_mac_addr[3] << 24) | (ap_mac_addr[2] << 16) |
3680 -                      (ap_mac_addr[1] << 8) | (ap_mac_addr[0]);
3681 -       data_word[5] = (ap_mac_addr[5] << 8) | (ap_mac_addr[4]);
3682 -
3683 -       if (AR_SREV_9462_20(ah)) {
3684 -               /* AR9462 2.0 has an extra descriptor word (time based
3685 -                * discard) compared to other chips */
3686 -               REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + (12 * 4)), 0);
3687 -               wow_ka_data_word0 = AR_WOW_TXBUF(13);
3688 -       } else {
3689 -               wow_ka_data_word0 = AR_WOW_TXBUF(12);
3690 -       }
3691 +       /* Fill out the mask with all FF's */
3692
3693 -       for (i = 0; i < KAL_NUM_DATA_WORDS; i++)
3694 -               REG_WRITE(ah, (wow_ka_data_word0 + i*4), data_word[i]);
3695 +       for (i = 0; i < MAX_PATTERN_MASK_SIZE; i++)
3696 +               dis_deauth_mask[i] = 0xff;
3697
3698 -}
3699 +       /* copy the first byte of frame control field */
3700 +       dis_deauth_pattern[byte_cnt] = 0xa0;
3701 +       byte_cnt++;
3702
3703 -void ath9k_hw_wow_apply_pattern(struct ath_hw *ah, u8 *user_pattern,
3704 -                               u8 *user_mask, int pattern_count,
3705 -                               int pattern_len)
3706 -{
3707 -       int i;
3708 -       u32 pattern_val, mask_val;
3709 -       u32 set, clr;
3710 +       /* skip 2nd byte of frame control and Duration field */
3711 +       byte_cnt += 3;
3712
3713 -       /* FIXME: should check count by querying the hardware capability */
3714 -       if (pattern_count >= MAX_NUM_PATTERN)
3715 -               return;
3716 +       /*
3717 +        * need not match the destination mac address, it can be a broadcast
3718 +        * mac address or an unicast to this station
3719 +        */
3720 +       byte_cnt += 6;
3721
3722 -       REG_SET_BIT(ah, AR_WOW_PATTERN, BIT(pattern_count));
3723 +       /* copy the source mac address */
3724 +       memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
3725
3726 -       /* set the registers for pattern */
3727 -       for (i = 0; i < MAX_PATTERN_SIZE; i += 4) {
3728 -               memcpy(&pattern_val, user_pattern, 4);
3729 -               REG_WRITE(ah, (AR_WOW_TB_PATTERN(pattern_count) + i),
3730 -                         pattern_val);
3731 -               user_pattern += 4;
3732 -       }
3733 +       byte_cnt += 6;
3734
3735 -       /* set the registers for mask */
3736 -       for (i = 0; i < MAX_PATTERN_MASK_SIZE; i += 4) {
3737 -               memcpy(&mask_val, user_mask, 4);
3738 -               REG_WRITE(ah, (AR_WOW_TB_MASK(pattern_count) + i), mask_val);
3739 -               user_mask += 4;
3740 -       }
3741 +       /* copy the bssid, its same as the source mac address */
3742
3743 -       /* set the pattern length to be matched
3744 -        *
3745 -        * AR_WOW_LENGTH1_REG1
3746 -        * bit 31:24 pattern 0 length
3747 -        * bit 23:16 pattern 1 length
3748 -        * bit 15:8 pattern 2 length
3749 -        * bit 7:0 pattern 3 length
3750 -        *
3751 -        * AR_WOW_LENGTH1_REG2
3752 -        * bit 31:24 pattern 4 length
3753 -        * bit 23:16 pattern 5 length
3754 -        * bit 15:8 pattern 6 length
3755 -        * bit 7:0 pattern 7 length
3756 -        *
3757 -        * the below logic writes out the new
3758 -        * pattern length for the corresponding
3759 -        * pattern_count, while masking out the
3760 -        * other fields
3761 -        */
3762 +       memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
3763
3764 -       ah->wow_event_mask |= BIT(pattern_count + AR_WOW_PAT_FOUND_SHIFT);
3765 +       /* Create Disassociate pattern mask */
3766
3767 -       if (pattern_count < 4) {
3768 -               /* Pattern 0-3 uses AR_WOW_LENGTH1 register */
3769 -               set = (pattern_len & AR_WOW_LENGTH_MAX) <<
3770 -                      AR_WOW_LEN1_SHIFT(pattern_count);
3771 -               clr = AR_WOW_LENGTH1_MASK(pattern_count);
3772 -               REG_RMW(ah, AR_WOW_LENGTH1, set, clr);
3773 -       } else {
3774 -               /* Pattern 4-7 uses AR_WOW_LENGTH2 register */
3775 -               set = (pattern_len & AR_WOW_LENGTH_MAX) <<
3776 -                      AR_WOW_LEN2_SHIFT(pattern_count);
3777 -               clr = AR_WOW_LENGTH2_MASK(pattern_count);
3778 -               REG_RMW(ah, AR_WOW_LENGTH2, set, clr);
3779 -       }
3780 +       dis_deauth_mask[0] = 0xfe;
3781 +       dis_deauth_mask[1] = 0x03;
3782 +       dis_deauth_mask[2] = 0xc0;
3783
3784 -}
3785 -EXPORT_SYMBOL(ath9k_hw_wow_apply_pattern);
3786 +       ath_dbg(common, WOW, "Adding disassoc/deauth patterns for WoW\n");
3787
3788 -u32 ath9k_hw_wow_wakeup(struct ath_hw *ah)
3789 -{
3790 -       u32 wow_status = 0;
3791 -       u32 val = 0, rval;
3792 +       ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
3793 +                                  pattern_count, byte_cnt);
3794
3795 +       pattern_count++;
3796         /*
3797 -        * read the WoW status register to know
3798 -        * the wakeup reason
3799 +        * for de-authenticate pattern, only the first byte of the frame
3800 +        * control field gets changed from 0xA0 to 0xC0
3801          */
3802 -       rval = REG_READ(ah, AR_WOW_PATTERN);
3803 -       val = AR_WOW_STATUS(rval);
3804 +       dis_deauth_pattern[0] = 0xC0;
3805
3806 -       /*
3807 -        * mask only the WoW events that we have enabled. Sometimes
3808 -        * we have spurious WoW events from the AR_WOW_PATTERN
3809 -        * register. This mask will clean it up.
3810 -        */
3811 +       ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
3812 +                                  pattern_count, byte_cnt);
3813
3814 -       val &= ah->wow_event_mask;
3815 +}
3816
3817 -       if (val) {
3818 -               if (val & AR_WOW_MAGIC_PAT_FOUND)
3819 -                       wow_status |= AH_WOW_MAGIC_PATTERN_EN;
3820 -               if (AR_WOW_PATTERN_FOUND(val))
3821 -                       wow_status |= AH_WOW_USER_PATTERN_EN;
3822 -               if (val & AR_WOW_KEEP_ALIVE_FAIL)
3823 -                       wow_status |= AH_WOW_LINK_CHANGE;
3824 -               if (val & AR_WOW_BEACON_FAIL)
3825 -                       wow_status |= AH_WOW_BEACON_MISS;
3826 -       }
3827 +static void ath9k_wow_add_pattern(struct ath_softc *sc,
3828 +                                 struct cfg80211_wowlan *wowlan)
3829 +{
3830 +       struct ath_hw *ah = sc->sc_ah;
3831 +       struct ath9k_wow_pattern *wow_pattern = NULL;
3832 +       struct cfg80211_pkt_pattern *patterns = wowlan->patterns;
3833 +       int mask_len;
3834 +       s8 i = 0;
3835 +
3836 +       if (!wowlan->n_patterns)
3837 +               return;
3838
3839         /*
3840 -        * set and clear WOW_PME_CLEAR registers for the chip to
3841 -        * generate next wow signal.
3842 -        * disable D3 before accessing other registers ?
3843 +        * Add the new user configured patterns
3844          */
3845 +       for (i = 0; i < wowlan->n_patterns; i++) {
3846
3847 -       /* do we need to check the bit value 0x01000000 (7-10) ?? */
3848 -       REG_RMW(ah, AR_PCIE_PM_CTRL, AR_PMCTRL_WOW_PME_CLR,
3849 -               AR_PMCTRL_PWR_STATE_D1D3);
3850 +               wow_pattern = kzalloc(sizeof(*wow_pattern), GFP_KERNEL);
3851
3852 -       /*
3853 -        * clear all events
3854 -        */
3855 -       REG_WRITE(ah, AR_WOW_PATTERN,
3856 -                 AR_WOW_CLEAR_EVENTS(REG_READ(ah, AR_WOW_PATTERN)));
3857 +               if (!wow_pattern)
3858 +                       return;
3859
3860 -       /*
3861 -        * restore the beacon threshold to init value
3862 -        */
3863 -       REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
3864 +               /*
3865 +                * TODO: convert the generic user space pattern to
3866 +                * appropriate chip specific/802.11 pattern.
3867 +                */
3868
3869 -       /*
3870 -        * Restore the way the PCI-E reset, Power-On-Reset, external
3871 -        * PCIE_POR_SHORT pins are tied to its original value.
3872 -        * Previously just before WoW sleep, we untie the PCI-E
3873 -        * reset to our Chip's Power On Reset so that any PCI-E
3874 -        * reset from the bus will not reset our chip
3875 -        */
3876 -       if (ah->is_pciexpress)
3877 -               ath9k_hw_configpcipowersave(ah, false);
3878 +               mask_len = DIV_ROUND_UP(wowlan->patterns[i].pattern_len, 8);
3879 +               memset(wow_pattern->pattern_bytes, 0, MAX_PATTERN_SIZE);
3880 +               memset(wow_pattern->mask_bytes, 0, MAX_PATTERN_SIZE);
3881 +               memcpy(wow_pattern->pattern_bytes, patterns[i].pattern,
3882 +                      patterns[i].pattern_len);
3883 +               memcpy(wow_pattern->mask_bytes, patterns[i].mask, mask_len);
3884 +               wow_pattern->pattern_len = patterns[i].pattern_len;
3885 +
3886 +               /*
3887 +                * just need to take care of deauth and disssoc pattern,
3888 +                * make sure we don't overwrite them.
3889 +                */
3890 +
3891 +               ath9k_hw_wow_apply_pattern(ah, wow_pattern->pattern_bytes,
3892 +                                          wow_pattern->mask_bytes,
3893 +                                          i + 2,
3894 +                                          wow_pattern->pattern_len);
3895 +               kfree(wow_pattern);
3896
3897 -       ah->wow_event_mask = 0;
3898 +       }
3899
3900 -       return wow_status;
3901  }
3902 -EXPORT_SYMBOL(ath9k_hw_wow_wakeup);
3903
3904 -void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable)
3905 +int ath9k_suspend(struct ieee80211_hw *hw,
3906 +                 struct cfg80211_wowlan *wowlan)
3907  {
3908 -       u32 wow_event_mask;
3909 -       u32 set, clr;
3910 +       struct ath_softc *sc = hw->priv;
3911 +       struct ath_hw *ah = sc->sc_ah;
3912 +       struct ath_common *common = ath9k_hw_common(ah);
3913 +       u32 wow_triggers_enabled = 0;
3914 +       int ret = 0;
3915
3916 -       /*
3917 -        * wow_event_mask is a mask to the AR_WOW_PATTERN register to
3918 -        * indicate which WoW events we have enabled. The WoW events
3919 -        * are from the 'pattern_enable' in this function and
3920 -        * 'pattern_count' of ath9k_hw_wow_apply_pattern()
3921 -        */
3922 -       wow_event_mask = ah->wow_event_mask;
3923 +       mutex_lock(&sc->mutex);
3924
3925 -       /*
3926 -        * Untie Power-on-Reset from the PCI-E-Reset. When we are in
3927 -        * WOW sleep, we do want the Reset from the PCI-E to disturb
3928 -        * our hw state
3929 -        */
3930 -       if (ah->is_pciexpress) {
3931 -               /*
3932 -                * we need to untie the internal POR (power-on-reset)
3933 -                * to the external PCI-E reset. We also need to tie
3934 -                * the PCI-E Phy reset to the PCI-E reset.
3935 -                */
3936 -               set = AR_WA_RESET_EN | AR_WA_POR_SHORT;
3937 -               clr = AR_WA_UNTIE_RESET_EN | AR_WA_D3_L1_DISABLE;
3938 -               REG_RMW(ah, AR_WA, set, clr);
3939 +       ath_cancel_work(sc);
3940 +       ath_stop_ani(sc);
3941 +       del_timer_sync(&sc->rx_poll_timer);
3942 +
3943 +       if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
3944 +               ath_dbg(common, ANY, "Device not present\n");
3945 +               ret = -EINVAL;
3946 +               goto fail_wow;
3947         }
3948
3949 -       /*
3950 -        * set the power states appropriately and enable PME
3951 -        */
3952 -       set = AR_PMCTRL_HOST_PME_EN | AR_PMCTRL_PWR_PM_CTRL_ENA |
3953 -             AR_PMCTRL_AUX_PWR_DET | AR_PMCTRL_WOW_PME_CLR;
3954 +       if (WARN_ON(!wowlan)) {
3955 +               ath_dbg(common, WOW, "None of the WoW triggers enabled\n");
3956 +               ret = -EINVAL;
3957 +               goto fail_wow;
3958 +       }
3959
3960 -       /*
3961 -        * set and clear WOW_PME_CLEAR registers for the chip
3962 -        * to generate next wow signal.
3963 -        */
3964 -       REG_SET_BIT(ah, AR_PCIE_PM_CTRL, set);
3965 -       clr = AR_PMCTRL_WOW_PME_CLR;
3966 -       REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, clr);
3967 +       if (!device_can_wakeup(sc->dev)) {
3968 +               ath_dbg(common, WOW, "device_can_wakeup failed, WoW is not enabled\n");
3969 +               ret = 1;
3970 +               goto fail_wow;
3971 +       }
3972
3973         /*
3974 -        * Setup for:
3975 -        *      - beacon misses
3976 -        *      - magic pattern
3977 -        *      - keep alive timeout
3978 -        *      - pattern matching
3979 +        * none of the sta vifs are associated
3980 +        * and we are not currently handling multivif
3981 +        * cases, for instance we have to seperately
3982 +        * configure 'keep alive frame' for each
3983 +        * STA.
3984          */
3985
3986 -       /*
3987 -        * Program default values for pattern backoff, aifs/slot/KAL count,
3988 -        * beacon miss timeout, KAL timeout, etc.
3989 -        */
3990 -       set = AR_WOW_BACK_OFF_SHIFT(AR_WOW_PAT_BACKOFF);
3991 -       REG_SET_BIT(ah, AR_WOW_PATTERN, set);
3992 +       if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
3993 +               ath_dbg(common, WOW, "None of the STA vifs are associated\n");
3994 +               ret = 1;
3995 +               goto fail_wow;
3996 +       }
3997 +
3998 +       if (sc->nvifs > 1) {
3999 +               ath_dbg(common, WOW, "WoW for multivif is not yet supported\n");
4000 +               ret = 1;
4001 +               goto fail_wow;
4002 +       }
4003
4004 -       set = AR_WOW_AIFS_CNT(AR_WOW_CNT_AIFS_CNT) |
4005 -             AR_WOW_SLOT_CNT(AR_WOW_CNT_SLOT_CNT) |
4006 -             AR_WOW_KEEP_ALIVE_CNT(AR_WOW_CNT_KA_CNT);
4007 -       REG_SET_BIT(ah, AR_WOW_COUNT, set);
4008 -
4009 -       if (pattern_enable & AH_WOW_BEACON_MISS)
4010 -               set = AR_WOW_BEACON_TIMO;
4011 -       /* We are not using beacon miss, program a large value */
4012 -       else
4013 -               set = AR_WOW_BEACON_TIMO_MAX;
4014 +       ath9k_wow_map_triggers(sc, wowlan, &wow_triggers_enabled);
4015
4016 -       REG_WRITE(ah, AR_WOW_BCN_TIMO, set);
4017 +       ath_dbg(common, WOW, "WoW triggers enabled 0x%x\n",
4018 +               wow_triggers_enabled);
4019
4020 -       /*
4021 -        * Keep alive timo in ms except AR9280
4022 -        */
4023 -       if (!pattern_enable)
4024 -               set = AR_WOW_KEEP_ALIVE_NEVER;
4025 -       else
4026 -               set = KAL_TIMEOUT * 32;
4027 +       ath9k_ps_wakeup(sc);
4028
4029 -       REG_WRITE(ah, AR_WOW_KEEP_ALIVE_TIMO, set);
4030 +       ath9k_stop_btcoex(sc);
4031
4032         /*
4033 -        * Keep alive delay in us. based on 'power on clock',
4034 -        * therefore in usec
4035 +        * Enable wake up on recieving disassoc/deauth
4036 +        * frame by default.
4037          */
4038 -       set = KAL_DELAY * 1000;
4039 -       REG_WRITE(ah, AR_WOW_KEEP_ALIVE_DELAY, set);
4040 +       ath9k_wow_add_disassoc_deauth_pattern(sc);
4041
4042 -       /*
4043 -        * Create keep alive pattern to respond to beacons
4044 -        */
4045 -       ath9k_wow_create_keep_alive_pattern(ah);
4046 +       if (wow_triggers_enabled & AH_WOW_USER_PATTERN_EN)
4047 +               ath9k_wow_add_pattern(sc, wowlan);
4048
4049 +       spin_lock_bh(&sc->sc_pcu_lock);
4050         /*
4051 -        * Configure MAC WoW Registers
4052 +        * To avoid false wake, we enable beacon miss interrupt only
4053 +        * when we go to sleep. We save the current interrupt mask
4054 +        * so we can restore it after the system wakes up
4055          */
4056 -       set = 0;
4057 -       /* Send keep alive timeouts anyway */
4058 -       clr = AR_WOW_KEEP_ALIVE_AUTO_DIS;
4059 -
4060 -       if (pattern_enable & AH_WOW_LINK_CHANGE)
4061 -               wow_event_mask |= AR_WOW_KEEP_ALIVE_FAIL;
4062 -       else
4063 -               set = AR_WOW_KEEP_ALIVE_FAIL_DIS;
4064 +       sc->wow_intr_before_sleep = ah->imask;
4065 +       ah->imask &= ~ATH9K_INT_GLOBAL;
4066 +       ath9k_hw_disable_interrupts(ah);
4067 +       ah->imask = ATH9K_INT_BMISS | ATH9K_INT_GLOBAL;
4068 +       ath9k_hw_set_interrupts(ah);
4069 +       ath9k_hw_enable_interrupts(ah);
4070
4071 -       set = AR_WOW_KEEP_ALIVE_FAIL_DIS;
4072 -       REG_RMW(ah, AR_WOW_KEEP_ALIVE, set, clr);
4073 +       spin_unlock_bh(&sc->sc_pcu_lock);
4074
4075         /*
4076 -        * we are relying on a bmiss failure. ensure we have
4077 -        * enough threshold to prevent false positives
4078 +        * we can now sync irq and kill any running tasklets, since we already
4079 +        * disabled interrupts and not holding a spin lock
4080          */
4081 -       REG_RMW_FIELD(ah, AR_RSSI_THR, AR_RSSI_THR_BM_THR,
4082 -                     AR_WOW_BMISSTHRESHOLD);
4083 +       synchronize_irq(sc->irq);
4084 +       tasklet_kill(&sc->intr_tq);
4085 +
4086 +       ath9k_hw_wow_enable(ah, wow_triggers_enabled);
4087
4088 -       set = 0;
4089 -       clr = 0;
4090 +       ath9k_ps_restore(sc);
4091 +       ath_dbg(common, ANY, "WoW enabled in ath9k\n");
4092 +       atomic_inc(&sc->wow_sleep_proc_intr);
4093
4094 -       if (pattern_enable & AH_WOW_BEACON_MISS) {
4095 -               set = AR_WOW_BEACON_FAIL_EN;
4096 -               wow_event_mask |= AR_WOW_BEACON_FAIL;
4097 -       } else {
4098 -               clr = AR_WOW_BEACON_FAIL_EN;
4099 +fail_wow:
4100 +       mutex_unlock(&sc->mutex);
4101 +       return ret;
4102 +}
4103 +
4104 +int ath9k_resume(struct ieee80211_hw *hw)
4105 +{
4106 +       struct ath_softc *sc = hw->priv;
4107 +       struct ath_hw *ah = sc->sc_ah;
4108 +       struct ath_common *common = ath9k_hw_common(ah);
4109 +       u32 wow_status;
4110 +
4111 +       mutex_lock(&sc->mutex);
4112 +
4113 +       ath9k_ps_wakeup(sc);
4114 +
4115 +       spin_lock_bh(&sc->sc_pcu_lock);
4116 +
4117 +       ath9k_hw_disable_interrupts(ah);
4118 +       ah->imask = sc->wow_intr_before_sleep;
4119 +       ath9k_hw_set_interrupts(ah);
4120 +       ath9k_hw_enable_interrupts(ah);
4121 +
4122 +       spin_unlock_bh(&sc->sc_pcu_lock);
4123 +
4124 +       wow_status = ath9k_hw_wow_wakeup(ah);
4125 +
4126 +       if (atomic_read(&sc->wow_got_bmiss_intr) == 0) {
4127 +               /*
4128 +                * some devices may not pick beacon miss
4129 +                * as the reason they woke up so we add
4130 +                * that here for that shortcoming.
4131 +                */
4132 +               wow_status |= AH_WOW_BEACON_MISS;
4133 +               atomic_dec(&sc->wow_got_bmiss_intr);
4134 +               ath_dbg(common, ANY, "Beacon miss interrupt picked up during WoW sleep\n");
4135         }
4136
4137 -       REG_RMW(ah, AR_WOW_BCN_EN, set, clr);
4138 +       atomic_dec(&sc->wow_sleep_proc_intr);
4139
4140 -       set = 0;
4141 -       clr = 0;
4142 -       /*
4143 -        * Enable the magic packet registers
4144 -        */
4145 -       if (pattern_enable & AH_WOW_MAGIC_PATTERN_EN) {
4146 -               set = AR_WOW_MAGIC_EN;
4147 -               wow_event_mask |= AR_WOW_MAGIC_PAT_FOUND;
4148 -       } else {
4149 -               clr = AR_WOW_MAGIC_EN;
4150 +       if (wow_status) {
4151 +               ath_dbg(common, ANY, "Waking up due to WoW triggers %s with WoW status = %x\n",
4152 +                       ath9k_hw_wow_event_to_string(wow_status), wow_status);
4153         }
4154 -       set |= AR_WOW_MAC_INTR_EN;
4155 -       REG_RMW(ah, AR_WOW_PATTERN, set, clr);
4156
4157 -       REG_WRITE(ah, AR_WOW_PATTERN_MATCH_LT_256B,
4158 -                 AR_WOW_PATTERN_SUPPORTED);
4159 +       ath_restart_work(sc);
4160 +       ath9k_start_btcoex(sc);
4161
4162 -       /*
4163 -        * Set the power states appropriately and enable PME
4164 -        */
4165 -       clr = 0;
4166 -       set = AR_PMCTRL_PWR_STATE_D1D3 | AR_PMCTRL_HOST_PME_EN |
4167 -             AR_PMCTRL_PWR_PM_CTRL_ENA;
4168 +       ath9k_ps_restore(sc);
4169 +       mutex_unlock(&sc->mutex);
4170
4171 -       clr = AR_PCIE_PM_CTRL_ENA;
4172 -       REG_RMW(ah, AR_PCIE_PM_CTRL, set, clr);
4173 +       return 0;
4174 +}
4175
4176 -       /*
4177 -        * this is needed to prevent the chip waking up
4178 -        * the host within 3-4 seconds with certain
4179 -        * platform/BIOS. The fix is to enable
4180 -        * D1 & D3 to match original definition and
4181 -        * also match the OTP value. Anyway this
4182 -        * is more related to SW WOW.
4183 -        */
4184 -       clr = AR_PMCTRL_PWR_STATE_D1D3;
4185 -       REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, clr);
4186 +void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled)
4187 +{
4188 +       struct ath_softc *sc = hw->priv;
4189
4190 -       set = AR_PMCTRL_PWR_STATE_D1D3_REAL;
4191 -       REG_SET_BIT(ah, AR_PCIE_PM_CTRL, set);
4192 +       mutex_lock(&sc->mutex);
4193 +       device_init_wakeup(sc->dev, 1);
4194 +       device_set_wakeup_enable(sc->dev, enabled);
4195 +       mutex_unlock(&sc->mutex);
4196 +}
4197
4198 -       REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
4199 +void ath9k_init_wow(struct ieee80211_hw *hw)
4200 +{
4201 +       struct ath_softc *sc = hw->priv;
4202
4203 -       /* to bring down WOW power low margin */
4204 -       set = BIT(13);
4205 -       REG_SET_BIT(ah, AR_PCIE_PHY_REG3, set);
4206 -       /* HW WoW */
4207 -       clr = BIT(5);
4208 -       REG_CLR_BIT(ah, AR_PCU_MISC_MODE3, clr);
4209 +       if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_WOW_DEVICE_CAPABLE) &&
4210 +           (sc->driver_data & ATH9K_PCI_WOW) &&
4211 +           device_can_wakeup(sc->dev))
4212 +               hw->wiphy->wowlan = &ath9k_wowlan_support;
4213
4214 -       ath9k_hw_set_powermode_wow_sleep(ah);
4215 -       ah->wow_event_mask = wow_event_mask;
4216 +       atomic_set(&sc->wow_sleep_proc_intr, -1);
4217 +       atomic_set(&sc->wow_got_bmiss_intr, -1);
4218  }
4219 -EXPORT_SYMBOL(ath9k_hw_wow_enable);
4220 --- a/drivers/net/wireless/ath/ath9k/xmit.c
4221 +++ b/drivers/net/wireless/ath/ath9k/xmit.c
4222 @@ -174,14 +174,7 @@ static void ath_txq_skb_done(struct ath_
4223  static struct ath_atx_tid *
4224  ath_get_skb_tid(struct ath_softc *sc, struct ath_node *an, struct sk_buff *skb)
4225  {
4226 -       struct ieee80211_hdr *hdr;
4227 -       u8 tidno = 0;
4228 -
4229 -       hdr = (struct ieee80211_hdr *) skb->data;
4230 -       if (ieee80211_is_data_qos(hdr->frame_control))
4231 -               tidno = ieee80211_get_qos_ctl(hdr)[0];
4232 -
4233 -       tidno &= IEEE80211_QOS_CTL_TID_MASK;
4234 +       u8 tidno = skb->priority & IEEE80211_QOS_CTL_TID_MASK;
4235         return ATH_AN_2_TID(an, tidno);
4236  }
4237
4238 @@ -1276,6 +1269,10 @@ static void ath_tx_fill_desc(struct ath_
4239                                 if (!rts_thresh || (len > rts_thresh))
4240                                         rts = true;
4241                         }
4242 +
4243 +                       if (!aggr)
4244 +                               len = fi->framelen;
4245 +
4246                         ath_buf_set_rate(sc, bf, &info, len, rts);
4247                 }
4248
4249 @@ -1786,6 +1783,9 @@ bool ath_drain_all_txq(struct ath_softc
4250                 if (!ATH_TXQ_SETUP(sc, i))
4251                         continue;
4252
4253 +               if (!sc->tx.txq[i].axq_depth)
4254 +                       continue;
4255 +
4256                 if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum))
4257                         npend |= BIT(i);
4258         }
4259 @@ -2749,6 +2749,8 @@ void ath_tx_node_cleanup(struct ath_soft
4260         }
4261  }
4262
4263 +#ifdef CONFIG_ATH9K_TX99
4264 +
4265  int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb,
4266                     struct ath_tx_control *txctl)
4267  {
4268 @@ -2791,3 +2793,5 @@ int ath9k_tx99_send(struct ath_softc *sc
4269
4270         return 0;
4271  }
4272 +
4273 +#endif /* CONFIG_ATH9K_TX99 */
4274 --- a/drivers/net/wireless/ath/regd.c
4275 +++ b/drivers/net/wireless/ath/regd.c
4276 @@ -37,17 +37,17 @@ static int __ath_regd_init(struct ath_re
4277
4278  /* We enable active scan on these a case by case basis by regulatory domain */
4279  #define ATH9K_2GHZ_CH12_13     REG_RULE(2467-10, 2472+10, 40, 0, 20,\
4280 -                                       NL80211_RRF_PASSIVE_SCAN)
4281 +                                       NL80211_RRF_NO_IR)
4282  #define ATH9K_2GHZ_CH14                REG_RULE(2484-10, 2484+10, 40, 0, 20,\
4283 -                               NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_OFDM)
4284 +                               NL80211_RRF_NO_IR | NL80211_RRF_NO_OFDM)
4285
4286  /* We allow IBSS on these on a case by case basis by regulatory domain */
4287  #define ATH9K_5GHZ_5150_5350   REG_RULE(5150-10, 5350+10, 80, 0, 30,\
4288 -                               NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS)
4289 +                               NL80211_RRF_NO_IR)
4290  #define ATH9K_5GHZ_5470_5850   REG_RULE(5470-10, 5850+10, 80, 0, 30,\
4291 -                               NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS)
4292 +                               NL80211_RRF_NO_IR)
4293  #define ATH9K_5GHZ_5725_5850   REG_RULE(5725-10, 5850+10, 80, 0, 30,\
4294 -                               NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS)
4295 +                               NL80211_RRF_NO_IR)
4296
4297  #define ATH9K_2GHZ_ALL         ATH9K_2GHZ_CH01_11, \
4298                                 ATH9K_2GHZ_CH12_13, \
4299 @@ -224,17 +224,16 @@ ath_reg_apply_beaconing_flags(struct wip
4300                                  * regulatory_hint().
4301                                  */
4302                                 if (!(reg_rule->flags &
4303 -                                   NL80211_RRF_NO_IBSS))
4304 +                                   NL80211_RRF_NO_IR))
4305                                         ch->flags &=
4306 -                                         ~IEEE80211_CHAN_NO_IBSS;
4307 +                                         ~IEEE80211_CHAN_NO_IR;
4308                                 if (!(reg_rule->flags &
4309 -                                   NL80211_RRF_PASSIVE_SCAN))
4310 +                                   NL80211_RRF_NO_IR))
4311                                         ch->flags &=
4312 -                                         ~IEEE80211_CHAN_PASSIVE_SCAN;
4313 +                                         ~IEEE80211_CHAN_NO_IR;
4314                         } else {
4315                                 if (ch->beacon_found)
4316 -                                       ch->flags &= ~(IEEE80211_CHAN_NO_IBSS |
4317 -                                         IEEE80211_CHAN_PASSIVE_SCAN);
4318 +                                       ch->flags &= ~IEEE80211_CHAN_NO_IR;
4319                         }
4320                 }
4321         }
4322 @@ -260,11 +259,11 @@ ath_reg_apply_active_scan_flags(struct w
4323          */
4324         if (initiator != NL80211_REGDOM_SET_BY_COUNTRY_IE) {
4325                 ch = &sband->channels[11]; /* CH 12 */
4326 -               if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
4327 -                       ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
4328 +               if (ch->flags & IEEE80211_CHAN_NO_IR)
4329 +                       ch->flags &= ~IEEE80211_CHAN_NO_IR;
4330                 ch = &sband->channels[12]; /* CH 13 */
4331 -               if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
4332 -                       ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
4333 +               if (ch->flags & IEEE80211_CHAN_NO_IR)
4334 +                       ch->flags &= ~IEEE80211_CHAN_NO_IR;
4335                 return;
4336         }
4337
4338 @@ -278,17 +277,17 @@ ath_reg_apply_active_scan_flags(struct w
4339         ch = &sband->channels[11]; /* CH 12 */
4340         reg_rule = freq_reg_info(wiphy, ch->center_freq);
4341         if (!IS_ERR(reg_rule)) {
4342 -               if (!(reg_rule->flags & NL80211_RRF_PASSIVE_SCAN))
4343 -                       if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
4344 -                               ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
4345 +               if (!(reg_rule->flags & NL80211_RRF_NO_IR))
4346 +                       if (ch->flags & IEEE80211_CHAN_NO_IR)
4347 +                               ch->flags &= ~IEEE80211_CHAN_NO_IR;
4348         }
4349
4350         ch = &sband->channels[12]; /* CH 13 */
4351         reg_rule = freq_reg_info(wiphy, ch->center_freq);
4352         if (!IS_ERR(reg_rule)) {
4353 -               if (!(reg_rule->flags & NL80211_RRF_PASSIVE_SCAN))
4354 -                       if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
4355 -                               ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
4356 +               if (!(reg_rule->flags & NL80211_RRF_NO_IR))
4357 +                       if (ch->flags & IEEE80211_CHAN_NO_IR)
4358 +                               ch->flags &= ~IEEE80211_CHAN_NO_IR;
4359         }
4360  }
4361
4362 @@ -320,8 +319,8 @@ static void ath_reg_apply_radar_flags(st
4363                  */
4364                 if (!(ch->flags & IEEE80211_CHAN_DISABLED))
4365                         ch->flags |= IEEE80211_CHAN_RADAR |
4366 -                                    IEEE80211_CHAN_NO_IBSS |
4367 -                                    IEEE80211_CHAN_PASSIVE_SCAN;
4368 +                                    IEEE80211_CHAN_NO_IR |
4369 +                                    IEEE80211_CHAN_NO_IR;
4370         }
4371  }
4372
4373 --- a/drivers/net/wireless/brcm80211/brcmfmac/p2p.c
4374 +++ b/drivers/net/wireless/brcm80211/brcmfmac/p2p.c
4375 @@ -812,7 +812,7 @@ static s32 brcmf_p2p_run_escan(struct br
4376                         struct ieee80211_channel *chan = request->channels[i];
4377
4378                         if (chan->flags & (IEEE80211_CHAN_RADAR |
4379 -                                          IEEE80211_CHAN_PASSIVE_SCAN))
4380 +                                          IEEE80211_CHAN_NO_IR))
4381                                 continue;
4382
4383                         chanspecs[i] = channel_to_chanspec(&p2p->cfg->d11inf,
4384 --- a/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.c
4385 +++ b/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.c
4386 @@ -202,9 +202,9 @@ static struct ieee80211_supported_band _
4387
4388  /* This is to override regulatory domains defined in cfg80211 module (reg.c)
4389   * By default world regulatory domain defined in reg.c puts the flags
4390 - * NL80211_RRF_PASSIVE_SCAN and NL80211_RRF_NO_IBSS for 5GHz channels (for
4391 - * 36..48 and 149..165). With respect to these flags, wpa_supplicant doesn't
4392 - * start p2p operations on 5GHz channels. All the changes in world regulatory
4393 + * NL80211_RRF_NO_IR for 5GHz channels (for * 36..48 and 149..165).
4394 + * With respect to these flags, wpa_supplicant doesn't * start p2p
4395 + * operations on 5GHz channels. All the changes in world regulatory
4396   * domain are to be done here.
4397   */
4398  static const struct ieee80211_regdomain brcmf_regdom = {
4399 @@ -5197,10 +5197,10 @@ static s32 brcmf_construct_reginfo(struc
4400                                         if (channel & WL_CHAN_RADAR)
4401                                                 band_chan_arr[index].flags |=
4402                                                         (IEEE80211_CHAN_RADAR |
4403 -                                                       IEEE80211_CHAN_NO_IBSS);
4404 +                                                       IEEE80211_CHAN_NO_IR);
4405                                         if (channel & WL_CHAN_PASSIVE)
4406                                                 band_chan_arr[index].flags |=
4407 -                                                   IEEE80211_CHAN_PASSIVE_SCAN;
4408 +                                                   IEEE80211_CHAN_NO_IR;
4409                                 }
4410                         }
4411                         if (!update)
4412 --- a/drivers/net/wireless/brcm80211/brcmsmac/channel.c
4413 +++ b/drivers/net/wireless/brcm80211/brcmsmac/channel.c
4414 @@ -59,23 +59,20 @@
4415
4416  #define BRCM_2GHZ_2412_2462    REG_RULE(2412-10, 2462+10, 40, 0, 19, 0)
4417  #define BRCM_2GHZ_2467_2472    REG_RULE(2467-10, 2472+10, 20, 0, 19, \
4418 -                                        NL80211_RRF_PASSIVE_SCAN | \
4419 -                                        NL80211_RRF_NO_IBSS)
4420 +                                        NL80211_RRF_NO_IR)
4421
4422  #define BRCM_5GHZ_5180_5240    REG_RULE(5180-10, 5240+10, 40, 0, 21, \
4423 -                                        NL80211_RRF_PASSIVE_SCAN | \
4424 -                                        NL80211_RRF_NO_IBSS)
4425 +                                        NL80211_RRF_NO_IR)
4426  #define BRCM_5GHZ_5260_5320    REG_RULE(5260-10, 5320+10, 40, 0, 21, \
4427 -                                        NL80211_RRF_PASSIVE_SCAN | \
4428 +                                        NL80211_RRF_NO_IR | \
4429                                          NL80211_RRF_DFS | \
4430 -                                        NL80211_RRF_NO_IBSS)
4431 +                                        NL80211_RRF_NO_IR)
4432  #define BRCM_5GHZ_5500_5700    REG_RULE(5500-10, 5700+10, 40, 0, 21, \
4433 -                                        NL80211_RRF_PASSIVE_SCAN | \
4434 +                                        NL80211_RRF_NO_IR | \
4435                                          NL80211_RRF_DFS | \
4436 -                                        NL80211_RRF_NO_IBSS)
4437 +                                        NL80211_RRF_NO_IR)
4438  #define BRCM_5GHZ_5745_5825    REG_RULE(5745-10, 5825+10, 40, 0, 21, \
4439 -                                        NL80211_RRF_PASSIVE_SCAN | \
4440 -                                        NL80211_RRF_NO_IBSS)
4441 +                                        NL80211_RRF_NO_IR)
4442
4443  static const struct ieee80211_regdomain brcms_regdom_x2 = {
4444         .n_reg_rules = 6,
4445 @@ -395,7 +392,7 @@ brcms_c_channel_set_chanspec(struct brcm
4446                 brcms_c_set_gmode(wlc, wlc->protection->gmode_user, false);
4447
4448         brcms_b_set_chanspec(wlc->hw, chanspec,
4449 -                             !!(ch->flags & IEEE80211_CHAN_PASSIVE_SCAN),
4450 +                             !!(ch->flags & IEEE80211_CHAN_NO_IR),
4451                               &txpwr);
4452  }
4453
4454 @@ -657,8 +654,8 @@ static void brcms_reg_apply_radar_flags(
4455                  */
4456                 if (!(ch->flags & IEEE80211_CHAN_DISABLED))
4457                         ch->flags |= IEEE80211_CHAN_RADAR |
4458 -                                    IEEE80211_CHAN_NO_IBSS |
4459 -                                    IEEE80211_CHAN_PASSIVE_SCAN;
4460 +                                    IEEE80211_CHAN_NO_IR |
4461 +                                    IEEE80211_CHAN_NO_IR;
4462         }
4463  }
4464
4465 @@ -688,14 +685,13 @@ brcms_reg_apply_beaconing_flags(struct w
4466                                 if (IS_ERR(rule))
4467                                         continue;
4468
4469 -                               if (!(rule->flags & NL80211_RRF_NO_IBSS))
4470 -                                       ch->flags &= ~IEEE80211_CHAN_NO_IBSS;
4471 -                               if (!(rule->flags & NL80211_RRF_PASSIVE_SCAN))
4472 +                               if (!(rule->flags & NL80211_RRF_NO_IR))
4473 +                                       ch->flags &= ~IEEE80211_CHAN_NO_IR;
4474 +                               if (!(rule->flags & NL80211_RRF_NO_IR))
4475                                         ch->flags &=
4476 -                                               ~IEEE80211_CHAN_PASSIVE_SCAN;
4477 +                                               ~IEEE80211_CHAN_NO_IR;
4478                         } else if (ch->beacon_found) {
4479 -                               ch->flags &= ~(IEEE80211_CHAN_NO_IBSS |
4480 -                                              IEEE80211_CHAN_PASSIVE_SCAN);
4481 +                               ch->flags &= ~IEEE80211_CHAN_NO_IR;
4482                         }
4483                 }
4484         }
4485 --- a/drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.c
4486 +++ b/drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.c
4487 @@ -125,13 +125,13 @@ static struct ieee80211_channel brcms_2g
4488         CHAN2GHZ(10, 2457, IEEE80211_CHAN_NO_HT40PLUS),
4489         CHAN2GHZ(11, 2462, IEEE80211_CHAN_NO_HT40PLUS),
4490         CHAN2GHZ(12, 2467,
4491 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_IBSS |
4492 +                IEEE80211_CHAN_NO_IR |
4493                  IEEE80211_CHAN_NO_HT40PLUS),
4494         CHAN2GHZ(13, 2472,
4495 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_IBSS |
4496 +                IEEE80211_CHAN_NO_IR |
4497                  IEEE80211_CHAN_NO_HT40PLUS),
4498         CHAN2GHZ(14, 2484,
4499 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_IBSS |
4500 +                IEEE80211_CHAN_NO_IR |
4501                  IEEE80211_CHAN_NO_HT40PLUS | IEEE80211_CHAN_NO_HT40MINUS |
4502                  IEEE80211_CHAN_NO_OFDM)
4503  };
4504 @@ -144,51 +144,51 @@ static struct ieee80211_channel brcms_5g
4505         CHAN5GHZ(48, IEEE80211_CHAN_NO_HT40PLUS),
4506         /* UNII-2 */
4507         CHAN5GHZ(52,
4508 -                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
4509 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
4510 +                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
4511 +                IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40MINUS),
4512         CHAN5GHZ(56,
4513 -                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
4514 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
4515 +                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
4516 +                IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40PLUS),
4517         CHAN5GHZ(60,
4518 -                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
4519 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
4520 +                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
4521 +                IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40MINUS),
4522         CHAN5GHZ(64,
4523 -                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
4524 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
4525 +                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
4526 +                IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40PLUS),
4527         /* MID */
4528         CHAN5GHZ(100,
4529 -                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
4530 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
4531 +                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
4532 +                IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40MINUS),
4533         CHAN5GHZ(104,
4534 -                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
4535 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
4536 +                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
4537 +                IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40PLUS),
4538         CHAN5GHZ(108,
4539 -                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
4540 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
4541 +                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
4542 +                IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40MINUS),
4543         CHAN5GHZ(112,
4544 -                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
4545 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
4546 +                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
4547 +                IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40PLUS),
4548         CHAN5GHZ(116,
4549 -                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
4550 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
4551 +                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
4552 +                IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40MINUS),
4553         CHAN5GHZ(120,
4554 -                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
4555 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
4556 +                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
4557 +                IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40PLUS),
4558         CHAN5GHZ(124,
4559 -                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
4560 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
4561 +                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
4562 +                IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40MINUS),
4563         CHAN5GHZ(128,
4564 -                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
4565 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
4566 +                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
4567 +                IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40PLUS),
4568         CHAN5GHZ(132,
4569 -                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
4570 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
4571 +                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
4572 +                IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40MINUS),
4573         CHAN5GHZ(136,
4574 -                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
4575 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
4576 +                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
4577 +                IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40PLUS),
4578         CHAN5GHZ(140,
4579 -                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
4580 -                IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS |
4581 +                IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
4582 +                IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40PLUS |
4583                  IEEE80211_CHAN_NO_HT40MINUS),
4584         /* UNII-3 */
4585         CHAN5GHZ(149, IEEE80211_CHAN_NO_HT40MINUS),
4586 --- a/drivers/net/wireless/cw1200/scan.c
4587 +++ b/drivers/net/wireless/cw1200/scan.c
4588 @@ -197,9 +197,9 @@ void cw1200_scan_work(struct work_struct
4589                         if ((*it)->band != first->band)
4590                                 break;
4591                         if (((*it)->flags ^ first->flags) &
4592 -                                       IEEE80211_CHAN_PASSIVE_SCAN)
4593 +                                       IEEE80211_CHAN_NO_IR)
4594                                 break;
4595 -                       if (!(first->flags & IEEE80211_CHAN_PASSIVE_SCAN) &&
4596 +                       if (!(first->flags & IEEE80211_CHAN_NO_IR) &&
4597                             (*it)->max_power != first->max_power)
4598                                 break;
4599                 }
4600 @@ -210,7 +210,7 @@ void cw1200_scan_work(struct work_struct
4601                 else
4602                         scan.max_tx_rate = WSM_TRANSMIT_RATE_1;
4603                 scan.num_probes =
4604 -                       (first->flags & IEEE80211_CHAN_PASSIVE_SCAN) ? 0 : 2;
4605 +                       (first->flags & IEEE80211_CHAN_NO_IR) ? 0 : 2;
4606                 scan.num_ssids = priv->scan.n_ssids;
4607                 scan.ssids = &priv->scan.ssids[0];
4608                 scan.num_channels = it - priv->scan.curr;
4609 @@ -233,7 +233,7 @@ void cw1200_scan_work(struct work_struct
4610                 }
4611                 for (i = 0; i < scan.num_channels; ++i) {
4612                         scan.ch[i].number = priv->scan.curr[i]->hw_value;
4613 -                       if (priv->scan.curr[i]->flags & IEEE80211_CHAN_PASSIVE_SCAN) {
4614 +                       if (priv->scan.curr[i]->flags & IEEE80211_CHAN_NO_IR) {
4615                                 scan.ch[i].min_chan_time = 50;
4616                                 scan.ch[i].max_chan_time = 100;
4617                         } else {
4618 @@ -241,7 +241,7 @@ void cw1200_scan_work(struct work_struct
4619                                 scan.ch[i].max_chan_time = 25;
4620                         }
4621                 }
4622 -               if (!(first->flags & IEEE80211_CHAN_PASSIVE_SCAN) &&
4623 +               if (!(first->flags & IEEE80211_CHAN_NO_IR) &&
4624                     priv->scan.output_power != first->max_power) {
4625                         priv->scan.output_power = first->max_power;
4626                         wsm_set_output_power(priv,
4627 --- a/drivers/net/wireless/ipw2x00/ipw2100.c
4628 +++ b/drivers/net/wireless/ipw2x00/ipw2100.c
4629 @@ -1934,10 +1934,10 @@ static int ipw2100_wdev_init(struct net_
4630                         bg_band->channels[i].max_power = geo->bg[i].max_power;
4631                         if (geo->bg[i].flags & LIBIPW_CH_PASSIVE_ONLY)
4632                                 bg_band->channels[i].flags |=
4633 -                                       IEEE80211_CHAN_PASSIVE_SCAN;
4634 +                                       IEEE80211_CHAN_NO_IR;
4635                         if (geo->bg[i].flags & LIBIPW_CH_NO_IBSS)
4636                                 bg_band->channels[i].flags |=
4637 -                                       IEEE80211_CHAN_NO_IBSS;
4638 +                                       IEEE80211_CHAN_NO_IR;
4639                         if (geo->bg[i].flags & LIBIPW_CH_RADAR_DETECT)
4640                                 bg_band->channels[i].flags |=
4641                                         IEEE80211_CHAN_RADAR;
4642 --- a/drivers/net/wireless/ipw2x00/ipw2200.c
4643 +++ b/drivers/net/wireless/ipw2x00/ipw2200.c
4644 @@ -11472,10 +11472,10 @@ static int ipw_wdev_init(struct net_devi
4645                         bg_band->channels[i].max_power = geo->bg[i].max_power;
4646                         if (geo->bg[i].flags & LIBIPW_CH_PASSIVE_ONLY)
4647                                 bg_band->channels[i].flags |=
4648 -                                       IEEE80211_CHAN_PASSIVE_SCAN;
4649 +                                       IEEE80211_CHAN_NO_IR;
4650                         if (geo->bg[i].flags & LIBIPW_CH_NO_IBSS)
4651                                 bg_band->channels[i].flags |=
4652 -                                       IEEE80211_CHAN_NO_IBSS;
4653 +                                       IEEE80211_CHAN_NO_IR;
4654                         if (geo->bg[i].flags & LIBIPW_CH_RADAR_DETECT)
4655                                 bg_band->channels[i].flags |=
4656                                         IEEE80211_CHAN_RADAR;
4657 @@ -11511,10 +11511,10 @@ static int ipw_wdev_init(struct net_devi
4658                         a_band->channels[i].max_power = geo->a[i].max_power;
4659                         if (geo->a[i].flags & LIBIPW_CH_PASSIVE_ONLY)
4660                                 a_band->channels[i].flags |=
4661 -                                       IEEE80211_CHAN_PASSIVE_SCAN;
4662 +                                       IEEE80211_CHAN_NO_IR;
4663                         if (geo->a[i].flags & LIBIPW_CH_NO_IBSS)
4664                                 a_band->channels[i].flags |=
4665 -                                       IEEE80211_CHAN_NO_IBSS;
4666 +                                       IEEE80211_CHAN_NO_IR;
4667                         if (geo->a[i].flags & LIBIPW_CH_RADAR_DETECT)
4668                                 a_band->channels[i].flags |=
4669                                         IEEE80211_CHAN_RADAR;
4670 --- a/drivers/net/wireless/iwlegacy/3945-mac.c
4671 +++ b/drivers/net/wireless/iwlegacy/3945-mac.c
4672 @@ -1595,7 +1595,7 @@ il3945_get_channels_for_scan(struct il_p
4673                  *  and use long active_dwell time.
4674                  */
4675                 if (!is_active || il_is_channel_passive(ch_info) ||
4676 -                   (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN)) {
4677 +                   (chan->flags & IEEE80211_CHAN_NO_IR)) {
4678                         scan_ch->type = 0;      /* passive */
4679                         if (IL_UCODE_API(il->ucode_ver) == 1)
4680                                 scan_ch->active_dwell =
4681 --- a/drivers/net/wireless/iwlegacy/4965-mac.c
4682 +++ b/drivers/net/wireless/iwlegacy/4965-mac.c
4683 @@ -805,7 +805,7 @@ il4965_get_channels_for_scan(struct il_p
4684                 }
4685
4686                 if (!is_active || il_is_channel_passive(ch_info) ||
4687 -                   (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN))
4688 +                   (chan->flags & IEEE80211_CHAN_NO_IR))
4689                         scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
4690                 else
4691                         scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE;
4692 --- a/drivers/net/wireless/iwlegacy/common.c
4693 +++ b/drivers/net/wireless/iwlegacy/common.c
4694 @@ -3447,10 +3447,10 @@ il_init_geos(struct il_priv *il)
4695
4696                 if (il_is_channel_valid(ch)) {
4697                         if (!(ch->flags & EEPROM_CHANNEL_IBSS))
4698 -                               geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
4699 +                               geo_ch->flags |= IEEE80211_CHAN_NO_IR;
4700
4701                         if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
4702 -                               geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
4703 +                               geo_ch->flags |= IEEE80211_CHAN_NO_IR;
4704
4705                         if (ch->flags & EEPROM_CHANNEL_RADAR)
4706                                 geo_ch->flags |= IEEE80211_CHAN_RADAR;
4707 --- a/drivers/net/wireless/iwlegacy/debug.c
4708 +++ b/drivers/net/wireless/iwlegacy/debug.c
4709 @@ -567,12 +567,12 @@ il_dbgfs_channels_read(struct file *file
4710                                       flags & IEEE80211_CHAN_RADAR ?
4711                                       " (IEEE 802.11h required)" : "",
4712                                       ((channels[i].
4713 -                                       flags & IEEE80211_CHAN_NO_IBSS) ||
4714 +                                       flags & IEEE80211_CHAN_NO_IR) ||
4715                                        (channels[i].
4716                                         flags & IEEE80211_CHAN_RADAR)) ? "" :
4717                                       ", IBSS",
4718                                       channels[i].
4719 -                                     flags & IEEE80211_CHAN_PASSIVE_SCAN ?
4720 +                                     flags & IEEE80211_CHAN_NO_IR ?
4721                                       "passive only" : "active/passive");
4722         }
4723         supp_band = il_get_hw_mode(il, IEEE80211_BAND_5GHZ);
4724 @@ -594,12 +594,12 @@ il_dbgfs_channels_read(struct file *file
4725                                       flags & IEEE80211_CHAN_RADAR ?
4726                                       " (IEEE 802.11h required)" : "",
4727                                       ((channels[i].
4728 -                                       flags & IEEE80211_CHAN_NO_IBSS) ||
4729 +                                       flags & IEEE80211_CHAN_NO_IR) ||
4730                                        (channels[i].
4731                                         flags & IEEE80211_CHAN_RADAR)) ? "" :
4732                                       ", IBSS",
4733                                       channels[i].
4734 -                                     flags & IEEE80211_CHAN_PASSIVE_SCAN ?
4735 +                                     flags & IEEE80211_CHAN_NO_IR ?
4736                                       "passive only" : "active/passive");
4737         }
4738         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
4739 --- a/drivers/net/wireless/iwlwifi/dvm/debugfs.c
4740 +++ b/drivers/net/wireless/iwlwifi/dvm/debugfs.c
4741 @@ -352,12 +352,12 @@ static ssize_t iwl_dbgfs_channels_read(s
4742                                         channels[i].max_power,
4743                                         channels[i].flags & IEEE80211_CHAN_RADAR ?
4744                                         " (IEEE 802.11h required)" : "",
4745 -                                       ((channels[i].flags & IEEE80211_CHAN_NO_IBSS)
4746 +                                       ((channels[i].flags & IEEE80211_CHAN_NO_IR)
4747                                         || (channels[i].flags &
4748                                         IEEE80211_CHAN_RADAR)) ? "" :
4749                                         ", IBSS",
4750                                         channels[i].flags &
4751 -                                       IEEE80211_CHAN_PASSIVE_SCAN ?
4752 +                                       IEEE80211_CHAN_NO_IR ?
4753                                         "passive only" : "active/passive");
4754         }
4755         supp_band = iwl_get_hw_mode(priv, IEEE80211_BAND_5GHZ);
4756 @@ -375,12 +375,12 @@ static ssize_t iwl_dbgfs_channels_read(s
4757                                         channels[i].max_power,
4758                                         channels[i].flags & IEEE80211_CHAN_RADAR ?
4759                                         " (IEEE 802.11h required)" : "",
4760 -                                       ((channels[i].flags & IEEE80211_CHAN_NO_IBSS)
4761 +                                       ((channels[i].flags & IEEE80211_CHAN_NO_IR)
4762                                         || (channels[i].flags &
4763                                         IEEE80211_CHAN_RADAR)) ? "" :
4764                                         ", IBSS",
4765                                         channels[i].flags &
4766 -                                       IEEE80211_CHAN_PASSIVE_SCAN ?
4767 +                                       IEEE80211_CHAN_NO_IR ?
4768                                         "passive only" : "active/passive");
4769         }
4770         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
4771 --- a/drivers/net/wireless/iwlwifi/dvm/scan.c
4772 +++ b/drivers/net/wireless/iwlwifi/dvm/scan.c
4773 @@ -544,7 +544,7 @@ static int iwl_get_channels_for_scan(str
4774                 channel = chan->hw_value;
4775                 scan_ch->channel = cpu_to_le16(channel);
4776
4777 -               if (!is_active || (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN))
4778 +               if (!is_active || (chan->flags & IEEE80211_CHAN_NO_IR))
4779                         scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
4780                 else
4781                         scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE;
4782 --- a/drivers/net/wireless/iwlwifi/iwl-eeprom-parse.c
4783 +++ b/drivers/net/wireless/iwlwifi/iwl-eeprom-parse.c
4784 @@ -614,10 +614,10 @@ static int iwl_init_channel_map(struct d
4785                         channel->flags = IEEE80211_CHAN_NO_HT40;
4786
4787                         if (!(eeprom_ch->flags & EEPROM_CHANNEL_IBSS))
4788 -                               channel->flags |= IEEE80211_CHAN_NO_IBSS;
4789 +                               channel->flags |= IEEE80211_CHAN_NO_IR;
4790
4791                         if (!(eeprom_ch->flags & EEPROM_CHANNEL_ACTIVE))
4792 -                               channel->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
4793 +                               channel->flags |= IEEE80211_CHAN_NO_IR;
4794
4795                         if (eeprom_ch->flags & EEPROM_CHANNEL_RADAR)
4796                                 channel->flags |= IEEE80211_CHAN_RADAR;
4797 --- a/drivers/net/wireless/iwlwifi/iwl-nvm-parse.c
4798 +++ b/drivers/net/wireless/iwlwifi/iwl-nvm-parse.c
4799 @@ -223,10 +223,10 @@ static int iwl_init_channel_map(struct d
4800                         channel->flags |= IEEE80211_CHAN_NO_160MHZ;
4801
4802                 if (!(ch_flags & NVM_CHANNEL_IBSS))
4803 -                       channel->flags |= IEEE80211_CHAN_NO_IBSS;
4804 +                       channel->flags |= IEEE80211_CHAN_NO_IR;
4805
4806                 if (!(ch_flags & NVM_CHANNEL_ACTIVE))
4807 -                       channel->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
4808 +                       channel->flags |= IEEE80211_CHAN_NO_IR;
4809
4810                 if (ch_flags & NVM_CHANNEL_RADAR)
4811                         channel->flags |= IEEE80211_CHAN_RADAR;
4812 --- a/drivers/net/wireless/iwlwifi/mvm/scan.c
4813 +++ b/drivers/net/wireless/iwlwifi/mvm/scan.c
4814 @@ -192,7 +192,7 @@ static void iwl_mvm_scan_fill_channels(s
4815         for (i = 0; i < cmd->channel_count; i++) {
4816                 chan->channel = cpu_to_le16(req->channels[i]->hw_value);
4817                 chan->type = cpu_to_le32(type);
4818 -               if (req->channels[i]->flags & IEEE80211_CHAN_PASSIVE_SCAN)
4819 +               if (req->channels[i]->flags & IEEE80211_CHAN_NO_IR)
4820                         chan->type &= cpu_to_le32(~SCAN_CHANNEL_TYPE_ACTIVE);
4821                 chan->active_dwell = cpu_to_le16(active_dwell);
4822                 chan->passive_dwell = cpu_to_le16(passive_dwell);
4823 @@ -642,7 +642,7 @@ static void iwl_build_channel_cfg(struct
4824                 channels->iter_count[index] = cpu_to_le16(1);
4825                 channels->iter_interval[index] = 0;
4826
4827 -               if (!(s_band->channels[i].flags & IEEE80211_CHAN_PASSIVE_SCAN))
4828 +               if (!(s_band->channels[i].flags & IEEE80211_CHAN_NO_IR))
4829                         channels->type[index] |=
4830                                 cpu_to_le32(IWL_SCAN_OFFLOAD_CHANNEL_ACTIVE);
4831
4832 --- a/drivers/net/wireless/mac80211_hwsim.c
4833 +++ b/drivers/net/wireless/mac80211_hwsim.c
4834 @@ -159,7 +159,7 @@ static const struct ieee80211_regdomain
4835         .reg_rules = {
4836                 REG_RULE(2412-10, 2462+10, 40, 0, 20, 0),
4837                 REG_RULE(5725-10, 5850+10, 40, 0, 30,
4838 -                       NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS),
4839 +                        NL80211_RRF_NO_IR),
4840         }
4841  };
4842
4843 @@ -1485,7 +1485,7 @@ static void hw_scan_work(struct work_str
4844                     req->channels[hwsim->scan_chan_idx]->center_freq);
4845
4846         hwsim->tmp_chan = req->channels[hwsim->scan_chan_idx];
4847 -       if (hwsim->tmp_chan->flags & IEEE80211_CHAN_PASSIVE_SCAN ||
4848 +       if (hwsim->tmp_chan->flags & IEEE80211_CHAN_NO_IR ||
4849             !req->n_ssids) {
4850                 dwell = 120;
4851         } else {
4852 --- a/drivers/net/wireless/mwifiex/cfg80211.c
4853 +++ b/drivers/net/wireless/mwifiex/cfg80211.c
4854 @@ -50,24 +50,24 @@ static const struct ieee80211_regdomain
4855                 REG_RULE(2412-10, 2462+10, 40, 3, 20, 0),
4856                 /* Channel 12 - 13 */
4857                 REG_RULE(2467-10, 2472+10, 20, 3, 20,
4858 -                        NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS),
4859 +                        NL80211_RRF_NO_IR),
4860                 /* Channel 14 */
4861                 REG_RULE(2484-10, 2484+10, 20, 3, 20,
4862 -                        NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS |
4863 +                        NL80211_RRF_NO_IR |
4864                          NL80211_RRF_NO_OFDM),
4865                 /* Channel 36 - 48 */
4866                 REG_RULE(5180-10, 5240+10, 40, 3, 20,
4867 -                        NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS),
4868 +                        NL80211_RRF_NO_IR),
4869                 /* Channel 149 - 165 */
4870                 REG_RULE(5745-10, 5825+10, 40, 3, 20,
4871 -                        NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS),
4872 +                        NL80211_RRF_NO_IR),
4873                 /* Channel 52 - 64 */
4874                 REG_RULE(5260-10, 5320+10, 40, 3, 30,
4875 -                        NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS |
4876 +                        NL80211_RRF_NO_IR |
4877                          NL80211_RRF_DFS),
4878                 /* Channel 100 - 140 */
4879                 REG_RULE(5500-10, 5700+10, 40, 3, 30,
4880 -                        NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS |
4881 +                        NL80211_RRF_NO_IR |
4882                          NL80211_RRF_DFS),
4883         }
4884  };
4885 @@ -1968,7 +1968,7 @@ mwifiex_cfg80211_scan(struct wiphy *wiph
4886                 user_scan_cfg->chan_list[i].chan_number = chan->hw_value;
4887                 user_scan_cfg->chan_list[i].radio_type = chan->band;
4888
4889 -               if (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN)
4890 +               if (chan->flags & IEEE80211_CHAN_NO_IR)
4891                         user_scan_cfg->chan_list[i].scan_type =
4892                                                 MWIFIEX_SCAN_TYPE_PASSIVE;
4893                 else
4894 --- a/drivers/net/wireless/mwifiex/scan.c
4895 +++ b/drivers/net/wireless/mwifiex/scan.c
4896 @@ -515,14 +515,14 @@ mwifiex_scan_create_channel_list(struct
4897                                 scan_chan_list[chan_idx].max_scan_time =
4898                                         cpu_to_le16((u16) user_scan_in->
4899                                         chan_list[0].scan_time);
4900 -                       else if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
4901 +                       else if (ch->flags & IEEE80211_CHAN_NO_IR)
4902                                 scan_chan_list[chan_idx].max_scan_time =
4903                                         cpu_to_le16(adapter->passive_scan_time);
4904                         else
4905                                 scan_chan_list[chan_idx].max_scan_time =
4906                                         cpu_to_le16(adapter->active_scan_time);
4907
4908 -                       if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
4909 +                       if (ch->flags & IEEE80211_CHAN_NO_IR)
4910                                 scan_chan_list[chan_idx].chan_scan_mode_bitmap
4911                                         |= MWIFIEX_PASSIVE_SCAN;
4912                         else
4913 --- a/drivers/net/wireless/rt2x00/rt2x00lib.h
4914 +++ b/drivers/net/wireless/rt2x00/rt2x00lib.h
4915 @@ -146,7 +146,7 @@ void rt2x00queue_remove_l2pad(struct sk_
4916   * @local: frame is not from mac80211
4917   */
4918  int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb,
4919 -                              bool local);
4920 +                              struct ieee80211_sta *sta, bool local);
4921
4922  /**
4923   * rt2x00queue_update_beacon - Send new beacon from mac80211
4924 --- a/drivers/net/wireless/rt2x00/rt2x00mac.c
4925 +++ b/drivers/net/wireless/rt2x00/rt2x00mac.c
4926 @@ -90,7 +90,7 @@ static int rt2x00mac_tx_rts_cts(struct r
4927                                   frag_skb->data, data_length, tx_info,
4928                                   (struct ieee80211_rts *)(skb->data));
4929
4930 -       retval = rt2x00queue_write_tx_frame(queue, skb, true);
4931 +       retval = rt2x00queue_write_tx_frame(queue, skb, NULL, true);
4932         if (retval) {
4933                 dev_kfree_skb_any(skb);
4934                 rt2x00_warn(rt2x00dev, "Failed to send RTS/CTS frame\n");
4935 @@ -151,7 +151,7 @@ void rt2x00mac_tx(struct ieee80211_hw *h
4936                         goto exit_fail;
4937         }
4938
4939 -       if (unlikely(rt2x00queue_write_tx_frame(queue, skb, false)))
4940 +       if (unlikely(rt2x00queue_write_tx_frame(queue, skb, control->sta, false)))
4941                 goto exit_fail;
4942
4943         /*
4944 --- a/drivers/net/wireless/rt2x00/rt2x00queue.c
4945 +++ b/drivers/net/wireless/rt2x00/rt2x00queue.c
4946 @@ -635,7 +635,7 @@ static void rt2x00queue_bar_check(struct
4947  }
4948
4949  int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb,
4950 -                              bool local)
4951 +                              struct ieee80211_sta *sta, bool local)
4952  {
4953         struct ieee80211_tx_info *tx_info;
4954         struct queue_entry *entry;
4955 @@ -649,7 +649,7 @@ int rt2x00queue_write_tx_frame(struct da
4956          * after that we are free to use the skb->cb array
4957          * for our information.
4958          */
4959 -       rt2x00queue_create_tx_descriptor(queue->rt2x00dev, skb, &txdesc, NULL);
4960 +       rt2x00queue_create_tx_descriptor(queue->rt2x00dev, skb, &txdesc, sta);
4961
4962         /*
4963          * All information is retrieved from the skb->cb array,
4964 --- a/drivers/net/wireless/rtl818x/rtl8187/dev.c
4965 +++ b/drivers/net/wireless/rtl818x/rtl8187/dev.c
4966 @@ -416,7 +416,7 @@ static int rtl8187_init_urbs(struct ieee
4967         struct rtl8187_rx_info *info;
4968         int ret = 0;
4969
4970 -       while (skb_queue_len(&priv->rx_queue) < 16) {
4971 +       while (skb_queue_len(&priv->rx_queue) < 32) {
4972                 skb = __dev_alloc_skb(RTL8187_MAX_RX, GFP_KERNEL);
4973                 if (!skb) {
4974                         ret = -ENOMEM;
4975 --- a/drivers/net/wireless/rtlwifi/base.c
4976 +++ b/drivers/net/wireless/rtlwifi/base.c
4977 @@ -1078,8 +1078,8 @@ u8 rtl_is_special_data(struct ieee80211_
4978
4979         ip = (struct iphdr *)((u8 *) skb->data + mac_hdr_len +
4980                               SNAP_SIZE + PROTOC_TYPE_SIZE);
4981 -       ether_type = *(u16 *) ((u8 *) skb->data + mac_hdr_len + SNAP_SIZE);
4982 -       /*      ether_type = ntohs(ether_type); */
4983 +       ether_type = be16_to_cpu(*(__be16 *)((u8 *)skb->data + mac_hdr_len +
4984 +                                            SNAP_SIZE));
4985
4986         if (ETH_P_IP == ether_type) {
4987                 if (IPPROTO_UDP == ip->protocol) {
4988 --- a/drivers/net/wireless/rtlwifi/regd.c
4989 +++ b/drivers/net/wireless/rtlwifi/regd.c
4990 @@ -59,30 +59,27 @@ static struct country_code_to_enum_rd al
4991   */
4992  #define RTL819x_2GHZ_CH12_13   \
4993         REG_RULE(2467-10, 2472+10, 40, 0, 20,\
4994 -       NL80211_RRF_PASSIVE_SCAN)
4995 +       NL80211_RRF_NO_IR)
4996
4997  #define RTL819x_2GHZ_CH14      \
4998         REG_RULE(2484-10, 2484+10, 40, 0, 20, \
4999 -       NL80211_RRF_PASSIVE_SCAN | \
5000 +       NL80211_RRF_NO_IR | \
5001         NL80211_RRF_NO_OFDM)
5002
5003  /* 5G chan 36 - chan 64*/
5004  #define RTL819x_5GHZ_5150_5350 \
5005         REG_RULE(5150-10, 5350+10, 40, 0, 30, \
5006 -       NL80211_RRF_PASSIVE_SCAN | \
5007 -       NL80211_RRF_NO_IBSS)
5008 +       NL80211_RRF_NO_IR)
5009
5010  /* 5G chan 100 - chan 165*/
5011  #define RTL819x_5GHZ_5470_5850 \
5012         REG_RULE(5470-10, 5850+10, 40, 0, 30, \
5013 -       NL80211_RRF_PASSIVE_SCAN | \
5014 -       NL80211_RRF_NO_IBSS)
5015 +       NL80211_RRF_NO_IR)
5016
5017  /* 5G chan 149 - chan 165*/
5018  #define RTL819x_5GHZ_5725_5850 \
5019         REG_RULE(5725-10, 5850+10, 40, 0, 30, \
5020 -       NL80211_RRF_PASSIVE_SCAN | \
5021 -       NL80211_RRF_NO_IBSS)
5022 +       NL80211_RRF_NO_IR)
5023
5024  #define RTL819x_5GHZ_ALL       \
5025         (RTL819x_5GHZ_5150_5350, RTL819x_5GHZ_5470_5850)
5026 @@ -185,16 +182,15 @@ static void _rtl_reg_apply_beaconing_fla
5027                                  *regulatory_hint().
5028                                  */
5029
5030 -                               if (!(reg_rule->flags & NL80211_RRF_NO_IBSS))
5031 -                                       ch->flags &= ~IEEE80211_CHAN_NO_IBSS;
5032 +                               if (!(reg_rule->flags & NL80211_RRF_NO_IR))
5033 +                                       ch->flags &= ~IEEE80211_CHAN_NO_IR;
5034                                 if (!(reg_rule->
5035 -                                    flags & NL80211_RRF_PASSIVE_SCAN))
5036 +                                    flags & NL80211_RRF_NO_IR))
5037                                         ch->flags &=
5038 -                                           ~IEEE80211_CHAN_PASSIVE_SCAN;
5039 +                                           ~IEEE80211_CHAN_NO_IR;
5040                         } else {
5041                                 if (ch->beacon_found)
5042 -                                       ch->flags &= ~(IEEE80211_CHAN_NO_IBSS |
5043 -                                                 IEEE80211_CHAN_PASSIVE_SCAN);
5044 +                                       ch->flags &= ~IEEE80211_CHAN_NO_IR;
5045                         }
5046                 }
5047         }
5048 @@ -219,11 +215,11 @@ static void _rtl_reg_apply_active_scan_f
5049          */
5050         if (initiator != NL80211_REGDOM_SET_BY_COUNTRY_IE) {
5051                 ch = &sband->channels[11];      /* CH 12 */
5052 -               if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
5053 -                       ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
5054 +               if (ch->flags & IEEE80211_CHAN_NO_IR)
5055 +                       ch->flags &= ~IEEE80211_CHAN_NO_IR;
5056                 ch = &sband->channels[12];      /* CH 13 */
5057 -               if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
5058 -                       ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
5059 +               if (ch->flags & IEEE80211_CHAN_NO_IR)
5060 +                       ch->flags &= ~IEEE80211_CHAN_NO_IR;
5061                 return;
5062         }
5063
5064 @@ -237,17 +233,17 @@ static void _rtl_reg_apply_active_scan_f
5065         ch = &sband->channels[11];      /* CH 12 */
5066         reg_rule = freq_reg_info(wiphy, ch->center_freq);
5067         if (!IS_ERR(reg_rule)) {
5068 -               if (!(reg_rule->flags & NL80211_RRF_PASSIVE_SCAN))
5069 -                       if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
5070 -                               ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
5071 +               if (!(reg_rule->flags & NL80211_RRF_NO_IR))
5072 +                       if (ch->flags & IEEE80211_CHAN_NO_IR)
5073 +                               ch->flags &= ~IEEE80211_CHAN_NO_IR;
5074         }
5075
5076         ch = &sband->channels[12];      /* CH 13 */
5077         reg_rule = freq_reg_info(wiphy, ch->center_freq);
5078         if (!IS_ERR(reg_rule)) {
5079 -               if (!(reg_rule->flags & NL80211_RRF_PASSIVE_SCAN))
5080 -                       if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
5081 -                               ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
5082 +               if (!(reg_rule->flags & NL80211_RRF_NO_IR))
5083 +                       if (ch->flags & IEEE80211_CHAN_NO_IR)
5084 +                               ch->flags &= ~IEEE80211_CHAN_NO_IR;
5085         }
5086  }
5087
5088 @@ -284,8 +280,8 @@ static void _rtl_reg_apply_radar_flags(s
5089                  */
5090                 if (!(ch->flags & IEEE80211_CHAN_DISABLED))
5091                         ch->flags |= IEEE80211_CHAN_RADAR |
5092 -                           IEEE80211_CHAN_NO_IBSS |
5093 -                           IEEE80211_CHAN_PASSIVE_SCAN;
5094 +                           IEEE80211_CHAN_NO_IR |
5095 +                           IEEE80211_CHAN_NO_IR;
5096         }
5097  }
5098
5099 --- a/drivers/net/wireless/ti/wl12xx/scan.c
5100 +++ b/drivers/net/wireless/ti/wl12xx/scan.c
5101 @@ -47,7 +47,7 @@ static int wl1271_get_scan_channels(stru
5102                      * In active scans, we only scan channels not
5103                      * marked as passive.
5104                      */
5105 -                   (passive || !(flags & IEEE80211_CHAN_PASSIVE_SCAN))) {
5106 +                   (passive || !(flags & IEEE80211_CHAN_NO_IR))) {
5107                         wl1271_debug(DEBUG_SCAN, "band %d, center_freq %d ",
5108                                      req->channels[i]->band,
5109                                      req->channels[i]->center_freq);
5110 --- a/drivers/net/wireless/ti/wlcore/cmd.c
5111 +++ b/drivers/net/wireless/ti/wlcore/cmd.c
5112 @@ -1688,7 +1688,7 @@ int wlcore_cmd_regdomain_config_locked(s
5113
5114                         if (channel->flags & (IEEE80211_CHAN_DISABLED |
5115                                               IEEE80211_CHAN_RADAR |
5116 -                                             IEEE80211_CHAN_PASSIVE_SCAN))
5117 +                                             IEEE80211_CHAN_NO_IR))
5118                                 continue;
5119
5120                         ch_bit_idx = wlcore_get_reg_conf_ch_idx(b, ch);
5121 --- a/drivers/net/wireless/ti/wlcore/main.c
5122 +++ b/drivers/net/wireless/ti/wlcore/main.c
5123 @@ -91,8 +91,7 @@ static void wl1271_reg_notify(struct wip
5124                         continue;
5125
5126                 if (ch->flags & IEEE80211_CHAN_RADAR)
5127 -                       ch->flags |= IEEE80211_CHAN_NO_IBSS |
5128 -                                    IEEE80211_CHAN_PASSIVE_SCAN;
5129 +                       ch->flags |= IEEE80211_CHAN_NO_IR;
5130
5131         }
5132
5133 --- a/drivers/net/wireless/ti/wlcore/scan.c
5134 +++ b/drivers/net/wireless/ti/wlcore/scan.c
5135 @@ -189,14 +189,14 @@ wlcore_scan_get_channels(struct wl1271 *
5136                 flags = req_channels[i]->flags;
5137
5138                 if (force_passive)
5139 -                       flags |= IEEE80211_CHAN_PASSIVE_SCAN;
5140 +                       flags |= IEEE80211_CHAN_NO_IR;
5141
5142                 if ((req_channels[i]->band == band) &&
5143                     !(flags & IEEE80211_CHAN_DISABLED) &&
5144                     (!!(flags & IEEE80211_CHAN_RADAR) == radar) &&
5145                     /* if radar is set, we ignore the passive flag */
5146                     (radar ||
5147 -                    !!(flags & IEEE80211_CHAN_PASSIVE_SCAN) == passive)) {
5148 +                    !!(flags & IEEE80211_CHAN_NO_IR) == passive)) {
5149
5150
5151                         if (flags & IEEE80211_CHAN_RADAR) {
5152 @@ -221,7 +221,7 @@ wlcore_scan_get_channels(struct wl1271 *
5153                             (band == IEEE80211_BAND_2GHZ) &&
5154                             (channels[j].channel >= 12) &&
5155                             (channels[j].channel <= 14) &&
5156 -                           (flags & IEEE80211_CHAN_PASSIVE_SCAN) &&
5157 +                           (flags & IEEE80211_CHAN_NO_IR) &&
5158                             !force_passive) {
5159                                 /* pactive channels treated as DFS */
5160                                 channels[j].flags = SCAN_CHANNEL_FLAGS_DFS;
5161 @@ -244,7 +244,7 @@ wlcore_scan_get_channels(struct wl1271 *
5162                                      max_dwell_time_active,
5163                                      flags & IEEE80211_CHAN_RADAR ?
5164                                         ", DFS" : "",
5165 -                                    flags & IEEE80211_CHAN_PASSIVE_SCAN ?
5166 +                                    flags & IEEE80211_CHAN_NO_IR ?
5167                                         ", PASSIVE" : "");
5168                         j++;
5169                 }
5170 --- a/include/net/cfg80211.h
5171 +++ b/include/net/cfg80211.h
5172 @@ -91,9 +91,8 @@ enum ieee80211_band {
5173   * Channel flags set by the regulatory control code.
5174   *
5175   * @IEEE80211_CHAN_DISABLED: This channel is disabled.
5176 - * @IEEE80211_CHAN_PASSIVE_SCAN: Only passive scanning is permitted
5177 - *     on this channel.
5178 - * @IEEE80211_CHAN_NO_IBSS: IBSS is not allowed on this channel.
5179 + * @IEEE80211_CHAN_NO_IR: do not initiate radiation, this includes
5180 + *     sending probe requests or beaconing.
5181   * @IEEE80211_CHAN_RADAR: Radar detection is required on this channel.
5182   * @IEEE80211_CHAN_NO_HT40PLUS: extension channel above this channel
5183   *     is not permitted.
5184 @@ -113,8 +112,8 @@ enum ieee80211_band {
5185   */
5186  enum ieee80211_channel_flags {
5187         IEEE80211_CHAN_DISABLED         = 1<<0,
5188 -       IEEE80211_CHAN_PASSIVE_SCAN     = 1<<1,
5189 -       IEEE80211_CHAN_NO_IBSS          = 1<<2,
5190 +       IEEE80211_CHAN_NO_IR            = 1<<1,
5191 +       /* hole at 1<<2 */
5192         IEEE80211_CHAN_RADAR            = 1<<3,
5193         IEEE80211_CHAN_NO_HT40PLUS      = 1<<4,
5194         IEEE80211_CHAN_NO_HT40MINUS     = 1<<5,
5195 @@ -4149,6 +4148,7 @@ void cfg80211_radar_event(struct wiphy *
5196  /**
5197   * cfg80211_cac_event - Channel availability check (CAC) event
5198   * @netdev: network device
5199 + * @chandef: chandef for the current channel
5200   * @event: type of event
5201   * @gfp: context flags
5202   *
5203 @@ -4157,6 +4157,7 @@ void cfg80211_radar_event(struct wiphy *
5204   * also by full-MAC drivers.
5205   */
5206  void cfg80211_cac_event(struct net_device *netdev,
5207 +                       const struct cfg80211_chan_def *chandef,
5208                         enum nl80211_radar_event event, gfp_t gfp);
5209
5210
5211 @@ -4282,7 +4283,8 @@ bool cfg80211_reg_can_beacon(struct wiph
5212   * @dev: the device which switched channels
5213   * @chandef: the new channel definition
5214   *
5215 - * Acquires wdev_lock, so must only be called from sleepable driver context!
5216 + * Caller must acquire wdev_lock, therefore must only be called from sleepable
5217 + * driver context!
5218   */
5219  void cfg80211_ch_switch_notify(struct net_device *dev,
5220                                struct cfg80211_chan_def *chandef);
5221 --- a/include/uapi/linux/nl80211.h
5222 +++ b/include/uapi/linux/nl80211.h
5223 @@ -1508,6 +1508,12 @@ enum nl80211_commands {
5224   *     to react to radar events, e.g. initiate a channel switch or leave the
5225   *     IBSS network.
5226   *
5227 + * @NL80211_ATTR_SUPPORT_5_MHZ: A flag indicating that the device supports
5228 + *     5 MHz channel bandwidth.
5229 + *
5230 + * @NL80211_ATTR_SUPPORT_10_MHZ: A flag indicating that the device supports
5231 + *     10 MHz channel bandwidth.
5232 + *
5233   * @NL80211_ATTR_MAX: highest attribute number currently defined
5234   * @__NL80211_ATTR_AFTER_LAST: internal use
5235   */
5236 @@ -1824,6 +1830,9 @@ enum nl80211_attrs {
5237
5238         NL80211_ATTR_HANDLE_DFS,
5239
5240 +       NL80211_ATTR_SUPPORT_5_MHZ,
5241 +       NL80211_ATTR_SUPPORT_10_MHZ,
5242 +
5243         /* add attributes here, update the policy in nl80211.c */
5244
5245         __NL80211_ATTR_AFTER_LAST,
5246 @@ -2224,10 +2233,9 @@ enum nl80211_band_attr {
5247   * @NL80211_FREQUENCY_ATTR_FREQ: Frequency in MHz
5248   * @NL80211_FREQUENCY_ATTR_DISABLED: Channel is disabled in current
5249   *     regulatory domain.
5250 - * @NL80211_FREQUENCY_ATTR_PASSIVE_SCAN: Only passive scanning is
5251 - *     permitted on this channel in current regulatory domain.
5252 - * @NL80211_FREQUENCY_ATTR_NO_IBSS: IBSS networks are not permitted
5253 - *     on this channel in current regulatory domain.
5254 + * @NL80211_FREQUENCY_ATTR_NO_IR: no mechanisms that initiate radiation
5255 + *     are permitted on this channel, this includes sending probe
5256 + *     requests, or modes of operation that require beaconing.
5257   * @NL80211_FREQUENCY_ATTR_RADAR: Radar detection is mandatory
5258   *     on this channel in current regulatory domain.
5259   * @NL80211_FREQUENCY_ATTR_MAX_TX_POWER: Maximum transmission power in mBm
5260 @@ -2254,8 +2262,8 @@ enum nl80211_frequency_attr {
5261         __NL80211_FREQUENCY_ATTR_INVALID,
5262         NL80211_FREQUENCY_ATTR_FREQ,
5263         NL80211_FREQUENCY_ATTR_DISABLED,
5264 -       NL80211_FREQUENCY_ATTR_PASSIVE_SCAN,
5265 -       NL80211_FREQUENCY_ATTR_NO_IBSS,
5266 +       NL80211_FREQUENCY_ATTR_NO_IR,
5267 +       __NL80211_FREQUENCY_ATTR_NO_IBSS,
5268         NL80211_FREQUENCY_ATTR_RADAR,
5269         NL80211_FREQUENCY_ATTR_MAX_TX_POWER,
5270         NL80211_FREQUENCY_ATTR_DFS_STATE,
5271 @@ -2271,6 +2279,9 @@ enum nl80211_frequency_attr {
5272  };
5273
5274  #define NL80211_FREQUENCY_ATTR_MAX_TX_POWER NL80211_FREQUENCY_ATTR_MAX_TX_POWER
5275 +#define NL80211_FREQUENCY_ATTR_PASSIVE_SCAN    NL80211_FREQUENCY_ATTR_NO_IR
5276 +#define NL80211_FREQUENCY_ATTR_NO_IBSS         NL80211_FREQUENCY_ATTR_NO_IR
5277 +#define NL80211_FREQUENCY_ATTR_NO_IR           NL80211_FREQUENCY_ATTR_NO_IR
5278
5279  /**
5280   * enum nl80211_bitrate_attr - bitrate attributes
5281 @@ -2413,8 +2424,9 @@ enum nl80211_sched_scan_match_attr {
5282   * @NL80211_RRF_DFS: DFS support is required to be used
5283   * @NL80211_RRF_PTP_ONLY: this is only for Point To Point links
5284   * @NL80211_RRF_PTMP_ONLY: this is only for Point To Multi Point links
5285 - * @NL80211_RRF_PASSIVE_SCAN: passive scan is required
5286 - * @NL80211_RRF_NO_IBSS: no IBSS is allowed
5287 + * @NL80211_RRF_NO_IR: no mechanisms that initiate radiation are allowed,
5288 + *     this includes probe requests or modes of operation that require
5289 + *     beaconing.
5290   */
5291  enum nl80211_reg_rule_flags {
5292         NL80211_RRF_NO_OFDM             = 1<<0,
5293 @@ -2424,10 +2436,17 @@ enum nl80211_reg_rule_flags {
5294         NL80211_RRF_DFS                 = 1<<4,
5295         NL80211_RRF_PTP_ONLY            = 1<<5,
5296         NL80211_RRF_PTMP_ONLY           = 1<<6,
5297 -       NL80211_RRF_PASSIVE_SCAN        = 1<<7,
5298 -       NL80211_RRF_NO_IBSS             = 1<<8,
5299 +       NL80211_RRF_NO_IR               = 1<<7,
5300 +       __NL80211_RRF_NO_IBSS           = 1<<8,
5301  };
5302
5303 +#define NL80211_RRF_PASSIVE_SCAN       NL80211_RRF_NO_IR
5304 +#define NL80211_RRF_NO_IBSS            NL80211_RRF_NO_IR
5305 +#define NL80211_RRF_NO_IR              NL80211_RRF_NO_IR
5306 +
5307 +/* For backport compatibility with older userspace */
5308 +#define NL80211_RRF_NO_IR_ALL          (NL80211_RRF_NO_IR | __NL80211_RRF_NO_IBSS)
5309 +
5310  /**
5311   * enum nl80211_dfs_regions - regulatory DFS regions
5312   *
5313 --- a/net/mac80211/cfg.c
5314 +++ b/net/mac80211/cfg.c
5315 @@ -846,7 +846,7 @@ static int ieee80211_set_probe_resp(stru
5316         if (!resp || !resp_len)
5317                 return 1;
5318
5319 -       old = rtnl_dereference(sdata->u.ap.probe_resp);
5320 +       old = sdata_dereference(sdata->u.ap.probe_resp, sdata);
5321
5322         new = kzalloc(sizeof(struct probe_resp) + resp_len, GFP_KERNEL);
5323         if (!new)
5324 @@ -870,7 +870,8 @@ int ieee80211_assign_beacon(struct ieee8
5325         int size, err;
5326         u32 changed = BSS_CHANGED_BEACON;
5327
5328 -       old = rtnl_dereference(sdata->u.ap.beacon);
5329 +       old = sdata_dereference(sdata->u.ap.beacon, sdata);
5330 +
5331
5332         /* Need to have a beacon head if we don't have one yet */
5333         if (!params->head && !old)
5334 @@ -947,7 +948,7 @@ static int ieee80211_start_ap(struct wip
5335                       BSS_CHANGED_P2P_PS;
5336         int err;
5337
5338 -       old = rtnl_dereference(sdata->u.ap.beacon);
5339 +       old = sdata_dereference(sdata->u.ap.beacon, sdata);
5340         if (old)
5341                 return -EALREADY;
5342
5343 @@ -1001,7 +1002,8 @@ static int ieee80211_start_ap(struct wip
5344
5345         err = drv_start_ap(sdata->local, sdata);
5346         if (err) {
5347 -               old = rtnl_dereference(sdata->u.ap.beacon);
5348 +               old = sdata_dereference(sdata->u.ap.beacon, sdata);
5349 +
5350                 if (old)
5351                         kfree_rcu(old, rcu_head);
5352                 RCU_INIT_POINTER(sdata->u.ap.beacon, NULL);
5353 @@ -1032,7 +1034,7 @@ static int ieee80211_change_beacon(struc
5354         if (sdata->vif.csa_active)
5355                 return -EBUSY;
5356
5357 -       old = rtnl_dereference(sdata->u.ap.beacon);
5358 +       old = sdata_dereference(sdata->u.ap.beacon, sdata);
5359         if (!old)
5360                 return -ENOENT;
5361
5362 @@ -1050,15 +1052,18 @@ static int ieee80211_stop_ap(struct wiph
5363         struct ieee80211_local *local = sdata->local;
5364         struct beacon_data *old_beacon;
5365         struct probe_resp *old_probe_resp;
5366 +       struct cfg80211_chan_def chandef;
5367
5368 -       old_beacon = rtnl_dereference(sdata->u.ap.beacon);
5369 +       old_beacon = sdata_dereference(sdata->u.ap.beacon, sdata);
5370         if (!old_beacon)
5371                 return -ENOENT;
5372 -       old_probe_resp = rtnl_dereference(sdata->u.ap.probe_resp);
5373 +       old_probe_resp = sdata_dereference(sdata->u.ap.probe_resp, sdata);
5374
5375         /* abort any running channel switch */
5376         sdata->vif.csa_active = false;
5377 -       cancel_work_sync(&sdata->csa_finalize_work);
5378 +       kfree(sdata->u.ap.next_beacon);
5379 +       sdata->u.ap.next_beacon = NULL;
5380 +
5381         cancel_work_sync(&sdata->u.ap.request_smps_work);
5382
5383         /* turn off carrier for this interface and dependent VLANs */
5384 @@ -1091,8 +1096,10 @@ static int ieee80211_stop_ap(struct wiph
5385         ieee80211_bss_info_change_notify(sdata, BSS_CHANGED_BEACON_ENABLED);
5386
5387         if (sdata->wdev.cac_started) {
5388 +               chandef = sdata->vif.bss_conf.chandef;
5389                 cancel_delayed_work_sync(&sdata->dfs_cac_timer_work);
5390 -               cfg80211_cac_event(sdata->dev, NL80211_RADAR_CAC_ABORTED,
5391 +               cfg80211_cac_event(sdata->dev, &chandef,
5392 +                                  NL80211_RADAR_CAC_ABORTED,
5393                                    GFP_KERNEL);
5394         }
5395
5396 @@ -1368,7 +1375,7 @@ static int sta_apply_parameters(struct i
5397                         changed |=
5398                               ieee80211_mps_set_sta_local_pm(sta,
5399                                                              params->local_pm);
5400 -               ieee80211_bss_info_change_notify(sdata, changed);
5401 +               ieee80211_mbss_info_change_notify(sdata, changed);
5402  #endif
5403         }
5404
5405 @@ -1953,7 +1960,7 @@ static int ieee80211_change_bss(struct w
5406         enum ieee80211_band band;
5407         u32 changed = 0;
5408
5409 -       if (!rtnl_dereference(sdata->u.ap.beacon))
5410 +       if (!sdata_dereference(sdata->u.ap.beacon, sdata))
5411                 return -ENOENT;
5412
5413         band = ieee80211_get_sdata_band(sdata);
5414 @@ -2964,27 +2971,33 @@ void ieee80211_csa_finalize_work(struct
5415         struct ieee80211_local *local = sdata->local;
5416         int err, changed = 0;
5417
5418 +       sdata_lock(sdata);
5419 +       /* AP might have been stopped while waiting for the lock. */
5420 +       if (!sdata->vif.csa_active)
5421 +               goto unlock;
5422 +
5423         if (!ieee80211_sdata_running(sdata))
5424 -               return;
5425 +               goto unlock;
5426
5427         sdata->radar_required = sdata->csa_radar_required;
5428 -       err = ieee80211_vif_change_channel(sdata, &local->csa_chandef,
5429 -                                          &changed);
5430 +       err = ieee80211_vif_change_channel(sdata, &changed);
5431         if (WARN_ON(err < 0))
5432 -               return;
5433 +               goto unlock;
5434
5435         if (!local->use_chanctx) {
5436 -               local->_oper_chandef = local->csa_chandef;
5437 +               local->_oper_chandef = sdata->csa_chandef;
5438                 ieee80211_hw_config(local, 0);
5439         }
5440
5441         ieee80211_bss_info_change_notify(sdata, changed);
5442
5443 +       sdata->vif.csa_active = false;
5444         switch (sdata->vif.type) {
5445         case NL80211_IFTYPE_AP:
5446                 err = ieee80211_assign_beacon(sdata, sdata->u.ap.next_beacon);
5447                 if (err < 0)
5448 -                       return;
5449 +                       goto unlock;
5450 +
5451                 changed |= err;
5452                 kfree(sdata->u.ap.next_beacon);
5453                 sdata->u.ap.next_beacon = NULL;
5454 @@ -2998,20 +3011,22 @@ void ieee80211_csa_finalize_work(struct
5455         case NL80211_IFTYPE_MESH_POINT:
5456                 err = ieee80211_mesh_finish_csa(sdata);
5457                 if (err < 0)
5458 -                       return;
5459 +                       goto unlock;
5460                 break;
5461  #endif
5462         default:
5463                 WARN_ON(1);
5464 -               return;
5465 +               goto unlock;
5466         }
5467 -       sdata->vif.csa_active = false;
5468
5469         ieee80211_wake_queues_by_reason(&sdata->local->hw,
5470                                         IEEE80211_MAX_QUEUE_MAP,
5471                                         IEEE80211_QUEUE_STOP_REASON_CSA);
5472
5473 -       cfg80211_ch_switch_notify(sdata->dev, &local->csa_chandef);
5474 +       cfg80211_ch_switch_notify(sdata->dev, &sdata->csa_chandef);
5475 +
5476 +unlock:
5477 +       sdata_unlock(sdata);
5478  }
5479
5480  static int ieee80211_channel_switch(struct wiphy *wiphy, struct net_device *dev,
5481 @@ -3024,6 +3039,8 @@ static int ieee80211_channel_switch(stru
5482         struct ieee80211_if_mesh __maybe_unused *ifmsh;
5483         int err, num_chanctx;
5484
5485 +       lockdep_assert_held(&sdata->wdev.mtx);
5486 +
5487         if (!list_empty(&local->roc_list) || local->scanning)
5488                 return -EBUSY;
5489
5490 @@ -3120,9 +3137,17 @@ static int ieee80211_channel_switch(stru
5491                     params->chandef.chan->band)
5492                         return -EINVAL;
5493
5494 +               ifmsh->chsw_init = true;
5495 +               if (!ifmsh->pre_value)
5496 +                       ifmsh->pre_value = 1;
5497 +               else
5498 +                       ifmsh->pre_value++;
5499 +
5500                 err = ieee80211_mesh_csa_beacon(sdata, params, true);
5501 -               if (err < 0)
5502 +               if (err < 0) {
5503 +                       ifmsh->chsw_init = false;
5504                         return err;
5505 +               }
5506                 break;
5507  #endif
5508         default:
5509 @@ -3136,7 +3161,7 @@ static int ieee80211_channel_switch(stru
5510                                 IEEE80211_MAX_QUEUE_MAP,
5511                                 IEEE80211_QUEUE_STOP_REASON_CSA);
5512
5513 -       local->csa_chandef = params->chandef;
5514 +       sdata->csa_chandef = params->chandef;
5515         sdata->vif.csa_active = true;
5516
5517         ieee80211_bss_info_change_notify(sdata, err);
5518 --- a/net/mac80211/iface.c
5519 +++ b/net/mac80211/iface.c
5520 @@ -749,6 +749,7 @@ static void ieee80211_do_stop(struct iee
5521         u32 hw_reconf_flags = 0;
5522         int i, flushed;
5523         struct ps_data *ps;
5524 +       struct cfg80211_chan_def chandef;
5525
5526         clear_bit(SDATA_STATE_RUNNING, &sdata->state);
5527
5528 @@ -828,11 +829,13 @@ static void ieee80211_do_stop(struct iee
5529         cancel_delayed_work_sync(&sdata->dfs_cac_timer_work);
5530
5531         if (sdata->wdev.cac_started) {
5532 +               chandef = sdata->vif.bss_conf.chandef;
5533                 WARN_ON(local->suspended);
5534                 mutex_lock(&local->iflist_mtx);
5535                 ieee80211_vif_release_channel(sdata);
5536                 mutex_unlock(&local->iflist_mtx);
5537 -               cfg80211_cac_event(sdata->dev, NL80211_RADAR_CAC_ABORTED,
5538 +               cfg80211_cac_event(sdata->dev, &chandef,
5539 +                                  NL80211_RADAR_CAC_ABORTED,
5540                                    GFP_KERNEL);
5541         }
5542
5543 @@ -1340,7 +1343,6 @@ static void ieee80211_setup_sdata(struct
5544                 sdata->vif.bss_conf.bssid = NULL;
5545                 break;
5546         case NL80211_IFTYPE_AP_VLAN:
5547 -               break;
5548         case NL80211_IFTYPE_P2P_DEVICE:
5549                 sdata->vif.bss_conf.bssid = sdata->vif.addr;
5550                 break;
5551 --- a/net/mac80211/mlme.c
5552 +++ b/net/mac80211/mlme.c
5553 @@ -886,8 +886,7 @@ static void ieee80211_chswitch_work(stru
5554         if (!ifmgd->associated)
5555                 goto out;
5556
5557 -       ret = ieee80211_vif_change_channel(sdata, &local->csa_chandef,
5558 -                                          &changed);
5559 +       ret = ieee80211_vif_change_channel(sdata, &changed);
5560         if (ret) {
5561                 sdata_info(sdata,
5562                            "vif channel switch failed, disconnecting\n");
5563 @@ -897,7 +896,7 @@ static void ieee80211_chswitch_work(stru
5564         }
5565
5566         if (!local->use_chanctx) {
5567 -               local->_oper_chandef = local->csa_chandef;
5568 +               local->_oper_chandef = sdata->csa_chandef;
5569                 /* Call "hw_config" only if doing sw channel switch.
5570                  * Otherwise update the channel directly
5571                  */
5572 @@ -908,7 +907,7 @@ static void ieee80211_chswitch_work(stru
5573         }
5574
5575         /* XXX: shouldn't really modify cfg80211-owned data! */
5576 -       ifmgd->associated->channel = local->csa_chandef.chan;
5577 +       ifmgd->associated->channel = sdata->csa_chandef.chan;
5578
5579         /* XXX: wait for a beacon first? */
5580         ieee80211_wake_queues_by_reason(&local->hw,
5581 @@ -1035,7 +1034,7 @@ ieee80211_sta_process_chanswitch(struct
5582         }
5583         mutex_unlock(&local->chanctx_mtx);
5584
5585 -       local->csa_chandef = csa_ie.chandef;
5586 +       sdata->csa_chandef = csa_ie.chandef;
5587
5588         if (csa_ie.mode)
5589                 ieee80211_stop_queues_by_reason(&local->hw,
5590 @@ -1398,10 +1397,12 @@ void ieee80211_dfs_cac_timer_work(struct
5591         struct ieee80211_sub_if_data *sdata =
5592                 container_of(delayed_work, struct ieee80211_sub_if_data,
5593                              dfs_cac_timer_work);
5594 +       struct cfg80211_chan_def chandef = sdata->vif.bss_conf.chandef;
5595
5596         ieee80211_vif_release_channel(sdata);
5597 -
5598 -       cfg80211_cac_event(sdata->dev, NL80211_RADAR_CAC_FINISHED, GFP_KERNEL);
5599 +       cfg80211_cac_event(sdata->dev, &chandef,
5600 +                          NL80211_RADAR_CAC_FINISHED,
5601 +                          GFP_KERNEL);
5602  }
5603
5604  /* MLME */
5605 --- a/net/mac80211/rx.c
5606 +++ b/net/mac80211/rx.c
5607 @@ -729,9 +729,7 @@ static void ieee80211_release_reorder_fr
5608         lockdep_assert_held(&tid_agg_rx->reorder_lock);
5609
5610         while (ieee80211_sn_less(tid_agg_rx->head_seq_num, head_seq_num)) {
5611 -               index = ieee80211_sn_sub(tid_agg_rx->head_seq_num,
5612 -                                        tid_agg_rx->ssn) %
5613 -                                                       tid_agg_rx->buf_size;
5614 +               index = tid_agg_rx->head_seq_num % tid_agg_rx->buf_size;
5615                 ieee80211_release_reorder_frame(sdata, tid_agg_rx, index,
5616                                                 frames);
5617         }
5618 @@ -757,8 +755,7 @@ static void ieee80211_sta_reorder_releas
5619         lockdep_assert_held(&tid_agg_rx->reorder_lock);
5620
5621         /* release the buffer until next missing frame */
5622 -       index = ieee80211_sn_sub(tid_agg_rx->head_seq_num,
5623 -                                tid_agg_rx->ssn) % tid_agg_rx->buf_size;
5624 +       index = tid_agg_rx->head_seq_num % tid_agg_rx->buf_size;
5625         if (!tid_agg_rx->reorder_buf[index] &&
5626             tid_agg_rx->stored_mpdu_num) {
5627                 /*
5628 @@ -793,15 +790,11 @@ static void ieee80211_sta_reorder_releas
5629         } else while (tid_agg_rx->reorder_buf[index]) {
5630                 ieee80211_release_reorder_frame(sdata, tid_agg_rx, index,
5631                                                 frames);
5632 -               index = ieee80211_sn_sub(tid_agg_rx->head_seq_num,
5633 -                                        tid_agg_rx->ssn) %
5634 -                                                       tid_agg_rx->buf_size;
5635 +               index = tid_agg_rx->head_seq_num % tid_agg_rx->buf_size;
5636         }
5637
5638         if (tid_agg_rx->stored_mpdu_num) {
5639 -               j = index = ieee80211_sn_sub(tid_agg_rx->head_seq_num,
5640 -                                            tid_agg_rx->ssn) %
5641 -                                                       tid_agg_rx->buf_size;
5642 +               j = index = tid_agg_rx->head_seq_num % tid_agg_rx->buf_size;
5643
5644                 for (; j != (index - 1) % tid_agg_rx->buf_size;
5645                      j = (j + 1) % tid_agg_rx->buf_size) {
5646 @@ -861,8 +854,7 @@ static bool ieee80211_sta_manage_reorder
5647
5648         /* Now the new frame is always in the range of the reordering buffer */
5649
5650 -       index = ieee80211_sn_sub(mpdu_seq_num,
5651 -                                tid_agg_rx->ssn) % tid_agg_rx->buf_size;
5652 +       index = mpdu_seq_num % tid_agg_rx->buf_size;
5653
5654         /* check if we already stored this frame */
5655         if (tid_agg_rx->reorder_buf[index]) {
5656 @@ -911,7 +903,8 @@ static void ieee80211_rx_reorder_ampdu(s
5657         u16 sc;
5658         u8 tid, ack_policy;
5659
5660 -       if (!ieee80211_is_data_qos(hdr->frame_control))
5661 +       if (!ieee80211_is_data_qos(hdr->frame_control) ||
5662 +           is_multicast_ether_addr(hdr->addr1))
5663                 goto dont_reorder;
5664
5665         /*
5666 --- a/net/mac80211/scan.c
5667 +++ b/net/mac80211/scan.c
5668 @@ -526,7 +526,7 @@ static int __ieee80211_start_scan(struct
5669                 ieee80211_hw_config(local, 0);
5670
5671                 if ((req->channels[0]->flags &
5672 -                    IEEE80211_CHAN_PASSIVE_SCAN) ||
5673 +                    IEEE80211_CHAN_NO_IR) ||
5674                     !local->scan_req->n_ssids) {
5675                         next_delay = IEEE80211_PASSIVE_CHANNEL_TIME;
5676                 } else {
5677 @@ -572,7 +572,7 @@ ieee80211_scan_get_channel_time(struct i
5678          * TODO: channel switching also consumes quite some time,
5679          * add that delay as well to get a better estimation
5680          */
5681 -       if (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN)
5682 +       if (chan->flags & IEEE80211_CHAN_NO_IR)
5683                 return IEEE80211_PASSIVE_CHANNEL_TIME;
5684         return IEEE80211_PROBE_DELAY + IEEE80211_CHANNEL_TIME;
5685  }
5686 @@ -696,7 +696,7 @@ static void ieee80211_scan_state_set_cha
5687          *
5688          * In any case, it is not necessary for a passive scan.
5689          */
5690 -       if (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN ||
5691 +       if (chan->flags & IEEE80211_CHAN_NO_IR ||
5692             !local->scan_req->n_ssids) {
5693                 *next_delay = IEEE80211_PASSIVE_CHANNEL_TIME;
5694                 local->next_scan_state = SCAN_DECISION;
5695 @@ -881,7 +881,7 @@ int ieee80211_request_ibss_scan(struct i
5696                                 struct ieee80211_channel *tmp_ch =
5697                                     &local->hw.wiphy->bands[band]->channels[i];
5698
5699 -                               if (tmp_ch->flags & (IEEE80211_CHAN_NO_IBSS |
5700 +                               if (tmp_ch->flags & (IEEE80211_CHAN_NO_IR |
5701                                                      IEEE80211_CHAN_DISABLED))
5702                                         continue;
5703
5704 @@ -895,7 +895,7 @@ int ieee80211_request_ibss_scan(struct i
5705
5706                 local->int_scan_req->n_channels = n_ch;
5707         } else {
5708 -               if (WARN_ON_ONCE(chan->flags & (IEEE80211_CHAN_NO_IBSS |
5709 +               if (WARN_ON_ONCE(chan->flags & (IEEE80211_CHAN_NO_IR |
5710                                                 IEEE80211_CHAN_DISABLED)))
5711                         goto unlock;
5712
5713 --- a/net/mac80211/tx.c
5714 +++ b/net/mac80211/tx.c
5715 @@ -463,7 +463,6 @@ ieee80211_tx_h_unicast_ps_buf(struct iee
5716  {
5717         struct sta_info *sta = tx->sta;
5718         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx->skb);
5719 -       struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)tx->skb->data;
5720         struct ieee80211_local *local = tx->local;
5721
5722         if (unlikely(!sta))
5723 @@ -474,15 +473,6 @@ ieee80211_tx_h_unicast_ps_buf(struct iee
5724                      !(info->flags & IEEE80211_TX_CTL_NO_PS_BUFFER))) {
5725                 int ac = skb_get_queue_mapping(tx->skb);
5726
5727 -               /* only deauth, disassoc and action are bufferable MMPDUs */
5728 -               if (ieee80211_is_mgmt(hdr->frame_control) &&
5729 -                   !ieee80211_is_deauth(hdr->frame_control) &&
5730 -                   !ieee80211_is_disassoc(hdr->frame_control) &&
5731 -                   !ieee80211_is_action(hdr->frame_control)) {
5732 -                       info->flags |= IEEE80211_TX_CTL_NO_PS_BUFFER;
5733 -                       return TX_CONTINUE;
5734 -               }
5735 -
5736                 ps_dbg(sta->sdata, "STA %pM aid %d: PS buffer for AC %d\n",
5737                        sta->sta.addr, sta->sta.aid, ac);
5738                 if (tx->local->total_ps_buffered >= TOTAL_MAX_TX_BUFFER)
5739 @@ -525,9 +515,21 @@ ieee80211_tx_h_unicast_ps_buf(struct iee
5740  static ieee80211_tx_result debug_noinline
5741  ieee80211_tx_h_ps_buf(struct ieee80211_tx_data *tx)
5742  {
5743 +       struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx->skb);
5744 +       struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)tx->skb->data;
5745 +
5746         if (unlikely(tx->flags & IEEE80211_TX_PS_BUFFERED))
5747                 return TX_CONTINUE;
5748
5749 +       /* only deauth, disassoc and action are bufferable MMPDUs */
5750 +       if (ieee80211_is_mgmt(hdr->frame_control) &&
5751 +           !ieee80211_is_deauth(hdr->frame_control) &&
5752 +           !ieee80211_is_disassoc(hdr->frame_control) &&
5753 +           !ieee80211_is_action(hdr->frame_control)) {
5754 +               info->flags |= IEEE80211_TX_CTL_NO_PS_BUFFER;
5755 +               return TX_CONTINUE;
5756 +       }
5757 +
5758         if (tx->flags & IEEE80211_TX_UNICAST)
5759                 return ieee80211_tx_h_unicast_ps_buf(tx);
5760         else
5761 @@ -1728,8 +1730,7 @@ netdev_tx_t ieee80211_monitor_start_xmit
5762          * radar detection by itself. We can do that later by adding a
5763          * monitor flag interfaces used for AP support.
5764          */
5765 -       if ((chan->flags & (IEEE80211_CHAN_NO_IBSS | IEEE80211_CHAN_RADAR |
5766 -                           IEEE80211_CHAN_PASSIVE_SCAN)))
5767 +       if ((chan->flags & (IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_RADAR)))
5768                 goto fail_rcu;
5769
5770         ieee80211_xmit(sdata, skb, chan->band);
5771 @@ -2530,7 +2531,8 @@ struct sk_buff *ieee80211_beacon_get_tim
5772                          */
5773                         skb = dev_alloc_skb(local->tx_headroom +
5774                                             beacon->head_len +
5775 -                                           beacon->tail_len + 256);
5776 +                                           beacon->tail_len + 256 +
5777 +                                           local->hw.extra_beacon_tailroom);
5778                         if (!skb)
5779                                 goto out;
5780
5781 @@ -2562,7 +2564,8 @@ struct sk_buff *ieee80211_beacon_get_tim
5782                         ieee80211_update_csa(sdata, presp);
5783
5784
5785 -               skb = dev_alloc_skb(local->tx_headroom + presp->head_len);
5786 +               skb = dev_alloc_skb(local->tx_headroom + presp->head_len +
5787 +                                   local->hw.extra_beacon_tailroom);
5788                 if (!skb)
5789                         goto out;
5790                 skb_reserve(skb, local->tx_headroom);
5791 @@ -2589,7 +2592,8 @@ struct sk_buff *ieee80211_beacon_get_tim
5792                 skb = dev_alloc_skb(local->tx_headroom +
5793                                     bcn->head_len +
5794                                     256 + /* TIM IE */
5795 -                                   bcn->tail_len);
5796 +                                   bcn->tail_len +
5797 +                                   local->hw.extra_beacon_tailroom);
5798                 if (!skb)
5799                         goto out;
5800                 skb_reserve(skb, local->tx_headroom);
5801 --- a/net/mac80211/util.c
5802 +++ b/net/mac80211/util.c
5803 @@ -2259,14 +2259,17 @@ u64 ieee80211_calculate_rx_timestamp(str
5804  void ieee80211_dfs_cac_cancel(struct ieee80211_local *local)
5805  {
5806         struct ieee80211_sub_if_data *sdata;
5807 +       struct cfg80211_chan_def chandef;
5808
5809         mutex_lock(&local->iflist_mtx);
5810         list_for_each_entry(sdata, &local->interfaces, list) {
5811                 cancel_delayed_work_sync(&sdata->dfs_cac_timer_work);
5812
5813                 if (sdata->wdev.cac_started) {
5814 +                       chandef = sdata->vif.bss_conf.chandef;
5815                         ieee80211_vif_release_channel(sdata);
5816                         cfg80211_cac_event(sdata->dev,
5817 +                                          &chandef,
5818                                            NL80211_RADAR_CAC_ABORTED,
5819                                            GFP_KERNEL);
5820                 }
5821 @@ -2459,16 +2462,146 @@ int ieee80211_send_action_csa(struct iee
5822                           WLAN_EID_CHAN_SWITCH_PARAM_TX_RESTRICT : 0x00;
5823                 put_unaligned_le16(WLAN_REASON_MESH_CHAN, pos); /* Reason Cd */
5824                 pos += 2;
5825 -               if (!ifmsh->pre_value)
5826 -                       ifmsh->pre_value = 1;
5827 -               else
5828 -                       ifmsh->pre_value++;
5829                 pre_value = cpu_to_le16(ifmsh->pre_value);
5830                 memcpy(pos, &pre_value, 2);             /* Precedence Value */
5831                 pos += 2;
5832 -               ifmsh->chsw_init = true;
5833         }
5834
5835         ieee80211_tx_skb(sdata, skb);
5836         return 0;
5837  }
5838 +
5839 +static bool
5840 +ieee80211_extend_noa_desc(struct ieee80211_noa_data *data, u32 tsf, int i)
5841 +{
5842 +       s32 end = data->desc[i].start + data->desc[i].duration - (tsf + 1);
5843 +       int skip;
5844 +
5845 +       if (end > 0)
5846 +               return false;
5847 +
5848 +       /* End time is in the past, check for repetitions */
5849 +       skip = DIV_ROUND_UP(-end, data->desc[i].interval);
5850 +       if (data->count[i] < 255) {
5851 +               if (data->count[i] <= skip) {
5852 +                       data->count[i] = 0;
5853 +                       return false;
5854 +               }
5855 +
5856 +               data->count[i] -= skip;
5857 +       }
5858 +
5859 +       data->desc[i].start += skip * data->desc[i].interval;
5860 +
5861 +       return true;
5862 +}
5863 +
5864 +static bool
5865 +ieee80211_extend_absent_time(struct ieee80211_noa_data *data, u32 tsf,
5866 +                            s32 *offset)
5867 +{
5868 +       bool ret = false;
5869 +       int i;
5870 +
5871 +       for (i = 0; i < IEEE80211_P2P_NOA_DESC_MAX; i++) {
5872 +               s32 cur;
5873 +
5874 +               if (!data->count[i])
5875 +                       continue;
5876 +
5877 +               if (ieee80211_extend_noa_desc(data, tsf + *offset, i))
5878 +                       ret = true;
5879 +
5880 +               cur = data->desc[i].start - tsf;
5881 +               if (cur > *offset)
5882 +                       continue;
5883 +
5884 +               cur = data->desc[i].start + data->desc[i].duration - tsf;
5885 +               if (cur > *offset)
5886 +                       *offset = cur;
5887 +       }
5888 +
5889 +       return ret;
5890 +}
5891 +
5892 +static u32
5893 +ieee80211_get_noa_absent_time(struct ieee80211_noa_data *data, u32 tsf)
5894 +{
5895 +       s32 offset = 0;
5896 +       int tries = 0;
5897 +
5898 +       ieee80211_extend_absent_time(data, tsf, &offset);
5899 +       do {
5900 +               if (!ieee80211_extend_absent_time(data, tsf, &offset))
5901 +                       break;
5902 +
5903 +               tries++;
5904 +       } while (tries < 5);
5905 +
5906 +       return offset;
5907 +}
5908 +
5909 +void ieee80211_update_p2p_noa(struct ieee80211_noa_data *data, u32 tsf)
5910 +{
5911 +       u32 next_offset = BIT(31) - 1;
5912 +       int i;
5913 +
5914 +       data->absent = 0;
5915 +       data->has_next_tsf = false;
5916 +       for (i = 0; i < IEEE80211_P2P_NOA_DESC_MAX; i++) {
5917 +               s32 start;
5918 +
5919 +               if (!data->count[i])
5920 +                       continue;
5921 +
5922 +               ieee80211_extend_noa_desc(data, tsf, i);
5923 +               start = data->desc[i].start - tsf;
5924 +               if (start <= 0)
5925 +                       data->absent |= BIT(i);
5926 +
5927 +               if (next_offset > start)
5928 +                       next_offset = start;
5929 +
5930 +               data->has_next_tsf = true;
5931 +       }
5932 +
5933 +       if (data->absent)
5934 +               next_offset = ieee80211_get_noa_absent_time(data, tsf);
5935 +
5936 +       data->next_tsf = tsf + next_offset;
5937 +}
5938 +EXPORT_SYMBOL(ieee80211_update_p2p_noa);
5939 +
5940 +int ieee80211_parse_p2p_noa(const struct ieee80211_p2p_noa_attr *attr,
5941 +                           struct ieee80211_noa_data *data, u32 tsf)
5942 +{
5943 +       int ret = 0;
5944 +       int i;
5945 +
5946 +       memset(data, 0, sizeof(*data));
5947 +
5948 +       for (i = 0; i < IEEE80211_P2P_NOA_DESC_MAX; i++) {
5949 +               const struct ieee80211_p2p_noa_desc *desc = &attr->desc[i];
5950 +
5951 +               if (!desc->count || !desc->duration)
5952 +                       continue;
5953 +
5954 +               data->count[i] = desc->count;
5955 +               data->desc[i].start = le32_to_cpu(desc->start_time);
5956 +               data->desc[i].duration = le32_to_cpu(desc->duration);
5957 +               data->desc[i].interval = le32_to_cpu(desc->interval);
5958 +
5959 +               if (data->count[i] > 1 &&
5960 +                   data->desc[i].interval < data->desc[i].duration)
5961 +                       continue;
5962 +
5963 +               ieee80211_extend_noa_desc(data, tsf, i);
5964 +               ret++;
5965 +       }
5966 +
5967 +       if (ret)
5968 +               ieee80211_update_p2p_noa(data, tsf);
5969 +
5970 +       return ret;
5971 +}
5972 +EXPORT_SYMBOL(ieee80211_parse_p2p_noa);
5973 --- a/net/wireless/chan.c
5974 +++ b/net/wireless/chan.c
5975 @@ -277,6 +277,32 @@ void cfg80211_set_dfs_state(struct wiphy
5976                                      width, dfs_state);
5977  }
5978
5979 +static u32 cfg80211_get_start_freq(u32 center_freq,
5980 +                                  u32 bandwidth)
5981 +{
5982 +       u32 start_freq;
5983 +
5984 +       if (bandwidth <= 20)
5985 +               start_freq = center_freq;
5986 +       else
5987 +               start_freq = center_freq - bandwidth/2 + 10;
5988 +
5989 +       return start_freq;
5990 +}
5991 +
5992 +static u32 cfg80211_get_end_freq(u32 center_freq,
5993 +                                u32 bandwidth)
5994 +{
5995 +       u32 end_freq;
5996 +
5997 +       if (bandwidth <= 20)
5998 +               end_freq = center_freq;
5999 +       else
6000 +               end_freq = center_freq + bandwidth/2 - 10;
6001 +
6002 +       return end_freq;
6003 +}
6004 +
6005  static int cfg80211_get_chans_dfs_required(struct wiphy *wiphy,
6006                                             u32 center_freq,
6007                                             u32 bandwidth)
6008 @@ -284,13 +310,8 @@ static int cfg80211_get_chans_dfs_requir
6009         struct ieee80211_channel *c;
6010         u32 freq, start_freq, end_freq;
6011
6012 -       if (bandwidth <= 20) {
6013 -               start_freq = center_freq;
6014 -               end_freq = center_freq;
6015 -       } else {
6016 -               start_freq = center_freq - bandwidth/2 + 10;
6017 -               end_freq = center_freq + bandwidth/2 - 10;
6018 -       }
6019 +       start_freq = cfg80211_get_start_freq(center_freq, bandwidth);
6020 +       end_freq = cfg80211_get_end_freq(center_freq, bandwidth);
6021
6022         for (freq = start_freq; freq <= end_freq; freq += 20) {
6023                 c = ieee80211_get_channel(wiphy, freq);
6024 @@ -330,33 +351,159 @@ int cfg80211_chandef_dfs_required(struct
6025  }
6026  EXPORT_SYMBOL(cfg80211_chandef_dfs_required);
6027
6028 -static bool cfg80211_secondary_chans_ok(struct wiphy *wiphy,
6029 -                                       u32 center_freq, u32 bandwidth,
6030 -                                       u32 prohibited_flags)
6031 +static int cfg80211_get_chans_dfs_usable(struct wiphy *wiphy,
6032 +                                        u32 center_freq,
6033 +                                        u32 bandwidth)
6034  {
6035         struct ieee80211_channel *c;
6036         u32 freq, start_freq, end_freq;
6037 +       int count = 0;
6038
6039 -       if (bandwidth <= 20) {
6040 -               start_freq = center_freq;
6041 -               end_freq = center_freq;
6042 -       } else {
6043 -               start_freq = center_freq - bandwidth/2 + 10;
6044 -               end_freq = center_freq + bandwidth/2 - 10;
6045 +       start_freq = cfg80211_get_start_freq(center_freq, bandwidth);
6046 +       end_freq = cfg80211_get_end_freq(center_freq, bandwidth);
6047 +
6048 +       /*
6049 +        * Check entire range of channels for the bandwidth.
6050 +        * Check all channels are DFS channels (DFS_USABLE or
6051 +        * DFS_AVAILABLE). Return number of usable channels
6052 +        * (require CAC). Allow DFS and non-DFS channel mix.
6053 +        */
6054 +       for (freq = start_freq; freq <= end_freq; freq += 20) {
6055 +               c = ieee80211_get_channel(wiphy, freq);
6056 +               if (!c)
6057 +                       return -EINVAL;
6058 +
6059 +               if (c->flags & IEEE80211_CHAN_DISABLED)
6060 +                       return -EINVAL;
6061 +
6062 +               if (c->flags & IEEE80211_CHAN_RADAR) {
6063 +                       if (c->dfs_state == NL80211_DFS_UNAVAILABLE)
6064 +                               return -EINVAL;
6065 +
6066 +                       if (c->dfs_state == NL80211_DFS_USABLE)
6067 +                               count++;
6068 +               }
6069 +       }
6070 +
6071 +       return count;
6072 +}
6073 +
6074 +bool cfg80211_chandef_dfs_usable(struct wiphy *wiphy,
6075 +                                const struct cfg80211_chan_def *chandef)
6076 +{
6077 +       int width;
6078 +       int r1, r2 = 0;
6079 +
6080 +       if (WARN_ON(!cfg80211_chandef_valid(chandef)))
6081 +               return false;
6082 +
6083 +       width = cfg80211_chandef_get_width(chandef);
6084 +       if (width < 0)
6085 +               return false;
6086 +
6087 +       r1 = cfg80211_get_chans_dfs_usable(wiphy, chandef->center_freq1,
6088 +                                         width);
6089 +
6090 +       if (r1 < 0)
6091 +               return false;
6092 +
6093 +       switch (chandef->width) {
6094 +       case NL80211_CHAN_WIDTH_80P80:
6095 +               WARN_ON(!chandef->center_freq2);
6096 +               r2 = cfg80211_get_chans_dfs_usable(wiphy,
6097 +                                                  chandef->center_freq2,
6098 +                                                  width);
6099 +               if (r2 < 0)
6100 +                       return false;
6101 +               break;
6102 +       default:
6103 +               WARN_ON(chandef->center_freq2);
6104 +               break;
6105         }
6106
6107 +       return (r1 + r2 > 0);
6108 +}
6109 +
6110 +
6111 +static bool cfg80211_get_chans_dfs_available(struct wiphy *wiphy,
6112 +                                            u32 center_freq,
6113 +                                            u32 bandwidth)
6114 +{
6115 +       struct ieee80211_channel *c;
6116 +       u32 freq, start_freq, end_freq;
6117 +
6118 +       start_freq = cfg80211_get_start_freq(center_freq, bandwidth);
6119 +       end_freq = cfg80211_get_end_freq(center_freq, bandwidth);
6120 +
6121 +       /*
6122 +        * Check entire range of channels for the bandwidth.
6123 +        * If any channel in between is disabled or has not
6124 +        * had gone through CAC return false
6125 +        */
6126         for (freq = start_freq; freq <= end_freq; freq += 20) {
6127                 c = ieee80211_get_channel(wiphy, freq);
6128                 if (!c)
6129                         return false;
6130
6131 -               /* check for radar flags */
6132 -               if ((prohibited_flags & c->flags & IEEE80211_CHAN_RADAR) &&
6133 +               if (c->flags & IEEE80211_CHAN_DISABLED)
6134 +                       return false;
6135 +
6136 +               if ((c->flags & IEEE80211_CHAN_RADAR)  &&
6137                     (c->dfs_state != NL80211_DFS_AVAILABLE))
6138                         return false;
6139 +       }
6140 +
6141 +       return true;
6142 +}
6143 +
6144 +static bool cfg80211_chandef_dfs_available(struct wiphy *wiphy,
6145 +                               const struct cfg80211_chan_def *chandef)
6146 +{
6147 +       int width;
6148 +       int r;
6149 +
6150 +       if (WARN_ON(!cfg80211_chandef_valid(chandef)))
6151 +               return false;
6152
6153 -               /* check for the other flags */
6154 -               if (c->flags & prohibited_flags & ~IEEE80211_CHAN_RADAR)
6155 +       width = cfg80211_chandef_get_width(chandef);
6156 +       if (width < 0)
6157 +               return false;
6158 +
6159 +       r = cfg80211_get_chans_dfs_available(wiphy, chandef->center_freq1,
6160 +                                            width);
6161 +
6162 +       /* If any of channels unavailable for cf1 just return */
6163 +       if (!r)
6164 +               return r;
6165 +
6166 +       switch (chandef->width) {
6167 +       case NL80211_CHAN_WIDTH_80P80:
6168 +               WARN_ON(!chandef->center_freq2);
6169 +               r = cfg80211_get_chans_dfs_available(wiphy,
6170 +                                                    chandef->center_freq2,
6171 +                                                    width);
6172 +       default:
6173 +               WARN_ON(chandef->center_freq2);
6174 +               break;
6175 +       }
6176 +
6177 +       return r;
6178 +}
6179 +
6180 +
6181 +static bool cfg80211_secondary_chans_ok(struct wiphy *wiphy,
6182 +                                       u32 center_freq, u32 bandwidth,
6183 +                                       u32 prohibited_flags)
6184 +{
6185 +       struct ieee80211_channel *c;
6186 +       u32 freq, start_freq, end_freq;
6187 +
6188 +       start_freq = cfg80211_get_start_freq(center_freq, bandwidth);
6189 +       end_freq = cfg80211_get_end_freq(center_freq, bandwidth);
6190 +
6191 +       for (freq = start_freq; freq <= end_freq; freq += 20) {
6192 +               c = ieee80211_get_channel(wiphy, freq);
6193 +               if (!c || c->flags & prohibited_flags)
6194                         return false;
6195         }
6196
6197 @@ -462,14 +609,19 @@ bool cfg80211_reg_can_beacon(struct wiph
6198                              struct cfg80211_chan_def *chandef)
6199  {
6200         bool res;
6201 +       u32 prohibited_flags = IEEE80211_CHAN_DISABLED |
6202 +                              IEEE80211_CHAN_NO_IR |
6203 +                              IEEE80211_CHAN_RADAR;
6204
6205         trace_cfg80211_reg_can_beacon(wiphy, chandef);
6206
6207 -       res = cfg80211_chandef_usable(wiphy, chandef,
6208 -                                     IEEE80211_CHAN_DISABLED |
6209 -                                     IEEE80211_CHAN_PASSIVE_SCAN |
6210 -                                     IEEE80211_CHAN_NO_IBSS |
6211 -                                     IEEE80211_CHAN_RADAR);
6212 +       if (cfg80211_chandef_dfs_required(wiphy, chandef) > 0 &&
6213 +           cfg80211_chandef_dfs_available(wiphy, chandef)) {
6214 +               /* We can skip IEEE80211_CHAN_NO_IR if chandef dfs available */
6215 +               prohibited_flags = IEEE80211_CHAN_DISABLED;
6216 +       }
6217 +
6218 +       res = cfg80211_chandef_usable(wiphy, chandef, prohibited_flags);
6219
6220         trace_cfg80211_return_bool(res);
6221         return res;
6222 --- a/net/wireless/core.h
6223 +++ b/net/wireless/core.h
6224 @@ -382,6 +382,19 @@ int cfg80211_can_use_iftype_chan(struct
6225                                  enum cfg80211_chan_mode chanmode,
6226                                  u8 radar_detect);
6227
6228 +/**
6229 + * cfg80211_chandef_dfs_usable - checks if chandef is DFS usable
6230 + * @wiphy: the wiphy to validate against
6231 + * @chandef: the channel definition to check
6232 + *
6233 + * Checks if chandef is usable and we can/need start CAC on such channel.
6234 + *
6235 + * Return: Return true if all channels available and at least
6236 + *        one channel require CAC (NL80211_DFS_USABLE)
6237 + */
6238 +bool cfg80211_chandef_dfs_usable(struct wiphy *wiphy,
6239 +                                const struct cfg80211_chan_def *chandef);
6240 +
6241  void cfg80211_set_dfs_state(struct wiphy *wiphy,
6242                             const struct cfg80211_chan_def *chandef,
6243                             enum nl80211_dfs_state dfs_state);
6244 --- a/net/wireless/genregdb.awk
6245 +++ b/net/wireless/genregdb.awk
6246 @@ -107,10 +107,13 @@ active && /^[ \t]*\(/ {
6247                 } else if (flagarray[arg] == "PTMP-ONLY") {
6248                         flags = flags "\n\t\t\tNL80211_RRF_PTMP_ONLY | "
6249                 } else if (flagarray[arg] == "PASSIVE-SCAN") {
6250 -                       flags = flags "\n\t\t\tNL80211_RRF_PASSIVE_SCAN | "
6251 +                       flags = flags "\n\t\t\tNL80211_RRF_NO_IR | "
6252                 } else if (flagarray[arg] == "NO-IBSS") {
6253 -                       flags = flags "\n\t\t\tNL80211_RRF_NO_IBSS | "
6254 +                       flags = flags "\n\t\t\tNL80211_RRF_NO_IR | "
6255 +               } else if (flagarray[arg] == "NO-IR") {
6256 +                       flags = flags "\n\t\t\tNL80211_RRF_NO_IR | "
6257                 }
6258 +
6259         }
6260         flags = flags "0"
6261         printf "\t\tREG_RULE(%d, %d, %d, %d, %d, %s),\n", start, end, bw, gain, power, flags
6262 --- a/net/wireless/ibss.c
6263 +++ b/net/wireless/ibss.c
6264 @@ -274,7 +274,7 @@ int cfg80211_ibss_wext_join(struct cfg80
6265
6266                         for (i = 0; i < sband->n_channels; i++) {
6267                                 chan = &sband->channels[i];
6268 -                               if (chan->flags & IEEE80211_CHAN_NO_IBSS)
6269 +                               if (chan->flags & IEEE80211_CHAN_NO_IR)
6270                                         continue;
6271                                 if (chan->flags & IEEE80211_CHAN_DISABLED)
6272                                         continue;
6273 @@ -345,7 +345,7 @@ int cfg80211_ibss_wext_siwfreq(struct ne
6274                 chan = ieee80211_get_channel(wdev->wiphy, freq);
6275                 if (!chan)
6276                         return -EINVAL;
6277 -               if (chan->flags & IEEE80211_CHAN_NO_IBSS ||
6278 +               if (chan->flags & IEEE80211_CHAN_NO_IR ||
6279                     chan->flags & IEEE80211_CHAN_DISABLED)
6280                         return -EINVAL;
6281         }
6282 --- a/net/wireless/mesh.c
6283 +++ b/net/wireless/mesh.c
6284 @@ -141,8 +141,7 @@ int __cfg80211_join_mesh(struct cfg80211
6285
6286                         for (i = 0; i < sband->n_channels; i++) {
6287                                 chan = &sband->channels[i];
6288 -                               if (chan->flags & (IEEE80211_CHAN_NO_IBSS |
6289 -                                                  IEEE80211_CHAN_PASSIVE_SCAN |
6290 +                               if (chan->flags & (IEEE80211_CHAN_NO_IR |
6291                                                    IEEE80211_CHAN_DISABLED |
6292                                                    IEEE80211_CHAN_RADAR))
6293                                         continue;
6294 --- a/net/wireless/mlme.c
6295 +++ b/net/wireless/mlme.c
6296 @@ -763,12 +763,12 @@ void cfg80211_radar_event(struct wiphy *
6297  EXPORT_SYMBOL(cfg80211_radar_event);
6298
6299  void cfg80211_cac_event(struct net_device *netdev,
6300 +                       const struct cfg80211_chan_def *chandef,
6301                         enum nl80211_radar_event event, gfp_t gfp)
6302  {
6303         struct wireless_dev *wdev = netdev->ieee80211_ptr;
6304         struct wiphy *wiphy = wdev->wiphy;
6305         struct cfg80211_registered_device *rdev = wiphy_to_dev(wiphy);
6306 -       struct cfg80211_chan_def chandef;
6307         unsigned long timeout;
6308
6309         trace_cfg80211_cac_event(netdev, event);
6310 @@ -779,14 +779,12 @@ void cfg80211_cac_event(struct net_devic
6311         if (WARN_ON(!wdev->channel))
6312                 return;
6313
6314 -       cfg80211_chandef_create(&chandef, wdev->channel, NL80211_CHAN_NO_HT);
6315 -
6316         switch (event) {
6317         case NL80211_RADAR_CAC_FINISHED:
6318                 timeout = wdev->cac_start_time +
6319                           msecs_to_jiffies(IEEE80211_DFS_MIN_CAC_TIME_MS);
6320                 WARN_ON(!time_after_eq(jiffies, timeout));
6321 -               cfg80211_set_dfs_state(wiphy, &chandef, NL80211_DFS_AVAILABLE);
6322 +               cfg80211_set_dfs_state(wiphy, chandef, NL80211_DFS_AVAILABLE);
6323                 break;
6324         case NL80211_RADAR_CAC_ABORTED:
6325                 break;
6326 @@ -796,6 +794,6 @@ void cfg80211_cac_event(struct net_devic
6327         }
6328         wdev->cac_started = false;
6329
6330 -       nl80211_radar_notify(rdev, &chandef, event, netdev, gfp);
6331 +       nl80211_radar_notify(rdev, chandef, event, netdev, gfp);
6332  }
6333  EXPORT_SYMBOL(cfg80211_cac_event);
6334 --- a/net/wireless/nl80211.c
6335 +++ b/net/wireless/nl80211.c
6336 @@ -545,12 +545,12 @@ static int nl80211_msg_put_channel(struc
6337         if ((chan->flags & IEEE80211_CHAN_DISABLED) &&
6338             nla_put_flag(msg, NL80211_FREQUENCY_ATTR_DISABLED))
6339                 goto nla_put_failure;
6340 -       if ((chan->flags & IEEE80211_CHAN_PASSIVE_SCAN) &&
6341 -           nla_put_flag(msg, NL80211_FREQUENCY_ATTR_PASSIVE_SCAN))
6342 -               goto nla_put_failure;
6343 -       if ((chan->flags & IEEE80211_CHAN_NO_IBSS) &&
6344 -           nla_put_flag(msg, NL80211_FREQUENCY_ATTR_NO_IBSS))
6345 -               goto nla_put_failure;
6346 +       if (chan->flags & IEEE80211_CHAN_NO_IR) {
6347 +               if (nla_put_flag(msg, NL80211_FREQUENCY_ATTR_NO_IR))
6348 +                       goto nla_put_failure;
6349 +               if (nla_put_flag(msg, __NL80211_FREQUENCY_ATTR_NO_IBSS))
6350 +                       goto nla_put_failure;
6351 +       }
6352         if (chan->flags & IEEE80211_CHAN_RADAR) {
6353                 if (nla_put_flag(msg, NL80211_FREQUENCY_ATTR_RADAR))
6354                         goto nla_put_failure;
6355 @@ -1229,7 +1229,8 @@ static int nl80211_send_wiphy(struct cfg
6356                     nla_put_flag(msg, NL80211_ATTR_TDLS_EXTERNAL_SETUP))
6357                         goto nla_put_failure;
6358                 if ((dev->wiphy.flags & WIPHY_FLAG_SUPPORTS_5_10_MHZ) &&
6359 -                   nla_put_flag(msg, WIPHY_FLAG_SUPPORTS_5_10_MHZ))
6360 +                   (nla_put_flag(msg, NL80211_ATTR_SUPPORT_5_MHZ) ||
6361 +                    nla_put_flag(msg, NL80211_ATTR_SUPPORT_10_MHZ)))
6362                         goto nla_put_failure;
6363
6364                 state->split_start++;
6365 @@ -2170,7 +2171,7 @@ static inline u64 wdev_id(struct wireles
6366  }
6367
6368  static int nl80211_send_chandef(struct sk_buff *msg,
6369 -                                struct cfg80211_chan_def *chandef)
6370 +                               const struct cfg80211_chan_def *chandef)
6371  {
6372         WARN_ON(!cfg80211_chandef_valid(chandef));
6373
6374 @@ -3219,6 +3220,7 @@ static int nl80211_start_ap(struct sk_bu
6375                         return PTR_ERR(params.acl);
6376         }
6377
6378 +       wdev_lock(wdev);
6379         err = rdev_start_ap(rdev, dev, &params);
6380         if (!err) {
6381                 wdev->preset_chandef = params.chandef;
6382 @@ -3227,6 +3229,7 @@ static int nl80211_start_ap(struct sk_bu
6383                 wdev->ssid_len = params.ssid_len;
6384                 memcpy(wdev->ssid, params.ssid, wdev->ssid_len);
6385         }
6386 +       wdev_unlock(wdev);
6387
6388         kfree(params.acl);
6389
6390 @@ -3255,7 +3258,11 @@ static int nl80211_set_beacon(struct sk_
6391         if (err)
6392                 return err;
6393
6394 -       return rdev_change_beacon(rdev, dev, &params);
6395 +       wdev_lock(wdev);
6396 +       err = rdev_change_beacon(rdev, dev, &params);
6397 +       wdev_unlock(wdev);
6398 +
6399 +       return err;
6400  }
6401
6402  static int nl80211_stop_ap(struct sk_buff *skb, struct genl_info *info)
6403 @@ -4461,7 +4468,9 @@ static int nl80211_set_bss(struct sk_buf
6404  {
6405         struct cfg80211_registered_device *rdev = info->user_ptr[0];
6406         struct net_device *dev = info->user_ptr[1];
6407 +       struct wireless_dev *wdev = dev->ieee80211_ptr;
6408         struct bss_parameters params;
6409 +       int err;
6410
6411         memset(&params, 0, sizeof(params));
6412         /* default to not changing parameters */
6413 @@ -4527,7 +4536,11 @@ static int nl80211_set_bss(struct sk_buf
6414             dev->ieee80211_ptr->iftype != NL80211_IFTYPE_P2P_GO)
6415                 return -EOPNOTSUPP;
6416
6417 -       return rdev_change_bss(rdev, dev, &params);
6418 +       wdev_lock(wdev);
6419 +       err = rdev_change_bss(rdev, dev, &params);
6420 +       wdev_unlock(wdev);
6421 +
6422 +       return err;
6423  }
6424
6425  static const struct nla_policy reg_rule_policy[NL80211_REG_RULE_ATTR_MAX + 1] = {
6426 @@ -5653,7 +5666,7 @@ static int nl80211_start_radar_detection
6427         if (err == 0)
6428                 return -EINVAL;
6429
6430 -       if (chandef.chan->dfs_state != NL80211_DFS_USABLE)
6431 +       if (!cfg80211_chandef_dfs_usable(wdev->wiphy, &chandef))
6432                 return -EINVAL;
6433
6434         if (!rdev->ops->start_radar_detection)
6435 @@ -5793,7 +5806,11 @@ skip_beacons:
6436         if (info->attrs[NL80211_ATTR_CH_SWITCH_BLOCK_TX])
6437                 params.block_tx = true;
6438
6439 -       return rdev_channel_switch(rdev, dev, &params);
6440 +       wdev_lock(wdev);
6441 +       err = rdev_channel_switch(rdev, dev, &params);
6442 +       wdev_unlock(wdev);
6443 +
6444 +       return err;
6445  }
6446
6447  static int nl80211_send_bss(struct sk_buff *msg, struct netlink_callback *cb,
6448 @@ -10809,21 +10826,18 @@ void cfg80211_ch_switch_notify(struct ne
6449         struct wiphy *wiphy = wdev->wiphy;
6450         struct cfg80211_registered_device *rdev = wiphy_to_dev(wiphy);
6451
6452 -       trace_cfg80211_ch_switch_notify(dev, chandef);
6453 +       ASSERT_WDEV_LOCK(wdev);
6454
6455 -       wdev_lock(wdev);
6456 +       trace_cfg80211_ch_switch_notify(dev, chandef);
6457
6458         if (WARN_ON(wdev->iftype != NL80211_IFTYPE_AP &&
6459                     wdev->iftype != NL80211_IFTYPE_P2P_GO &&
6460                     wdev->iftype != NL80211_IFTYPE_ADHOC &&
6461                     wdev->iftype != NL80211_IFTYPE_MESH_POINT))
6462 -               goto out;
6463 +               return;
6464
6465         wdev->channel = chandef->chan;
6466         nl80211_ch_switch_notify(rdev, dev, chandef, GFP_KERNEL);
6467 -out:
6468 -       wdev_unlock(wdev);
6469 -       return;
6470  }
6471  EXPORT_SYMBOL(cfg80211_ch_switch_notify);
6472
6473 @@ -10882,7 +10896,7 @@ EXPORT_SYMBOL(cfg80211_cqm_txe_notify);
6474
6475  void
6476  nl80211_radar_notify(struct cfg80211_registered_device *rdev,
6477 -                    struct cfg80211_chan_def *chandef,
6478 +                    const struct cfg80211_chan_def *chandef,
6479                      enum nl80211_radar_event event,
6480                      struct net_device *netdev, gfp_t gfp)
6481  {
6482 --- a/net/wireless/nl80211.h
6483 +++ b/net/wireless/nl80211.h
6484 @@ -70,7 +70,7 @@ int nl80211_send_mgmt(struct cfg80211_re
6485
6486  void
6487  nl80211_radar_notify(struct cfg80211_registered_device *rdev,
6488 -                    struct cfg80211_chan_def *chandef,
6489 +                    const struct cfg80211_chan_def *chandef,
6490                      enum nl80211_radar_event event,
6491                      struct net_device *netdev, gfp_t gfp);
6492
6493 --- a/net/wireless/reg.c
6494 +++ b/net/wireless/reg.c
6495 @@ -163,35 +163,29 @@ static const struct ieee80211_regdomain
6496                 REG_RULE(2412-10, 2462+10, 40, 6, 20, 0),
6497                 /* IEEE 802.11b/g, channels 12..13. */
6498                 REG_RULE(2467-10, 2472+10, 40, 6, 20,
6499 -                       NL80211_RRF_PASSIVE_SCAN |
6500 -                       NL80211_RRF_NO_IBSS),
6501 +                       NL80211_RRF_NO_IR),
6502                 /* IEEE 802.11 channel 14 - Only JP enables
6503                  * this and for 802.11b only */
6504                 REG_RULE(2484-10, 2484+10, 20, 6, 20,
6505 -                       NL80211_RRF_PASSIVE_SCAN |
6506 -                       NL80211_RRF_NO_IBSS |
6507 +                       NL80211_RRF_NO_IR |
6508                         NL80211_RRF_NO_OFDM),
6509                 /* IEEE 802.11a, channel 36..48 */
6510                 REG_RULE(5180-10, 5240+10, 160, 6, 20,
6511 -                        NL80211_RRF_PASSIVE_SCAN |
6512 -                        NL80211_RRF_NO_IBSS),
6513 +                        NL80211_RRF_NO_IR),
6514
6515                 /* IEEE 802.11a, channel 52..64 - DFS required */
6516                 REG_RULE(5260-10, 5320+10, 160, 6, 20,
6517 -                       NL80211_RRF_PASSIVE_SCAN |
6518 -                       NL80211_RRF_NO_IBSS |
6519 +                       NL80211_RRF_NO_IR |
6520                         NL80211_RRF_DFS),
6521
6522                 /* IEEE 802.11a, channel 100..144 - DFS required */
6523                 REG_RULE(5500-10, 5720+10, 160, 6, 20,
6524 -                       NL80211_RRF_PASSIVE_SCAN |
6525 -                       NL80211_RRF_NO_IBSS |
6526 +                       NL80211_RRF_NO_IR |
6527                         NL80211_RRF_DFS),
6528
6529                 /* IEEE 802.11a, channel 149..165 */
6530                 REG_RULE(5745-10, 5825+10, 80, 6, 20,
6531 -                       NL80211_RRF_PASSIVE_SCAN |
6532 -                       NL80211_RRF_NO_IBSS),
6533 +                       NL80211_RRF_NO_IR),
6534
6535                 /* IEEE 802.11ad (60gHz), channels 1..3 */
6536                 REG_RULE(56160+2160*1-1080, 56160+2160*3+1080, 2160, 0, 0, 0),
6537 @@ -698,10 +692,8 @@ regdom_intersect(const struct ieee80211_
6538  static u32 map_regdom_flags(u32 rd_flags)
6539  {
6540         u32 channel_flags = 0;
6541 -       if (rd_flags & NL80211_RRF_PASSIVE_SCAN)
6542 -               channel_flags |= IEEE80211_CHAN_PASSIVE_SCAN;
6543 -       if (rd_flags & NL80211_RRF_NO_IBSS)
6544 -               channel_flags |= IEEE80211_CHAN_NO_IBSS;
6545 +       if (rd_flags & NL80211_RRF_NO_IR_ALL)
6546 +               channel_flags |= IEEE80211_CHAN_NO_IR;
6547         if (rd_flags & NL80211_RRF_DFS)
6548                 channel_flags |= IEEE80211_CHAN_RADAR;
6549         if (rd_flags & NL80211_RRF_NO_OFDM)
6550 @@ -1066,13 +1058,8 @@ static void handle_reg_beacon(struct wip
6551         chan_before.center_freq = chan->center_freq;
6552         chan_before.flags = chan->flags;
6553
6554 -       if (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN) {
6555 -               chan->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
6556 -               channel_changed = true;
6557 -       }
6558 -
6559 -       if (chan->flags & IEEE80211_CHAN_NO_IBSS) {
6560 -               chan->flags &= ~IEEE80211_CHAN_NO_IBSS;
6561 +       if (chan->flags & IEEE80211_CHAN_NO_IR) {
6562 +               chan->flags &= ~IEEE80211_CHAN_NO_IR;
6563                 channel_changed = true;
6564         }
6565
6566 --- /dev/null
6567 +++ b/drivers/net/wireless/ath/ath9k/ar9003_wow.c
6568 @@ -0,0 +1,422 @@
6569 +/*
6570 + * Copyright (c) 2012 Qualcomm Atheros, Inc.
6571 + *
6572 + * Permission to use, copy, modify, and/or distribute this software for any
6573 + * purpose with or without fee is hereby granted, provided that the above
6574 + * copyright notice and this permission notice appear in all copies.
6575 + *
6576 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
6577 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
6578 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
6579 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
6580 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
6581 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
6582 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
6583 + */
6584 +
6585 +#include <linux/export.h>
6586 +#include "ath9k.h"
6587 +#include "reg.h"
6588 +#include "hw-ops.h"
6589 +
6590 +const char *ath9k_hw_wow_event_to_string(u32 wow_event)
6591 +{
6592 +       if (wow_event & AH_WOW_MAGIC_PATTERN_EN)
6593 +               return "Magic pattern";
6594 +       if (wow_event & AH_WOW_USER_PATTERN_EN)
6595 +               return "User pattern";
6596 +       if (wow_event & AH_WOW_LINK_CHANGE)
6597 +               return "Link change";
6598 +       if (wow_event & AH_WOW_BEACON_MISS)
6599 +               return "Beacon miss";
6600 +
6601 +       return  "unknown reason";
6602 +}
6603 +EXPORT_SYMBOL(ath9k_hw_wow_event_to_string);
6604 +
6605 +static void ath9k_hw_set_powermode_wow_sleep(struct ath_hw *ah)
6606 +{
6607 +       struct ath_common *common = ath9k_hw_common(ah);
6608 +
6609 +       REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
6610 +
6611 +       /* set rx disable bit */
6612 +       REG_WRITE(ah, AR_CR, AR_CR_RXD);
6613 +
6614 +       if (!ath9k_hw_wait(ah, AR_CR, AR_CR_RXE, 0, AH_WAIT_TIMEOUT)) {
6615 +               ath_err(common, "Failed to stop Rx DMA in 10ms AR_CR=0x%08x AR_DIAG_SW=0x%08x\n",
6616 +                       REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW));
6617 +               return;
6618 +       }
6619 +
6620 +       REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_ON_INT);
6621 +}
6622 +
6623 +static void ath9k_wow_create_keep_alive_pattern(struct ath_hw *ah)
6624 +{
6625 +       struct ath_common *common = ath9k_hw_common(ah);
6626 +       u8 sta_mac_addr[ETH_ALEN], ap_mac_addr[ETH_ALEN];
6627 +       u32 ctl[13] = {0};
6628 +       u32 data_word[KAL_NUM_DATA_WORDS];
6629 +       u8 i;
6630 +       u32 wow_ka_data_word0;
6631 +
6632 +       memcpy(sta_mac_addr, common->macaddr, ETH_ALEN);
6633 +       memcpy(ap_mac_addr, common->curbssid, ETH_ALEN);
6634 +
6635 +       /* set the transmit buffer */
6636 +       ctl[0] = (KAL_FRAME_LEN | (MAX_RATE_POWER << 16));
6637 +       ctl[1] = 0;
6638 +       ctl[3] = 0xb;   /* OFDM_6M hardware value for this rate */
6639 +       ctl[4] = 0;
6640 +       ctl[7] = (ah->txchainmask) << 2;
6641 +       ctl[2] = 0xf << 16; /* tx_tries 0 */
6642 +
6643 +       for (i = 0; i < KAL_NUM_DESC_WORDS; i++)
6644 +               REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + i * 4), ctl[i]);
6645 +
6646 +       REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + i * 4), ctl[i]);
6647 +
6648 +       data_word[0] = (KAL_FRAME_TYPE << 2) | (KAL_FRAME_SUB_TYPE << 4) |
6649 +                      (KAL_TO_DS << 8) | (KAL_DURATION_ID << 16);
6650 +       data_word[1] = (ap_mac_addr[3] << 24) | (ap_mac_addr[2] << 16) |
6651 +                      (ap_mac_addr[1] << 8) | (ap_mac_addr[0]);
6652 +       data_word[2] = (sta_mac_addr[1] << 24) | (sta_mac_addr[0] << 16) |
6653 +                      (ap_mac_addr[5] << 8) | (ap_mac_addr[4]);
6654 +       data_word[3] = (sta_mac_addr[5] << 24) | (sta_mac_addr[4] << 16) |
6655 +                      (sta_mac_addr[3] << 8) | (sta_mac_addr[2]);
6656 +       data_word[4] = (ap_mac_addr[3] << 24) | (ap_mac_addr[2] << 16) |
6657 +                      (ap_mac_addr[1] << 8) | (ap_mac_addr[0]);
6658 +       data_word[5] = (ap_mac_addr[5] << 8) | (ap_mac_addr[4]);
6659 +
6660 +       if (AR_SREV_9462_20(ah)) {
6661 +               /* AR9462 2.0 has an extra descriptor word (time based
6662 +                * discard) compared to other chips */
6663 +               REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + (12 * 4)), 0);
6664 +               wow_ka_data_word0 = AR_WOW_TXBUF(13);
6665 +       } else {
6666 +               wow_ka_data_word0 = AR_WOW_TXBUF(12);
6667 +       }
6668 +
6669 +       for (i = 0; i < KAL_NUM_DATA_WORDS; i++)
6670 +               REG_WRITE(ah, (wow_ka_data_word0 + i*4), data_word[i]);
6671 +
6672 +}
6673 +
6674 +void ath9k_hw_wow_apply_pattern(struct ath_hw *ah, u8 *user_pattern,
6675 +                               u8 *user_mask, int pattern_count,
6676 +                               int pattern_len)
6677 +{
6678 +       int i;
6679 +       u32 pattern_val, mask_val;
6680 +       u32 set, clr;
6681 +
6682 +       /* FIXME: should check count by querying the hardware capability */
6683 +       if (pattern_count >= MAX_NUM_PATTERN)
6684 +               return;
6685 +
6686 +       REG_SET_BIT(ah, AR_WOW_PATTERN, BIT(pattern_count));
6687 +
6688 +       /* set the registers for pattern */
6689 +       for (i = 0; i < MAX_PATTERN_SIZE; i += 4) {
6690 +               memcpy(&pattern_val, user_pattern, 4);
6691 +               REG_WRITE(ah, (AR_WOW_TB_PATTERN(pattern_count) + i),
6692 +                         pattern_val);
6693 +               user_pattern += 4;
6694 +       }
6695 +
6696 +       /* set the registers for mask */
6697 +       for (i = 0; i < MAX_PATTERN_MASK_SIZE; i += 4) {
6698 +               memcpy(&mask_val, user_mask, 4);
6699 +               REG_WRITE(ah, (AR_WOW_TB_MASK(pattern_count) + i), mask_val);
6700 +               user_mask += 4;
6701 +       }
6702 +
6703 +       /* set the pattern length to be matched
6704 +        *
6705 +        * AR_WOW_LENGTH1_REG1
6706 +        * bit 31:24 pattern 0 length
6707 +        * bit 23:16 pattern 1 length
6708 +        * bit 15:8 pattern 2 length
6709 +        * bit 7:0 pattern 3 length
6710 +        *
6711 +        * AR_WOW_LENGTH1_REG2
6712 +        * bit 31:24 pattern 4 length
6713 +        * bit 23:16 pattern 5 length
6714 +        * bit 15:8 pattern 6 length
6715 +        * bit 7:0 pattern 7 length
6716 +        *
6717 +        * the below logic writes out the new
6718 +        * pattern length for the corresponding
6719 +        * pattern_count, while masking out the
6720 +        * other fields
6721 +        */
6722 +
6723 +       ah->wow_event_mask |= BIT(pattern_count + AR_WOW_PAT_FOUND_SHIFT);
6724 +
6725 +       if (pattern_count < 4) {
6726 +               /* Pattern 0-3 uses AR_WOW_LENGTH1 register */
6727 +               set = (pattern_len & AR_WOW_LENGTH_MAX) <<
6728 +                      AR_WOW_LEN1_SHIFT(pattern_count);
6729 +               clr = AR_WOW_LENGTH1_MASK(pattern_count);
6730 +               REG_RMW(ah, AR_WOW_LENGTH1, set, clr);
6731 +       } else {
6732 +               /* Pattern 4-7 uses AR_WOW_LENGTH2 register */
6733 +               set = (pattern_len & AR_WOW_LENGTH_MAX) <<
6734 +                      AR_WOW_LEN2_SHIFT(pattern_count);
6735 +               clr = AR_WOW_LENGTH2_MASK(pattern_count);
6736 +               REG_RMW(ah, AR_WOW_LENGTH2, set, clr);
6737 +       }
6738 +
6739 +}
6740 +EXPORT_SYMBOL(ath9k_hw_wow_apply_pattern);
6741 +
6742 +u32 ath9k_hw_wow_wakeup(struct ath_hw *ah)
6743 +{
6744 +       u32 wow_status = 0;
6745 +       u32 val = 0, rval;
6746 +
6747 +       /*
6748 +        * read the WoW status register to know
6749 +        * the wakeup reason
6750 +        */
6751 +       rval = REG_READ(ah, AR_WOW_PATTERN);
6752 +       val = AR_WOW_STATUS(rval);
6753 +
6754 +       /*
6755 +        * mask only the WoW events that we have enabled. Sometimes
6756 +        * we have spurious WoW events from the AR_WOW_PATTERN
6757 +        * register. This mask will clean it up.
6758 +        */
6759 +
6760 +       val &= ah->wow_event_mask;
6761 +
6762 +       if (val) {
6763 +               if (val & AR_WOW_MAGIC_PAT_FOUND)
6764 +                       wow_status |= AH_WOW_MAGIC_PATTERN_EN;
6765 +               if (AR_WOW_PATTERN_FOUND(val))
6766 +                       wow_status |= AH_WOW_USER_PATTERN_EN;
6767 +               if (val & AR_WOW_KEEP_ALIVE_FAIL)
6768 +                       wow_status |= AH_WOW_LINK_CHANGE;
6769 +               if (val & AR_WOW_BEACON_FAIL)
6770 +                       wow_status |= AH_WOW_BEACON_MISS;
6771 +       }
6772 +
6773 +       /*
6774 +        * set and clear WOW_PME_CLEAR registers for the chip to
6775 +        * generate next wow signal.
6776 +        * disable D3 before accessing other registers ?
6777 +        */
6778 +
6779 +       /* do we need to check the bit value 0x01000000 (7-10) ?? */
6780 +       REG_RMW(ah, AR_PCIE_PM_CTRL, AR_PMCTRL_WOW_PME_CLR,
6781 +               AR_PMCTRL_PWR_STATE_D1D3);
6782 +
6783 +       /*
6784 +        * clear all events
6785 +        */
6786 +       REG_WRITE(ah, AR_WOW_PATTERN,
6787 +                 AR_WOW_CLEAR_EVENTS(REG_READ(ah, AR_WOW_PATTERN)));
6788 +
6789 +       /*
6790 +        * restore the beacon threshold to init value
6791 +        */
6792 +       REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
6793 +
6794 +       /*
6795 +        * Restore the way the PCI-E reset, Power-On-Reset, external
6796 +        * PCIE_POR_SHORT pins are tied to its original value.
6797 +        * Previously just before WoW sleep, we untie the PCI-E
6798 +        * reset to our Chip's Power On Reset so that any PCI-E
6799 +        * reset from the bus will not reset our chip
6800 +        */
6801 +       if (ah->is_pciexpress)
6802 +               ath9k_hw_configpcipowersave(ah, false);
6803 +
6804 +       ah->wow_event_mask = 0;
6805 +
6806 +       return wow_status;
6807 +}
6808 +EXPORT_SYMBOL(ath9k_hw_wow_wakeup);
6809 +
6810 +void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable)
6811 +{
6812 +       u32 wow_event_mask;
6813 +       u32 set, clr;
6814 +
6815 +       /*
6816 +        * wow_event_mask is a mask to the AR_WOW_PATTERN register to
6817 +        * indicate which WoW events we have enabled. The WoW events
6818 +        * are from the 'pattern_enable' in this function and
6819 +        * 'pattern_count' of ath9k_hw_wow_apply_pattern()
6820 +        */
6821 +       wow_event_mask = ah->wow_event_mask;
6822 +
6823 +       /*
6824 +        * Untie Power-on-Reset from the PCI-E-Reset. When we are in
6825 +        * WOW sleep, we do want the Reset from the PCI-E to disturb
6826 +        * our hw state
6827 +        */
6828 +       if (ah->is_pciexpress) {
6829 +               /*
6830 +                * we need to untie the internal POR (power-on-reset)
6831 +                * to the external PCI-E reset. We also need to tie
6832 +                * the PCI-E Phy reset to the PCI-E reset.
6833 +                */
6834 +               set = AR_WA_RESET_EN | AR_WA_POR_SHORT;
6835 +               clr = AR_WA_UNTIE_RESET_EN | AR_WA_D3_L1_DISABLE;
6836 +               REG_RMW(ah, AR_WA, set, clr);
6837 +       }
6838 +
6839 +       /*
6840 +        * set the power states appropriately and enable PME
6841 +        */
6842 +       set = AR_PMCTRL_HOST_PME_EN | AR_PMCTRL_PWR_PM_CTRL_ENA |
6843 +             AR_PMCTRL_AUX_PWR_DET | AR_PMCTRL_WOW_PME_CLR;
6844 +
6845 +       /*
6846 +        * set and clear WOW_PME_CLEAR registers for the chip
6847 +        * to generate next wow signal.
6848 +        */
6849 +       REG_SET_BIT(ah, AR_PCIE_PM_CTRL, set);
6850 +       clr = AR_PMCTRL_WOW_PME_CLR;
6851 +       REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, clr);
6852 +
6853 +       /*
6854 +        * Setup for:
6855 +        *      - beacon misses
6856 +        *      - magic pattern
6857 +        *      - keep alive timeout
6858 +        *      - pattern matching
6859 +        */
6860 +
6861 +       /*
6862 +        * Program default values for pattern backoff, aifs/slot/KAL count,
6863 +        * beacon miss timeout, KAL timeout, etc.
6864 +        */
6865 +       set = AR_WOW_BACK_OFF_SHIFT(AR_WOW_PAT_BACKOFF);
6866 +       REG_SET_BIT(ah, AR_WOW_PATTERN, set);
6867 +
6868 +       set = AR_WOW_AIFS_CNT(AR_WOW_CNT_AIFS_CNT) |
6869 +             AR_WOW_SLOT_CNT(AR_WOW_CNT_SLOT_CNT) |
6870 +             AR_WOW_KEEP_ALIVE_CNT(AR_WOW_CNT_KA_CNT);
6871 +       REG_SET_BIT(ah, AR_WOW_COUNT, set);
6872 +
6873 +       if (pattern_enable & AH_WOW_BEACON_MISS)
6874 +               set = AR_WOW_BEACON_TIMO;
6875 +       /* We are not using beacon miss, program a large value */
6876 +       else
6877 +               set = AR_WOW_BEACON_TIMO_MAX;
6878 +
6879 +       REG_WRITE(ah, AR_WOW_BCN_TIMO, set);
6880 +
6881 +       /*
6882 +        * Keep alive timo in ms except AR9280
6883 +        */
6884 +       if (!pattern_enable)
6885 +               set = AR_WOW_KEEP_ALIVE_NEVER;
6886 +       else
6887 +               set = KAL_TIMEOUT * 32;
6888 +
6889 +       REG_WRITE(ah, AR_WOW_KEEP_ALIVE_TIMO, set);
6890 +
6891 +       /*
6892 +        * Keep alive delay in us. based on 'power on clock',
6893 +        * therefore in usec
6894 +        */
6895 +       set = KAL_DELAY * 1000;
6896 +       REG_WRITE(ah, AR_WOW_KEEP_ALIVE_DELAY, set);
6897 +
6898 +       /*
6899 +        * Create keep alive pattern to respond to beacons
6900 +        */
6901 +       ath9k_wow_create_keep_alive_pattern(ah);
6902 +
6903 +       /*
6904 +        * Configure MAC WoW Registers
6905 +        */
6906 +       set = 0;
6907 +       /* Send keep alive timeouts anyway */
6908 +       clr = AR_WOW_KEEP_ALIVE_AUTO_DIS;
6909 +
6910 +       if (pattern_enable & AH_WOW_LINK_CHANGE)
6911 +               wow_event_mask |= AR_WOW_KEEP_ALIVE_FAIL;
6912 +       else
6913 +               set = AR_WOW_KEEP_ALIVE_FAIL_DIS;
6914 +
6915 +       set = AR_WOW_KEEP_ALIVE_FAIL_DIS;
6916 +       REG_RMW(ah, AR_WOW_KEEP_ALIVE, set, clr);
6917 +
6918 +       /*
6919 +        * we are relying on a bmiss failure. ensure we have
6920 +        * enough threshold to prevent false positives
6921 +        */
6922 +       REG_RMW_FIELD(ah, AR_RSSI_THR, AR_RSSI_THR_BM_THR,
6923 +                     AR_WOW_BMISSTHRESHOLD);
6924 +
6925 +       set = 0;
6926 +       clr = 0;
6927 +
6928 +       if (pattern_enable & AH_WOW_BEACON_MISS) {
6929 +               set = AR_WOW_BEACON_FAIL_EN;
6930 +               wow_event_mask |= AR_WOW_BEACON_FAIL;
6931 +       } else {
6932 +               clr = AR_WOW_BEACON_FAIL_EN;
6933 +       }
6934 +
6935 +       REG_RMW(ah, AR_WOW_BCN_EN, set, clr);
6936 +
6937 +       set = 0;
6938 +       clr = 0;
6939 +       /*
6940 +        * Enable the magic packet registers
6941 +        */
6942 +       if (pattern_enable & AH_WOW_MAGIC_PATTERN_EN) {
6943 +               set = AR_WOW_MAGIC_EN;
6944 +               wow_event_mask |= AR_WOW_MAGIC_PAT_FOUND;
6945 +       } else {
6946 +               clr = AR_WOW_MAGIC_EN;
6947 +       }
6948 +       set |= AR_WOW_MAC_INTR_EN;
6949 +       REG_RMW(ah, AR_WOW_PATTERN, set, clr);
6950 +
6951 +       REG_WRITE(ah, AR_WOW_PATTERN_MATCH_LT_256B,
6952 +                 AR_WOW_PATTERN_SUPPORTED);
6953 +
6954 +       /*
6955 +        * Set the power states appropriately and enable PME
6956 +        */
6957 +       clr = 0;
6958 +       set = AR_PMCTRL_PWR_STATE_D1D3 | AR_PMCTRL_HOST_PME_EN |
6959 +             AR_PMCTRL_PWR_PM_CTRL_ENA;
6960 +
6961 +       clr = AR_PCIE_PM_CTRL_ENA;
6962 +       REG_RMW(ah, AR_PCIE_PM_CTRL, set, clr);
6963 +
6964 +       /*
6965 +        * this is needed to prevent the chip waking up
6966 +        * the host within 3-4 seconds with certain
6967 +        * platform/BIOS. The fix is to enable
6968 +        * D1 & D3 to match original definition and
6969 +        * also match the OTP value. Anyway this
6970 +        * is more related to SW WOW.
6971 +        */
6972 +       clr = AR_PMCTRL_PWR_STATE_D1D3;
6973 +       REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, clr);
6974 +
6975 +       set = AR_PMCTRL_PWR_STATE_D1D3_REAL;
6976 +       REG_SET_BIT(ah, AR_PCIE_PM_CTRL, set);
6977 +
6978 +       REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
6979 +
6980 +       /* to bring down WOW power low margin */
6981 +       set = BIT(13);
6982 +       REG_SET_BIT(ah, AR_PCIE_PHY_REG3, set);
6983 +       /* HW WoW */
6984 +       clr = BIT(5);
6985 +       REG_CLR_BIT(ah, AR_PCU_MISC_MODE3, clr);
6986 +
6987 +       ath9k_hw_set_powermode_wow_sleep(ah);
6988 +       ah->wow_event_mask = wow_event_mask;
6989 +}
6990 +EXPORT_SYMBOL(ath9k_hw_wow_enable);
6991 --- /dev/null
6992 +++ b/drivers/net/wireless/ath/ath9k/tx99.c
6993 @@ -0,0 +1,263 @@
6994 +/*
6995 + * Copyright (c) 2013 Qualcomm Atheros, Inc.
6996 + *
6997 + * Permission to use, copy, modify, and/or distribute this software for any
6998 + * purpose with or without fee is hereby granted, provided that the above
6999 + * copyright notice and this permission notice appear in all copies.
7000 + *
7001 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
7002 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
7003 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
7004 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
7005 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
7006 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
7007 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
7008 + */
7009 +
7010 +#include "ath9k.h"
7011 +
7012 +static void ath9k_tx99_stop(struct ath_softc *sc)
7013 +{
7014 +       struct ath_hw *ah = sc->sc_ah;
7015 +       struct ath_common *common = ath9k_hw_common(ah);
7016 +
7017 +       ath_drain_all_txq(sc);
7018 +       ath_startrecv(sc);
7019 +
7020 +       ath9k_hw_set_interrupts(ah);
7021 +       ath9k_hw_enable_interrupts(ah);
7022 +
7023 +       ieee80211_wake_queues(sc->hw);
7024 +
7025 +       kfree_skb(sc->tx99_skb);
7026 +       sc->tx99_skb = NULL;
7027 +       sc->tx99_state = false;
7028 +
7029 +       ath9k_hw_tx99_stop(sc->sc_ah);
7030 +       ath_dbg(common, XMIT, "TX99 stopped\n");
7031 +}
7032 +
7033 +static struct sk_buff *ath9k_build_tx99_skb(struct ath_softc *sc)
7034 +{
7035 +       static u8 PN9Data[] = {0xff, 0x87, 0xb8, 0x59, 0xb7, 0xa1, 0xcc, 0x24,
7036 +                              0x57, 0x5e, 0x4b, 0x9c, 0x0e, 0xe9, 0xea, 0x50,
7037 +                              0x2a, 0xbe, 0xb4, 0x1b, 0xb6, 0xb0, 0x5d, 0xf1,
7038 +                              0xe6, 0x9a, 0xe3, 0x45, 0xfd, 0x2c, 0x53, 0x18,
7039 +                              0x0c, 0xca, 0xc9, 0xfb, 0x49, 0x37, 0xe5, 0xa8,
7040 +                              0x51, 0x3b, 0x2f, 0x61, 0xaa, 0x72, 0x18, 0x84,
7041 +                              0x02, 0x23, 0x23, 0xab, 0x63, 0x89, 0x51, 0xb3,
7042 +                              0xe7, 0x8b, 0x72, 0x90, 0x4c, 0xe8, 0xfb, 0xc0};
7043 +       u32 len = 1200;
7044 +       struct ieee80211_hw *hw = sc->hw;
7045 +       struct ieee80211_hdr *hdr;
7046 +       struct ieee80211_tx_info *tx_info;
7047 +       struct sk_buff *skb;
7048 +
7049 +       skb = alloc_skb(len, GFP_KERNEL);
7050 +       if (!skb)
7051 +               return NULL;
7052 +
7053 +       skb_put(skb, len);
7054 +
7055 +       memset(skb->data, 0, len);
7056 +
7057 +       hdr = (struct ieee80211_hdr *)skb->data;
7058 +       hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_DATA);
7059 +       hdr->duration_id = 0;
7060 +
7061 +       memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN);
7062 +       memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN);
7063 +       memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);
7064 +
7065 +       hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
7066 +
7067 +       tx_info = IEEE80211_SKB_CB(skb);
7068 +       memset(tx_info, 0, sizeof(*tx_info));
7069 +       tx_info->band = hw->conf.chandef.chan->band;
7070 +       tx_info->flags = IEEE80211_TX_CTL_NO_ACK;
7071 +       tx_info->control.vif = sc->tx99_vif;
7072 +
7073 +       memcpy(skb->data + sizeof(*hdr), PN9Data, sizeof(PN9Data));
7074 +
7075 +       return skb;
7076 +}
7077 +
7078 +static void ath9k_tx99_deinit(struct ath_softc *sc)
7079 +{
7080 +       ath_reset(sc);
7081 +
7082 +       ath9k_ps_wakeup(sc);
7083 +       ath9k_tx99_stop(sc);
7084 +       ath9k_ps_restore(sc);
7085 +}
7086 +
7087 +static int ath9k_tx99_init(struct ath_softc *sc)
7088 +{
7089 +       struct ieee80211_hw *hw = sc->hw;
7090 +       struct ath_hw *ah = sc->sc_ah;
7091 +       struct ath_common *common = ath9k_hw_common(ah);
7092 +       struct ath_tx_control txctl;
7093 +       int r;
7094 +
7095 +       if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
7096 +               ath_err(common,
7097 +                       "driver is in invalid state unable to use TX99");
7098 +               return -EINVAL;
7099 +       }
7100 +
7101 +       sc->tx99_skb = ath9k_build_tx99_skb(sc);
7102 +       if (!sc->tx99_skb)
7103 +               return -ENOMEM;
7104 +
7105 +       memset(&txctl, 0, sizeof(txctl));
7106 +       txctl.txq = sc->tx.txq_map[IEEE80211_AC_VO];
7107 +
7108 +       ath_reset(sc);
7109 +
7110 +       ath9k_ps_wakeup(sc);
7111 +
7112 +       ath9k_hw_disable_interrupts(ah);
7113 +       atomic_set(&ah->intr_ref_cnt, -1);
7114 +       ath_drain_all_txq(sc);
7115 +       ath_stoprecv(sc);
7116 +
7117 +       sc->tx99_state = true;
7118 +
7119 +       ieee80211_stop_queues(hw);
7120 +
7121 +       if (sc->tx99_power == MAX_RATE_POWER + 1)
7122 +               sc->tx99_power = MAX_RATE_POWER;
7123 +
7124 +       ath9k_hw_tx99_set_txpower(ah, sc->tx99_power);
7125 +       r = ath9k_tx99_send(sc, sc->tx99_skb, &txctl);
7126 +       if (r) {
7127 +               ath_dbg(common, XMIT, "Failed to xmit TX99 skb\n");
7128 +               return r;
7129 +       }
7130 +
7131 +       ath_dbg(common, XMIT, "TX99 xmit started using %d ( %ddBm)\n",
7132 +               sc->tx99_power,
7133 +               sc->tx99_power / 2);
7134 +
7135 +       /* We leave the harware awake as it will be chugging on */
7136 +
7137 +       return 0;
7138 +}
7139 +
7140 +static ssize_t read_file_tx99(struct file *file, char __user *user_buf,
7141 +                             size_t count, loff_t *ppos)
7142 +{
7143 +       struct ath_softc *sc = file->private_data;
7144 +       char buf[3];
7145 +       unsigned int len;
7146 +
7147 +       len = sprintf(buf, "%d\n", sc->tx99_state);
7148 +       return simple_read_from_buffer(user_buf, count, ppos, buf, len);
7149 +}
7150 +
7151 +static ssize_t write_file_tx99(struct file *file, const char __user *user_buf,
7152 +                              size_t count, loff_t *ppos)
7153 +{
7154 +       struct ath_softc *sc = file->private_data;
7155 +       struct ath_common *common = ath9k_hw_common(sc->sc_ah);
7156 +       char buf[32];
7157 +       bool start;
7158 +       ssize_t len;
7159 +       int r;
7160 +
7161 +       if (sc->nvifs > 1)
7162 +               return -EOPNOTSUPP;
7163 +
7164 +       len = min(count, sizeof(buf) - 1);
7165 +       if (copy_from_user(buf, user_buf, len))
7166 +               return -EFAULT;
7167 +
7168 +       if (strtobool(buf, &start))
7169 +               return -EINVAL;
7170 +
7171 +       if (start == sc->tx99_state) {
7172 +               if (!start)
7173 +                       return count;
7174 +               ath_dbg(common, XMIT, "Resetting TX99\n");
7175 +               ath9k_tx99_deinit(sc);
7176 +       }
7177 +
7178 +       if (!start) {
7179 +               ath9k_tx99_deinit(sc);
7180 +               return count;
7181 +       }
7182 +
7183 +       r = ath9k_tx99_init(sc);
7184 +       if (r)
7185 +               return r;
7186 +
7187 +       return count;
7188 +}
7189 +
7190 +static const struct file_operations fops_tx99 = {
7191 +       .read = read_file_tx99,
7192 +       .write = write_file_tx99,
7193 +       .open = simple_open,
7194 +       .owner = THIS_MODULE,
7195 +       .llseek = default_llseek,
7196 +};
7197 +
7198 +static ssize_t read_file_tx99_power(struct file *file,
7199 +                                   char __user *user_buf,
7200 +                                   size_t count, loff_t *ppos)
7201 +{
7202 +       struct ath_softc *sc = file->private_data;
7203 +       char buf[32];
7204 +       unsigned int len;
7205 +
7206 +       len = sprintf(buf, "%d (%d dBm)\n",
7207 +                     sc->tx99_power,
7208 +                     sc->tx99_power / 2);
7209 +
7210 +       return simple_read_from_buffer(user_buf, count, ppos, buf, len);
7211 +}
7212 +
7213 +static ssize_t write_file_tx99_power(struct file *file,
7214 +                                    const char __user *user_buf,
7215 +                                    size_t count, loff_t *ppos)
7216 +{
7217 +       struct ath_softc *sc = file->private_data;
7218 +       int r;
7219 +       u8 tx_power;
7220 +
7221 +       r = kstrtou8_from_user(user_buf, count, 0, &tx_power);
7222 +       if (r)
7223 +               return r;
7224 +
7225 +       if (tx_power > MAX_RATE_POWER)
7226 +               return -EINVAL;
7227 +
7228 +       sc->tx99_power = tx_power;
7229 +
7230 +       ath9k_ps_wakeup(sc);
7231 +       ath9k_hw_tx99_set_txpower(sc->sc_ah, sc->tx99_power);
7232 +       ath9k_ps_restore(sc);
7233 +
7234 +       return count;
7235 +}
7236 +
7237 +static const struct file_operations fops_tx99_power = {
7238 +       .read = read_file_tx99_power,
7239 +       .write = write_file_tx99_power,
7240 +       .open = simple_open,
7241 +       .owner = THIS_MODULE,
7242 +       .llseek = default_llseek,
7243 +};
7244 +
7245 +void ath9k_tx99_init_debug(struct ath_softc *sc)
7246 +{
7247 +       if (!AR_SREV_9300_20_OR_LATER(sc->sc_ah))
7248 +               return;
7249 +
7250 +       debugfs_create_file("tx99", S_IRUSR | S_IWUSR,
7251 +                           sc->debug.debugfs_phy, sc,
7252 +                           &fops_tx99);
7253 +       debugfs_create_file("tx99_power", S_IRUSR | S_IWUSR,
7254 +                           sc->debug.debugfs_phy, sc,
7255 +                           &fops_tx99_power);
7256 +}
7257 --- a/drivers/net/wireless/ath/ath9k/dfs_debug.c
7258 +++ b/drivers/net/wireless/ath/ath9k/dfs_debug.c
7259 @@ -44,14 +44,20 @@ static ssize_t read_file_dfs(struct file
7260         if (buf == NULL)
7261                 return -ENOMEM;
7262
7263 -       if (sc->dfs_detector)
7264 -               dfs_pool_stats = sc->dfs_detector->get_stats(sc->dfs_detector);
7265 -
7266         len += scnprintf(buf + len, size - len, "DFS support for "
7267                          "macVersion = 0x%x, macRev = 0x%x: %s\n",
7268                          hw_ver->macVersion, hw_ver->macRev,
7269                          (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_DFS) ?
7270                                         "enabled" : "disabled");
7271 +
7272 +       if (!sc->dfs_detector) {
7273 +               len += scnprintf(buf + len, size - len,
7274 +                               "DFS detector not enabled\n");
7275 +               goto exit;
7276 +       }
7277 +
7278 +       dfs_pool_stats = sc->dfs_detector->get_stats(sc->dfs_detector);
7279 +
7280         len += scnprintf(buf + len, size - len, "Pulse detector statistics:\n");
7281         ATH9K_DFS_STAT("pulse events reported   ", pulses_total);
7282         ATH9K_DFS_STAT("invalid pulse events    ", pulses_no_dfs);
7283 @@ -76,6 +82,7 @@ static ssize_t read_file_dfs(struct file
7284         ATH9K_DFS_POOL_STAT("Seqs. alloc error       ", pseq_alloc_error);
7285         ATH9K_DFS_POOL_STAT("Seqs. in use            ", pseq_used);
7286
7287 +exit:
7288         if (len > size)
7289                 len = size;
7290
7291 --- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
7292 +++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
7293 @@ -641,11 +641,12 @@ static void ar9003_hw_override_ini(struc
7294                 else
7295                         ah->enabled_cals &= ~TX_IQ_CAL;
7296
7297 -               if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE)
7298 -                       ah->enabled_cals |= TX_CL_CAL;
7299 -               else
7300 -                       ah->enabled_cals &= ~TX_CL_CAL;
7301         }
7302 +
7303 +       if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE)
7304 +               ah->enabled_cals |= TX_CL_CAL;
7305 +       else
7306 +               ah->enabled_cals &= ~TX_CL_CAL;
7307  }
7308
7309  static void ar9003_hw_prog_ini(struct ath_hw *ah,
7310 @@ -701,6 +702,54 @@ static int ar9550_hw_get_modes_txgain_in
7311         return ret;
7312  }
7313
7314 +static void ar9003_doubler_fix(struct ath_hw *ah)
7315 +{
7316 +       if (AR_SREV_9300(ah) || AR_SREV_9580(ah) || AR_SREV_9550(ah)) {
7317 +               REG_RMW(ah, AR_PHY_65NM_CH0_RXTX2,
7318 +                       1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
7319 +                       1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0);
7320 +               REG_RMW(ah, AR_PHY_65NM_CH1_RXTX2,
7321 +                       1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
7322 +                       1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0);
7323 +               REG_RMW(ah, AR_PHY_65NM_CH2_RXTX2,
7324 +                       1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
7325 +                       1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0);
7326 +
7327 +               udelay(200);
7328 +
7329 +               REG_CLR_BIT(ah, AR_PHY_65NM_CH0_RXTX2,
7330 +                           AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK);
7331 +               REG_CLR_BIT(ah, AR_PHY_65NM_CH1_RXTX2,
7332 +                           AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK);
7333 +               REG_CLR_BIT(ah, AR_PHY_65NM_CH2_RXTX2,
7334 +                           AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK);
7335 +
7336 +               udelay(1);
7337 +
7338 +               REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX2,
7339 +                             AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1);
7340 +               REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX2,
7341 +                             AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1);
7342 +               REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX2,
7343 +                             AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1);
7344 +
7345 +               udelay(200);
7346 +
7347 +               REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH12,
7348 +                             AR_PHY_65NM_CH0_SYNTH12_VREFMUL3, 0xf);
7349 +
7350 +               REG_RMW(ah, AR_PHY_65NM_CH0_RXTX2, 0,
7351 +                       1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
7352 +                       1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S);
7353 +               REG_RMW(ah, AR_PHY_65NM_CH1_RXTX2, 0,
7354 +                       1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
7355 +                       1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S);
7356 +               REG_RMW(ah, AR_PHY_65NM_CH2_RXTX2, 0,
7357 +                       1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
7358 +                       1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S);
7359 +       }
7360 +}
7361 +
7362  static int ar9003_hw_process_ini(struct ath_hw *ah,
7363                                  struct ath9k_channel *chan)
7364  {
7365 @@ -726,6 +775,8 @@ static int ar9003_hw_process_ini(struct
7366                                            modesIndex);
7367         }
7368
7369 +       ar9003_doubler_fix(ah);
7370 +
7371         /*
7372          * RXGAIN initvals.
7373          */
7374 @@ -1281,6 +1332,7 @@ static void ar9003_hw_ani_cache_ini_regs
7375  static void ar9003_hw_set_radar_params(struct ath_hw *ah,
7376                                        struct ath_hw_radar_conf *conf)
7377  {
7378 +       unsigned int regWrites = 0;
7379         u32 radar_0 = 0, radar_1 = 0;
7380
7381         if (!conf) {
7382 @@ -1307,6 +1359,11 @@ static void ar9003_hw_set_radar_params(s
7383                 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
7384         else
7385                 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
7386 +
7387 +       if (AR_SREV_9300(ah) || AR_SREV_9340(ah) || AR_SREV_9580(ah)) {
7388 +               REG_WRITE_ARRAY(&ah->ini_dfs,
7389 +                               IS_CHAN_HT40(ah->curchan) ? 2 : 1, regWrites);
7390 +       }
7391  }
7392
7393  static void ar9003_hw_set_radar_conf(struct ath_hw *ah)
7394 --- a/drivers/net/wireless/ath/ath9k/ar9003_phy.h
7395 +++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
7396 @@ -270,7 +270,7 @@
7397  #define AR_PHY_AGC              (AR_AGC_BASE + 0x14)
7398  #define AR_PHY_EXT_ATTEN_CTL_0  (AR_AGC_BASE + 0x18)
7399  #define AR_PHY_CCA_0            (AR_AGC_BASE + 0x1c)
7400 -#define AR_PHY_EXT_CCA0         (AR_AGC_BASE + 0x20)
7401 +#define AR_PHY_CCA_CTRL_0       (AR_AGC_BASE + 0x20)
7402  #define AR_PHY_RESTART          (AR_AGC_BASE + 0x24)
7403
7404  /*
7405 @@ -341,14 +341,15 @@
7406  #define AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ     -95
7407  #define AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ     -100
7408
7409 +#define AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ -95
7410 +#define AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ -100
7411 +
7412  #define AR_PHY_CCA_NOM_VAL_9462_2GHZ          -127
7413  #define AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ     -127
7414  #define AR_PHY_CCA_MAX_GOOD_VAL_9462_2GHZ     -60
7415 -#define AR_PHY_CCA_MAX_GOOD_VAL_9462_FCC_2GHZ -95
7416  #define AR_PHY_CCA_NOM_VAL_9462_5GHZ          -127
7417  #define AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ     -127
7418  #define AR_PHY_CCA_MAX_GOOD_VAL_9462_5GHZ     -60
7419 -#define AR_PHY_CCA_MAX_GOOD_VAL_9462_FCC_5GHZ -100
7420
7421  #define AR_PHY_CCA_NOM_VAL_9330_2GHZ          -118
7422
7423 @@ -397,6 +398,8 @@
7424  #define AR9280_PHY_CCA_THRESH62_S   12
7425  #define AR_PHY_EXT_CCA0_THRESH62    0x000000FF
7426  #define AR_PHY_EXT_CCA0_THRESH62_S  0
7427 +#define AR_PHY_EXT_CCA0_THRESH62_1    0x000001FF
7428 +#define AR_PHY_EXT_CCA0_THRESH62_1_S  0
7429  #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK          0x0000003F
7430  #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S        0
7431  #define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME           0x00001FC0
7432 @@ -656,13 +659,24 @@
7433  #define AR_PHY_SYNTH4_LONG_SHIFT_SELECT   ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x00000001 : 0x00000002)
7434  #define AR_PHY_SYNTH4_LONG_SHIFT_SELECT_S ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0 : 1)
7435  #define AR_PHY_65NM_CH0_SYNTH7      0x16098
7436 +#define AR_PHY_65NM_CH0_SYNTH12     0x160ac
7437  #define AR_PHY_65NM_CH0_BIAS1       0x160c0
7438  #define AR_PHY_65NM_CH0_BIAS2       0x160c4
7439  #define AR_PHY_65NM_CH0_BIAS4       0x160cc
7440 +#define AR_PHY_65NM_CH0_RXTX2       0x16104
7441 +#define AR_PHY_65NM_CH1_RXTX2       0x16504
7442 +#define AR_PHY_65NM_CH2_RXTX2       0x16904
7443  #define AR_PHY_65NM_CH0_RXTX4       0x1610c
7444  #define AR_PHY_65NM_CH1_RXTX4       0x1650c
7445  #define AR_PHY_65NM_CH2_RXTX4       0x1690c
7446
7447 +#define AR_PHY_65NM_CH0_SYNTH12_VREFMUL3           0x00780000
7448 +#define AR_PHY_65NM_CH0_SYNTH12_VREFMUL3_S         19
7449 +#define AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK         0x00000004
7450 +#define AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S       2
7451 +#define AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK        0x00000008
7452 +#define AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S      3
7453 +
7454  #define AR_CH0_TOP     (AR_SREV_9300(ah) ? 0x16288 : \
7455                          (((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x1628c : 0x16280)))
7456  #define AR_CH0_TOP_XPABIASLVL (AR_SREV_9550(ah) ? 0x3c0 : 0x300)
7457 --- a/drivers/net/wireless/rt2x00/rt2x00dev.c
7458 +++ b/drivers/net/wireless/rt2x00/rt2x00dev.c
7459 @@ -181,6 +181,7 @@ static void rt2x00lib_autowakeup(struct
7460  static void rt2x00lib_bc_buffer_iter(void *data, u8 *mac,
7461                                      struct ieee80211_vif *vif)
7462  {
7463 +       struct ieee80211_tx_control control = {};
7464         struct rt2x00_dev *rt2x00dev = data;
7465         struct sk_buff *skb;
7466
7467 @@ -195,7 +196,7 @@ static void rt2x00lib_bc_buffer_iter(voi
7468          */
7469         skb = ieee80211_get_buffered_bc(rt2x00dev->hw, vif);
7470         while (skb) {
7471 -               rt2x00mac_tx(rt2x00dev->hw, NULL, skb);
7472 +               rt2x00mac_tx(rt2x00dev->hw, &control, skb);
7473                 skb = ieee80211_get_buffered_bc(rt2x00dev->hw, vif);
7474         }
7475  }
7476 --- a/drivers/net/wireless/ath/ath9k/ar9003_calib.c
7477 +++ b/drivers/net/wireless/ath/ath9k/ar9003_calib.c
7478 @@ -898,7 +898,7 @@ static void ar9003_hw_tx_iq_cal_reload(s
7479
7480  static void ar9003_hw_manual_peak_cal(struct ath_hw *ah, u8 chain, bool is_2g)
7481  {
7482 -       int offset[8], total = 0, test;
7483 +       int offset[8] = {0}, total = 0, test;
7484         int agc_out, i;
7485
7486         REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_GAINSTAGES(chain),
7487 @@ -923,12 +923,18 @@ static void ar9003_hw_manual_peak_cal(st
7488                       AR_PHY_65NM_RXRF_AGC_AGC_ON_OVR, 0x1);
7489         REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
7490                       AR_PHY_65NM_RXRF_AGC_AGC_CAL_OVR, 0x1);
7491 -       if (is_2g)
7492 -               REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
7493 -                             AR_PHY_65NM_RXRF_AGC_AGC2G_DBDAC_OVR, 0x0);
7494 -       else
7495 +
7496 +       if (AR_SREV_9330_11(ah)) {
7497                 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
7498 -                             AR_PHY_65NM_RXRF_AGC_AGC5G_DBDAC_OVR, 0x0);
7499 +                             AR_PHY_65NM_RXRF_AGC_AGC2G_CALDAC_OVR, 0x0);
7500 +       } else {
7501 +               if (is_2g)
7502 +                       REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
7503 +                                     AR_PHY_65NM_RXRF_AGC_AGC2G_DBDAC_OVR, 0x0);
7504 +               else
7505 +                       REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
7506 +                                     AR_PHY_65NM_RXRF_AGC_AGC5G_DBDAC_OVR, 0x0);
7507 +       }
7508
7509         for (i = 6; i > 0; i--) {
7510                 offset[i] = BIT(i - 1);
7511 @@ -964,9 +970,9 @@ static void ar9003_hw_manual_peak_cal(st
7512                       AR_PHY_65NM_RXRF_AGC_AGC_CAL_OVR, 0);
7513  }
7514
7515 -static void ar9003_hw_do_manual_peak_cal(struct ath_hw *ah,
7516 -                                        struct ath9k_channel *chan,
7517 -                                        bool run_rtt_cal)
7518 +static void ar9003_hw_do_pcoem_manual_peak_cal(struct ath_hw *ah,
7519 +                                              struct ath9k_channel *chan,
7520 +                                              bool run_rtt_cal)
7521  {
7522         struct ath9k_hw_cal_data *caldata = ah->caldata;
7523         int i;
7524 @@ -1040,14 +1046,14 @@ static void ar9003_hw_cl_cal_post_proc(s
7525         }
7526  }
7527
7528 -static bool ar9003_hw_init_cal(struct ath_hw *ah,
7529 -                              struct ath9k_channel *chan)
7530 +static bool ar9003_hw_init_cal_pcoem(struct ath_hw *ah,
7531 +                                    struct ath9k_channel *chan)
7532  {
7533         struct ath_common *common = ath9k_hw_common(ah);
7534         struct ath9k_hw_cal_data *caldata = ah->caldata;
7535         bool txiqcal_done = false;
7536         bool is_reusable = true, status = true;
7537 -       bool run_rtt_cal = false, run_agc_cal, sep_iq_cal = false;
7538 +       bool run_rtt_cal = false, run_agc_cal;
7539         bool rtt = !!(ah->caps.hw_caps & ATH9K_HW_CAP_RTT);
7540         u32 rx_delay = 0;
7541         u32 agc_ctrl = 0, agc_supp_cals = AR_PHY_AGC_CONTROL_OFFSET_CAL |
7542 @@ -1119,22 +1125,12 @@ static bool ar9003_hw_init_cal(struct at
7543                         REG_CLR_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0,
7544                                     AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL);
7545                 txiqcal_done = run_agc_cal = true;
7546 -       } else if (caldata && !test_bit(TXIQCAL_DONE, &caldata->cal_flags)) {
7547 -               run_agc_cal = true;
7548 -               sep_iq_cal = true;
7549         }
7550
7551  skip_tx_iqcal:
7552         if (ath9k_hw_mci_is_enabled(ah) && IS_CHAN_2GHZ(chan) && run_agc_cal)
7553                 ar9003_mci_init_cal_req(ah, &is_reusable);
7554
7555 -       if (sep_iq_cal) {
7556 -               txiqcal_done = ar9003_hw_tx_iq_cal_run(ah);
7557 -               REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
7558 -               udelay(5);
7559 -               REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
7560 -       }
7561 -
7562         if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE) {
7563                 rx_delay = REG_READ(ah, AR_PHY_RX_DELAY);
7564                 /* Disable BB_active */
7565 @@ -1155,7 +1151,7 @@ skip_tx_iqcal:
7566                                        AR_PHY_AGC_CONTROL_CAL,
7567                                        0, AH_WAIT_TIMEOUT);
7568
7569 -               ar9003_hw_do_manual_peak_cal(ah, chan, run_rtt_cal);
7570 +               ar9003_hw_do_pcoem_manual_peak_cal(ah, chan, run_rtt_cal);
7571         }
7572
7573         if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE) {
7574 @@ -1228,13 +1224,112 @@ skip_tx_iqcal:
7575         return true;
7576  }
7577
7578 +static bool ar9003_hw_init_cal_soc(struct ath_hw *ah,
7579 +                                  struct ath9k_channel *chan)
7580 +{
7581 +       struct ath_common *common = ath9k_hw_common(ah);
7582 +       struct ath9k_hw_cal_data *caldata = ah->caldata;
7583 +       bool txiqcal_done = false;
7584 +       bool is_reusable = true, status = true;
7585 +       bool run_agc_cal = false, sep_iq_cal = false;
7586 +
7587 +       /* Use chip chainmask only for calibration */
7588 +       ar9003_hw_set_chain_masks(ah, ah->caps.rx_chainmask, ah->caps.tx_chainmask);
7589 +
7590 +       if (ah->enabled_cals & TX_CL_CAL) {
7591 +               REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
7592 +               run_agc_cal = true;
7593 +       }
7594 +
7595 +       if (IS_CHAN_HALF_RATE(chan) || IS_CHAN_QUARTER_RATE(chan))
7596 +               goto skip_tx_iqcal;
7597 +
7598 +       /* Do Tx IQ Calibration */
7599 +       REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_1,
7600 +                     AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT,
7601 +                     DELPT);
7602 +
7603 +       /*
7604 +        * For AR9485 or later chips, TxIQ cal runs as part of
7605 +        * AGC calibration. Specifically, AR9550 in SoC chips.
7606 +        */
7607 +       if (ah->enabled_cals & TX_IQ_ON_AGC_CAL) {
7608 +               txiqcal_done = true;
7609 +               run_agc_cal = true;
7610 +       } else {
7611 +               sep_iq_cal = true;
7612 +               run_agc_cal = true;
7613 +       }
7614 +
7615 +       /*
7616 +        * In the SoC family, this will run for AR9300, AR9331 and AR9340.
7617 +        */
7618 +       if (sep_iq_cal) {
7619 +               txiqcal_done = ar9003_hw_tx_iq_cal_run(ah);
7620 +               REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
7621 +               udelay(5);
7622 +               REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
7623 +       }
7624 +
7625 +skip_tx_iqcal:
7626 +       if (run_agc_cal || !(ah->ah_flags & AH_FASTCC)) {
7627 +               if (AR_SREV_9330_11(ah))
7628 +                       ar9003_hw_manual_peak_cal(ah, 0, IS_CHAN_2GHZ(chan));
7629 +
7630 +               /* Calibrate the AGC */
7631 +               REG_WRITE(ah, AR_PHY_AGC_CONTROL,
7632 +                         REG_READ(ah, AR_PHY_AGC_CONTROL) |
7633 +                         AR_PHY_AGC_CONTROL_CAL);
7634 +
7635 +               /* Poll for offset calibration complete */
7636 +               status = ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
7637 +                                      AR_PHY_AGC_CONTROL_CAL,
7638 +                                      0, AH_WAIT_TIMEOUT);
7639 +       }
7640 +
7641 +       if (!status) {
7642 +               ath_dbg(common, CALIBRATE,
7643 +                       "offset calibration failed to complete in %d ms; noisy environment?\n",
7644 +                       AH_WAIT_TIMEOUT / 1000);
7645 +               return false;
7646 +       }
7647 +
7648 +       if (txiqcal_done)
7649 +               ar9003_hw_tx_iq_cal_post_proc(ah, is_reusable);
7650 +
7651 +       /* Revert chainmask to runtime parameters */
7652 +       ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
7653 +
7654 +       /* Initialize list pointers */
7655 +       ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL;
7656 +
7657 +       INIT_CAL(&ah->iq_caldata);
7658 +       INSERT_CAL(ah, &ah->iq_caldata);
7659 +       ath_dbg(common, CALIBRATE, "enabling IQ Calibration\n");
7660 +
7661 +       /* Initialize current pointer to first element in list */
7662 +       ah->cal_list_curr = ah->cal_list;
7663 +
7664 +       if (ah->cal_list_curr)
7665 +               ath9k_hw_reset_calibration(ah, ah->cal_list_curr);
7666 +
7667 +       if (caldata)
7668 +               caldata->CalValid = 0;
7669 +
7670 +       return true;
7671 +}
7672 +
7673  void ar9003_hw_attach_calib_ops(struct ath_hw *ah)
7674  {
7675         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
7676         struct ath_hw_ops *ops = ath9k_hw_ops(ah);
7677
7678 +       if (AR_SREV_9485(ah) || AR_SREV_9462(ah) || AR_SREV_9565(ah))
7679 +               priv_ops->init_cal = ar9003_hw_init_cal_pcoem;
7680 +       else
7681 +               priv_ops->init_cal = ar9003_hw_init_cal_soc;
7682 +
7683         priv_ops->init_cal_settings = ar9003_hw_init_cal_settings;
7684 -       priv_ops->init_cal = ar9003_hw_init_cal;
7685         priv_ops->setup_calibration = ar9003_hw_setup_calibration;
7686
7687         ops->calibrate = ar9003_hw_calibrate;
7688 --- a/drivers/net/wireless/ath/ath9k/common.c
7689 +++ b/drivers/net/wireless/ath/ath9k/common.c
7690 @@ -98,10 +98,8 @@ struct ath9k_channel *ath9k_cmn_get_chan
7691  {
7692         struct ieee80211_channel *curchan = chandef->chan;
7693         struct ath9k_channel *channel;
7694 -       u8 chan_idx;
7695
7696 -       chan_idx = curchan->hw_value;
7697 -       channel = &ah->channels[chan_idx];
7698 +       channel = &ah->channels[curchan->hw_value];
7699         ath9k_cmn_update_ichannel(channel, chandef);
7700
7701         return channel;
7702 --- a/net/mac80211/rc80211_minstrel_ht.c
7703 +++ b/net/mac80211/rc80211_minstrel_ht.c
7704 @@ -226,7 +226,7 @@ minstrel_ht_calc_tp(struct minstrel_ht_s
7705                 nsecs = 1000 * mi->overhead / MINSTREL_TRUNC(mi->avg_ampdu_len);
7706
7707         nsecs += minstrel_mcs_groups[group].duration[rate];
7708 -       tp = 1000000 * ((mr->probability * 1000) / nsecs);
7709 +       tp = 1000000 * ((prob * 1000) / nsecs);
7710
7711         mr->cur_tp = MINSTREL_TRUNC(tp);
7712  }
7713 --- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
7714 +++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
7715 @@ -131,6 +131,7 @@ static const struct ar9300_eeprom ar9300
7716                 .thresh62 = 28,
7717                 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
7718                 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
7719 +               .switchcomspdt = 0,
7720                 .xlna_bias_strength = 0,
7721                 .futureModal = {
7722                         0, 0, 0, 0, 0, 0, 0,
7723 @@ -138,7 +139,7 @@ static const struct ar9300_eeprom ar9300
7724          },
7725         .base_ext1 = {
7726                 .ant_div_control = 0,
7727 -               .future = {0, 0, 0},
7728 +               .future = {0, 0},
7729                 .tempslopextension = {0, 0, 0, 0, 0, 0, 0, 0}
7730         },
7731         .calFreqPier2G = {
7732 @@ -333,6 +334,7 @@ static const struct ar9300_eeprom ar9300
7733                 .thresh62 = 28,
7734                 .papdRateMaskHt20 = LE32(0x0c80c080),
7735                 .papdRateMaskHt40 = LE32(0x0080c080),
7736 +               .switchcomspdt = 0,
7737                 .xlna_bias_strength = 0,
7738                 .futureModal = {
7739                         0, 0, 0, 0, 0, 0, 0,
7740 @@ -707,6 +709,7 @@ static const struct ar9300_eeprom ar9300
7741                 .thresh62 = 28,
7742                 .papdRateMaskHt20 = LE32(0x0c80c080),
7743                 .papdRateMaskHt40 = LE32(0x0080c080),
7744 +               .switchcomspdt = 0,
7745                 .xlna_bias_strength = 0,
7746                 .futureModal = {
7747                         0, 0, 0, 0, 0, 0, 0,
7748 @@ -714,7 +717,7 @@ static const struct ar9300_eeprom ar9300
7749          },
7750          .base_ext1 = {
7751                 .ant_div_control = 0,
7752 -               .future = {0, 0, 0},
7753 +               .future = {0, 0},
7754                 .tempslopextension = {0, 0, 0, 0, 0, 0, 0, 0}
7755          },
7756         .calFreqPier2G = {
7757 @@ -909,6 +912,7 @@ static const struct ar9300_eeprom ar9300
7758                 .thresh62 = 28,
7759                 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
7760                 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
7761 +               .switchcomspdt = 0,
7762                 .xlna_bias_strength = 0,
7763                 .futureModal = {
7764                         0, 0, 0, 0, 0, 0, 0,
7765 @@ -1284,6 +1288,7 @@ static const struct ar9300_eeprom ar9300
7766                 .thresh62 = 28,
7767                 .papdRateMaskHt20 = LE32(0x0c80c080),
7768                 .papdRateMaskHt40 = LE32(0x0080c080),
7769 +               .switchcomspdt = 0,
7770                 .xlna_bias_strength = 0,
7771                 .futureModal = {
7772                         0, 0, 0, 0, 0, 0, 0,
7773 @@ -1291,7 +1296,7 @@ static const struct ar9300_eeprom ar9300
7774         },
7775         .base_ext1 = {
7776                 .ant_div_control = 0,
7777 -               .future = {0, 0, 0},
7778 +               .future = {0, 0},
7779                 .tempslopextension = {0, 0, 0, 0, 0, 0, 0, 0}
7780         },
7781         .calFreqPier2G = {
7782 @@ -1486,6 +1491,7 @@ static const struct ar9300_eeprom ar9300
7783                 .thresh62 = 28,
7784                 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
7785                 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
7786 +               .switchcomspdt = 0,
7787                 .xlna_bias_strength = 0,
7788                 .futureModal = {
7789                         0, 0, 0, 0, 0, 0, 0,
7790 @@ -1861,6 +1867,7 @@ static const struct ar9300_eeprom ar9300
7791                 .thresh62 = 28,
7792                 .papdRateMaskHt20 = LE32(0x0c80c080),
7793                 .papdRateMaskHt40 = LE32(0x0080c080),
7794 +               .switchcomspdt = 0,
7795                 .xlna_bias_strength = 0,
7796                 .futureModal = {
7797                         0, 0, 0, 0, 0, 0, 0,
7798 @@ -1868,7 +1875,7 @@ static const struct ar9300_eeprom ar9300
7799         },
7800         .base_ext1 = {
7801                 .ant_div_control = 0,
7802 -               .future = {0, 0, 0},
7803 +               .future = {0, 0},
7804                 .tempslopextension = {0, 0, 0, 0, 0, 0, 0, 0}
7805         },
7806         .calFreqPier2G = {
7807 @@ -2063,6 +2070,7 @@ static const struct ar9300_eeprom ar9300
7808                 .thresh62 = 28,
7809                 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
7810                 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
7811 +               .switchcomspdt = 0,
7812                 .xlna_bias_strength = 0,
7813                 .futureModal = {
7814                         0, 0, 0, 0, 0, 0, 0,
7815 @@ -2437,6 +2445,7 @@ static const struct ar9300_eeprom ar9300
7816                 .thresh62 = 28,
7817                 .papdRateMaskHt20 = LE32(0x0c80C080),
7818                 .papdRateMaskHt40 = LE32(0x0080C080),
7819 +               .switchcomspdt = 0,
7820                 .xlna_bias_strength = 0,
7821                 .futureModal = {
7822                         0, 0, 0, 0, 0, 0, 0,
7823 @@ -2444,7 +2453,7 @@ static const struct ar9300_eeprom ar9300
7824          },
7825          .base_ext1 = {
7826                 .ant_div_control = 0,
7827 -               .future = {0, 0, 0},
7828 +               .future = {0, 0},
7829                 .tempslopextension = {0, 0, 0, 0, 0, 0, 0, 0}
7830          },
7831         .calFreqPier2G = {
7832 @@ -2639,6 +2648,7 @@ static const struct ar9300_eeprom ar9300
7833                 .thresh62 = 28,
7834                 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
7835                 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
7836 +               .switchcomspdt = 0,
7837                 .xlna_bias_strength = 0,
7838                 .futureModal = {
7839                         0, 0, 0, 0, 0, 0, 0,
7840 @@ -3965,7 +3975,7 @@ static void ar9003_hw_apply_tuning_caps(
7841         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
7842         u8 tuning_caps_param = eep->baseEepHeader.params_for_tuning_caps[0];
7843
7844 -       if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
7845 +       if (AR_SREV_9340(ah))
7846                 return;
7847
7848         if (eep->baseEepHeader.featureEnable & 0x40) {
7849 @@ -3984,18 +3994,20 @@ static void ar9003_hw_quick_drop_apply(s
7850         int quick_drop;
7851         s32 t[3], f[3] = {5180, 5500, 5785};
7852
7853 -       if (!(pBase->miscConfiguration & BIT(1)))
7854 +       if (!(pBase->miscConfiguration & BIT(4)))
7855                 return;
7856
7857 -       if (freq < 4000)
7858 -               quick_drop = eep->modalHeader2G.quick_drop;
7859 -       else {
7860 -               t[0] = eep->base_ext1.quick_drop_low;
7861 -               t[1] = eep->modalHeader5G.quick_drop;
7862 -               t[2] = eep->base_ext1.quick_drop_high;
7863 -               quick_drop = ar9003_hw_power_interpolate(freq, f, t, 3);
7864 +       if (AR_SREV_9300(ah) || AR_SREV_9580(ah) || AR_SREV_9340(ah)) {
7865 +               if (freq < 4000) {
7866 +                       quick_drop = eep->modalHeader2G.quick_drop;
7867 +               } else {
7868 +                       t[0] = eep->base_ext1.quick_drop_low;
7869 +                       t[1] = eep->modalHeader5G.quick_drop;
7870 +                       t[2] = eep->base_ext1.quick_drop_high;
7871 +                       quick_drop = ar9003_hw_power_interpolate(freq, f, t, 3);
7872 +               }
7873 +               REG_RMW_FIELD(ah, AR_PHY_AGC, AR_PHY_AGC_QUICK_DROP, quick_drop);
7874         }
7875 -       REG_RMW_FIELD(ah, AR_PHY_AGC, AR_PHY_AGC_QUICK_DROP, quick_drop);
7876  }
7877
7878  static void ar9003_hw_txend_to_xpa_off_apply(struct ath_hw *ah, bool is2ghz)
7879 @@ -4035,7 +4047,7 @@ static void ar9003_hw_xlna_bias_strength
7880         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
7881         u8 bias;
7882
7883 -       if (!(eep->baseEepHeader.featureEnable & 0x40))
7884 +       if (!(eep->baseEepHeader.miscConfiguration & 0x40))
7885                 return;
7886
7887         if (!AR_SREV_9300(ah))
7888 @@ -4109,6 +4121,37 @@ static void ar9003_hw_thermo_cal_apply(s
7889         }
7890  }
7891
7892 +static void ar9003_hw_apply_minccapwr_thresh(struct ath_hw *ah,
7893 +                                            bool is2ghz)
7894 +{
7895 +       struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
7896 +       const u_int32_t cca_ctrl[AR9300_MAX_CHAINS] = {
7897 +               AR_PHY_CCA_CTRL_0,
7898 +               AR_PHY_CCA_CTRL_1,
7899 +               AR_PHY_CCA_CTRL_2,
7900 +       };
7901 +       int chain;
7902 +       u32 val;
7903 +
7904 +       if (is2ghz) {
7905 +               if (!(eep->base_ext1.misc_enable & BIT(2)))
7906 +                       return;
7907 +       } else {
7908 +               if (!(eep->base_ext1.misc_enable & BIT(3)))
7909 +                       return;
7910 +       }
7911 +
7912 +       for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
7913 +               if (!(ah->caps.tx_chainmask & BIT(chain)))
7914 +                       continue;
7915 +
7916 +               val = ar9003_modal_header(ah, is2ghz)->noiseFloorThreshCh[chain];
7917 +               REG_RMW_FIELD(ah, cca_ctrl[chain],
7918 +                             AR_PHY_EXT_CCA0_THRESH62_1, val);
7919 +       }
7920 +
7921 +}
7922 +
7923  static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
7924                                              struct ath9k_channel *chan)
7925  {
7926 @@ -4120,9 +4163,10 @@ static void ath9k_hw_ar9300_set_board_va
7927         ar9003_hw_xlna_bias_strength_apply(ah, is2ghz);
7928         ar9003_hw_atten_apply(ah, chan);
7929         ar9003_hw_quick_drop_apply(ah, chan->channel);
7930 -       if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah) && !AR_SREV_9550(ah))
7931 +       if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah))
7932                 ar9003_hw_internal_regulator_apply(ah);
7933         ar9003_hw_apply_tuning_caps(ah);
7934 +       ar9003_hw_apply_minccapwr_thresh(ah, chan);
7935         ar9003_hw_txend_to_xpa_off_apply(ah, is2ghz);
7936         ar9003_hw_thermometer_apply(ah);
7937         ar9003_hw_thermo_cal_apply(ah);
7938 --- a/net/mac80211/ieee80211_i.h
7939 +++ b/net/mac80211/ieee80211_i.h
7940 @@ -735,6 +735,7 @@ struct ieee80211_sub_if_data {
7941         int csa_counter_offset_beacon;
7942         int csa_counter_offset_presp;
7943         bool csa_radar_required;
7944 +       struct cfg80211_chan_def csa_chandef;
7945
7946         /* used to reconfigure hardware SM PS */
7947         struct work_struct recalc_smps;
7948 @@ -811,6 +812,9 @@ static inline void sdata_unlock(struct i
7949         __release(&sdata->wdev.mtx);
7950  }
7951
7952 +#define sdata_dereference(p, sdata) \
7953 +       rcu_dereference_protected(p, lockdep_is_held(&sdata->wdev.mtx))
7954 +
7955  static inline void
7956  sdata_assert_lock(struct ieee80211_sub_if_data *sdata)
7957  {
7958 @@ -1098,7 +1102,6 @@ struct ieee80211_local {
7959         enum mac80211_scan_state next_scan_state;
7960         struct delayed_work scan_work;
7961         struct ieee80211_sub_if_data __rcu *scan_sdata;
7962 -       struct cfg80211_chan_def csa_chandef;
7963         /* For backward compatibility only -- do not use */
7964         struct cfg80211_chan_def _oper_chandef;
7965
7966 @@ -1236,6 +1239,7 @@ struct ieee80211_csa_ie {
7967         u8 mode;
7968         u8 count;
7969         u8 ttl;
7970 +       u16 pre_value;
7971  };
7972
7973  /* Parsed Information Elements */
7974 @@ -1738,7 +1742,6 @@ ieee80211_vif_change_bandwidth(struct ie
7975  /* NOTE: only use ieee80211_vif_change_channel() for channel switch */
7976  int __must_check
7977  ieee80211_vif_change_channel(struct ieee80211_sub_if_data *sdata,
7978 -                            const struct cfg80211_chan_def *chandef,
7979                              u32 *changed);
7980  void ieee80211_vif_release_channel(struct ieee80211_sub_if_data *sdata);
7981  void ieee80211_vif_vlan_copy_chanctx(struct ieee80211_sub_if_data *sdata);
7982 --- a/net/mac80211/chan.c
7983 +++ b/net/mac80211/chan.c
7984 @@ -411,12 +411,12 @@ int ieee80211_vif_use_channel(struct iee
7985  }
7986
7987  int ieee80211_vif_change_channel(struct ieee80211_sub_if_data *sdata,
7988 -                                const struct cfg80211_chan_def *chandef,
7989                                  u32 *changed)
7990  {
7991         struct ieee80211_local *local = sdata->local;
7992         struct ieee80211_chanctx_conf *conf;
7993         struct ieee80211_chanctx *ctx;
7994 +       const struct cfg80211_chan_def *chandef = &sdata->csa_chandef;
7995         int ret;
7996         u32 chanctx_changed = 0;
7997
7998 --- a/net/mac80211/ibss.c
7999 +++ b/net/mac80211/ibss.c
8000 @@ -534,7 +534,7 @@ int ieee80211_ibss_finish_csa(struct iee
8001         int err;
8002         u16 capability;
8003
8004 -       sdata_lock(sdata);
8005 +       sdata_assert_lock(sdata);
8006         /* update cfg80211 bss information with the new channel */
8007         if (!is_zero_ether_addr(ifibss->bssid)) {
8008                 capability = WLAN_CAPABILITY_IBSS;
8009 @@ -550,16 +550,15 @@ int ieee80211_ibss_finish_csa(struct iee
8010                                         capability);
8011                 /* XXX: should not really modify cfg80211 data */
8012                 if (cbss) {
8013 -                       cbss->channel = sdata->local->csa_chandef.chan;
8014 +                       cbss->channel = sdata->csa_chandef.chan;
8015                         cfg80211_put_bss(sdata->local->hw.wiphy, cbss);
8016                 }
8017         }
8018
8019 -       ifibss->chandef = sdata->local->csa_chandef;
8020 +       ifibss->chandef = sdata->csa_chandef;
8021
8022         /* generate the beacon */
8023         err = ieee80211_ibss_csa_beacon(sdata, NULL);
8024 -       sdata_unlock(sdata);
8025         if (err < 0)
8026                 return err;
8027
8028 @@ -922,7 +921,7 @@ ieee80211_ibss_process_chanswitch(struct
8029                                 IEEE80211_MAX_QUEUE_MAP,
8030                                 IEEE80211_QUEUE_STOP_REASON_CSA);
8031
8032 -       sdata->local->csa_chandef = params.chandef;
8033 +       sdata->csa_chandef = params.chandef;
8034         sdata->vif.csa_active = true;
8035
8036         ieee80211_bss_info_change_notify(sdata, err);
8037 --- a/net/mac80211/mesh.c
8038 +++ b/net/mac80211/mesh.c
8039 @@ -943,14 +943,19 @@ ieee80211_mesh_process_chnswitch(struct
8040                  params.chandef.chan->center_freq);
8041
8042         params.block_tx = csa_ie.mode & WLAN_EID_CHAN_SWITCH_PARAM_TX_RESTRICT;
8043 -       if (beacon)
8044 +       if (beacon) {
8045                 ifmsh->chsw_ttl = csa_ie.ttl - 1;
8046 -       else
8047 -               ifmsh->chsw_ttl = 0;
8048 +               if (ifmsh->pre_value >= csa_ie.pre_value)
8049 +                       return false;
8050 +               ifmsh->pre_value = csa_ie.pre_value;
8051 +       }
8052
8053 -       if (ifmsh->chsw_ttl > 0)
8054 +       if (ifmsh->chsw_ttl < ifmsh->mshcfg.dot11MeshTTL) {
8055                 if (ieee80211_mesh_csa_beacon(sdata, &params, false) < 0)
8056                         return false;
8057 +       } else {
8058 +               return false;
8059 +       }
8060
8061         sdata->csa_radar_required = params.radar_required;
8062
8063 @@ -959,7 +964,7 @@ ieee80211_mesh_process_chnswitch(struct
8064                                 IEEE80211_MAX_QUEUE_MAP,
8065                                 IEEE80211_QUEUE_STOP_REASON_CSA);
8066
8067 -       sdata->local->csa_chandef = params.chandef;
8068 +       sdata->csa_chandef = params.chandef;
8069         sdata->vif.csa_active = true;
8070
8071         ieee80211_bss_info_change_notify(sdata, err);
8072 @@ -1163,7 +1168,6 @@ static int mesh_fwd_csa_frame(struct iee
8073         offset_ttl = (len < 42) ? 7 : 10;
8074         *(pos + offset_ttl) -= 1;
8075         *(pos + offset_ttl + 1) &= ~WLAN_EID_CHAN_SWITCH_PARAM_INITIATOR;
8076 -       sdata->u.mesh.chsw_ttl = *(pos + offset_ttl);
8077
8078         memcpy(mgmt_fwd, mgmt, len);
8079         eth_broadcast_addr(mgmt_fwd->da);
8080 @@ -1182,7 +1186,7 @@ static void mesh_rx_csa_frame(struct iee
8081         u16 pre_value;
8082         bool fwd_csa = true;
8083         size_t baselen;
8084 -       u8 *pos, ttl;
8085 +       u8 *pos;
8086
8087         if (mgmt->u.action.u.measurement.action_code !=
8088             WLAN_ACTION_SPCT_CHL_SWITCH)
8089 @@ -1193,8 +1197,8 @@ static void mesh_rx_csa_frame(struct iee
8090                            u.action.u.chan_switch.variable);
8091         ieee802_11_parse_elems(pos, len - baselen, false, &elems);
8092
8093 -       ttl = elems.mesh_chansw_params_ie->mesh_ttl;
8094 -       if (!--ttl)
8095 +       ifmsh->chsw_ttl = elems.mesh_chansw_params_ie->mesh_ttl;
8096 +       if (!--ifmsh->chsw_ttl)
8097                 fwd_csa = false;
8098
8099         pre_value = le16_to_cpu(elems.mesh_chansw_params_ie->mesh_pre_value);
8100 --- a/net/mac80211/spectmgmt.c
8101 +++ b/net/mac80211/spectmgmt.c
8102 @@ -78,6 +78,8 @@ int ieee80211_parse_ch_switch_ie(struct
8103         if (elems->mesh_chansw_params_ie) {
8104                 csa_ie->ttl = elems->mesh_chansw_params_ie->mesh_ttl;
8105                 csa_ie->mode = elems->mesh_chansw_params_ie->mesh_flags;
8106 +               csa_ie->pre_value = le16_to_cpu(
8107 +                               elems->mesh_chansw_params_ie->mesh_pre_value);
8108         }
8109
8110         new_freq = ieee80211_channel_to_frequency(new_chan_no, new_band);
8111 --- a/drivers/net/wireless/ath/ath6kl/cfg80211.c
8112 +++ b/drivers/net/wireless/ath/ath6kl/cfg80211.c
8113 @@ -1109,7 +1109,9 @@ void ath6kl_cfg80211_ch_switch_notify(st
8114                                 (mode == WMI_11G_HT20) ?
8115                                         NL80211_CHAN_HT20 : NL80211_CHAN_NO_HT);
8116
8117 +       mutex_lock(vif->wdev->mtx);
8118         cfg80211_ch_switch_notify(vif->ndev, &chandef);
8119 +       mutex_unlock(vif->wdev->mtx);
8120  }
8121
8122  static int ath6kl_cfg80211_add_key(struct wiphy *wiphy, struct net_device *ndev,
8123 --- a/drivers/net/wireless/ath/ath9k/ar9462_2p1_initvals.h
8124 +++ b/drivers/net/wireless/ath/ath9k/ar9462_2p1_initvals.h
8125 @@ -20,6 +20,44 @@
8126
8127  /* AR9462 2.1 */
8128
8129 +#define ar9462_2p1_mac_postamble ar9462_2p0_mac_postamble
8130 +
8131 +#define ar9462_2p1_baseband_core ar9462_2p0_baseband_core
8132 +
8133 +#define ar9462_2p1_radio_core ar9462_2p0_radio_core
8134 +
8135 +#define ar9462_2p1_radio_postamble ar9462_2p0_radio_postamble
8136 +
8137 +#define ar9462_2p1_soc_postamble ar9462_2p0_soc_postamble
8138 +
8139 +#define ar9462_2p1_radio_postamble_sys2ant ar9462_2p0_radio_postamble_sys2ant
8140 +
8141 +#define ar9462_2p1_common_rx_gain ar9462_2p0_common_rx_gain
8142 +
8143 +#define ar9462_2p1_common_mixed_rx_gain ar9462_2p0_common_mixed_rx_gain
8144 +
8145 +#define ar9462_2p1_common_5g_xlna_only_rxgain ar9462_2p0_common_5g_xlna_only_rxgain
8146 +
8147 +#define ar9462_2p1_baseband_core_mix_rxgain ar9462_2p0_baseband_core_mix_rxgain
8148 +
8149 +#define ar9462_2p1_baseband_postamble_mix_rxgain ar9462_2p0_baseband_postamble_mix_rxgain
8150 +
8151 +#define ar9462_2p1_baseband_postamble_5g_xlna ar9462_2p0_baseband_postamble_5g_xlna
8152 +
8153 +#define ar9462_2p1_common_wo_xlna_rx_gain ar9462_2p0_common_wo_xlna_rx_gain
8154 +
8155 +#define ar9462_2p1_modes_low_ob_db_tx_gain ar9462_2p0_modes_low_ob_db_tx_gain
8156 +
8157 +#define ar9462_2p1_modes_high_ob_db_tx_gain ar9462_2p0_modes_high_ob_db_tx_gain
8158 +
8159 +#define ar9462_2p1_modes_mix_ob_db_tx_gain ar9462_2p0_modes_mix_ob_db_tx_gain
8160 +
8161 +#define ar9462_2p1_modes_fast_clock ar9462_2p0_modes_fast_clock
8162 +
8163 +#define ar9462_2p1_baseband_core_txfir_coeff_japan_2484 ar9462_2p0_baseband_core_txfir_coeff_japan_2484
8164 +
8165 +#define ar9462_2p1_pciephy_clkreq_disable_L1 ar9462_2p0_pciephy_clkreq_disable_L1
8166 +
8167  static const u32 ar9462_2p1_mac_core[][2] = {
8168         /* Addr      allmodes  */
8169         {0x00000008, 0x00000000},
8170 @@ -183,168 +221,6 @@ static const u32 ar9462_2p1_mac_core[][2
8171         {0x000083d0, 0x000301ff},
8172  };
8173
8174 -static const u32 ar9462_2p1_mac_postamble[][5] = {
8175 -       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
8176 -       {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
8177 -       {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
8178 -       {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
8179 -       {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
8180 -       {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b},
8181 -       {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
8182 -       {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
8183 -       {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
8184 -};
8185 -
8186 -static const u32 ar9462_2p1_baseband_core[][2] = {
8187 -       /* Addr      allmodes  */
8188 -       {0x00009800, 0xafe68e30},
8189 -       {0x00009804, 0xfd14e000},
8190 -       {0x00009808, 0x9c0a9f6b},
8191 -       {0x0000980c, 0x04900000},
8192 -       {0x00009814, 0x9280c00a},
8193 -       {0x00009818, 0x00000000},
8194 -       {0x0000981c, 0x00020028},
8195 -       {0x00009834, 0x6400a290},
8196 -       {0x00009838, 0x0108ecff},
8197 -       {0x0000983c, 0x0d000600},
8198 -       {0x00009880, 0x201fff00},
8199 -       {0x00009884, 0x00001042},
8200 -       {0x000098a4, 0x00200400},
8201 -       {0x000098b0, 0x32440bbe},
8202 -       {0x000098d0, 0x004b6a8e},
8203 -       {0x000098d4, 0x00000820},
8204 -       {0x000098dc, 0x00000000},
8205 -       {0x000098e4, 0x01ffffff},
8206 -       {0x000098e8, 0x01ffffff},
8207 -       {0x000098ec, 0x01ffffff},
8208 -       {0x000098f0, 0x00000000},
8209 -       {0x000098f4, 0x00000000},
8210 -       {0x00009bf0, 0x80000000},
8211 -       {0x00009c04, 0xff55ff55},
8212 -       {0x00009c08, 0x0320ff55},
8213 -       {0x00009c0c, 0x00000000},
8214 -       {0x00009c10, 0x00000000},
8215 -       {0x00009c14, 0x00046384},
8216 -       {0x00009c18, 0x05b6b440},
8217 -       {0x00009c1c, 0x00b6b440},
8218 -       {0x00009d00, 0xc080a333},
8219 -       {0x00009d04, 0x40206c10},
8220 -       {0x00009d08, 0x009c4060},
8221 -       {0x00009d0c, 0x9883800a},
8222 -       {0x00009d10, 0x01834061},
8223 -       {0x00009d14, 0x00c0040b},
8224 -       {0x00009d18, 0x00000000},
8225 -       {0x00009e08, 0x0038230c},
8226 -       {0x00009e24, 0x990bb515},
8227 -       {0x00009e28, 0x0c6f0000},
8228 -       {0x00009e30, 0x06336f77},
8229 -       {0x00009e34, 0x6af6532f},
8230 -       {0x00009e38, 0x0cc80c00},
8231 -       {0x00009e40, 0x15262820},
8232 -       {0x00009e4c, 0x00001004},
8233 -       {0x00009e50, 0x00ff03f1},
8234 -       {0x00009e54, 0xe4c555c2},
8235 -       {0x00009e58, 0xfd857722},
8236 -       {0x00009e5c, 0xe9198724},
8237 -       {0x00009fc0, 0x803e4788},
8238 -       {0x00009fc4, 0x0001efb5},
8239 -       {0x00009fcc, 0x40000014},
8240 -       {0x00009fd0, 0x0a193b93},
8241 -       {0x0000a20c, 0x00000000},
8242 -       {0x0000a220, 0x00000000},
8243 -       {0x0000a224, 0x00000000},
8244 -       {0x0000a228, 0x10002310},
8245 -       {0x0000a23c, 0x00000000},
8246 -       {0x0000a244, 0x0c000000},
8247 -       {0x0000a2a0, 0x00000001},
8248 -       {0x0000a2c0, 0x00000001},
8249 -       {0x0000a2c8, 0x00000000},
8250 -       {0x0000a2cc, 0x18c43433},
8251 -       {0x0000a2d4, 0x00000000},
8252 -       {0x0000a2ec, 0x00000000},
8253 -       {0x0000a2f0, 0x00000000},
8254 -       {0x0000a2f4, 0x00000000},
8255 -       {0x0000a2f8, 0x00000000},
8256 -       {0x0000a344, 0x00000000},
8257 -       {0x0000a34c, 0x00000000},
8258 -       {0x0000a350, 0x0000a000},
8259 -       {0x0000a364, 0x00000000},
8260 -       {0x0000a370, 0x00000000},
8261 -       {0x0000a390, 0x00000001},
8262 -       {0x0000a394, 0x00000444},
8263 -       {0x0000a398, 0x001f0e0f},
8264 -       {0x0000a39c, 0x0075393f},
8265 -       {0x0000a3a0, 0xb79f6427},
8266 -       {0x0000a3c0, 0x20202020},
8267 -       {0x0000a3c4, 0x22222220},
8268 -       {0x0000a3c8, 0x20200020},
8269 -       {0x0000a3cc, 0x20202020},
8270 -       {0x0000a3d0, 0x20202020},
8271 -       {0x0000a3d4, 0x20202020},
8272 -       {0x0000a3d8, 0x20202020},
8273 -       {0x0000a3dc, 0x20202020},
8274 -       {0x0000a3e0, 0x20202020},
8275 -       {0x0000a3e4, 0x20202020},
8276 -       {0x0000a3e8, 0x20202020},
8277 -       {0x0000a3ec, 0x20202020},
8278 -       {0x0000a3f0, 0x00000000},
8279 -       {0x0000a3f4, 0x00000006},
8280 -       {0x0000a3f8, 0x0c9bd380},
8281 -       {0x0000a3fc, 0x000f0f01},
8282 -       {0x0000a400, 0x8fa91f01},
8283 -       {0x0000a404, 0x00000000},
8284 -       {0x0000a408, 0x0e79e5c6},
8285 -       {0x0000a40c, 0x00820820},
8286 -       {0x0000a414, 0x1ce739ce},
8287 -       {0x0000a418, 0x2d001dce},
8288 -       {0x0000a434, 0x00000000},
8289 -       {0x0000a438, 0x00001801},
8290 -       {0x0000a43c, 0x00100000},
8291 -       {0x0000a444, 0x00000000},
8292 -       {0x0000a448, 0x05000080},
8293 -       {0x0000a44c, 0x00000001},
8294 -       {0x0000a450, 0x00010000},
8295 -       {0x0000a454, 0x07000000},
8296 -       {0x0000a644, 0xbfad9d74},
8297 -       {0x0000a648, 0x0048060a},
8298 -       {0x0000a64c, 0x00002037},
8299 -       {0x0000a670, 0x03020100},
8300 -       {0x0000a674, 0x09080504},
8301 -       {0x0000a678, 0x0d0c0b0a},
8302 -       {0x0000a67c, 0x13121110},
8303 -       {0x0000a680, 0x31301514},
8304 -       {0x0000a684, 0x35343332},
8305 -       {0x0000a688, 0x00000036},
8306 -       {0x0000a690, 0x00000838},
8307 -       {0x0000a6b0, 0x0000000a},
8308 -       {0x0000a6b4, 0x00512c01},
8309 -       {0x0000a7c0, 0x00000000},
8310 -       {0x0000a7c4, 0xfffffffc},
8311 -       {0x0000a7c8, 0x00000000},
8312 -       {0x0000a7cc, 0x00000000},
8313 -       {0x0000a7d0, 0x00000000},
8314 -       {0x0000a7d4, 0x00000004},
8315 -       {0x0000a7dc, 0x00000000},
8316 -       {0x0000a7f0, 0x80000000},
8317 -       {0x0000a8d0, 0x004b6a8e},
8318 -       {0x0000a8d4, 0x00000820},
8319 -       {0x0000a8dc, 0x00000000},
8320 -       {0x0000a8f0, 0x00000000},
8321 -       {0x0000a8f4, 0x00000000},
8322 -       {0x0000abf0, 0x80000000},
8323 -       {0x0000b2d0, 0x00000080},
8324 -       {0x0000b2d4, 0x00000000},
8325 -       {0x0000b2ec, 0x00000000},
8326 -       {0x0000b2f0, 0x00000000},
8327 -       {0x0000b2f4, 0x00000000},
8328 -       {0x0000b2f8, 0x00000000},
8329 -       {0x0000b408, 0x0e79e5c0},
8330 -       {0x0000b40c, 0x00820820},
8331 -       {0x0000b420, 0x00000000},
8332 -       {0x0000b6b0, 0x0000000a},
8333 -       {0x0000b6b4, 0x00000001},
8334 -};
8335 -
8336  static const u32 ar9462_2p1_baseband_postamble[][5] = {
8337         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
8338         {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a800d},
8339 @@ -361,7 +237,7 @@ static const u32 ar9462_2p1_baseband_pos
8340         {0x00009e14, 0x37b95d5e, 0x37b9605e, 0x3236605e, 0x32365a5e},
8341         {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8342         {0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c},
8343 -       {0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce},
8344 +       {0x00009e20, 0x000003a5, 0x000003a5, 0x000003a5, 0x000003a5},
8345         {0x00009e2c, 0x0000001c, 0x0000001c, 0x00000021, 0x00000021},
8346         {0x00009e3c, 0xcf946220, 0xcf946220, 0xcfd5c782, 0xcfd5c282},
8347         {0x00009e44, 0x62321e27, 0x62321e27, 0xfe291e27, 0xfe291e27},
8348 @@ -400,1375 +276,16 @@ static const u32 ar9462_2p1_baseband_pos
8349         {0x0000ae04, 0x001c0000, 0x001c0000, 0x001c0000, 0x00100000},
8350         {0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8351         {0x0000ae1c, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
8352 -       {0x0000ae20, 0x000001b5, 0x000001b5, 0x000001ce, 0x000001ce},
8353 +       {0x0000ae20, 0x000001a6, 0x000001a6, 0x000001aa, 0x000001aa},
8354         {0x0000b284, 0x00000000, 0x00000000, 0x00000550, 0x00000550},
8355  };
8356
8357 -static const u32 ar9462_2p1_radio_core[][2] = {
8358 -       /* Addr      allmodes  */
8359 -       {0x00016000, 0x36db6db6},
8360 -       {0x00016004, 0x6db6db40},
8361 -       {0x00016008, 0x73f00000},
8362 -       {0x0001600c, 0x00000000},
8363 -       {0x00016010, 0x6d820001},
8364 -       {0x00016040, 0x7f80fff8},
8365 -       {0x0001604c, 0x2699e04f},
8366 -       {0x00016050, 0x6db6db6c},
8367 -       {0x00016058, 0x6c200000},
8368 -       {0x00016080, 0x000c0000},
8369 -       {0x00016084, 0x9a68048c},
8370 -       {0x00016088, 0x54214514},
8371 -       {0x0001608c, 0x1203040b},
8372 -       {0x00016090, 0x24926490},
8373 -       {0x00016098, 0xd2888888},
8374 -       {0x000160a0, 0x0a108ffe},
8375 -       {0x000160a4, 0x812fc491},
8376 -       {0x000160a8, 0x423c8000},
8377 -       {0x000160b4, 0x92000000},
8378 -       {0x000160b8, 0x0285dddc},
8379 -       {0x000160bc, 0x02908888},
8380 -       {0x000160c0, 0x00adb6d0},
8381 -       {0x000160c4, 0x6db6db60},
8382 -       {0x000160c8, 0x6db6db6c},
8383 -       {0x000160cc, 0x0de6c1b0},
8384 -       {0x00016100, 0x3fffbe04},
8385 -       {0x00016104, 0xfff80000},
8386 -       {0x00016108, 0x00200400},
8387 -       {0x00016110, 0x00000000},
8388 -       {0x00016144, 0x02084080},
8389 -       {0x00016148, 0x000080c0},
8390 -       {0x00016280, 0x050a0001},
8391 -       {0x00016284, 0x3d841418},
8392 -       {0x00016288, 0x00000000},
8393 -       {0x0001628c, 0xe3000000},
8394 -       {0x00016290, 0xa1005080},
8395 -       {0x00016294, 0x00000020},
8396 -       {0x00016298, 0x54a82900},
8397 -       {0x00016340, 0x121e4276},
8398 -       {0x00016344, 0x00300000},
8399 -       {0x00016400, 0x36db6db6},
8400 -       {0x00016404, 0x6db6db40},
8401 -       {0x00016408, 0x73f00000},
8402 -       {0x0001640c, 0x00000000},
8403 -       {0x00016410, 0x6c800001},
8404 -       {0x00016440, 0x7f80fff8},
8405 -       {0x0001644c, 0x4699e04f},
8406 -       {0x00016450, 0x6db6db6c},
8407 -       {0x00016500, 0x3fffbe04},
8408 -       {0x00016504, 0xfff80000},
8409 -       {0x00016508, 0x00200400},
8410 -       {0x00016510, 0x00000000},
8411 -       {0x00016544, 0x02084080},
8412 -       {0x00016548, 0x000080c0},
8413 -};
8414 -
8415 -static const u32 ar9462_2p1_radio_postamble[][5] = {
8416 -       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
8417 -       {0x0001609c, 0x0b8ee524, 0x0b8ee524, 0x0b8ee524, 0x0b8ee524},
8418 -       {0x000160b0, 0x01d67f70, 0x01d67f70, 0x01d67f70, 0x01d67f70},
8419 -       {0x0001610c, 0x48000000, 0x40000000, 0x40000000, 0x40000000},
8420 -       {0x0001650c, 0x48000000, 0x40000000, 0x40000000, 0x40000000},
8421 -};
8422 -
8423  static const u32 ar9462_2p1_soc_preamble[][2] = {
8424         /* Addr      allmodes  */
8425 -       {0x000040a4, 0x00a0c1c9},
8426 +       {0x000040a4, 0x00a0c9c9},
8427         {0x00007020, 0x00000000},
8428         {0x00007034, 0x00000002},
8429         {0x00007038, 0x000004c2},
8430  };
8431
8432 -static const u32 ar9462_2p1_soc_postamble[][5] = {
8433 -       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
8434 -       {0x00007010, 0x00000033, 0x00000033, 0x00000033, 0x00000033},
8435 -};
8436 -
8437 -static const u32 ar9462_2p1_radio_postamble_sys2ant[][5] = {
8438 -       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
8439 -       {0x000160ac, 0xa4646c08, 0xa4646c08, 0x24645808, 0x24645808},
8440 -       {0x00016140, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
8441 -       {0x00016540, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
8442 -};
8443 -
8444 -static const u32 ar9462_2p1_common_rx_gain[][2] = {
8445 -       /* Addr      allmodes  */
8446 -       {0x0000a000, 0x00010000},
8447 -       {0x0000a004, 0x00030002},
8448 -       {0x0000a008, 0x00050004},
8449 -       {0x0000a00c, 0x00810080},
8450 -       {0x0000a010, 0x00830082},
8451 -       {0x0000a014, 0x01810180},
8452 -       {0x0000a018, 0x01830182},
8453 -       {0x0000a01c, 0x01850184},
8454 -       {0x0000a020, 0x01890188},
8455 -       {0x0000a024, 0x018b018a},
8456 -       {0x0000a028, 0x018d018c},
8457 -       {0x0000a02c, 0x01910190},
8458 -       {0x0000a030, 0x01930192},
8459 -       {0x0000a034, 0x01950194},
8460 -       {0x0000a038, 0x038a0196},
8461 -       {0x0000a03c, 0x038c038b},
8462 -       {0x0000a040, 0x0390038d},
8463 -       {0x0000a044, 0x03920391},
8464 -       {0x0000a048, 0x03940393},
8465 -       {0x0000a04c, 0x03960395},
8466 -       {0x0000a050, 0x00000000},
8467 -       {0x0000a054, 0x00000000},
8468 -       {0x0000a058, 0x00000000},
8469 -       {0x0000a05c, 0x00000000},
8470 -       {0x0000a060, 0x00000000},
8471 -       {0x0000a064, 0x00000000},
8472 -       {0x0000a068, 0x00000000},
8473 -       {0x0000a06c, 0x00000000},
8474 -       {0x0000a070, 0x00000000},
8475 -       {0x0000a074, 0x00000000},
8476 -       {0x0000a078, 0x00000000},
8477 -       {0x0000a07c, 0x00000000},
8478 -       {0x0000a080, 0x22222229},
8479 -       {0x0000a084, 0x1d1d1d1d},
8480 -       {0x0000a088, 0x1d1d1d1d},
8481 -       {0x0000a08c, 0x1d1d1d1d},
8482 -       {0x0000a090, 0x171d1d1d},
8483 -       {0x0000a094, 0x11111717},
8484 -       {0x0000a098, 0x00030311},
8485 -       {0x0000a09c, 0x00000000},
8486 -       {0x0000a0a0, 0x00000000},
8487 -       {0x0000a0a4, 0x00000000},
8488 -       {0x0000a0a8, 0x00000000},
8489 -       {0x0000a0ac, 0x00000000},
8490 -       {0x0000a0b0, 0x00000000},
8491 -       {0x0000a0b4, 0x00000000},
8492 -       {0x0000a0b8, 0x00000000},
8493 -       {0x0000a0bc, 0x00000000},
8494 -       {0x0000a0c0, 0x001f0000},
8495 -       {0x0000a0c4, 0x01000101},
8496 -       {0x0000a0c8, 0x011e011f},
8497 -       {0x0000a0cc, 0x011c011d},
8498 -       {0x0000a0d0, 0x02030204},
8499 -       {0x0000a0d4, 0x02010202},
8500 -       {0x0000a0d8, 0x021f0200},
8501 -       {0x0000a0dc, 0x0302021e},
8502 -       {0x0000a0e0, 0x03000301},
8503 -       {0x0000a0e4, 0x031e031f},
8504 -       {0x0000a0e8, 0x0402031d},
8505 -       {0x0000a0ec, 0x04000401},
8506 -       {0x0000a0f0, 0x041e041f},
8507 -       {0x0000a0f4, 0x0502041d},
8508 -       {0x0000a0f8, 0x05000501},
8509 -       {0x0000a0fc, 0x051e051f},
8510 -       {0x0000a100, 0x06010602},
8511 -       {0x0000a104, 0x061f0600},
8512 -       {0x0000a108, 0x061d061e},
8513 -       {0x0000a10c, 0x07020703},
8514 -       {0x0000a110, 0x07000701},
8515 -       {0x0000a114, 0x00000000},
8516 -       {0x0000a118, 0x00000000},
8517 -       {0x0000a11c, 0x00000000},
8518 -       {0x0000a120, 0x00000000},
8519 -       {0x0000a124, 0x00000000},
8520 -       {0x0000a128, 0x00000000},
8521 -       {0x0000a12c, 0x00000000},
8522 -       {0x0000a130, 0x00000000},
8523 -       {0x0000a134, 0x00000000},
8524 -       {0x0000a138, 0x00000000},
8525 -       {0x0000a13c, 0x00000000},
8526 -       {0x0000a140, 0x001f0000},
8527 -       {0x0000a144, 0x01000101},
8528 -       {0x0000a148, 0x011e011f},
8529 -       {0x0000a14c, 0x011c011d},
8530 -       {0x0000a150, 0x02030204},
8531 -       {0x0000a154, 0x02010202},
8532 -       {0x0000a158, 0x021f0200},
8533 -       {0x0000a15c, 0x0302021e},
8534 -       {0x0000a160, 0x03000301},
8535 -       {0x0000a164, 0x031e031f},
8536 -       {0x0000a168, 0x0402031d},
8537 -       {0x0000a16c, 0x04000401},
8538 -       {0x0000a170, 0x041e041f},
8539 -       {0x0000a174, 0x0502041d},
8540 -       {0x0000a178, 0x05000501},
8541 -       {0x0000a17c, 0x051e051f},
8542 -       {0x0000a180, 0x06010602},
8543 -       {0x0000a184, 0x061f0600},
8544 -       {0x0000a188, 0x061d061e},
8545 -       {0x0000a18c, 0x07020703},
8546 -       {0x0000a190, 0x07000701},
8547 -       {0x0000a194, 0x00000000},
8548 -       {0x0000a198, 0x00000000},
8549 -       {0x0000a19c, 0x00000000},
8550 -       {0x0000a1a0, 0x00000000},
8551 -       {0x0000a1a4, 0x00000000},
8552 -       {0x0000a1a8, 0x00000000},
8553 -       {0x0000a1ac, 0x00000000},
8554 -       {0x0000a1b0, 0x00000000},
8555 -       {0x0000a1b4, 0x00000000},
8556 -       {0x0000a1b8, 0x00000000},
8557 -       {0x0000a1bc, 0x00000000},
8558 -       {0x0000a1c0, 0x00000000},
8559 -       {0x0000a1c4, 0x00000000},
8560 -       {0x0000a1c8, 0x00000000},
8561 -       {0x0000a1cc, 0x00000000},
8562 -       {0x0000a1d0, 0x00000000},
8563 -       {0x0000a1d4, 0x00000000},
8564 -       {0x0000a1d8, 0x00000000},
8565 -       {0x0000a1dc, 0x00000000},
8566 -       {0x0000a1e0, 0x00000000},
8567 -       {0x0000a1e4, 0x00000000},
8568 -       {0x0000a1e8, 0x00000000},
8569 -       {0x0000a1ec, 0x00000000},
8570 -       {0x0000a1f0, 0x00000396},
8571 -       {0x0000a1f4, 0x00000396},
8572 -       {0x0000a1f8, 0x00000396},
8573 -       {0x0000a1fc, 0x00000196},
8574 -       {0x0000b000, 0x00010000},
8575 -       {0x0000b004, 0x00030002},
8576 -       {0x0000b008, 0x00050004},
8577 -       {0x0000b00c, 0x00810080},
8578 -       {0x0000b010, 0x00830082},
8579 -       {0x0000b014, 0x01810180},
8580 -       {0x0000b018, 0x01830182},
8581 -       {0x0000b01c, 0x01850184},
8582 -       {0x0000b020, 0x02810280},
8583 -       {0x0000b024, 0x02830282},
8584 -       {0x0000b028, 0x02850284},
8585 -       {0x0000b02c, 0x02890288},
8586 -       {0x0000b030, 0x028b028a},
8587 -       {0x0000b034, 0x0388028c},
8588 -       {0x0000b038, 0x038a0389},
8589 -       {0x0000b03c, 0x038c038b},
8590 -       {0x0000b040, 0x0390038d},
8591 -       {0x0000b044, 0x03920391},
8592 -       {0x0000b048, 0x03940393},
8593 -       {0x0000b04c, 0x03960395},
8594 -       {0x0000b050, 0x00000000},
8595 -       {0x0000b054, 0x00000000},
8596 -       {0x0000b058, 0x00000000},
8597 -       {0x0000b05c, 0x00000000},
8598 -       {0x0000b060, 0x00000000},
8599 -       {0x0000b064, 0x00000000},
8600 -       {0x0000b068, 0x00000000},
8601 -       {0x0000b06c, 0x00000000},
8602 -       {0x0000b070, 0x00000000},
8603 -       {0x0000b074, 0x00000000},
8604 -       {0x0000b078, 0x00000000},
8605 -       {0x0000b07c, 0x00000000},
8606 -       {0x0000b080, 0x2a2d2f32},
8607 -       {0x0000b084, 0x21232328},
8608 -       {0x0000b088, 0x19191c1e},
8609 -       {0x0000b08c, 0x12141417},
8610 -       {0x0000b090, 0x07070e0e},
8611 -       {0x0000b094, 0x03030305},
8612 -       {0x0000b098, 0x00000003},
8613 -       {0x0000b09c, 0x00000000},
8614 -       {0x0000b0a0, 0x00000000},
8615 -       {0x0000b0a4, 0x00000000},
8616 -       {0x0000b0a8, 0x00000000},
8617 -       {0x0000b0ac, 0x00000000},
8618 -       {0x0000b0b0, 0x00000000},
8619 -       {0x0000b0b4, 0x00000000},
8620 -       {0x0000b0b8, 0x00000000},
8621 -       {0x0000b0bc, 0x00000000},
8622 -       {0x0000b0c0, 0x003f0020},
8623 -       {0x0000b0c4, 0x00400041},
8624 -       {0x0000b0c8, 0x0140005f},
8625 -       {0x0000b0cc, 0x0160015f},
8626 -       {0x0000b0d0, 0x017e017f},
8627 -       {0x0000b0d4, 0x02410242},
8628 -       {0x0000b0d8, 0x025f0240},
8629 -       {0x0000b0dc, 0x027f0260},
8630 -       {0x0000b0e0, 0x0341027e},
8631 -       {0x0000b0e4, 0x035f0340},
8632 -       {0x0000b0e8, 0x037f0360},
8633 -       {0x0000b0ec, 0x04400441},
8634 -       {0x0000b0f0, 0x0460045f},
8635 -       {0x0000b0f4, 0x0541047f},
8636 -       {0x0000b0f8, 0x055f0540},
8637 -       {0x0000b0fc, 0x057f0560},
8638 -       {0x0000b100, 0x06400641},
8639 -       {0x0000b104, 0x0660065f},
8640 -       {0x0000b108, 0x067e067f},
8641 -       {0x0000b10c, 0x07410742},
8642 -       {0x0000b110, 0x075f0740},
8643 -       {0x0000b114, 0x077f0760},
8644 -       {0x0000b118, 0x07800781},
8645 -       {0x0000b11c, 0x07a0079f},
8646 -       {0x0000b120, 0x07c107bf},
8647 -       {0x0000b124, 0x000007c0},
8648 -       {0x0000b128, 0x00000000},
8649 -       {0x0000b12c, 0x00000000},
8650 -       {0x0000b130, 0x00000000},
8651 -       {0x0000b134, 0x00000000},
8652 -       {0x0000b138, 0x00000000},
8653 -       {0x0000b13c, 0x00000000},
8654 -       {0x0000b140, 0x003f0020},
8655 -       {0x0000b144, 0x00400041},
8656 -       {0x0000b148, 0x0140005f},
8657 -       {0x0000b14c, 0x0160015f},
8658 -       {0x0000b150, 0x017e017f},
8659 -       {0x0000b154, 0x02410242},
8660 -       {0x0000b158, 0x025f0240},
8661 -       {0x0000b15c, 0x027f0260},
8662 -       {0x0000b160, 0x0341027e},
8663 -       {0x0000b164, 0x035f0340},
8664 -       {0x0000b168, 0x037f0360},
8665 -       {0x0000b16c, 0x04400441},
8666 -       {0x0000b170, 0x0460045f},
8667 -       {0x0000b174, 0x0541047f},
8668 -       {0x0000b178, 0x055f0540},
8669 -       {0x0000b17c, 0x057f0560},
8670 -       {0x0000b180, 0x06400641},
8671 -       {0x0000b184, 0x0660065f},
8672 -       {0x0000b188, 0x067e067f},
8673 -       {0x0000b18c, 0x07410742},
8674 -       {0x0000b190, 0x075f0740},
8675 -       {0x0000b194, 0x077f0760},
8676 -       {0x0000b198, 0x07800781},
8677 -       {0x0000b19c, 0x07a0079f},
8678 -       {0x0000b1a0, 0x07c107bf},
8679 -       {0x0000b1a4, 0x000007c0},
8680 -       {0x0000b1a8, 0x00000000},
8681 -       {0x0000b1ac, 0x00000000},
8682 -       {0x0000b1b0, 0x00000000},
8683 -       {0x0000b1b4, 0x00000000},
8684 -       {0x0000b1b8, 0x00000000},
8685 -       {0x0000b1bc, 0x00000000},
8686 -       {0x0000b1c0, 0x00000000},
8687 -       {0x0000b1c4, 0x00000000},
8688 -       {0x0000b1c8, 0x00000000},
8689 -       {0x0000b1cc, 0x00000000},
8690 -       {0x0000b1d0, 0x00000000},
8691 -       {0x0000b1d4, 0x00000000},
8692 -       {0x0000b1d8, 0x00000000},
8693 -       {0x0000b1dc, 0x00000000},
8694 -       {0x0000b1e0, 0x00000000},
8695 -       {0x0000b1e4, 0x00000000},
8696 -       {0x0000b1e8, 0x00000000},
8697 -       {0x0000b1ec, 0x00000000},
8698 -       {0x0000b1f0, 0x00000396},
8699 -       {0x0000b1f4, 0x00000396},
8700 -       {0x0000b1f8, 0x00000396},
8701 -       {0x0000b1fc, 0x00000196},
8702 -};
8703 -
8704 -static const u32 ar9462_2p1_common_mixed_rx_gain[][2] = {
8705 -       /* Addr      allmodes  */
8706 -       {0x0000a000, 0x00010000},
8707 -       {0x0000a004, 0x00030002},
8708 -       {0x0000a008, 0x00050004},
8709 -       {0x0000a00c, 0x00810080},
8710 -       {0x0000a010, 0x00830082},
8711 -       {0x0000a014, 0x01810180},
8712 -       {0x0000a018, 0x01830182},
8713 -       {0x0000a01c, 0x01850184},
8714 -       {0x0000a020, 0x01890188},
8715 -       {0x0000a024, 0x018b018a},
8716 -       {0x0000a028, 0x018d018c},
8717 -       {0x0000a02c, 0x03820190},
8718 -       {0x0000a030, 0x03840383},
8719 -       {0x0000a034, 0x03880385},
8720 -       {0x0000a038, 0x038a0389},
8721 -       {0x0000a03c, 0x038c038b},
8722 -       {0x0000a040, 0x0390038d},
8723 -       {0x0000a044, 0x03920391},
8724 -       {0x0000a048, 0x03940393},
8725 -       {0x0000a04c, 0x03960395},
8726 -       {0x0000a050, 0x00000000},
8727 -       {0x0000a054, 0x00000000},
8728 -       {0x0000a058, 0x00000000},
8729 -       {0x0000a05c, 0x00000000},
8730 -       {0x0000a060, 0x00000000},
8731 -       {0x0000a064, 0x00000000},
8732 -       {0x0000a068, 0x00000000},
8733 -       {0x0000a06c, 0x00000000},
8734 -       {0x0000a070, 0x00000000},
8735 -       {0x0000a074, 0x00000000},
8736 -       {0x0000a078, 0x00000000},
8737 -       {0x0000a07c, 0x00000000},
8738 -       {0x0000a080, 0x29292929},
8739 -       {0x0000a084, 0x29292929},
8740 -       {0x0000a088, 0x29292929},
8741 -       {0x0000a08c, 0x29292929},
8742 -       {0x0000a090, 0x22292929},
8743 -       {0x0000a094, 0x1d1d2222},
8744 -       {0x0000a098, 0x0c111117},
8745 -       {0x0000a09c, 0x00030303},
8746 -       {0x0000a0a0, 0x00000000},
8747 -       {0x0000a0a4, 0x00000000},
8748 -       {0x0000a0a8, 0x00000000},
8749 -       {0x0000a0ac, 0x00000000},
8750 -       {0x0000a0b0, 0x00000000},
8751 -       {0x0000a0b4, 0x00000000},
8752 -       {0x0000a0b8, 0x00000000},
8753 -       {0x0000a0bc, 0x00000000},
8754 -       {0x0000a0c0, 0x001f0000},
8755 -       {0x0000a0c4, 0x01000101},
8756 -       {0x0000a0c8, 0x011e011f},
8757 -       {0x0000a0cc, 0x011c011d},
8758 -       {0x0000a0d0, 0x02030204},
8759 -       {0x0000a0d4, 0x02010202},
8760 -       {0x0000a0d8, 0x021f0200},
8761 -       {0x0000a0dc, 0x0302021e},
8762 -       {0x0000a0e0, 0x03000301},
8763 -       {0x0000a0e4, 0x031e031f},
8764 -       {0x0000a0e8, 0x0402031d},
8765 -       {0x0000a0ec, 0x04000401},
8766 -       {0x0000a0f0, 0x041e041f},
8767 -       {0x0000a0f4, 0x0502041d},
8768 -       {0x0000a0f8, 0x05000501},
8769 -       {0x0000a0fc, 0x051e051f},
8770 -       {0x0000a100, 0x06010602},
8771 -       {0x0000a104, 0x061f0600},
8772 -       {0x0000a108, 0x061d061e},
8773 -       {0x0000a10c, 0x07020703},
8774 -       {0x0000a110, 0x07000701},
8775 -       {0x0000a114, 0x00000000},
8776 -       {0x0000a118, 0x00000000},
8777 -       {0x0000a11c, 0x00000000},
8778 -       {0x0000a120, 0x00000000},
8779 -       {0x0000a124, 0x00000000},
8780 -       {0x0000a128, 0x00000000},
8781 -       {0x0000a12c, 0x00000000},
8782 -       {0x0000a130, 0x00000000},
8783 -       {0x0000a134, 0x00000000},
8784 -       {0x0000a138, 0x00000000},
8785 -       {0x0000a13c, 0x00000000},
8786 -       {0x0000a140, 0x001f0000},
8787 -       {0x0000a144, 0x01000101},
8788 -       {0x0000a148, 0x011e011f},
8789 -       {0x0000a14c, 0x011c011d},
8790 -       {0x0000a150, 0x02030204},
8791 -       {0x0000a154, 0x02010202},
8792 -       {0x0000a158, 0x021f0200},
8793 -       {0x0000a15c, 0x0302021e},
8794 -       {0x0000a160, 0x03000301},
8795 -       {0x0000a164, 0x031e031f},
8796 -       {0x0000a168, 0x0402031d},
8797 -       {0x0000a16c, 0x04000401},
8798 -       {0x0000a170, 0x041e041f},
8799 -       {0x0000a174, 0x0502041d},
8800 -       {0x0000a178, 0x05000501},
8801 -       {0x0000a17c, 0x051e051f},
8802 -       {0x0000a180, 0x06010602},
8803 -       {0x0000a184, 0x061f0600},
8804 -       {0x0000a188, 0x061d061e},
8805 -       {0x0000a18c, 0x07020703},
8806 -       {0x0000a190, 0x07000701},
8807 -       {0x0000a194, 0x00000000},
8808 -       {0x0000a198, 0x00000000},
8809 -       {0x0000a19c, 0x00000000},
8810 -       {0x0000a1a0, 0x00000000},
8811 -       {0x0000a1a4, 0x00000000},
8812 -       {0x0000a1a8, 0x00000000},
8813 -       {0x0000a1ac, 0x00000000},
8814 -       {0x0000a1b0, 0x00000000},
8815 -       {0x0000a1b4, 0x00000000},
8816 -       {0x0000a1b8, 0x00000000},
8817 -       {0x0000a1bc, 0x00000000},
8818 -       {0x0000a1c0, 0x00000000},
8819 -       {0x0000a1c4, 0x00000000},
8820 -       {0x0000a1c8, 0x00000000},
8821 -       {0x0000a1cc, 0x00000000},
8822 -       {0x0000a1d0, 0x00000000},
8823 -       {0x0000a1d4, 0x00000000},
8824 -       {0x0000a1d8, 0x00000000},
8825 -       {0x0000a1dc, 0x00000000},
8826 -       {0x0000a1e0, 0x00000000},
8827 -       {0x0000a1e4, 0x00000000},
8828 -       {0x0000a1e8, 0x00000000},
8829 -       {0x0000a1ec, 0x00000000},
8830 -       {0x0000a1f0, 0x00000396},
8831 -       {0x0000a1f4, 0x00000396},
8832 -       {0x0000a1f8, 0x00000396},
8833 -       {0x0000a1fc, 0x00000196},
8834 -       {0x0000b000, 0x00010000},
8835 -       {0x0000b004, 0x00030002},
8836 -       {0x0000b008, 0x00050004},
8837 -       {0x0000b00c, 0x00810080},
8838 -       {0x0000b010, 0x00830082},
8839 -       {0x0000b014, 0x01810180},
8840 -       {0x0000b018, 0x01830182},
8841 -       {0x0000b01c, 0x01850184},
8842 -       {0x0000b020, 0x02810280},
8843 -       {0x0000b024, 0x02830282},
8844 -       {0x0000b028, 0x02850284},
8845 -       {0x0000b02c, 0x02890288},
8846 -       {0x0000b030, 0x028b028a},
8847 -       {0x0000b034, 0x0388028c},
8848 -       {0x0000b038, 0x038a0389},
8849 -       {0x0000b03c, 0x038c038b},
8850 -       {0x0000b040, 0x0390038d},
8851 -       {0x0000b044, 0x03920391},
8852 -       {0x0000b048, 0x03940393},
8853 -       {0x0000b04c, 0x03960395},
8854 -       {0x0000b050, 0x00000000},
8855 -       {0x0000b054, 0x00000000},
8856 -       {0x0000b058, 0x00000000},
8857 -       {0x0000b05c, 0x00000000},
8858 -       {0x0000b060, 0x00000000},
8859 -       {0x0000b064, 0x00000000},
8860 -       {0x0000b068, 0x00000000},
8861 -       {0x0000b06c, 0x00000000},
8862 -       {0x0000b070, 0x00000000},
8863 -       {0x0000b074, 0x00000000},
8864 -       {0x0000b078, 0x00000000},
8865 -       {0x0000b07c, 0x00000000},
8866 -       {0x0000b080, 0x2a2d2f32},
8867 -       {0x0000b084, 0x21232328},
8868 -       {0x0000b088, 0x19191c1e},
8869 -       {0x0000b08c, 0x12141417},
8870 -       {0x0000b090, 0x07070e0e},
8871 -       {0x0000b094, 0x03030305},
8872 -       {0x0000b098, 0x00000003},
8873 -       {0x0000b09c, 0x00000000},
8874 -       {0x0000b0a0, 0x00000000},
8875 -       {0x0000b0a4, 0x00000000},
8876 -       {0x0000b0a8, 0x00000000},
8877 -       {0x0000b0ac, 0x00000000},
8878 -       {0x0000b0b0, 0x00000000},
8879 -       {0x0000b0b4, 0x00000000},
8880 -       {0x0000b0b8, 0x00000000},
8881 -       {0x0000b0bc, 0x00000000},
8882 -       {0x0000b0c0, 0x003f0020},
8883 -       {0x0000b0c4, 0x00400041},
8884 -       {0x0000b0c8, 0x0140005f},
8885 -       {0x0000b0cc, 0x0160015f},
8886 -       {0x0000b0d0, 0x017e017f},
8887 -       {0x0000b0d4, 0x02410242},
8888 -       {0x0000b0d8, 0x025f0240},
8889 -       {0x0000b0dc, 0x027f0260},
8890 -       {0x0000b0e0, 0x0341027e},
8891 -       {0x0000b0e4, 0x035f0340},
8892 -       {0x0000b0e8, 0x037f0360},
8893 -       {0x0000b0ec, 0x04400441},
8894 -       {0x0000b0f0, 0x0460045f},
8895 -       {0x0000b0f4, 0x0541047f},
8896 -       {0x0000b0f8, 0x055f0540},
8897 -       {0x0000b0fc, 0x057f0560},
8898 -       {0x0000b100, 0x06400641},
8899 -       {0x0000b104, 0x0660065f},
8900 -       {0x0000b108, 0x067e067f},
8901 -       {0x0000b10c, 0x07410742},
8902 -       {0x0000b110, 0x075f0740},
8903 -       {0x0000b114, 0x077f0760},
8904 -       {0x0000b118, 0x07800781},
8905 -       {0x0000b11c, 0x07a0079f},
8906 -       {0x0000b120, 0x07c107bf},
8907 -       {0x0000b124, 0x000007c0},
8908 -       {0x0000b128, 0x00000000},
8909 -       {0x0000b12c, 0x00000000},
8910 -       {0x0000b130, 0x00000000},
8911 -       {0x0000b134, 0x00000000},
8912 -       {0x0000b138, 0x00000000},
8913 -       {0x0000b13c, 0x00000000},
8914 -       {0x0000b140, 0x003f0020},
8915 -       {0x0000b144, 0x00400041},
8916 -       {0x0000b148, 0x0140005f},
8917 -       {0x0000b14c, 0x0160015f},
8918 -       {0x0000b150, 0x017e017f},
8919 -       {0x0000b154, 0x02410242},
8920 -       {0x0000b158, 0x025f0240},
8921 -       {0x0000b15c, 0x027f0260},
8922 -       {0x0000b160, 0x0341027e},
8923 -       {0x0000b164, 0x035f0340},
8924 -       {0x0000b168, 0x037f0360},
8925 -       {0x0000b16c, 0x04400441},
8926 -       {0x0000b170, 0x0460045f},
8927 -       {0x0000b174, 0x0541047f},
8928 -       {0x0000b178, 0x055f0540},
8929 -       {0x0000b17c, 0x057f0560},
8930 -       {0x0000b180, 0x06400641},
8931 -       {0x0000b184, 0x0660065f},
8932 -       {0x0000b188, 0x067e067f},
8933 -       {0x0000b18c, 0x07410742},
8934 -       {0x0000b190, 0x075f0740},
8935 -       {0x0000b194, 0x077f0760},
8936 -       {0x0000b198, 0x07800781},
8937 -       {0x0000b19c, 0x07a0079f},
8938 -       {0x0000b1a0, 0x07c107bf},
8939 -       {0x0000b1a4, 0x000007c0},
8940 -       {0x0000b1a8, 0x00000000},
8941 -       {0x0000b1ac, 0x00000000},
8942 -       {0x0000b1b0, 0x00000000},
8943 -       {0x0000b1b4, 0x00000000},
8944 -       {0x0000b1b8, 0x00000000},
8945 -       {0x0000b1bc, 0x00000000},
8946 -       {0x0000b1c0, 0x00000000},
8947 -       {0x0000b1c4, 0x00000000},
8948 -       {0x0000b1c8, 0x00000000},
8949 -       {0x0000b1cc, 0x00000000},
8950 -       {0x0000b1d0, 0x00000000},
8951 -       {0x0000b1d4, 0x00000000},
8952 -       {0x0000b1d8, 0x00000000},
8953 -       {0x0000b1dc, 0x00000000},
8954 -       {0x0000b1e0, 0x00000000},
8955 -       {0x0000b1e4, 0x00000000},
8956 -       {0x0000b1e8, 0x00000000},
8957 -       {0x0000b1ec, 0x00000000},
8958 -       {0x0000b1f0, 0x00000396},
8959 -       {0x0000b1f4, 0x00000396},
8960 -       {0x0000b1f8, 0x00000396},
8961 -       {0x0000b1fc, 0x00000196},
8962 -};
8963 -
8964 -static const u32 ar9462_2p1_baseband_core_mix_rxgain[][2] = {
8965 -       /* Addr      allmodes  */
8966 -       {0x00009fd0, 0x0a2d6b93},
8967 -};
8968 -
8969 -static const u32 ar9462_2p1_baseband_postamble_mix_rxgain[][5] = {
8970 -       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
8971 -       {0x00009820, 0x206a022e, 0x206a022e, 0x206a01ae, 0x206a01ae},
8972 -       {0x00009824, 0x63c640de, 0x5ac640d0, 0x63c640da, 0x63c640da},
8973 -       {0x00009828, 0x0796be89, 0x0696b081, 0x0916be81, 0x0916be81},
8974 -       {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000d8, 0x6c4000d8},
8975 -       {0x00009e10, 0x92c88d2e, 0x7ec88d2e, 0x7ec86d2e, 0x7ec86d2e},
8976 -       {0x00009e14, 0x37b95d5e, 0x37b9605e, 0x3236605e, 0x32395c5e},
8977 -};
8978 -
8979 -static const u32 ar9462_2p1_baseband_postamble_5g_xlna[][5] = {
8980 -       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
8981 -       {0x00009e3c, 0xcf946220, 0xcf946220, 0xcfd5c782, 0xcfd5c282},
8982 -};
8983 -
8984 -static const u32 ar9462_2p1_common_wo_xlna_rx_gain[][2] = {
8985 -       /* Addr      allmodes  */
8986 -       {0x0000a000, 0x00010000},
8987 -       {0x0000a004, 0x00030002},
8988 -       {0x0000a008, 0x00050004},
8989 -       {0x0000a00c, 0x00810080},
8990 -       {0x0000a010, 0x00830082},
8991 -       {0x0000a014, 0x01810180},
8992 -       {0x0000a018, 0x01830182},
8993 -       {0x0000a01c, 0x01850184},
8994 -       {0x0000a020, 0x01890188},
8995 -       {0x0000a024, 0x018b018a},
8996 -       {0x0000a028, 0x018d018c},
8997 -       {0x0000a02c, 0x03820190},
8998 -       {0x0000a030, 0x03840383},
8999 -       {0x0000a034, 0x03880385},
9000 -       {0x0000a038, 0x038a0389},
9001 -       {0x0000a03c, 0x038c038b},
9002 -       {0x0000a040, 0x0390038d},
9003 -       {0x0000a044, 0x03920391},
9004 -       {0x0000a048, 0x03940393},
9005 -       {0x0000a04c, 0x03960395},
9006 -       {0x0000a050, 0x00000000},
9007 -       {0x0000a054, 0x00000000},
9008 -       {0x0000a058, 0x00000000},
9009 -       {0x0000a05c, 0x00000000},
9010 -       {0x0000a060, 0x00000000},
9011 -       {0x0000a064, 0x00000000},
9012 -       {0x0000a068, 0x00000000},
9013 -       {0x0000a06c, 0x00000000},
9014 -       {0x0000a070, 0x00000000},
9015 -       {0x0000a074, 0x00000000},
9016 -       {0x0000a078, 0x00000000},
9017 -       {0x0000a07c, 0x00000000},
9018 -       {0x0000a080, 0x29292929},
9019 -       {0x0000a084, 0x29292929},
9020 -       {0x0000a088, 0x29292929},
9021 -       {0x0000a08c, 0x29292929},
9022 -       {0x0000a090, 0x22292929},
9023 -       {0x0000a094, 0x1d1d2222},
9024 -       {0x0000a098, 0x0c111117},
9025 -       {0x0000a09c, 0x00030303},
9026 -       {0x0000a0a0, 0x00000000},
9027 -       {0x0000a0a4, 0x00000000},
9028 -       {0x0000a0a8, 0x00000000},
9029 -       {0x0000a0ac, 0x00000000},
9030 -       {0x0000a0b0, 0x00000000},
9031 -       {0x0000a0b4, 0x00000000},
9032 -       {0x0000a0b8, 0x00000000},
9033 -       {0x0000a0bc, 0x00000000},
9034 -       {0x0000a0c0, 0x001f0000},
9035 -       {0x0000a0c4, 0x01000101},
9036 -       {0x0000a0c8, 0x011e011f},
9037 -       {0x0000a0cc, 0x011c011d},
9038 -       {0x0000a0d0, 0x02030204},
9039 -       {0x0000a0d4, 0x02010202},
9040 -       {0x0000a0d8, 0x021f0200},
9041 -       {0x0000a0dc, 0x0302021e},
9042 -       {0x0000a0e0, 0x03000301},
9043 -       {0x0000a0e4, 0x031e031f},
9044 -       {0x0000a0e8, 0x0402031d},
9045 -       {0x0000a0ec, 0x04000401},
9046 -       {0x0000a0f0, 0x041e041f},
9047 -       {0x0000a0f4, 0x0502041d},
9048 -       {0x0000a0f8, 0x05000501},
9049 -       {0x0000a0fc, 0x051e051f},
9050 -       {0x0000a100, 0x06010602},
9051 -       {0x0000a104, 0x061f0600},
9052 -       {0x0000a108, 0x061d061e},
9053 -       {0x0000a10c, 0x07020703},
9054 -       {0x0000a110, 0x07000701},
9055 -       {0x0000a114, 0x00000000},
9056 -       {0x0000a118, 0x00000000},
9057 -       {0x0000a11c, 0x00000000},
9058 -       {0x0000a120, 0x00000000},
9059 -       {0x0000a124, 0x00000000},
9060 -       {0x0000a128, 0x00000000},
9061 -       {0x0000a12c, 0x00000000},
9062 -       {0x0000a130, 0x00000000},
9063 -       {0x0000a134, 0x00000000},
9064 -       {0x0000a138, 0x00000000},
9065 -       {0x0000a13c, 0x00000000},
9066 -       {0x0000a140, 0x001f0000},
9067 -       {0x0000a144, 0x01000101},
9068 -       {0x0000a148, 0x011e011f},
9069 -       {0x0000a14c, 0x011c011d},
9070 -       {0x0000a150, 0x02030204},
9071 -       {0x0000a154, 0x02010202},
9072 -       {0x0000a158, 0x021f0200},
9073 -       {0x0000a15c, 0x0302021e},
9074 -       {0x0000a160, 0x03000301},
9075 -       {0x0000a164, 0x031e031f},
9076 -       {0x0000a168, 0x0402031d},
9077 -       {0x0000a16c, 0x04000401},
9078 -       {0x0000a170, 0x041e041f},
9079 -       {0x0000a174, 0x0502041d},
9080 -       {0x0000a178, 0x05000501},
9081 -       {0x0000a17c, 0x051e051f},
9082 -       {0x0000a180, 0x06010602},
9083 -       {0x0000a184, 0x061f0600},
9084 -       {0x0000a188, 0x061d061e},
9085 -       {0x0000a18c, 0x07020703},
9086 -       {0x0000a190, 0x07000701},
9087 -       {0x0000a194, 0x00000000},
9088 -       {0x0000a198, 0x00000000},
9089 -       {0x0000a19c, 0x00000000},
9090 -       {0x0000a1a0, 0x00000000},
9091 -       {0x0000a1a4, 0x00000000},
9092 -       {0x0000a1a8, 0x00000000},
9093 -       {0x0000a1ac, 0x00000000},
9094 -       {0x0000a1b0, 0x00000000},
9095 -       {0x0000a1b4, 0x00000000},
9096 -       {0x0000a1b8, 0x00000000},
9097 -       {0x0000a1bc, 0x00000000},
9098 -       {0x0000a1c0, 0x00000000},
9099 -       {0x0000a1c4, 0x00000000},
9100 -       {0x0000a1c8, 0x00000000},
9101 -       {0x0000a1cc, 0x00000000},
9102 -       {0x0000a1d0, 0x00000000},
9103 -       {0x0000a1d4, 0x00000000},
9104 -       {0x0000a1d8, 0x00000000},
9105 -       {0x0000a1dc, 0x00000000},
9106 -       {0x0000a1e0, 0x00000000},
9107 -       {0x0000a1e4, 0x00000000},
9108 -       {0x0000a1e8, 0x00000000},
9109 -       {0x0000a1ec, 0x00000000},
9110 -       {0x0000a1f0, 0x00000396},
9111 -       {0x0000a1f4, 0x00000396},
9112 -       {0x0000a1f8, 0x00000396},
9113 -       {0x0000a1fc, 0x00000196},
9114 -       {0x0000b000, 0x00010000},
9115 -       {0x0000b004, 0x00030002},
9116 -       {0x0000b008, 0x00050004},
9117 -       {0x0000b00c, 0x00810080},
9118 -       {0x0000b010, 0x00830082},
9119 -       {0x0000b014, 0x01810180},
9120 -       {0x0000b018, 0x01830182},
9121 -       {0x0000b01c, 0x01850184},
9122 -       {0x0000b020, 0x02810280},
9123 -       {0x0000b024, 0x02830282},
9124 -       {0x0000b028, 0x02850284},
9125 -       {0x0000b02c, 0x02890288},
9126 -       {0x0000b030, 0x028b028a},
9127 -       {0x0000b034, 0x0388028c},
9128 -       {0x0000b038, 0x038a0389},
9129 -       {0x0000b03c, 0x038c038b},
9130 -       {0x0000b040, 0x0390038d},
9131 -       {0x0000b044, 0x03920391},
9132 -       {0x0000b048, 0x03940393},
9133 -       {0x0000b04c, 0x03960395},
9134 -       {0x0000b050, 0x00000000},
9135 -       {0x0000b054, 0x00000000},
9136 -       {0x0000b058, 0x00000000},
9137 -       {0x0000b05c, 0x00000000},
9138 -       {0x0000b060, 0x00000000},
9139 -       {0x0000b064, 0x00000000},
9140 -       {0x0000b068, 0x00000000},
9141 -       {0x0000b06c, 0x00000000},
9142 -       {0x0000b070, 0x00000000},
9143 -       {0x0000b074, 0x00000000},
9144 -       {0x0000b078, 0x00000000},
9145 -       {0x0000b07c, 0x00000000},
9146 -       {0x0000b080, 0x32323232},
9147 -       {0x0000b084, 0x2f2f3232},
9148 -       {0x0000b088, 0x23282a2d},
9149 -       {0x0000b08c, 0x1c1e2123},
9150 -       {0x0000b090, 0x14171919},
9151 -       {0x0000b094, 0x0e0e1214},
9152 -       {0x0000b098, 0x03050707},
9153 -       {0x0000b09c, 0x00030303},
9154 -       {0x0000b0a0, 0x00000000},
9155 -       {0x0000b0a4, 0x00000000},
9156 -       {0x0000b0a8, 0x00000000},
9157 -       {0x0000b0ac, 0x00000000},
9158 -       {0x0000b0b0, 0x00000000},
9159 -       {0x0000b0b4, 0x00000000},
9160 -       {0x0000b0b8, 0x00000000},
9161 -       {0x0000b0bc, 0x00000000},
9162 -       {0x0000b0c0, 0x003f0020},
9163 -       {0x0000b0c4, 0x00400041},
9164 -       {0x0000b0c8, 0x0140005f},
9165 -       {0x0000b0cc, 0x0160015f},
9166 -       {0x0000b0d0, 0x017e017f},
9167 -       {0x0000b0d4, 0x02410242},
9168 -       {0x0000b0d8, 0x025f0240},
9169 -       {0x0000b0dc, 0x027f0260},
9170 -       {0x0000b0e0, 0x0341027e},
9171 -       {0x0000b0e4, 0x035f0340},
9172 -       {0x0000b0e8, 0x037f0360},
9173 -       {0x0000b0ec, 0x04400441},
9174 -       {0x0000b0f0, 0x0460045f},
9175 -       {0x0000b0f4, 0x0541047f},
9176 -       {0x0000b0f8, 0x055f0540},
9177 -       {0x0000b0fc, 0x057f0560},
9178 -       {0x0000b100, 0x06400641},
9179 -       {0x0000b104, 0x0660065f},
9180 -       {0x0000b108, 0x067e067f},
9181 -       {0x0000b10c, 0x07410742},
9182 -       {0x0000b110, 0x075f0740},
9183 -       {0x0000b114, 0x077f0760},
9184 -       {0x0000b118, 0x07800781},
9185 -       {0x0000b11c, 0x07a0079f},
9186 -       {0x0000b120, 0x07c107bf},
9187 -       {0x0000b124, 0x000007c0},
9188 -       {0x0000b128, 0x00000000},
9189 -       {0x0000b12c, 0x00000000},
9190 -       {0x0000b130, 0x00000000},
9191 -       {0x0000b134, 0x00000000},
9192 -       {0x0000b138, 0x00000000},
9193 -       {0x0000b13c, 0x00000000},
9194 -       {0x0000b140, 0x003f0020},
9195 -       {0x0000b144, 0x00400041},
9196 -       {0x0000b148, 0x0140005f},
9197 -       {0x0000b14c, 0x0160015f},
9198 -       {0x0000b150, 0x017e017f},
9199 -       {0x0000b154, 0x02410242},
9200 -       {0x0000b158, 0x025f0240},
9201 -       {0x0000b15c, 0x027f0260},
9202 -       {0x0000b160, 0x0341027e},
9203 -       {0x0000b164, 0x035f0340},
9204 -       {0x0000b168, 0x037f0360},
9205 -       {0x0000b16c, 0x04400441},
9206 -       {0x0000b170, 0x0460045f},
9207 -       {0x0000b174, 0x0541047f},
9208 -       {0x0000b178, 0x055f0540},
9209 -       {0x0000b17c, 0x057f0560},
9210 -       {0x0000b180, 0x06400641},
9211 -       {0x0000b184, 0x0660065f},
9212 -       {0x0000b188, 0x067e067f},
9213 -       {0x0000b18c, 0x07410742},
9214 -       {0x0000b190, 0x075f0740},
9215 -       {0x0000b194, 0x077f0760},
9216 -       {0x0000b198, 0x07800781},
9217 -       {0x0000b19c, 0x07a0079f},
9218 -       {0x0000b1a0, 0x07c107bf},
9219 -       {0x0000b1a4, 0x000007c0},
9220 -       {0x0000b1a8, 0x00000000},
9221 -       {0x0000b1ac, 0x00000000},
9222 -       {0x0000b1b0, 0x00000000},
9223 -       {0x0000b1b4, 0x00000000},
9224 -       {0x0000b1b8, 0x00000000},
9225 -       {0x0000b1bc, 0x00000000},
9226 -       {0x0000b1c0, 0x00000000},
9227 -       {0x0000b1c4, 0x00000000},
9228 -       {0x0000b1c8, 0x00000000},
9229 -       {0x0000b1cc, 0x00000000},
9230 -       {0x0000b1d0, 0x00000000},
9231 -       {0x0000b1d4, 0x00000000},
9232 -       {0x0000b1d8, 0x00000000},
9233 -       {0x0000b1dc, 0x00000000},
9234 -       {0x0000b1e0, 0x00000000},
9235 -       {0x0000b1e4, 0x00000000},
9236 -       {0x0000b1e8, 0x00000000},
9237 -       {0x0000b1ec, 0x00000000},
9238 -       {0x0000b1f0, 0x00000396},
9239 -       {0x0000b1f4, 0x00000396},
9240 -       {0x0000b1f8, 0x00000396},
9241 -       {0x0000b1fc, 0x00000196},
9242 -};
9243 -
9244 -static const u32 ar9462_2p1_common_5g_xlna_only_rx_gain[][2] = {
9245 -       /* Addr      allmodes  */
9246 -       {0x0000a000, 0x00010000},
9247 -       {0x0000a004, 0x00030002},
9248 -       {0x0000a008, 0x00050004},
9249 -       {0x0000a00c, 0x00810080},
9250 -       {0x0000a010, 0x00830082},
9251 -       {0x0000a014, 0x01810180},
9252 -       {0x0000a018, 0x01830182},
9253 -       {0x0000a01c, 0x01850184},
9254 -       {0x0000a020, 0x01890188},
9255 -       {0x0000a024, 0x018b018a},
9256 -       {0x0000a028, 0x018d018c},
9257 -       {0x0000a02c, 0x03820190},
9258 -       {0x0000a030, 0x03840383},
9259 -       {0x0000a034, 0x03880385},
9260 -       {0x0000a038, 0x038a0389},
9261 -       {0x0000a03c, 0x038c038b},
9262 -       {0x0000a040, 0x0390038d},
9263 -       {0x0000a044, 0x03920391},
9264 -       {0x0000a048, 0x03940393},
9265 -       {0x0000a04c, 0x03960395},
9266 -       {0x0000a050, 0x00000000},
9267 -       {0x0000a054, 0x00000000},
9268 -       {0x0000a058, 0x00000000},
9269 -       {0x0000a05c, 0x00000000},
9270 -       {0x0000a060, 0x00000000},
9271 -       {0x0000a064, 0x00000000},
9272 -       {0x0000a068, 0x00000000},
9273 -       {0x0000a06c, 0x00000000},
9274 -       {0x0000a070, 0x00000000},
9275 -       {0x0000a074, 0x00000000},
9276 -       {0x0000a078, 0x00000000},
9277 -       {0x0000a07c, 0x00000000},
9278 -       {0x0000a080, 0x29292929},
9279 -       {0x0000a084, 0x29292929},
9280 -       {0x0000a088, 0x29292929},
9281 -       {0x0000a08c, 0x29292929},
9282 -       {0x0000a090, 0x22292929},
9283 -       {0x0000a094, 0x1d1d2222},
9284 -       {0x0000a098, 0x0c111117},
9285 -       {0x0000a09c, 0x00030303},
9286 -       {0x0000a0a0, 0x00000000},
9287 -       {0x0000a0a4, 0x00000000},
9288 -       {0x0000a0a8, 0x00000000},
9289 -       {0x0000a0ac, 0x00000000},
9290 -       {0x0000a0b0, 0x00000000},
9291 -       {0x0000a0b4, 0x00000000},
9292 -       {0x0000a0b8, 0x00000000},
9293 -       {0x0000a0bc, 0x00000000},
9294 -       {0x0000a0c0, 0x001f0000},
9295 -       {0x0000a0c4, 0x01000101},
9296 -       {0x0000a0c8, 0x011e011f},
9297 -       {0x0000a0cc, 0x011c011d},
9298 -       {0x0000a0d0, 0x02030204},
9299 -       {0x0000a0d4, 0x02010202},
9300 -       {0x0000a0d8, 0x021f0200},
9301 -       {0x0000a0dc, 0x0302021e},
9302 -       {0x0000a0e0, 0x03000301},
9303 -       {0x0000a0e4, 0x031e031f},
9304 -       {0x0000a0e8, 0x0402031d},
9305 -       {0x0000a0ec, 0x04000401},
9306 -       {0x0000a0f0, 0x041e041f},
9307 -       {0x0000a0f4, 0x0502041d},
9308 -       {0x0000a0f8, 0x05000501},
9309 -       {0x0000a0fc, 0x051e051f},
9310 -       {0x0000a100, 0x06010602},
9311 -       {0x0000a104, 0x061f0600},
9312 -       {0x0000a108, 0x061d061e},
9313 -       {0x0000a10c, 0x07020703},
9314 -       {0x0000a110, 0x07000701},
9315 -       {0x0000a114, 0x00000000},
9316 -       {0x0000a118, 0x00000000},
9317 -       {0x0000a11c, 0x00000000},
9318 -       {0x0000a120, 0x00000000},
9319 -       {0x0000a124, 0x00000000},
9320 -       {0x0000a128, 0x00000000},
9321 -       {0x0000a12c, 0x00000000},
9322 -       {0x0000a130, 0x00000000},
9323 -       {0x0000a134, 0x00000000},
9324 -       {0x0000a138, 0x00000000},
9325 -       {0x0000a13c, 0x00000000},
9326 -       {0x0000a140, 0x001f0000},
9327 -       {0x0000a144, 0x01000101},
9328 -       {0x0000a148, 0x011e011f},
9329 -       {0x0000a14c, 0x011c011d},
9330 -       {0x0000a150, 0x02030204},
9331 -       {0x0000a154, 0x02010202},
9332 -       {0x0000a158, 0x021f0200},
9333 -       {0x0000a15c, 0x0302021e},
9334 -       {0x0000a160, 0x03000301},
9335 -       {0x0000a164, 0x031e031f},
9336 -       {0x0000a168, 0x0402031d},
9337 -       {0x0000a16c, 0x04000401},
9338 -       {0x0000a170, 0x041e041f},
9339 -       {0x0000a174, 0x0502041d},
9340 -       {0x0000a178, 0x05000501},
9341 -       {0x0000a17c, 0x051e051f},
9342 -       {0x0000a180, 0x06010602},
9343 -       {0x0000a184, 0x061f0600},
9344 -       {0x0000a188, 0x061d061e},
9345 -       {0x0000a18c, 0x07020703},
9346 -       {0x0000a190, 0x07000701},
9347 -       {0x0000a194, 0x00000000},
9348 -       {0x0000a198, 0x00000000},
9349 -       {0x0000a19c, 0x00000000},
9350 -       {0x0000a1a0, 0x00000000},
9351 -       {0x0000a1a4, 0x00000000},
9352 -       {0x0000a1a8, 0x00000000},
9353 -       {0x0000a1ac, 0x00000000},
9354 -       {0x0000a1b0, 0x00000000},
9355 -       {0x0000a1b4, 0x00000000},
9356 -       {0x0000a1b8, 0x00000000},
9357 -       {0x0000a1bc, 0x00000000},
9358 -       {0x0000a1c0, 0x00000000},
9359 -       {0x0000a1c4, 0x00000000},
9360 -       {0x0000a1c8, 0x00000000},
9361 -       {0x0000a1cc, 0x00000000},
9362 -       {0x0000a1d0, 0x00000000},
9363 -       {0x0000a1d4, 0x00000000},
9364 -       {0x0000a1d8, 0x00000000},
9365 -       {0x0000a1dc, 0x00000000},
9366 -       {0x0000a1e0, 0x00000000},
9367 -       {0x0000a1e4, 0x00000000},
9368 -       {0x0000a1e8, 0x00000000},
9369 -       {0x0000a1ec, 0x00000000},
9370 -       {0x0000a1f0, 0x00000396},
9371 -       {0x0000a1f4, 0x00000396},
9372 -       {0x0000a1f8, 0x00000396},
9373 -       {0x0000a1fc, 0x00000196},
9374 -       {0x0000b000, 0x00010000},
9375 -       {0x0000b004, 0x00030002},
9376 -       {0x0000b008, 0x00050004},
9377 -       {0x0000b00c, 0x00810080},
9378 -       {0x0000b010, 0x00830082},
9379 -       {0x0000b014, 0x01810180},
9380 -       {0x0000b018, 0x01830182},
9381 -       {0x0000b01c, 0x01850184},
9382 -       {0x0000b020, 0x02810280},
9383 -       {0x0000b024, 0x02830282},
9384 -       {0x0000b028, 0x02850284},
9385 -       {0x0000b02c, 0x02890288},
9386 -       {0x0000b030, 0x028b028a},
9387 -       {0x0000b034, 0x0388028c},
9388 -       {0x0000b038, 0x038a0389},
9389 -       {0x0000b03c, 0x038c038b},
9390 -       {0x0000b040, 0x0390038d},
9391 -       {0x0000b044, 0x03920391},
9392 -       {0x0000b048, 0x03940393},
9393 -       {0x0000b04c, 0x03960395},
9394 -       {0x0000b050, 0x00000000},
9395 -       {0x0000b054, 0x00000000},
9396 -       {0x0000b058, 0x00000000},
9397 -       {0x0000b05c, 0x00000000},
9398 -       {0x0000b060, 0x00000000},
9399 -       {0x0000b064, 0x00000000},
9400 -       {0x0000b068, 0x00000000},
9401 -       {0x0000b06c, 0x00000000},
9402 -       {0x0000b070, 0x00000000},
9403 -       {0x0000b074, 0x00000000},
9404 -       {0x0000b078, 0x00000000},
9405 -       {0x0000b07c, 0x00000000},
9406 -       {0x0000b080, 0x2a2d2f32},
9407 -       {0x0000b084, 0x21232328},
9408 -       {0x0000b088, 0x19191c1e},
9409 -       {0x0000b08c, 0x12141417},
9410 -       {0x0000b090, 0x07070e0e},
9411 -       {0x0000b094, 0x03030305},
9412 -       {0x0000b098, 0x00000003},
9413 -       {0x0000b09c, 0x00000000},
9414 -       {0x0000b0a0, 0x00000000},
9415 -       {0x0000b0a4, 0x00000000},
9416 -       {0x0000b0a8, 0x00000000},
9417 -       {0x0000b0ac, 0x00000000},
9418 -       {0x0000b0b0, 0x00000000},
9419 -       {0x0000b0b4, 0x00000000},
9420 -       {0x0000b0b8, 0x00000000},
9421 -       {0x0000b0bc, 0x00000000},
9422 -       {0x0000b0c0, 0x003f0020},
9423 -       {0x0000b0c4, 0x00400041},
9424 -       {0x0000b0c8, 0x0140005f},
9425 -       {0x0000b0cc, 0x0160015f},
9426 -       {0x0000b0d0, 0x017e017f},
9427 -       {0x0000b0d4, 0x02410242},
9428 -       {0x0000b0d8, 0x025f0240},
9429 -       {0x0000b0dc, 0x027f0260},
9430 -       {0x0000b0e0, 0x0341027e},
9431 -       {0x0000b0e4, 0x035f0340},
9432 -       {0x0000b0e8, 0x037f0360},
9433 -       {0x0000b0ec, 0x04400441},
9434 -       {0x0000b0f0, 0x0460045f},
9435 -       {0x0000b0f4, 0x0541047f},
9436 -       {0x0000b0f8, 0x055f0540},
9437 -       {0x0000b0fc, 0x057f0560},
9438 -       {0x0000b100, 0x06400641},
9439 -       {0x0000b104, 0x0660065f},
9440 -       {0x0000b108, 0x067e067f},
9441 -       {0x0000b10c, 0x07410742},
9442 -       {0x0000b110, 0x075f0740},
9443 -       {0x0000b114, 0x077f0760},
9444 -       {0x0000b118, 0x07800781},
9445 -       {0x0000b11c, 0x07a0079f},
9446 -       {0x0000b120, 0x07c107bf},
9447 -       {0x0000b124, 0x000007c0},
9448 -       {0x0000b128, 0x00000000},
9449 -       {0x0000b12c, 0x00000000},
9450 -       {0x0000b130, 0x00000000},
9451 -       {0x0000b134, 0x00000000},
9452 -       {0x0000b138, 0x00000000},
9453 -       {0x0000b13c, 0x00000000},
9454 -       {0x0000b140, 0x003f0020},
9455 -       {0x0000b144, 0x00400041},
9456 -       {0x0000b148, 0x0140005f},
9457 -       {0x0000b14c, 0x0160015f},
9458 -       {0x0000b150, 0x017e017f},
9459 -       {0x0000b154, 0x02410242},
9460 -       {0x0000b158, 0x025f0240},
9461 -       {0x0000b15c, 0x027f0260},
9462 -       {0x0000b160, 0x0341027e},
9463 -       {0x0000b164, 0x035f0340},
9464 -       {0x0000b168, 0x037f0360},
9465 -       {0x0000b16c, 0x04400441},
9466 -       {0x0000b170, 0x0460045f},
9467 -       {0x0000b174, 0x0541047f},
9468 -       {0x0000b178, 0x055f0540},
9469 -       {0x0000b17c, 0x057f0560},
9470 -       {0x0000b180, 0x06400641},
9471 -       {0x0000b184, 0x0660065f},
9472 -       {0x0000b188, 0x067e067f},
9473 -       {0x0000b18c, 0x07410742},
9474 -       {0x0000b190, 0x075f0740},
9475 -       {0x0000b194, 0x077f0760},
9476 -       {0x0000b198, 0x07800781},
9477 -       {0x0000b19c, 0x07a0079f},
9478 -       {0x0000b1a0, 0x07c107bf},
9479 -       {0x0000b1a4, 0x000007c0},
9480 -       {0x0000b1a8, 0x00000000},
9481 -       {0x0000b1ac, 0x00000000},
9482 -       {0x0000b1b0, 0x00000000},
9483 -       {0x0000b1b4, 0x00000000},
9484 -       {0x0000b1b8, 0x00000000},
9485 -       {0x0000b1bc, 0x00000000},
9486 -       {0x0000b1c0, 0x00000000},
9487 -       {0x0000b1c4, 0x00000000},
9488 -       {0x0000b1c8, 0x00000000},
9489 -       {0x0000b1cc, 0x00000000},
9490 -       {0x0000b1d0, 0x00000000},
9491 -       {0x0000b1d4, 0x00000000},
9492 -       {0x0000b1d8, 0x00000000},
9493 -       {0x0000b1dc, 0x00000000},
9494 -       {0x0000b1e0, 0x00000000},
9495 -       {0x0000b1e4, 0x00000000},
9496 -       {0x0000b1e8, 0x00000000},
9497 -       {0x0000b1ec, 0x00000000},
9498 -       {0x0000b1f0, 0x00000396},
9499 -       {0x0000b1f4, 0x00000396},
9500 -       {0x0000b1f8, 0x00000396},
9501 -       {0x0000b1fc, 0x00000196},
9502 -};
9503 -
9504 -static const u32 ar9462_2p1_modes_low_ob_db_tx_gain[][5] = {
9505 -       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
9506 -       {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
9507 -       {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
9508 -       {0x0000a2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
9509 -       {0x0000a2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
9510 -       {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
9511 -       {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
9512 -       {0x0000a458, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9513 -       {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9514 -       {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
9515 -       {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004},
9516 -       {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
9517 -       {0x0000a510, 0x16000220, 0x16000220, 0x0f000202, 0x0f000202},
9518 -       {0x0000a514, 0x1c000223, 0x1c000223, 0x12000400, 0x12000400},
9519 -       {0x0000a518, 0x21020220, 0x21020220, 0x16000402, 0x16000402},
9520 -       {0x0000a51c, 0x27020223, 0x27020223, 0x19000404, 0x19000404},
9521 -       {0x0000a520, 0x2b022220, 0x2b022220, 0x1c000603, 0x1c000603},
9522 -       {0x0000a524, 0x2f022222, 0x2f022222, 0x21000a02, 0x21000a02},
9523 -       {0x0000a528, 0x34022225, 0x34022225, 0x25000a04, 0x25000a04},
9524 -       {0x0000a52c, 0x3a02222a, 0x3a02222a, 0x28000a20, 0x28000a20},
9525 -       {0x0000a530, 0x3e02222c, 0x3e02222c, 0x2c000e20, 0x2c000e20},
9526 -       {0x0000a534, 0x4202242a, 0x4202242a, 0x30000e22, 0x30000e22},
9527 -       {0x0000a538, 0x4702244a, 0x4702244a, 0x34000e24, 0x34000e24},
9528 -       {0x0000a53c, 0x4b02244c, 0x4b02244c, 0x38001640, 0x38001640},
9529 -       {0x0000a540, 0x4e02246c, 0x4e02246c, 0x3c001660, 0x3c001660},
9530 -       {0x0000a544, 0x5302266c, 0x5302266c, 0x3f001861, 0x3f001861},
9531 -       {0x0000a548, 0x5702286c, 0x5702286c, 0x43001a81, 0x43001a81},
9532 -       {0x0000a54c, 0x5c04286b, 0x5c04286b, 0x47001a83, 0x47001a83},
9533 -       {0x0000a550, 0x61042a6c, 0x61042a6c, 0x4a001c84, 0x4a001c84},
9534 -       {0x0000a554, 0x66062a6c, 0x66062a6c, 0x4e001ce3, 0x4e001ce3},
9535 -       {0x0000a558, 0x6b062e6c, 0x6b062e6c, 0x52001ce5, 0x52001ce5},
9536 -       {0x0000a55c, 0x7006308c, 0x7006308c, 0x56001ce9, 0x56001ce9},
9537 -       {0x0000a560, 0x730a308a, 0x730a308a, 0x5a001ceb, 0x5a001ceb},
9538 -       {0x0000a564, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
9539 -       {0x0000a568, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
9540 -       {0x0000a56c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
9541 -       {0x0000a570, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
9542 -       {0x0000a574, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
9543 -       {0x0000a578, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
9544 -       {0x0000a57c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
9545 -       {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9546 -       {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9547 -       {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9548 -       {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9549 -       {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9550 -       {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000},
9551 -       {0x0000a618, 0x01404501, 0x01404501, 0x01404501, 0x01404501},
9552 -       {0x0000a61c, 0x02008802, 0x02008802, 0x02008501, 0x02008501},
9553 -       {0x0000a620, 0x0300cc03, 0x0300cc03, 0x0280ca03, 0x0280ca03},
9554 -       {0x0000a624, 0x0300cc03, 0x0300cc03, 0x03010c04, 0x03010c04},
9555 -       {0x0000a628, 0x0300cc03, 0x0300cc03, 0x04014c04, 0x04014c04},
9556 -       {0x0000a62c, 0x03810c03, 0x03810c03, 0x04015005, 0x04015005},
9557 -       {0x0000a630, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
9558 -       {0x0000a634, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
9559 -       {0x0000a638, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
9560 -       {0x0000a63c, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
9561 -       {0x0000b2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
9562 -       {0x0000b2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
9563 -       {0x0000b2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
9564 -       {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
9565 -       {0x00016044, 0x012482d4, 0x012482d4, 0x012482d4, 0x012482d4},
9566 -       {0x00016048, 0x64992060, 0x64992060, 0x64992060, 0x64992060},
9567 -       {0x00016054, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000},
9568 -       {0x00016444, 0x012482d4, 0x012482d4, 0x012482d4, 0x012482d4},
9569 -       {0x00016448, 0x64992000, 0x64992000, 0x64992000, 0x64992000},
9570 -       {0x00016454, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000},
9571 -};
9572 -
9573 -static const u32 ar9462_2p1_modes_high_ob_db_tx_gain[][5] = {
9574 -       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
9575 -       {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
9576 -       {0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
9577 -       {0x0000a2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584},
9578 -       {0x0000a2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800},
9579 -       {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
9580 -       {0x0000a410, 0x000050da, 0x000050da, 0x000050de, 0x000050de},
9581 -       {0x0000a458, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9582 -       {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000},
9583 -       {0x0000a504, 0x06002223, 0x06002223, 0x04000002, 0x04000002},
9584 -       {0x0000a508, 0x0a022220, 0x0a022220, 0x08000004, 0x08000004},
9585 -       {0x0000a50c, 0x0f022223, 0x0f022223, 0x0b000200, 0x0b000200},
9586 -       {0x0000a510, 0x14022620, 0x14022620, 0x0f000202, 0x0f000202},
9587 -       {0x0000a514, 0x18022622, 0x18022622, 0x11000400, 0x11000400},
9588 -       {0x0000a518, 0x1b022822, 0x1b022822, 0x15000402, 0x15000402},
9589 -       {0x0000a51c, 0x20022842, 0x20022842, 0x19000404, 0x19000404},
9590 -       {0x0000a520, 0x22022c41, 0x22022c41, 0x1b000603, 0x1b000603},
9591 -       {0x0000a524, 0x28023042, 0x28023042, 0x1f000a02, 0x1f000a02},
9592 -       {0x0000a528, 0x2c023044, 0x2c023044, 0x23000a04, 0x23000a04},
9593 -       {0x0000a52c, 0x2f023644, 0x2f023644, 0x26000a20, 0x26000a20},
9594 -       {0x0000a530, 0x34025643, 0x34025643, 0x2a000e20, 0x2a000e20},
9595 -       {0x0000a534, 0x38025a44, 0x38025a44, 0x2e000e22, 0x2e000e22},
9596 -       {0x0000a538, 0x3b025e45, 0x3b025e45, 0x31000e24, 0x31000e24},
9597 -       {0x0000a53c, 0x41025e4a, 0x41025e4a, 0x34001640, 0x34001640},
9598 -       {0x0000a540, 0x48025e6c, 0x48025e6c, 0x38001660, 0x38001660},
9599 -       {0x0000a544, 0x4e025e8e, 0x4e025e8e, 0x3b001861, 0x3b001861},
9600 -       {0x0000a548, 0x55025eb3, 0x55025eb3, 0x3e001a81, 0x3e001a81},
9601 -       {0x0000a54c, 0x58025ef3, 0x58025ef3, 0x42001a83, 0x42001a83},
9602 -       {0x0000a550, 0x5d025ef6, 0x5d025ef6, 0x44001a84, 0x44001a84},
9603 -       {0x0000a554, 0x62025f56, 0x62025f56, 0x48001ce3, 0x48001ce3},
9604 -       {0x0000a558, 0x66027f56, 0x66027f56, 0x4c001ce5, 0x4c001ce5},
9605 -       {0x0000a55c, 0x6a029f56, 0x6a029f56, 0x50001ce9, 0x50001ce9},
9606 -       {0x0000a560, 0x70049f56, 0x70049f56, 0x54001ceb, 0x54001ceb},
9607 -       {0x0000a564, 0x751ffff6, 0x751ffff6, 0x56001eec, 0x56001eec},
9608 -       {0x0000a568, 0x751ffff6, 0x751ffff6, 0x58001ef0, 0x58001ef0},
9609 -       {0x0000a56c, 0x751ffff6, 0x751ffff6, 0x5a001ef4, 0x5a001ef4},
9610 -       {0x0000a570, 0x751ffff6, 0x751ffff6, 0x5c001ff6, 0x5c001ff6},
9611 -       {0x0000a574, 0x751ffff6, 0x751ffff6, 0x5c001ff6, 0x5c001ff6},
9612 -       {0x0000a578, 0x751ffff6, 0x751ffff6, 0x5c001ff6, 0x5c001ff6},
9613 -       {0x0000a57c, 0x751ffff6, 0x751ffff6, 0x5c001ff6, 0x5c001ff6},
9614 -       {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9615 -       {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9616 -       {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9617 -       {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9618 -       {0x0000a610, 0x00804000, 0x00804000, 0x00000000, 0x00000000},
9619 -       {0x0000a614, 0x00804201, 0x00804201, 0x01404000, 0x01404000},
9620 -       {0x0000a618, 0x0280c802, 0x0280c802, 0x01404501, 0x01404501},
9621 -       {0x0000a61c, 0x0280ca03, 0x0280ca03, 0x02008501, 0x02008501},
9622 -       {0x0000a620, 0x04c15104, 0x04c15104, 0x0280ca03, 0x0280ca03},
9623 -       {0x0000a624, 0x04c15305, 0x04c15305, 0x03010c04, 0x03010c04},
9624 -       {0x0000a628, 0x04c15305, 0x04c15305, 0x04014c04, 0x04014c04},
9625 -       {0x0000a62c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
9626 -       {0x0000a630, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
9627 -       {0x0000a634, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
9628 -       {0x0000a638, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
9629 -       {0x0000a63c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
9630 -       {0x0000b2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
9631 -       {0x0000b2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584},
9632 -       {0x0000b2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800},
9633 -       {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
9634 -       {0x00016044, 0x056d82e4, 0x056d82e4, 0x056d82e4, 0x056d82e4},
9635 -       {0x00016048, 0x8db49060, 0x8db49060, 0x8db49060, 0x8db49060},
9636 -       {0x00016054, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000},
9637 -       {0x00016444, 0x056d82e4, 0x056d82e4, 0x056d82e4, 0x056d82e4},
9638 -       {0x00016448, 0x8db49000, 0x8db49000, 0x8db49000, 0x8db49000},
9639 -       {0x00016454, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000},
9640 -};
9641 -
9642 -static const u32 ar9462_2p1_modes_mix_ob_db_tx_gain[][5] = {
9643 -       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
9644 -       {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
9645 -       {0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
9646 -       {0x0000a2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584},
9647 -       {0x0000a2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800},
9648 -       {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
9649 -       {0x0000a410, 0x0000d0da, 0x0000d0da, 0x0000d0de, 0x0000d0de},
9650 -       {0x0000a458, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9651 -       {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000},
9652 -       {0x0000a504, 0x06002223, 0x06002223, 0x04000002, 0x04000002},
9653 -       {0x0000a508, 0x0a022220, 0x0a022220, 0x08000004, 0x08000004},
9654 -       {0x0000a50c, 0x0f022223, 0x0f022223, 0x0b000200, 0x0b000200},
9655 -       {0x0000a510, 0x14022620, 0x14022620, 0x0f000202, 0x0f000202},
9656 -       {0x0000a514, 0x18022622, 0x18022622, 0x12000400, 0x12000400},
9657 -       {0x0000a518, 0x1b022822, 0x1b022822, 0x16000402, 0x16000402},
9658 -       {0x0000a51c, 0x20022842, 0x20022842, 0x19000404, 0x19000404},
9659 -       {0x0000a520, 0x22022c41, 0x22022c41, 0x1c000603, 0x1c000603},
9660 -       {0x0000a524, 0x28023042, 0x28023042, 0x21000a02, 0x21000a02},
9661 -       {0x0000a528, 0x2c023044, 0x2c023044, 0x25000a04, 0x25000a04},
9662 -       {0x0000a52c, 0x2f023644, 0x2f023644, 0x28000a20, 0x28000a20},
9663 -       {0x0000a530, 0x34025643, 0x34025643, 0x2c000e20, 0x2c000e20},
9664 -       {0x0000a534, 0x38025a44, 0x38025a44, 0x30000e22, 0x30000e22},
9665 -       {0x0000a538, 0x3b025e45, 0x3b025e45, 0x34000e24, 0x34000e24},
9666 -       {0x0000a53c, 0x41025e4a, 0x41025e4a, 0x38001640, 0x38001640},
9667 -       {0x0000a540, 0x48025e6c, 0x48025e6c, 0x3c001660, 0x3c001660},
9668 -       {0x0000a544, 0x4e025e8e, 0x4e025e8e, 0x3f001861, 0x3f001861},
9669 -       {0x0000a548, 0x55025eb3, 0x55025eb3, 0x43001a81, 0x43001a81},
9670 -       {0x0000a54c, 0x58025ef3, 0x58025ef3, 0x47001a83, 0x47001a83},
9671 -       {0x0000a550, 0x5d025ef6, 0x5d025ef6, 0x4a001c84, 0x4a001c84},
9672 -       {0x0000a554, 0x62025f56, 0x62025f56, 0x4e001ce3, 0x4e001ce3},
9673 -       {0x0000a558, 0x66027f56, 0x66027f56, 0x52001ce5, 0x52001ce5},
9674 -       {0x0000a55c, 0x6a029f56, 0x6a029f56, 0x56001ce9, 0x56001ce9},
9675 -       {0x0000a560, 0x70049f56, 0x70049f56, 0x5a001ceb, 0x5a001ceb},
9676 -       {0x0000a564, 0x751ffff6, 0x751ffff6, 0x5c001eec, 0x5c001eec},
9677 -       {0x0000a568, 0x751ffff6, 0x751ffff6, 0x5e001ef0, 0x5e001ef0},
9678 -       {0x0000a56c, 0x751ffff6, 0x751ffff6, 0x60001ef4, 0x60001ef4},
9679 -       {0x0000a570, 0x751ffff6, 0x751ffff6, 0x62001ff6, 0x62001ff6},
9680 -       {0x0000a574, 0x751ffff6, 0x751ffff6, 0x62001ff6, 0x62001ff6},
9681 -       {0x0000a578, 0x751ffff6, 0x751ffff6, 0x62001ff6, 0x62001ff6},
9682 -       {0x0000a57c, 0x751ffff6, 0x751ffff6, 0x62001ff6, 0x62001ff6},
9683 -       {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9684 -       {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9685 -       {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9686 -       {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9687 -       {0x0000a610, 0x00804000, 0x00804000, 0x00000000, 0x00000000},
9688 -       {0x0000a614, 0x00804201, 0x00804201, 0x01404000, 0x01404000},
9689 -       {0x0000a618, 0x0280c802, 0x0280c802, 0x01404501, 0x01404501},
9690 -       {0x0000a61c, 0x0280ca03, 0x0280ca03, 0x02008501, 0x02008501},
9691 -       {0x0000a620, 0x04c15104, 0x04c15104, 0x0280ca03, 0x0280ca03},
9692 -       {0x0000a624, 0x04c15305, 0x04c15305, 0x03010c04, 0x03010c04},
9693 -       {0x0000a628, 0x04c15305, 0x04c15305, 0x04014c04, 0x04014c04},
9694 -       {0x0000a62c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
9695 -       {0x0000a630, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
9696 -       {0x0000a634, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
9697 -       {0x0000a638, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
9698 -       {0x0000a63c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
9699 -       {0x0000b2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
9700 -       {0x0000b2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584},
9701 -       {0x0000b2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800},
9702 -       {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
9703 -};
9704 -
9705 -static const u32 ar9462_2p1_modes_fast_clock[][3] = {
9706 -       /* Addr      5G_HT20     5G_HT40   */
9707 -       {0x00001030, 0x00000268, 0x000004d0},
9708 -       {0x00001070, 0x0000018c, 0x00000318},
9709 -       {0x000010b0, 0x00000fd0, 0x00001fa0},
9710 -       {0x00008014, 0x044c044c, 0x08980898},
9711 -       {0x0000801c, 0x148ec02b, 0x148ec057},
9712 -       {0x00008318, 0x000044c0, 0x00008980},
9713 -       {0x00009e00, 0x0372131c, 0x0372131c},
9714 -       {0x0000a230, 0x0000400b, 0x00004016},
9715 -       {0x0000a254, 0x00000898, 0x00001130},
9716 -};
9717 -
9718 -static const u32 ar9462_2p1_baseband_core_txfir_coeff_japan_2484[][2] = {
9719 -       /* Addr      allmodes  */
9720 -       {0x0000a398, 0x00000000},
9721 -       {0x0000a39c, 0x6f7f0301},
9722 -       {0x0000a3a0, 0xca9228ee},
9723 -};
9724 -
9725  #endif /* INITVALS_9462_2P1_H */
9726 --- a/drivers/net/wireless/ath/ath9k/ar9485_initvals.h
9727 +++ b/drivers/net/wireless/ath/ath9k/ar9485_initvals.h
9728 @@ -20,24 +20,11 @@
9729
9730  /* AR9485 1.1 */
9731
9732 -static const u32 ar9485_1_1_mac_postamble[][5] = {
9733 -       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
9734 -       {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
9735 -       {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
9736 -       {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
9737 -       {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
9738 -       {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b},
9739 -       {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
9740 -       {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
9741 -       {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
9742 -};
9743 +#define ar9485_modes_lowest_ob_db_tx_gain_1_1 ar9485Modes_low_ob_db_tx_gain_1_1
9744
9745 -static const u32 ar9485_1_1_pcie_phy_pll_on_clkreq_disable_L1[][2] = {
9746 -       /* Addr      allmodes  */
9747 -       {0x00018c00, 0x18012e5e},
9748 -       {0x00018c04, 0x000801d8},
9749 -       {0x00018c08, 0x0000080c},
9750 -};
9751 +#define ar9485_1_1_mac_postamble ar9331_1p1_mac_postamble
9752 +
9753 +#define ar9485_1_1_baseband_core_txfir_coeff_japan_2484 ar9300_2p2_baseband_core_txfir_coeff_japan_2484
9754
9755  static const u32 ar9485Common_wo_xlna_rx_gain_1_1[][2] = {
9756         /* Addr      allmodes  */
9757 @@ -553,100 +540,6 @@ static const u32 ar9485Modes_low_ob_db_t
9758         {0x00016048, 0x6c924260, 0x6c924260, 0x6c924260, 0x6c924260},
9759  };
9760
9761 -static const u32 ar9485_modes_lowest_ob_db_tx_gain_1_1[][5] = {
9762 -       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
9763 -       {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
9764 -       {0x0000a2d8, 0xf999a83a, 0xf999a83a, 0x7999a83a, 0x7999a83a},
9765 -       {0x0000a2dc, 0x00000000, 0x00000000, 0xfe2d3552, 0xfe2d3552},
9766 -       {0x0000a2e0, 0x00000000, 0x00000000, 0xfe2d3552, 0xfe2d3552},
9767 -       {0x0000a2e4, 0x00000000, 0x00000000, 0xfe2d3552, 0xfe2d3552},
9768 -       {0x0000a2e8, 0x00000000, 0x00000000, 0xfe2d3552, 0xfe2d3552},
9769 -       {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d8, 0x000050d8},
9770 -       {0x0000a458, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9771 -       {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
9772 -       {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
9773 -       {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
9774 -       {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
9775 -       {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
9776 -       {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
9777 -       {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
9778 -       {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
9779 -       {0x0000a520, 0x2f001f04, 0x2f001f04, 0x21000603, 0x21000603},
9780 -       {0x0000a524, 0x35001fc4, 0x35001fc4, 0x25000605, 0x25000605},
9781 -       {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2a000a03, 0x2a000a03},
9782 -       {0x0000a52c, 0x41023e85, 0x41023e85, 0x2c000a04, 0x2c000a04},
9783 -       {0x0000a530, 0x48023ec6, 0x48023ec6, 0x34000e20, 0x34000e20},
9784 -       {0x0000a534, 0x4d023f01, 0x4d023f01, 0x35000e21, 0x35000e21},
9785 -       {0x0000a538, 0x53023f4b, 0x53023f4b, 0x43000e62, 0x43000e62},
9786 -       {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x45000e63, 0x45000e63},
9787 -       {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x49000e65, 0x49000e65},
9788 -       {0x0000a544, 0x6502feca, 0x6502feca, 0x4b000e66, 0x4b000e66},
9789 -       {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x4d001645, 0x4d001645},
9790 -       {0x0000a54c, 0x7203feca, 0x7203feca, 0x51001865, 0x51001865},
9791 -       {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x55001a86, 0x55001a86},
9792 -       {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x57001ce9, 0x57001ce9},
9793 -       {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x5a001ceb, 0x5a001ceb},
9794 -       {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x5e001eeb, 0x5e001eeb},
9795 -       {0x0000a560, 0x900fff0b, 0x900fff0b, 0x5e001eeb, 0x5e001eeb},
9796 -       {0x0000a564, 0x960fffcb, 0x960fffcb, 0x5e001eeb, 0x5e001eeb},
9797 -       {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
9798 -       {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
9799 -       {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
9800 -       {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
9801 -       {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
9802 -       {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
9803 -       {0x0000a580, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9804 -       {0x0000a584, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9805 -       {0x0000a588, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9806 -       {0x0000a58c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9807 -       {0x0000a590, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9808 -       {0x0000a594, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9809 -       {0x0000a598, 0x00000000, 0x00000000, 0x01404501, 0x01404501},
9810 -       {0x0000a59c, 0x00000000, 0x00000000, 0x02808a02, 0x02808a02},
9811 -       {0x0000a5a0, 0x00000000, 0x00000000, 0x02808a02, 0x02808a02},
9812 -       {0x0000a5a4, 0x00000000, 0x00000000, 0x02808803, 0x02808803},
9813 -       {0x0000a5a8, 0x00000000, 0x00000000, 0x04c14b04, 0x04c14b04},
9814 -       {0x0000a5ac, 0x00000000, 0x00000000, 0x04c15305, 0x04c15305},
9815 -       {0x0000a5b0, 0x00000000, 0x00000000, 0x04c15305, 0x04c15305},
9816 -       {0x0000a5b4, 0x00000000, 0x00000000, 0x04c15305, 0x04c15305},
9817 -       {0x0000a5b8, 0x00000000, 0x00000000, 0x04c15305, 0x04c15305},
9818 -       {0x0000a5bc, 0x00000000, 0x00000000, 0x04c15305, 0x04c15305},
9819 -       {0x0000b500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9820 -       {0x0000b504, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9821 -       {0x0000b508, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9822 -       {0x0000b50c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9823 -       {0x0000b510, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9824 -       {0x0000b514, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9825 -       {0x0000b518, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9826 -       {0x0000b51c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9827 -       {0x0000b520, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9828 -       {0x0000b524, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9829 -       {0x0000b528, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9830 -       {0x0000b52c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9831 -       {0x0000b530, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9832 -       {0x0000b534, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9833 -       {0x0000b538, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9834 -       {0x0000b53c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9835 -       {0x0000b540, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9836 -       {0x0000b544, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9837 -       {0x0000b548, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9838 -       {0x0000b54c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9839 -       {0x0000b550, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9840 -       {0x0000b554, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9841 -       {0x0000b558, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9842 -       {0x0000b55c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9843 -       {0x0000b560, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9844 -       {0x0000b564, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9845 -       {0x0000b568, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9846 -       {0x0000b56c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9847 -       {0x0000b570, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9848 -       {0x0000b574, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9849 -       {0x0000b578, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9850 -       {0x0000b57c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9851 -       {0x00016044, 0x05d6b2db, 0x05d6b2db, 0x05d6b2db, 0x05d6b2db},
9852 -       {0x00016048, 0x6c924260, 0x6c924260, 0x6c924260, 0x6c924260},
9853 -};
9854 -
9855  static const u32 ar9485Modes_green_spur_ob_db_tx_gain_1_1[][5] = {
9856         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
9857         {0x000098bc, 0x00000003, 0x00000003, 0x00000003, 0x00000003},
9858 @@ -1101,20 +994,6 @@ static const u32 ar9485_common_rx_gain_1
9859         {0x0000a1fc, 0x00000296},
9860  };
9861
9862 -static const u32 ar9485_1_1_pcie_phy_pll_on_clkreq_enable_L1[][2] = {
9863 -       /* Addr      allmodes  */
9864 -       {0x00018c00, 0x18052e5e},
9865 -       {0x00018c04, 0x000801d8},
9866 -       {0x00018c08, 0x0000080c},
9867 -};
9868 -
9869 -static const u32 ar9485_1_1_pcie_phy_clkreq_enable_L1[][2] = {
9870 -       /* Addr      allmodes  */
9871 -       {0x00018c00, 0x18053e5e},
9872 -       {0x00018c04, 0x000801d8},
9873 -       {0x00018c08, 0x0000080c},
9874 -};
9875 -
9876  static const u32 ar9485_1_1_soc_preamble[][2] = {
9877         /* Addr      allmodes  */
9878         {0x00004014, 0xba280400},
9879 @@ -1173,13 +1052,6 @@ static const u32 ar9485_1_1_baseband_pos
9880         {0x0000be18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
9881  };
9882
9883 -static const u32 ar9485_1_1_pcie_phy_clkreq_disable_L1[][2] = {
9884 -       /* Addr      allmodes  */
9885 -       {0x00018c00, 0x18013e5e},
9886 -       {0x00018c04, 0x000801d8},
9887 -       {0x00018c08, 0x0000080c},
9888 -};
9889 -
9890  static const u32 ar9485_1_1_radio_postamble[][2] = {
9891         /* Addr      allmodes  */
9892         {0x0001609c, 0x0b283f31},
9893 @@ -1351,11 +1223,18 @@ static const u32 ar9485_1_1_mac_core[][2
9894         {0x000083d0, 0x000301ff},
9895  };
9896
9897 -static const u32 ar9485_1_1_baseband_core_txfir_coeff_japan_2484[][2] = {
9898 +static const u32 ar9485_1_1_pcie_phy_clkreq_disable_L1[][2] = {
9899         /* Addr      allmodes  */
9900 -       {0x0000a398, 0x00000000},
9901 -       {0x0000a39c, 0x6f7f0301},
9902 -       {0x0000a3a0, 0xca9228ee},
9903 +       {0x00018c00, 0x18013e5e},
9904 +       {0x00018c04, 0x000801d8},
9905 +       {0x00018c08, 0x0000080c},
9906 +};
9907 +
9908 +static const u32 ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1[][2] = {
9909 +       /* Addr      allmodes  */
9910 +       {0x00018c00, 0x1801265e},
9911 +       {0x00018c04, 0x000801d8},
9912 +       {0x00018c08, 0x0000080c},
9913  };
9914
9915  #endif /* INITVALS_9485_H */
9916 --- a/drivers/net/wireless/ath/ath9k/pci.c
9917 +++ b/drivers/net/wireless/ath/ath9k/pci.c
9918 @@ -195,6 +195,93 @@ static DEFINE_PCI_DEVICE_TABLE(ath_pci_i
9919                          0x3219),
9920           .driver_data = ATH9K_PCI_BT_ANT_DIV },
9921
9922 +       /* AR9485 cards with PLL power-save disabled by default. */
9923 +       { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
9924 +                        0x0032,
9925 +                        PCI_VENDOR_ID_AZWAVE,
9926 +                        0x2C97),
9927 +         .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
9928 +       { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
9929 +                        0x0032,
9930 +                        PCI_VENDOR_ID_AZWAVE,
9931 +                        0x2100),
9932 +         .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
9933 +       { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
9934 +                        0x0032,
9935 +                        0x1C56, /* ASKEY */
9936 +                        0x4001),
9937 +         .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
9938 +       { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
9939 +                        0x0032,
9940 +                        0x11AD, /* LITEON */
9941 +                        0x6627),
9942 +         .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
9943 +       { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
9944 +                        0x0032,
9945 +                        0x11AD, /* LITEON */
9946 +                        0x6628),
9947 +         .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
9948 +       { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
9949 +                        0x0032,
9950 +                        PCI_VENDOR_ID_FOXCONN,
9951 +                        0xE04E),
9952 +         .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
9953 +       { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
9954 +                        0x0032,
9955 +                        PCI_VENDOR_ID_FOXCONN,
9956 +                        0xE04F),
9957 +         .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
9958 +       { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
9959 +                        0x0032,
9960 +                        0x144F, /* ASKEY */
9961 +                        0x7197),
9962 +         .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
9963 +       { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
9964 +                        0x0032,
9965 +                        0x1B9A, /* XAVI */
9966 +                        0x2000),
9967 +         .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
9968 +       { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
9969 +                        0x0032,
9970 +                        0x1B9A, /* XAVI */
9971 +                        0x2001),
9972 +         .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
9973 +       { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
9974 +                        0x0032,
9975 +                        PCI_VENDOR_ID_AZWAVE,
9976 +                        0x1186),
9977 +         .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
9978 +       { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
9979 +                        0x0032,
9980 +                        PCI_VENDOR_ID_AZWAVE,
9981 +                        0x1F86),
9982 +         .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
9983 +       { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
9984 +                        0x0032,
9985 +                        PCI_VENDOR_ID_AZWAVE,
9986 +                        0x1195),
9987 +         .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
9988 +       { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
9989 +                        0x0032,
9990 +                        PCI_VENDOR_ID_AZWAVE,
9991 +                        0x1F95),
9992 +         .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
9993 +       { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
9994 +                        0x0032,
9995 +                        0x1B9A, /* XAVI */
9996 +                        0x1C00),
9997 +         .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
9998 +       { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
9999 +                        0x0032,
10000 +                        0x1B9A, /* XAVI */
10001 +                        0x1C01),
10002 +         .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
10003 +       { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
10004 +                        0x0032,
10005 +                        PCI_VENDOR_ID_ASUSTEK,
10006 +                        0x850D),
10007 +         .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
10008 +
10009         { PCI_VDEVICE(ATHEROS, 0x0032) }, /* PCI-E  AR9485 */
10010         { PCI_VDEVICE(ATHEROS, 0x0033) }, /* PCI-E  AR9580 */
10011
10012 --- a/drivers/net/wireless/ath/ath9k/ar9462_2p0_initvals.h
10013 +++ b/drivers/net/wireless/ath/ath9k/ar9462_2p0_initvals.h
10014 @@ -20,7 +20,15 @@
10015
10016  /* AR9462 2.0 */
10017
10018 -static const u32 ar9462_modes_fast_clock_2p0[][3] = {
10019 +#define ar9462_2p0_mac_postamble ar9331_1p1_mac_postamble
10020 +
10021 +#define ar9462_2p0_common_wo_xlna_rx_gain ar9300Common_wo_xlna_rx_gain_table_2p2
10022 +
10023 +#define ar9462_2p0_common_5g_xlna_only_rxgain ar9462_2p0_common_mixed_rx_gain
10024 +
10025 +#define ar9462_2p0_baseband_core_txfir_coeff_japan_2484 ar9300_2p2_baseband_core_txfir_coeff_japan_2484
10026 +
10027 +static const u32 ar9462_2p0_modes_fast_clock[][3] = {
10028         /* Addr      5G_HT20     5G_HT40   */
10029         {0x00001030, 0x00000268, 0x000004d0},
10030         {0x00001070, 0x0000018c, 0x00000318},
10031 @@ -33,13 +41,6 @@ static const u32 ar9462_modes_fast_clock
10032         {0x0000a254, 0x00000898, 0x00001130},
10033  };
10034
10035 -static const u32 ar9462_pciephy_clkreq_enable_L1_2p0[][2] = {
10036 -       /* Addr      allmodes  */
10037 -       {0x00018c00, 0x18253ede},
10038 -       {0x00018c04, 0x000801d8},
10039 -       {0x00018c08, 0x0003780c},
10040 -};
10041 -
10042  static const u32 ar9462_2p0_baseband_postamble[][5] = {
10043         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
10044         {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a800d},
10045 @@ -99,7 +100,7 @@ static const u32 ar9462_2p0_baseband_pos
10046         {0x0000b284, 0x00000000, 0x00000000, 0x00000550, 0x00000550},
10047  };
10048
10049 -static const u32 ar9462_common_rx_gain_table_2p0[][2] = {
10050 +static const u32 ar9462_2p0_common_rx_gain[][2] = {
10051         /* Addr      allmodes  */
10052         {0x0000a000, 0x00010000},
10053         {0x0000a004, 0x00030002},
10054 @@ -359,20 +360,13 @@ static const u32 ar9462_common_rx_gain_t
10055         {0x0000b1fc, 0x00000196},
10056  };
10057
10058 -static const u32 ar9462_pciephy_clkreq_disable_L1_2p0[][2] = {
10059 +static const u32 ar9462_2p0_pciephy_clkreq_disable_L1[][2] = {
10060         /* Addr      allmodes  */
10061         {0x00018c00, 0x18213ede},
10062         {0x00018c04, 0x000801d8},
10063         {0x00018c08, 0x0003780c},
10064  };
10065
10066 -static const u32 ar9462_pciephy_pll_on_clkreq_disable_L1_2p0[][2] = {
10067 -       /* Addr      allmodes  */
10068 -       {0x00018c00, 0x18212ede},
10069 -       {0x00018c04, 0x000801d8},
10070 -       {0x00018c08, 0x0003780c},
10071 -};
10072 -
10073  static const u32 ar9462_2p0_radio_postamble_sys2ant[][5] = {
10074         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
10075         {0x000160ac, 0xa4646c08, 0xa4646c08, 0x24645808, 0x24645808},
10076 @@ -380,348 +374,81 @@ static const u32 ar9462_2p0_radio_postam
10077         {0x00016540, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
10078  };
10079
10080 -static const u32 ar9462_common_wo_xlna_rx_gain_table_2p0[][2] = {
10081 -       /* Addr      allmodes  */
10082 -       {0x0000a000, 0x00010000},
10083 -       {0x0000a004, 0x00030002},
10084 -       {0x0000a008, 0x00050004},
10085 -       {0x0000a00c, 0x00810080},
10086 -       {0x0000a010, 0x00830082},
10087 -       {0x0000a014, 0x01810180},
10088 -       {0x0000a018, 0x01830182},
10089 -       {0x0000a01c, 0x01850184},
10090 -       {0x0000a020, 0x01890188},
10091 -       {0x0000a024, 0x018b018a},
10092 -       {0x0000a028, 0x018d018c},
10093 -       {0x0000a02c, 0x03820190},
10094 -       {0x0000a030, 0x03840383},
10095 -       {0x0000a034, 0x03880385},
10096 -       {0x0000a038, 0x038a0389},
10097 -       {0x0000a03c, 0x038c038b},
10098 -       {0x0000a040, 0x0390038d},
10099 -       {0x0000a044, 0x03920391},
10100 -       {0x0000a048, 0x03940393},
10101 -       {0x0000a04c, 0x03960395},
10102 -       {0x0000a050, 0x00000000},
10103 -       {0x0000a054, 0x00000000},
10104 -       {0x0000a058, 0x00000000},
10105 -       {0x0000a05c, 0x00000000},
10106 -       {0x0000a060, 0x00000000},
10107 -       {0x0000a064, 0x00000000},
10108 -       {0x0000a068, 0x00000000},
10109 -       {0x0000a06c, 0x00000000},
10110 -       {0x0000a070, 0x00000000},
10111 -       {0x0000a074, 0x00000000},
10112 -       {0x0000a078, 0x00000000},
10113 -       {0x0000a07c, 0x00000000},
10114 -       {0x0000a080, 0x29292929},
10115 -       {0x0000a084, 0x29292929},
10116 -       {0x0000a088, 0x29292929},
10117 -       {0x0000a08c, 0x29292929},
10118 -       {0x0000a090, 0x22292929},
10119 -       {0x0000a094, 0x1d1d2222},
10120 -       {0x0000a098, 0x0c111117},
10121 -       {0x0000a09c, 0x00030303},
10122 -       {0x0000a0a0, 0x00000000},
10123 -       {0x0000a0a4, 0x00000000},
10124 -       {0x0000a0a8, 0x00000000},
10125 -       {0x0000a0ac, 0x00000000},
10126 -       {0x0000a0b0, 0x00000000},
10127 -       {0x0000a0b4, 0x00000000},
10128 -       {0x0000a0b8, 0x00000000},
10129 -       {0x0000a0bc, 0x00000000},
10130 -       {0x0000a0c0, 0x001f0000},
10131 -       {0x0000a0c4, 0x01000101},
10132 -       {0x0000a0c8, 0x011e011f},
10133 -       {0x0000a0cc, 0x011c011d},
10134 -       {0x0000a0d0, 0x02030204},
10135 -       {0x0000a0d4, 0x02010202},
10136 -       {0x0000a0d8, 0x021f0200},
10137 -       {0x0000a0dc, 0x0302021e},
10138 -       {0x0000a0e0, 0x03000301},
10139 -       {0x0000a0e4, 0x031e031f},
10140 -       {0x0000a0e8, 0x0402031d},
10141 -       {0x0000a0ec, 0x04000401},
10142 -       {0x0000a0f0, 0x041e041f},
10143 -       {0x0000a0f4, 0x0502041d},
10144 -       {0x0000a0f8, 0x05000501},
10145 -       {0x0000a0fc, 0x051e051f},
10146 -       {0x0000a100, 0x06010602},
10147 -       {0x0000a104, 0x061f0600},
10148 -       {0x0000a108, 0x061d061e},
10149 -       {0x0000a10c, 0x07020703},
10150 -       {0x0000a110, 0x07000701},
10151 -       {0x0000a114, 0x00000000},
10152 -       {0x0000a118, 0x00000000},
10153 -       {0x0000a11c, 0x00000000},
10154 -       {0x0000a120, 0x00000000},
10155 -       {0x0000a124, 0x00000000},
10156 -       {0x0000a128, 0x00000000},
10157 -       {0x0000a12c, 0x00000000},
10158 -       {0x0000a130, 0x00000000},
10159 -       {0x0000a134, 0x00000000},
10160 -       {0x0000a138, 0x00000000},
10161 -       {0x0000a13c, 0x00000000},
10162 -       {0x0000a140, 0x001f0000},
10163 -       {0x0000a144, 0x01000101},
10164 -       {0x0000a148, 0x011e011f},
10165 -       {0x0000a14c, 0x011c011d},
10166 -       {0x0000a150, 0x02030204},
10167 -       {0x0000a154, 0x02010202},
10168 -       {0x0000a158, 0x021f0200},
10169 -       {0x0000a15c, 0x0302021e},
10170 -       {0x0000a160, 0x03000301},
10171 -       {0x0000a164, 0x031e031f},
10172 -       {0x0000a168, 0x0402031d},
10173 -       {0x0000a16c, 0x04000401},
10174 -       {0x0000a170, 0x041e041f},
10175 -       {0x0000a174, 0x0502041d},
10176 -       {0x0000a178, 0x05000501},
10177 -       {0x0000a17c, 0x051e051f},
10178 -       {0x0000a180, 0x06010602},
10179 -       {0x0000a184, 0x061f0600},
10180 -       {0x0000a188, 0x061d061e},
10181 -       {0x0000a18c, 0x07020703},
10182 -       {0x0000a190, 0x07000701},
10183 -       {0x0000a194, 0x00000000},
10184 -       {0x0000a198, 0x00000000},
10185 -       {0x0000a19c, 0x00000000},
10186 -       {0x0000a1a0, 0x00000000},
10187 -       {0x0000a1a4, 0x00000000},
10188 -       {0x0000a1a8, 0x00000000},
10189 -       {0x0000a1ac, 0x00000000},
10190 -       {0x0000a1b0, 0x00000000},
10191 -       {0x0000a1b4, 0x00000000},
10192 -       {0x0000a1b8, 0x00000000},
10193 -       {0x0000a1bc, 0x00000000},
10194 -       {0x0000a1c0, 0x00000000},
10195 -       {0x0000a1c4, 0x00000000},
10196 -       {0x0000a1c8, 0x00000000},
10197 -       {0x0000a1cc, 0x00000000},
10198 -       {0x0000a1d0, 0x00000000},
10199 -       {0x0000a1d4, 0x00000000},
10200 -       {0x0000a1d8, 0x00000000},
10201 -       {0x0000a1dc, 0x00000000},
10202 -       {0x0000a1e0, 0x00000000},
10203 -       {0x0000a1e4, 0x00000000},
10204 -       {0x0000a1e8, 0x00000000},
10205 -       {0x0000a1ec, 0x00000000},
10206 -       {0x0000a1f0, 0x00000396},
10207 -       {0x0000a1f4, 0x00000396},
10208 -       {0x0000a1f8, 0x00000396},
10209 -       {0x0000a1fc, 0x00000196},
10210 -       {0x0000b000, 0x00010000},
10211 -       {0x0000b004, 0x00030002},
10212 -       {0x0000b008, 0x00050004},
10213 -       {0x0000b00c, 0x00810080},
10214 -       {0x0000b010, 0x00830082},
10215 -       {0x0000b014, 0x01810180},
10216 -       {0x0000b018, 0x01830182},
10217 -       {0x0000b01c, 0x01850184},
10218 -       {0x0000b020, 0x02810280},
10219 -       {0x0000b024, 0x02830282},
10220 -       {0x0000b028, 0x02850284},
10221 -       {0x0000b02c, 0x02890288},
10222 -       {0x0000b030, 0x028b028a},
10223 -       {0x0000b034, 0x0388028c},
10224 -       {0x0000b038, 0x038a0389},
10225 -       {0x0000b03c, 0x038c038b},
10226 -       {0x0000b040, 0x0390038d},
10227 -       {0x0000b044, 0x03920391},
10228 -       {0x0000b048, 0x03940393},
10229 -       {0x0000b04c, 0x03960395},
10230 -       {0x0000b050, 0x00000000},
10231 -       {0x0000b054, 0x00000000},
10232 -       {0x0000b058, 0x00000000},
10233 -       {0x0000b05c, 0x00000000},
10234 -       {0x0000b060, 0x00000000},
10235 -       {0x0000b064, 0x00000000},
10236 -       {0x0000b068, 0x00000000},
10237 -       {0x0000b06c, 0x00000000},
10238 -       {0x0000b070, 0x00000000},
10239 -       {0x0000b074, 0x00000000},
10240 -       {0x0000b078, 0x00000000},
10241 -       {0x0000b07c, 0x00000000},
10242 -       {0x0000b080, 0x32323232},
10243 -       {0x0000b084, 0x2f2f3232},
10244 -       {0x0000b088, 0x23282a2d},
10245 -       {0x0000b08c, 0x1c1e2123},
10246 -       {0x0000b090, 0x14171919},
10247 -       {0x0000b094, 0x0e0e1214},
10248 -       {0x0000b098, 0x03050707},
10249 -       {0x0000b09c, 0x00030303},
10250 -       {0x0000b0a0, 0x00000000},
10251 -       {0x0000b0a4, 0x00000000},
10252 -       {0x0000b0a8, 0x00000000},
10253 -       {0x0000b0ac, 0x00000000},
10254 -       {0x0000b0b0, 0x00000000},
10255 -       {0x0000b0b4, 0x00000000},
10256 -       {0x0000b0b8, 0x00000000},
10257 -       {0x0000b0bc, 0x00000000},
10258 -       {0x0000b0c0, 0x003f0020},
10259 -       {0x0000b0c4, 0x00400041},
10260 -       {0x0000b0c8, 0x0140005f},
10261 -       {0x0000b0cc, 0x0160015f},
10262 -       {0x0000b0d0, 0x017e017f},
10263 -       {0x0000b0d4, 0x02410242},
10264 -       {0x0000b0d8, 0x025f0240},
10265 -       {0x0000b0dc, 0x027f0260},
10266 -       {0x0000b0e0, 0x0341027e},
10267 -       {0x0000b0e4, 0x035f0340},
10268 -       {0x0000b0e8, 0x037f0360},
10269 -       {0x0000b0ec, 0x04400441},
10270 -       {0x0000b0f0, 0x0460045f},
10271 -       {0x0000b0f4, 0x0541047f},
10272 -       {0x0000b0f8, 0x055f0540},
10273 -       {0x0000b0fc, 0x057f0560},
10274 -       {0x0000b100, 0x06400641},
10275 -       {0x0000b104, 0x0660065f},
10276 -       {0x0000b108, 0x067e067f},
10277 -       {0x0000b10c, 0x07410742},
10278 -       {0x0000b110, 0x075f0740},
10279 -       {0x0000b114, 0x077f0760},
10280 -       {0x0000b118, 0x07800781},
10281 -       {0x0000b11c, 0x07a0079f},
10282 -       {0x0000b120, 0x07c107bf},
10283 -       {0x0000b124, 0x000007c0},
10284 -       {0x0000b128, 0x00000000},
10285 -       {0x0000b12c, 0x00000000},
10286 -       {0x0000b130, 0x00000000},
10287 -       {0x0000b134, 0x00000000},
10288 -       {0x0000b138, 0x00000000},
10289 -       {0x0000b13c, 0x00000000},
10290 -       {0x0000b140, 0x003f0020},
10291 -       {0x0000b144, 0x00400041},
10292 -       {0x0000b148, 0x0140005f},
10293 -       {0x0000b14c, 0x0160015f},
10294 -       {0x0000b150, 0x017e017f},
10295 -       {0x0000b154, 0x02410242},
10296 -       {0x0000b158, 0x025f0240},
10297 -       {0x0000b15c, 0x027f0260},
10298 -       {0x0000b160, 0x0341027e},
10299 -       {0x0000b164, 0x035f0340},
10300 -       {0x0000b168, 0x037f0360},
10301 -       {0x0000b16c, 0x04400441},
10302 -       {0x0000b170, 0x0460045f},
10303 -       {0x0000b174, 0x0541047f},
10304 -       {0x0000b178, 0x055f0540},
10305 -       {0x0000b17c, 0x057f0560},
10306 -       {0x0000b180, 0x06400641},
10307 -       {0x0000b184, 0x0660065f},
10308 -       {0x0000b188, 0x067e067f},
10309 -       {0x0000b18c, 0x07410742},
10310 -       {0x0000b190, 0x075f0740},
10311 -       {0x0000b194, 0x077f0760},
10312 -       {0x0000b198, 0x07800781},
10313 -       {0x0000b19c, 0x07a0079f},
10314 -       {0x0000b1a0, 0x07c107bf},
10315 -       {0x0000b1a4, 0x000007c0},
10316 -       {0x0000b1a8, 0x00000000},
10317 -       {0x0000b1ac, 0x00000000},
10318 -       {0x0000b1b0, 0x00000000},
10319 -       {0x0000b1b4, 0x00000000},
10320 -       {0x0000b1b8, 0x00000000},
10321 -       {0x0000b1bc, 0x00000000},
10322 -       {0x0000b1c0, 0x00000000},
10323 -       {0x0000b1c4, 0x00000000},
10324 -       {0x0000b1c8, 0x00000000},
10325 -       {0x0000b1cc, 0x00000000},
10326 -       {0x0000b1d0, 0x00000000},
10327 -       {0x0000b1d4, 0x00000000},
10328 -       {0x0000b1d8, 0x00000000},
10329 -       {0x0000b1dc, 0x00000000},
10330 -       {0x0000b1e0, 0x00000000},
10331 -       {0x0000b1e4, 0x00000000},
10332 -       {0x0000b1e8, 0x00000000},
10333 -       {0x0000b1ec, 0x00000000},
10334 -       {0x0000b1f0, 0x00000396},
10335 -       {0x0000b1f4, 0x00000396},
10336 -       {0x0000b1f8, 0x00000396},
10337 -       {0x0000b1fc, 0x00000196},
10338 -};
10339 -
10340 -static const u32 ar9462_2p0_baseband_core_txfir_coeff_japan_2484[][2] = {
10341 -       /* Addr      allmodes  */
10342 -       {0x0000a398, 0x00000000},
10343 -       {0x0000a39c, 0x6f7f0301},
10344 -       {0x0000a3a0, 0xca9228ee},
10345 -};
10346 -
10347 -static const u32 ar9462_modes_low_ob_db_tx_gain_table_2p0[][5] = {
10348 -       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
10349 -       {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
10350 -       {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
10351 -       {0x0000a2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
10352 -       {0x0000a2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
10353 -       {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
10354 -       {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
10355 -       {0x0000a458, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
10356 -       {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
10357 -       {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
10358 -       {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004},
10359 -       {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
10360 -       {0x0000a510, 0x16000220, 0x16000220, 0x0f000202, 0x0f000202},
10361 -       {0x0000a514, 0x1c000223, 0x1c000223, 0x12000400, 0x12000400},
10362 -       {0x0000a518, 0x21020220, 0x21020220, 0x16000402, 0x16000402},
10363 -       {0x0000a51c, 0x27020223, 0x27020223, 0x19000404, 0x19000404},
10364 -       {0x0000a520, 0x2b022220, 0x2b022220, 0x1c000603, 0x1c000603},
10365 -       {0x0000a524, 0x2f022222, 0x2f022222, 0x21000a02, 0x21000a02},
10366 -       {0x0000a528, 0x34022225, 0x34022225, 0x25000a04, 0x25000a04},
10367 -       {0x0000a52c, 0x3a02222a, 0x3a02222a, 0x28000a20, 0x28000a20},
10368 -       {0x0000a530, 0x3e02222c, 0x3e02222c, 0x2c000e20, 0x2c000e20},
10369 -       {0x0000a534, 0x4202242a, 0x4202242a, 0x30000e22, 0x30000e22},
10370 -       {0x0000a538, 0x4702244a, 0x4702244a, 0x34000e24, 0x34000e24},
10371 -       {0x0000a53c, 0x4b02244c, 0x4b02244c, 0x38001640, 0x38001640},
10372 -       {0x0000a540, 0x4e02246c, 0x4e02246c, 0x3c001660, 0x3c001660},
10373 -       {0x0000a544, 0x5302266c, 0x5302266c, 0x3f001861, 0x3f001861},
10374 -       {0x0000a548, 0x5702286c, 0x5702286c, 0x43001a81, 0x43001a81},
10375 -       {0x0000a54c, 0x5c04286b, 0x5c04286b, 0x47001a83, 0x47001a83},
10376 -       {0x0000a550, 0x61042a6c, 0x61042a6c, 0x4a001c84, 0x4a001c84},
10377 -       {0x0000a554, 0x66062a6c, 0x66062a6c, 0x4e001ce3, 0x4e001ce3},
10378 -       {0x0000a558, 0x6b062e6c, 0x6b062e6c, 0x52001ce5, 0x52001ce5},
10379 -       {0x0000a55c, 0x7006308c, 0x7006308c, 0x56001ce9, 0x56001ce9},
10380 -       {0x0000a560, 0x730a308a, 0x730a308a, 0x5a001ceb, 0x5a001ceb},
10381 -       {0x0000a564, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
10382 -       {0x0000a568, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
10383 -       {0x0000a56c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
10384 -       {0x0000a570, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
10385 -       {0x0000a574, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
10386 -       {0x0000a578, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
10387 -       {0x0000a57c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
10388 -       {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
10389 -       {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
10390 -       {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
10391 -       {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
10392 -       {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
10393 -       {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000},
10394 -       {0x0000a618, 0x01404501, 0x01404501, 0x01404501, 0x01404501},
10395 -       {0x0000a61c, 0x02008802, 0x02008802, 0x02008501, 0x02008501},
10396 -       {0x0000a620, 0x0300cc03, 0x0300cc03, 0x0280ca03, 0x0280ca03},
10397 -       {0x0000a624, 0x0300cc03, 0x0300cc03, 0x03010c04, 0x03010c04},
10398 -       {0x0000a628, 0x0300cc03, 0x0300cc03, 0x04014c04, 0x04014c04},
10399 -       {0x0000a62c, 0x03810c03, 0x03810c03, 0x04015005, 0x04015005},
10400 -       {0x0000a630, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
10401 -       {0x0000a634, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
10402 -       {0x0000a638, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
10403 -       {0x0000a63c, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
10404 -       {0x0000b2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
10405 -       {0x0000b2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
10406 -       {0x0000b2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
10407 -       {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
10408 -       {0x00016044, 0x012482d4, 0x012482d4, 0x012482d4, 0x012482d4},
10409 -       {0x00016048, 0x64992060, 0x64992060, 0x64992060, 0x64992060},
10410 -       {0x00016054, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000},
10411 -       {0x00016444, 0x012482d4, 0x012482d4, 0x012482d4, 0x012482d4},
10412 -       {0x00016448, 0x64992000, 0x64992000, 0x64992000, 0x64992000},
10413 -       {0x00016454, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000},
10414 -};
10415 -
10416 -static const u32 ar9462_2p0_soc_postamble[][5] = {
10417 -       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
10418 -       {0x00007010, 0x00000033, 0x00000033, 0x00000033, 0x00000033},
10419 -};
10420 -
10421 -static const u32 ar9462_2p0_baseband_core[][2] = {
10422 +static const u32 ar9462_2p0_modes_low_ob_db_tx_gain[][5] = {
10423 +       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
10424 +       {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
10425 +       {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
10426 +       {0x0000a2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
10427 +       {0x0000a2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
10428 +       {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
10429 +       {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
10430 +       {0x0000a458, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
10431 +       {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
10432 +       {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
10433 +       {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004},
10434 +       {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
10435 +       {0x0000a510, 0x16000220, 0x16000220, 0x0f000202, 0x0f000202},
10436 +       {0x0000a514, 0x1c000223, 0x1c000223, 0x12000400, 0x12000400},
10437 +       {0x0000a518, 0x21020220, 0x21020220, 0x16000402, 0x16000402},
10438 +       {0x0000a51c, 0x27020223, 0x27020223, 0x19000404, 0x19000404},
10439 +       {0x0000a520, 0x2b022220, 0x2b022220, 0x1c000603, 0x1c000603},
10440 +       {0x0000a524, 0x2f022222, 0x2f022222, 0x21000a02, 0x21000a02},
10441 +       {0x0000a528, 0x34022225, 0x34022225, 0x25000a04, 0x25000a04},
10442 +       {0x0000a52c, 0x3a02222a, 0x3a02222a, 0x28000a20, 0x28000a20},
10443 +       {0x0000a530, 0x3e02222c, 0x3e02222c, 0x2c000e20, 0x2c000e20},
10444 +       {0x0000a534, 0x4202242a, 0x4202242a, 0x30000e22, 0x30000e22},
10445 +       {0x0000a538, 0x4702244a, 0x4702244a, 0x34000e24, 0x34000e24},
10446 +       {0x0000a53c, 0x4b02244c, 0x4b02244c, 0x38001640, 0x38001640},
10447 +       {0x0000a540, 0x4e02246c, 0x4e02246c, 0x3c001660, 0x3c001660},
10448 +       {0x0000a544, 0x5302266c, 0x5302266c, 0x3f001861, 0x3f001861},
10449 +       {0x0000a548, 0x5702286c, 0x5702286c, 0x43001a81, 0x43001a81},
10450 +       {0x0000a54c, 0x5c04286b, 0x5c04286b, 0x47001a83, 0x47001a83},
10451 +       {0x0000a550, 0x61042a6c, 0x61042a6c, 0x4a001c84, 0x4a001c84},
10452 +       {0x0000a554, 0x66062a6c, 0x66062a6c, 0x4e001ce3, 0x4e001ce3},
10453 +       {0x0000a558, 0x6b062e6c, 0x6b062e6c, 0x52001ce5, 0x52001ce5},
10454 +       {0x0000a55c, 0x7006308c, 0x7006308c, 0x56001ce9, 0x56001ce9},
10455 +       {0x0000a560, 0x730a308a, 0x730a308a, 0x5a001ceb, 0x5a001ceb},
10456 +       {0x0000a564, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
10457 +       {0x0000a568, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
10458 +       {0x0000a56c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
10459 +       {0x0000a570, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
10460 +       {0x0000a574, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
10461 +       {0x0000a578, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
10462 +       {0x0000a57c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
10463 +       {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
10464 +       {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
10465 +       {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
10466 +       {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
10467 +       {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
10468 +       {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000},
10469 +       {0x0000a618, 0x01404501, 0x01404501, 0x01404501, 0x01404501},
10470 +       {0x0000a61c, 0x02008802, 0x02008802, 0x02008501, 0x02008501},
10471 +       {0x0000a620, 0x0300cc03, 0x0300cc03, 0x0280ca03, 0x0280ca03},
10472 +       {0x0000a624, 0x0300cc03, 0x0300cc03, 0x03010c04, 0x03010c04},
10473 +       {0x0000a628, 0x0300cc03, 0x0300cc03, 0x04014c04, 0x04014c04},
10474 +       {0x0000a62c, 0x03810c03, 0x03810c03, 0x04015005, 0x04015005},
10475 +       {0x0000a630, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
10476 +       {0x0000a634, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
10477 +       {0x0000a638, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
10478 +       {0x0000a63c, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
10479 +       {0x0000b2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
10480 +       {0x0000b2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
10481 +       {0x0000b2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
10482 +       {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
10483 +       {0x00016044, 0x012482d4, 0x012482d4, 0x012482d4, 0x012482d4},
10484 +       {0x00016048, 0x64992060, 0x64992060, 0x64992060, 0x64992060},
10485 +       {0x00016054, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000},
10486 +       {0x00016444, 0x012482d4, 0x012482d4, 0x012482d4, 0x012482d4},
10487 +       {0x00016448, 0x64992000, 0x64992000, 0x64992000, 0x64992000},
10488 +       {0x00016454, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000},
10489 +};
10490 +
10491 +static const u32 ar9462_2p0_soc_postamble[][5] = {
10492 +       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
10493 +       {0x00007010, 0x00000033, 0x00000033, 0x00000033, 0x00000033},
10494 +};
10495 +
10496 +static const u32 ar9462_2p0_baseband_core[][2] = {
10497         /* Addr      allmodes  */
10498         {0x00009800, 0xafe68e30},
10499         {0x00009804, 0xfd14e000},
10500 @@ -879,7 +606,7 @@ static const u32 ar9462_2p0_radio_postam
10501         {0x0001650c, 0x48000000, 0x40000000, 0x40000000, 0x40000000},
10502  };
10503
10504 -static const u32 ar9462_modes_mix_ob_db_tx_gain_table_2p0[][5] = {
10505 +static const u32 ar9462_2p0_modes_mix_ob_db_tx_gain[][5] = {
10506         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
10507         {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
10508         {0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
10509 @@ -942,7 +669,7 @@ static const u32 ar9462_modes_mix_ob_db_
10510         {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
10511  };
10512
10513 -static const u32 ar9462_modes_high_ob_db_tx_gain_table_2p0[][5] = {
10514 +static const u32 ar9462_2p0_modes_high_ob_db_tx_gain[][5] = {
10515         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
10516         {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
10517         {0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
10518 @@ -1240,19 +967,7 @@ static const u32 ar9462_2p0_mac_core[][2
10519         {0x000083d0, 0x000301ff},
10520  };
10521
10522 -static const u32 ar9462_2p0_mac_postamble[][5] = {
10523 -       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
10524 -       {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
10525 -       {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
10526 -       {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
10527 -       {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
10528 -       {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b},
10529 -       {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
10530 -       {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
10531 -       {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
10532 -};
10533 -
10534 -static const u32 ar9462_common_mixed_rx_gain_table_2p0[][2] = {
10535 +static const u32 ar9462_2p0_common_mixed_rx_gain[][2] = {
10536         /* Addr      allmodes  */
10537         {0x0000a000, 0x00010000},
10538         {0x0000a004, 0x00030002},
10539 @@ -1517,266 +1232,6 @@ static const u32 ar9462_2p0_baseband_pos
10540         {0x00009e3c, 0xcf946220, 0xcf946220, 0xcfd5c782, 0xcfd5c282},
10541  };
10542
10543 -static const u32 ar9462_2p0_5g_xlna_only_rxgain[][2] = {
10544 -       /* Addr      allmodes  */
10545 -       {0x0000a000, 0x00010000},
10546 -       {0x0000a004, 0x00030002},
10547 -       {0x0000a008, 0x00050004},
10548 -       {0x0000a00c, 0x00810080},
10549 -       {0x0000a010, 0x00830082},
10550 -       {0x0000a014, 0x01810180},
10551 -       {0x0000a018, 0x01830182},
10552 -       {0x0000a01c, 0x01850184},
10553 -       {0x0000a020, 0x01890188},
10554 -       {0x0000a024, 0x018b018a},
10555 -       {0x0000a028, 0x018d018c},
10556 -       {0x0000a02c, 0x03820190},
10557 -       {0x0000a030, 0x03840383},
10558 -       {0x0000a034, 0x03880385},
10559 -       {0x0000a038, 0x038a0389},
10560 -       {0x0000a03c, 0x038c038b},
10561 -       {0x0000a040, 0x0390038d},
10562 -       {0x0000a044, 0x03920391},
10563 -       {0x0000a048, 0x03940393},
10564 -       {0x0000a04c, 0x03960395},
10565 -       {0x0000a050, 0x00000000},
10566 -       {0x0000a054, 0x00000000},
10567 -       {0x0000a058, 0x00000000},
10568 -       {0x0000a05c, 0x00000000},
10569 -       {0x0000a060, 0x00000000},
10570 -       {0x0000a064, 0x00000000},
10571 -       {0x0000a068, 0x00000000},
10572 -       {0x0000a06c, 0x00000000},
10573 -       {0x0000a070, 0x00000000},
10574 -       {0x0000a074, 0x00000000},
10575 -       {0x0000a078, 0x00000000},
10576 -       {0x0000a07c, 0x00000000},
10577 -       {0x0000a080, 0x29292929},
10578 -       {0x0000a084, 0x29292929},
10579 -       {0x0000a088, 0x29292929},
10580 -       {0x0000a08c, 0x29292929},
10581 -       {0x0000a090, 0x22292929},
10582 -       {0x0000a094, 0x1d1d2222},
10583 -       {0x0000a098, 0x0c111117},
10584 -       {0x0000a09c, 0x00030303},
10585 -       {0x0000a0a0, 0x00000000},
10586 -       {0x0000a0a4, 0x00000000},
10587 -       {0x0000a0a8, 0x00000000},
10588 -       {0x0000a0ac, 0x00000000},
10589 -       {0x0000a0b0, 0x00000000},
10590 -       {0x0000a0b4, 0x00000000},
10591 -       {0x0000a0b8, 0x00000000},
10592 -       {0x0000a0bc, 0x00000000},
10593 -       {0x0000a0c0, 0x001f0000},
10594 -       {0x0000a0c4, 0x01000101},
10595 -       {0x0000a0c8, 0x011e011f},
10596 -       {0x0000a0cc, 0x011c011d},
10597 -       {0x0000a0d0, 0x02030204},
10598 -       {0x0000a0d4, 0x02010202},
10599 -       {0x0000a0d8, 0x021f0200},
10600 -       {0x0000a0dc, 0x0302021e},
10601 -       {0x0000a0e0, 0x03000301},
10602 -       {0x0000a0e4, 0x031e031f},
10603 -       {0x0000a0e8, 0x0402031d},
10604 -       {0x0000a0ec, 0x04000401},
10605 -       {0x0000a0f0, 0x041e041f},
10606 -       {0x0000a0f4, 0x0502041d},
10607 -       {0x0000a0f8, 0x05000501},
10608 -       {0x0000a0fc, 0x051e051f},
10609 -       {0x0000a100, 0x06010602},
10610 -       {0x0000a104, 0x061f0600},
10611 -       {0x0000a108, 0x061d061e},
10612 -       {0x0000a10c, 0x07020703},
10613 -       {0x0000a110, 0x07000701},
10614 -       {0x0000a114, 0x00000000},
10615 -       {0x0000a118, 0x00000000},
10616 -       {0x0000a11c, 0x00000000},
10617 -       {0x0000a120, 0x00000000},
10618 -       {0x0000a124, 0x00000000},
10619 -       {0x0000a128, 0x00000000},
10620 -       {0x0000a12c, 0x00000000},
10621 -       {0x0000a130, 0x00000000},
10622 -       {0x0000a134, 0x00000000},
10623 -       {0x0000a138, 0x00000000},
10624 -       {0x0000a13c, 0x00000000},
10625 -       {0x0000a140, 0x001f0000},
10626 -       {0x0000a144, 0x01000101},
10627 -       {0x0000a148, 0x011e011f},
10628 -       {0x0000a14c, 0x011c011d},
10629 -       {0x0000a150, 0x02030204},
10630 -       {0x0000a154, 0x02010202},
10631 -       {0x0000a158, 0x021f0200},
10632 -       {0x0000a15c, 0x0302021e},
10633 -       {0x0000a160, 0x03000301},
10634 -       {0x0000a164, 0x031e031f},
10635 -       {0x0000a168, 0x0402031d},
10636 -       {0x0000a16c, 0x04000401},
10637 -       {0x0000a170, 0x041e041f},
10638 -       {0x0000a174, 0x0502041d},
10639 -       {0x0000a178, 0x05000501},
10640 -       {0x0000a17c, 0x051e051f},
10641 -       {0x0000a180, 0x06010602},
10642 -       {0x0000a184, 0x061f0600},
10643 -       {0x0000a188, 0x061d061e},
10644 -       {0x0000a18c, 0x07020703},
10645 -       {0x0000a190, 0x07000701},
10646 -       {0x0000a194, 0x00000000},
10647 -       {0x0000a198, 0x00000000},
10648 -       {0x0000a19c, 0x00000000},
10649 -       {0x0000a1a0, 0x00000000},
10650 -       {0x0000a1a4, 0x00000000},
10651 -       {0x0000a1a8, 0x00000000},
10652 -       {0x0000a1ac, 0x00000000},
10653 -       {0x0000a1b0, 0x00000000},
10654 -       {0x0000a1b4, 0x00000000},
10655 -       {0x0000a1b8, 0x00000000},
10656 -       {0x0000a1bc, 0x00000000},
10657 -       {0x0000a1c0, 0x00000000},
10658 -       {0x0000a1c4, 0x00000000},
10659 -       {0x0000a1c8, 0x00000000},
10660 -       {0x0000a1cc, 0x00000000},
10661 -       {0x0000a1d0, 0x00000000},
10662 -       {0x0000a1d4, 0x00000000},
10663 -       {0x0000a1d8, 0x00000000},
10664 -       {0x0000a1dc, 0x00000000},
10665 -       {0x0000a1e0, 0x00000000},
10666 -       {0x0000a1e4, 0x00000000},
10667 -       {0x0000a1e8, 0x00000000},
10668 -       {0x0000a1ec, 0x00000000},
10669 -       {0x0000a1f0, 0x00000396},
10670 -       {0x0000a1f4, 0x00000396},
10671 -       {0x0000a1f8, 0x00000396},
10672 -       {0x0000a1fc, 0x00000196},
10673 -       {0x0000b000, 0x00010000},
10674 -       {0x0000b004, 0x00030002},
10675 -       {0x0000b008, 0x00050004},
10676 -       {0x0000b00c, 0x00810080},
10677 -       {0x0000b010, 0x00830082},
10678 -       {0x0000b014, 0x01810180},
10679 -       {0x0000b018, 0x01830182},
10680 -       {0x0000b01c, 0x01850184},
10681 -       {0x0000b020, 0x02810280},
10682 -       {0x0000b024, 0x02830282},
10683 -       {0x0000b028, 0x02850284},
10684 -       {0x0000b02c, 0x02890288},
10685 -       {0x0000b030, 0x028b028a},
10686 -       {0x0000b034, 0x0388028c},
10687 -       {0x0000b038, 0x038a0389},
10688 -       {0x0000b03c, 0x038c038b},
10689 -       {0x0000b040, 0x0390038d},
10690 -       {0x0000b044, 0x03920391},
10691 -       {0x0000b048, 0x03940393},
10692 -       {0x0000b04c, 0x03960395},
10693 -       {0x0000b050, 0x00000000},
10694 -       {0x0000b054, 0x00000000},
10695 -       {0x0000b058, 0x00000000},
10696 -       {0x0000b05c, 0x00000000},
10697 -       {0x0000b060, 0x00000000},
10698 -       {0x0000b064, 0x00000000},
10699 -       {0x0000b068, 0x00000000},
10700 -       {0x0000b06c, 0x00000000},
10701 -       {0x0000b070, 0x00000000},
10702 -       {0x0000b074, 0x00000000},
10703 -       {0x0000b078, 0x00000000},
10704 -       {0x0000b07c, 0x00000000},
10705 -       {0x0000b080, 0x2a2d2f32},
10706 -       {0x0000b084, 0x21232328},
10707 -       {0x0000b088, 0x19191c1e},
10708 -       {0x0000b08c, 0x12141417},
10709 -       {0x0000b090, 0x07070e0e},
10710 -       {0x0000b094, 0x03030305},
10711 -       {0x0000b098, 0x00000003},
10712 -       {0x0000b09c, 0x00000000},
10713 -       {0x0000b0a0, 0x00000000},
10714 -       {0x0000b0a4, 0x00000000},
10715 -       {0x0000b0a8, 0x00000000},
10716 -       {0x0000b0ac, 0x00000000},
10717 -       {0x0000b0b0, 0x00000000},
10718 -       {0x0000b0b4, 0x00000000},
10719 -       {0x0000b0b8, 0x00000000},
10720 -       {0x0000b0bc, 0x00000000},
10721 -       {0x0000b0c0, 0x003f0020},
10722 -       {0x0000b0c4, 0x00400041},
10723 -       {0x0000b0c8, 0x0140005f},
10724 -       {0x0000b0cc, 0x0160015f},
10725 -       {0x0000b0d0, 0x017e017f},
10726 -       {0x0000b0d4, 0x02410242},
10727 -       {0x0000b0d8, 0x025f0240},
10728 -       {0x0000b0dc, 0x027f0260},
10729 -       {0x0000b0e0, 0x0341027e},
10730 -       {0x0000b0e4, 0x035f0340},
10731 -       {0x0000b0e8, 0x037f0360},
10732 -       {0x0000b0ec, 0x04400441},
10733 -       {0x0000b0f0, 0x0460045f},
10734 -       {0x0000b0f4, 0x0541047f},
10735 -       {0x0000b0f8, 0x055f0540},
10736 -       {0x0000b0fc, 0x057f0560},
10737 -       {0x0000b100, 0x06400641},
10738 -       {0x0000b104, 0x0660065f},
10739 -       {0x0000b108, 0x067e067f},
10740 -       {0x0000b10c, 0x07410742},
10741 -       {0x0000b110, 0x075f0740},
10742 -       {0x0000b114, 0x077f0760},
10743 -       {0x0000b118, 0x07800781},
10744 -       {0x0000b11c, 0x07a0079f},
10745 -       {0x0000b120, 0x07c107bf},
10746 -       {0x0000b124, 0x000007c0},
10747 -       {0x0000b128, 0x00000000},
10748 -       {0x0000b12c, 0x00000000},
10749 -       {0x0000b130, 0x00000000},
10750 -       {0x0000b134, 0x00000000},
10751 -       {0x0000b138, 0x00000000},
10752 -       {0x0000b13c, 0x00000000},
10753 -       {0x0000b140, 0x003f0020},
10754 -       {0x0000b144, 0x00400041},
10755 -       {0x0000b148, 0x0140005f},
10756 -       {0x0000b14c, 0x0160015f},
10757 -       {0x0000b150, 0x017e017f},
10758 -       {0x0000b154, 0x02410242},
10759 -       {0x0000b158, 0x025f0240},
10760 -       {0x0000b15c, 0x027f0260},
10761 -       {0x0000b160, 0x0341027e},
10762 -       {0x0000b164, 0x035f0340},
10763 -       {0x0000b168, 0x037f0360},
10764 -       {0x0000b16c, 0x04400441},
10765 -       {0x0000b170, 0x0460045f},
10766 -       {0x0000b174, 0x0541047f},
10767 -       {0x0000b178, 0x055f0540},
10768 -       {0x0000b17c, 0x057f0560},
10769 -       {0x0000b180, 0x06400641},
10770 -       {0x0000b184, 0x0660065f},
10771 -       {0x0000b188, 0x067e067f},
10772 -       {0x0000b18c, 0x07410742},
10773 -       {0x0000b190, 0x075f0740},
10774 -       {0x0000b194, 0x077f0760},
10775 -       {0x0000b198, 0x07800781},
10776 -       {0x0000b19c, 0x07a0079f},
10777 -       {0x0000b1a0, 0x07c107bf},
10778 -       {0x0000b1a4, 0x000007c0},
10779 -       {0x0000b1a8, 0x00000000},
10780 -       {0x0000b1ac, 0x00000000},
10781 -       {0x0000b1b0, 0x00000000},
10782 -       {0x0000b1b4, 0x00000000},
10783 -       {0x0000b1b8, 0x00000000},
10784 -       {0x0000b1bc, 0x00000000},
10785 -       {0x0000b1c0, 0x00000000},
10786 -       {0x0000b1c4, 0x00000000},
10787 -       {0x0000b1c8, 0x00000000},
10788 -       {0x0000b1cc, 0x00000000},
10789 -       {0x0000b1d0, 0x00000000},
10790 -       {0x0000b1d4, 0x00000000},
10791 -       {0x0000b1d8, 0x00000000},
10792 -       {0x0000b1dc, 0x00000000},
10793 -       {0x0000b1e0, 0x00000000},
10794 -       {0x0000b1e4, 0x00000000},
10795 -       {0x0000b1e8, 0x00000000},
10796 -       {0x0000b1ec, 0x00000000},
10797 -       {0x0000b1f0, 0x00000396},
10798 -       {0x0000b1f4, 0x00000396},
10799 -       {0x0000b1f8, 0x00000396},
10800 -       {0x0000b1fc, 0x00000196},
10801 -};
10802 -
10803  static const u32 ar9462_2p0_baseband_core_mix_rxgain[][2] = {
10804         /* Addr      allmodes  */
10805         {0x00009fd0, 0x0a2d6b93},
10806 --- a/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
10807 +++ b/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
10808 @@ -303,7 +303,7 @@ static const u32 ar9300_2p2_mac_postambl
10809         {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
10810         {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
10811         {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b},
10812 -       {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
10813 +       {0x00008120, 0x18f04800, 0x18f04800, 0x18f04810, 0x18f04810},
10814         {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
10815         {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
10816  };
10817 @@ -352,7 +352,7 @@ static const u32 ar9300_2p2_baseband_pos
10818         {0x0000a288, 0x00000110, 0x00000110, 0x00000110, 0x00000110},
10819         {0x0000a28c, 0x00022222, 0x00022222, 0x00022222, 0x00022222},
10820         {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
10821 -       {0x0000a2d0, 0x00041981, 0x00041981, 0x00041981, 0x00041982},
10822 +       {0x0000a2d0, 0x00041983, 0x00041983, 0x00041981, 0x00041982},
10823         {0x0000a2d8, 0x7999a83b, 0x7999a83b, 0x7999a83b, 0x7999a83b},
10824         {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
10825         {0x0000a830, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
10826 @@ -378,9 +378,9 @@ static const u32 ar9300_2p2_baseband_cor
10827         {0x00009814, 0x9280c00a},
10828         {0x00009818, 0x00000000},
10829         {0x0000981c, 0x00020028},
10830 -       {0x00009834, 0x6400a290},
10831 +       {0x00009834, 0x6400a190},
10832         {0x00009838, 0x0108ecff},
10833 -       {0x0000983c, 0x0d000600},
10834 +       {0x0000983c, 0x14000600},
10835         {0x00009880, 0x201fff00},
10836         {0x00009884, 0x00001042},
10837         {0x000098a4, 0x00200400},
10838 @@ -401,7 +401,7 @@ static const u32 ar9300_2p2_baseband_cor
10839         {0x00009d04, 0x40206c10},
10840         {0x00009d08, 0x009c4060},
10841         {0x00009d0c, 0x9883800a},
10842 -       {0x00009d10, 0x01834061},
10843 +       {0x00009d10, 0x01884061},
10844         {0x00009d14, 0x00c0040b},
10845         {0x00009d18, 0x00000000},
10846         {0x00009e08, 0x0038230c},
10847 @@ -459,7 +459,7 @@ static const u32 ar9300_2p2_baseband_cor
10848         {0x0000a3e8, 0x20202020},
10849         {0x0000a3ec, 0x20202020},
10850         {0x0000a3f0, 0x00000000},
10851 -       {0x0000a3f4, 0x00000246},
10852 +       {0x0000a3f4, 0x00000000},
10853         {0x0000a3f8, 0x0c9bd380},
10854         {0x0000a3fc, 0x000f0f01},
10855         {0x0000a400, 0x8fa91f01},
10856 @@ -534,107 +534,107 @@ static const u32 ar9300_2p2_baseband_cor
10857
10858  static const u32 ar9300Modes_high_power_tx_gain_table_2p2[][5] = {
10859         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
10860 -       {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
10861 -       {0x0000a2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
10862 -       {0x0000a2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
10863 +       {0x0000a2dc, 0x000cfff0, 0x000cfff0, 0x03aaa352, 0x03aaa352},
10864 +       {0x0000a2e0, 0x000f0000, 0x000f0000, 0x03ccc584, 0x03ccc584},
10865 +       {0x0000a2e4, 0x03f00000, 0x03f00000, 0x03f0f800, 0x03f0f800},
10866         {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
10867 -       {0x0000a410, 0x000050d8, 0x000050d8, 0x000050d9, 0x000050d9},
10868 -       {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000},
10869 -       {0x0000a504, 0x04002222, 0x04002222, 0x04000002, 0x04000002},
10870 -       {0x0000a508, 0x09002421, 0x09002421, 0x08000004, 0x08000004},
10871 -       {0x0000a50c, 0x0d002621, 0x0d002621, 0x0b000200, 0x0b000200},
10872 -       {0x0000a510, 0x13004620, 0x13004620, 0x0f000202, 0x0f000202},
10873 -       {0x0000a514, 0x19004a20, 0x19004a20, 0x11000400, 0x11000400},
10874 -       {0x0000a518, 0x1d004e20, 0x1d004e20, 0x15000402, 0x15000402},
10875 -       {0x0000a51c, 0x21005420, 0x21005420, 0x19000404, 0x19000404},
10876 -       {0x0000a520, 0x26005e20, 0x26005e20, 0x1b000603, 0x1b000603},
10877 -       {0x0000a524, 0x2b005e40, 0x2b005e40, 0x1f000a02, 0x1f000a02},
10878 -       {0x0000a528, 0x2f005e42, 0x2f005e42, 0x23000a04, 0x23000a04},
10879 -       {0x0000a52c, 0x33005e44, 0x33005e44, 0x26000a20, 0x26000a20},
10880 -       {0x0000a530, 0x38005e65, 0x38005e65, 0x2a000e20, 0x2a000e20},
10881 -       {0x0000a534, 0x3c005e69, 0x3c005e69, 0x2e000e22, 0x2e000e22},
10882 -       {0x0000a538, 0x40005e6b, 0x40005e6b, 0x31000e24, 0x31000e24},
10883 -       {0x0000a53c, 0x44005e6d, 0x44005e6d, 0x34001640, 0x34001640},
10884 -       {0x0000a540, 0x49005e72, 0x49005e72, 0x38001660, 0x38001660},
10885 -       {0x0000a544, 0x4e005eb2, 0x4e005eb2, 0x3b001861, 0x3b001861},
10886 -       {0x0000a548, 0x53005f12, 0x53005f12, 0x3e001a81, 0x3e001a81},
10887 -       {0x0000a54c, 0x59025eb2, 0x59025eb2, 0x42001a83, 0x42001a83},
10888 -       {0x0000a550, 0x5e025f12, 0x5e025f12, 0x44001c84, 0x44001c84},
10889 -       {0x0000a554, 0x61027f12, 0x61027f12, 0x48001ce3, 0x48001ce3},
10890 -       {0x0000a558, 0x6702bf12, 0x6702bf12, 0x4c001ce5, 0x4c001ce5},
10891 -       {0x0000a55c, 0x6b02bf14, 0x6b02bf14, 0x50001ce9, 0x50001ce9},
10892 -       {0x0000a560, 0x6f02bf16, 0x6f02bf16, 0x54001ceb, 0x54001ceb},
10893 -       {0x0000a564, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
10894 -       {0x0000a568, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
10895 -       {0x0000a56c, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
10896 -       {0x0000a570, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
10897 -       {0x0000a574, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
10898 -       {0x0000a578, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
10899 -       {0x0000a57c, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
10900 -       {0x0000a580, 0x00802220, 0x00802220, 0x00800000, 0x00800000},
10901 -       {0x0000a584, 0x04802222, 0x04802222, 0x04800002, 0x04800002},
10902 -       {0x0000a588, 0x09802421, 0x09802421, 0x08800004, 0x08800004},
10903 -       {0x0000a58c, 0x0d802621, 0x0d802621, 0x0b800200, 0x0b800200},
10904 -       {0x0000a590, 0x13804620, 0x13804620, 0x0f800202, 0x0f800202},
10905 -       {0x0000a594, 0x19804a20, 0x19804a20, 0x11800400, 0x11800400},
10906 -       {0x0000a598, 0x1d804e20, 0x1d804e20, 0x15800402, 0x15800402},
10907 -       {0x0000a59c, 0x21805420, 0x21805420, 0x19800404, 0x19800404},
10908 -       {0x0000a5a0, 0x26805e20, 0x26805e20, 0x1b800603, 0x1b800603},
10909 -       {0x0000a5a4, 0x2b805e40, 0x2b805e40, 0x1f800a02, 0x1f800a02},
10910 -       {0x0000a5a8, 0x2f805e42, 0x2f805e42, 0x23800a04, 0x23800a04},
10911 -       {0x0000a5ac, 0x33805e44, 0x33805e44, 0x26800a20, 0x26800a20},
10912 -       {0x0000a5b0, 0x38805e65, 0x38805e65, 0x2a800e20, 0x2a800e20},
10913 -       {0x0000a5b4, 0x3c805e69, 0x3c805e69, 0x2e800e22, 0x2e800e22},
10914 -       {0x0000a5b8, 0x40805e6b, 0x40805e6b, 0x31800e24, 0x31800e24},
10915 -       {0x0000a5bc, 0x44805e6d, 0x44805e6d, 0x34801640, 0x34801640},
10916 -       {0x0000a5c0, 0x49805e72, 0x49805e72, 0x38801660, 0x38801660},
10917 -       {0x0000a5c4, 0x4e805eb2, 0x4e805eb2, 0x3b801861, 0x3b801861},
10918 -       {0x0000a5c8, 0x53805f12, 0x53805f12, 0x3e801a81, 0x3e801a81},
10919 -       {0x0000a5cc, 0x59825eb2, 0x59825eb2, 0x42801a83, 0x42801a83},
10920 -       {0x0000a5d0, 0x5e825f12, 0x5e825f12, 0x44801c84, 0x44801c84},
10921 -       {0x0000a5d4, 0x61827f12, 0x61827f12, 0x48801ce3, 0x48801ce3},
10922 -       {0x0000a5d8, 0x6782bf12, 0x6782bf12, 0x4c801ce5, 0x4c801ce5},
10923 -       {0x0000a5dc, 0x6b82bf14, 0x6b82bf14, 0x50801ce9, 0x50801ce9},
10924 -       {0x0000a5e0, 0x6f82bf16, 0x6f82bf16, 0x54801ceb, 0x54801ceb},
10925 -       {0x0000a5e4, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
10926 -       {0x0000a5e8, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
10927 -       {0x0000a5ec, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
10928 -       {0x0000a5f0, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
10929 -       {0x0000a5f4, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
10930 -       {0x0000a5f8, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
10931 -       {0x0000a5fc, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
10932 +       {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
10933 +       {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
10934 +       {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
10935 +       {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004},
10936 +       {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
10937 +       {0x0000a510, 0x15000028, 0x15000028, 0x0f000202, 0x0f000202},
10938 +       {0x0000a514, 0x1b00002b, 0x1b00002b, 0x12000400, 0x12000400},
10939 +       {0x0000a518, 0x1f020028, 0x1f020028, 0x16000402, 0x16000402},
10940 +       {0x0000a51c, 0x2502002b, 0x2502002b, 0x19000404, 0x19000404},
10941 +       {0x0000a520, 0x2a04002a, 0x2a04002a, 0x1c000603, 0x1c000603},
10942 +       {0x0000a524, 0x2e06002a, 0x2e06002a, 0x21000a02, 0x21000a02},
10943 +       {0x0000a528, 0x3302202d, 0x3302202d, 0x25000a04, 0x25000a04},
10944 +       {0x0000a52c, 0x3804202c, 0x3804202c, 0x28000a20, 0x28000a20},
10945 +       {0x0000a530, 0x3c06202c, 0x3c06202c, 0x2c000e20, 0x2c000e20},
10946 +       {0x0000a534, 0x4108202d, 0x4108202d, 0x30000e22, 0x30000e22},
10947 +       {0x0000a538, 0x4506402d, 0x4506402d, 0x34000e24, 0x34000e24},
10948 +       {0x0000a53c, 0x4906222d, 0x4906222d, 0x38001640, 0x38001640},
10949 +       {0x0000a540, 0x4d062231, 0x4d062231, 0x3c001660, 0x3c001660},
10950 +       {0x0000a544, 0x50082231, 0x50082231, 0x3f001861, 0x3f001861},
10951 +       {0x0000a548, 0x5608422e, 0x5608422e, 0x43001a81, 0x43001a81},
10952 +       {0x0000a54c, 0x5e08442e, 0x5e08442e, 0x47001a83, 0x47001a83},
10953 +       {0x0000a550, 0x620a4431, 0x620a4431, 0x4a001c84, 0x4a001c84},
10954 +       {0x0000a554, 0x640a4432, 0x640a4432, 0x4e001ce3, 0x4e001ce3},
10955 +       {0x0000a558, 0x680a4434, 0x680a4434, 0x52001ce5, 0x52001ce5},
10956 +       {0x0000a55c, 0x6c0a6434, 0x6c0a6434, 0x56001ce9, 0x56001ce9},
10957 +       {0x0000a560, 0x6f0a6633, 0x6f0a6633, 0x5a001ceb, 0x5a001ceb},
10958 +       {0x0000a564, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
10959 +       {0x0000a568, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
10960 +       {0x0000a56c, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
10961 +       {0x0000a570, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
10962 +       {0x0000a574, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
10963 +       {0x0000a578, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
10964 +       {0x0000a57c, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
10965 +       {0x0000a580, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
10966 +       {0x0000a584, 0x06800003, 0x06800003, 0x04800002, 0x04800002},
10967 +       {0x0000a588, 0x0a800020, 0x0a800020, 0x08800004, 0x08800004},
10968 +       {0x0000a58c, 0x10800023, 0x10800023, 0x0b800200, 0x0b800200},
10969 +       {0x0000a590, 0x15800028, 0x15800028, 0x0f800202, 0x0f800202},
10970 +       {0x0000a594, 0x1b80002b, 0x1b80002b, 0x12800400, 0x12800400},
10971 +       {0x0000a598, 0x1f820028, 0x1f820028, 0x16800402, 0x16800402},
10972 +       {0x0000a59c, 0x2582002b, 0x2582002b, 0x19800404, 0x19800404},
10973 +       {0x0000a5a0, 0x2a84002a, 0x2a84002a, 0x1c800603, 0x1c800603},
10974 +       {0x0000a5a4, 0x2e86002a, 0x2e86002a, 0x21800a02, 0x21800a02},
10975 +       {0x0000a5a8, 0x3382202d, 0x3382202d, 0x25800a04, 0x25800a04},
10976 +       {0x0000a5ac, 0x3884202c, 0x3884202c, 0x28800a20, 0x28800a20},
10977 +       {0x0000a5b0, 0x3c86202c, 0x3c86202c, 0x2c800e20, 0x2c800e20},
10978 +       {0x0000a5b4, 0x4188202d, 0x4188202d, 0x30800e22, 0x30800e22},
10979 +       {0x0000a5b8, 0x4586402d, 0x4586402d, 0x34800e24, 0x34800e24},
10980 +       {0x0000a5bc, 0x4986222d, 0x4986222d, 0x38801640, 0x38801640},
10981 +       {0x0000a5c0, 0x4d862231, 0x4d862231, 0x3c801660, 0x3c801660},
10982 +       {0x0000a5c4, 0x50882231, 0x50882231, 0x3f801861, 0x3f801861},
10983 +       {0x0000a5c8, 0x5688422e, 0x5688422e, 0x43801a81, 0x43801a81},
10984 +       {0x0000a5cc, 0x5e88442e, 0x5e88442e, 0x47801a83, 0x47801a83},
10985 +       {0x0000a5d0, 0x628a4431, 0x628a4431, 0x4a801c84, 0x4a801c84},
10986 +       {0x0000a5d4, 0x648a4432, 0x648a4432, 0x4e801ce3, 0x4e801ce3},
10987 +       {0x0000a5d8, 0x688a4434, 0x688a4434, 0x52801ce5, 0x52801ce5},
10988 +       {0x0000a5dc, 0x6c8a6434, 0x6c8a6434, 0x56801ce9, 0x56801ce9},
10989 +       {0x0000a5e0, 0x6f8a6633, 0x6f8a6633, 0x5a801ceb, 0x5a801ceb},
10990 +       {0x0000a5e4, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
10991 +       {0x0000a5e8, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
10992 +       {0x0000a5ec, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
10993 +       {0x0000a5f0, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
10994 +       {0x0000a5f4, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
10995 +       {0x0000a5f8, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
10996 +       {0x0000a5fc, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
10997         {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
10998         {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
10999 -       {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
11000 -       {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
11001 -       {0x0000a610, 0x00804000, 0x00804000, 0x00000000, 0x00000000},
11002 -       {0x0000a614, 0x00804201, 0x00804201, 0x01404000, 0x01404000},
11003 -       {0x0000a618, 0x0280c802, 0x0280c802, 0x01404501, 0x01404501},
11004 -       {0x0000a61c, 0x0280ca03, 0x0280ca03, 0x02008501, 0x02008501},
11005 -       {0x0000a620, 0x04c15104, 0x04c15104, 0x0280ca03, 0x0280ca03},
11006 -       {0x0000a624, 0x04c15305, 0x04c15305, 0x03010c04, 0x03010c04},
11007 -       {0x0000a628, 0x04c15305, 0x04c15305, 0x04014c04, 0x04014c04},
11008 -       {0x0000a62c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
11009 -       {0x0000a630, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
11010 -       {0x0000a634, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
11011 -       {0x0000a638, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
11012 -       {0x0000a63c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
11013 -       {0x0000b2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
11014 -       {0x0000b2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
11015 -       {0x0000b2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
11016 +       {0x0000a608, 0x01804601, 0x01804601, 0x00000000, 0x00000000},
11017 +       {0x0000a60c, 0x01804601, 0x01804601, 0x00000000, 0x00000000},
11018 +       {0x0000a610, 0x01804601, 0x01804601, 0x00000000, 0x00000000},
11019 +       {0x0000a614, 0x01804601, 0x01804601, 0x01404000, 0x01404000},
11020 +       {0x0000a618, 0x01804601, 0x01804601, 0x01404501, 0x01404501},
11021 +       {0x0000a61c, 0x01804601, 0x01804601, 0x02008501, 0x02008501},
11022 +       {0x0000a620, 0x03408d02, 0x03408d02, 0x0280ca03, 0x0280ca03},
11023 +       {0x0000a624, 0x0300cc03, 0x0300cc03, 0x03010c04, 0x03010c04},
11024 +       {0x0000a628, 0x03410d04, 0x03410d04, 0x04014c04, 0x04014c04},
11025 +       {0x0000a62c, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
11026 +       {0x0000a630, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
11027 +       {0x0000a634, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
11028 +       {0x0000a638, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
11029 +       {0x0000a63c, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
11030 +       {0x0000b2dc, 0x000cfff0, 0x000cfff0, 0x03aaa352, 0x03aaa352},
11031 +       {0x0000b2e0, 0x000f0000, 0x000f0000, 0x03ccc584, 0x03ccc584},
11032 +       {0x0000b2e4, 0x03f00000, 0x03f00000, 0x03f0f800, 0x03f0f800},
11033         {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
11034 -       {0x0000c2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
11035 -       {0x0000c2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
11036 -       {0x0000c2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
11037 +       {0x0000c2dc, 0x000cfff0, 0x000cfff0, 0x03aaa352, 0x03aaa352},
11038 +       {0x0000c2e0, 0x000f0000, 0x000f0000, 0x03ccc584, 0x03ccc584},
11039 +       {0x0000c2e4, 0x03f00000, 0x03f00000, 0x03f0f800, 0x03f0f800},
11040         {0x0000c2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
11041         {0x00016044, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
11042 -       {0x00016048, 0x66480001, 0x66480001, 0x66480001, 0x66480001},
11043 +       {0x00016048, 0x61200001, 0x61200001, 0x66480001, 0x66480001},
11044         {0x00016068, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
11045         {0x00016444, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
11046 -       {0x00016448, 0x66480001, 0x66480001, 0x66480001, 0x66480001},
11047 +       {0x00016448, 0x61200001, 0x61200001, 0x66480001, 0x66480001},
11048         {0x00016468, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
11049         {0x00016844, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
11050 -       {0x00016848, 0x66480001, 0x66480001, 0x66480001, 0x66480001},
11051 +       {0x00016848, 0x61200001, 0x61200001, 0x66480001, 0x66480001},
11052         {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
11053  };
11054
11055 @@ -644,7 +644,7 @@ static const u32 ar9300Modes_high_ob_db_
11056         {0x0000a2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584},
11057         {0x0000a2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800},
11058         {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
11059 -       {0x0000a410, 0x000050d8, 0x000050d8, 0x000050d9, 0x000050d9},
11060 +       {0x0000a410, 0x000050d4, 0x000050d4, 0x000050d9, 0x000050d9},
11061         {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000},
11062         {0x0000a504, 0x04002222, 0x04002222, 0x04000002, 0x04000002},
11063         {0x0000a508, 0x09002421, 0x09002421, 0x08000004, 0x08000004},
11064 @@ -1086,8 +1086,8 @@ static const u32 ar9300Common_rx_gain_ta
11065         {0x0000b074, 0x00000000},
11066         {0x0000b078, 0x00000000},
11067         {0x0000b07c, 0x00000000},
11068 -       {0x0000b080, 0x2a2d2f32},
11069 -       {0x0000b084, 0x21232328},
11070 +       {0x0000b080, 0x23232323},
11071 +       {0x0000b084, 0x21232323},
11072         {0x0000b088, 0x19191c1e},
11073         {0x0000b08c, 0x12141417},
11074         {0x0000b090, 0x07070e0e},
11075 @@ -1385,9 +1385,9 @@ static const u32 ar9300_2p2_mac_core[][2
11076         {0x000081f8, 0x00000000},
11077         {0x000081fc, 0x00000000},
11078         {0x00008240, 0x00100000},
11079 -       {0x00008244, 0x0010f424},
11080 +       {0x00008244, 0x0010f400},
11081         {0x00008248, 0x00000800},
11082 -       {0x0000824c, 0x0001e848},
11083 +       {0x0000824c, 0x0001e800},
11084         {0x00008250, 0x00000000},
11085         {0x00008254, 0x00000000},
11086         {0x00008258, 0x00000000},
11087 @@ -1726,16 +1726,30 @@ static const u32 ar9300PciePhy_pll_on_cl
11088
11089  static const u32 ar9300PciePhy_clkreq_enable_L1_2p2[][2] = {
11090         /* Addr      allmodes  */
11091 -       {0x00004040, 0x08253e5e},
11092 +       {0x00004040, 0x0825365e},
11093         {0x00004040, 0x0008003b},
11094         {0x00004044, 0x00000000},
11095  };
11096
11097  static const u32 ar9300PciePhy_clkreq_disable_L1_2p2[][2] = {
11098         /* Addr      allmodes  */
11099 -       {0x00004040, 0x08213e5e},
11100 +       {0x00004040, 0x0821365e},
11101         {0x00004040, 0x0008003b},
11102         {0x00004044, 0x00000000},
11103  };
11104
11105 +static const u32 ar9300_2p2_baseband_core_txfir_coeff_japan_2484[][2] = {
11106 +       /* Addr      allmodes  */
11107 +       {0x0000a398, 0x00000000},
11108 +       {0x0000a39c, 0x6f7f0301},
11109 +       {0x0000a3a0, 0xca9228ee},
11110 +};
11111 +
11112 +static const u32 ar9300_2p2_baseband_postamble_dfs_channel[][3] = {
11113 +       /* Addr      5G          2G        */
11114 +       {0x00009824, 0x5ac668d0, 0x5ac668d0},
11115 +       {0x00009e0c, 0x6d4000e2, 0x6d4000e2},
11116 +       {0x00009e14, 0x37b9625e, 0x37b9625e},
11117 +};
11118 +
11119  #endif /* INITVALS_9003_2P2_H */
11120 --- /dev/null
11121 +++ b/drivers/net/wireless/ath/ath9k/ar9565_1p1_initvals.h
11122 @@ -0,0 +1,64 @@
11123 +/*
11124 + * Copyright (c) 2010-2011 Atheros Communications Inc.
11125 + * Copyright (c) 2011-2012 Qualcomm Atheros Inc.
11126 + *
11127 + * Permission to use, copy, modify, and/or distribute this software for any
11128 + * purpose with or without fee is hereby granted, provided that the above
11129 + * copyright notice and this permission notice appear in all copies.
11130 + *
11131 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11132 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11133 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11134 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
11135 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
11136 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
11137 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
11138 + */
11139 +
11140 +#ifndef INITVALS_9565_1P1_H
11141 +#define INITVALS_9565_1P1_H
11142 +
11143 +/* AR9565 1.1 */
11144 +
11145 +#define ar9565_1p1_mac_core ar9565_1p0_mac_core
11146 +
11147 +#define ar9565_1p1_mac_postamble ar9565_1p0_mac_postamble
11148 +
11149 +#define ar9565_1p1_baseband_core ar9565_1p0_baseband_core
11150 +
11151 +#define ar9565_1p1_baseband_postamble ar9565_1p0_baseband_postamble
11152 +
11153 +#define ar9565_1p1_radio_core ar9565_1p0_radio_core
11154 +
11155 +#define ar9565_1p1_soc_preamble ar9565_1p0_soc_preamble
11156 +
11157 +#define ar9565_1p1_soc_postamble ar9565_1p0_soc_postamble
11158 +
11159 +#define ar9565_1p1_Common_rx_gain_table ar9565_1p0_Common_rx_gain_table
11160 +
11161 +#define ar9565_1p1_Modes_lowest_ob_db_tx_gain_table ar9565_1p0_Modes_lowest_ob_db_tx_gain_table
11162 +
11163 +#define ar9565_1p1_pciephy_clkreq_disable_L1 ar9565_1p0_pciephy_clkreq_disable_L1
11164 +
11165 +#define ar9565_1p1_modes_fast_clock ar9565_1p0_modes_fast_clock
11166 +
11167 +#define ar9565_1p1_common_wo_xlna_rx_gain_table ar9565_1p0_common_wo_xlna_rx_gain_table
11168 +
11169 +#define ar9565_1p1_modes_low_ob_db_tx_gain_table ar9565_1p0_modes_low_ob_db_tx_gain_table
11170 +
11171 +#define ar9565_1p1_modes_high_ob_db_tx_gain_table ar9565_1p0_modes_high_ob_db_tx_gain_table
11172 +
11173 +#define ar9565_1p1_modes_high_power_tx_gain_table ar9565_1p0_modes_high_power_tx_gain_table
11174 +
11175 +#define ar9565_1p1_baseband_core_txfir_coeff_japan_2484 ar9565_1p0_baseband_core_txfir_coeff_japan_2484
11176 +
11177 +static const u32 ar9565_1p1_radio_postamble[][5] = {
11178 +       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
11179 +       {0x0001609c, 0x0b8ee524, 0x0b8ee524, 0x0b8ee524, 0x0b8ee524},
11180 +       {0x000160ac, 0xa4646c08, 0xa4646c08, 0x24645808, 0x24645808},
11181 +       {0x000160b0, 0x01d67f70, 0x01d67f70, 0x01d67f70, 0x01d67f70},
11182 +       {0x0001610c, 0x40000000, 0x40000000, 0x40000000, 0x40000000},
11183 +       {0x00016140, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
11184 +};
11185 +
11186 +#endif /* INITVALS_9565_1P1_H */
11187 --- a/drivers/net/wireless/ath/ath9k/ar9580_1p0_initvals.h
11188 +++ b/drivers/net/wireless/ath/ath9k/ar9580_1p0_initvals.h
11189 @@ -20,18 +20,34 @@
11190
11191  /* AR9580 1.0 */
11192
11193 +#define ar9580_1p0_soc_preamble ar9300_2p2_soc_preamble
11194 +
11195 +#define ar9580_1p0_soc_postamble ar9300_2p2_soc_postamble
11196 +
11197 +#define ar9580_1p0_radio_core ar9300_2p2_radio_core
11198 +
11199 +#define ar9580_1p0_mac_postamble ar9300_2p2_mac_postamble
11200 +
11201 +#define ar9580_1p0_wo_xlna_rx_gain_table ar9300Common_wo_xlna_rx_gain_table_2p2
11202 +
11203 +#define ar9580_1p0_type5_tx_gain_table ar9300Modes_type5_tx_gain_table_2p2
11204 +
11205 +#define ar9580_1p0_high_ob_db_tx_gain_table ar9300Modes_high_ob_db_tx_gain_table_2p2
11206 +
11207  #define ar9580_1p0_modes_fast_clock ar9300Modes_fast_clock_2p2
11208
11209 +#define ar9580_1p0_baseband_core_txfir_coeff_japan_2484 ar9300_2p2_baseband_core_txfir_coeff_japan_2484
11210 +
11211  static const u32 ar9580_1p0_radio_postamble[][5] = {
11212         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
11213         {0x0001609c, 0x0dd08f29, 0x0dd08f29, 0x0b283f31, 0x0b283f31},
11214         {0x000160ac, 0xa4653c00, 0xa4653c00, 0x24652800, 0x24652800},
11215         {0x000160b0, 0x03284f3e, 0x03284f3e, 0x05d08f20, 0x05d08f20},
11216 -       {0x0001610c, 0x08000000, 0x00000000, 0x00000000, 0x00000000},
11217 +       {0x0001610c, 0xc8000000, 0xc0000000, 0xc0000000, 0xc0000000},
11218         {0x00016140, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
11219 -       {0x0001650c, 0x08000000, 0x00000000, 0x00000000, 0x00000000},
11220 +       {0x0001650c, 0xc8000000, 0xc0000000, 0xc0000000, 0xc0000000},
11221         {0x00016540, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
11222 -       {0x0001690c, 0x08000000, 0x00000000, 0x00000000, 0x00000000},
11223 +       {0x0001690c, 0xc8000000, 0xc0000000, 0xc0000000, 0xc0000000},
11224         {0x00016940, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
11225  };
11226
11227 @@ -41,12 +57,10 @@ static const u32 ar9580_1p0_baseband_cor
11228         {0x00009804, 0xfd14e000},
11229         {0x00009808, 0x9c0a9f6b},
11230         {0x0000980c, 0x04900000},
11231 -       {0x00009814, 0x3280c00a},
11232 -       {0x00009818, 0x00000000},
11233         {0x0000981c, 0x00020028},
11234 -       {0x00009834, 0x6400a290},
11235 +       {0x00009834, 0x6400a190},
11236         {0x00009838, 0x0108ecff},
11237 -       {0x0000983c, 0x0d000600},
11238 +       {0x0000983c, 0x14000600},
11239         {0x00009880, 0x201fff00},
11240         {0x00009884, 0x00001042},
11241         {0x000098a4, 0x00200400},
11242 @@ -67,7 +81,7 @@ static const u32 ar9580_1p0_baseband_cor
11243         {0x00009d04, 0x40206c10},
11244         {0x00009d08, 0x009c4060},
11245         {0x00009d0c, 0x9883800a},
11246 -       {0x00009d10, 0x01834061},
11247 +       {0x00009d10, 0x01884061},
11248         {0x00009d14, 0x00c0040b},
11249         {0x00009d18, 0x00000000},
11250         {0x00009e08, 0x0038230c},
11251 @@ -198,8 +212,6 @@ static const u32 ar9580_1p0_baseband_cor
11252         {0x0000c420, 0x00000000},
11253  };
11254
11255 -#define ar9580_1p0_mac_postamble ar9300_2p2_mac_postamble
11256 -
11257  static const u32 ar9580_1p0_low_ob_db_tx_gain_table[][5] = {
11258         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
11259         {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
11260 @@ -306,7 +318,112 @@ static const u32 ar9580_1p0_low_ob_db_tx
11261         {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
11262  };
11263
11264 -#define ar9580_1p0_high_power_tx_gain_table ar9580_1p0_low_ob_db_tx_gain_table
11265 +static const u32 ar9580_1p0_high_power_tx_gain_table[][5] = {
11266 +       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
11267 +       {0x0000a2dc, 0x000cfff0, 0x000cfff0, 0x03aaa352, 0x03aaa352},
11268 +       {0x0000a2e0, 0x000f0000, 0x000f0000, 0x03ccc584, 0x03ccc584},
11269 +       {0x0000a2e4, 0x03f00000, 0x03f00000, 0x03f0f800, 0x03f0f800},
11270 +       {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
11271 +       {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
11272 +       {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
11273 +       {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
11274 +       {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004},
11275 +       {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
11276 +       {0x0000a510, 0x15000028, 0x15000028, 0x0f000202, 0x0f000202},
11277 +       {0x0000a514, 0x1b00002b, 0x1b00002b, 0x12000400, 0x12000400},
11278 +       {0x0000a518, 0x1f020028, 0x1f020028, 0x16000402, 0x16000402},
11279 +       {0x0000a51c, 0x2502002b, 0x2502002b, 0x19000404, 0x19000404},
11280 +       {0x0000a520, 0x2a04002a, 0x2a04002a, 0x1c000603, 0x1c000603},
11281 +       {0x0000a524, 0x2e06002a, 0x2e06002a, 0x21000a02, 0x21000a02},
11282 +       {0x0000a528, 0x3302202d, 0x3302202d, 0x25000a04, 0x25000a04},
11283 +       {0x0000a52c, 0x3804202c, 0x3804202c, 0x28000a20, 0x28000a20},
11284 +       {0x0000a530, 0x3c06202c, 0x3c06202c, 0x2c000e20, 0x2c000e20},
11285 +       {0x0000a534, 0x4108202d, 0x4108202d, 0x30000e22, 0x30000e22},
11286 +       {0x0000a538, 0x4506402d, 0x4506402d, 0x34000e24, 0x34000e24},
11287 +       {0x0000a53c, 0x4906222d, 0x4906222d, 0x38001640, 0x38001640},
11288 +       {0x0000a540, 0x4d062231, 0x4d062231, 0x3c001660, 0x3c001660},
11289 +       {0x0000a544, 0x50082231, 0x50082231, 0x3f001861, 0x3f001861},
11290 +       {0x0000a548, 0x5608422e, 0x5608422e, 0x43001a81, 0x43001a81},
11291 +       {0x0000a54c, 0x5e08442e, 0x5e08442e, 0x47001a83, 0x47001a83},
11292 +       {0x0000a550, 0x620a4431, 0x620a4431, 0x4a001c84, 0x4a001c84},
11293 +       {0x0000a554, 0x640a4432, 0x640a4432, 0x4e001ce3, 0x4e001ce3},
11294 +       {0x0000a558, 0x680a4434, 0x680a4434, 0x52001ce5, 0x52001ce5},
11295 +       {0x0000a55c, 0x6c0a6434, 0x6c0a6434, 0x56001ce9, 0x56001ce9},
11296 +       {0x0000a560, 0x6f0a6633, 0x6f0a6633, 0x5a001ceb, 0x5a001ceb},
11297 +       {0x0000a564, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
11298 +       {0x0000a568, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
11299 +       {0x0000a56c, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
11300 +       {0x0000a570, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
11301 +       {0x0000a574, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
11302 +       {0x0000a578, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
11303 +       {0x0000a57c, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
11304 +       {0x0000a580, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
11305 +       {0x0000a584, 0x06800003, 0x06800003, 0x04800002, 0x04800002},
11306 +       {0x0000a588, 0x0a800020, 0x0a800020, 0x08800004, 0x08800004},
11307 +       {0x0000a58c, 0x10800023, 0x10800023, 0x0b800200, 0x0b800200},
11308 +       {0x0000a590, 0x15800028, 0x15800028, 0x0f800202, 0x0f800202},
11309 +       {0x0000a594, 0x1b80002b, 0x1b80002b, 0x12800400, 0x12800400},
11310 +       {0x0000a598, 0x1f820028, 0x1f820028, 0x16800402, 0x16800402},
11311 +       {0x0000a59c, 0x2582002b, 0x2582002b, 0x19800404, 0x19800404},
11312 +       {0x0000a5a0, 0x2a84002a, 0x2a84002a, 0x1c800603, 0x1c800603},
11313 +       {0x0000a5a4, 0x2e86002a, 0x2e86002a, 0x21800a02, 0x21800a02},
11314 +       {0x0000a5a8, 0x3382202d, 0x3382202d, 0x25800a04, 0x25800a04},
11315 +       {0x0000a5ac, 0x3884202c, 0x3884202c, 0x28800a20, 0x28800a20},
11316 +       {0x0000a5b0, 0x3c86202c, 0x3c86202c, 0x2c800e20, 0x2c800e20},
11317 +       {0x0000a5b4, 0x4188202d, 0x4188202d, 0x30800e22, 0x30800e22},
11318 +       {0x0000a5b8, 0x4586402d, 0x4586402d, 0x34800e24, 0x34800e24},
11319 +       {0x0000a5bc, 0x4986222d, 0x4986222d, 0x38801640, 0x38801640},
11320 +       {0x0000a5c0, 0x4d862231, 0x4d862231, 0x3c801660, 0x3c801660},
11321 +       {0x0000a5c4, 0x50882231, 0x50882231, 0x3f801861, 0x3f801861},
11322 +       {0x0000a5c8, 0x5688422e, 0x5688422e, 0x43801a81, 0x43801a81},
11323 +       {0x0000a5cc, 0x5a88442e, 0x5a88442e, 0x47801a83, 0x47801a83},
11324 +       {0x0000a5d0, 0x5e8a4431, 0x5e8a4431, 0x4a801c84, 0x4a801c84},
11325 +       {0x0000a5d4, 0x648a4432, 0x648a4432, 0x4e801ce3, 0x4e801ce3},
11326 +       {0x0000a5d8, 0x688a4434, 0x688a4434, 0x52801ce5, 0x52801ce5},
11327 +       {0x0000a5dc, 0x6c8a6434, 0x6c8a6434, 0x56801ce9, 0x56801ce9},
11328 +       {0x0000a5e0, 0x6f8a6633, 0x6f8a6633, 0x5a801ceb, 0x5a801ceb},
11329 +       {0x0000a5e4, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
11330 +       {0x0000a5e8, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
11331 +       {0x0000a5ec, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
11332 +       {0x0000a5f0, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
11333 +       {0x0000a5f4, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
11334 +       {0x0000a5f8, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
11335 +       {0x0000a5fc, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
11336 +       {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
11337 +       {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
11338 +       {0x0000a608, 0x01804601, 0x01804601, 0x00000000, 0x00000000},
11339 +       {0x0000a60c, 0x01804601, 0x01804601, 0x00000000, 0x00000000},
11340 +       {0x0000a610, 0x01804601, 0x01804601, 0x00000000, 0x00000000},
11341 +       {0x0000a614, 0x01804601, 0x01804601, 0x01404000, 0x01404000},
11342 +       {0x0000a618, 0x01804601, 0x01804601, 0x01404501, 0x01404501},
11343 +       {0x0000a61c, 0x01804601, 0x01804601, 0x02008501, 0x02008501},
11344 +       {0x0000a620, 0x03408d02, 0x03408d02, 0x0280ca03, 0x0280ca03},
11345 +       {0x0000a624, 0x0300cc03, 0x0300cc03, 0x03010c04, 0x03010c04},
11346 +       {0x0000a628, 0x03410d04, 0x03410d04, 0x04014c04, 0x04014c04},
11347 +       {0x0000a62c, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
11348 +       {0x0000a630, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
11349 +       {0x0000a634, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
11350 +       {0x0000a638, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
11351 +       {0x0000a63c, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
11352 +       {0x0000b2dc, 0x000cfff0, 0x000cfff0, 0x03aaa352, 0x03aaa352},
11353 +       {0x0000b2e0, 0x000f0000, 0x000f0000, 0x03ccc584, 0x03ccc584},
11354 +       {0x0000b2e4, 0x03f00000, 0x03f00000, 0x03f0f800, 0x03f0f800},
11355 +       {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
11356 +       {0x0000c2dc, 0x000cfff0, 0x000cfff0, 0x03aaa352, 0x03aaa352},
11357 +       {0x0000c2e0, 0x000f0000, 0x000f0000, 0x03ccc584, 0x03ccc584},
11358 +       {0x0000c2e4, 0x03f00000, 0x03f00000, 0x03f0f800, 0x03f0f800},
11359 +       {0x0000c2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
11360 +       {0x00016044, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
11361 +       {0x00016048, 0x65240001, 0x65240001, 0x66480001, 0x66480001},
11362 +       {0x00016068, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
11363 +       {0x00016288, 0x05a2040a, 0x05a2040a, 0x05a20408, 0x05a20408},
11364 +       {0x00016444, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
11365 +       {0x00016448, 0x65240001, 0x65240001, 0x66480001, 0x66480001},
11366 +       {0x00016468, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
11367 +       {0x00016844, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
11368 +       {0x00016848, 0x65240001, 0x65240001, 0x66480001, 0x66480001},
11369 +       {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
11370 +};
11371
11372  static const u32 ar9580_1p0_lowest_ob_db_tx_gain_table[][5] = {
11373         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
11374 @@ -414,8 +531,6 @@ static const u32 ar9580_1p0_lowest_ob_db
11375         {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
11376  };
11377
11378 -#define ar9580_1p0_baseband_core_txfir_coeff_japan_2484 ar9462_2p0_baseband_core_txfir_coeff_japan_2484
11379 -
11380  static const u32 ar9580_1p0_mac_core[][2] = {
11381         /* Addr      allmodes  */
11382         {0x00000008, 0x00000000},
11383 @@ -679,14 +794,6 @@ static const u32 ar9580_1p0_mixed_ob_db_
11384         {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
11385  };
11386
11387 -#define ar9580_1p0_wo_xlna_rx_gain_table ar9300Common_wo_xlna_rx_gain_table_2p2
11388 -
11389 -#define ar9580_1p0_soc_postamble ar9300_2p2_soc_postamble
11390 -
11391 -#define ar9580_1p0_high_ob_db_tx_gain_table ar9300Modes_high_ob_db_tx_gain_table_2p2
11392 -
11393 -#define ar9580_1p0_type5_tx_gain_table ar9300Modes_type5_tx_gain_table_2p2
11394 -
11395  static const u32 ar9580_1p0_type6_tx_gain_table[][5] = {
11396         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
11397         {0x0000a2dc, 0x000cfff0, 0x000cfff0, 0x03aaa352, 0x03aaa352},
11398 @@ -761,165 +868,271 @@ static const u32 ar9580_1p0_type6_tx_gai
11399         {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
11400  };
11401
11402 -static const u32 ar9580_1p0_soc_preamble[][2] = {
11403 +static const u32 ar9580_1p0_rx_gain_table[][2] = {
11404         /* Addr      allmodes  */
11405 -       {0x000040a4, 0x00a0c1c9},
11406 -       {0x00007008, 0x00000000},
11407 -       {0x00007020, 0x00000000},
11408 -       {0x00007034, 0x00000002},
11409 -       {0x00007038, 0x000004c2},
11410 -       {0x00007048, 0x00000008},
11411 -};
11412 -
11413 -#define ar9580_1p0_rx_gain_table ar9462_common_rx_gain_table_2p0
11414 -
11415 -static const u32 ar9580_1p0_radio_core[][2] = {
11416 -       /* Addr      allmodes  */
11417 -       {0x00016000, 0x36db6db6},
11418 -       {0x00016004, 0x6db6db40},
11419 -       {0x00016008, 0x73f00000},
11420 -       {0x0001600c, 0x00000000},
11421 -       {0x00016040, 0x7f80fff8},
11422 -       {0x0001604c, 0x76d005b5},
11423 -       {0x00016050, 0x556cf031},
11424 -       {0x00016054, 0x13449440},
11425 -       {0x00016058, 0x0c51c92c},
11426 -       {0x0001605c, 0x3db7fffc},
11427 -       {0x00016060, 0xfffffffc},
11428 -       {0x00016064, 0x000f0278},
11429 -       {0x0001606c, 0x6db60000},
11430 -       {0x00016080, 0x00000000},
11431 -       {0x00016084, 0x0e48048c},
11432 -       {0x00016088, 0x54214514},
11433 -       {0x0001608c, 0x119f481e},
11434 -       {0x00016090, 0x24926490},
11435 -       {0x00016098, 0xd2888888},
11436 -       {0x000160a0, 0x0a108ffe},
11437 -       {0x000160a4, 0x812fc370},
11438 -       {0x000160a8, 0x423c8000},
11439 -       {0x000160b4, 0x92480080},
11440 -       {0x000160c0, 0x00adb6d0},
11441 -       {0x000160c4, 0x6db6db60},
11442 -       {0x000160c8, 0x6db6db6c},
11443 -       {0x000160cc, 0x01e6c000},
11444 -       {0x00016100, 0x3fffbe01},
11445 -       {0x00016104, 0xfff80000},
11446 -       {0x00016108, 0x00080010},
11447 -       {0x00016144, 0x02084080},
11448 -       {0x00016148, 0x00000000},
11449 -       {0x00016280, 0x058a0001},
11450 -       {0x00016284, 0x3d840208},
11451 -       {0x00016288, 0x05a20408},
11452 -       {0x0001628c, 0x00038c07},
11453 -       {0x00016290, 0x00000004},
11454 -       {0x00016294, 0x458aa14f},
11455 -       {0x00016380, 0x00000000},
11456 -       {0x00016384, 0x00000000},
11457 -       {0x00016388, 0x00800700},
11458 -       {0x0001638c, 0x00800700},
11459 -       {0x00016390, 0x00800700},
11460 -       {0x00016394, 0x00000000},
11461 -       {0x00016398, 0x00000000},
11462 -       {0x0001639c, 0x00000000},
11463 -       {0x000163a0, 0x00000001},
11464 -       {0x000163a4, 0x00000001},
11465 -       {0x000163a8, 0x00000000},
11466 -       {0x000163ac, 0x00000000},
11467 -       {0x000163b0, 0x00000000},
11468 -       {0x000163b4, 0x00000000},
11469 -       {0x000163b8, 0x00000000},
11470 -       {0x000163bc, 0x00000000},
11471 -       {0x000163c0, 0x000000a0},
11472 -       {0x000163c4, 0x000c0000},
11473 -       {0x000163c8, 0x14021402},
11474 -       {0x000163cc, 0x00001402},
11475 -       {0x000163d0, 0x00000000},
11476 -       {0x000163d4, 0x00000000},
11477 -       {0x00016400, 0x36db6db6},
11478 -       {0x00016404, 0x6db6db40},
11479 -       {0x00016408, 0x73f00000},
11480 -       {0x0001640c, 0x00000000},
11481 -       {0x00016440, 0x7f80fff8},
11482 -       {0x0001644c, 0x76d005b5},
11483 -       {0x00016450, 0x556cf031},
11484 -       {0x00016454, 0x13449440},
11485 -       {0x00016458, 0x0c51c92c},
11486 -       {0x0001645c, 0x3db7fffc},
11487 -       {0x00016460, 0xfffffffc},
11488 -       {0x00016464, 0x000f0278},
11489 -       {0x0001646c, 0x6db60000},
11490 -       {0x00016500, 0x3fffbe01},
11491 -       {0x00016504, 0xfff80000},
11492 -       {0x00016508, 0x00080010},
11493 -       {0x00016544, 0x02084080},
11494 -       {0x00016548, 0x00000000},
11495 -       {0x00016780, 0x00000000},
11496 -       {0x00016784, 0x00000000},
11497 -       {0x00016788, 0x00800700},
11498 -       {0x0001678c, 0x00800700},
11499 -       {0x00016790, 0x00800700},
11500 -       {0x00016794, 0x00000000},
11501 -       {0x00016798, 0x00000000},
11502 -       {0x0001679c, 0x00000000},
11503 -       {0x000167a0, 0x00000001},
11504 -       {0x000167a4, 0x00000001},
11505 -       {0x000167a8, 0x00000000},
11506 -       {0x000167ac, 0x00000000},
11507 -       {0x000167b0, 0x00000000},
11508 -       {0x000167b4, 0x00000000},
11509 -       {0x000167b8, 0x00000000},
11510 -       {0x000167bc, 0x00000000},
11511 -       {0x000167c0, 0x000000a0},
11512 -       {0x000167c4, 0x000c0000},
11513 -       {0x000167c8, 0x14021402},
11514 -       {0x000167cc, 0x00001402},
11515 -       {0x000167d0, 0x00000000},
11516 -       {0x000167d4, 0x00000000},
11517 -       {0x00016800, 0x36db6db6},
11518 -       {0x00016804, 0x6db6db40},
11519 -       {0x00016808, 0x73f00000},
11520 -       {0x0001680c, 0x00000000},
11521 -       {0x00016840, 0x7f80fff8},
11522 -       {0x0001684c, 0x76d005b5},
11523 -       {0x00016850, 0x556cf031},
11524 -       {0x00016854, 0x13449440},
11525 -       {0x00016858, 0x0c51c92c},
11526 -       {0x0001685c, 0x3db7fffc},
11527 -       {0x00016860, 0xfffffffc},
11528 -       {0x00016864, 0x000f0278},
11529 -       {0x0001686c, 0x6db60000},
11530 -       {0x00016900, 0x3fffbe01},
11531 -       {0x00016904, 0xfff80000},
11532 -       {0x00016908, 0x00080010},
11533 -       {0x00016944, 0x02084080},
11534 -       {0x00016948, 0x00000000},
11535 -       {0x00016b80, 0x00000000},
11536 -       {0x00016b84, 0x00000000},
11537 -       {0x00016b88, 0x00800700},
11538 -       {0x00016b8c, 0x00800700},
11539 -       {0x00016b90, 0x00800700},
11540 -       {0x00016b94, 0x00000000},
11541 -       {0x00016b98, 0x00000000},
11542 -       {0x00016b9c, 0x00000000},
11543 -       {0x00016ba0, 0x00000001},
11544 -       {0x00016ba4, 0x00000001},
11545 -       {0x00016ba8, 0x00000000},
11546 -       {0x00016bac, 0x00000000},
11547 -       {0x00016bb0, 0x00000000},
11548 -       {0x00016bb4, 0x00000000},
11549 -       {0x00016bb8, 0x00000000},
11550 -       {0x00016bbc, 0x00000000},
11551 -       {0x00016bc0, 0x000000a0},
11552 -       {0x00016bc4, 0x000c0000},
11553 -       {0x00016bc8, 0x14021402},
11554 -       {0x00016bcc, 0x00001402},
11555 -       {0x00016bd0, 0x00000000},
11556 -       {0x00016bd4, 0x00000000},
11557 +       {0x0000a000, 0x00010000},
11558 +       {0x0000a004, 0x00030002},
11559 +       {0x0000a008, 0x00050004},
11560 +       {0x0000a00c, 0x00810080},
11561 +       {0x0000a010, 0x00830082},
11562 +       {0x0000a014, 0x01810180},
11563 +       {0x0000a018, 0x01830182},
11564 +       {0x0000a01c, 0x01850184},
11565 +       {0x0000a020, 0x01890188},
11566 +       {0x0000a024, 0x018b018a},
11567 +       {0x0000a028, 0x018d018c},
11568 +       {0x0000a02c, 0x01910190},
11569 +       {0x0000a030, 0x01930192},
11570 +       {0x0000a034, 0x01950194},
11571 +       {0x0000a038, 0x038a0196},
11572 +       {0x0000a03c, 0x038c038b},
11573 +       {0x0000a040, 0x0390038d},
11574 +       {0x0000a044, 0x03920391},
11575 +       {0x0000a048, 0x03940393},
11576 +       {0x0000a04c, 0x03960395},
11577 +       {0x0000a050, 0x00000000},
11578 +       {0x0000a054, 0x00000000},
11579 +       {0x0000a058, 0x00000000},
11580 +       {0x0000a05c, 0x00000000},
11581 +       {0x0000a060, 0x00000000},
11582 +       {0x0000a064, 0x00000000},
11583 +       {0x0000a068, 0x00000000},
11584 +       {0x0000a06c, 0x00000000},
11585 +       {0x0000a070, 0x00000000},
11586 +       {0x0000a074, 0x00000000},
11587 +       {0x0000a078, 0x00000000},
11588 +       {0x0000a07c, 0x00000000},
11589 +       {0x0000a080, 0x22222229},
11590 +       {0x0000a084, 0x1d1d1d1d},
11591 +       {0x0000a088, 0x1d1d1d1d},
11592 +       {0x0000a08c, 0x1d1d1d1d},
11593 +       {0x0000a090, 0x171d1d1d},
11594 +       {0x0000a094, 0x11111717},
11595 +       {0x0000a098, 0x00030311},
11596 +       {0x0000a09c, 0x00000000},
11597 +       {0x0000a0a0, 0x00000000},
11598 +       {0x0000a0a4, 0x00000000},
11599 +       {0x0000a0a8, 0x00000000},
11600 +       {0x0000a0ac, 0x00000000},
11601 +       {0x0000a0b0, 0x00000000},
11602 +       {0x0000a0b4, 0x00000000},
11603 +       {0x0000a0b8, 0x00000000},
11604 +       {0x0000a0bc, 0x00000000},
11605 +       {0x0000a0c0, 0x001f0000},
11606 +       {0x0000a0c4, 0x01000101},
11607 +       {0x0000a0c8, 0x011e011f},
11608 +       {0x0000a0cc, 0x011c011d},
11609 +       {0x0000a0d0, 0x02030204},
11610 +       {0x0000a0d4, 0x02010202},
11611 +       {0x0000a0d8, 0x021f0200},
11612 +       {0x0000a0dc, 0x0302021e},
11613 +       {0x0000a0e0, 0x03000301},
11614 +       {0x0000a0e4, 0x031e031f},
11615 +       {0x0000a0e8, 0x0402031d},
11616 +       {0x0000a0ec, 0x04000401},
11617 +       {0x0000a0f0, 0x041e041f},
11618 +       {0x0000a0f4, 0x0502041d},
11619 +       {0x0000a0f8, 0x05000501},
11620 +       {0x0000a0fc, 0x051e051f},
11621 +       {0x0000a100, 0x06010602},
11622 +       {0x0000a104, 0x061f0600},
11623 +       {0x0000a108, 0x061d061e},
11624 +       {0x0000a10c, 0x07020703},
11625 +       {0x0000a110, 0x07000701},
11626 +       {0x0000a114, 0x00000000},
11627 +       {0x0000a118, 0x00000000},
11628 +       {0x0000a11c, 0x00000000},
11629 +       {0x0000a120, 0x00000000},
11630 +       {0x0000a124, 0x00000000},
11631 +       {0x0000a128, 0x00000000},
11632 +       {0x0000a12c, 0x00000000},
11633 +       {0x0000a130, 0x00000000},
11634 +       {0x0000a134, 0x00000000},
11635 +       {0x0000a138, 0x00000000},
11636 +       {0x0000a13c, 0x00000000},
11637 +       {0x0000a140, 0x001f0000},
11638 +       {0x0000a144, 0x01000101},
11639 +       {0x0000a148, 0x011e011f},
11640 +       {0x0000a14c, 0x011c011d},
11641 +       {0x0000a150, 0x02030204},
11642 +       {0x0000a154, 0x02010202},
11643 +       {0x0000a158, 0x021f0200},
11644 +       {0x0000a15c, 0x0302021e},
11645 +       {0x0000a160, 0x03000301},
11646 +       {0x0000a164, 0x031e031f},
11647 +       {0x0000a168, 0x0402031d},
11648 +       {0x0000a16c, 0x04000401},
11649 +       {0x0000a170, 0x041e041f},
11650 +       {0x0000a174, 0x0502041d},
11651 +       {0x0000a178, 0x05000501},
11652 +       {0x0000a17c, 0x051e051f},
11653 +       {0x0000a180, 0x06010602},
11654 +       {0x0000a184, 0x061f0600},
11655 +       {0x0000a188, 0x061d061e},
11656 +       {0x0000a18c, 0x07020703},
11657 +       {0x0000a190, 0x07000701},
11658 +       {0x0000a194, 0x00000000},
11659 +       {0x0000a198, 0x00000000},
11660 +       {0x0000a19c, 0x00000000},
11661 +       {0x0000a1a0, 0x00000000},
11662 +       {0x0000a1a4, 0x00000000},
11663 +       {0x0000a1a8, 0x00000000},
11664 +       {0x0000a1ac, 0x00000000},
11665 +       {0x0000a1b0, 0x00000000},
11666 +       {0x0000a1b4, 0x00000000},
11667 +       {0x0000a1b8, 0x00000000},
11668 +       {0x0000a1bc, 0x00000000},
11669 +       {0x0000a1c0, 0x00000000},
11670 +       {0x0000a1c4, 0x00000000},
11671 +       {0x0000a1c8, 0x00000000},
11672 +       {0x0000a1cc, 0x00000000},
11673 +       {0x0000a1d0, 0x00000000},
11674 +       {0x0000a1d4, 0x00000000},
11675 +       {0x0000a1d8, 0x00000000},
11676 +       {0x0000a1dc, 0x00000000},
11677 +       {0x0000a1e0, 0x00000000},
11678 +       {0x0000a1e4, 0x00000000},
11679 +       {0x0000a1e8, 0x00000000},
11680 +       {0x0000a1ec, 0x00000000},
11681 +       {0x0000a1f0, 0x00000396},
11682 +       {0x0000a1f4, 0x00000396},
11683 +       {0x0000a1f8, 0x00000396},
11684 +       {0x0000a1fc, 0x00000196},
11685 +       {0x0000b000, 0x00010000},
11686 +       {0x0000b004, 0x00030002},
11687 +       {0x0000b008, 0x00050004},
11688 +       {0x0000b00c, 0x00810080},
11689 +       {0x0000b010, 0x00830082},
11690 +       {0x0000b014, 0x01810180},
11691 +       {0x0000b018, 0x01830182},
11692 +       {0x0000b01c, 0x01850184},
11693 +       {0x0000b020, 0x02810280},
11694 +       {0x0000b024, 0x02830282},
11695 +       {0x0000b028, 0x02850284},
11696 +       {0x0000b02c, 0x02890288},
11697 +       {0x0000b030, 0x028b028a},
11698 +       {0x0000b034, 0x0388028c},
11699 +       {0x0000b038, 0x038a0389},
11700 +       {0x0000b03c, 0x038c038b},
11701 +       {0x0000b040, 0x0390038d},
11702 +       {0x0000b044, 0x03920391},
11703 +       {0x0000b048, 0x03940393},
11704 +       {0x0000b04c, 0x03960395},
11705 +       {0x0000b050, 0x00000000},
11706 +       {0x0000b054, 0x00000000},
11707 +       {0x0000b058, 0x00000000},
11708 +       {0x0000b05c, 0x00000000},
11709 +       {0x0000b060, 0x00000000},
11710 +       {0x0000b064, 0x00000000},
11711 +       {0x0000b068, 0x00000000},
11712 +       {0x0000b06c, 0x00000000},
11713 +       {0x0000b070, 0x00000000},
11714 +       {0x0000b074, 0x00000000},
11715 +       {0x0000b078, 0x00000000},
11716 +       {0x0000b07c, 0x00000000},
11717 +       {0x0000b080, 0x23232323},
11718 +       {0x0000b084, 0x21232323},
11719 +       {0x0000b088, 0x19191c1e},
11720 +       {0x0000b08c, 0x12141417},
11721 +       {0x0000b090, 0x07070e0e},
11722 +       {0x0000b094, 0x03030305},
11723 +       {0x0000b098, 0x00000003},
11724 +       {0x0000b09c, 0x00000000},
11725 +       {0x0000b0a0, 0x00000000},
11726 +       {0x0000b0a4, 0x00000000},
11727 +       {0x0000b0a8, 0x00000000},
11728 +       {0x0000b0ac, 0x00000000},
11729 +       {0x0000b0b0, 0x00000000},
11730 +       {0x0000b0b4, 0x00000000},
11731 +       {0x0000b0b8, 0x00000000},
11732 +       {0x0000b0bc, 0x00000000},
11733 +       {0x0000b0c0, 0x003f0020},
11734 +       {0x0000b0c4, 0x00400041},
11735 +       {0x0000b0c8, 0x0140005f},
11736 +       {0x0000b0cc, 0x0160015f},
11737 +       {0x0000b0d0, 0x017e017f},
11738 +       {0x0000b0d4, 0x02410242},
11739 +       {0x0000b0d8, 0x025f0240},
11740 +       {0x0000b0dc, 0x027f0260},
11741 +       {0x0000b0e0, 0x0341027e},
11742 +       {0x0000b0e4, 0x035f0340},
11743 +       {0x0000b0e8, 0x037f0360},
11744 +       {0x0000b0ec, 0x04400441},
11745 +       {0x0000b0f0, 0x0460045f},
11746 +       {0x0000b0f4, 0x0541047f},
11747 +       {0x0000b0f8, 0x055f0540},
11748 +       {0x0000b0fc, 0x057f0560},
11749 +       {0x0000b100, 0x06400641},
11750 +       {0x0000b104, 0x0660065f},
11751 +       {0x0000b108, 0x067e067f},
11752 +       {0x0000b10c, 0x07410742},
11753 +       {0x0000b110, 0x075f0740},
11754 +       {0x0000b114, 0x077f0760},
11755 +       {0x0000b118, 0x07800781},
11756 +       {0x0000b11c, 0x07a0079f},
11757 +       {0x0000b120, 0x07c107bf},
11758 +       {0x0000b124, 0x000007c0},
11759 +       {0x0000b128, 0x00000000},
11760 +       {0x0000b12c, 0x00000000},
11761 +       {0x0000b130, 0x00000000},
11762 +       {0x0000b134, 0x00000000},
11763 +       {0x0000b138, 0x00000000},
11764 +       {0x0000b13c, 0x00000000},
11765 +       {0x0000b140, 0x003f0020},
11766 +       {0x0000b144, 0x00400041},
11767 +       {0x0000b148, 0x0140005f},
11768 +       {0x0000b14c, 0x0160015f},
11769 +       {0x0000b150, 0x017e017f},
11770 +       {0x0000b154, 0x02410242},
11771 +       {0x0000b158, 0x025f0240},
11772 +       {0x0000b15c, 0x027f0260},
11773 +       {0x0000b160, 0x0341027e},
11774 +       {0x0000b164, 0x035f0340},
11775 +       {0x0000b168, 0x037f0360},
11776 +       {0x0000b16c, 0x04400441},
11777 +       {0x0000b170, 0x0460045f},
11778 +       {0x0000b174, 0x0541047f},
11779 +       {0x0000b178, 0x055f0540},
11780 +       {0x0000b17c, 0x057f0560},
11781 +       {0x0000b180, 0x06400641},
11782 +       {0x0000b184, 0x0660065f},
11783 +       {0x0000b188, 0x067e067f},
11784 +       {0x0000b18c, 0x07410742},
11785 +       {0x0000b190, 0x075f0740},
11786 +       {0x0000b194, 0x077f0760},
11787 +       {0x0000b198, 0x07800781},
11788 +       {0x0000b19c, 0x07a0079f},
11789 +       {0x0000b1a0, 0x07c107bf},
11790 +       {0x0000b1a4, 0x000007c0},
11791 +       {0x0000b1a8, 0x00000000},
11792 +       {0x0000b1ac, 0x00000000},
11793 +       {0x0000b1b0, 0x00000000},
11794 +       {0x0000b1b4, 0x00000000},
11795 +       {0x0000b1b8, 0x00000000},
11796 +       {0x0000b1bc, 0x00000000},
11797 +       {0x0000b1c0, 0x00000000},
11798 +       {0x0000b1c4, 0x00000000},
11799 +       {0x0000b1c8, 0x00000000},
11800 +       {0x0000b1cc, 0x00000000},
11801 +       {0x0000b1d0, 0x00000000},
11802 +       {0x0000b1d4, 0x00000000},
11803 +       {0x0000b1d8, 0x00000000},
11804 +       {0x0000b1dc, 0x00000000},
11805 +       {0x0000b1e0, 0x00000000},
11806 +       {0x0000b1e4, 0x00000000},
11807 +       {0x0000b1e8, 0x00000000},
11808 +       {0x0000b1ec, 0x00000000},
11809 +       {0x0000b1f0, 0x00000396},
11810 +       {0x0000b1f4, 0x00000396},
11811 +       {0x0000b1f8, 0x00000396},
11812 +       {0x0000b1fc, 0x00000196},
11813  };
11814
11815  static const u32 ar9580_1p0_baseband_postamble[][5] = {
11816         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
11817         {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a8011},
11818 +       {0x00009814, 0x3280c00a, 0x3280c00a, 0x3280c00a, 0x3280c00a},
11819 +       {0x00009818, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
11820         {0x00009820, 0x206a022e, 0x206a022e, 0x206a012e, 0x206a012e},
11821         {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0},
11822         {0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881},
11823 @@ -956,7 +1169,7 @@ static const u32 ar9580_1p0_baseband_pos
11824         {0x0000a288, 0x00000110, 0x00000110, 0x00000110, 0x00000110},
11825         {0x0000a28c, 0x00022222, 0x00022222, 0x00022222, 0x00022222},
11826         {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
11827 -       {0x0000a2d0, 0x00041981, 0x00041981, 0x00041981, 0x00041982},
11828 +       {0x0000a2d0, 0x00041983, 0x00041983, 0x00041981, 0x00041982},
11829         {0x0000a2d8, 0x7999a83b, 0x7999a83b, 0x7999a83b, 0x7999a83b},
11830         {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
11831         {0x0000a830, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
11832 @@ -994,4 +1207,13 @@ static const u32 ar9580_1p0_pcie_phy_pll
11833         {0x00004044, 0x00000000},
11834  };
11835
11836 +static const u32 ar9580_1p0_baseband_postamble_dfs_channel[][3] = {
11837 +       /* Addr      5G          2G        */
11838 +       {0x00009814, 0x3400c00f, 0x3400c00f},
11839 +       {0x00009824, 0x5ac668d0, 0x5ac668d0},
11840 +       {0x00009828, 0x06903080, 0x06903080},
11841 +       {0x00009e0c, 0x6d4000e2, 0x6d4000e2},
11842 +       {0x00009e14, 0x37b9625e, 0x37b9625e},
11843 +};
11844 +
11845  #endif /* INITVALS_9580_1P0_H */
11846 --- a/drivers/net/wireless/ath/ath9k/reg.h
11847 +++ b/drivers/net/wireless/ath/ath9k/reg.h
11848 @@ -809,6 +809,8 @@
11849  #define AR_SREV_REVISION_9462_21       3
11850  #define AR_SREV_VERSION_9565            0x2C0
11851  #define AR_SREV_REVISION_9565_10        0
11852 +#define AR_SREV_REVISION_9565_101       1
11853 +#define AR_SREV_REVISION_9565_11        2
11854  #define AR_SREV_VERSION_9550           0x400
11855
11856  #define AR_SREV_5416(_ah) \
11857 @@ -881,9 +883,6 @@
11858
11859  #define AR_SREV_9330(_ah) \
11860         (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9330))
11861 -#define AR_SREV_9330_10(_ah) \
11862 -       (AR_SREV_9330((_ah)) && \
11863 -        ((_ah)->hw_version.macRev == AR_SREV_REVISION_9330_10))
11864  #define AR_SREV_9330_11(_ah) \
11865         (AR_SREV_9330((_ah)) && \
11866          ((_ah)->hw_version.macRev == AR_SREV_REVISION_9330_11))
11867 @@ -927,10 +926,18 @@
11868
11869  #define AR_SREV_9565(_ah) \
11870         (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9565))
11871 -
11872  #define AR_SREV_9565_10(_ah) \
11873         (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9565) && \
11874          ((_ah)->hw_version.macRev == AR_SREV_REVISION_9565_10))
11875 +#define AR_SREV_9565_101(_ah) \
11876 +       (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9565) && \
11877 +        ((_ah)->hw_version.macRev == AR_SREV_REVISION_9565_101))
11878 +#define AR_SREV_9565_11(_ah) \
11879 +       (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9565) && \
11880 +        ((_ah)->hw_version.macRev == AR_SREV_REVISION_9565_11))
11881 +#define AR_SREV_9565_11_OR_LATER(_ah) \
11882 +       (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9565) && \
11883 +        ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9565_11))
11884
11885  #define AR_SREV_9550(_ah) \
11886         (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9550))
11887 --- a/drivers/net/wireless/ath/ath9k/ar9330_1p1_initvals.h
11888 +++ b/drivers/net/wireless/ath/ath9k/ar9330_1p1_initvals.h
11889 @@ -18,6 +18,10 @@
11890  #ifndef INITVALS_9330_1P1_H
11891  #define INITVALS_9330_1P1_H
11892
11893 +#define ar9331_1p1_baseband_core_txfir_coeff_japan_2484 ar9300_2p2_baseband_core_txfir_coeff_japan_2484
11894 +
11895 +#define ar9331_modes_high_power_tx_gain_1p1 ar9331_modes_lowest_ob_db_tx_gain_1p1
11896 +
11897  static const u32 ar9331_1p1_baseband_postamble[][5] = {
11898         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
11899         {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8005, 0xd00a8005},
11900 @@ -55,7 +59,7 @@ static const u32 ar9331_1p1_baseband_pos
11901         {0x0000a284, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
11902         {0x0000a288, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
11903         {0x0000a28c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
11904 -       {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
11905 +       {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00058d18, 0x00058d18},
11906         {0x0000a2d0, 0x00071982, 0x00071982, 0x00071982, 0x00071982},
11907         {0x0000a2d8, 0xf999a83a, 0xf999a83a, 0xf999a83a, 0xf999a83a},
11908         {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
11909 @@ -252,7 +256,7 @@ static const u32 ar9331_modes_low_ob_db_
11910         {0x0000a2e0, 0xffffcc84, 0xffffcc84, 0xffffcc84, 0xffffcc84},
11911         {0x0000a2e4, 0xfffff000, 0xfffff000, 0xfffff000, 0xfffff000},
11912         {0x0000a2e8, 0xfffe0000, 0xfffe0000, 0xfffe0000, 0xfffe0000},
11913 -       {0x0000a410, 0x000050d7, 0x000050d7, 0x000050d0, 0x000050d0},
11914 +       {0x0000a410, 0x000050d7, 0x000050d7, 0x000050d4, 0x000050d4},
11915         {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
11916         {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
11917         {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
11918 @@ -337,8 +341,6 @@ static const u32 ar9331_modes_low_ob_db_
11919         {0x00016284, 0x14d3f000, 0x14d3f000, 0x14d3f000, 0x14d3f000},
11920  };
11921
11922 -#define ar9331_1p1_baseband_core_txfir_coeff_japan_2484 ar9462_2p0_baseband_core_txfir_coeff_japan_2484
11923 -
11924  static const u32 ar9331_1p1_xtal_25M[][2] = {
11925         /* Addr      allmodes  */
11926         {0x00007038, 0x000002f8},
11927 @@ -373,17 +375,17 @@ static const u32 ar9331_1p1_radio_core[]
11928         {0x000160b4, 0x92480040},
11929         {0x000160c0, 0x006db6db},
11930         {0x000160c4, 0x0186db60},
11931 -       {0x000160c8, 0x6db4db6c},
11932 +       {0x000160c8, 0x6db6db6c},
11933         {0x000160cc, 0x6de6c300},
11934         {0x000160d0, 0x14500820},
11935         {0x00016100, 0x04cb0001},
11936         {0x00016104, 0xfff80015},
11937         {0x00016108, 0x00080010},
11938         {0x0001610c, 0x00170000},
11939 -       {0x00016140, 0x10800000},
11940 +       {0x00016140, 0x50804000},
11941         {0x00016144, 0x01884080},
11942         {0x00016148, 0x000080c0},
11943 -       {0x00016280, 0x01000015},
11944 +       {0x00016280, 0x01001015},
11945         {0x00016284, 0x14d20000},
11946         {0x00016288, 0x00318000},
11947         {0x0001628c, 0x50000000},
11948 @@ -622,12 +624,12 @@ static const u32 ar9331_1p1_baseband_cor
11949         {0x0000a370, 0x00000000},
11950         {0x0000a390, 0x00000001},
11951         {0x0000a394, 0x00000444},
11952 -       {0x0000a398, 0x001f0e0f},
11953 -       {0x0000a39c, 0x0075393f},
11954 -       {0x0000a3a0, 0xb79f6427},
11955 -       {0x0000a3a4, 0x00000000},
11956 -       {0x0000a3a8, 0xaaaaaaaa},
11957 -       {0x0000a3ac, 0x3c466478},
11958 +       {0x0000a398, 0x00000000},
11959 +       {0x0000a39c, 0x210d0401},
11960 +       {0x0000a3a0, 0xab9a7144},
11961 +       {0x0000a3a4, 0x00000011},
11962 +       {0x0000a3a8, 0x3c3c003d},
11963 +       {0x0000a3ac, 0x30310030},
11964         {0x0000a3c0, 0x20202020},
11965         {0x0000a3c4, 0x22222220},
11966         {0x0000a3c8, 0x20200020},
11967 @@ -686,100 +688,18 @@ static const u32 ar9331_1p1_baseband_cor
11968         {0x0000a7dc, 0x00000001},
11969  };
11970
11971 -static const u32 ar9331_modes_high_power_tx_gain_1p1[][5] = {
11972 +static const u32 ar9331_1p1_mac_postamble[][5] = {
11973         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
11974 -       {0x0000a2d8, 0x7999a83a, 0x7999a83a, 0x7999a83a, 0x7999a83a},
11975 -       {0x0000a2dc, 0xffff2a52, 0xffff2a52, 0xffff2a52, 0xffff2a52},
11976 -       {0x0000a2e0, 0xffffcc84, 0xffffcc84, 0xffffcc84, 0xffffcc84},
11977 -       {0x0000a2e4, 0xfffff000, 0xfffff000, 0xfffff000, 0xfffff000},
11978 -       {0x0000a2e8, 0xfffe0000, 0xfffe0000, 0xfffe0000, 0xfffe0000},
11979 -       {0x0000a410, 0x000050d7, 0x000050d7, 0x000050d0, 0x000050d0},
11980 -       {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
11981 -       {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
11982 -       {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
11983 -       {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
11984 -       {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
11985 -       {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
11986 -       {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
11987 -       {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
11988 -       {0x0000a520, 0x2f001f04, 0x2f001f04, 0x23000a00, 0x23000a00},
11989 -       {0x0000a524, 0x35001fc4, 0x35001fc4, 0x27000a02, 0x27000a02},
11990 -       {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2b000a04, 0x2b000a04},
11991 -       {0x0000a52c, 0x41023e85, 0x41023e85, 0x2d000a20, 0x2d000a20},
11992 -       {0x0000a530, 0x48023ec6, 0x48023ec6, 0x31000a22, 0x31000a22},
11993 -       {0x0000a534, 0x4d023f01, 0x4d023f01, 0x35000a24, 0x35000a24},
11994 -       {0x0000a538, 0x53023f4b, 0x53023f4b, 0x38000a43, 0x38000a43},
11995 -       {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x3b000e42, 0x3b000e42},
11996 -       {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x3f000e44, 0x3f000e44},
11997 -       {0x0000a544, 0x6502feca, 0x6502feca, 0x42000e64, 0x42000e64},
11998 -       {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x46000e66, 0x46000e66},
11999 -       {0x0000a54c, 0x7203feca, 0x7203feca, 0x4a000ea6, 0x4a000ea6},
12000 -       {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x4a000ea6, 0x4a000ea6},
12001 -       {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x4a000ea6, 0x4a000ea6},
12002 -       {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x4a000ea6, 0x4a000ea6},
12003 -       {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x4a000ea6, 0x4a000ea6},
12004 -       {0x0000a560, 0x900fff0b, 0x900fff0b, 0x4a000ea6, 0x4a000ea6},
12005 -       {0x0000a564, 0x960fffcb, 0x960fffcb, 0x4a000ea6, 0x4a000ea6},
12006 -       {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
12007 -       {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
12008 -       {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
12009 -       {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
12010 -       {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
12011 -       {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
12012 -       {0x0000a580, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
12013 -       {0x0000a584, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
12014 -       {0x0000a588, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
12015 -       {0x0000a58c, 0x11062202, 0x11062202, 0x0b000200, 0x0b000200},
12016 -       {0x0000a590, 0x17022e00, 0x17022e00, 0x0f000202, 0x0f000202},
12017 -       {0x0000a594, 0x1d000ec2, 0x1d000ec2, 0x11000400, 0x11000400},
12018 -       {0x0000a598, 0x25020ec0, 0x25020ec0, 0x15000402, 0x15000402},
12019 -       {0x0000a59c, 0x2b020ec3, 0x2b020ec3, 0x19000404, 0x19000404},
12020 -       {0x0000a5a0, 0x2f001f04, 0x2f001f04, 0x1b000603, 0x1b000603},
12021 -       {0x0000a5a4, 0x35001fc4, 0x35001fc4, 0x1f000a02, 0x1f000a02},
12022 -       {0x0000a5a8, 0x3c022f04, 0x3c022f04, 0x23000a04, 0x23000a04},
12023 -       {0x0000a5ac, 0x41023e85, 0x41023e85, 0x26000a20, 0x26000a20},
12024 -       {0x0000a5b0, 0x48023ec6, 0x48023ec6, 0x2a000e20, 0x2a000e20},
12025 -       {0x0000a5b4, 0x4d023f01, 0x4d023f01, 0x2e000e22, 0x2e000e22},
12026 -       {0x0000a5b8, 0x53023f4b, 0x53023f4b, 0x31000e24, 0x31000e24},
12027 -       {0x0000a5bc, 0x5a027f09, 0x5a027f09, 0x34001640, 0x34001640},
12028 -       {0x0000a5c0, 0x5f027fc9, 0x5f027fc9, 0x38001660, 0x38001660},
12029 -       {0x0000a5c4, 0x6502feca, 0x6502feca, 0x3b001861, 0x3b001861},
12030 -       {0x0000a5c8, 0x6b02ff4a, 0x6b02ff4a, 0x3e001a81, 0x3e001a81},
12031 -       {0x0000a5cc, 0x7203feca, 0x7203feca, 0x42001a83, 0x42001a83},
12032 -       {0x0000a5d0, 0x7703ff0b, 0x7703ff0b, 0x44001c84, 0x44001c84},
12033 -       {0x0000a5d4, 0x7d06ffcb, 0x7d06ffcb, 0x48001ce3, 0x48001ce3},
12034 -       {0x0000a5d8, 0x8407ff0b, 0x8407ff0b, 0x4c001ce5, 0x4c001ce5},
12035 -       {0x0000a5dc, 0x8907ffcb, 0x8907ffcb, 0x50001ce9, 0x50001ce9},
12036 -       {0x0000a5e0, 0x900fff0b, 0x900fff0b, 0x54001ceb, 0x54001ceb},
12037 -       {0x0000a5e4, 0x960fffcb, 0x960fffcb, 0x56001eec, 0x56001eec},
12038 -       {0x0000a5e8, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
12039 -       {0x0000a5ec, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
12040 -       {0x0000a5f0, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
12041 -       {0x0000a5f4, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
12042 -       {0x0000a5f8, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
12043 -       {0x0000a5fc, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
12044 -       {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
12045 -       {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
12046 -       {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
12047 -       {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
12048 -       {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
12049 -       {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000},
12050 -       {0x0000a618, 0x01404501, 0x01404501, 0x01404501, 0x01404501},
12051 -       {0x0000a61c, 0x02008802, 0x02008802, 0x02008802, 0x02008802},
12052 -       {0x0000a620, 0x0280c802, 0x0280c802, 0x0280c802, 0x0280c802},
12053 -       {0x0000a624, 0x03010a03, 0x03010a03, 0x03010a03, 0x03010a03},
12054 -       {0x0000a628, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
12055 -       {0x0000a62c, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
12056 -       {0x0000a630, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
12057 -       {0x0000a634, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
12058 -       {0x0000a638, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
12059 -       {0x0000a63c, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
12060 -       {0x00016044, 0x034922db, 0x034922db, 0x034922db, 0x034922db},
12061 -       {0x00016284, 0x14d3f000, 0x14d3f000, 0x14d3f000, 0x14d3f000},
12062 +       {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
12063 +       {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
12064 +       {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
12065 +       {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
12066 +       {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b},
12067 +       {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
12068 +       {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
12069 +       {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
12070  };
12071
12072 -#define ar9331_1p1_mac_postamble ar9300_2p2_mac_postamble
12073 -
12074  static const u32 ar9331_1p1_soc_preamble[][2] = {
12075         /* Addr      allmodes  */
12076         {0x00007020, 0x00000000},
12077 --- a/drivers/net/wireless/ath/ath9k/ar9330_1p2_initvals.h
12078 +++ b/drivers/net/wireless/ath/ath9k/ar9330_1p2_initvals.h
12079 @@ -18,6 +18,28 @@
12080  #ifndef INITVALS_9330_1P2_H
12081  #define INITVALS_9330_1P2_H
12082
12083 +#define ar9331_modes_high_power_tx_gain_1p2 ar9331_modes_high_ob_db_tx_gain_1p2
12084 +
12085 +#define ar9331_modes_low_ob_db_tx_gain_1p2 ar9331_modes_high_ob_db_tx_gain_1p2
12086 +
12087 +#define ar9331_modes_lowest_ob_db_tx_gain_1p2 ar9331_modes_high_ob_db_tx_gain_1p2
12088 +
12089 +#define ar9331_1p2_baseband_core_txfir_coeff_japan_2484 ar9331_1p1_baseband_core_txfir_coeff_japan_2484
12090 +
12091 +#define ar9331_1p2_xtal_25M ar9331_1p1_xtal_25M
12092 +
12093 +#define ar9331_1p2_xtal_40M ar9331_1p1_xtal_40M
12094 +
12095 +#define ar9331_1p2_soc_postamble ar9331_1p1_soc_postamble
12096 +
12097 +#define ar9331_1p2_mac_postamble ar9331_1p1_mac_postamble
12098 +
12099 +#define ar9331_1p2_soc_preamble ar9331_1p1_soc_preamble
12100 +
12101 +#define ar9331_1p2_mac_core ar9331_1p1_mac_core
12102 +
12103 +#define ar9331_common_wo_xlna_rx_gain_1p2 ar9331_common_wo_xlna_rx_gain_1p1
12104 +
12105  static const u32 ar9331_modes_high_ob_db_tx_gain_1p2[][5] = {
12106         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
12107         {0x0000a410, 0x000050d7, 0x000050d7, 0x000050d7, 0x000050d7},
12108 @@ -103,57 +125,6 @@ static const u32 ar9331_modes_high_ob_db
12109         {0x0000a63c, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
12110  };
12111
12112 -#define ar9331_modes_high_power_tx_gain_1p2 ar9331_modes_high_ob_db_tx_gain_1p2
12113 -
12114 -#define ar9331_modes_low_ob_db_tx_gain_1p2 ar9331_modes_high_power_tx_gain_1p2
12115 -
12116 -#define ar9331_modes_lowest_ob_db_tx_gain_1p2 ar9331_modes_low_ob_db_tx_gain_1p2
12117 -
12118 -static const u32 ar9331_1p2_baseband_postamble[][5] = {
12119 -       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
12120 -       {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8005, 0xd00a8005},
12121 -       {0x00009820, 0x206a002e, 0x206a002e, 0x206a002e, 0x206a002e},
12122 -       {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0},
12123 -       {0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881},
12124 -       {0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4},
12125 -       {0x00009830, 0x0000059c, 0x0000059c, 0x0000059c, 0x0000059c},
12126 -       {0x00009c00, 0x00000044, 0x00000044, 0x00000044, 0x00000044},
12127 -       {0x00009e00, 0x0372161e, 0x0372161e, 0x037216a4, 0x037216a4},
12128 -       {0x00009e04, 0x00182020, 0x00182020, 0x00182020, 0x00182020},
12129 -       {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2},
12130 -       {0x00009e10, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e},
12131 -       {0x00009e14, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e},
12132 -       {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
12133 -       {0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c},
12134 -       {0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce},
12135 -       {0x00009e2c, 0x0000001c, 0x0000001c, 0x00003221, 0x00003221},
12136 -       {0x00009e3c, 0xcf946222, 0xcf946222, 0xcf946222, 0xcf946222},
12137 -       {0x00009e44, 0x02321e27, 0x02321e27, 0x02282324, 0x02282324},
12138 -       {0x00009e48, 0x5030201a, 0x5030201a, 0x50302010, 0x50302010},
12139 -       {0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000},
12140 -       {0x0000a204, 0x00003fc0, 0x00003fc4, 0x00003fc4, 0x00003fc0},
12141 -       {0x0000a208, 0x00000104, 0x00000104, 0x00000004, 0x00000004},
12142 -       {0x0000a230, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b},
12143 -       {0x0000a234, 0x00000fff, 0x00000fff, 0x10000fff, 0x00000fff},
12144 -       {0x0000a238, 0xffb81018, 0xffb81018, 0xffb81018, 0xffb81018},
12145 -       {0x0000a250, 0x00000000, 0x00000000, 0x00000210, 0x00000108},
12146 -       {0x0000a254, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898},
12147 -       {0x0000a258, 0x02020002, 0x02020002, 0x02020002, 0x02020002},
12148 -       {0x0000a25c, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e},
12149 -       {0x0000a260, 0x3a021501, 0x3a021501, 0x3a021501, 0x3a021501},
12150 -       {0x0000a264, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e},
12151 -       {0x0000a280, 0x00000007, 0x00000007, 0x0000000b, 0x0000000b},
12152 -       {0x0000a284, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
12153 -       {0x0000a288, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
12154 -       {0x0000a28c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
12155 -       {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
12156 -       {0x0000a2d0, 0x00071981, 0x00071981, 0x00071981, 0x00071981},
12157 -       {0x0000a2d8, 0xf999a83a, 0xf999a83a, 0xf999a83a, 0xf999a83a},
12158 -       {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
12159 -       {0x0000ae04, 0x00802020, 0x00802020, 0x00802020, 0x00802020},
12160 -       {0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
12161 -};
12162 -
12163  static const u32 ar9331_1p2_radio_core[][2] = {
12164         /* Addr      allmodes  */
12165         {0x00016000, 0x36db6db6},
12166 @@ -219,24 +190,318 @@ static const u32 ar9331_1p2_radio_core[]
12167         {0x000163d4, 0x00000000},
12168  };
12169
12170 -#define ar9331_1p2_baseband_core_txfir_coeff_japan_2484 ar9331_1p1_baseband_core_txfir_coeff_japan_2484
12171 -
12172 -#define ar9331_1p2_xtal_25M ar9331_1p1_xtal_25M
12173 -
12174 -#define ar9331_1p2_xtal_40M ar9331_1p1_xtal_40M
12175 -
12176 -#define ar9331_1p2_baseband_core ar9331_1p1_baseband_core
12177 -
12178 -#define ar9331_1p2_soc_postamble ar9331_1p1_soc_postamble
12179 -
12180 -#define ar9331_1p2_mac_postamble ar9331_1p1_mac_postamble
12181 -
12182 -#define ar9331_1p2_soc_preamble ar9331_1p1_soc_preamble
12183 -
12184 -#define ar9331_1p2_mac_core ar9331_1p1_mac_core
12185 +static const u32 ar9331_1p2_baseband_core[][2] = {
12186 +       /* Addr      allmodes  */
12187 +       {0x00009800, 0xafe68e30},
12188 +       {0x00009804, 0xfd14e000},
12189 +       {0x00009808, 0x9c0a8f6b},
12190 +       {0x0000980c, 0x04800000},
12191 +       {0x00009814, 0x9280c00a},
12192 +       {0x00009818, 0x00000000},
12193 +       {0x0000981c, 0x00020028},
12194 +       {0x00009834, 0x5f3ca3de},
12195 +       {0x00009838, 0x0108ecff},
12196 +       {0x0000983c, 0x14750600},
12197 +       {0x00009880, 0x201fff00},
12198 +       {0x00009884, 0x00001042},
12199 +       {0x000098a4, 0x00200400},
12200 +       {0x000098b0, 0x32840bbe},
12201 +       {0x000098d0, 0x004b6a8e},
12202 +       {0x000098d4, 0x00000820},
12203 +       {0x000098dc, 0x00000000},
12204 +       {0x000098f0, 0x00000000},
12205 +       {0x000098f4, 0x00000000},
12206 +       {0x00009c04, 0x00000000},
12207 +       {0x00009c08, 0x03200000},
12208 +       {0x00009c0c, 0x00000000},
12209 +       {0x00009c10, 0x00000000},
12210 +       {0x00009c14, 0x00046384},
12211 +       {0x00009c18, 0x05b6b440},
12212 +       {0x00009c1c, 0x00b6b440},
12213 +       {0x00009d00, 0xc080a333},
12214 +       {0x00009d04, 0x40206c10},
12215 +       {0x00009d08, 0x009c4060},
12216 +       {0x00009d0c, 0x1883800a},
12217 +       {0x00009d10, 0x01834061},
12218 +       {0x00009d14, 0x00c00400},
12219 +       {0x00009d18, 0x00000000},
12220 +       {0x00009e08, 0x0038233c},
12221 +       {0x00009e24, 0x9927b515},
12222 +       {0x00009e28, 0x12ef0200},
12223 +       {0x00009e30, 0x06336f77},
12224 +       {0x00009e34, 0x6af6532f},
12225 +       {0x00009e38, 0x0cc80c00},
12226 +       {0x00009e40, 0x0d261820},
12227 +       {0x00009e4c, 0x00001004},
12228 +       {0x00009e50, 0x00ff03f1},
12229 +       {0x00009fc0, 0x803e4788},
12230 +       {0x00009fc4, 0x0001efb5},
12231 +       {0x00009fcc, 0x40000014},
12232 +       {0x0000a20c, 0x00000000},
12233 +       {0x0000a220, 0x00000000},
12234 +       {0x0000a224, 0x00000000},
12235 +       {0x0000a228, 0x10002310},
12236 +       {0x0000a23c, 0x00000000},
12237 +       {0x0000a244, 0x0c000000},
12238 +       {0x0000a2a0, 0x00000001},
12239 +       {0x0000a2c0, 0x00000001},
12240 +       {0x0000a2c8, 0x00000000},
12241 +       {0x0000a2cc, 0x18c43433},
12242 +       {0x0000a2d4, 0x00000000},
12243 +       {0x0000a2dc, 0x00000000},
12244 +       {0x0000a2e0, 0x00000000},
12245 +       {0x0000a2e4, 0x00000000},
12246 +       {0x0000a2e8, 0x00000000},
12247 +       {0x0000a2ec, 0x00000000},
12248 +       {0x0000a2f0, 0x00000000},
12249 +       {0x0000a2f4, 0x00000000},
12250 +       {0x0000a2f8, 0x00000000},
12251 +       {0x0000a344, 0x00000000},
12252 +       {0x0000a34c, 0x00000000},
12253 +       {0x0000a350, 0x0000a000},
12254 +       {0x0000a364, 0x00000000},
12255 +       {0x0000a370, 0x00000000},
12256 +       {0x0000a390, 0x00000001},
12257 +       {0x0000a394, 0x00000444},
12258 +       {0x0000a398, 0x001f0e0f},
12259 +       {0x0000a39c, 0x0075393f},
12260 +       {0x0000a3a0, 0xb79f6427},
12261 +       {0x0000a3a4, 0x00000000},
12262 +       {0x0000a3a8, 0xaaaaaaaa},
12263 +       {0x0000a3ac, 0x3c466478},
12264 +       {0x0000a3c0, 0x20202020},
12265 +       {0x0000a3c4, 0x22222220},
12266 +       {0x0000a3c8, 0x20200020},
12267 +       {0x0000a3cc, 0x20202020},
12268 +       {0x0000a3d0, 0x20202020},
12269 +       {0x0000a3d4, 0x20202020},
12270 +       {0x0000a3d8, 0x20202020},
12271 +       {0x0000a3dc, 0x20202020},
12272 +       {0x0000a3e0, 0x20202020},
12273 +       {0x0000a3e4, 0x20202020},
12274 +       {0x0000a3e8, 0x20202020},
12275 +       {0x0000a3ec, 0x20202020},
12276 +       {0x0000a3f0, 0x00000000},
12277 +       {0x0000a3f4, 0x00000006},
12278 +       {0x0000a3f8, 0x0cdbd380},
12279 +       {0x0000a3fc, 0x000f0f01},
12280 +       {0x0000a400, 0x8fa91f01},
12281 +       {0x0000a404, 0x00000000},
12282 +       {0x0000a408, 0x0e79e5c6},
12283 +       {0x0000a40c, 0x00820820},
12284 +       {0x0000a414, 0x1ce739ce},
12285 +       {0x0000a418, 0x2d001dce},
12286 +       {0x0000a41c, 0x1ce739ce},
12287 +       {0x0000a420, 0x000001ce},
12288 +       {0x0000a424, 0x1ce739ce},
12289 +       {0x0000a428, 0x000001ce},
12290 +       {0x0000a42c, 0x1ce739ce},
12291 +       {0x0000a430, 0x1ce739ce},
12292 +       {0x0000a434, 0x00000000},
12293 +       {0x0000a438, 0x00001801},
12294 +       {0x0000a43c, 0x00000000},
12295 +       {0x0000a440, 0x00000000},
12296 +       {0x0000a444, 0x00000000},
12297 +       {0x0000a448, 0x04000000},
12298 +       {0x0000a44c, 0x00000001},
12299 +       {0x0000a450, 0x00010000},
12300 +       {0x0000a458, 0x00000000},
12301 +       {0x0000a640, 0x00000000},
12302 +       {0x0000a644, 0x3fad9d74},
12303 +       {0x0000a648, 0x0048060a},
12304 +       {0x0000a64c, 0x00003c37},
12305 +       {0x0000a670, 0x03020100},
12306 +       {0x0000a674, 0x09080504},
12307 +       {0x0000a678, 0x0d0c0b0a},
12308 +       {0x0000a67c, 0x13121110},
12309 +       {0x0000a680, 0x31301514},
12310 +       {0x0000a684, 0x35343332},
12311 +       {0x0000a688, 0x00000036},
12312 +       {0x0000a690, 0x00000838},
12313 +       {0x0000a7c0, 0x00000000},
12314 +       {0x0000a7c4, 0xfffffffc},
12315 +       {0x0000a7c8, 0x00000000},
12316 +       {0x0000a7cc, 0x00000000},
12317 +       {0x0000a7d0, 0x00000000},
12318 +       {0x0000a7d4, 0x00000004},
12319 +       {0x0000a7dc, 0x00000001},
12320 +};
12321
12322 -#define ar9331_common_wo_xlna_rx_gain_1p2 ar9331_common_wo_xlna_rx_gain_1p1
12323 +static const u32 ar9331_1p2_baseband_postamble[][5] = {
12324 +       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
12325 +       {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8005, 0xd00a8005},
12326 +       {0x00009820, 0x206a002e, 0x206a002e, 0x206a002e, 0x206a002e},
12327 +       {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0},
12328 +       {0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881},
12329 +       {0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4},
12330 +       {0x00009830, 0x0000059c, 0x0000059c, 0x0000059c, 0x0000059c},
12331 +       {0x00009c00, 0x00000044, 0x00000044, 0x00000044, 0x00000044},
12332 +       {0x00009e00, 0x0372161e, 0x0372161e, 0x037216a4, 0x037216a4},
12333 +       {0x00009e04, 0x00182020, 0x00182020, 0x00182020, 0x00182020},
12334 +       {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2},
12335 +       {0x00009e10, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e},
12336 +       {0x00009e14, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e},
12337 +       {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
12338 +       {0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c},
12339 +       {0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce},
12340 +       {0x00009e2c, 0x0000001c, 0x0000001c, 0x00003221, 0x00003221},
12341 +       {0x00009e3c, 0xcf946222, 0xcf946222, 0xcf946222, 0xcf946222},
12342 +       {0x00009e44, 0x02321e27, 0x02321e27, 0x02282324, 0x02282324},
12343 +       {0x00009e48, 0x5030201a, 0x5030201a, 0x50302010, 0x50302010},
12344 +       {0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000},
12345 +       {0x0000a204, 0x00003fc0, 0x00003fc4, 0x00003fc4, 0x00003fc0},
12346 +       {0x0000a208, 0x00000104, 0x00000104, 0x00000004, 0x00000004},
12347 +       {0x0000a230, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b},
12348 +       {0x0000a234, 0x00000fff, 0x00000fff, 0x10000fff, 0x00000fff},
12349 +       {0x0000a238, 0xffb81018, 0xffb81018, 0xffb81018, 0xffb81018},
12350 +       {0x0000a250, 0x00000000, 0x00000000, 0x00000210, 0x00000108},
12351 +       {0x0000a254, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898},
12352 +       {0x0000a258, 0x02020002, 0x02020002, 0x02020002, 0x02020002},
12353 +       {0x0000a25c, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e},
12354 +       {0x0000a260, 0x3a021501, 0x3a021501, 0x3a021501, 0x3a021501},
12355 +       {0x0000a264, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e},
12356 +       {0x0000a280, 0x00000007, 0x00000007, 0x0000000b, 0x0000000b},
12357 +       {0x0000a284, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
12358 +       {0x0000a288, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
12359 +       {0x0000a28c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
12360 +       {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
12361 +       {0x0000a2d0, 0x00071981, 0x00071981, 0x00071981, 0x00071981},
12362 +       {0x0000a2d8, 0xf999a83a, 0xf999a83a, 0xf999a83a, 0xf999a83a},
12363 +       {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
12364 +       {0x0000ae04, 0x00802020, 0x00802020, 0x00802020, 0x00802020},
12365 +       {0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
12366 +};
12367
12368 -#define ar9331_common_rx_gain_1p2 ar9485_common_rx_gain_1_1
12369 +static const u32 ar9331_common_rx_gain_1p2[][2] = {
12370 +       /* Addr      allmodes  */
12371 +       {0x0000a000, 0x00010000},
12372 +       {0x0000a004, 0x00030002},
12373 +       {0x0000a008, 0x00050004},
12374 +       {0x0000a00c, 0x00810080},
12375 +       {0x0000a010, 0x01800082},
12376 +       {0x0000a014, 0x01820181},
12377 +       {0x0000a018, 0x01840183},
12378 +       {0x0000a01c, 0x01880185},
12379 +       {0x0000a020, 0x018a0189},
12380 +       {0x0000a024, 0x02850284},
12381 +       {0x0000a028, 0x02890288},
12382 +       {0x0000a02c, 0x03850384},
12383 +       {0x0000a030, 0x03890388},
12384 +       {0x0000a034, 0x038b038a},
12385 +       {0x0000a038, 0x038d038c},
12386 +       {0x0000a03c, 0x03910390},
12387 +       {0x0000a040, 0x03930392},
12388 +       {0x0000a044, 0x03950394},
12389 +       {0x0000a048, 0x00000396},
12390 +       {0x0000a04c, 0x00000000},
12391 +       {0x0000a050, 0x00000000},
12392 +       {0x0000a054, 0x00000000},
12393 +       {0x0000a058, 0x00000000},
12394 +       {0x0000a05c, 0x00000000},
12395 +       {0x0000a060, 0x00000000},
12396 +       {0x0000a064, 0x00000000},
12397 +       {0x0000a068, 0x00000000},
12398 +       {0x0000a06c, 0x00000000},
12399 +       {0x0000a070, 0x00000000},
12400 +       {0x0000a074, 0x00000000},
12401 +       {0x0000a078, 0x00000000},
12402 +       {0x0000a07c, 0x00000000},
12403 +       {0x0000a080, 0x28282828},
12404 +       {0x0000a084, 0x28282828},
12405 +       {0x0000a088, 0x28282828},
12406 +       {0x0000a08c, 0x28282828},
12407 +       {0x0000a090, 0x28282828},
12408 +       {0x0000a094, 0x21212128},
12409 +       {0x0000a098, 0x171c1c1c},
12410 +       {0x0000a09c, 0x02020212},
12411 +       {0x0000a0a0, 0x00000202},
12412 +       {0x0000a0a4, 0x00000000},
12413 +       {0x0000a0a8, 0x00000000},
12414 +       {0x0000a0ac, 0x00000000},
12415 +       {0x0000a0b0, 0x00000000},
12416 +       {0x0000a0b4, 0x00000000},
12417 +       {0x0000a0b8, 0x00000000},
12418 +       {0x0000a0bc, 0x00000000},
12419 +       {0x0000a0c0, 0x001f0000},
12420 +       {0x0000a0c4, 0x111f1100},
12421 +       {0x0000a0c8, 0x111d111e},
12422 +       {0x0000a0cc, 0x111b111c},
12423 +       {0x0000a0d0, 0x22032204},
12424 +       {0x0000a0d4, 0x22012202},
12425 +       {0x0000a0d8, 0x221f2200},
12426 +       {0x0000a0dc, 0x221d221e},
12427 +       {0x0000a0e0, 0x33013302},
12428 +       {0x0000a0e4, 0x331f3300},
12429 +       {0x0000a0e8, 0x4402331e},
12430 +       {0x0000a0ec, 0x44004401},
12431 +       {0x0000a0f0, 0x441e441f},
12432 +       {0x0000a0f4, 0x55015502},
12433 +       {0x0000a0f8, 0x551f5500},
12434 +       {0x0000a0fc, 0x6602551e},
12435 +       {0x0000a100, 0x66006601},
12436 +       {0x0000a104, 0x661e661f},
12437 +       {0x0000a108, 0x7703661d},
12438 +       {0x0000a10c, 0x77017702},
12439 +       {0x0000a110, 0x00007700},
12440 +       {0x0000a114, 0x00000000},
12441 +       {0x0000a118, 0x00000000},
12442 +       {0x0000a11c, 0x00000000},
12443 +       {0x0000a120, 0x00000000},
12444 +       {0x0000a124, 0x00000000},
12445 +       {0x0000a128, 0x00000000},
12446 +       {0x0000a12c, 0x00000000},
12447 +       {0x0000a130, 0x00000000},
12448 +       {0x0000a134, 0x00000000},
12449 +       {0x0000a138, 0x00000000},
12450 +       {0x0000a13c, 0x00000000},
12451 +       {0x0000a140, 0x001f0000},
12452 +       {0x0000a144, 0x111f1100},
12453 +       {0x0000a148, 0x111d111e},
12454 +       {0x0000a14c, 0x111b111c},
12455 +       {0x0000a150, 0x22032204},
12456 +       {0x0000a154, 0x22012202},
12457 +       {0x0000a158, 0x221f2200},
12458 +       {0x0000a15c, 0x221d221e},
12459 +       {0x0000a160, 0x33013302},
12460 +       {0x0000a164, 0x331f3300},
12461 +       {0x0000a168, 0x4402331e},
12462 +       {0x0000a16c, 0x44004401},
12463 +       {0x0000a170, 0x441e441f},
12464 +       {0x0000a174, 0x55015502},
12465 +       {0x0000a178, 0x551f5500},
12466 +       {0x0000a17c, 0x6602551e},
12467 +       {0x0000a180, 0x66006601},
12468 +       {0x0000a184, 0x661e661f},
12469 +       {0x0000a188, 0x7703661d},
12470 +       {0x0000a18c, 0x77017702},
12471 +       {0x0000a190, 0x00007700},
12472 +       {0x0000a194, 0x00000000},
12473 +       {0x0000a198, 0x00000000},
12474 +       {0x0000a19c, 0x00000000},
12475 +       {0x0000a1a0, 0x00000000},
12476 +       {0x0000a1a4, 0x00000000},
12477 +       {0x0000a1a8, 0x00000000},
12478 +       {0x0000a1ac, 0x00000000},
12479 +       {0x0000a1b0, 0x00000000},
12480 +       {0x0000a1b4, 0x00000000},
12481 +       {0x0000a1b8, 0x00000000},
12482 +       {0x0000a1bc, 0x00000000},
12483 +       {0x0000a1c0, 0x00000000},
12484 +       {0x0000a1c4, 0x00000000},
12485 +       {0x0000a1c8, 0x00000000},
12486 +       {0x0000a1cc, 0x00000000},
12487 +       {0x0000a1d0, 0x00000000},
12488 +       {0x0000a1d4, 0x00000000},
12489 +       {0x0000a1d8, 0x00000000},
12490 +       {0x0000a1dc, 0x00000000},
12491 +       {0x0000a1e0, 0x00000000},
12492 +       {0x0000a1e4, 0x00000000},
12493 +       {0x0000a1e8, 0x00000000},
12494 +       {0x0000a1ec, 0x00000000},
12495 +       {0x0000a1f0, 0x00000396},
12496 +       {0x0000a1f4, 0x00000396},
12497 +       {0x0000a1f8, 0x00000396},
12498 +       {0x0000a1fc, 0x00000296},
12499 +};
12500
12501  #endif /* INITVALS_9330_1P2_H */
12502 --- a/drivers/net/wireless/ath/ath9k/ar955x_1p0_initvals.h
12503 +++ b/drivers/net/wireless/ath/ath9k/ar955x_1p0_initvals.h
12504 @@ -20,6 +20,14 @@
12505
12506  /* AR955X 1.0 */
12507
12508 +#define ar955x_1p0_soc_postamble ar9300_2p2_soc_postamble
12509 +
12510 +#define ar955x_1p0_common_rx_gain_table ar9300Common_rx_gain_table_2p2
12511 +
12512 +#define ar955x_1p0_common_wo_xlna_rx_gain_table ar9300Common_wo_xlna_rx_gain_table_2p2
12513 +
12514 +#define ar955x_1p0_baseband_core_txfir_coeff_japan_2484 ar9300_2p2_baseband_core_txfir_coeff_japan_2484
12515 +
12516  static const u32 ar955x_1p0_radio_postamble[][5] = {
12517         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
12518         {0x00016098, 0xd2dd5554, 0xd2dd5554, 0xd28b3330, 0xd28b3330},
12519 @@ -37,13 +45,6 @@ static const u32 ar955x_1p0_radio_postam
12520         {0x00016940, 0x10804008, 0x10804008, 0x10804008, 0x10804008},
12521  };
12522
12523 -static const u32 ar955x_1p0_baseband_core_txfir_coeff_japan_2484[][2] = {
12524 -       /* Addr      allmodes  */
12525 -       {0x0000a398, 0x00000000},
12526 -       {0x0000a39c, 0x6f7f0301},
12527 -       {0x0000a3a0, 0xca9228ee},
12528 -};
12529 -
12530  static const u32 ar955x_1p0_baseband_postamble[][5] = {
12531         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
12532         {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a8011},
12533 @@ -473,266 +474,6 @@ static const u32 ar955x_1p0_mac_core[][2
12534         {0x000083d0, 0x8c7901ff},
12535  };
12536
12537 -static const u32 ar955x_1p0_common_rx_gain_table[][2] = {
12538 -       /* Addr      allmodes  */
12539 -       {0x0000a000, 0x00010000},
12540 -       {0x0000a004, 0x00030002},
12541 -       {0x0000a008, 0x00050004},
12542 -       {0x0000a00c, 0x00810080},
12543 -       {0x0000a010, 0x00830082},
12544 -       {0x0000a014, 0x01810180},
12545 -       {0x0000a018, 0x01830182},
12546 -       {0x0000a01c, 0x01850184},
12547 -       {0x0000a020, 0x01890188},
12548 -       {0x0000a024, 0x018b018a},
12549 -       {0x0000a028, 0x018d018c},
12550 -       {0x0000a02c, 0x01910190},
12551 -       {0x0000a030, 0x01930192},
12552 -       {0x0000a034, 0x01950194},
12553 -       {0x0000a038, 0x038a0196},
12554 -       {0x0000a03c, 0x038c038b},
12555 -       {0x0000a040, 0x0390038d},
12556 -       {0x0000a044, 0x03920391},
12557 -       {0x0000a048, 0x03940393},
12558 -       {0x0000a04c, 0x03960395},
12559 -       {0x0000a050, 0x00000000},
12560 -       {0x0000a054, 0x00000000},
12561 -       {0x0000a058, 0x00000000},
12562 -       {0x0000a05c, 0x00000000},
12563 -       {0x0000a060, 0x00000000},
12564 -       {0x0000a064, 0x00000000},
12565 -       {0x0000a068, 0x00000000},
12566 -       {0x0000a06c, 0x00000000},
12567 -       {0x0000a070, 0x00000000},
12568 -       {0x0000a074, 0x00000000},
12569 -       {0x0000a078, 0x00000000},
12570 -       {0x0000a07c, 0x00000000},
12571 -       {0x0000a080, 0x22222229},
12572 -       {0x0000a084, 0x1d1d1d1d},
12573 -       {0x0000a088, 0x1d1d1d1d},
12574 -       {0x0000a08c, 0x1d1d1d1d},
12575 -       {0x0000a090, 0x171d1d1d},
12576 -       {0x0000a094, 0x11111717},
12577 -       {0x0000a098, 0x00030311},
12578 -       {0x0000a09c, 0x00000000},
12579 -       {0x0000a0a0, 0x00000000},
12580 -       {0x0000a0a4, 0x00000000},
12581 -       {0x0000a0a8, 0x00000000},
12582 -       {0x0000a0ac, 0x00000000},
12583 -       {0x0000a0b0, 0x00000000},
12584 -       {0x0000a0b4, 0x00000000},
12585 -       {0x0000a0b8, 0x00000000},
12586 -       {0x0000a0bc, 0x00000000},
12587 -       {0x0000a0c0, 0x001f0000},
12588 -       {0x0000a0c4, 0x01000101},
12589 -       {0x0000a0c8, 0x011e011f},
12590 -       {0x0000a0cc, 0x011c011d},
12591 -       {0x0000a0d0, 0x02030204},
12592 -       {0x0000a0d4, 0x02010202},
12593 -       {0x0000a0d8, 0x021f0200},
12594 -       {0x0000a0dc, 0x0302021e},
12595 -       {0x0000a0e0, 0x03000301},
12596 -       {0x0000a0e4, 0x031e031f},
12597 -       {0x0000a0e8, 0x0402031d},
12598 -       {0x0000a0ec, 0x04000401},
12599 -       {0x0000a0f0, 0x041e041f},
12600 -       {0x0000a0f4, 0x0502041d},
12601 -       {0x0000a0f8, 0x05000501},
12602 -       {0x0000a0fc, 0x051e051f},
12603 -       {0x0000a100, 0x06010602},
12604 -       {0x0000a104, 0x061f0600},
12605 -       {0x0000a108, 0x061d061e},
12606 -       {0x0000a10c, 0x07020703},
12607 -       {0x0000a110, 0x07000701},
12608 -       {0x0000a114, 0x00000000},
12609 -       {0x0000a118, 0x00000000},
12610 -       {0x0000a11c, 0x00000000},
12611 -       {0x0000a120, 0x00000000},
12612 -       {0x0000a124, 0x00000000},
12613 -       {0x0000a128, 0x00000000},
12614 -       {0x0000a12c, 0x00000000},
12615 -       {0x0000a130, 0x00000000},
12616 -       {0x0000a134, 0x00000000},
12617 -       {0x0000a138, 0x00000000},
12618 -       {0x0000a13c, 0x00000000},
12619 -       {0x0000a140, 0x001f0000},
12620 -       {0x0000a144, 0x01000101},
12621 -       {0x0000a148, 0x011e011f},
12622 -       {0x0000a14c, 0x011c011d},
12623 -       {0x0000a150, 0x02030204},
12624 -       {0x0000a154, 0x02010202},
12625 -       {0x0000a158, 0x021f0200},
12626 -       {0x0000a15c, 0x0302021e},
12627 -       {0x0000a160, 0x03000301},
12628 -       {0x0000a164, 0x031e031f},
12629 -       {0x0000a168, 0x0402031d},
12630 -       {0x0000a16c, 0x04000401},
12631 -       {0x0000a170, 0x041e041f},
12632 -       {0x0000a174, 0x0502041d},
12633 -       {0x0000a178, 0x05000501},
12634 -       {0x0000a17c, 0x051e051f},
12635 -       {0x0000a180, 0x06010602},
12636 -       {0x0000a184, 0x061f0600},
12637 -       {0x0000a188, 0x061d061e},
12638 -       {0x0000a18c, 0x07020703},
12639 -       {0x0000a190, 0x07000701},
12640 -       {0x0000a194, 0x00000000},
12641 -       {0x0000a198, 0x00000000},
12642 -       {0x0000a19c, 0x00000000},
12643 -       {0x0000a1a0, 0x00000000},
12644 -       {0x0000a1a4, 0x00000000},
12645 -       {0x0000a1a8, 0x00000000},
12646 -       {0x0000a1ac, 0x00000000},
12647 -       {0x0000a1b0, 0x00000000},
12648 -       {0x0000a1b4, 0x00000000},
12649 -       {0x0000a1b8, 0x00000000},
12650 -       {0x0000a1bc, 0x00000000},
12651 -       {0x0000a1c0, 0x00000000},
12652 -       {0x0000a1c4, 0x00000000},
12653 -       {0x0000a1c8, 0x00000000},
12654 -       {0x0000a1cc, 0x00000000},
12655 -       {0x0000a1d0, 0x00000000},
12656 -       {0x0000a1d4, 0x00000000},
12657 -       {0x0000a1d8, 0x00000000},
12658 -       {0x0000a1dc, 0x00000000},
12659 -       {0x0000a1e0, 0x00000000},
12660 -       {0x0000a1e4, 0x00000000},
12661 -       {0x0000a1e8, 0x00000000},
12662 -       {0x0000a1ec, 0x00000000},
12663 -       {0x0000a1f0, 0x00000396},
12664 -       {0x0000a1f4, 0x00000396},
12665 -       {0x0000a1f8, 0x00000396},
12666 -       {0x0000a1fc, 0x00000196},
12667 -       {0x0000b000, 0x00010000},
12668 -       {0x0000b004, 0x00030002},
12669 -       {0x0000b008, 0x00050004},
12670 -       {0x0000b00c, 0x00810080},
12671 -       {0x0000b010, 0x00830082},
12672 -       {0x0000b014, 0x01810180},
12673 -       {0x0000b018, 0x01830182},
12674 -       {0x0000b01c, 0x01850184},
12675 -       {0x0000b020, 0x02810280},
12676 -       {0x0000b024, 0x02830282},
12677 -       {0x0000b028, 0x02850284},
12678 -       {0x0000b02c, 0x02890288},
12679 -       {0x0000b030, 0x028b028a},
12680 -       {0x0000b034, 0x0388028c},
12681 -       {0x0000b038, 0x038a0389},
12682 -       {0x0000b03c, 0x038c038b},
12683 -       {0x0000b040, 0x0390038d},
12684 -       {0x0000b044, 0x03920391},
12685 -       {0x0000b048, 0x03940393},
12686 -       {0x0000b04c, 0x03960395},
12687 -       {0x0000b050, 0x00000000},
12688 -       {0x0000b054, 0x00000000},
12689 -       {0x0000b058, 0x00000000},
12690 -       {0x0000b05c, 0x00000000},
12691 -       {0x0000b060, 0x00000000},
12692 -       {0x0000b064, 0x00000000},
12693 -       {0x0000b068, 0x00000000},
12694 -       {0x0000b06c, 0x00000000},
12695 -       {0x0000b070, 0x00000000},
12696 -       {0x0000b074, 0x00000000},
12697 -       {0x0000b078, 0x00000000},
12698 -       {0x0000b07c, 0x00000000},
12699 -       {0x0000b080, 0x23232323},
12700 -       {0x0000b084, 0x21232323},
12701 -       {0x0000b088, 0x19191c1e},
12702 -       {0x0000b08c, 0x12141417},
12703 -       {0x0000b090, 0x07070e0e},
12704 -       {0x0000b094, 0x03030305},
12705 -       {0x0000b098, 0x00000003},
12706 -       {0x0000b09c, 0x00000000},
12707 -       {0x0000b0a0, 0x00000000},
12708 -       {0x0000b0a4, 0x00000000},
12709 -       {0x0000b0a8, 0x00000000},
12710 -       {0x0000b0ac, 0x00000000},
12711 -       {0x0000b0b0, 0x00000000},
12712 -       {0x0000b0b4, 0x00000000},
12713 -       {0x0000b0b8, 0x00000000},
12714 -       {0x0000b0bc, 0x00000000},
12715 -       {0x0000b0c0, 0x003f0020},
12716 -       {0x0000b0c4, 0x00400041},
12717 -       {0x0000b0c8, 0x0140005f},
12718 -       {0x0000b0cc, 0x0160015f},
12719 -       {0x0000b0d0, 0x017e017f},
12720 -       {0x0000b0d4, 0x02410242},
12721 -       {0x0000b0d8, 0x025f0240},
12722 -       {0x0000b0dc, 0x027f0260},
12723 -       {0x0000b0e0, 0x0341027e},
12724 -       {0x0000b0e4, 0x035f0340},
12725 -       {0x0000b0e8, 0x037f0360},
12726 -       {0x0000b0ec, 0x04400441},
12727 -       {0x0000b0f0, 0x0460045f},
12728 -       {0x0000b0f4, 0x0541047f},
12729 -       {0x0000b0f8, 0x055f0540},
12730 -       {0x0000b0fc, 0x057f0560},
12731 -       {0x0000b100, 0x06400641},
12732 -       {0x0000b104, 0x0660065f},
12733 -       {0x0000b108, 0x067e067f},
12734 -       {0x0000b10c, 0x07410742},
12735 -       {0x0000b110, 0x075f0740},
12736 -       {0x0000b114, 0x077f0760},
12737 -       {0x0000b118, 0x07800781},
12738 -       {0x0000b11c, 0x07a0079f},
12739 -       {0x0000b120, 0x07c107bf},
12740 -       {0x0000b124, 0x000007c0},
12741 -       {0x0000b128, 0x00000000},
12742 -       {0x0000b12c, 0x00000000},
12743 -       {0x0000b130, 0x00000000},
12744 -       {0x0000b134, 0x00000000},
12745 -       {0x0000b138, 0x00000000},
12746 -       {0x0000b13c, 0x00000000},
12747 -       {0x0000b140, 0x003f0020},
12748 -       {0x0000b144, 0x00400041},
12749 -       {0x0000b148, 0x0140005f},
12750 -       {0x0000b14c, 0x0160015f},
12751 -       {0x0000b150, 0x017e017f},
12752 -       {0x0000b154, 0x02410242},
12753 -       {0x0000b158, 0x025f0240},
12754 -       {0x0000b15c, 0x027f0260},
12755 -       {0x0000b160, 0x0341027e},
12756 -       {0x0000b164, 0x035f0340},
12757 -       {0x0000b168, 0x037f0360},
12758 -       {0x0000b16c, 0x04400441},
12759 -       {0x0000b170, 0x0460045f},
12760 -       {0x0000b174, 0x0541047f},
12761 -       {0x0000b178, 0x055f0540},
12762 -       {0x0000b17c, 0x057f0560},
12763 -       {0x0000b180, 0x06400641},
12764 -       {0x0000b184, 0x0660065f},
12765 -       {0x0000b188, 0x067e067f},
12766 -       {0x0000b18c, 0x07410742},
12767 -       {0x0000b190, 0x075f0740},
12768 -       {0x0000b194, 0x077f0760},
12769 -       {0x0000b198, 0x07800781},
12770 -       {0x0000b19c, 0x07a0079f},
12771 -       {0x0000b1a0, 0x07c107bf},
12772 -       {0x0000b1a4, 0x000007c0},
12773 -       {0x0000b1a8, 0x00000000},
12774 -       {0x0000b1ac, 0x00000000},
12775 -       {0x0000b1b0, 0x00000000},
12776 -       {0x0000b1b4, 0x00000000},
12777 -       {0x0000b1b8, 0x00000000},
12778 -       {0x0000b1bc, 0x00000000},
12779 -       {0x0000b1c0, 0x00000000},
12780 -       {0x0000b1c4, 0x00000000},
12781 -       {0x0000b1c8, 0x00000000},
12782 -       {0x0000b1cc, 0x00000000},
12783 -       {0x0000b1d0, 0x00000000},
12784 -       {0x0000b1d4, 0x00000000},
12785 -       {0x0000b1d8, 0x00000000},
12786 -       {0x0000b1dc, 0x00000000},
12787 -       {0x0000b1e0, 0x00000000},
12788 -       {0x0000b1e4, 0x00000000},
12789 -       {0x0000b1e8, 0x00000000},
12790 -       {0x0000b1ec, 0x00000000},
12791 -       {0x0000b1f0, 0x00000396},
12792 -       {0x0000b1f4, 0x00000396},
12793 -       {0x0000b1f8, 0x00000396},
12794 -       {0x0000b1fc, 0x00000196},
12795 -};
12796 -
12797  static const u32 ar955x_1p0_baseband_core[][2] = {
12798         /* Addr      allmodes  */
12799         {0x00009800, 0xafe68e30},
12800 @@ -891,266 +632,6 @@ static const u32 ar955x_1p0_baseband_cor
12801         {0x0000c420, 0x00000000},
12802  };
12803
12804 -static const u32 ar955x_1p0_common_wo_xlna_rx_gain_table[][2] = {
12805 -       /* Addr      allmodes  */
12806 -       {0x0000a000, 0x00010000},
12807 -       {0x0000a004, 0x00030002},
12808 -       {0x0000a008, 0x00050004},
12809 -       {0x0000a00c, 0x00810080},
12810 -       {0x0000a010, 0x00830082},
12811 -       {0x0000a014, 0x01810180},
12812 -       {0x0000a018, 0x01830182},
12813 -       {0x0000a01c, 0x01850184},
12814 -       {0x0000a020, 0x01890188},
12815 -       {0x0000a024, 0x018b018a},
12816 -       {0x0000a028, 0x018d018c},
12817 -       {0x0000a02c, 0x03820190},
12818 -       {0x0000a030, 0x03840383},
12819 -       {0x0000a034, 0x03880385},
12820 -       {0x0000a038, 0x038a0389},
12821 -       {0x0000a03c, 0x038c038b},
12822 -       {0x0000a040, 0x0390038d},
12823 -       {0x0000a044, 0x03920391},
12824 -       {0x0000a048, 0x03940393},
12825 -       {0x0000a04c, 0x03960395},
12826 -       {0x0000a050, 0x00000000},
12827 -       {0x0000a054, 0x00000000},
12828 -       {0x0000a058, 0x00000000},
12829 -       {0x0000a05c, 0x00000000},
12830 -       {0x0000a060, 0x00000000},
12831 -       {0x0000a064, 0x00000000},
12832 -       {0x0000a068, 0x00000000},
12833 -       {0x0000a06c, 0x00000000},
12834 -       {0x0000a070, 0x00000000},
12835 -       {0x0000a074, 0x00000000},
12836 -       {0x0000a078, 0x00000000},
12837 -       {0x0000a07c, 0x00000000},
12838 -       {0x0000a080, 0x29292929},
12839 -       {0x0000a084, 0x29292929},
12840 -       {0x0000a088, 0x29292929},
12841 -       {0x0000a08c, 0x29292929},
12842 -       {0x0000a090, 0x22292929},
12843 -       {0x0000a094, 0x1d1d2222},
12844 -       {0x0000a098, 0x0c111117},
12845 -       {0x0000a09c, 0x00030303},
12846 -       {0x0000a0a0, 0x00000000},
12847 -       {0x0000a0a4, 0x00000000},
12848 -       {0x0000a0a8, 0x00000000},
12849 -       {0x0000a0ac, 0x00000000},
12850 -       {0x0000a0b0, 0x00000000},
12851 -       {0x0000a0b4, 0x00000000},
12852 -       {0x0000a0b8, 0x00000000},
12853 -       {0x0000a0bc, 0x00000000},
12854 -       {0x0000a0c0, 0x001f0000},
12855 -       {0x0000a0c4, 0x01000101},
12856 -       {0x0000a0c8, 0x011e011f},
12857 -       {0x0000a0cc, 0x011c011d},
12858 -       {0x0000a0d0, 0x02030204},
12859 -       {0x0000a0d4, 0x02010202},
12860 -       {0x0000a0d8, 0x021f0200},
12861 -       {0x0000a0dc, 0x0302021e},
12862 -       {0x0000a0e0, 0x03000301},
12863 -       {0x0000a0e4, 0x031e031f},
12864 -       {0x0000a0e8, 0x0402031d},
12865 -       {0x0000a0ec, 0x04000401},
12866 -       {0x0000a0f0, 0x041e041f},
12867 -       {0x0000a0f4, 0x0502041d},
12868 -       {0x0000a0f8, 0x05000501},
12869 -       {0x0000a0fc, 0x051e051f},
12870 -       {0x0000a100, 0x06010602},
12871 -       {0x0000a104, 0x061f0600},
12872 -       {0x0000a108, 0x061d061e},
12873 -       {0x0000a10c, 0x07020703},
12874 -       {0x0000a110, 0x07000701},
12875 -       {0x0000a114, 0x00000000},
12876 -       {0x0000a118, 0x00000000},
12877 -       {0x0000a11c, 0x00000000},
12878 -       {0x0000a120, 0x00000000},
12879 -       {0x0000a124, 0x00000000},
12880 -       {0x0000a128, 0x00000000},
12881 -       {0x0000a12c, 0x00000000},
12882 -       {0x0000a130, 0x00000000},
12883 -       {0x0000a134, 0x00000000},
12884 -       {0x0000a138, 0x00000000},
12885 -       {0x0000a13c, 0x00000000},
12886 -       {0x0000a140, 0x001f0000},
12887 -       {0x0000a144, 0x01000101},
12888 -       {0x0000a148, 0x011e011f},
12889 -       {0x0000a14c, 0x011c011d},
12890 -       {0x0000a150, 0x02030204},
12891 -       {0x0000a154, 0x02010202},
12892 -       {0x0000a158, 0x021f0200},
12893 -       {0x0000a15c, 0x0302021e},
12894 -       {0x0000a160, 0x03000301},
12895 -       {0x0000a164, 0x031e031f},
12896 -       {0x0000a168, 0x0402031d},
12897 -       {0x0000a16c, 0x04000401},
12898 -       {0x0000a170, 0x041e041f},
12899 -       {0x0000a174, 0x0502041d},
12900 -       {0x0000a178, 0x05000501},
12901 -       {0x0000a17c, 0x051e051f},
12902 -       {0x0000a180, 0x06010602},
12903 -       {0x0000a184, 0x061f0600},
12904 -       {0x0000a188, 0x061d061e},
12905 -       {0x0000a18c, 0x07020703},
12906 -       {0x0000a190, 0x07000701},
12907 -       {0x0000a194, 0x00000000},
12908 -       {0x0000a198, 0x00000000},
12909 -       {0x0000a19c, 0x00000000},
12910 -       {0x0000a1a0, 0x00000000},
12911 -       {0x0000a1a4, 0x00000000},
12912 -       {0x0000a1a8, 0x00000000},
12913 -       {0x0000a1ac, 0x00000000},
12914 -       {0x0000a1b0, 0x00000000},
12915 -       {0x0000a1b4, 0x00000000},
12916 -       {0x0000a1b8, 0x00000000},
12917 -       {0x0000a1bc, 0x00000000},
12918 -       {0x0000a1c0, 0x00000000},
12919 -       {0x0000a1c4, 0x00000000},
12920 -       {0x0000a1c8, 0x00000000},
12921 -       {0x0000a1cc, 0x00000000},
12922 -       {0x0000a1d0, 0x00000000},
12923 -       {0x0000a1d4, 0x00000000},
12924 -       {0x0000a1d8, 0x00000000},
12925 -       {0x0000a1dc, 0x00000000},
12926 -       {0x0000a1e0, 0x00000000},
12927 -       {0x0000a1e4, 0x00000000},
12928 -       {0x0000a1e8, 0x00000000},
12929 -       {0x0000a1ec, 0x00000000},
12930 -       {0x0000a1f0, 0x00000396},
12931 -       {0x0000a1f4, 0x00000396},
12932 -       {0x0000a1f8, 0x00000396},
12933 -       {0x0000a1fc, 0x00000196},
12934 -       {0x0000b000, 0x00010000},
12935 -       {0x0000b004, 0x00030002},
12936 -       {0x0000b008, 0x00050004},
12937 -       {0x0000b00c, 0x00810080},
12938 -       {0x0000b010, 0x00830082},
12939 -       {0x0000b014, 0x01810180},
12940 -       {0x0000b018, 0x01830182},
12941 -       {0x0000b01c, 0x01850184},
12942 -       {0x0000b020, 0x02810280},
12943 -       {0x0000b024, 0x02830282},
12944 -       {0x0000b028, 0x02850284},
12945 -       {0x0000b02c, 0x02890288},
12946 -       {0x0000b030, 0x028b028a},
12947 -       {0x0000b034, 0x0388028c},
12948 -       {0x0000b038, 0x038a0389},
12949 -       {0x0000b03c, 0x038c038b},
12950 -       {0x0000b040, 0x0390038d},
12951 -       {0x0000b044, 0x03920391},
12952 -       {0x0000b048, 0x03940393},
12953 -       {0x0000b04c, 0x03960395},
12954 -       {0x0000b050, 0x00000000},
12955 -       {0x0000b054, 0x00000000},
12956 -       {0x0000b058, 0x00000000},
12957 -       {0x0000b05c, 0x00000000},
12958 -       {0x0000b060, 0x00000000},
12959 -       {0x0000b064, 0x00000000},
12960 -       {0x0000b068, 0x00000000},
12961 -       {0x0000b06c, 0x00000000},
12962 -       {0x0000b070, 0x00000000},
12963 -       {0x0000b074, 0x00000000},
12964 -       {0x0000b078, 0x00000000},
12965 -       {0x0000b07c, 0x00000000},
12966 -       {0x0000b080, 0x32323232},
12967 -       {0x0000b084, 0x2f2f3232},
12968 -       {0x0000b088, 0x23282a2d},
12969 -       {0x0000b08c, 0x1c1e2123},
12970 -       {0x0000b090, 0x14171919},
12971 -       {0x0000b094, 0x0e0e1214},
12972 -       {0x0000b098, 0x03050707},
12973 -       {0x0000b09c, 0x00030303},
12974 -       {0x0000b0a0, 0x00000000},
12975 -       {0x0000b0a4, 0x00000000},
12976 -       {0x0000b0a8, 0x00000000},
12977 -       {0x0000b0ac, 0x00000000},
12978 -       {0x0000b0b0, 0x00000000},
12979 -       {0x0000b0b4, 0x00000000},
12980 -       {0x0000b0b8, 0x00000000},
12981 -       {0x0000b0bc, 0x00000000},
12982 -       {0x0000b0c0, 0x003f0020},
12983 -       {0x0000b0c4, 0x00400041},
12984 -       {0x0000b0c8, 0x0140005f},
12985 -       {0x0000b0cc, 0x0160015f},
12986 -       {0x0000b0d0, 0x017e017f},
12987 -       {0x0000b0d4, 0x02410242},
12988 -       {0x0000b0d8, 0x025f0240},
12989 -       {0x0000b0dc, 0x027f0260},
12990 -       {0x0000b0e0, 0x0341027e},
12991 -       {0x0000b0e4, 0x035f0340},
12992 -       {0x0000b0e8, 0x037f0360},
12993 -       {0x0000b0ec, 0x04400441},
12994 -       {0x0000b0f0, 0x0460045f},
12995 -       {0x0000b0f4, 0x0541047f},
12996 -       {0x0000b0f8, 0x055f0540},
12997 -       {0x0000b0fc, 0x057f0560},
12998 -       {0x0000b100, 0x06400641},
12999 -       {0x0000b104, 0x0660065f},
13000 -       {0x0000b108, 0x067e067f},
13001 -       {0x0000b10c, 0x07410742},
13002 -       {0x0000b110, 0x075f0740},
13003 -       {0x0000b114, 0x077f0760},
13004 -       {0x0000b118, 0x07800781},
13005 -       {0x0000b11c, 0x07a0079f},
13006 -       {0x0000b120, 0x07c107bf},
13007 -       {0x0000b124, 0x000007c0},
13008 -       {0x0000b128, 0x00000000},
13009 -       {0x0000b12c, 0x00000000},
13010 -       {0x0000b130, 0x00000000},
13011 -       {0x0000b134, 0x00000000},
13012 -       {0x0000b138, 0x00000000},
13013 -       {0x0000b13c, 0x00000000},
13014 -       {0x0000b140, 0x003f0020},
13015 -       {0x0000b144, 0x00400041},
13016 -       {0x0000b148, 0x0140005f},
13017 -       {0x0000b14c, 0x0160015f},
13018 -       {0x0000b150, 0x017e017f},
13019 -       {0x0000b154, 0x02410242},
13020 -       {0x0000b158, 0x025f0240},
13021 -       {0x0000b15c, 0x027f0260},
13022 -       {0x0000b160, 0x0341027e},
13023 -       {0x0000b164, 0x035f0340},
13024 -       {0x0000b168, 0x037f0360},
13025 -       {0x0000b16c, 0x04400441},
13026 -       {0x0000b170, 0x0460045f},
13027 -       {0x0000b174, 0x0541047f},
13028 -       {0x0000b178, 0x055f0540},
13029 -       {0x0000b17c, 0x057f0560},
13030 -       {0x0000b180, 0x06400641},
13031 -       {0x0000b184, 0x0660065f},
13032 -       {0x0000b188, 0x067e067f},
13033 -       {0x0000b18c, 0x07410742},
13034 -       {0x0000b190, 0x075f0740},
13035 -       {0x0000b194, 0x077f0760},
13036 -       {0x0000b198, 0x07800781},
13037 -       {0x0000b19c, 0x07a0079f},
13038 -       {0x0000b1a0, 0x07c107bf},
13039 -       {0x0000b1a4, 0x000007c0},
13040 -       {0x0000b1a8, 0x00000000},
13041 -       {0x0000b1ac, 0x00000000},
13042 -       {0x0000b1b0, 0x00000000},
13043 -       {0x0000b1b4, 0x00000000},
13044 -       {0x0000b1b8, 0x00000000},
13045 -       {0x0000b1bc, 0x00000000},
13046 -       {0x0000b1c0, 0x00000000},
13047 -       {0x0000b1c4, 0x00000000},
13048 -       {0x0000b1c8, 0x00000000},
13049 -       {0x0000b1cc, 0x00000000},
13050 -       {0x0000b1d0, 0x00000000},
13051 -       {0x0000b1d4, 0x00000000},
13052 -       {0x0000b1d8, 0x00000000},
13053 -       {0x0000b1dc, 0x00000000},
13054 -       {0x0000b1e0, 0x00000000},
13055 -       {0x0000b1e4, 0x00000000},
13056 -       {0x0000b1e8, 0x00000000},
13057 -       {0x0000b1ec, 0x00000000},
13058 -       {0x0000b1f0, 0x00000396},
13059 -       {0x0000b1f4, 0x00000396},
13060 -       {0x0000b1f8, 0x00000396},
13061 -       {0x0000b1fc, 0x00000196},
13062 -};
13063 -
13064  static const u32 ar955x_1p0_soc_preamble[][2] = {
13065         /* Addr      allmodes  */
13066         {0x00007000, 0x00000000},
13067 @@ -1263,11 +744,6 @@ static const u32 ar955x_1p0_modes_no_xpa
13068         {0x00016848, 0x66482401, 0x66482401, 0x66482401, 0x66482401, 0x66482401, 0x66482401, 0x66482401, 0x66482401},
13069  };
13070
13071 -static const u32 ar955x_1p0_soc_postamble[][5] = {
13072 -       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
13073 -       {0x00007010, 0x00000023, 0x00000023, 0x00000023, 0x00000023},
13074 -};
13075 -
13076  static const u32 ar955x_1p0_modes_fast_clock[][3] = {
13077         /* Addr      5G_HT20     5G_HT40   */
13078         {0x00001030, 0x00000268, 0x000004d0},
13079 --- a/drivers/net/wireless/ath/ath9k/ar9565_1p0_initvals.h
13080 +++ b/drivers/net/wireless/ath/ath9k/ar9565_1p0_initvals.h
13081 @@ -20,6 +20,12 @@
13082
13083  /* AR9565 1.0 */
13084
13085 +#define ar9565_1p0_mac_postamble ar9331_1p1_mac_postamble
13086 +
13087 +#define ar9565_1p0_Modes_lowest_ob_db_tx_gain_table ar9565_1p0_modes_low_ob_db_tx_gain_table
13088 +
13089 +#define ar9565_1p0_baseband_core_txfir_coeff_japan_2484 ar9300_2p2_baseband_core_txfir_coeff_japan_2484
13090 +
13091  static const u32 ar9565_1p0_mac_core[][2] = {
13092         /* Addr      allmodes  */
13093         {0x00000008, 0x00000000},
13094 @@ -182,18 +188,6 @@ static const u32 ar9565_1p0_mac_core[][2
13095         {0x000083d0, 0x800301ff},
13096  };
13097
13098 -static const u32 ar9565_1p0_mac_postamble[][5] = {
13099 -       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
13100 -       {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
13101 -       {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
13102 -       {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
13103 -       {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
13104 -       {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b},
13105 -       {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
13106 -       {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
13107 -       {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
13108 -};
13109 -
13110  static const u32 ar9565_1p0_baseband_core[][2] = {
13111         /* Addr      allmodes  */
13112         {0x00009800, 0xafe68e30},
13113 @@ -711,66 +705,6 @@ static const u32 ar9565_1p0_Common_rx_ga
13114         {0x0000b1fc, 0x00000196},
13115  };
13116
13117 -static const u32 ar9565_1p0_Modes_lowest_ob_db_tx_gain_table[][5] = {
13118 -       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
13119 -       {0x0000a2dc, 0xfc0a9380, 0xfc0a9380, 0xfdab5b52, 0xfdab5b52},
13120 -       {0x0000a2e0, 0xffecec00, 0xffecec00, 0xfd339c84, 0xfd339c84},
13121 -       {0x0000a2e4, 0xfc0f0000, 0xfc0f0000, 0xfec3e000, 0xfec3e000},
13122 -       {0x0000a2e8, 0xfc100000, 0xfc100000, 0xfffc0000, 0xfffc0000},
13123 -       {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
13124 -       {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
13125 -       {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
13126 -       {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004},
13127 -       {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
13128 -       {0x0000a510, 0x16000220, 0x16000220, 0x0f000202, 0x0f000202},
13129 -       {0x0000a514, 0x1c000223, 0x1c000223, 0x12000400, 0x12000400},
13130 -       {0x0000a518, 0x21020220, 0x21020220, 0x16000402, 0x16000402},
13131 -       {0x0000a51c, 0x27020223, 0x27020223, 0x19000404, 0x19000404},
13132 -       {0x0000a520, 0x2b022220, 0x2b022220, 0x1c000603, 0x1c000603},
13133 -       {0x0000a524, 0x2f022222, 0x2f022222, 0x21000a02, 0x21000a02},
13134 -       {0x0000a528, 0x34022225, 0x34022225, 0x25000a04, 0x25000a04},
13135 -       {0x0000a52c, 0x3a02222a, 0x3a02222a, 0x28000a20, 0x28000a20},
13136 -       {0x0000a530, 0x3e02222c, 0x3e02222c, 0x2c000e20, 0x2c000e20},
13137 -       {0x0000a534, 0x4202242a, 0x4202242a, 0x30000e22, 0x30000e22},
13138 -       {0x0000a538, 0x4702244a, 0x4702244a, 0x34000e24, 0x34000e24},
13139 -       {0x0000a53c, 0x4b02244c, 0x4b02244c, 0x38001640, 0x38001640},
13140 -       {0x0000a540, 0x4e02246c, 0x4e02246c, 0x3c001660, 0x3c001660},
13141 -       {0x0000a544, 0x5302266c, 0x5302266c, 0x3f001861, 0x3f001861},
13142 -       {0x0000a548, 0x5702286c, 0x5702286c, 0x43001a81, 0x43001a81},
13143 -       {0x0000a54c, 0x5c04286b, 0x5c04286b, 0x47001a83, 0x47001a83},
13144 -       {0x0000a550, 0x61042a6c, 0x61042a6c, 0x4a001c84, 0x4a001c84},
13145 -       {0x0000a554, 0x66062a6c, 0x66062a6c, 0x4e001ce3, 0x4e001ce3},
13146 -       {0x0000a558, 0x6b062e6c, 0x6b062e6c, 0x52001ce5, 0x52001ce5},
13147 -       {0x0000a55c, 0x7006308c, 0x7006308c, 0x56001ce9, 0x56001ce9},
13148 -       {0x0000a560, 0x730a308a, 0x730a308a, 0x5a001ceb, 0x5a001ceb},
13149 -       {0x0000a564, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
13150 -       {0x0000a568, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
13151 -       {0x0000a56c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
13152 -       {0x0000a570, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
13153 -       {0x0000a574, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
13154 -       {0x0000a578, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
13155 -       {0x0000a57c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
13156 -       {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
13157 -       {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
13158 -       {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
13159 -       {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
13160 -       {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
13161 -       {0x0000a614, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
13162 -       {0x0000a618, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
13163 -       {0x0000a61c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
13164 -       {0x0000a620, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
13165 -       {0x0000a624, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
13166 -       {0x0000a628, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
13167 -       {0x0000a62c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
13168 -       {0x0000a630, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
13169 -       {0x0000a634, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
13170 -       {0x0000a638, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
13171 -       {0x0000a63c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
13172 -       {0x00016044, 0x012482d4, 0x012482d4, 0x012482d4, 0x012482d4},
13173 -       {0x00016048, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
13174 -       {0x00016054, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
13175 -};
13176 -
13177  static const u32 ar9565_1p0_pciephy_clkreq_disable_L1[][2] = {
13178         /* Addr      allmodes  */
13179         {0x00018c00, 0x18212ede},
13180 @@ -1231,11 +1165,4 @@ static const u32 ar9565_1p0_modes_high_p
13181         {0x00016054, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
13182  };
13183
13184 -static const u32 ar9565_1p0_baseband_core_txfir_coeff_japan_2484[][2] = {
13185 -       /* Addr      allmodes  */
13186 -       {0x0000a398, 0x00000000},
13187 -       {0x0000a39c, 0x6f7f0301},
13188 -       {0x0000a3a0, 0xca9228ee},
13189 -};
13190 -
13191  #endif /* INITVALS_9565_1P0_H */
13192 --- a/include/linux/ath9k_platform.h
13193 +++ b/include/linux/ath9k_platform.h
13194 @@ -32,6 +32,8 @@ struct ath9k_platform_data {
13195         u32 gpio_val;
13196
13197         bool is_clk_25mhz;
13198 +       bool tx_gain_buffalo;
13199 +
13200         int (*get_mac_revision)(void);
13201         int (*external_reset)(void);
13202  };
13203 --- /dev/null
13204 +++ b/drivers/net/wireless/ath/ath9k/ar9003_buffalo_initvals.h
13205 @@ -0,0 +1,126 @@
13206 +/*
13207 + * Copyright (c) 2013 Qualcomm Atheros Inc.
13208 + *
13209 + * Permission to use, copy, modify, and/or distribute this software for any
13210 + * purpose with or without fee is hereby granted, provided that the above
13211 + * copyright notice and this permission notice appear in all copies.
13212 + *
13213 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13214 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13215 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13216 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13217 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13218 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
13219 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
13220 + */
13221 +
13222 +#ifndef INITVALS_9003_BUFFALO_H
13223 +#define INITVALS_9003_BUFFALO_H
13224 +
13225 +static const u32 ar9300Modes_high_power_tx_gain_table_buffalo[][5] = {
13226 +       /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
13227 +       {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
13228 +       {0x0000a2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
13229 +       {0x0000a2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
13230 +       {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
13231 +       {0x0000a410, 0x000050d8, 0x000050d8, 0x000050d9, 0x000050d9},
13232 +       {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000},
13233 +       {0x0000a504, 0x04002222, 0x04002222, 0x04000002, 0x04000002},
13234 +       {0x0000a508, 0x09002421, 0x09002421, 0x08000004, 0x08000004},
13235 +       {0x0000a50c, 0x0d002621, 0x0d002621, 0x0b000200, 0x0b000200},
13236 +       {0x0000a510, 0x13004620, 0x13004620, 0x0f000202, 0x0f000202},
13237 +       {0x0000a514, 0x19004a20, 0x19004a20, 0x11000400, 0x11000400},
13238 +       {0x0000a518, 0x1d004e20, 0x1d004e20, 0x15000402, 0x15000402},
13239 +       {0x0000a51c, 0x21005420, 0x21005420, 0x19000404, 0x19000404},
13240 +       {0x0000a520, 0x26005e20, 0x26005e20, 0x1b000603, 0x1b000603},
13241 +       {0x0000a524, 0x2b005e40, 0x2b005e40, 0x1f000a02, 0x1f000a02},
13242 +       {0x0000a528, 0x2f005e42, 0x2f005e42, 0x23000a04, 0x23000a04},
13243 +       {0x0000a52c, 0x33005e44, 0x33005e44, 0x26000a20, 0x26000a20},
13244 +       {0x0000a530, 0x38005e65, 0x38005e65, 0x2a000e20, 0x2a000e20},
13245 +       {0x0000a534, 0x3c005e69, 0x3c005e69, 0x2e000e22, 0x2e000e22},
13246 +       {0x0000a538, 0x40005e6b, 0x40005e6b, 0x31000e24, 0x31000e24},
13247 +       {0x0000a53c, 0x44005e6d, 0x44005e6d, 0x34001640, 0x34001640},
13248 +       {0x0000a540, 0x49005e72, 0x49005e72, 0x38001660, 0x38001660},
13249 +       {0x0000a544, 0x4e005eb2, 0x4e005eb2, 0x3b001861, 0x3b001861},
13250 +       {0x0000a548, 0x53005f12, 0x53005f12, 0x3e001a81, 0x3e001a81},
13251 +       {0x0000a54c, 0x59025eb2, 0x59025eb2, 0x42001a83, 0x42001a83},
13252 +       {0x0000a550, 0x5e025f12, 0x5e025f12, 0x44001c84, 0x44001c84},
13253 +       {0x0000a554, 0x61027f12, 0x61027f12, 0x48001ce3, 0x48001ce3},
13254 +       {0x0000a558, 0x6702bf12, 0x6702bf12, 0x4c001ce5, 0x4c001ce5},
13255 +       {0x0000a55c, 0x6b02bf14, 0x6b02bf14, 0x50001ce9, 0x50001ce9},
13256 +       {0x0000a560, 0x6f02bf16, 0x6f02bf16, 0x54001ceb, 0x54001ceb},
13257 +       {0x0000a564, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
13258 +       {0x0000a568, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
13259 +       {0x0000a56c, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
13260 +       {0x0000a570, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
13261 +       {0x0000a574, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
13262 +       {0x0000a578, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
13263 +       {0x0000a57c, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
13264 +       {0x0000a580, 0x00802220, 0x00802220, 0x00800000, 0x00800000},
13265 +       {0x0000a584, 0x04802222, 0x04802222, 0x04800002, 0x04800002},
13266 +       {0x0000a588, 0x09802421, 0x09802421, 0x08800004, 0x08800004},
13267 +       {0x0000a58c, 0x0d802621, 0x0d802621, 0x0b800200, 0x0b800200},
13268 +       {0x0000a590, 0x13804620, 0x13804620, 0x0f800202, 0x0f800202},
13269 +       {0x0000a594, 0x19804a20, 0x19804a20, 0x11800400, 0x11800400},
13270 +       {0x0000a598, 0x1d804e20, 0x1d804e20, 0x15800402, 0x15800402},
13271 +       {0x0000a59c, 0x21805420, 0x21805420, 0x19800404, 0x19800404},
13272 +       {0x0000a5a0, 0x26805e20, 0x26805e20, 0x1b800603, 0x1b800603},
13273 +       {0x0000a5a4, 0x2b805e40, 0x2b805e40, 0x1f800a02, 0x1f800a02},
13274 +       {0x0000a5a8, 0x2f805e42, 0x2f805e42, 0x23800a04, 0x23800a04},
13275 +       {0x0000a5ac, 0x33805e44, 0x33805e44, 0x26800a20, 0x26800a20},
13276 +       {0x0000a5b0, 0x38805e65, 0x38805e65, 0x2a800e20, 0x2a800e20},
13277 +       {0x0000a5b4, 0x3c805e69, 0x3c805e69, 0x2e800e22, 0x2e800e22},
13278 +       {0x0000a5b8, 0x40805e6b, 0x40805e6b, 0x31800e24, 0x31800e24},
13279 +       {0x0000a5bc, 0x44805e6d, 0x44805e6d, 0x34801640, 0x34801640},
13280 +       {0x0000a5c0, 0x49805e72, 0x49805e72, 0x38801660, 0x38801660},
13281 +       {0x0000a5c4, 0x4e805eb2, 0x4e805eb2, 0x3b801861, 0x3b801861},
13282 +       {0x0000a5c8, 0x53805f12, 0x53805f12, 0x3e801a81, 0x3e801a81},
13283 +       {0x0000a5cc, 0x59825eb2, 0x59825eb2, 0x42801a83, 0x42801a83},
13284 +       {0x0000a5d0, 0x5e825f12, 0x5e825f12, 0x44801c84, 0x44801c84},
13285 +       {0x0000a5d4, 0x61827f12, 0x61827f12, 0x48801ce3, 0x48801ce3},
13286 +       {0x0000a5d8, 0x6782bf12, 0x6782bf12, 0x4c801ce5, 0x4c801ce5},
13287 +       {0x0000a5dc, 0x6b82bf14, 0x6b82bf14, 0x50801ce9, 0x50801ce9},
13288 +       {0x0000a5e0, 0x6f82bf16, 0x6f82bf16, 0x54801ceb, 0x54801ceb},
13289 +       {0x0000a5e4, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
13290 +       {0x0000a5e8, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
13291 +       {0x0000a5ec, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
13292 +       {0x0000a5f0, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
13293 +       {0x0000a5f4, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
13294 +       {0x0000a5f8, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
13295 +       {0x0000a5fc, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
13296 +       {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
13297 +       {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
13298 +       {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
13299 +       {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
13300 +       {0x0000a610, 0x00804000, 0x00804000, 0x00000000, 0x00000000},
13301 +       {0x0000a614, 0x00804201, 0x00804201, 0x01404000, 0x01404000},
13302 +       {0x0000a618, 0x0280c802, 0x0280c802, 0x01404501, 0x01404501},
13303 +       {0x0000a61c, 0x0280ca03, 0x0280ca03, 0x02008501, 0x02008501},
13304 +       {0x0000a620, 0x04c15104, 0x04c15104, 0x0280ca03, 0x0280ca03},
13305 +       {0x0000a624, 0x04c15305, 0x04c15305, 0x03010c04, 0x03010c04},
13306 +       {0x0000a628, 0x04c15305, 0x04c15305, 0x04014c04, 0x04014c04},
13307 +       {0x0000a62c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
13308 +       {0x0000a630, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
13309 +       {0x0000a634, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
13310 +       {0x0000a638, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
13311 +       {0x0000a63c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
13312 +       {0x0000b2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
13313 +       {0x0000b2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
13314 +       {0x0000b2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
13315 +       {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
13316 +       {0x0000c2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
13317 +       {0x0000c2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
13318 +       {0x0000c2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
13319 +       {0x0000c2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
13320 +       {0x00016044, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
13321 +       {0x00016048, 0x66480001, 0x66480001, 0x66480001, 0x66480001},
13322 +       {0x00016068, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
13323 +       {0x00016444, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
13324 +       {0x00016448, 0x66480001, 0x66480001, 0x66480001, 0x66480001},
13325 +       {0x00016468, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
13326 +       {0x00016844, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
13327 +       {0x00016848, 0x66480001, 0x66480001, 0x66480001, 0x66480001},
13328 +       {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
13329 +};
13330 +
13331 +#endif /* INITVALS_9003_BUFFALO_H */
13332 --- a/drivers/net/wireless/ath/ath9k/ar9002_mac.c
13333 +++ b/drivers/net/wireless/ath/ath9k/ar9002_mac.c
13334 @@ -29,7 +29,8 @@ static void ar9002_hw_set_desc_link(void
13335         ((struct ath_desc*) ds)->ds_link = ds_link;
13336  }
13337
13338 -static bool ar9002_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
13339 +static bool ar9002_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked,
13340 +                             u32 *sync_cause_p)
13341  {
13342         u32 isr = 0;
13343         u32 mask2 = 0;
13344 @@ -76,9 +77,16 @@ static bool ar9002_hw_get_isr(struct ath
13345                                 mask2 |= ATH9K_INT_CST;
13346                         if (isr2 & AR_ISR_S2_TSFOOR)
13347                                 mask2 |= ATH9K_INT_TSFOOR;
13348 +
13349 +                       if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
13350 +                               REG_WRITE(ah, AR_ISR_S2, isr2);
13351 +                               isr &= ~AR_ISR_BCNMISC;
13352 +                       }
13353                 }
13354
13355 -               isr = REG_READ(ah, AR_ISR_RAC);
13356 +               if (pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)
13357 +                       isr = REG_READ(ah, AR_ISR_RAC);
13358 +
13359                 if (isr == 0xffffffff) {
13360                         *masked = 0;
13361                         return false;
13362 @@ -97,11 +105,23 @@ static bool ar9002_hw_get_isr(struct ath
13363
13364                         *masked |= ATH9K_INT_TX;
13365
13366 -                       s0_s = REG_READ(ah, AR_ISR_S0_S);
13367 +                       if (pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED) {
13368 +                               s0_s = REG_READ(ah, AR_ISR_S0_S);
13369 +                               s1_s = REG_READ(ah, AR_ISR_S1_S);
13370 +                       } else {
13371 +                               s0_s = REG_READ(ah, AR_ISR_S0);
13372 +                               REG_WRITE(ah, AR_ISR_S0, s0_s);
13373 +                               s1_s = REG_READ(ah, AR_ISR_S1);
13374 +                               REG_WRITE(ah, AR_ISR_S1, s1_s);
13375 +
13376 +                               isr &= ~(AR_ISR_TXOK |
13377 +                                        AR_ISR_TXDESC |
13378 +                                        AR_ISR_TXERR |
13379 +                                        AR_ISR_TXEOL);
13380 +                       }
13381 +
13382                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
13383                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
13384 -
13385 -                       s1_s = REG_READ(ah, AR_ISR_S1_S);
13386                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
13387                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
13388                 }
13389 @@ -114,13 +134,23 @@ static bool ar9002_hw_get_isr(struct ath
13390                 *masked |= mask2;
13391         }
13392
13393 +       if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
13394 +               REG_WRITE(ah, AR_ISR, isr);
13395 +               REG_READ(ah, AR_ISR);
13396 +       }
13397 +
13398         if (AR_SREV_9100(ah))
13399                 return true;
13400
13401         if (isr & AR_ISR_GENTMR) {
13402                 u32 s5_s;
13403
13404 -               s5_s = REG_READ(ah, AR_ISR_S5_S);
13405 +               if (pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED) {
13406 +                       s5_s = REG_READ(ah, AR_ISR_S5_S);
13407 +               } else {
13408 +                       s5_s = REG_READ(ah, AR_ISR_S5);
13409 +               }
13410 +
13411                 ah->intr_gen_timer_trigger =
13412                                 MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
13413
13414 @@ -133,10 +163,16 @@ static bool ar9002_hw_get_isr(struct ath
13415                 if ((s5_s & AR_ISR_S5_TIM_TIMER) &&
13416                     !(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
13417                         *masked |= ATH9K_INT_TIM_TIMER;
13418 +
13419 +               if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
13420 +                       REG_WRITE(ah, AR_ISR_S5, s5_s);
13421 +                       isr &= ~AR_ISR_GENTMR;
13422 +               }
13423         }
13424
13425         if (sync_cause) {
13426 -               ath9k_debug_sync_cause(common, sync_cause);
13427 +               if (sync_cause_p)
13428 +                       *sync_cause_p = sync_cause;
13429                 fatal_int =
13430                         (sync_cause &
13431                          (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
13432 --- a/drivers/net/wireless/ath/ath9k/antenna.c
13433 +++ b/drivers/net/wireless/ath/ath9k/antenna.c
13434 @@ -724,14 +724,14 @@ void ath_ant_comb_scan(struct ath_softc
13435         struct ath_ant_comb *antcomb = &sc->ant_comb;
13436         int alt_ratio = 0, alt_rssi_avg = 0, main_rssi_avg = 0, curr_alt_set;
13437         int curr_main_set;
13438 -       int main_rssi = rs->rs_rssi_ctl0;
13439 -       int alt_rssi = rs->rs_rssi_ctl1;
13440 +       int main_rssi = rs->rs_rssi_ctl[0];
13441 +       int alt_rssi = rs->rs_rssi_ctl[1];
13442         int rx_ant_conf,  main_ant_conf;
13443         bool short_scan = false, ret;
13444
13445 -       rx_ant_conf = (rs->rs_rssi_ctl2 >> ATH_ANT_RX_CURRENT_SHIFT) &
13446 +       rx_ant_conf = (rs->rs_rssi_ctl[2] >> ATH_ANT_RX_CURRENT_SHIFT) &
13447                        ATH_ANT_RX_MASK;
13448 -       main_ant_conf = (rs->rs_rssi_ctl2 >> ATH_ANT_RX_MAIN_SHIFT) &
13449 +       main_ant_conf = (rs->rs_rssi_ctl[2] >> ATH_ANT_RX_MAIN_SHIFT) &
13450                          ATH_ANT_RX_MASK;
13451
13452         if (alt_rssi >= antcomb->low_rssi_thresh) {
13453 --- a/drivers/net/wireless/ath/ath9k/ar9002_hw.c
13454 +++ b/drivers/net/wireless/ath/ath9k/ar9002_hw.c
13455 @@ -32,12 +32,8 @@ static int ar9002_hw_init_mode_regs(stru
13456                 return 0;
13457         }
13458
13459 -       if (ah->config.pcie_clock_req)
13460 -               INIT_INI_ARRAY(&ah->iniPcieSerdes,
13461 -                          ar9280PciePhy_clkreq_off_L1_9280);
13462 -       else
13463 -               INIT_INI_ARRAY(&ah->iniPcieSerdes,
13464 -                          ar9280PciePhy_clkreq_always_on_L1_9280);
13465 +       INIT_INI_ARRAY(&ah->iniPcieSerdes,
13466 +                      ar9280PciePhy_clkreq_always_on_L1_9280);
13467
13468         if (AR_SREV_9287_11_OR_LATER(ah)) {
13469                 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1);
13470 --- a/drivers/net/wireless/ath/ath9k/ar9002_phy.c
13471 +++ b/drivers/net/wireless/ath/ath9k/ar9002_phy.c
13472 @@ -201,7 +201,6 @@ static void ar9002_hw_spur_mitigate(stru
13473         ath9k_hw_get_channel_centers(ah, chan, &centers);
13474         freq = centers.synth_center;
13475
13476 -       ah->config.spurmode = SPUR_ENABLE_EEPROM;
13477         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
13478                 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
13479
13480 --- a/drivers/net/wireless/ath/ath9k/ar9003_mac.c
13481 +++ b/drivers/net/wireless/ath/ath9k/ar9003_mac.c
13482 @@ -175,7 +175,8 @@ static void ar9003_hw_set_desc_link(void
13483         ads->ctl10 |= ar9003_calc_ptr_chksum(ads);
13484  }
13485
13486 -static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
13487 +static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked,
13488 +                             u32 *sync_cause_p)
13489  {
13490         u32 isr = 0;
13491         u32 mask2 = 0;
13492 @@ -310,7 +311,8 @@ static bool ar9003_hw_get_isr(struct ath
13493                 ar9003_mci_get_isr(ah, masked);
13494
13495         if (sync_cause) {
13496 -               ath9k_debug_sync_cause(common, sync_cause);
13497 +               if (sync_cause_p)
13498 +                       *sync_cause_p = sync_cause;
13499                 fatal_int =
13500                         (sync_cause &
13501                          (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
13502 @@ -476,12 +478,12 @@ int ath9k_hw_process_rxdesc_edma(struct
13503
13504         /* XXX: Keycache */
13505         rxs->rs_rssi = MS(rxsp->status5, AR_RxRSSICombined);
13506 -       rxs->rs_rssi_ctl0 = MS(rxsp->status1, AR_RxRSSIAnt00);
13507 -       rxs->rs_rssi_ctl1 = MS(rxsp->status1, AR_RxRSSIAnt01);
13508 -       rxs->rs_rssi_ctl2 = MS(rxsp->status1, AR_RxRSSIAnt02);
13509 -       rxs->rs_rssi_ext0 = MS(rxsp->status5, AR_RxRSSIAnt10);
13510 -       rxs->rs_rssi_ext1 = MS(rxsp->status5, AR_RxRSSIAnt11);
13511 -       rxs->rs_rssi_ext2 = MS(rxsp->status5, AR_RxRSSIAnt12);
13512 +       rxs->rs_rssi_ctl[0] = MS(rxsp->status1, AR_RxRSSIAnt00);
13513 +       rxs->rs_rssi_ctl[1] = MS(rxsp->status1, AR_RxRSSIAnt01);
13514 +       rxs->rs_rssi_ctl[2] = MS(rxsp->status1, AR_RxRSSIAnt02);
13515 +       rxs->rs_rssi_ext[0] = MS(rxsp->status5, AR_RxRSSIAnt10);
13516 +       rxs->rs_rssi_ext[1] = MS(rxsp->status5, AR_RxRSSIAnt11);
13517 +       rxs->rs_rssi_ext[2] = MS(rxsp->status5, AR_RxRSSIAnt12);
13518
13519         if (rxsp->status11 & AR_RxKeyIdxValid)
13520                 rxs->rs_keyix = MS(rxsp->status11, AR_KeyIdx);
13521 --- a/drivers/net/wireless/ath/ath9k/beacon.c
13522 +++ b/drivers/net/wireless/ath/ath9k/beacon.c
13523 @@ -274,18 +274,19 @@ static int ath9k_beacon_choose_slot(stru
13524         return slot;
13525  }
13526
13527 -void ath9k_set_tsfadjust(struct ath_softc *sc, struct ieee80211_vif *vif)
13528 +static void ath9k_set_tsfadjust(struct ath_softc *sc, struct ieee80211_vif *vif)
13529  {
13530         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
13531         struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
13532         struct ath_vif *avp = (void *)vif->drv_priv;
13533 -       u64 tsfadjust;
13534 +       u32 tsfadjust;
13535
13536         if (avp->av_bslot == 0)
13537                 return;
13538
13539 -       tsfadjust = cur_conf->beacon_interval * avp->av_bslot / ATH_BCBUF;
13540 -       avp->tsf_adjust = cpu_to_le64(TU_TO_USEC(tsfadjust));
13541 +       tsfadjust = cur_conf->beacon_interval * avp->av_bslot;
13542 +       tsfadjust = TU_TO_USEC(tsfadjust) / ATH_BCBUF;
13543 +       avp->tsf_adjust = cpu_to_le64(tsfadjust);
13544
13545         ath_dbg(common, CONFIG, "tsfadjust is: %llu for bslot: %d\n",
13546                 (unsigned long long)tsfadjust, avp->av_bslot);
13547 @@ -431,6 +432,33 @@ static void ath9k_beacon_init(struct ath
13548         ath9k_hw_enable_interrupts(ah);
13549  }
13550
13551 +/* Calculate the modulo of a 64 bit TSF snapshot with a TU divisor */
13552 +static u32 ath9k_mod_tsf64_tu(u64 tsf, u32 div_tu)
13553 +{
13554 +       u32 tsf_mod, tsf_hi, tsf_lo, mod_hi, mod_lo;
13555 +
13556 +       tsf_mod = tsf & (BIT(10) - 1);
13557 +       tsf_hi = tsf >> 32;
13558 +       tsf_lo = ((u32) tsf) >> 10;
13559 +
13560 +       mod_hi = tsf_hi % div_tu;
13561 +       mod_lo = ((mod_hi << 22) + tsf_lo) % div_tu;
13562 +
13563 +       return (mod_lo << 10) | tsf_mod;
13564 +}
13565 +
13566 +static u32 ath9k_get_next_tbtt(struct ath_softc *sc, u64 tsf,
13567 +                              unsigned int interval)
13568 +{
13569 +       struct ath_hw *ah = sc->sc_ah;
13570 +       unsigned int offset;
13571 +
13572 +       tsf += TU_TO_USEC(FUDGE + ah->config.sw_beacon_response_time);
13573 +       offset = ath9k_mod_tsf64_tu(tsf, interval);
13574 +
13575 +       return (u32) tsf + TU_TO_USEC(interval) - offset;
13576 +}
13577 +
13578  /*
13579   * For multi-bss ap support beacons are either staggered evenly over N slots or
13580   * burst together.  For the former arrange for the SWBA to be delivered for each
13581 @@ -446,7 +474,8 @@ static void ath9k_beacon_config_ap(struc
13582         /* NB: the beacon interval is kept internally in TU's */
13583         intval = TU_TO_USEC(conf->beacon_interval);
13584         intval /= ATH_BCBUF;
13585 -       nexttbtt = intval;
13586 +       nexttbtt = ath9k_get_next_tbtt(sc, ath9k_hw_gettsf64(ah),
13587 +                                      conf->beacon_interval);
13588
13589         if (conf->enable_beacon)
13590                 ah->imask |= ATH9K_INT_SWBA;
13591 @@ -458,7 +487,7 @@ static void ath9k_beacon_config_ap(struc
13592                 (conf->enable_beacon) ? "Enable" : "Disable",
13593                 nexttbtt, intval, conf->beacon_interval);
13594
13595 -       ath9k_beacon_init(sc, nexttbtt, intval, true);
13596 +       ath9k_beacon_init(sc, nexttbtt, intval, false);
13597  }
13598
13599  /*
13600 @@ -475,11 +504,9 @@ static void ath9k_beacon_config_sta(stru
13601         struct ath_hw *ah = sc->sc_ah;
13602         struct ath_common *common = ath9k_hw_common(ah);
13603         struct ath9k_beacon_state bs;
13604 -       int dtimperiod, dtimcount, sleepduration;
13605 -       int cfpperiod, cfpcount;
13606 -       u32 nexttbtt = 0, intval, tsftu;
13607 +       int dtim_intval, sleepduration;
13608 +       u32 nexttbtt = 0, intval;
13609         u64 tsf;
13610 -       int num_beacons, offset, dtim_dec_count, cfp_dec_count;
13611
13612         /* No need to configure beacon if we are not associated */
13613         if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
13614 @@ -492,53 +519,25 @@ static void ath9k_beacon_config_sta(stru
13615         intval = conf->beacon_interval;
13616
13617         /*
13618 -        * Setup dtim and cfp parameters according to
13619 +        * Setup dtim parameters according to
13620          * last beacon we received (which may be none).
13621          */
13622 -       dtimperiod = conf->dtim_period;
13623 -       dtimcount = conf->dtim_count;
13624 -       if (dtimcount >= dtimperiod)    /* NB: sanity check */
13625 -               dtimcount = 0;
13626 -       cfpperiod = 1;                  /* NB: no PCF support yet */
13627 -       cfpcount = 0;
13628 -
13629 +       dtim_intval = intval * conf->dtim_period;
13630         sleepduration = conf->listen_interval * intval;
13631
13632         /*
13633          * Pull nexttbtt forward to reflect the current
13634 -        * TSF and calculate dtim+cfp state for the result.
13635 +        * TSF and calculate dtim state for the result.
13636          */
13637         tsf = ath9k_hw_gettsf64(ah);
13638 -       tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE;
13639 +       nexttbtt = ath9k_get_next_tbtt(sc, tsf, intval);
13640
13641 -       num_beacons = tsftu / intval + 1;
13642 -       offset = tsftu % intval;
13643 -       nexttbtt = tsftu - offset;
13644 -       if (offset)
13645 -               nexttbtt += intval;
13646 -
13647 -       /* DTIM Beacon every dtimperiod Beacon */
13648 -       dtim_dec_count = num_beacons % dtimperiod;
13649 -       /* CFP every cfpperiod DTIM Beacon */
13650 -       cfp_dec_count = (num_beacons / dtimperiod) % cfpperiod;
13651 -       if (dtim_dec_count)
13652 -               cfp_dec_count++;
13653 -
13654 -       dtimcount -= dtim_dec_count;
13655 -       if (dtimcount < 0)
13656 -               dtimcount += dtimperiod;
13657 -
13658 -       cfpcount -= cfp_dec_count;
13659 -       if (cfpcount < 0)
13660 -               cfpcount += cfpperiod;
13661 -
13662 -       bs.bs_intval = intval;
13663 +       bs.bs_intval = TU_TO_USEC(intval);
13664 +       bs.bs_dtimperiod = conf->dtim_period * bs.bs_intval;
13665         bs.bs_nexttbtt = nexttbtt;
13666 -       bs.bs_dtimperiod = dtimperiod*intval;
13667 -       bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval;
13668 -       bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod;
13669 -       bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod;
13670 -       bs.bs_cfpmaxduration = 0;
13671 +       bs.bs_nextdtim = nexttbtt;
13672 +       if (conf->dtim_period > 1)
13673 +               bs.bs_nextdtim = ath9k_get_next_tbtt(sc, tsf, dtim_intval);
13674
13675         /*
13676          * Calculate the number of consecutive beacons to miss* before taking
13677 @@ -566,18 +565,16 @@ static void ath9k_beacon_config_sta(stru
13678          * XXX fixed at 100ms
13679          */
13680
13681 -       bs.bs_sleepduration = roundup(IEEE80211_MS_TO_TU(100), sleepduration);
13682 +       bs.bs_sleepduration = TU_TO_USEC(roundup(IEEE80211_MS_TO_TU(100),
13683 +                                                sleepduration));
13684         if (bs.bs_sleepduration > bs.bs_dtimperiod)
13685                 bs.bs_sleepduration = bs.bs_dtimperiod;
13686
13687         /* TSF out of range threshold fixed at 1 second */
13688         bs.bs_tsfoor_threshold = ATH9K_TSFOOR_THRESHOLD;
13689
13690 -       ath_dbg(common, BEACON, "tsf: %llu tsftu: %u\n", tsf, tsftu);
13691 -       ath_dbg(common, BEACON,
13692 -               "bmiss: %u sleep: %u cfp-period: %u maxdur: %u next: %u\n",
13693 -               bs.bs_bmissthreshold, bs.bs_sleepduration,
13694 -               bs.bs_cfpperiod, bs.bs_cfpmaxduration, bs.bs_cfpnext);
13695 +       ath_dbg(common, BEACON, "bmiss: %u sleep: %u\n",
13696 +               bs.bs_bmissthreshold, bs.bs_sleepduration);
13697
13698         /* Set the computed STA beacon timers */
13699
13700 @@ -600,25 +597,11 @@ static void ath9k_beacon_config_adhoc(st
13701
13702         intval = TU_TO_USEC(conf->beacon_interval);
13703
13704 -       if (conf->ibss_creator) {
13705 +       if (conf->ibss_creator)
13706                 nexttbtt = intval;
13707 -       } else {
13708 -               u32 tbtt, offset, tsftu;
13709 -               u64 tsf;
13710 -
13711 -               /*
13712 -                * Pull nexttbtt forward to reflect the current
13713 -                * sync'd TSF.
13714 -                */
13715 -               tsf = ath9k_hw_gettsf64(ah);
13716 -               tsftu = TSF_TO_TU(tsf >> 32, tsf) + FUDGE;
13717 -               offset = tsftu % conf->beacon_interval;
13718 -               tbtt = tsftu - offset;
13719 -               if (offset)
13720 -                       tbtt += conf->beacon_interval;
13721 -
13722 -               nexttbtt = TU_TO_USEC(tbtt);
13723 -       }
13724 +       else
13725 +               nexttbtt = ath9k_get_next_tbtt(sc, ath9k_hw_gettsf64(ah),
13726 +                                              conf->beacon_interval);
13727
13728         if (conf->enable_beacon)
13729                 ah->imask |= ATH9K_INT_SWBA;
13730 @@ -640,7 +623,8 @@ static void ath9k_beacon_config_adhoc(st
13731                 set_bit(SC_OP_BEACONS, &sc->sc_flags);
13732  }
13733
13734 -bool ath9k_allow_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif)
13735 +static bool ath9k_allow_beacon_config(struct ath_softc *sc,
13736 +                                     struct ieee80211_vif *vif)
13737  {
13738         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
13739         struct ath_vif *avp = (void *)vif->drv_priv;
13740 @@ -711,12 +695,17 @@ void ath9k_beacon_config(struct ath_soft
13741         unsigned long flags;
13742         bool skip_beacon = false;
13743
13744 +       if (vif->type == NL80211_IFTYPE_AP)
13745 +               ath9k_set_tsfadjust(sc, vif);
13746 +
13747 +       if (!ath9k_allow_beacon_config(sc, vif))
13748 +               return;
13749 +
13750         if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION) {
13751                 ath9k_cache_beacon_config(sc, bss_conf);
13752                 ath9k_set_beacon(sc);
13753                 set_bit(SC_OP_BEACONS, &sc->sc_flags);
13754                 return;
13755 -
13756         }
13757
13758         /*
13759 --- a/drivers/net/wireless/ath/ath9k/btcoex.c
13760 +++ b/drivers/net/wireless/ath/ath9k/btcoex.c
13761 @@ -66,7 +66,6 @@ void ath9k_hw_init_btcoex_hw(struct ath_
13762                 .bt_first_slot_time = 5,
13763                 .bt_hold_rx_clear = true,
13764         };
13765 -       u32 i, idx;
13766         bool rxclear_polarity = ath_bt_config.bt_rxclear_polarity;
13767
13768         if (AR_SREV_9300_20_OR_LATER(ah))
13769 @@ -88,11 +87,6 @@ void ath9k_hw_init_btcoex_hw(struct ath_
13770                 SM(ath_bt_config.bt_hold_rx_clear, AR_BT_HOLD_RX_CLEAR) |
13771                 SM(ATH_BTCOEX_BMISS_THRESH, AR_BT_BCN_MISS_THRESH) |
13772                 AR_BT_DISABLE_BT_ANT;
13773 -
13774 -       for (i = 0; i < 32; i++) {
13775 -               idx = (debruijn32 << i) >> 27;
13776 -               ah->hw_gen_timers.gen_timer_index[idx] = i;
13777 -       }
13778  }
13779  EXPORT_SYMBOL(ath9k_hw_init_btcoex_hw);
13780
13781 --- a/drivers/net/wireless/ath/ath9k/dfs.c
13782 +++ b/drivers/net/wireless/ath/ath9k/dfs.c
13783 @@ -158,8 +158,8 @@ void ath9k_dfs_process_phyerr(struct ath
13784                 return;
13785         }
13786
13787 -       ard.rssi = rs->rs_rssi_ctl0;
13788 -       ard.ext_rssi = rs->rs_rssi_ext0;
13789 +       ard.rssi = rs->rs_rssi_ctl[0];
13790 +       ard.ext_rssi = rs->rs_rssi_ext[0];
13791
13792         /*
13793          * hardware stores this as 8 bit signed value.
13794 --- a/drivers/net/wireless/ath/ath9k/eeprom_4k.c
13795 +++ b/drivers/net/wireless/ath/ath9k/eeprom_4k.c
13796 @@ -1085,31 +1085,7 @@ static void ath9k_hw_4k_set_board_values
13797
13798  static u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
13799  {
13800 -#define EEP_MAP4K_SPURCHAN \
13801 -       (ah->eeprom.map4k.modalHeader.spurChans[i].spurChan)
13802 -       struct ath_common *common = ath9k_hw_common(ah);
13803 -
13804 -       u16 spur_val = AR_NO_SPUR;
13805 -
13806 -       ath_dbg(common, ANI, "Getting spur idx:%d is2Ghz:%d val:%x\n",
13807 -               i, is2GHz, ah->config.spurchans[i][is2GHz]);
13808 -
13809 -       switch (ah->config.spurmode) {
13810 -       case SPUR_DISABLE:
13811 -               break;
13812 -       case SPUR_ENABLE_IOCTL:
13813 -               spur_val = ah->config.spurchans[i][is2GHz];
13814 -               ath_dbg(common, ANI, "Getting spur val from new loc. %d\n",
13815 -                       spur_val);
13816 -               break;
13817 -       case SPUR_ENABLE_EEPROM:
13818 -               spur_val = EEP_MAP4K_SPURCHAN;
13819 -               break;
13820 -       }
13821 -
13822 -       return spur_val;
13823 -
13824 -#undef EEP_MAP4K_SPURCHAN
13825 +       return ah->eeprom.map4k.modalHeader.spurChans[i].spurChan;
13826  }
13827
13828  const struct eeprom_ops eep_4k_ops = {
13829 --- a/drivers/net/wireless/ath/ath9k/eeprom_9287.c
13830 +++ b/drivers/net/wireless/ath/ath9k/eeprom_9287.c
13831 @@ -1004,31 +1004,7 @@ static void ath9k_hw_ar9287_set_board_va
13832  static u16 ath9k_hw_ar9287_get_spur_channel(struct ath_hw *ah,
13833                                             u16 i, bool is2GHz)
13834  {
13835 -#define EEP_MAP9287_SPURCHAN \
13836 -       (ah->eeprom.map9287.modalHeader.spurChans[i].spurChan)
13837 -
13838 -       struct ath_common *common = ath9k_hw_common(ah);
13839 -       u16 spur_val = AR_NO_SPUR;
13840 -
13841 -       ath_dbg(common, ANI, "Getting spur idx:%d is2Ghz:%d val:%x\n",
13842 -               i, is2GHz, ah->config.spurchans[i][is2GHz]);
13843 -
13844 -       switch (ah->config.spurmode) {
13845 -       case SPUR_DISABLE:
13846 -               break;
13847 -       case SPUR_ENABLE_IOCTL:
13848 -               spur_val = ah->config.spurchans[i][is2GHz];
13849 -               ath_dbg(common, ANI, "Getting spur val from new loc. %d\n",
13850 -                       spur_val);
13851 -               break;
13852 -       case SPUR_ENABLE_EEPROM:
13853 -               spur_val = EEP_MAP9287_SPURCHAN;
13854 -               break;
13855 -       }
13856 -
13857 -       return spur_val;
13858 -
13859 -#undef EEP_MAP9287_SPURCHAN
13860 +       return ah->eeprom.map9287.modalHeader.spurChans[i].spurChan;
13861  }
13862
13863  const struct eeprom_ops eep_ar9287_ops = {
13864 --- a/drivers/net/wireless/ath/ath9k/eeprom_def.c
13865 +++ b/drivers/net/wireless/ath/ath9k/eeprom_def.c
13866 @@ -1348,31 +1348,7 @@ static void ath9k_hw_def_set_txpower(str
13867
13868  static u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
13869  {
13870 -#define EEP_DEF_SPURCHAN \
13871 -       (ah->eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan)
13872 -       struct ath_common *common = ath9k_hw_common(ah);
13873 -
13874 -       u16 spur_val = AR_NO_SPUR;
13875 -
13876 -       ath_dbg(common, ANI, "Getting spur idx:%d is2Ghz:%d val:%x\n",
13877 -               i, is2GHz, ah->config.spurchans[i][is2GHz]);
13878 -
13879 -       switch (ah->config.spurmode) {
13880 -       case SPUR_DISABLE:
13881 -               break;
13882 -       case SPUR_ENABLE_IOCTL:
13883 -               spur_val = ah->config.spurchans[i][is2GHz];
13884 -               ath_dbg(common, ANI, "Getting spur val from new loc. %d\n",
13885 -                       spur_val);
13886 -               break;
13887 -       case SPUR_ENABLE_EEPROM:
13888 -               spur_val = EEP_DEF_SPURCHAN;
13889 -               break;
13890 -       }
13891 -
13892 -       return spur_val;
13893 -
13894 -#undef EEP_DEF_SPURCHAN
13895 +       return ah->eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan;
13896  }
13897
13898  const struct eeprom_ops eep_def_ops = {
13899 --- a/drivers/net/wireless/ath/ath9k/gpio.c
13900 +++ b/drivers/net/wireless/ath/ath9k/gpio.c
13901 @@ -157,36 +157,6 @@ static void ath_detect_bt_priority(struc
13902         }
13903  }
13904
13905 -static void ath9k_gen_timer_start(struct ath_hw *ah,
13906 -                                 struct ath_gen_timer *timer,
13907 -                                 u32 trig_timeout,
13908 -                                 u32 timer_period)
13909 -{
13910 -       ath9k_hw_gen_timer_start(ah, timer, trig_timeout, timer_period);
13911 -
13912 -       if ((ah->imask & ATH9K_INT_GENTIMER) == 0) {
13913 -               ath9k_hw_disable_interrupts(ah);
13914 -               ah->imask |= ATH9K_INT_GENTIMER;
13915 -               ath9k_hw_set_interrupts(ah);
13916 -               ath9k_hw_enable_interrupts(ah);
13917 -       }
13918 -}
13919 -
13920 -static void ath9k_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
13921 -{
13922 -       struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
13923 -
13924 -       ath9k_hw_gen_timer_stop(ah, timer);
13925 -
13926 -       /* if no timer is enabled, turn off interrupt mask */
13927 -       if (timer_table->timer_mask.val == 0) {
13928 -               ath9k_hw_disable_interrupts(ah);
13929 -               ah->imask &= ~ATH9K_INT_GENTIMER;
13930 -               ath9k_hw_set_interrupts(ah);
13931 -               ath9k_hw_enable_interrupts(ah);
13932 -       }
13933 -}
13934 -
13935  static void ath_mci_ftp_adjust(struct ath_softc *sc)
13936  {
13937         struct ath_btcoex *btcoex = &sc->btcoex;
13938 @@ -257,19 +227,9 @@ static void ath_btcoex_period_timer(unsi
13939
13940         spin_unlock_bh(&btcoex->btcoex_lock);
13941
13942 -       /*
13943 -        * btcoex_period is in msec while (btocex/btscan_)no_stomp are in usec,
13944 -        * ensure that we properly convert btcoex_period to usec
13945 -        * for any comparision with (btcoex/btscan_)no_stomp.
13946 -        */
13947 -       if (btcoex->btcoex_period * 1000 != btcoex->btcoex_no_stomp) {
13948 -               if (btcoex->hw_timer_enabled)
13949 -                       ath9k_gen_timer_stop(ah, btcoex->no_stomp_timer);
13950 -
13951 -               ath9k_gen_timer_start(ah, btcoex->no_stomp_timer, timer_period,
13952 -                                     timer_period * 10);
13953 -               btcoex->hw_timer_enabled = true;
13954 -       }
13955 +       if (btcoex->btcoex_period != btcoex->btcoex_no_stomp)
13956 +               mod_timer(&btcoex->no_stomp_timer,
13957 +                        jiffies + msecs_to_jiffies(timer_period));
13958
13959         ath9k_ps_restore(sc);
13960
13961 @@ -282,7 +242,7 @@ skip_hw_wakeup:
13962   * Generic tsf based hw timer which configures weight
13963   * registers to time slice between wlan and bt traffic
13964   */
13965 -static void ath_btcoex_no_stomp_timer(void *arg)
13966 +static void ath_btcoex_no_stomp_timer(unsigned long arg)
13967  {
13968         struct ath_softc *sc = (struct ath_softc *)arg;
13969         struct ath_hw *ah = sc->sc_ah;
13970 @@ -311,24 +271,18 @@ static int ath_init_btcoex_timer(struct
13971         struct ath_btcoex *btcoex = &sc->btcoex;
13972
13973         btcoex->btcoex_period = ATH_BTCOEX_DEF_BT_PERIOD;
13974 -       btcoex->btcoex_no_stomp = (100 - ATH_BTCOEX_DEF_DUTY_CYCLE) * 1000 *
13975 +       btcoex->btcoex_no_stomp = (100 - ATH_BTCOEX_DEF_DUTY_CYCLE) *
13976                 btcoex->btcoex_period / 100;
13977 -       btcoex->btscan_no_stomp = (100 - ATH_BTCOEX_BTSCAN_DUTY_CYCLE) * 1000 *
13978 +       btcoex->btscan_no_stomp = (100 - ATH_BTCOEX_BTSCAN_DUTY_CYCLE) *
13979                                    btcoex->btcoex_period / 100;
13980
13981         setup_timer(&btcoex->period_timer, ath_btcoex_period_timer,
13982                         (unsigned long) sc);
13983 +       setup_timer(&btcoex->no_stomp_timer, ath_btcoex_no_stomp_timer,
13984 +                       (unsigned long) sc);
13985
13986         spin_lock_init(&btcoex->btcoex_lock);
13987
13988 -       btcoex->no_stomp_timer = ath_gen_timer_alloc(sc->sc_ah,
13989 -                       ath_btcoex_no_stomp_timer,
13990 -                       ath_btcoex_no_stomp_timer,
13991 -                       (void *) sc, AR_FIRST_NDP_TIMER);
13992 -
13993 -       if (!btcoex->no_stomp_timer)
13994 -               return -ENOMEM;
13995 -
13996         return 0;
13997  }
13998
13999 @@ -343,10 +297,7 @@ void ath9k_btcoex_timer_resume(struct at
14000         ath_dbg(ath9k_hw_common(ah), BTCOEX, "Starting btcoex timers\n");
14001
14002         /* make sure duty cycle timer is also stopped when resuming */
14003 -       if (btcoex->hw_timer_enabled) {
14004 -               ath9k_gen_timer_stop(sc->sc_ah, btcoex->no_stomp_timer);
14005 -               btcoex->hw_timer_enabled = false;
14006 -       }
14007 +       del_timer_sync(&btcoex->no_stomp_timer);
14008
14009         btcoex->bt_priority_cnt = 0;
14010         btcoex->bt_priority_time = jiffies;
14011 @@ -363,24 +314,16 @@ void ath9k_btcoex_timer_resume(struct at
14012  void ath9k_btcoex_timer_pause(struct ath_softc *sc)
14013  {
14014         struct ath_btcoex *btcoex = &sc->btcoex;
14015 -       struct ath_hw *ah = sc->sc_ah;
14016
14017         del_timer_sync(&btcoex->period_timer);
14018 -
14019 -       if (btcoex->hw_timer_enabled) {
14020 -               ath9k_gen_timer_stop(ah, btcoex->no_stomp_timer);
14021 -               btcoex->hw_timer_enabled = false;
14022 -       }
14023 +       del_timer_sync(&btcoex->no_stomp_timer);
14024  }
14025
14026  void ath9k_btcoex_stop_gen_timer(struct ath_softc *sc)
14027  {
14028         struct ath_btcoex *btcoex = &sc->btcoex;
14029
14030 -       if (btcoex->hw_timer_enabled) {
14031 -               ath9k_gen_timer_stop(sc->sc_ah, btcoex->no_stomp_timer);
14032 -               btcoex->hw_timer_enabled = false;
14033 -       }
14034 +       del_timer_sync(&btcoex->no_stomp_timer);
14035  }
14036
14037  u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc, u32 max_4ms_framelen)
14038 @@ -400,12 +343,6 @@ u16 ath9k_btcoex_aggr_limit(struct ath_s
14039
14040  void ath9k_btcoex_handle_interrupt(struct ath_softc *sc, u32 status)
14041  {
14042 -       struct ath_hw *ah = sc->sc_ah;
14043 -
14044 -       if (ath9k_hw_get_btcoex_scheme(ah) == ATH_BTCOEX_CFG_3WIRE)
14045 -               if (status & ATH9K_INT_GENTIMER)
14046 -                       ath_gen_timer_isr(sc->sc_ah);
14047 -
14048         if (status & ATH9K_INT_MCI)
14049                 ath_mci_intr(sc);
14050  }
14051 @@ -447,10 +384,6 @@ void ath9k_deinit_btcoex(struct ath_soft
14052  {
14053         struct ath_hw *ah = sc->sc_ah;
14054
14055 -        if ((sc->btcoex.no_stomp_timer) &&
14056 -           ath9k_hw_get_btcoex_scheme(sc->sc_ah) == ATH_BTCOEX_CFG_3WIRE)
14057 -               ath_gen_timer_free(sc->sc_ah, sc->btcoex.no_stomp_timer);
14058 -
14059         if (ath9k_hw_mci_is_enabled(ah))
14060                 ath_mci_cleanup(sc);
14061  }
14062 --- a/drivers/net/wireless/ath/ath9k/htc_drv_beacon.c
14063 +++ b/drivers/net/wireless/ath/ath9k/htc_drv_beacon.c
14064 @@ -70,11 +70,11 @@ static void ath9k_htc_beacon_config_sta(
14065         struct ath9k_beacon_state bs;
14066         enum ath9k_int imask = 0;
14067         int dtimperiod, dtimcount, sleepduration;
14068 -       int cfpperiod, cfpcount, bmiss_timeout;
14069 +       int bmiss_timeout;
14070         u32 nexttbtt = 0, intval, tsftu;
14071         __be32 htc_imask = 0;
14072         u64 tsf;
14073 -       int num_beacons, offset, dtim_dec_count, cfp_dec_count;
14074 +       int num_beacons, offset, dtim_dec_count;
14075         int ret __attribute__ ((unused));
14076         u8 cmd_rsp;
14077
14078 @@ -84,7 +84,7 @@ static void ath9k_htc_beacon_config_sta(
14079         bmiss_timeout = (ATH_DEFAULT_BMISS_LIMIT * bss_conf->beacon_interval);
14080
14081         /*
14082 -        * Setup dtim and cfp parameters according to
14083 +        * Setup dtim parameters according to
14084          * last beacon we received (which may be none).
14085          */
14086         dtimperiod = bss_conf->dtim_period;
14087 @@ -93,8 +93,6 @@ static void ath9k_htc_beacon_config_sta(
14088         dtimcount = 1;
14089         if (dtimcount >= dtimperiod)    /* NB: sanity check */
14090                 dtimcount = 0;
14091 -       cfpperiod = 1;                  /* NB: no PCF support yet */
14092 -       cfpcount = 0;
14093
14094         sleepduration = intval;
14095         if (sleepduration <= 0)
14096 @@ -102,7 +100,7 @@ static void ath9k_htc_beacon_config_sta(
14097
14098         /*
14099          * Pull nexttbtt forward to reflect the current
14100 -        * TSF and calculate dtim+cfp state for the result.
14101 +        * TSF and calculate dtim state for the result.
14102          */
14103         tsf = ath9k_hw_gettsf64(priv->ah);
14104         tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE;
14105 @@ -115,26 +113,14 @@ static void ath9k_htc_beacon_config_sta(
14106
14107         /* DTIM Beacon every dtimperiod Beacon */
14108         dtim_dec_count = num_beacons % dtimperiod;
14109 -       /* CFP every cfpperiod DTIM Beacon */
14110 -       cfp_dec_count = (num_beacons / dtimperiod) % cfpperiod;
14111 -       if (dtim_dec_count)
14112 -               cfp_dec_count++;
14113 -
14114         dtimcount -= dtim_dec_count;
14115         if (dtimcount < 0)
14116                 dtimcount += dtimperiod;
14117
14118 -       cfpcount -= cfp_dec_count;
14119 -       if (cfpcount < 0)
14120 -               cfpcount += cfpperiod;
14121 -
14122 -       bs.bs_intval = intval;
14123 -       bs.bs_nexttbtt = nexttbtt;
14124 -       bs.bs_dtimperiod = dtimperiod*intval;
14125 -       bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval;
14126 -       bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod;
14127 -       bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod;
14128 -       bs.bs_cfpmaxduration = 0;
14129 +       bs.bs_intval = TU_TO_USEC(intval);
14130 +       bs.bs_nexttbtt = TU_TO_USEC(nexttbtt);
14131 +       bs.bs_dtimperiod = dtimperiod * bs.bs_intval;
14132 +       bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount * bs.bs_intval;
14133
14134         /*
14135          * Calculate the number of consecutive beacons to miss* before taking
14136 @@ -161,7 +147,8 @@ static void ath9k_htc_beacon_config_sta(
14137          * XXX fixed at 100ms
14138          */
14139
14140 -       bs.bs_sleepduration = roundup(IEEE80211_MS_TO_TU(100), sleepduration);
14141 +       bs.bs_sleepduration = TU_TO_USEC(roundup(IEEE80211_MS_TO_TU(100),
14142 +                                                sleepduration));
14143         if (bs.bs_sleepduration > bs.bs_dtimperiod)
14144                 bs.bs_sleepduration = bs.bs_dtimperiod;
14145
14146 @@ -170,10 +157,8 @@ static void ath9k_htc_beacon_config_sta(
14147
14148         ath_dbg(common, CONFIG, "intval: %u tsf: %llu tsftu: %u\n",
14149                 intval, tsf, tsftu);
14150 -       ath_dbg(common, CONFIG,
14151 -               "bmiss: %u sleep: %u cfp-period: %u maxdur: %u next: %u\n",
14152 -               bs.bs_bmissthreshold, bs.bs_sleepduration,
14153 -               bs.bs_cfpperiod, bs.bs_cfpmaxduration, bs.bs_cfpnext);
14154 +       ath_dbg(common, CONFIG, "bmiss: %u sleep: %u\n",
14155 +               bs.bs_bmissthreshold, bs.bs_sleepduration);
14156
14157         /* Set the computed STA beacon timers */
14158
14159 --- a/drivers/net/wireless/ath/ath9k/mac.c
14160 +++ b/drivers/net/wireless/ath/ath9k/mac.c
14161 @@ -481,8 +481,7 @@ bool ath9k_hw_resettxqueue(struct ath_hw
14162                             | AR_Q_MISC_CBR_INCR_DIS0);
14163                 value = (qi->tqi_readyTime -
14164                          (ah->config.sw_beacon_response_time -
14165 -                         ah->config.dma_beacon_response_time) -
14166 -                        ah->config.additional_swba_backoff) * 1024;
14167 +                         ah->config.dma_beacon_response_time)) * 1024;
14168                 REG_WRITE(ah, AR_QRDYTIMECFG(q),
14169                           value | AR_Q_RDYTIMECFG_EN);
14170                 REG_SET_BIT(ah, AR_DMISC(q),
14171 @@ -550,25 +549,25 @@ int ath9k_hw_rxprocdesc(struct ath_hw *a
14172
14173         if (ads.ds_rxstatus8 & AR_PostDelimCRCErr) {
14174                 rs->rs_rssi = ATH9K_RSSI_BAD;
14175 -               rs->rs_rssi_ctl0 = ATH9K_RSSI_BAD;
14176 -               rs->rs_rssi_ctl1 = ATH9K_RSSI_BAD;
14177 -               rs->rs_rssi_ctl2 = ATH9K_RSSI_BAD;
14178 -               rs->rs_rssi_ext0 = ATH9K_RSSI_BAD;
14179 -               rs->rs_rssi_ext1 = ATH9K_RSSI_BAD;
14180 -               rs->rs_rssi_ext2 = ATH9K_RSSI_BAD;
14181 +               rs->rs_rssi_ctl[0] = ATH9K_RSSI_BAD;
14182 +               rs->rs_rssi_ctl[1] = ATH9K_RSSI_BAD;
14183 +               rs->rs_rssi_ctl[2] = ATH9K_RSSI_BAD;
14184 +               rs->rs_rssi_ext[0] = ATH9K_RSSI_BAD;
14185 +               rs->rs_rssi_ext[1] = ATH9K_RSSI_BAD;
14186 +               rs->rs_rssi_ext[2] = ATH9K_RSSI_BAD;
14187         } else {
14188                 rs->rs_rssi = MS(ads.ds_rxstatus4, AR_RxRSSICombined);
14189 -               rs->rs_rssi_ctl0 = MS(ads.ds_rxstatus0,
14190 +               rs->rs_rssi_ctl[0] = MS(ads.ds_rxstatus0,
14191                                                 AR_RxRSSIAnt00);
14192 -               rs->rs_rssi_ctl1 = MS(ads.ds_rxstatus0,
14193 +               rs->rs_rssi_ctl[1] = MS(ads.ds_rxstatus0,
14194                                                 AR_RxRSSIAnt01);
14195 -               rs->rs_rssi_ctl2 = MS(ads.ds_rxstatus0,
14196 +               rs->rs_rssi_ctl[2] = MS(ads.ds_rxstatus0,
14197                                                 AR_RxRSSIAnt02);
14198 -               rs->rs_rssi_ext0 = MS(ads.ds_rxstatus4,
14199 +               rs->rs_rssi_ext[0] = MS(ads.ds_rxstatus4,
14200                                                 AR_RxRSSIAnt10);
14201 -               rs->rs_rssi_ext1 = MS(ads.ds_rxstatus4,
14202 +               rs->rs_rssi_ext[1] = MS(ads.ds_rxstatus4,
14203                                                 AR_RxRSSIAnt11);
14204 -               rs->rs_rssi_ext2 = MS(ads.ds_rxstatus4,
14205 +               rs->rs_rssi_ext[2] = MS(ads.ds_rxstatus4,
14206                                                 AR_RxRSSIAnt12);
14207         }
14208         if (ads.ds_rxstatus8 & AR_RxKeyIdxValid)
14209 --- a/drivers/net/wireless/ath/ath9k/mac.h
14210 +++ b/drivers/net/wireless/ath/ath9k/mac.h
14211 @@ -133,12 +133,8 @@ struct ath_rx_status {
14212         u8 rs_rate;
14213         u8 rs_antenna;
14214         u8 rs_more;
14215 -       int8_t rs_rssi_ctl0;
14216 -       int8_t rs_rssi_ctl1;
14217 -       int8_t rs_rssi_ctl2;
14218 -       int8_t rs_rssi_ext0;
14219 -       int8_t rs_rssi_ext1;
14220 -       int8_t rs_rssi_ext2;
14221 +       int8_t rs_rssi_ctl[3];
14222 +       int8_t rs_rssi_ext[3];
14223         u8 rs_isaggr;
14224         u8 rs_firstaggr;
14225         u8 rs_moreaggr;
14226 --- a/drivers/net/wireless/ath/ath9k/mci.c
14227 +++ b/drivers/net/wireless/ath/ath9k/mci.c
14228 @@ -200,7 +200,7 @@ skip_tuning:
14229         if (btcoex->duty_cycle > ATH_MCI_MAX_DUTY_CYCLE)
14230                 btcoex->duty_cycle = ATH_MCI_MAX_DUTY_CYCLE;
14231
14232 -       btcoex->btcoex_no_stomp =  btcoex->btcoex_period * 1000 *
14233 +       btcoex->btcoex_no_stomp =  btcoex->btcoex_period *
14234                 (100 - btcoex->duty_cycle) / 100;
14235
14236         ath9k_hw_btcoex_enable(sc->sc_ah);
14237 --- a/drivers/net/wireless/ath/ath9k/recv.c
14238 +++ b/drivers/net/wireless/ath/ath9k/recv.c
14239 @@ -15,7 +15,6 @@
14240   */
14241
14242  #include <linux/dma-mapping.h>
14243 -#include <linux/relay.h>
14244  #include "ath9k.h"
14245  #include "ar9003_mac.h"
14246
14247 @@ -906,6 +905,7 @@ static void ath9k_process_rssi(struct at
14248         struct ath_hw *ah = common->ah;
14249         int last_rssi;
14250         int rssi = rx_stats->rs_rssi;
14251 +       int i, j;
14252
14253         /*
14254          * RSSI is not available for subframes in an A-MPDU.
14255 @@ -924,6 +924,20 @@ static void ath9k_process_rssi(struct at
14256                 return;
14257         }
14258
14259 +       for (i = 0, j = 0; i < ARRAY_SIZE(rx_stats->rs_rssi_ctl); i++) {
14260 +               s8 rssi;
14261 +
14262 +               if (!(ah->rxchainmask & BIT(i)))
14263 +                       continue;
14264 +
14265 +               rssi = rx_stats->rs_rssi_ctl[i];
14266 +               if (rssi != ATH9K_RSSI_BAD) {
14267 +                   rxs->chains |= BIT(j);
14268 +                   rxs->chain_signal[j] = ah->noise + rssi;
14269 +               }
14270 +               j++;
14271 +       }
14272 +
14273         /*
14274          * Update Beacon RSSI, this is used by ANI.
14275          */
14276 @@ -960,186 +974,6 @@ static void ath9k_process_tsf(struct ath
14277                 rxs->mactime += 0x100000000ULL;
14278  }
14279
14280 -#ifdef CPTCFG_ATH9K_DEBUGFS
14281 -static s8 fix_rssi_inv_only(u8 rssi_val)
14282 -{
14283 -       if (rssi_val == 128)
14284 -               rssi_val = 0;
14285 -       return (s8) rssi_val;
14286 -}
14287 -#endif
14288 -
14289 -/* returns 1 if this was a spectral frame, even if not handled. */
14290 -static int ath_process_fft(struct ath_softc *sc, struct ieee80211_hdr *hdr,
14291 -                          struct ath_rx_status *rs, u64 tsf)
14292 -{
14293 -#ifdef CPTCFG_ATH9K_DEBUGFS
14294 -       struct ath_hw *ah = sc->sc_ah;
14295 -       u8 num_bins, *bins, *vdata = (u8 *)hdr;
14296 -       struct fft_sample_ht20 fft_sample_20;
14297 -       struct fft_sample_ht20_40 fft_sample_40;
14298 -       struct fft_sample_tlv *tlv;
14299 -       struct ath_radar_info *radar_info;
14300 -       int len = rs->rs_datalen;
14301 -       int dc_pos;
14302 -       u16 fft_len, length, freq = ah->curchan->chan->center_freq;
14303 -       enum nl80211_channel_type chan_type;
14304 -
14305 -       /* AR9280 and before report via ATH9K_PHYERR_RADAR, AR93xx and newer
14306 -        * via ATH9K_PHYERR_SPECTRAL. Haven't seen ATH9K_PHYERR_FALSE_RADAR_EXT
14307 -        * yet, but this is supposed to be possible as well.
14308 -        */
14309 -       if (rs->rs_phyerr != ATH9K_PHYERR_RADAR &&
14310 -           rs->rs_phyerr != ATH9K_PHYERR_FALSE_RADAR_EXT &&
14311 -           rs->rs_phyerr != ATH9K_PHYERR_SPECTRAL)
14312 -               return 0;
14313 -
14314 -       /* check if spectral scan bit is set. This does not have to be checked
14315 -        * if received through a SPECTRAL phy error, but shouldn't hurt.
14316 -        */
14317 -       radar_info = ((struct ath_radar_info *)&vdata[len]) - 1;
14318 -       if (!(radar_info->pulse_bw_info & SPECTRAL_SCAN_BITMASK))
14319 -               return 0;
14320 -
14321 -       chan_type = cfg80211_get_chandef_type(&sc->hw->conf.chandef);
14322 -       if ((chan_type == NL80211_CHAN_HT40MINUS) ||
14323 -           (chan_type == NL80211_CHAN_HT40PLUS)) {
14324 -               fft_len = SPECTRAL_HT20_40_TOTAL_DATA_LEN;
14325 -               num_bins = SPECTRAL_HT20_40_NUM_BINS;
14326 -               bins = (u8 *)fft_sample_40.data;
14327 -       } else {
14328 -               fft_len = SPECTRAL_HT20_TOTAL_DATA_LEN;
14329 -               num_bins = SPECTRAL_HT20_NUM_BINS;
14330 -               bins = (u8 *)fft_sample_20.data;
14331 -       }
14332 -
14333 -       /* Variation in the data length is possible and will be fixed later */
14334 -       if ((len > fft_len + 2) || (len < fft_len - 1))
14335 -               return 1;
14336 -
14337 -       switch (len - fft_len) {
14338 -       case 0:
14339 -               /* length correct, nothing to do. */
14340 -               memcpy(bins, vdata, num_bins);
14341 -               break;
14342 -       case -1:
14343 -               /* first byte missing, duplicate it. */
14344 -               memcpy(&bins[1], vdata, num_bins - 1);
14345 -               bins[0] = vdata[0];
14346 -               break;
14347 -       case 2:
14348 -               /* MAC added 2 extra bytes at bin 30 and 32, remove them. */
14349 -               memcpy(bins, vdata, 30);
14350 -               bins[30] = vdata[31];
14351 -               memcpy(&bins[31], &vdata[33], num_bins - 31);
14352 -               break;
14353 -       case 1:
14354 -               /* MAC added 2 extra bytes AND first byte is missing. */
14355 -               bins[0] = vdata[0];
14356 -               memcpy(&bins[1], vdata, 30);
14357 -               bins[31] = vdata[31];
14358 -               memcpy(&bins[32], &vdata[33], num_bins - 32);
14359 -               break;
14360 -       default:
14361 -               return 1;
14362 -       }
14363 -
14364 -       /* DC value (value in the middle) is the blind spot of the spectral
14365 -        * sample and invalid, interpolate it.
14366 -        */
14367 -       dc_pos = num_bins / 2;
14368 -       bins[dc_pos] = (bins[dc_pos + 1] + bins[dc_pos - 1]) / 2;
14369 -
14370 -       if ((chan_type == NL80211_CHAN_HT40MINUS) ||
14371 -           (chan_type == NL80211_CHAN_HT40PLUS)) {
14372 -               s8 lower_rssi, upper_rssi;
14373 -               s16 ext_nf;
14374 -               u8 lower_max_index, upper_max_index;
14375 -               u8 lower_bitmap_w, upper_bitmap_w;
14376 -               u16 lower_mag, upper_mag;
14377 -               struct ath9k_hw_cal_data *caldata = ah->caldata;
14378 -               struct ath_ht20_40_mag_info *mag_info;
14379 -
14380 -               if (caldata)
14381 -                       ext_nf = ath9k_hw_getchan_noise(ah, ah->curchan,
14382 -                                       caldata->nfCalHist[3].privNF);
14383 -               else
14384 -                       ext_nf = ATH_DEFAULT_NOISE_FLOOR;
14385 -
14386 -               length = sizeof(fft_sample_40) - sizeof(struct fft_sample_tlv);
14387 -               fft_sample_40.tlv.type = ATH_FFT_SAMPLE_HT20_40;
14388 -               fft_sample_40.tlv.length = __cpu_to_be16(length);
14389 -               fft_sample_40.freq = __cpu_to_be16(freq);
14390 -               fft_sample_40.channel_type = chan_type;
14391 -
14392 -               if (chan_type == NL80211_CHAN_HT40PLUS) {
14393 -                       lower_rssi = fix_rssi_inv_only(rs->rs_rssi_ctl0);
14394 -                       upper_rssi = fix_rssi_inv_only(rs->rs_rssi_ext0);
14395 -
14396 -                       fft_sample_40.lower_noise = ah->noise;
14397 -                       fft_sample_40.upper_noise = ext_nf;
14398 -               } else {
14399 -                       lower_rssi = fix_rssi_inv_only(rs->rs_rssi_ext0);
14400 -                       upper_rssi = fix_rssi_inv_only(rs->rs_rssi_ctl0);
14401 -
14402 -                       fft_sample_40.lower_noise = ext_nf;
14403 -                       fft_sample_40.upper_noise = ah->noise;
14404 -               }
14405 -               fft_sample_40.lower_rssi = lower_rssi;
14406 -               fft_sample_40.upper_rssi = upper_rssi;
14407 -
14408 -               mag_info = ((struct ath_ht20_40_mag_info *)radar_info) - 1;
14409 -               lower_mag = spectral_max_magnitude(mag_info->lower_bins);
14410 -               upper_mag = spectral_max_magnitude(mag_info->upper_bins);
14411 -               fft_sample_40.lower_max_magnitude = __cpu_to_be16(lower_mag);
14412 -               fft_sample_40.upper_max_magnitude = __cpu_to_be16(upper_mag);
14413 -               lower_max_index = spectral_max_index(mag_info->lower_bins);
14414 -               upper_max_index = spectral_max_index(mag_info->upper_bins);
14415 -               fft_sample_40.lower_max_index = lower_max_index;
14416 -               fft_sample_40.upper_max_index = upper_max_index;
14417 -               lower_bitmap_w = spectral_bitmap_weight(mag_info->lower_bins);
14418 -               upper_bitmap_w = spectral_bitmap_weight(mag_info->upper_bins);
14419 -               fft_sample_40.lower_bitmap_weight = lower_bitmap_w;
14420 -               fft_sample_40.upper_bitmap_weight = upper_bitmap_w;
14421 -               fft_sample_40.max_exp = mag_info->max_exp & 0xf;
14422 -
14423 -               fft_sample_40.tsf = __cpu_to_be64(tsf);
14424 -
14425 -               tlv = (struct fft_sample_tlv *)&fft_sample_40;
14426 -       } else {
14427 -               u8 max_index, bitmap_w;
14428 -               u16 magnitude;
14429 -               struct ath_ht20_mag_info *mag_info;
14430 -
14431 -               length = sizeof(fft_sample_20) - sizeof(struct fft_sample_tlv);
14432 -               fft_sample_20.tlv.type = ATH_FFT_SAMPLE_HT20;
14433 -               fft_sample_20.tlv.length = __cpu_to_be16(length);
14434 -               fft_sample_20.freq = __cpu_to_be16(freq);
14435 -
14436 -               fft_sample_20.rssi = fix_rssi_inv_only(rs->rs_rssi_ctl0);
14437 -               fft_sample_20.noise = ah->noise;
14438 -
14439 -               mag_info = ((struct ath_ht20_mag_info *)radar_info) - 1;
14440 -               magnitude = spectral_max_magnitude(mag_info->all_bins);
14441 -               fft_sample_20.max_magnitude = __cpu_to_be16(magnitude);
14442 -               max_index = spectral_max_index(mag_info->all_bins);
14443 -               fft_sample_20.max_index = max_index;
14444 -               bitmap_w = spectral_bitmap_weight(mag_info->all_bins);
14445 -               fft_sample_20.bitmap_weight = bitmap_w;
14446 -               fft_sample_20.max_exp = mag_info->max_exp & 0xf;
14447 -
14448 -               fft_sample_20.tsf = __cpu_to_be64(tsf);
14449 -
14450 -               tlv = (struct fft_sample_tlv *)&fft_sample_20;
14451 -       }
14452 -
14453 -       ath_debug_send_fft_sample(sc, tlv);
14454 -       return 1;
14455 -#else
14456 -       return 0;
14457 -#endif
14458 -}
14459 -
14460  static bool ath9k_is_mybeacon(struct ath_softc *sc, struct ieee80211_hdr *hdr)
14461  {
14462         struct ath_hw *ah = sc->sc_ah;
14463 --- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
14464 +++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
14465 @@ -270,10 +270,20 @@ struct cal_ctl_data_5g {
14466         u8 ctlEdges[AR9300_NUM_BAND_EDGES_5G];
14467  } __packed;
14468
14469 +#define MAX_BASE_EXTENSION_FUTURE 2
14470 +
14471  struct ar9300_BaseExtension_1 {
14472         u8 ant_div_control;
14473 -       u8 future[3];
14474 -       u8 tempslopextension[8];
14475 +       u8 future[MAX_BASE_EXTENSION_FUTURE];
14476 +       /*
14477 +        * misc_enable:
14478 +        *
14479 +        * BIT 0   - TX Gain Cap enable.
14480 +        * BIT 1   - Uncompressed Checksum enable.
14481 +        * BIT 2/3 - MinCCApwr enable 2g/5g.
14482 +        */
14483 +       u8 misc_enable;
14484 +       int8_t tempslopextension[8];
14485         int8_t quick_drop_low;
14486         int8_t quick_drop_high;
14487  } __packed;
14488 --- a/drivers/net/wireless/ath/ath9k/debug.h
14489 +++ b/drivers/net/wireless/ath/ath9k/debug.h
14490 @@ -292,11 +292,11 @@ void ath9k_sta_add_debugfs(struct ieee80
14491                            struct ieee80211_vif *vif,
14492                            struct ieee80211_sta *sta,
14493                            struct dentry *dir);
14494 -void ath_debug_send_fft_sample(struct ath_softc *sc,
14495 -                              struct fft_sample_tlv *fft_sample);
14496  void ath9k_debug_stat_ant(struct ath_softc *sc,
14497                           struct ath_hw_antcomb_conf *div_ant_conf,
14498                           int main_rssi_avg, int alt_rssi_avg);
14499 +void ath9k_debug_sync_cause(struct ath_softc *sc, u32 sync_cause);
14500 +
14501  #else
14502
14503  #define RX_STAT_INC(c) /* NOP */
14504 @@ -331,6 +331,11 @@ static inline void ath9k_debug_stat_ant(
14505
14506  }
14507
14508 +static inline void
14509 +ath9k_debug_sync_cause(struct ath_softc *sc, u32 sync_cause)
14510 +{
14511 +}
14512 +
14513  #endif /* CPTCFG_ATH9K_DEBUGFS */
14514
14515  #endif /* DEBUG_H */
14516 --- /dev/null
14517 +++ b/drivers/net/wireless/ath/ath9k/spectral.c
14518 @@ -0,0 +1,543 @@
14519 +/*
14520 + * Copyright (c) 2013 Qualcomm Atheros, Inc.
14521 + *
14522 + * Permission to use, copy, modify, and/or distribute this software for any
14523 + * purpose with or without fee is hereby granted, provided that the above
14524 + * copyright notice and this permission notice appear in all copies.
14525 + *
14526 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14527 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14528 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14529 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14530 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14531 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14532 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
14533 + */
14534 +
14535 +#include <linux/relay.h>
14536 +#include "ath9k.h"
14537 +
14538 +static s8 fix_rssi_inv_only(u8 rssi_val)
14539 +{
14540 +       if (rssi_val == 128)
14541 +               rssi_val = 0;
14542 +       return (s8) rssi_val;
14543 +}
14544 +
14545 +static void ath_debug_send_fft_sample(struct ath_softc *sc,
14546 +                                     struct fft_sample_tlv *fft_sample_tlv)
14547 +{
14548 +       int length;
14549 +       if (!sc->rfs_chan_spec_scan)
14550 +               return;
14551 +
14552 +       length = __be16_to_cpu(fft_sample_tlv->length) +
14553 +                sizeof(*fft_sample_tlv);
14554 +       relay_write(sc->rfs_chan_spec_scan, fft_sample_tlv, length);
14555 +}
14556 +
14557 +/* returns 1 if this was a spectral frame, even if not handled. */
14558 +int ath_process_fft(struct ath_softc *sc, struct ieee80211_hdr *hdr,
14559 +                   struct ath_rx_status *rs, u64 tsf)
14560 +{
14561 +       struct ath_hw *ah = sc->sc_ah;
14562 +       u8 num_bins, *bins, *vdata = (u8 *)hdr;
14563 +       struct fft_sample_ht20 fft_sample_20;
14564 +       struct fft_sample_ht20_40 fft_sample_40;
14565 +       struct fft_sample_tlv *tlv;
14566 +       struct ath_radar_info *radar_info;
14567 +       int len = rs->rs_datalen;
14568 +       int dc_pos;
14569 +       u16 fft_len, length, freq = ah->curchan->chan->center_freq;
14570 +       enum nl80211_channel_type chan_type;
14571 +
14572 +       /* AR9280 and before report via ATH9K_PHYERR_RADAR, AR93xx and newer
14573 +        * via ATH9K_PHYERR_SPECTRAL. Haven't seen ATH9K_PHYERR_FALSE_RADAR_EXT
14574 +        * yet, but this is supposed to be possible as well.
14575 +        */
14576 +       if (rs->rs_phyerr != ATH9K_PHYERR_RADAR &&
14577 +           rs->rs_phyerr != ATH9K_PHYERR_FALSE_RADAR_EXT &&
14578 +           rs->rs_phyerr != ATH9K_PHYERR_SPECTRAL)
14579 +               return 0;
14580 +
14581 +       /* check if spectral scan bit is set. This does not have to be checked
14582 +        * if received through a SPECTRAL phy error, but shouldn't hurt.
14583 +        */
14584 +       radar_info = ((struct ath_radar_info *)&vdata[len]) - 1;
14585 +       if (!(radar_info->pulse_bw_info & SPECTRAL_SCAN_BITMASK))
14586 +               return 0;
14587 +
14588 +       chan_type = cfg80211_get_chandef_type(&sc->hw->conf.chandef);
14589 +       if ((chan_type == NL80211_CHAN_HT40MINUS) ||
14590 +           (chan_type == NL80211_CHAN_HT40PLUS)) {
14591 +               fft_len = SPECTRAL_HT20_40_TOTAL_DATA_LEN;
14592 +               num_bins = SPECTRAL_HT20_40_NUM_BINS;
14593 +               bins = (u8 *)fft_sample_40.data;
14594 +       } else {
14595 +               fft_len = SPECTRAL_HT20_TOTAL_DATA_LEN;
14596 +               num_bins = SPECTRAL_HT20_NUM_BINS;
14597 +               bins = (u8 *)fft_sample_20.data;
14598 +       }
14599 +
14600 +       /* Variation in the data length is possible and will be fixed later */
14601 +       if ((len > fft_len + 2) || (len < fft_len - 1))
14602 +               return 1;
14603 +
14604 +       switch (len - fft_len) {
14605 +       case 0:
14606 +               /* length correct, nothing to do. */
14607 +               memcpy(bins, vdata, num_bins);
14608 +               break;
14609 +       case -1:
14610 +               /* first byte missing, duplicate it. */
14611 +               memcpy(&bins[1], vdata, num_bins - 1);
14612 +               bins[0] = vdata[0];
14613 +               break;
14614 +       case 2:
14615 +               /* MAC added 2 extra bytes at bin 30 and 32, remove them. */
14616 +               memcpy(bins, vdata, 30);
14617 +               bins[30] = vdata[31];
14618 +               memcpy(&bins[31], &vdata[33], num_bins - 31);
14619 +               break;
14620 +       case 1:
14621 +               /* MAC added 2 extra bytes AND first byte is missing. */
14622 +               bins[0] = vdata[0];
14623 +               memcpy(&bins[1], vdata, 30);
14624 +               bins[31] = vdata[31];
14625 +               memcpy(&bins[32], &vdata[33], num_bins - 32);
14626 +               break;
14627 +       default:
14628 +               return 1;
14629 +       }
14630 +
14631 +       /* DC value (value in the middle) is the blind spot of the spectral
14632 +        * sample and invalid, interpolate it.
14633 +        */
14634 +       dc_pos = num_bins / 2;
14635 +       bins[dc_pos] = (bins[dc_pos + 1] + bins[dc_pos - 1]) / 2;
14636 +
14637 +       if ((chan_type == NL80211_CHAN_HT40MINUS) ||
14638 +           (chan_type == NL80211_CHAN_HT40PLUS)) {
14639 +               s8 lower_rssi, upper_rssi;
14640 +               s16 ext_nf;
14641 +               u8 lower_max_index, upper_max_index;
14642 +               u8 lower_bitmap_w, upper_bitmap_w;
14643 +               u16 lower_mag, upper_mag;
14644 +               struct ath9k_hw_cal_data *caldata = ah->caldata;
14645 +               struct ath_ht20_40_mag_info *mag_info;
14646 +
14647 +               if (caldata)
14648 +                       ext_nf = ath9k_hw_getchan_noise(ah, ah->curchan,
14649 +                                       caldata->nfCalHist[3].privNF);
14650 +               else
14651 +                       ext_nf = ATH_DEFAULT_NOISE_FLOOR;
14652 +
14653 +               length = sizeof(fft_sample_40) - sizeof(struct fft_sample_tlv);
14654 +               fft_sample_40.tlv.type = ATH_FFT_SAMPLE_HT20_40;
14655 +               fft_sample_40.tlv.length = __cpu_to_be16(length);
14656 +               fft_sample_40.freq = __cpu_to_be16(freq);
14657 +               fft_sample_40.channel_type = chan_type;
14658 +
14659 +               if (chan_type == NL80211_CHAN_HT40PLUS) {
14660 +                       lower_rssi = fix_rssi_inv_only(rs->rs_rssi_ctl[0]);
14661 +                       upper_rssi = fix_rssi_inv_only(rs->rs_rssi_ext[0]);
14662 +
14663 +                       fft_sample_40.lower_noise = ah->noise;
14664 +                       fft_sample_40.upper_noise = ext_nf;
14665 +               } else {
14666 +                       lower_rssi = fix_rssi_inv_only(rs->rs_rssi_ext[0]);
14667 +                       upper_rssi = fix_rssi_inv_only(rs->rs_rssi_ctl[0]);
14668 +
14669 +                       fft_sample_40.lower_noise = ext_nf;
14670 +                       fft_sample_40.upper_noise = ah->noise;
14671 +               }
14672 +               fft_sample_40.lower_rssi = lower_rssi;
14673 +               fft_sample_40.upper_rssi = upper_rssi;
14674 +
14675 +               mag_info = ((struct ath_ht20_40_mag_info *)radar_info) - 1;
14676 +               lower_mag = spectral_max_magnitude(mag_info->lower_bins);
14677 +               upper_mag = spectral_max_magnitude(mag_info->upper_bins);
14678 +               fft_sample_40.lower_max_magnitude = __cpu_to_be16(lower_mag);
14679 +               fft_sample_40.upper_max_magnitude = __cpu_to_be16(upper_mag);
14680 +               lower_max_index = spectral_max_index(mag_info->lower_bins);
14681 +               upper_max_index = spectral_max_index(mag_info->upper_bins);
14682 +               fft_sample_40.lower_max_index = lower_max_index;
14683 +               fft_sample_40.upper_max_index = upper_max_index;
14684 +               lower_bitmap_w = spectral_bitmap_weight(mag_info->lower_bins);
14685 +               upper_bitmap_w = spectral_bitmap_weight(mag_info->upper_bins);
14686 +               fft_sample_40.lower_bitmap_weight = lower_bitmap_w;
14687 +               fft_sample_40.upper_bitmap_weight = upper_bitmap_w;
14688 +               fft_sample_40.max_exp = mag_info->max_exp & 0xf;
14689 +
14690 +               fft_sample_40.tsf = __cpu_to_be64(tsf);
14691 +
14692 +               tlv = (struct fft_sample_tlv *)&fft_sample_40;
14693 +       } else {
14694 +               u8 max_index, bitmap_w;
14695 +               u16 magnitude;
14696 +               struct ath_ht20_mag_info *mag_info;
14697 +
14698 +               length = sizeof(fft_sample_20) - sizeof(struct fft_sample_tlv);
14699 +               fft_sample_20.tlv.type = ATH_FFT_SAMPLE_HT20;
14700 +               fft_sample_20.tlv.length = __cpu_to_be16(length);
14701 +               fft_sample_20.freq = __cpu_to_be16(freq);
14702 +
14703 +               fft_sample_20.rssi = fix_rssi_inv_only(rs->rs_rssi_ctl[0]);
14704 +               fft_sample_20.noise = ah->noise;
14705 +
14706 +               mag_info = ((struct ath_ht20_mag_info *)radar_info) - 1;
14707 +               magnitude = spectral_max_magnitude(mag_info->all_bins);
14708 +               fft_sample_20.max_magnitude = __cpu_to_be16(magnitude);
14709 +               max_index = spectral_max_index(mag_info->all_bins);
14710 +               fft_sample_20.max_index = max_index;
14711 +               bitmap_w = spectral_bitmap_weight(mag_info->all_bins);
14712 +               fft_sample_20.bitmap_weight = bitmap_w;
14713 +               fft_sample_20.max_exp = mag_info->max_exp & 0xf;
14714 +
14715 +               fft_sample_20.tsf = __cpu_to_be64(tsf);
14716 +
14717 +               tlv = (struct fft_sample_tlv *)&fft_sample_20;
14718 +       }
14719 +
14720 +       ath_debug_send_fft_sample(sc, tlv);
14721 +
14722 +       return 1;
14723 +}
14724 +
14725 +/*********************/
14726 +/* spectral_scan_ctl */
14727 +/*********************/
14728 +
14729 +static ssize_t read_file_spec_scan_ctl(struct file *file, char __user *user_buf,
14730 +                                      size_t count, loff_t *ppos)
14731 +{
14732 +       struct ath_softc *sc = file->private_data;
14733 +       char *mode = "";
14734 +       unsigned int len;
14735 +
14736 +       switch (sc->spectral_mode) {
14737 +       case SPECTRAL_DISABLED:
14738 +               mode = "disable";
14739 +               break;
14740 +       case SPECTRAL_BACKGROUND:
14741 +               mode = "background";
14742 +               break;
14743 +       case SPECTRAL_CHANSCAN:
14744 +               mode = "chanscan";
14745 +               break;
14746 +       case SPECTRAL_MANUAL:
14747 +               mode = "manual";
14748 +               break;
14749 +       }
14750 +       len = strlen(mode);
14751 +       return simple_read_from_buffer(user_buf, count, ppos, mode, len);
14752 +}
14753 +
14754 +static ssize_t write_file_spec_scan_ctl(struct file *file,
14755 +                                       const char __user *user_buf,
14756 +                                       size_t count, loff_t *ppos)
14757 +{
14758 +       struct ath_softc *sc = file->private_data;
14759 +       struct ath_common *common = ath9k_hw_common(sc->sc_ah);
14760 +       char buf[32];
14761 +       ssize_t len;
14762 +
14763 +       if (config_enabled(CPTCFG_ATH9K_TX99))
14764 +               return -EOPNOTSUPP;
14765 +
14766 +       len = min(count, sizeof(buf) - 1);
14767 +       if (copy_from_user(buf, user_buf, len))
14768 +               return -EFAULT;
14769 +
14770 +       buf[len] = '\0';
14771 +
14772 +       if (strncmp("trigger", buf, 7) == 0) {
14773 +               ath9k_spectral_scan_trigger(sc->hw);
14774 +       } else if (strncmp("background", buf, 9) == 0) {
14775 +               ath9k_spectral_scan_config(sc->hw, SPECTRAL_BACKGROUND);
14776 +               ath_dbg(common, CONFIG, "spectral scan: background mode enabled\n");
14777 +       } else if (strncmp("chanscan", buf, 8) == 0) {
14778 +               ath9k_spectral_scan_config(sc->hw, SPECTRAL_CHANSCAN);
14779 +               ath_dbg(common, CONFIG, "spectral scan: channel scan mode enabled\n");
14780 +       } else if (strncmp("manual", buf, 6) == 0) {
14781 +               ath9k_spectral_scan_config(sc->hw, SPECTRAL_MANUAL);
14782 +               ath_dbg(common, CONFIG, "spectral scan: manual mode enabled\n");
14783 +       } else if (strncmp("disable", buf, 7) == 0) {
14784 +               ath9k_spectral_scan_config(sc->hw, SPECTRAL_DISABLED);
14785 +               ath_dbg(common, CONFIG, "spectral scan: disabled\n");
14786 +       } else {
14787 +               return -EINVAL;
14788 +       }
14789 +
14790 +       return count;
14791 +}
14792 +
14793 +static const struct file_operations fops_spec_scan_ctl = {
14794 +       .read = read_file_spec_scan_ctl,
14795 +       .write = write_file_spec_scan_ctl,
14796 +       .open = simple_open,
14797 +       .owner = THIS_MODULE,
14798 +       .llseek = default_llseek,
14799 +};
14800 +
14801 +/*************************/
14802 +/* spectral_short_repeat */
14803 +/*************************/
14804 +
14805 +static ssize_t read_file_spectral_short_repeat(struct file *file,
14806 +                                              char __user *user_buf,
14807 +                                              size_t count, loff_t *ppos)
14808 +{
14809 +       struct ath_softc *sc = file->private_data;
14810 +       char buf[32];
14811 +       unsigned int len;
14812 +
14813 +       len = sprintf(buf, "%d\n", sc->spec_config.short_repeat);
14814 +       return simple_read_from_buffer(user_buf, count, ppos, buf, len);
14815 +}
14816 +
14817 +static ssize_t write_file_spectral_short_repeat(struct file *file,
14818 +                                               const char __user *user_buf,
14819 +                                               size_t count, loff_t *ppos)
14820 +{
14821 +       struct ath_softc *sc = file->private_data;
14822 +       unsigned long val;
14823 +       char buf[32];
14824 +       ssize_t len;
14825 +
14826 +       len = min(count, sizeof(buf) - 1);
14827 +       if (copy_from_user(buf, user_buf, len))
14828 +               return -EFAULT;
14829 +
14830 +       buf[len] = '\0';
14831 +       if (kstrtoul(buf, 0, &val))
14832 +               return -EINVAL;
14833 +
14834 +       if (val < 0 || val > 1)
14835 +               return -EINVAL;
14836 +
14837 +       sc->spec_config.short_repeat = val;
14838 +       return count;
14839 +}
14840 +
14841 +static const struct file_operations fops_spectral_short_repeat = {
14842 +       .read = read_file_spectral_short_repeat,
14843 +       .write = write_file_spectral_short_repeat,
14844 +       .open = simple_open,
14845 +       .owner = THIS_MODULE,
14846 +       .llseek = default_llseek,
14847 +};
14848 +
14849 +/******************/
14850 +/* spectral_count */
14851 +/******************/
14852 +
14853 +static ssize_t read_file_spectral_count(struct file *file,
14854 +                                       char __user *user_buf,
14855 +                                       size_t count, loff_t *ppos)
14856 +{
14857 +       struct ath_softc *sc = file->private_data;
14858 +       char buf[32];
14859 +       unsigned int len;
14860 +
14861 +       len = sprintf(buf, "%d\n", sc->spec_config.count);
14862 +       return simple_read_from_buffer(user_buf, count, ppos, buf, len);
14863 +}
14864 +
14865 +static ssize_t write_file_spectral_count(struct file *file,
14866 +                                        const char __user *user_buf,
14867 +                                        size_t count, loff_t *ppos)
14868 +{
14869 +       struct ath_softc *sc = file->private_data;
14870 +       unsigned long val;
14871 +       char buf[32];
14872 +       ssize_t len;
14873 +
14874 +       len = min(count, sizeof(buf) - 1);
14875 +       if (copy_from_user(buf, user_buf, len))
14876 +               return -EFAULT;
14877 +
14878 +       buf[len] = '\0';
14879 +       if (kstrtoul(buf, 0, &val))
14880 +               return -EINVAL;
14881 +
14882 +       if (val < 0 || val > 255)
14883 +               return -EINVAL;
14884 +
14885 +       sc->spec_config.count = val;
14886 +       return count;
14887 +}
14888 +
14889 +static const struct file_operations fops_spectral_count = {
14890 +       .read = read_file_spectral_count,
14891 +       .write = write_file_spectral_count,
14892 +       .open = simple_open,
14893 +       .owner = THIS_MODULE,
14894 +       .llseek = default_llseek,
14895 +};
14896 +
14897 +/*******************/
14898 +/* spectral_period */
14899 +/*******************/
14900 +
14901 +static ssize_t read_file_spectral_period(struct file *file,
14902 +                                        char __user *user_buf,
14903 +                                        size_t count, loff_t *ppos)
14904 +{
14905 +       struct ath_softc *sc = file->private_data;
14906 +       char buf[32];
14907 +       unsigned int len;
14908 +
14909 +       len = sprintf(buf, "%d\n", sc->spec_config.period);
14910 +       return simple_read_from_buffer(user_buf, count, ppos, buf, len);
14911 +}
14912 +
14913 +static ssize_t write_file_spectral_period(struct file *file,
14914 +                                         const char __user *user_buf,
14915 +                                         size_t count, loff_t *ppos)
14916 +{
14917 +       struct ath_softc *sc = file->private_data;
14918 +       unsigned long val;
14919 +       char buf[32];
14920 +       ssize_t len;
14921 +
14922 +       len = min(count, sizeof(buf) - 1);
14923 +       if (copy_from_user(buf, user_buf, len))
14924 +               return -EFAULT;
14925 +
14926 +       buf[len] = '\0';
14927 +       if (kstrtoul(buf, 0, &val))
14928 +               return -EINVAL;
14929 +
14930 +       if (val < 0 || val > 255)
14931 +               return -EINVAL;
14932 +
14933 +       sc->spec_config.period = val;
14934 +       return count;
14935 +}
14936 +
14937 +static const struct file_operations fops_spectral_period = {
14938 +       .read = read_file_spectral_period,
14939 +       .write = write_file_spectral_period,
14940 +       .open = simple_open,
14941 +       .owner = THIS_MODULE,
14942 +       .llseek = default_llseek,
14943 +};
14944 +
14945 +/***********************/
14946 +/* spectral_fft_period */
14947 +/***********************/
14948 +
14949 +static ssize_t read_file_spectral_fft_period(struct file *file,
14950 +                                            char __user *user_buf,
14951 +                                            size_t count, loff_t *ppos)
14952 +{
14953 +       struct ath_softc *sc = file->private_data;
14954 +       char buf[32];
14955 +       unsigned int len;
14956 +
14957 +       len = sprintf(buf, "%d\n", sc->spec_config.fft_period);
14958 +       return simple_read_from_buffer(user_buf, count, ppos, buf, len);
14959 +}
14960 +
14961 +static ssize_t write_file_spectral_fft_period(struct file *file,
14962 +                                             const char __user *user_buf,
14963 +                                             size_t count, loff_t *ppos)
14964 +{
14965 +       struct ath_softc *sc = file->private_data;
14966 +       unsigned long val;
14967 +       char buf[32];
14968 +       ssize_t len;
14969 +
14970 +       len = min(count, sizeof(buf) - 1);
14971 +       if (copy_from_user(buf, user_buf, len))
14972 +               return -EFAULT;
14973 +
14974 +       buf[len] = '\0';
14975 +       if (kstrtoul(buf, 0, &val))
14976 +               return -EINVAL;
14977 +
14978 +       if (val < 0 || val > 15)
14979 +               return -EINVAL;
14980 +
14981 +       sc->spec_config.fft_period = val;
14982 +       return count;
14983 +}
14984 +
14985 +static const struct file_operations fops_spectral_fft_period = {
14986 +       .read = read_file_spectral_fft_period,
14987 +       .write = write_file_spectral_fft_period,
14988 +       .open = simple_open,
14989 +       .owner = THIS_MODULE,
14990 +       .llseek = default_llseek,
14991 +};
14992 +
14993 +/*******************/
14994 +/* Relay interface */
14995 +/*******************/
14996 +
14997 +static struct dentry *create_buf_file_handler(const char *filename,
14998 +                                             struct dentry *parent,
14999 +                                             umode_t mode,
15000 +                                             struct rchan_buf *buf,
15001 +                                             int *is_global)
15002 +{
15003 +       struct dentry *buf_file;
15004 +
15005 +       buf_file = debugfs_create_file(filename, mode, parent, buf,
15006 +                                      &relay_file_operations);
15007 +       *is_global = 1;
15008 +       return buf_file;
15009 +}
15010 +
15011 +static int remove_buf_file_handler(struct dentry *dentry)
15012 +{
15013 +       debugfs_remove(dentry);
15014 +
15015 +       return 0;
15016 +}
15017 +
15018 +struct rchan_callbacks rfs_spec_scan_cb = {
15019 +       .create_buf_file = create_buf_file_handler,
15020 +       .remove_buf_file = remove_buf_file_handler,
15021 +};
15022 +
15023 +/*********************/
15024 +/* Debug Init/Deinit */
15025 +/*********************/
15026 +
15027 +void ath9k_spectral_deinit_debug(struct ath_softc *sc)
15028 +{
15029 +       if (config_enabled(CPTCFG_ATH9K_DEBUGFS) && sc->rfs_chan_spec_scan) {
15030 +               relay_close(sc->rfs_chan_spec_scan);
15031 +               sc->rfs_chan_spec_scan = NULL;
15032 +       }
15033 +}
15034 +
15035 +void ath9k_spectral_init_debug(struct ath_softc *sc)
15036 +{
15037 +       sc->rfs_chan_spec_scan = relay_open("spectral_scan",
15038 +                                           sc->debug.debugfs_phy,
15039 +                                           1024, 256, &rfs_spec_scan_cb,
15040 +                                           NULL);
15041 +       debugfs_create_file("spectral_scan_ctl",
15042 +                           S_IRUSR | S_IWUSR,
15043 +                           sc->debug.debugfs_phy, sc,
15044 +                           &fops_spec_scan_ctl);
15045 +       debugfs_create_file("spectral_short_repeat",
15046 +                           S_IRUSR | S_IWUSR,
15047 +                           sc->debug.debugfs_phy, sc,
15048 +                           &fops_spectral_short_repeat);
15049 +       debugfs_create_file("spectral_count",
15050 +                           S_IRUSR | S_IWUSR,
15051 +                           sc->debug.debugfs_phy, sc,
15052 +                           &fops_spectral_count);
15053 +       debugfs_create_file("spectral_period",
15054 +                           S_IRUSR | S_IWUSR,
15055 +                           sc->debug.debugfs_phy, sc,
15056 +                           &fops_spectral_period);
15057 +       debugfs_create_file("spectral_fft_period",
15058 +                           S_IRUSR | S_IWUSR,
15059 +                           sc->debug.debugfs_phy, sc,
15060 +                           &fops_spectral_fft_period);
15061 +}
15062 --- /dev/null
15063 +++ b/drivers/net/wireless/ath/ath9k/spectral.h
15064 @@ -0,0 +1,212 @@
15065 +/*
15066 + * Copyright (c) 2013 Qualcomm Atheros, Inc.
15067 + *
15068 + * Permission to use, copy, modify, and/or distribute this software for any
15069 + * purpose with or without fee is hereby granted, provided that the above
15070 + * copyright notice and this permission notice appear in all copies.
15071 + *
15072 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
15073 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
15074 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15075 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15076 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15077 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15078 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15079 + */
15080 +
15081 +#ifndef SPECTRAL_H
15082 +#define SPECTRAL_H
15083 +
15084 +/* enum spectral_mode:
15085 + *
15086 + * @SPECTRAL_DISABLED: spectral mode is disabled
15087 + * @SPECTRAL_BACKGROUND: hardware sends samples when it is not busy with
15088 + *     something else.
15089 + * @SPECTRAL_MANUAL: spectral scan is enabled, triggering for samples
15090 + *     is performed manually.
15091 + * @SPECTRAL_CHANSCAN: Like manual, but also triggered when changing channels
15092 + *     during a channel scan.
15093 + */
15094 +enum spectral_mode {
15095 +       SPECTRAL_DISABLED = 0,
15096 +       SPECTRAL_BACKGROUND,
15097 +       SPECTRAL_MANUAL,
15098 +       SPECTRAL_CHANSCAN,
15099 +};
15100 +
15101 +#define SPECTRAL_SCAN_BITMASK          0x10
15102 +/* Radar info packet format, used for DFS and spectral formats. */
15103 +struct ath_radar_info {
15104 +       u8 pulse_length_pri;
15105 +       u8 pulse_length_ext;
15106 +       u8 pulse_bw_info;
15107 +} __packed;
15108 +
15109 +/* The HT20 spectral data has 4 bytes of additional information at it's end.
15110 + *
15111 + * [7:0]: all bins {max_magnitude[1:0], bitmap_weight[5:0]}
15112 + * [7:0]: all bins  max_magnitude[9:2]
15113 + * [7:0]: all bins {max_index[5:0], max_magnitude[11:10]}
15114 + * [3:0]: max_exp (shift amount to size max bin to 8-bit unsigned)
15115 + */
15116 +struct ath_ht20_mag_info {
15117 +       u8 all_bins[3];
15118 +       u8 max_exp;
15119 +} __packed;
15120 +
15121 +#define SPECTRAL_HT20_NUM_BINS         56
15122 +
15123 +/* WARNING: don't actually use this struct! MAC may vary the amount of
15124 + * data by -1/+2. This struct is for reference only.
15125 + */
15126 +struct ath_ht20_fft_packet {
15127 +       u8 data[SPECTRAL_HT20_NUM_BINS];
15128 +       struct ath_ht20_mag_info mag_info;
15129 +       struct ath_radar_info radar_info;
15130 +} __packed;
15131 +
15132 +#define SPECTRAL_HT20_TOTAL_DATA_LEN   (sizeof(struct ath_ht20_fft_packet))
15133 +
15134 +/* Dynamic 20/40 mode:
15135 + *
15136 + * [7:0]: lower bins {max_magnitude[1:0], bitmap_weight[5:0]}
15137 + * [7:0]: lower bins  max_magnitude[9:2]
15138 + * [7:0]: lower bins {max_index[5:0], max_magnitude[11:10]}
15139 + * [7:0]: upper bins {max_magnitude[1:0], bitmap_weight[5:0]}
15140 + * [7:0]: upper bins  max_magnitude[9:2]
15141 + * [7:0]: upper bins {max_index[5:0], max_magnitude[11:10]}
15142 + * [3:0]: max_exp (shift amount to size max bin to 8-bit unsigned)
15143 + */
15144 +struct ath_ht20_40_mag_info {
15145 +       u8 lower_bins[3];
15146 +       u8 upper_bins[3];
15147 +       u8 max_exp;
15148 +} __packed;
15149 +
15150 +#define SPECTRAL_HT20_40_NUM_BINS              128
15151 +
15152 +/* WARNING: don't actually use this struct! MAC may vary the amount of
15153 + * data. This struct is for reference only.
15154 + */
15155 +struct ath_ht20_40_fft_packet {
15156 +       u8 data[SPECTRAL_HT20_40_NUM_BINS];
15157 +       struct ath_ht20_40_mag_info mag_info;
15158 +       struct ath_radar_info radar_info;
15159 +} __packed;
15160 +
15161 +
15162 +#define SPECTRAL_HT20_40_TOTAL_DATA_LEN        (sizeof(struct ath_ht20_40_fft_packet))
15163 +
15164 +/* grabs the max magnitude from the all/upper/lower bins */
15165 +static inline u16 spectral_max_magnitude(u8 *bins)
15166 +{
15167 +       return (bins[0] & 0xc0) >> 6 |
15168 +              (bins[1] & 0xff) << 2 |
15169 +              (bins[2] & 0x03) << 10;
15170 +}
15171 +
15172 +/* return the max magnitude from the all/upper/lower bins */
15173 +static inline u8 spectral_max_index(u8 *bins)
15174 +{
15175 +       s8 m = (bins[2] & 0xfc) >> 2;
15176 +
15177 +       /* TODO: this still doesn't always report the right values ... */
15178 +       if (m > 32)
15179 +               m |= 0xe0;
15180 +       else
15181 +               m &= ~0xe0;
15182 +
15183 +       return m + 29;
15184 +}
15185 +
15186 +/* return the bitmap weight from the all/upper/lower bins */
15187 +static inline u8 spectral_bitmap_weight(u8 *bins)
15188 +{
15189 +       return bins[0] & 0x3f;
15190 +}
15191 +
15192 +/* FFT sample format given to userspace via debugfs.
15193 + *
15194 + * Please keep the type/length at the front position and change
15195 + * other fields after adding another sample type
15196 + *
15197 + * TODO: this might need rework when switching to nl80211-based
15198 + * interface.
15199 + */
15200 +enum ath_fft_sample_type {
15201 +       ATH_FFT_SAMPLE_HT20 = 1,
15202 +       ATH_FFT_SAMPLE_HT20_40,
15203 +};
15204 +
15205 +struct fft_sample_tlv {
15206 +       u8 type;        /* see ath_fft_sample */
15207 +       __be16 length;
15208 +       /* type dependent data follows */
15209 +} __packed;
15210 +
15211 +struct fft_sample_ht20 {
15212 +       struct fft_sample_tlv tlv;
15213 +
15214 +       u8 max_exp;
15215 +
15216 +       __be16 freq;
15217 +       s8 rssi;
15218 +       s8 noise;
15219 +
15220 +       __be16 max_magnitude;
15221 +       u8 max_index;
15222 +       u8 bitmap_weight;
15223 +
15224 +       __be64 tsf;
15225 +
15226 +       u8 data[SPECTRAL_HT20_NUM_BINS];
15227 +} __packed;
15228 +
15229 +struct fft_sample_ht20_40 {
15230 +       struct fft_sample_tlv tlv;
15231 +
15232 +       u8 channel_type;
15233 +       __be16 freq;
15234 +
15235 +       s8 lower_rssi;
15236 +       s8 upper_rssi;
15237 +
15238 +       __be64 tsf;
15239 +
15240 +       s8 lower_noise;
15241 +       s8 upper_noise;
15242 +
15243 +       __be16 lower_max_magnitude;
15244 +       __be16 upper_max_magnitude;
15245 +
15246 +       u8 lower_max_index;
15247 +       u8 upper_max_index;
15248 +
15249 +       u8 lower_bitmap_weight;
15250 +       u8 upper_bitmap_weight;
15251 +
15252 +       u8 max_exp;
15253 +
15254 +       u8 data[SPECTRAL_HT20_40_NUM_BINS];
15255 +} __packed;
15256 +
15257 +void ath9k_spectral_init_debug(struct ath_softc *sc);
15258 +void ath9k_spectral_deinit_debug(struct ath_softc *sc);
15259 +
15260 +void ath9k_spectral_scan_trigger(struct ieee80211_hw *hw);
15261 +int ath9k_spectral_scan_config(struct ieee80211_hw *hw,
15262 +                              enum spectral_mode spectral_mode);
15263 +
15264 +#ifdef CPTCFG_ATH9K_DEBUGFS
15265 +int ath_process_fft(struct ath_softc *sc, struct ieee80211_hdr *hdr,
15266 +                   struct ath_rx_status *rs, u64 tsf);
15267 +#else
15268 +static inline int ath_process_fft(struct ath_softc *sc,
15269 +                                 struct ieee80211_hdr *hdr,
15270 +                                 struct ath_rx_status *rs, u64 tsf)
15271 +{
15272 +       return 0;
15273 +}
15274 +#endif /* CPTCFG_ATH9K_DEBUGFS */
15275 +
15276 +#endif /* SPECTRAL_H */
15277 --- a/include/net/mac80211.h
15278 +++ b/include/net/mac80211.h
15279 @@ -1566,6 +1566,9 @@ enum ieee80211_hw_flags {
15280   * @extra_tx_headroom: headroom to reserve in each transmit skb
15281   *     for use by the driver (e.g. for transmit headers.)
15282   *
15283 + * @extra_beacon_tailroom: tailroom to reserve in each beacon tx skb.
15284 + *     Can be used by drivers to add extra IEs.
15285 + *
15286   * @channel_change_time: time (in microseconds) it takes to change channels.
15287   *
15288   * @max_signal: Maximum value for signal (rssi) in RX information, used
15289 @@ -1644,6 +1647,7 @@ struct ieee80211_hw {
15290         void *priv;
15291         u32 flags;
15292         unsigned int extra_tx_headroom;
15293 +       unsigned int extra_beacon_tailroom;
15294         int channel_change_time;
15295         int vif_data_size;
15296         int sta_data_size;
15297 @@ -4595,4 +4599,49 @@ bool ieee80211_tx_prepare_skb(struct iee
15298                               struct ieee80211_vif *vif, struct sk_buff *skb,
15299                               int band, struct ieee80211_sta **sta);
15300
15301 +/**
15302 + * struct ieee80211_noa_data - holds temporary data for tracking P2P NoA state
15303 + *
15304 + * @next_tsf: TSF timestamp of the next absent state change
15305 + * @has_next_tsf: next absent state change event pending
15306 + *
15307 + * @absent: descriptor bitmask, set if GO is currently absent
15308 + *
15309 + * private:
15310 + *
15311 + * @count: count fields from the NoA descriptors
15312 + * @desc: adjusted data from the NoA
15313 + */
15314 +struct ieee80211_noa_data {
15315 +       u32 next_tsf;
15316 +       bool has_next_tsf;
15317 +
15318 +       u8 absent;
15319 +
15320 +       u8 count[IEEE80211_P2P_NOA_DESC_MAX];
15321 +       struct {
15322 +               u32 start;
15323 +               u32 duration;
15324 +               u32 interval;
15325 +       } desc[IEEE80211_P2P_NOA_DESC_MAX];
15326 +};
15327 +
15328 +/**
15329 + * ieee80211_parse_p2p_noa - initialize NoA tracking data from P2P IE
15330 + *
15331 + * @attr: P2P NoA IE
15332 + * @data: NoA tracking data
15333 + * @tsf: current TSF timestamp
15334 + */
15335 +int ieee80211_parse_p2p_noa(const struct ieee80211_p2p_noa_attr *attr,
15336 +                           struct ieee80211_noa_data *data, u32 tsf);
15337 +
15338 +/**
15339 + * ieee80211_update_p2p_noa - get next pending P2P GO absent state change
15340 + *
15341 + * @data: NoA tracking data
15342 + * @tsf: current TSF timestamp
15343 + */
15344 +void ieee80211_update_p2p_noa(struct ieee80211_noa_data *data, u32 tsf);
15345 +
15346  #endif /* MAC80211_H */
15347 --- a/drivers/net/wireless/ath/ath9k/hw-ops.h
15348 +++ b/drivers/net/wireless/ath/ath9k/hw-ops.h
15349 @@ -49,9 +49,10 @@ static inline bool ath9k_hw_calibrate(st
15350         return ath9k_hw_ops(ah)->calibrate(ah, chan, rxchainmask, longcal);
15351  }
15352
15353 -static inline bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
15354 +static inline bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked,
15355 +                                  u32 *sync_cause_p)
15356  {
15357 -       return ath9k_hw_ops(ah)->get_isr(ah, masked);
15358 +       return ath9k_hw_ops(ah)->get_isr(ah, masked, sync_cause_p);
15359  }
15360
15361  static inline void ath9k_hw_set_txdesc(struct ath_hw *ah, void *ds,