package/kernel/lantiq/ltq-atm/src/ltq_atm.c

   1 /******************************************************************************
   2 **
   3 ** FILE NAME    : ifxmips_atm_core.c
   4 ** PROJECT      : UEIP
   5 ** MODULES      : ATM
   6 **
   7 ** DATE         : 7 Jul 2009
   8 ** AUTHOR       : Xu Liang
   9 ** DESCRIPTION  : ATM driver common source file (core functions)
  10 ** COPYRIGHT    :       Copyright (c) 2006
  11 **                      Infineon Technologies AG
  12 **                      Am Campeon 1-12, 85579 Neubiberg, Germany
  13 **
  14 **    This program is free software; you can redistribute it and/or modify
  15 **    it under the terms of the GNU General Public License as published by
  16 **    the Free Software Foundation; either version 2 of the License, or
  17 **    (at your option) any later version.
  18 **
  19 ** HISTORY
  20 ** $Date        $Author         $Comment
  21 ** 07 JUL 2009  Xu Liang        Init Version
  22 *******************************************************************************/
  23
  24 #define IFX_ATM_VER_MAJOR               1
  25 #define IFX_ATM_VER_MID                 0
  26 #define IFX_ATM_VER_MINOR               26
  27
  28 #include <linux/kernel.h>
  29 #include <linux/module.h>
  30 #include <linux/version.h>
  31 #include <linux/types.h>
  32 #include <linux/errno.h>
  33 #include <linux/proc_fs.h>
  34 #include <linux/init.h>
  35 #include <linux/ioctl.h>
  36 #include <linux/atmdev.h>
  37 #include <linux/platform_device.h>
  38 #include <linux/of_device.h>
  39 #include <linux/atm.h>
  40 #include <linux/clk.h>
  41 #include <linux/interrupt.h>
  42 #ifdef CONFIG_XFRM
  43   #include <net/xfrm.h>
  44 #endif
  45
  46 #include <lantiq_soc.h>
  47
  48 #include "ifxmips_atm_core.h"
  49
  50 #define MODULE_PARM_ARRAY(a, b)   module_param_array(a, int, NULL, 0)
  51 #define MODULE_PARM(a, b)         module_param(a, int, 0)
  52
  53 /*!
  54   \brief QSB cell delay variation due to concurrency
  55  */
  56 static int qsb_tau   = 1;                       /*  QSB cell delay variation due to concurrency     */
  57 /*!
  58   \brief QSB scheduler burst length
  59  */
  60 static int qsb_srvm  = 0x0F;                    /*  QSB scheduler burst length                      */
  61 /*!
  62   \brief QSB time step, all legal values are 1, 2, 4
  63  */
  64 static int qsb_tstep = 4 ;                      /*  QSB time step, all legal values are 1, 2, 4     */
  65
  66 /*!
  67   \brief Write descriptor delay
  68  */
  69 static int write_descriptor_delay  = 0x20;      /*  Write descriptor delay                          */
  70
  71 /*!
  72   \brief AAL5 padding byte ('~')
  73  */
  74 static int aal5_fill_pattern       = 0x007E;    /*  AAL5 padding byte ('~')                         */
  75 /*!
  76   \brief Max frame size for RX
  77  */
  78 static int aal5r_max_packet_size   = 0x0700;    /*  Max frame size for RX                           */
  79 /*!
  80   \brief Min frame size for RX
  81  */
  82 static int aal5r_min_packet_size   = 0x0000;    /*  Min frame size for RX                           */
  83 /*!
  84   \brief Max frame size for TX
  85  */
  86 static int aal5s_max_packet_size   = 0x0700;    /*  Max frame size for TX                           */
  87 /*!
  88   \brief Min frame size for TX
  89  */
  90 static int aal5s_min_packet_size   = 0x0000;    /*  Min frame size for TX                           */
  91 /*!
  92   \brief Drop error packet in RX path
  93  */
  94 static int aal5r_drop_error_packet = 1;         /*  Drop error packet in RX path                    */
  95
  96 /*!
  97   \brief Number of descriptors per DMA RX channel
  98  */
  99 static int dma_rx_descriptor_length = 128;      /*  Number of descriptors per DMA RX channel        */
 100 /*!
 101   \brief Number of descriptors per DMA TX channel
 102  */
 103 static int dma_tx_descriptor_length = 64;       /*  Number of descriptors per DMA TX channel        */
 104 /*!
 105   \brief PPE core clock cycles between descriptor write and effectiveness in external RAM
 106  */
 107 static int dma_rx_clp1_descriptor_threshold = 38;
 108 /*@}*/
 109
 110 MODULE_PARM(qsb_tau, "i");
 111 MODULE_PARM_DESC(qsb_tau, "Cell delay variation. Value must be > 0");
 112 MODULE_PARM(qsb_srvm, "i");
 113 MODULE_PARM_DESC(qsb_srvm, "Maximum burst size");
 114 MODULE_PARM(qsb_tstep, "i");
 115 MODULE_PARM_DESC(qsb_tstep, "n*32 cycles per sbs cycles n=1,2,4");
 116
 117 MODULE_PARM(write_descriptor_delay, "i");
 118 MODULE_PARM_DESC(write_descriptor_delay, "PPE core clock cycles between descriptor write and effectiveness in external RAM");
 119
 120 MODULE_PARM(aal5_fill_pattern, "i");
 121 MODULE_PARM_DESC(aal5_fill_pattern, "Filling pattern (PAD) for AAL5 frames");
 122 MODULE_PARM(aal5r_max_packet_size, "i");
 123 MODULE_PARM_DESC(aal5r_max_packet_size, "Max packet size in byte for downstream AAL5 frames");
 124 MODULE_PARM(aal5r_min_packet_size, "i");
 125 MODULE_PARM_DESC(aal5r_min_packet_size, "Min packet size in byte for downstream AAL5 frames");
 126 MODULE_PARM(aal5s_max_packet_size, "i");
 127 MODULE_PARM_DESC(aal5s_max_packet_size, "Max packet size in byte for upstream AAL5 frames");
 128 MODULE_PARM(aal5s_min_packet_size, "i");
 129 MODULE_PARM_DESC(aal5s_min_packet_size, "Min packet size in byte for upstream AAL5 frames");
 130 MODULE_PARM(aal5r_drop_error_packet, "i");
 131 MODULE_PARM_DESC(aal5r_drop_error_packet, "Non-zero value to drop error packet for downstream");
 132
 133 MODULE_PARM(dma_rx_descriptor_length, "i");
 134 MODULE_PARM_DESC(dma_rx_descriptor_length, "Number of descriptor assigned to DMA RX channel (>16)");
 135 MODULE_PARM(dma_tx_descriptor_length, "i");
 136 MODULE_PARM_DESC(dma_tx_descriptor_length, "Number of descriptor assigned to DMA TX channel (>16)");
 137 MODULE_PARM(dma_rx_clp1_descriptor_threshold, "i");
 138 MODULE_PARM_DESC(dma_rx_clp1_descriptor_threshold, "Descriptor threshold for cells with cell loss priority 1");
 139
 140
 141
 142 /*
 143  * ####################################
 144  *              Definition
 145  * ####################################
 146  */
 147
 148 #ifdef CONFIG_AMAZON_SE
 149   #define ENABLE_LESS_CACHE_INV                 1
 150   #define LESS_CACHE_INV_LEN                    96
 151 #endif
 152
 153 #define DUMP_SKB_LEN                            ~0
 154
 155
 156
 157 /*
 158  * ####################################
 159  *             Declaration
 160  * ####################################
 161  */
 162
 163 /*
 164  *  Network Operations
 165  */
 166 static int ppe_ioctl(struct atm_dev *, unsigned int, void *);
 167 static int ppe_open(struct atm_vcc *);
 168 static void ppe_close(struct atm_vcc *);
 169 static int ppe_send(struct atm_vcc *, struct sk_buff *);
 170 static int ppe_send_oam(struct atm_vcc *, void *, int);
 171 static int ppe_change_qos(struct atm_vcc *, struct atm_qos *, int);
 172
 173 /*
 174  *  ADSL LED
 175  */
 176 static inline void adsl_led_flash(void);
 177
 178 /*
 179  *  64-bit operation used by MIB calculation
 180  */
 181 static inline void u64_add_u32(ppe_u64_t, unsigned int, ppe_u64_t *);
 182
 183 /*
 184  *  buffer manage functions
 185  */
 186 static inline struct sk_buff* alloc_skb_rx(void);
 187 static inline struct sk_buff* alloc_skb_tx(unsigned int);
 188 struct sk_buff* atm_alloc_tx(struct atm_vcc *, unsigned int);
 189 static inline void atm_free_tx_skb_vcc(struct sk_buff *, struct atm_vcc *);
 190 static inline struct sk_buff *get_skb_rx_pointer(unsigned int);
 191 static inline int get_tx_desc(unsigned int);
 192 static struct sk_buff* skb_duplicate(struct sk_buff *);
 193 static struct sk_buff* skb_break_away_from_protocol(struct sk_buff *);
 194
 195 /*
 196  *  mailbox handler and signal function
 197  */
 198 static inline void mailbox_oam_rx_handler(void);
 199 static inline void mailbox_aal_rx_handler(void);
 200 static irqreturn_t mailbox_irq_handler(int, void *);
 201 static inline void mailbox_signal(unsigned int, int);
 202 static void do_ppe_tasklet(unsigned long);
 203 DECLARE_TASKLET(g_dma_tasklet, do_ppe_tasklet, 0);
 204
 205 /*
 206  *  QSB & HTU setting functions
 207  */
 208 static void set_qsb(struct atm_vcc *, struct atm_qos *, unsigned int);
 209 static void qsb_global_set(void);
 210 static inline void set_htu_entry(unsigned int, unsigned int, unsigned int, int, int);
 211 static inline void clear_htu_entry(unsigned int);
 212 static void validate_oam_htu_entry(void);
 213 static void invalidate_oam_htu_entry(void);
 214
 215 /*
 216  *  look up for connection ID
 217  */
 218 static inline int find_vpi(unsigned int);
 219 static inline int find_vpivci(unsigned int, unsigned int);
 220 static inline int find_vcc(struct atm_vcc *);
 221
 222 static inline int ifx_atm_version(const struct ltq_atm_ops *ops, char *);
 223
 224 /*
 225  *  Init & clean-up functions
 226  */
 227 static inline void check_parameters(void);
 228 static inline int init_priv_data(void);
 229 static inline void clear_priv_data(void);
 230 static inline void init_rx_tables(void);
 231 static inline void init_tx_tables(void);
 232
 233 /*
 234  *  Exteranl Function
 235  */
 236 #if defined(CONFIG_IFX_OAM) || defined(CONFIG_IFX_OAM_MODULE)
 237 extern void ifx_push_oam(unsigned char *);
 238 #else
 239 static inline void ifx_push_oam(unsigned char *dummy) {}
 240 #endif
 241
 242 #if defined(CONFIG_IFXMIPS_DSL_CPE_MEI) || defined(CONFIG_IFXMIPS_DSL_CPE_MEI_MODULE)
 243 extern int ifx_mei_atm_showtime_check(int *is_showtime, struct port_cell_info *port_cell, void **xdata_addr);
 244 extern int (*ifx_mei_atm_showtime_enter)(struct port_cell_info *, void *);
 245
 246 extern int (*ifx_mei_atm_showtime_exit)(void);
 247 extern int ifx_mei_atm_led_blink(void);
 248 #else
 249 static inline int ifx_mei_atm_led_blink(void) { return 0; }
 250 static inline int ifx_mei_atm_showtime_check(int *is_showtime, struct port_cell_info *port_cell, void **xdata_addr)
 251 {
 252         if ( is_showtime != NULL )
 253                 *is_showtime = 0;
 254         return 0;
 255 }
 256 int (*ifx_mei_atm_showtime_enter)(struct port_cell_info *, void *) = NULL;
 257 EXPORT_SYMBOL(ifx_mei_atm_showtime_enter);
 258
 259 int (*ifx_mei_atm_showtime_exit)(void) = NULL;
 260 EXPORT_SYMBOL(ifx_mei_atm_showtime_exit);
 261
 262 #endif
 263
 264 static struct sk_buff* (*ifx_atm_alloc_tx)(struct atm_vcc *, unsigned int) = NULL;
 265
 266 static struct atm_priv_data g_atm_priv_data;
 267
 268 static struct atmdev_ops g_ifx_atm_ops = {
 269         .open = ppe_open,
 270         .close = ppe_close,
 271         .ioctl = ppe_ioctl,
 272         .send = ppe_send,
 273         .send_oam = ppe_send_oam,
 274         .change_qos = ppe_change_qos,
 275         .owner = THIS_MODULE,
 276 };
 277
 278 static int g_showtime = 0;
 279 static void *g_xdata_addr = NULL;
 280
 281 static int ppe_ioctl(struct atm_dev *dev, unsigned int cmd, void *arg)
 282 {
 283         int ret = 0;
 284         atm_cell_ifEntry_t mib_cell;
 285         atm_aal5_ifEntry_t mib_aal5;
 286         atm_aal5_vcc_x_t mib_vcc;
 287         unsigned int value;
 288         int conn;
 289
 290         if ( _IOC_TYPE(cmd) != PPE_ATM_IOC_MAGIC
 291                         || _IOC_NR(cmd) >= PPE_ATM_IOC_MAXNR )
 292                 return -ENOTTY;
 293
 294         if ( _IOC_DIR(cmd) & _IOC_READ )
 295                 ret = !access_ok(VERIFY_WRITE, arg, _IOC_SIZE(cmd));
 296         else if ( _IOC_DIR(cmd) & _IOC_WRITE )
 297                 ret = !access_ok(VERIFY_READ, arg, _IOC_SIZE(cmd));
 298         if ( ret )
 299                 return -EFAULT;
 300
 301         switch (cmd) {
 302         case PPE_ATM_MIB_CELL:  /*  cell level  MIB */
 303                 /*  These MIB should be read at ARC side, now put zero only.    */
 304                 mib_cell.ifHCInOctets_h = 0;
 305                 mib_cell.ifHCInOctets_l = 0;
 306                 mib_cell.ifHCOutOctets_h = 0;
 307                 mib_cell.ifHCOutOctets_l = 0;
 308                 mib_cell.ifInErrors = 0;
 309                 mib_cell.ifInUnknownProtos = WAN_MIB_TABLE->wrx_drophtu_cell;
 310                 mib_cell.ifOutErrors = 0;
 311
 312                 ret = sizeof(mib_cell) - copy_to_user(arg, &mib_cell, sizeof(mib_cell));
 313                 break;
 314
 315         case PPE_ATM_MIB_AAL5:  /*  AAL5 MIB    */
 316                 value = WAN_MIB_TABLE->wrx_total_byte;
 317                 u64_add_u32(g_atm_priv_data.wrx_total_byte, value - g_atm_priv_data.prev_wrx_total_byte, &g_atm_priv_data.wrx_total_byte);
 318                 g_atm_priv_data.prev_wrx_total_byte = value;
 319                 mib_aal5.ifHCInOctets_h = g_atm_priv_data.wrx_total_byte.h;
 320                 mib_aal5.ifHCInOctets_l = g_atm_priv_data.wrx_total_byte.l;
 321
 322                 value = WAN_MIB_TABLE->wtx_total_byte;
 323                 u64_add_u32(g_atm_priv_data.wtx_total_byte, value - g_atm_priv_data.prev_wtx_total_byte, &g_atm_priv_data.wtx_total_byte);
 324                 g_atm_priv_data.prev_wtx_total_byte = value;
 325                 mib_aal5.ifHCOutOctets_h = g_atm_priv_data.wtx_total_byte.h;
 326                 mib_aal5.ifHCOutOctets_l = g_atm_priv_data.wtx_total_byte.l;
 327
 328                 mib_aal5.ifInUcastPkts  = g_atm_priv_data.wrx_pdu;
 329                 mib_aal5.ifOutUcastPkts = WAN_MIB_TABLE->wtx_total_pdu;
 330                 mib_aal5.ifInErrors     = WAN_MIB_TABLE->wrx_err_pdu;
 331                 mib_aal5.ifInDiscards   = WAN_MIB_TABLE->wrx_dropdes_pdu + g_atm_priv_data.wrx_drop_pdu;
 332                 mib_aal5.ifOutErros     = g_atm_priv_data.wtx_err_pdu;
 333                 mib_aal5.ifOutDiscards  = g_atm_priv_data.wtx_drop_pdu;
 334
 335                 ret = sizeof(mib_aal5) - copy_to_user(arg, &mib_aal5, sizeof(mib_aal5));
 336                 break;
 337
 338         case PPE_ATM_MIB_VCC:   /*  VCC related MIB */
 339                 copy_from_user(&mib_vcc, arg, sizeof(mib_vcc));
 340                 conn = find_vpivci(mib_vcc.vpi, mib_vcc.vci);
 341                 if (conn >= 0) {
 342                         mib_vcc.mib_vcc.aal5VccCrcErrors     = g_atm_priv_data.conn[conn].aal5_vcc_crc_err;
 343                         mib_vcc.mib_vcc.aal5VccOverSizedSDUs = g_atm_priv_data.conn[conn].aal5_vcc_oversize_sdu;
 344                         mib_vcc.mib_vcc.aal5VccSarTimeOuts   = 0;   /*  no timer support    */
 345                         ret = sizeof(mib_vcc) - copy_to_user(arg, &mib_vcc, sizeof(mib_vcc));
 346                 } else
 347                         ret = -EINVAL;
 348                 break;
 349
 350         default:
 351                 ret = -ENOIOCTLCMD;
 352         }
 353
 354         return ret;
 355 }
 356
 357 static int ppe_open(struct atm_vcc *vcc)
 358 {
 359         int ret;
 360         short vpi = vcc->vpi;
 361         int   vci = vcc->vci;
 362         struct port *port = &g_atm_priv_data.port[(int)vcc->dev->dev_data];
 363         int conn;
 364         int f_enable_irq = 0;
 365
 366         if ( vcc->qos.aal != ATM_AAL5 && vcc->qos.aal != ATM_AAL0 )
 367                 return -EPROTONOSUPPORT;
 368
 369 #if !defined(DISABLE_QOS_WORKAROUND) || !DISABLE_QOS_WORKAROUND
 370         /*  check bandwidth */
 371         if ( (vcc->qos.txtp.traffic_class == ATM_CBR && vcc->qos.txtp.max_pcr > (port->tx_max_cell_rate - port->tx_current_cell_rate))
 372                 || (vcc->qos.txtp.traffic_class == ATM_VBR_RT && vcc->qos.txtp.max_pcr > (port->tx_max_cell_rate - port->tx_current_cell_rate))
 373 #if 0
 374                 || (vcc->qos.txtp.traffic_class == ATM_VBR_NRT && vcc->qos.txtp.scr > (port->tx_max_cell_rate - port->tx_current_cell_rate))
 375 #endif
 376                 || (vcc->qos.txtp.traffic_class == ATM_UBR_PLUS && vcc->qos.txtp.min_pcr > (port->tx_max_cell_rate - port->tx_current_cell_rate)) )
 377         {
 378                 ret = -EINVAL;
 379                 goto PPE_OPEN_EXIT;
 380         }
 381 #endif
 382
 383         /*  check existing vpi,vci  */
 384         conn = find_vpivci(vpi, vci);
 385         if ( conn >= 0 ) {
 386                 ret = -EADDRINUSE;
 387                 goto PPE_OPEN_EXIT;
 388         }
 389
 390         /*  check whether it need to enable irq */
 391         if ( g_atm_priv_data.conn_table == 0 )
 392                 f_enable_irq = 1;
 393
 394         /*  allocate connection */
 395         for ( conn = 0; conn < MAX_PVC_NUMBER; conn++ ) {
 396                 if ( test_and_set_bit(conn, &g_atm_priv_data.conn_table) == 0 ) {
 397                         g_atm_priv_data.conn[conn].vcc = vcc;
 398                         break;
 399                 }
 400         }
 401         if ( conn == MAX_PVC_NUMBER ) {
 402                 ret = -EINVAL;
 403                 goto PPE_OPEN_EXIT;
 404         }
 405
 406         /*  reserve bandwidth   */
 407         switch ( vcc->qos.txtp.traffic_class ) {
 408         case ATM_CBR:
 409         case ATM_VBR_RT:
 410                 port->tx_current_cell_rate += vcc->qos.txtp.max_pcr;
 411                 break;
 412         case ATM_VBR_NRT:
 413 #if 0
 414                 port->tx_current_cell_rate += vcc->qos.txtp.scr;
 415 #endif
 416                 break;
 417         case ATM_UBR_PLUS:
 418                 port->tx_current_cell_rate += vcc->qos.txtp.min_pcr;
 419                 break;
 420         }
 421
 422         /*  set qsb */
 423         set_qsb(vcc, &vcc->qos, conn);
 424
 425         /*  update atm_vcc structure    */
 426         vcc->itf = (int)vcc->dev->dev_data;
 427         vcc->vpi = vpi;
 428         vcc->vci = vci;
 429         set_bit(ATM_VF_READY, &vcc->flags);
 430
 431         /*  enable irq  */
 432         if ( f_enable_irq ) {
 433                 ifx_atm_alloc_tx = atm_alloc_tx;
 434
 435                 *MBOX_IGU1_ISRC = (1 << RX_DMA_CH_AAL) | (1 << RX_DMA_CH_OAM);
 436                 *MBOX_IGU1_IER  = (1 << RX_DMA_CH_AAL) | (1 << RX_DMA_CH_OAM);
 437
 438                 enable_irq(PPE_MAILBOX_IGU1_INT);
 439         }
 440
 441         /*  set port    */
 442         WTX_QUEUE_CONFIG(conn + FIRST_QSB_QID)->sbid = (int)vcc->dev->dev_data;
 443
 444         /*  set htu entry   */
 445         set_htu_entry(vpi, vci, conn, vcc->qos.aal == ATM_AAL5 ? 1 : 0, 0);
 446
 447         ret = 0;
 448
 449 PPE_OPEN_EXIT:
 450         return ret;
 451 }
 452
 453 static void ppe_close(struct atm_vcc *vcc)
 454 {
 455         int conn;
 456         struct port *port;
 457         struct connection *connection;
 458         if ( vcc == NULL )
 459                 return;
 460
 461         /*  get connection id   */
 462         conn = find_vcc(vcc);
 463         if ( conn < 0 ) {
 464                 pr_err("can't find vcc\n");
 465                 goto PPE_CLOSE_EXIT;
 466         }
 467         connection = &g_atm_priv_data.conn[conn];
 468         port = &g_atm_priv_data.port[connection->port];
 469
 470         /*  clear htu   */
 471         clear_htu_entry(conn);
 472
 473         /*  release connection  */
 474         connection->vcc = NULL;
 475         connection->aal5_vcc_crc_err = 0;
 476         connection->aal5_vcc_oversize_sdu = 0;
 477         clear_bit(conn, &g_atm_priv_data.conn_table);
 478
 479         /*  disable irq */
 480         if ( g_atm_priv_data.conn_table == 0 ) {
 481                 disable_irq(PPE_MAILBOX_IGU1_INT);
 482                 ifx_atm_alloc_tx = NULL;
 483         }
 484
 485         /*  release bandwidth   */
 486         switch ( vcc->qos.txtp.traffic_class )
 487         {
 488         case ATM_CBR:
 489         case ATM_VBR_RT:
 490                 port->tx_current_cell_rate -= vcc->qos.txtp.max_pcr;
 491                 break;
 492         case ATM_VBR_NRT:
 493 #if 0
 494                 port->tx_current_cell_rate -= vcc->qos.txtp.scr;
 495 #endif
 496                 break;
 497         case ATM_UBR_PLUS:
 498                 port->tx_current_cell_rate -= vcc->qos.txtp.min_pcr;
 499                 break;
 500         }
 501
 502         /* wait for incoming packets to be processed by upper layers */
 503         tasklet_unlock_wait(&g_dma_tasklet);
 504
 505 PPE_CLOSE_EXIT:
 506         return;
 507 }
 508
 509 static int ppe_send(struct atm_vcc *vcc, struct sk_buff *skb)
 510 {
 511         int ret;
 512         int conn;
 513         int desc_base;
 514         struct tx_descriptor reg_desc = {0};
 515         struct sk_buff *new_skb;
 516
 517         if ( vcc == NULL || skb == NULL )
 518                 return -EINVAL;
 519
 520         skb_get(skb);
 521         atm_free_tx_skb_vcc(skb, vcc);
 522
 523         conn = find_vcc(vcc);
 524         if ( conn < 0 ) {
 525                 ret = -EINVAL;
 526                 goto FIND_VCC_FAIL;
 527         }
 528
 529         if ( !g_showtime ) {
 530                 pr_debug("not in showtime\n");
 531                 ret = -EIO;
 532                 goto PPE_SEND_FAIL;
 533         }
 534
 535         if ( vcc->qos.aal == ATM_AAL5 ) {
 536                 int byteoff;
 537                 int datalen;
 538                 struct tx_inband_header *header;
 539
 540                 byteoff = (unsigned int)skb->data & (DATA_BUFFER_ALIGNMENT - 1);
 541                 if ( skb_headroom(skb) < byteoff + TX_INBAND_HEADER_LENGTH )
 542                         new_skb = skb_duplicate(skb);
 543                 else
 544                         new_skb = skb_break_away_from_protocol(skb);
 545                 if ( new_skb == NULL ) {
 546                         pr_err("either skb_duplicate or skb_break_away_from_protocol fail\n");
 547                         ret = -ENOMEM;
 548                         goto PPE_SEND_FAIL;
 549                 }
 550                 dev_kfree_skb_any(skb);
 551                 skb = new_skb;
 552
 553                 datalen = skb->len;
 554                 byteoff = (unsigned int)skb->data & (DATA_BUFFER_ALIGNMENT - 1);
 555
 556                 skb_push(skb, byteoff + TX_INBAND_HEADER_LENGTH);
 557
 558                 header = (struct tx_inband_header *)skb->data;
 559
 560                 /*  setup inband trailer    */
 561                 header->uu   = 0;
 562                 header->cpi  = 0;
 563                 header->pad  = aal5_fill_pattern;
 564                 header->res1 = 0;
 565
 566                 /*  setup cell header   */
 567                 header->clp  = (vcc->atm_options & ATM_ATMOPT_CLP) ? 1 : 0;
 568                 header->pti  = ATM_PTI_US0;
 569                 header->vci  = vcc->vci;
 570                 header->vpi  = vcc->vpi;
 571                 header->gfc  = 0;
 572
 573                 /*  setup descriptor    */
 574                 reg_desc.dataptr = (unsigned int)skb->data >> 2;
 575                 reg_desc.datalen = datalen;
 576                 reg_desc.byteoff = byteoff;
 577                 reg_desc.iscell  = 0;
 578         } else {
 579                 /*  if data pointer is not aligned, allocate new sk_buff    */
 580                 if ( ((unsigned int)skb->data & (DATA_BUFFER_ALIGNMENT - 1)) != 0 ) {
 581                         pr_err("skb->data not aligned\n");
 582                         new_skb = skb_duplicate(skb);
 583                 } else
 584                         new_skb = skb_break_away_from_protocol(skb);
 585                 if ( new_skb == NULL ) {
 586                         pr_err("either skb_duplicate or skb_break_away_from_protocol fail\n");
 587                         ret = -ENOMEM;
 588                         goto PPE_SEND_FAIL;
 589                 }
 590                 dev_kfree_skb_any(skb);
 591                 skb = new_skb;
 592
 593                 reg_desc.dataptr = (unsigned int)skb->data >> 2;
 594                 reg_desc.datalen = skb->len;
 595                 reg_desc.byteoff = 0;
 596                 reg_desc.iscell  = 1;
 597         }
 598
 599         reg_desc.own = 1;
 600         reg_desc.c = 1;
 601         reg_desc.sop = reg_desc.eop = 1;
 602
 603         desc_base = get_tx_desc(conn);
 604         if ( desc_base < 0 ) {
 605                 pr_debug("ALLOC_TX_CONNECTION_FAIL\n");
 606                 ret = -EIO;
 607                 goto PPE_SEND_FAIL;
 608         }
 609
 610         if ( vcc->stats )
 611                 atomic_inc(&vcc->stats->tx);
 612         if ( vcc->qos.aal == ATM_AAL5 )
 613                 g_atm_priv_data.wtx_pdu++;
 614
 615         /*  update descriptor send pointer  */
 616         if ( g_atm_priv_data.conn[conn].tx_skb[desc_base] != NULL )
 617                 dev_kfree_skb_any(g_atm_priv_data.conn[conn].tx_skb[desc_base]);
 618         g_atm_priv_data.conn[conn].tx_skb[desc_base] = skb;
 619
 620         /*  write discriptor to memory and write back cache */
 621         g_atm_priv_data.conn[conn].tx_desc[desc_base] = reg_desc;
 622         dma_cache_wback((unsigned long)skb->data, skb->len);
 623
 624         mailbox_signal(conn, 1);
 625
 626         adsl_led_flash();
 627
 628         return 0;
 629
 630 FIND_VCC_FAIL:
 631         pr_err("FIND_VCC_FAIL\n");
 632         g_atm_priv_data.wtx_err_pdu++;
 633         dev_kfree_skb_any(skb);
 634         return ret;
 635
 636 PPE_SEND_FAIL:
 637         if ( vcc->qos.aal == ATM_AAL5 )
 638                 g_atm_priv_data.wtx_drop_pdu++;
 639         if ( vcc->stats )
 640                 atomic_inc(&vcc->stats->tx_err);
 641         dev_kfree_skb_any(skb);
 642         return ret;
 643 }
 644
 645 /* operation and maintainance */
 646 static int ppe_send_oam(struct atm_vcc *vcc, void *cell, int flags)
 647 {
 648         int conn;
 649         struct uni_cell_header *uni_cell_header = (struct uni_cell_header *)cell;
 650         int desc_base;
 651         struct sk_buff *skb;
 652         struct tx_descriptor reg_desc = {0};
 653
 654         if ( ((uni_cell_header->pti == ATM_PTI_SEGF5 || uni_cell_header->pti == ATM_PTI_E2EF5)
 655                         && find_vpivci(uni_cell_header->vpi, uni_cell_header->vci) < 0)
 656                         || ((uni_cell_header->vci == 0x03 || uni_cell_header->vci == 0x04)
 657                         && find_vpi(uni_cell_header->vpi) < 0) )
 658         {
 659                 g_atm_priv_data.wtx_err_oam++;
 660                 return -EINVAL;
 661         }
 662
 663         if ( !g_showtime ) {
 664                 pr_err("not in showtime\n");
 665                 g_atm_priv_data.wtx_drop_oam++;
 666                 return -EIO;
 667         }
 668
 669         conn = find_vcc(vcc);
 670         if ( conn < 0 ) {
 671                 pr_err("FIND_VCC_FAIL\n");
 672                 g_atm_priv_data.wtx_drop_oam++;
 673                 return -EINVAL;
 674         }
 675
 676         skb = alloc_skb_tx(CELL_SIZE);
 677         if ( skb == NULL ) {
 678                 pr_err("ALLOC_SKB_TX_FAIL\n");
 679                 g_atm_priv_data.wtx_drop_oam++;
 680                 return -ENOMEM;
 681         }
 682         skb_put(skb, CELL_SIZE);
 683         memcpy(skb->data, cell, CELL_SIZE);
 684
 685         reg_desc.dataptr = (unsigned int)skb->data >> 2;
 686         reg_desc.datalen = CELL_SIZE;
 687         reg_desc.byteoff = 0;
 688         reg_desc.iscell  = 1;
 689
 690         reg_desc.own = 1;
 691         reg_desc.c = 1;
 692         reg_desc.sop = reg_desc.eop = 1;
 693
 694         desc_base = get_tx_desc(conn);
 695         if ( desc_base < 0 ) {
 696                 dev_kfree_skb_any(skb);
 697                 pr_err("ALLOC_TX_CONNECTION_FAIL\n");
 698                 g_atm_priv_data.wtx_drop_oam++;
 699                 return -EIO;
 700         }
 701
 702         if ( vcc->stats )
 703                 atomic_inc(&vcc->stats->tx);
 704
 705         /*  update descriptor send pointer  */
 706         if ( g_atm_priv_data.conn[conn].tx_skb[desc_base] != NULL )
 707                 dev_kfree_skb_any(g_atm_priv_data.conn[conn].tx_skb[desc_base]);
 708         g_atm_priv_data.conn[conn].tx_skb[desc_base] = skb;
 709
 710         /*  write discriptor to memory and write back cache */
 711         g_atm_priv_data.conn[conn].tx_desc[desc_base] = reg_desc;
 712         dma_cache_wback((unsigned long)skb->data, CELL_SIZE);
 713
 714         mailbox_signal(conn, 1);
 715
 716         g_atm_priv_data.wtx_oam++;
 717         adsl_led_flash();
 718
 719         return 0;
 720 }
 721
 722 static int ppe_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, int flags)
 723 {
 724         int conn;
 725
 726         if ( vcc == NULL || qos == NULL )
 727                 return -EINVAL;
 728
 729         conn = find_vcc(vcc);
 730         if ( conn < 0 )
 731                 return -EINVAL;
 732
 733         set_qsb(vcc, qos, conn);
 734
 735         return 0;
 736 }
 737
 738 static inline void adsl_led_flash(void)
 739 {
 740         ifx_mei_atm_led_blink();
 741 }
 742
 743 /*
 744 *  Description:
 745 *    Add a 32-bit value to 64-bit value, and put result in a 64-bit variable.
 746 *  Input:
 747 *    opt1 --- ppe_u64_t, first operand, a 64-bit unsigned integer value
 748 *    opt2 --- unsigned int, second operand, a 32-bit unsigned integer value
 749 *    ret  --- ppe_u64_t, pointer to a variable to hold result
 750 *  Output:
 751 *    none
 752 */
 753 static inline void u64_add_u32(ppe_u64_t opt1, unsigned int opt2, ppe_u64_t *ret)
 754 {
 755         ret->l = opt1.l + opt2;
 756         if ( ret->l < opt1.l || ret->l < opt2 )
 757                 ret->h++;
 758 }
 759
 760 static inline struct sk_buff* alloc_skb_rx(void)
 761 {
 762         struct sk_buff *skb;
 763
 764         skb = dev_alloc_skb(RX_DMA_CH_AAL_BUF_SIZE + DATA_BUFFER_ALIGNMENT);
 765         if ( skb != NULL ) {
 766                 /*  must be burst length alignment  */
 767                 if ( ((unsigned int)skb->data & (DATA_BUFFER_ALIGNMENT - 1)) != 0 )
 768                         skb_reserve(skb, ~((unsigned int)skb->data + (DATA_BUFFER_ALIGNMENT - 1)) & (DATA_BUFFER_ALIGNMENT - 1));
 769                 /*  pub skb in reserved area "skb->data - 4"    */
 770                 *((struct sk_buff **)skb->data - 1) = skb;
 771                 /*  write back and invalidate cache */
 772                 dma_cache_wback_inv((unsigned long)skb->data - sizeof(skb), sizeof(skb));
 773                 /*  invalidate cache    */
 774 #if defined(ENABLE_LESS_CACHE_INV) && ENABLE_LESS_CACHE_INV
 775                 dma_cache_inv((unsigned long)skb->data, LESS_CACHE_INV_LEN);
 776 #else
 777                 dma_cache_inv((unsigned long)skb->data, RX_DMA_CH_AAL_BUF_SIZE);
 778 #endif
 779         }
 780         return skb;
 781 }
 782
 783 static inline struct sk_buff* alloc_skb_tx(unsigned int size)
 784 {
 785         struct sk_buff *skb;
 786
 787         /*  allocate memory including header and padding    */
 788         size += TX_INBAND_HEADER_LENGTH + MAX_TX_PACKET_ALIGN_BYTES + MAX_TX_PACKET_PADDING_BYTES;
 789         size &= ~(DATA_BUFFER_ALIGNMENT - 1);
 790         skb = dev_alloc_skb(size + DATA_BUFFER_ALIGNMENT);
 791         /*  must be burst length alignment  */
 792         if ( skb != NULL )
 793                 skb_reserve(skb, (~((unsigned int)skb->data + (DATA_BUFFER_ALIGNMENT - 1)) & (DATA_BUFFER_ALIGNMENT - 1)) + TX_INBAND_HEADER_LENGTH);
 794         return skb;
 795 }
 796
 797 struct sk_buff* atm_alloc_tx(struct atm_vcc *vcc, unsigned int size)
 798 {
 799         int conn;
 800         struct sk_buff *skb;
 801
 802         /*  oversize packet */
 803         if ( size > aal5s_max_packet_size ) {
 804                 pr_err("atm_alloc_tx: oversize packet\n");
 805                 return NULL;
 806         }
 807         /*  send buffer overflow    */
 808         if ( sk_wmem_alloc_get(sk_atm(vcc)) && !atm_may_send(vcc, size) ) {
 809                 pr_err("atm_alloc_tx: send buffer overflow\n");
 810                 return NULL;
 811         }
 812         conn = find_vcc(vcc);
 813         if ( conn < 0 ) {
 814                 pr_err("atm_alloc_tx: unknown VCC\n");
 815                 return NULL;
 816         }
 817
 818         skb = dev_alloc_skb(size);
 819         if ( skb == NULL ) {
 820                 pr_err("atm_alloc_tx: sk buffer is used up\n");
 821                 return NULL;
 822         }
 823
 824         atomic_add(skb->truesize, &sk_atm(vcc)->sk_wmem_alloc);
 825
 826         return skb;
 827 }
 828
 829 static inline void atm_free_tx_skb_vcc(struct sk_buff *skb, struct atm_vcc *vcc)
 830 {
 831         if ( vcc->pop != NULL )
 832                 vcc->pop(vcc, skb);
 833         else
 834                 dev_kfree_skb_any(skb);
 835 }
 836
 837 static inline struct sk_buff *get_skb_rx_pointer(unsigned int dataptr)
 838 {
 839         unsigned int skb_dataptr;
 840         struct sk_buff *skb;
 841
 842         skb_dataptr = ((dataptr - 1) << 2) | KSEG1;
 843         skb = *(struct sk_buff **)skb_dataptr;
 844
 845         ASSERT((unsigned int)skb >= KSEG0, "invalid skb - skb = %#08x, dataptr = %#08x", (unsigned int)skb, dataptr);
 846         ASSERT(((unsigned int)skb->data | KSEG1) == ((dataptr << 2) | KSEG1), "invalid skb - skb = %#08x, skb->data = %#08x, dataptr = %#08x", (unsigned int)skb, (unsigned int)skb->data, dataptr);
 847
 848         return skb;
 849 }
 850
 851 static inline int get_tx_desc(unsigned int conn)
 852 {
 853         int desc_base = -1;
 854         struct connection *p_conn = &g_atm_priv_data.conn[conn];
 855
 856         if ( p_conn->tx_desc[p_conn->tx_desc_pos].own == 0 ) {
 857                 desc_base = p_conn->tx_desc_pos;
 858                 if ( ++(p_conn->tx_desc_pos) == dma_tx_descriptor_length )
 859                         p_conn->tx_desc_pos = 0;
 860         }
 861
 862         return desc_base;
 863 }
 864
 865 static struct sk_buff* skb_duplicate(struct sk_buff *skb)
 866 {
 867         struct sk_buff *new_skb;
 868
 869         new_skb = alloc_skb_tx(skb->len);
 870         if ( new_skb == NULL )
 871                 return NULL;
 872
 873         skb_put(new_skb, skb->len);
 874         memcpy(new_skb->data, skb->data, skb->len);
 875
 876         return new_skb;
 877 }
 878
 879 static struct sk_buff* skb_break_away_from_protocol(struct sk_buff *skb)
 880 {
 881         struct sk_buff *new_skb;
 882
 883         if ( skb_shared(skb) ) {
 884                 new_skb = skb_clone(skb, GFP_ATOMIC);
 885                 if ( new_skb == NULL )
 886                         return NULL;
 887         } else
 888                 new_skb = skb_get(skb);
 889
 890         skb_dst_drop(new_skb);
 891 #if defined(CONFIG_NF_CONNTRACK) || defined(CONFIG_NF_CONNTRACK_MODULE)
 892         nf_conntrack_put(new_skb->nfct);
 893         new_skb->nfct = NULL;
 894   #ifdef CONFIG_BRIDGE_NETFILTER
 895         nf_bridge_put(new_skb->nf_bridge);
 896         new_skb->nf_bridge = NULL;
 897   #endif
 898 #endif
 899
 900         return new_skb;
 901 }
 902
 903 static inline void mailbox_oam_rx_handler(void)
 904 {
 905         unsigned int vlddes = WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_OAM)->vlddes;
 906         struct rx_descriptor reg_desc;
 907         struct uni_cell_header *header;
 908         int conn;
 909         struct atm_vcc *vcc;
 910         unsigned int i;
 911
 912         for ( i = 0; i < vlddes; i++ ) {
 913                 unsigned int loop_count = 0;
 914
 915                 do {
 916                         reg_desc = g_atm_priv_data.oam_desc[g_atm_priv_data.oam_desc_pos];
 917                         if ( ++loop_count == 1000 )
 918                                 break;
 919                 } while ( reg_desc.own || !reg_desc.c );    //  keep test OWN and C bit until data is ready
 920                 ASSERT(loop_count == 1, "loop_count = %u, own = %d, c = %d, oam_desc_pos = %u", loop_count, (int)reg_desc.own, (int)reg_desc.c, g_atm_priv_data.oam_desc_pos);
 921
 922                 header = (struct uni_cell_header *)&g_atm_priv_data.oam_buf[g_atm_priv_data.oam_desc_pos * RX_DMA_CH_OAM_BUF_SIZE];
 923
 924                 if ( header->pti == ATM_PTI_SEGF5 || header->pti == ATM_PTI_E2EF5 )
 925                         conn = find_vpivci(header->vpi, header->vci);
 926                 else if ( header->vci == 0x03 || header->vci == 0x04 )
 927                         conn = find_vpi(header->vpi);
 928                 else
 929                         conn = -1;
 930
 931                 if ( conn >= 0 && g_atm_priv_data.conn[conn].vcc != NULL ) {
 932                         vcc = g_atm_priv_data.conn[conn].vcc;
 933
 934                         if ( vcc->push_oam != NULL )
 935                                 vcc->push_oam(vcc, header);
 936                         else
 937                                 ifx_push_oam((unsigned char *)header);
 938
 939                         g_atm_priv_data.wrx_oam++;
 940
 941                         adsl_led_flash();
 942                 } else
 943                         g_atm_priv_data.wrx_drop_oam++;
 944
 945                 reg_desc.byteoff = 0;
 946                 reg_desc.datalen = RX_DMA_CH_OAM_BUF_SIZE;
 947                 reg_desc.own = 1;
 948                 reg_desc.c   = 0;
 949
 950                 g_atm_priv_data.oam_desc[g_atm_priv_data.oam_desc_pos] = reg_desc;
 951                 if ( ++g_atm_priv_data.oam_desc_pos == RX_DMA_CH_OAM_DESC_LEN )
 952                         g_atm_priv_data.oam_desc_pos = 0;
 953
 954                 dma_cache_inv((unsigned long)header, CELL_SIZE);
 955                 mailbox_signal(RX_DMA_CH_OAM, 0);
 956         }
 957 }
 958
 959 static inline void mailbox_aal_rx_handler(void)
 960 {
 961         unsigned int vlddes = WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_AAL)->vlddes;
 962         struct rx_descriptor reg_desc;
 963         int conn;
 964         struct atm_vcc *vcc;
 965         struct sk_buff *skb, *new_skb;
 966         struct rx_inband_trailer *trailer;
 967         unsigned int i;
 968
 969         for ( i = 0; i < vlddes; i++ ) {
 970                 unsigned int loop_count = 0;
 971
 972                 do {
 973                         reg_desc = g_atm_priv_data.aal_desc[g_atm_priv_data.aal_desc_pos];
 974                         if ( ++loop_count == 1000 )
 975                                 break;
 976                 } while ( reg_desc.own || !reg_desc.c );    //  keep test OWN and C bit until data is ready
 977                 ASSERT(loop_count == 1, "loop_count = %u, own = %d, c = %d, aal_desc_pos = %u", loop_count, (int)reg_desc.own, (int)reg_desc.c, g_atm_priv_data.aal_desc_pos);
 978
 979                 conn = reg_desc.id;
 980
 981                 if ( g_atm_priv_data.conn[conn].vcc != NULL ) {
 982                         vcc = g_atm_priv_data.conn[conn].vcc;
 983
 984                         skb = get_skb_rx_pointer(reg_desc.dataptr);
 985
 986                         if ( reg_desc.err ) {
 987                                 if ( vcc->qos.aal == ATM_AAL5 ) {
 988                                         trailer = (struct rx_inband_trailer *)((unsigned int)skb->data + ((reg_desc.byteoff + reg_desc.datalen + MAX_RX_PACKET_PADDING_BYTES) & ~MAX_RX_PACKET_PADDING_BYTES));
 989                                         if ( trailer->stw_crc )
 990                                                 g_atm_priv_data.conn[conn].aal5_vcc_crc_err++;
 991                                         if ( trailer->stw_ovz )
 992                                                 g_atm_priv_data.conn[conn].aal5_vcc_oversize_sdu++;
 993                                         g_atm_priv_data.wrx_drop_pdu++;
 994                                 }
 995                                 if ( vcc->stats ) {
 996                                         atomic_inc(&vcc->stats->rx_drop);
 997                                         atomic_inc(&vcc->stats->rx_err);
 998                                 }
 999                                 reg_desc.err = 0;
1000                         } else if ( atm_charge(vcc, skb->truesize) ) {
1001                                 new_skb = alloc_skb_rx();
1002                                 if ( new_skb != NULL ) {
1003 #if defined(ENABLE_LESS_CACHE_INV) && ENABLE_LESS_CACHE_INV
1004                                         if ( reg_desc.byteoff + reg_desc.datalen > LESS_CACHE_INV_LEN )
1005                                                 dma_cache_inv((unsigned long)skb->data + LESS_CACHE_INV_LEN, reg_desc.byteoff + reg_desc.datalen - LESS_CACHE_INV_LEN);
1006 #endif
1007
1008                                         skb_reserve(skb, reg_desc.byteoff);
1009                                         skb_put(skb, reg_desc.datalen);
1010                                         ATM_SKB(skb)->vcc = vcc;
1011
1012                                         vcc->push(vcc, skb);
1013
1014                                         if ( vcc->qos.aal == ATM_AAL5 )
1015                                                 g_atm_priv_data.wrx_pdu++;
1016                                         if ( vcc->stats )
1017                                                 atomic_inc(&vcc->stats->rx);
1018                                         adsl_led_flash();
1019
1020                                         reg_desc.dataptr = (unsigned int)new_skb->data >> 2;
1021                                 } else {
1022                                         atm_return(vcc, skb->truesize);
1023                                         if ( vcc->qos.aal == ATM_AAL5 )
1024                                                 g_atm_priv_data.wrx_drop_pdu++;
1025                                         if ( vcc->stats )
1026                                                 atomic_inc(&vcc->stats->rx_drop);
1027                                 }
1028                         } else {
1029                                 if ( vcc->qos.aal == ATM_AAL5 )
1030                                         g_atm_priv_data.wrx_drop_pdu++;
1031                                 if ( vcc->stats )
1032                                         atomic_inc(&vcc->stats->rx_drop);
1033                         }
1034                 } else {
1035                         g_atm_priv_data.wrx_drop_pdu++;
1036                 }
1037
1038                 reg_desc.byteoff = 0;
1039                 reg_desc.datalen = RX_DMA_CH_AAL_BUF_SIZE;
1040                 reg_desc.own = 1;
1041                 reg_desc.c   = 0;
1042
1043                 g_atm_priv_data.aal_desc[g_atm_priv_data.aal_desc_pos] = reg_desc;
1044                 if ( ++g_atm_priv_data.aal_desc_pos == dma_rx_descriptor_length )
1045                         g_atm_priv_data.aal_desc_pos = 0;
1046
1047                 mailbox_signal(RX_DMA_CH_AAL, 0);
1048         }
1049 }
1050
1051 static void do_ppe_tasklet(unsigned long data)
1052 {
1053         *MBOX_IGU1_ISRC = *MBOX_IGU1_ISR;
1054         mailbox_oam_rx_handler();
1055         mailbox_aal_rx_handler();
1056
1057         if ((*MBOX_IGU1_ISR & ((1 << RX_DMA_CH_AAL) | (1 << RX_DMA_CH_OAM))) != 0)
1058                 tasklet_schedule(&g_dma_tasklet);
1059         else
1060                 enable_irq(PPE_MAILBOX_IGU1_INT);
1061 }
1062
1063 static irqreturn_t mailbox_irq_handler(int irq, void *dev_id)
1064 {
1065         if ( !*MBOX_IGU1_ISR )
1066                 return IRQ_HANDLED;
1067
1068         disable_irq_nosync(PPE_MAILBOX_IGU1_INT);
1069         tasklet_schedule(&g_dma_tasklet);
1070
1071         return IRQ_HANDLED;
1072 }
1073
1074 static inline void mailbox_signal(unsigned int queue, int is_tx)
1075 {
1076         int count = 1000;
1077
1078         if ( is_tx ) {
1079                 while ( MBOX_IGU3_ISR_ISR(queue + FIRST_QSB_QID + 16) && count > 0 )
1080                         count--;
1081                 *MBOX_IGU3_ISRS = MBOX_IGU3_ISRS_SET(queue + FIRST_QSB_QID + 16);
1082         } else {
1083                 while ( MBOX_IGU3_ISR_ISR(queue) && count > 0 )
1084                         count--;
1085                 *MBOX_IGU3_ISRS = MBOX_IGU3_ISRS_SET(queue);
1086         }
1087
1088         ASSERT(count > 0, "queue = %u, is_tx = %d, MBOX_IGU3_ISR = 0x%08x", queue, is_tx, IFX_REG_R32(MBOX_IGU3_ISR));
1089 }
1090
1091 static void set_qsb(struct atm_vcc *vcc, struct atm_qos *qos, unsigned int queue)
1092 {
1093         struct clk *fpi_clk = clk_get_fpi();
1094         unsigned int qsb_clk = clk_get_rate(fpi_clk);
1095         unsigned int qsb_qid = queue + FIRST_QSB_QID;
1096         union qsb_queue_parameter_table qsb_queue_parameter_table = {{0}};
1097         union qsb_queue_vbr_parameter_table qsb_queue_vbr_parameter_table = {{0}};
1098         unsigned int tmp;
1099
1100
1101         /*
1102          *  Peak Cell Rate (PCR) Limiter
1103          */
1104         if ( qos->txtp.max_pcr == 0 )
1105                 qsb_queue_parameter_table.bit.tp = 0;   /*  disable PCR limiter */
1106         else {
1107                 /*  peak cell rate would be slightly lower than requested [maximum_rate / pcr = (qsb_clock / 8) * (time_step / 4) / pcr] */
1108                 tmp = ((qsb_clk * qsb_tstep) >> 5) / qos->txtp.max_pcr + 1;
1109                 /*  check if overflow takes place   */
1110                 qsb_queue_parameter_table.bit.tp = tmp > QSB_TP_TS_MAX ? QSB_TP_TS_MAX : tmp;
1111         }
1112
1113 #if !defined(DISABLE_QOS_WORKAROUND) || !DISABLE_QOS_WORKAROUND
1114         //  A funny issue. Create two PVCs, one UBR and one UBR with max_pcr.
1115         //  Send packets to these two PVCs at same time, it trigger strange behavior.
1116         //  In A1, RAM from 0x80000000 to 0x0x8007FFFF was corrupted with fixed pattern 0x00000000 0x40000000.
1117         //  In A4, PPE firmware keep emiting unknown cell and do not respond to driver.
1118         //  To work around, create UBR always with max_pcr.
1119         //  If user want to create UBR without max_pcr, we give a default one larger than line-rate.
1120         if ( qos->txtp.traffic_class == ATM_UBR && qsb_queue_parameter_table.bit.tp == 0 ) {
1121                 int port = g_atm_priv_data.conn[queue].port;
1122                 unsigned int max_pcr = g_atm_priv_data.port[port].tx_max_cell_rate + 1000;
1123
1124                 tmp = ((qsb_clk * qsb_tstep) >> 5) / max_pcr + 1;
1125                 if ( tmp > QSB_TP_TS_MAX )
1126                         tmp = QSB_TP_TS_MAX;
1127                 else if ( tmp < 1 )
1128                         tmp = 1;
1129                 qsb_queue_parameter_table.bit.tp = tmp;
1130         }
1131 #endif
1132
1133         /*
1134          *  Weighted Fair Queueing Factor (WFQF)
1135          */
1136         switch ( qos->txtp.traffic_class ) {
1137         case ATM_CBR:
1138         case ATM_VBR_RT:
1139                 /*  real time queue gets weighted fair queueing bypass  */
1140                 qsb_queue_parameter_table.bit.wfqf = 0;
1141                 break;
1142         case ATM_VBR_NRT:
1143         case ATM_UBR_PLUS:
1144                 /*  WFQF calculation here is based on virtual cell rates, to reduce granularity for high rates  */
1145                 /*  WFQF is maximum cell rate / garenteed cell rate                                             */
1146                 /*  wfqf = qsb_minimum_cell_rate * QSB_WFQ_NONUBR_MAX / requested_minimum_peak_cell_rate        */
1147                 if ( qos->txtp.min_pcr == 0 )
1148                         qsb_queue_parameter_table.bit.wfqf = QSB_WFQ_NONUBR_MAX;
1149                 else {
1150                         tmp = QSB_GCR_MIN * QSB_WFQ_NONUBR_MAX / qos->txtp.min_pcr;
1151                         if ( tmp == 0 )
1152                                 qsb_queue_parameter_table.bit.wfqf = 1;
1153                         else if ( tmp > QSB_WFQ_NONUBR_MAX )
1154                                 qsb_queue_parameter_table.bit.wfqf = QSB_WFQ_NONUBR_MAX;
1155                         else
1156                                 qsb_queue_parameter_table.bit.wfqf = tmp;
1157                 }
1158                 break;
1159         default:
1160         case ATM_UBR:
1161                 qsb_queue_parameter_table.bit.wfqf = QSB_WFQ_UBR_BYPASS;
1162         }
1163
1164         /*
1165          *  Sustained Cell Rate (SCR) Leaky Bucket Shaper VBR.0/VBR.1
1166          */
1167         if ( qos->txtp.traffic_class == ATM_VBR_RT || qos->txtp.traffic_class == ATM_VBR_NRT ) {
1168 #if 0
1169                 if ( qos->txtp.scr == 0 ) {
1170 #endif
1171                         /*  disable shaper  */
1172                         qsb_queue_vbr_parameter_table.bit.taus = 0;
1173                         qsb_queue_vbr_parameter_table.bit.ts = 0;
1174 #if 0
1175                 } else {
1176                         /*  Cell Loss Priority  (CLP)   */
1177                         if ( (vcc->atm_options & ATM_ATMOPT_CLP) )
1178                                 /*  CLP1    */
1179                                 qsb_queue_parameter_table.bit.vbr = 1;
1180                         else
1181                                 /*  CLP0    */
1182                                 qsb_queue_parameter_table.bit.vbr = 0;
1183                         /*  Rate Shaper Parameter (TS) and Burst Tolerance Parameter for SCR (tauS) */
1184                         tmp = ((qsb_clk * qsb_tstep) >> 5) / qos->txtp.scr + 1;
1185                         qsb_queue_vbr_parameter_table.bit.ts = tmp > QSB_TP_TS_MAX ? QSB_TP_TS_MAX : tmp;
1186                         tmp = (qos->txtp.mbs - 1) * (qsb_queue_vbr_parameter_table.bit.ts - qsb_queue_parameter_table.bit.tp) / 64;
1187                         if ( tmp == 0 )
1188                                 qsb_queue_vbr_parameter_table.bit.taus = 1;
1189                         else if ( tmp > QSB_TAUS_MAX )
1190                                 qsb_queue_vbr_parameter_table.bit.taus = QSB_TAUS_MAX;
1191                         else
1192                                 qsb_queue_vbr_parameter_table.bit.taus = tmp;
1193                 }
1194 #endif
1195         } else {
1196                 qsb_queue_vbr_parameter_table.bit.taus = 0;
1197                 qsb_queue_vbr_parameter_table.bit.ts = 0;
1198         }
1199
1200         /*  Queue Parameter Table (QPT) */
1201         *QSB_RTM   = QSB_RTM_DM_SET(QSB_QPT_SET_MASK);
1202         *QSB_RTD   = QSB_RTD_TTV_SET(qsb_queue_parameter_table.dword);
1203         *QSB_RAMAC = QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE) | QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_QPT) | QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW) | QSB_RAMAC_TESEL_SET(qsb_qid);
1204         /*  Queue VBR Paramter Table (QVPT) */
1205         *QSB_RTM   = QSB_RTM_DM_SET(QSB_QVPT_SET_MASK);
1206         *QSB_RTD   = QSB_RTD_TTV_SET(qsb_queue_vbr_parameter_table.dword);
1207         *QSB_RAMAC = QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE) | QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_VBR) | QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW) | QSB_RAMAC_TESEL_SET(qsb_qid);
1208
1209 }
1210
1211 static void qsb_global_set(void)
1212 {
1213         struct clk *fpi_clk = clk_get_fpi();
1214         unsigned int qsb_clk = clk_get_rate(fpi_clk);
1215         int i;
1216         unsigned int tmp1, tmp2, tmp3;
1217
1218         *QSB_ICDV = QSB_ICDV_TAU_SET(qsb_tau);
1219         *QSB_SBL  = QSB_SBL_SBL_SET(qsb_srvm);
1220         *QSB_CFG  = QSB_CFG_TSTEPC_SET(qsb_tstep >> 1);
1221
1222         /*
1223          *  set SCT and SPT per port
1224          */
1225         for ( i = 0; i < ATM_PORT_NUMBER; i++ ) {
1226                 if ( g_atm_priv_data.port[i].tx_max_cell_rate != 0 ) {
1227                         tmp1 = ((qsb_clk * qsb_tstep) >> 1) / g_atm_priv_data.port[i].tx_max_cell_rate;
1228                         tmp2 = tmp1 >> 6;                   /*  integer value of Tsb    */
1229                         tmp3 = (tmp1 & ((1 << 6) - 1)) + 1; /*  fractional part of Tsb  */
1230                         /*  carry over to integer part (?)  */
1231                         if ( tmp3 == (1 << 6) ) {
1232                                 tmp3 = 0;
1233                                 tmp2++;
1234                         }
1235                         if ( tmp2 == 0 )
1236                                 tmp2 = tmp3 = 1;
1237                         /*  1. set mask                                 */
1238                         /*  2. write value to data transfer register    */
1239                         /*  3. start the tranfer                        */
1240                         /*  SCT (FracRate)  */
1241                         *QSB_RTM   = QSB_RTM_DM_SET(QSB_SET_SCT_MASK);
1242                         *QSB_RTD   = QSB_RTD_TTV_SET(tmp3);
1243                         *QSB_RAMAC = QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE) |
1244                                         QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_SCT) |
1245                                         QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW) |
1246                                         QSB_RAMAC_TESEL_SET(i & 0x01);
1247                         /*  SPT (SBV + PN + IntRage)    */
1248                         *QSB_RTM   = QSB_RTM_DM_SET(QSB_SET_SPT_MASK);
1249                         *QSB_RTD   = QSB_RTD_TTV_SET(QSB_SPT_SBV_VALID | QSB_SPT_PN_SET(i & 0x01) | QSB_SPT_INTRATE_SET(tmp2));
1250                         *QSB_RAMAC = QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE) |
1251                                 QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_SPT) |
1252                                 QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW) |
1253                                 QSB_RAMAC_TESEL_SET(i & 0x01);
1254                 }
1255         }
1256 }
1257
1258 static inline void set_htu_entry(unsigned int vpi, unsigned int vci, unsigned int queue, int aal5, int is_retx)
1259 {
1260         struct htu_entry htu_entry = {
1261                 res1:       0x00,
1262                 clp:        is_retx ? 0x01 : 0x00,
1263                 pid:        g_atm_priv_data.conn[queue].port & 0x01,
1264                 vpi:        vpi,
1265                 vci:        vci,
1266                 pti:        0x00,
1267                 vld:        0x01};
1268
1269         struct htu_mask htu_mask = {
1270                 set:        0x01,
1271                 clp:        0x01,
1272                 pid_mask:   0x02,
1273                 vpi_mask:   0x00,
1274                 vci_mask:   0x0000,
1275                 pti_mask:   0x03,   //  0xx, user data
1276                 clear:      0x00};
1277
1278         struct htu_result htu_result = {
1279                 res1:       0x00,
1280                 cellid:     queue,
1281                 res2:       0x00,
1282                 type:       aal5 ? 0x00 : 0x01,
1283                 ven:        0x01,
1284                 res3:       0x00,
1285                 qid:        queue};
1286
1287         *HTU_RESULT(queue + OAM_HTU_ENTRY_NUMBER) = htu_result;
1288         *HTU_MASK(queue + OAM_HTU_ENTRY_NUMBER)   = htu_mask;
1289         *HTU_ENTRY(queue + OAM_HTU_ENTRY_NUMBER)  = htu_entry;
1290 }
1291
1292 static inline void clear_htu_entry(unsigned int queue)
1293 {
1294         HTU_ENTRY(queue + OAM_HTU_ENTRY_NUMBER)->vld = 0;
1295 }
1296
1297 static void validate_oam_htu_entry(void)
1298 {
1299         HTU_ENTRY(OAM_F4_SEG_HTU_ENTRY)->vld = 1;
1300         HTU_ENTRY(OAM_F4_TOT_HTU_ENTRY)->vld = 1;
1301         HTU_ENTRY(OAM_F5_HTU_ENTRY)->vld = 1;
1302 }
1303
1304 static void invalidate_oam_htu_entry(void)
1305 {
1306         HTU_ENTRY(OAM_F4_SEG_HTU_ENTRY)->vld = 0;
1307         HTU_ENTRY(OAM_F4_TOT_HTU_ENTRY)->vld = 0;
1308         HTU_ENTRY(OAM_F5_HTU_ENTRY)->vld = 0;
1309 }
1310
1311 static inline int find_vpi(unsigned int vpi)
1312 {
1313         int i;
1314         unsigned int bit;
1315
1316         for ( i = 0, bit = 1; i < MAX_PVC_NUMBER; i++, bit <<= 1 ) {
1317                 if ( (g_atm_priv_data.conn_table & bit) != 0
1318                                 && g_atm_priv_data.conn[i].vcc != NULL
1319                                 && vpi == g_atm_priv_data.conn[i].vcc->vpi )
1320                         return i;
1321         }
1322
1323         return -1;
1324 }
1325
1326 static inline int find_vpivci(unsigned int vpi, unsigned int vci)
1327 {
1328         int i;
1329         unsigned int bit;
1330
1331         for ( i = 0, bit = 1; i < MAX_PVC_NUMBER; i++, bit <<= 1 ) {
1332                 if ( (g_atm_priv_data.conn_table & bit) != 0
1333                                 && g_atm_priv_data.conn[i].vcc != NULL
1334                                 && vpi == g_atm_priv_data.conn[i].vcc->vpi
1335                                 && vci == g_atm_priv_data.conn[i].vcc->vci )
1336                         return i;
1337         }
1338
1339         return -1;
1340 }
1341
1342 static inline int find_vcc(struct atm_vcc *vcc)
1343 {
1344         int i;
1345         unsigned int bit;
1346
1347         for ( i = 0, bit = 1; i < MAX_PVC_NUMBER; i++, bit <<= 1 ) {
1348                 if ( (g_atm_priv_data.conn_table & bit) != 0
1349                         && g_atm_priv_data.conn[i].vcc == vcc )
1350                 return i;
1351         }
1352
1353         return -1;
1354 }
1355
1356 static inline int ifx_atm_version(const struct ltq_atm_ops *ops, char *buf)
1357 {
1358         int len = 0;
1359         unsigned int major, minor;
1360
1361         ops->fw_ver(&major, &minor);
1362
1363         len += sprintf(buf + len, "ATM%d.%d.%d", IFX_ATM_VER_MAJOR, IFX_ATM_VER_MID, IFX_ATM_VER_MINOR);
1364         len += sprintf(buf + len, "    ATM (A1) firmware version %d.%d\n", major, minor);
1365
1366         return len;
1367 }
1368
1369 static inline void check_parameters(void)
1370 {
1371         /*  Please refer to Amazon spec 15.4 for setting these values.  */
1372         if ( qsb_tau < 1 )
1373                 qsb_tau = 1;
1374         if ( qsb_tstep < 1 )
1375                 qsb_tstep = 1;
1376         else if ( qsb_tstep > 4 )
1377                 qsb_tstep = 4;
1378         else if ( qsb_tstep == 3 )
1379                 qsb_tstep = 2;
1380
1381         /*  There is a delay between PPE write descriptor and descriptor is       */
1382         /*  really stored in memory. Host also has this delay when writing        */
1383         /*  descriptor. So PPE will use this value to determine if the write      */
1384         /*  operation makes effect.                                               */
1385         if ( write_descriptor_delay < 0 )
1386                 write_descriptor_delay = 0;
1387
1388         if ( aal5_fill_pattern < 0 )
1389                 aal5_fill_pattern = 0;
1390         else
1391                 aal5_fill_pattern &= 0xFF;
1392
1393         /*  Because of the limitation of length field in descriptors, the packet  */
1394         /*  size could not be larger than 64K minus overhead size.                */
1395         if ( aal5r_max_packet_size < 0 )
1396                 aal5r_max_packet_size = 0;
1397         else if ( aal5r_max_packet_size >= 65535 - MAX_RX_FRAME_EXTRA_BYTES )
1398                 aal5r_max_packet_size = 65535 - MAX_RX_FRAME_EXTRA_BYTES;
1399         if ( aal5r_min_packet_size < 0 )
1400                 aal5r_min_packet_size = 0;
1401         else if ( aal5r_min_packet_size > aal5r_max_packet_size )
1402                 aal5r_min_packet_size = aal5r_max_packet_size;
1403         if ( aal5s_max_packet_size < 0 )
1404                 aal5s_max_packet_size = 0;
1405         else if ( aal5s_max_packet_size >= 65535 - MAX_TX_FRAME_EXTRA_BYTES )
1406                 aal5s_max_packet_size = 65535 - MAX_TX_FRAME_EXTRA_BYTES;
1407         if ( aal5s_min_packet_size < 0 )
1408                 aal5s_min_packet_size = 0;
1409         else if ( aal5s_min_packet_size > aal5s_max_packet_size )
1410                 aal5s_min_packet_size = aal5s_max_packet_size;
1411
1412         if ( dma_rx_descriptor_length < 2 )
1413                 dma_rx_descriptor_length = 2;
1414         if ( dma_tx_descriptor_length < 2 )
1415                 dma_tx_descriptor_length = 2;
1416         if ( dma_rx_clp1_descriptor_threshold < 0 )
1417                 dma_rx_clp1_descriptor_threshold = 0;
1418         else if ( dma_rx_clp1_descriptor_threshold > dma_rx_descriptor_length )
1419                 dma_rx_clp1_descriptor_threshold = dma_rx_descriptor_length;
1420
1421         if ( dma_tx_descriptor_length < 2 )
1422                 dma_tx_descriptor_length = 2;
1423 }
1424
1425 static inline int init_priv_data(void)
1426 {
1427         void *p;
1428         int i;
1429         struct rx_descriptor rx_desc = {0};
1430         struct sk_buff *skb;
1431         volatile struct tx_descriptor *p_tx_desc;
1432         struct sk_buff **ppskb;
1433
1434         //  clear atm private data structure
1435         memset(&g_atm_priv_data, 0, sizeof(g_atm_priv_data));
1436
1437         //  allocate memory for RX (AAL) descriptors
1438         p = kzalloc(dma_rx_descriptor_length * sizeof(struct rx_descriptor) + DESC_ALIGNMENT, GFP_KERNEL);
1439         if ( p == NULL )
1440                 return -1;
1441         dma_cache_wback_inv((unsigned long)p, dma_rx_descriptor_length * sizeof(struct rx_descriptor) + DESC_ALIGNMENT);
1442         g_atm_priv_data.aal_desc_base = p;
1443         p = (void *)((((unsigned int)p + DESC_ALIGNMENT - 1) & ~(DESC_ALIGNMENT - 1)) | KSEG1);
1444         g_atm_priv_data.aal_desc = (volatile struct rx_descriptor *)p;
1445
1446         //  allocate memory for RX (OAM) descriptors
1447         p = kzalloc(RX_DMA_CH_OAM_DESC_LEN * sizeof(struct rx_descriptor) + DESC_ALIGNMENT, GFP_KERNEL);
1448         if ( p == NULL )
1449                 return -1;
1450         dma_cache_wback_inv((unsigned long)p, RX_DMA_CH_OAM_DESC_LEN * sizeof(struct rx_descriptor) + DESC_ALIGNMENT);
1451         g_atm_priv_data.oam_desc_base = p;
1452         p = (void *)((((unsigned int)p + DESC_ALIGNMENT - 1) & ~(DESC_ALIGNMENT - 1)) | KSEG1);
1453         g_atm_priv_data.oam_desc = (volatile struct rx_descriptor *)p;
1454
1455         //  allocate memory for RX (OAM) buffer
1456         p = kzalloc(RX_DMA_CH_OAM_DESC_LEN * RX_DMA_CH_OAM_BUF_SIZE + DATA_BUFFER_ALIGNMENT, GFP_KERNEL);
1457         if ( p == NULL )
1458                 return -1;
1459         dma_cache_wback_inv((unsigned long)p, RX_DMA_CH_OAM_DESC_LEN * RX_DMA_CH_OAM_BUF_SIZE + DATA_BUFFER_ALIGNMENT);
1460         g_atm_priv_data.oam_buf_base = p;
1461         p = (void *)(((unsigned int)p + DATA_BUFFER_ALIGNMENT - 1) & ~(DATA_BUFFER_ALIGNMENT - 1));
1462         g_atm_priv_data.oam_buf = p;
1463
1464         //  allocate memory for TX descriptors
1465         p = kzalloc(MAX_PVC_NUMBER * dma_tx_descriptor_length * sizeof(struct tx_descriptor) + DESC_ALIGNMENT, GFP_KERNEL);
1466         if ( p == NULL )
1467                 return -1;
1468         dma_cache_wback_inv((unsigned long)p, MAX_PVC_NUMBER * dma_tx_descriptor_length * sizeof(struct tx_descriptor) + DESC_ALIGNMENT);
1469         g_atm_priv_data.tx_desc_base = p;
1470
1471         //  allocate memory for TX skb pointers
1472         p = kzalloc(MAX_PVC_NUMBER * dma_tx_descriptor_length * sizeof(struct sk_buff *) + 4, GFP_KERNEL);
1473         if ( p == NULL )
1474                 return -1;
1475         dma_cache_wback_inv((unsigned long)p, MAX_PVC_NUMBER * dma_tx_descriptor_length * sizeof(struct sk_buff *) + 4);
1476         g_atm_priv_data.tx_skb_base = p;
1477
1478         //  setup RX (AAL) descriptors
1479         rx_desc.own     = 1;
1480         rx_desc.c       = 0;
1481         rx_desc.sop     = 1;
1482         rx_desc.eop     = 1;
1483         rx_desc.byteoff = 0;
1484         rx_desc.id      = 0;
1485         rx_desc.err     = 0;
1486         rx_desc.datalen = RX_DMA_CH_AAL_BUF_SIZE;
1487         for ( i = 0; i < dma_rx_descriptor_length; i++ ) {
1488                 skb = alloc_skb_rx();
1489                 if ( skb == NULL )
1490                         return -1;
1491                 rx_desc.dataptr = ((unsigned int)skb->data >> 2) & 0x0FFFFFFF;
1492                 g_atm_priv_data.aal_desc[i] = rx_desc;
1493         }
1494
1495         //  setup RX (OAM) descriptors
1496         p = (void *)((unsigned int)g_atm_priv_data.oam_buf | KSEG1);
1497         rx_desc.own     = 1;
1498         rx_desc.c       = 0;
1499         rx_desc.sop     = 1;
1500         rx_desc.eop     = 1;
1501         rx_desc.byteoff = 0;
1502         rx_desc.id      = 0;
1503         rx_desc.err     = 0;
1504         rx_desc.datalen = RX_DMA_CH_OAM_BUF_SIZE;
1505         for ( i = 0; i < RX_DMA_CH_OAM_DESC_LEN; i++ ) {
1506                 rx_desc.dataptr = ((unsigned int)p >> 2) & 0x0FFFFFFF;
1507                 g_atm_priv_data.oam_desc[i] = rx_desc;
1508                 p = (void *)((unsigned int)p + RX_DMA_CH_OAM_BUF_SIZE);
1509         }
1510
1511         //  setup TX descriptors and skb pointers
1512         p_tx_desc = (volatile struct tx_descriptor *)((((unsigned int)g_atm_priv_data.tx_desc_base + DESC_ALIGNMENT - 1) & ~(DESC_ALIGNMENT - 1)) | KSEG1);
1513         ppskb = (struct sk_buff **)(((unsigned int)g_atm_priv_data.tx_skb_base + 3) & ~3);
1514         for ( i = 0; i < MAX_PVC_NUMBER; i++ ) {
1515                 g_atm_priv_data.conn[i].tx_desc = &p_tx_desc[i * dma_tx_descriptor_length];
1516                 g_atm_priv_data.conn[i].tx_skb  = &ppskb[i * dma_tx_descriptor_length];
1517         }
1518
1519         for ( i = 0; i < ATM_PORT_NUMBER; i++ )
1520                 g_atm_priv_data.port[i].tx_max_cell_rate = DEFAULT_TX_LINK_RATE;
1521
1522         return 0;
1523 }
1524
1525 static inline void clear_priv_data(void)
1526 {
1527         int i, j;
1528         struct sk_buff *skb;
1529
1530         for ( i = 0; i < MAX_PVC_NUMBER; i++ ) {
1531                 if ( g_atm_priv_data.conn[i].tx_skb != NULL ) {
1532                         for ( j = 0; j < dma_tx_descriptor_length; j++ )
1533                                 if ( g_atm_priv_data.conn[i].tx_skb[j] != NULL )
1534                                         dev_kfree_skb_any(g_atm_priv_data.conn[i].tx_skb[j]);
1535                 }
1536         }
1537
1538         if ( g_atm_priv_data.tx_skb_base != NULL )
1539                 kfree(g_atm_priv_data.tx_skb_base);
1540
1541         if ( g_atm_priv_data.tx_desc_base != NULL )
1542                 kfree(g_atm_priv_data.tx_desc_base);
1543
1544         if ( g_atm_priv_data.oam_buf_base != NULL )
1545                 kfree(g_atm_priv_data.oam_buf_base);
1546
1547         if ( g_atm_priv_data.oam_desc_base != NULL )
1548                 kfree(g_atm_priv_data.oam_desc_base);
1549
1550         if ( g_atm_priv_data.aal_desc_base != NULL ) {
1551                 for ( i = 0; i < dma_rx_descriptor_length; i++ ) {
1552                         if ( g_atm_priv_data.aal_desc[i].sop || g_atm_priv_data.aal_desc[i].eop ) { //  descriptor initialized
1553                                 skb = get_skb_rx_pointer(g_atm_priv_data.aal_desc[i].dataptr);
1554                                 dev_kfree_skb_any(skb);
1555                         }
1556                 }
1557                 kfree(g_atm_priv_data.aal_desc_base);
1558         }
1559 }
1560
1561 static inline void init_rx_tables(void)
1562 {
1563         int i;
1564         struct wrx_queue_config wrx_queue_config = {0};
1565         struct wrx_dma_channel_config wrx_dma_channel_config = {0};
1566         struct htu_entry htu_entry = {0};
1567         struct htu_result htu_result = {0};
1568         struct htu_mask htu_mask = {
1569                 set:        0x01,
1570                 clp:        0x01,
1571                 pid_mask:   0x00,
1572                 vpi_mask:   0x00,
1573                 vci_mask:   0x00,
1574                 pti_mask:   0x00,
1575                 clear:      0x00
1576         };
1577
1578         /*
1579          *  General Registers
1580          */
1581         *CFG_WRX_HTUTS  = MAX_PVC_NUMBER + OAM_HTU_ENTRY_NUMBER;
1582 #ifndef CONFIG_AMAZON_SE
1583         *CFG_WRX_QNUM   = MAX_QUEUE_NUMBER;
1584 #endif
1585         *CFG_WRX_DCHNUM = RX_DMA_CH_TOTAL;
1586         *WRX_DMACH_ON   = (1 << RX_DMA_CH_TOTAL) - 1;
1587         *WRX_HUNT_BITTH = DEFAULT_RX_HUNT_BITTH;
1588
1589         /*
1590          *  WRX Queue Configuration Table
1591          */
1592         wrx_queue_config.uumask    = 0xFF;
1593         wrx_queue_config.cpimask   = 0xFF;
1594         wrx_queue_config.uuexp     = 0;
1595         wrx_queue_config.cpiexp    = 0;
1596         wrx_queue_config.mfs       = aal5r_max_packet_size;
1597         wrx_queue_config.oversize  = aal5r_max_packet_size;
1598         wrx_queue_config.undersize = aal5r_min_packet_size;
1599         wrx_queue_config.errdp     = aal5r_drop_error_packet;
1600         wrx_queue_config.dmach     = RX_DMA_CH_AAL;
1601         for ( i = 0; i < MAX_QUEUE_NUMBER; i++ )
1602                 *WRX_QUEUE_CONFIG(i) = wrx_queue_config;
1603         WRX_QUEUE_CONFIG(OAM_RX_QUEUE)->dmach = RX_DMA_CH_OAM;
1604
1605         /*
1606          *  WRX DMA Channel Configuration Table
1607          */
1608         wrx_dma_channel_config.chrl   = 0;
1609         wrx_dma_channel_config.clp1th = dma_rx_clp1_descriptor_threshold;
1610         wrx_dma_channel_config.mode   = 0;
1611         wrx_dma_channel_config.rlcfg  = 0;
1612
1613         wrx_dma_channel_config.deslen = RX_DMA_CH_OAM_DESC_LEN;
1614         wrx_dma_channel_config.desba  = ((unsigned int)g_atm_priv_data.oam_desc >> 2) & 0x0FFFFFFF;
1615         *WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_OAM) = wrx_dma_channel_config;
1616
1617         wrx_dma_channel_config.deslen = dma_rx_descriptor_length;
1618         wrx_dma_channel_config.desba  = ((unsigned int)g_atm_priv_data.aal_desc >> 2) & 0x0FFFFFFF;
1619         *WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_AAL) = wrx_dma_channel_config;
1620
1621         /*
1622          *  HTU Tables
1623          */
1624         for (i = 0; i < MAX_PVC_NUMBER; i++) {
1625                 htu_result.qid = (unsigned int)i;
1626
1627                 *HTU_ENTRY(i + OAM_HTU_ENTRY_NUMBER)  = htu_entry;
1628                 *HTU_MASK(i + OAM_HTU_ENTRY_NUMBER)   = htu_mask;
1629                 *HTU_RESULT(i + OAM_HTU_ENTRY_NUMBER) = htu_result;
1630         }
1631
1632         /*  OAM HTU Entry   */
1633         htu_entry.vci = 0x03;
1634         htu_mask.pid_mask = 0x03;
1635         htu_mask.vpi_mask = 0xFF;
1636         htu_mask.vci_mask = 0x0000;
1637         htu_mask.pti_mask = 0x07;
1638         htu_result.cellid = OAM_RX_QUEUE;
1639         htu_result.type   = 1;
1640         htu_result.ven    = 1;
1641         htu_result.qid    = OAM_RX_QUEUE;
1642         *HTU_RESULT(OAM_F4_SEG_HTU_ENTRY) = htu_result;
1643         *HTU_MASK(OAM_F4_SEG_HTU_ENTRY)   = htu_mask;
1644         *HTU_ENTRY(OAM_F4_SEG_HTU_ENTRY)  = htu_entry;
1645         htu_entry.vci     = 0x04;
1646         htu_result.cellid = OAM_RX_QUEUE;
1647         htu_result.type   = 1;
1648         htu_result.ven    = 1;
1649         htu_result.qid    = OAM_RX_QUEUE;
1650         *HTU_RESULT(OAM_F4_TOT_HTU_ENTRY) = htu_result;
1651         *HTU_MASK(OAM_F4_TOT_HTU_ENTRY)   = htu_mask;
1652         *HTU_ENTRY(OAM_F4_TOT_HTU_ENTRY)  = htu_entry;
1653         htu_entry.vci     = 0x00;
1654         htu_entry.pti     = 0x04;
1655         htu_mask.vci_mask = 0xFFFF;
1656         htu_mask.pti_mask = 0x01;
1657         htu_result.cellid = OAM_RX_QUEUE;
1658         htu_result.type   = 1;
1659         htu_result.ven    = 1;
1660         htu_result.qid    = OAM_RX_QUEUE;
1661         *HTU_RESULT(OAM_F5_HTU_ENTRY) = htu_result;
1662         *HTU_MASK(OAM_F5_HTU_ENTRY)   = htu_mask;
1663         *HTU_ENTRY(OAM_F5_HTU_ENTRY)  = htu_entry;
1664 }
1665
1666 static inline void init_tx_tables(void)
1667 {
1668         int i;
1669         struct wtx_queue_config wtx_queue_config = {0};
1670         struct wtx_dma_channel_config wtx_dma_channel_config = {0};
1671         struct wtx_port_config wtx_port_config = {
1672                 res1:   0,
1673                 qid:    0,
1674                 qsben:  1
1675         };
1676
1677         /*
1678          *  General Registers
1679          */
1680         *CFG_WTX_DCHNUM     = MAX_TX_DMA_CHANNEL_NUMBER;
1681         *WTX_DMACH_ON       = ((1 << MAX_TX_DMA_CHANNEL_NUMBER) - 1) ^ ((1 << FIRST_QSB_QID) - 1);
1682         *CFG_WRDES_DELAY    = write_descriptor_delay;
1683
1684         /*
1685          *  WTX Port Configuration Table
1686          */
1687         for ( i = 0; i < ATM_PORT_NUMBER; i++ )
1688                 *WTX_PORT_CONFIG(i) = wtx_port_config;
1689
1690         /*
1691          *  WTX Queue Configuration Table
1692          */
1693         wtx_queue_config.qsben = 1;
1694         wtx_queue_config.sbid  = 0;
1695         for ( i = 0; i < MAX_TX_DMA_CHANNEL_NUMBER; i++ ) {
1696                 wtx_queue_config.qsb_vcid = i;
1697                 *WTX_QUEUE_CONFIG(i) = wtx_queue_config;
1698         }
1699
1700         /*
1701          *  WTX DMA Channel Configuration Table
1702          */
1703         wtx_dma_channel_config.mode   = 0;
1704         wtx_dma_channel_config.deslen = 0;
1705         wtx_dma_channel_config.desba  = 0;
1706         for ( i = 0; i < FIRST_QSB_QID; i++ )
1707                 *WTX_DMA_CHANNEL_CONFIG(i) = wtx_dma_channel_config;
1708         /*  normal connection   */
1709         wtx_dma_channel_config.deslen = dma_tx_descriptor_length;
1710         for ( ; i < MAX_TX_DMA_CHANNEL_NUMBER ; i++ ) {
1711                 wtx_dma_channel_config.desba = ((unsigned int)g_atm_priv_data.conn[i - FIRST_QSB_QID].tx_desc >> 2) & 0x0FFFFFFF;
1712                 *WTX_DMA_CHANNEL_CONFIG(i) = wtx_dma_channel_config;
1713         }
1714 }
1715
1716 static int atm_showtime_enter(struct port_cell_info *port_cell, void *xdata_addr)
1717 {
1718         int i, j;
1719
1720         ASSERT(port_cell != NULL, "port_cell is NULL");
1721         ASSERT(xdata_addr != NULL, "xdata_addr is NULL");
1722
1723         for ( j = 0; j < ATM_PORT_NUMBER && j < port_cell->port_num; j++ )
1724                 if ( port_cell->tx_link_rate[j] > 0 )
1725                         break;
1726         for ( i = 0; i < ATM_PORT_NUMBER && i < port_cell->port_num; i++ )
1727                 g_atm_priv_data.port[i].tx_max_cell_rate =
1728                         port_cell->tx_link_rate[i] > 0 ? port_cell->tx_link_rate[i] : port_cell->tx_link_rate[j];
1729
1730         qsb_global_set();
1731
1732         for ( i = 0; i < MAX_PVC_NUMBER; i++ )
1733                 if ( g_atm_priv_data.conn[i].vcc != NULL )
1734                         set_qsb(g_atm_priv_data.conn[i].vcc, &g_atm_priv_data.conn[i].vcc->qos, i);
1735
1736         //  TODO: ReTX set xdata_addr
1737         g_xdata_addr = xdata_addr;
1738
1739         g_showtime = 1;
1740
1741 #if defined(CONFIG_VR9)
1742         IFX_REG_W32(0x0F, UTP_CFG);
1743 #endif
1744
1745         printk("enter showtime, cell rate: 0 - %d, 1 - %d, xdata addr: 0x%08x\n",
1746                 g_atm_priv_data.port[0].tx_max_cell_rate,
1747                 g_atm_priv_data.port[1].tx_max_cell_rate,
1748                 (unsigned int)g_xdata_addr);
1749
1750         return 0;
1751 }
1752
1753 static int atm_showtime_exit(void)
1754 {
1755         if ( !g_showtime )
1756                 return -1;
1757
1758 #if defined(CONFIG_VR9)
1759         IFX_REG_W32(0x00, UTP_CFG);
1760 #endif
1761         g_showtime = 0;
1762         g_xdata_addr = NULL;
1763         printk("leave showtime\n");
1764         return 0;
1765 }
1766
1767 extern struct ltq_atm_ops ar9_ops;
1768 extern struct ltq_atm_ops vr9_ops;
1769 extern struct ltq_atm_ops danube_ops;
1770 extern struct ltq_atm_ops ase_ops;
1771
1772 static const struct of_device_id ltq_atm_match[] = {
1773 #ifdef CONFIG_DANUBE
1774         { .compatible = "lantiq,ppe-danube", .data = &danube_ops },
1775 #elif defined CONFIG_AMAZON_SE
1776         { .compatible = "lantiq,ppe-ase", .data = &ase_ops },
1777 #elif defined CONFIG_AR9
1778         { .compatible = "lantiq,ppe-arx100", .data = &ar9_ops },
1779 #elif defined CONFIG_VR9
1780         { .compatible = "lantiq,ppe-xrx200", .data = &vr9_ops },
1781 #endif
1782         {},
1783 };
1784 MODULE_DEVICE_TABLE(of, ltq_atm_match);
1785
1786 static int ltq_atm_probe(struct platform_device *pdev)
1787 {
1788         const struct of_device_id *match;
1789         struct ltq_atm_ops *ops = NULL;
1790         int ret;
1791         int port_num;
1792         struct port_cell_info port_cell = {0};
1793         int i, j;
1794         char ver_str[256];
1795
1796         match = of_match_device(ltq_atm_match, &pdev->dev);
1797         if (!match) {
1798                 dev_err(&pdev->dev, "failed to find matching device\n");
1799                 return -ENOENT;
1800         }
1801         ops = (struct ltq_atm_ops *) match->data;
1802
1803         check_parameters();
1804
1805         ret = init_priv_data();
1806         if ( ret != 0 ) {
1807                 pr_err("INIT_PRIV_DATA_FAIL\n");
1808                 goto INIT_PRIV_DATA_FAIL;
1809         }
1810
1811         ops->init();
1812         init_rx_tables();
1813         init_tx_tables();
1814
1815         /*  create devices  */
1816         for ( port_num = 0; port_num < ATM_PORT_NUMBER; port_num++ ) {
1817                 g_atm_priv_data.port[port_num].dev = atm_dev_register("ifxmips_atm", NULL, &g_ifx_atm_ops, -1, NULL);
1818                 if ( !g_atm_priv_data.port[port_num].dev ) {
1819                         pr_err("failed to register atm device %d!\n", port_num);
1820                         ret = -EIO;
1821                         goto ATM_DEV_REGISTER_FAIL;
1822                 } else {
1823                         g_atm_priv_data.port[port_num].dev->ci_range.vpi_bits = 8;
1824                         g_atm_priv_data.port[port_num].dev->ci_range.vci_bits = 16;
1825                         g_atm_priv_data.port[port_num].dev->link_rate = g_atm_priv_data.port[port_num].tx_max_cell_rate;
1826                         g_atm_priv_data.port[port_num].dev->dev_data = (void*)port_num;
1827                 }
1828         }
1829
1830         /*  register interrupt handler  */
1831 #if LINUX_VERSION_CODE >= KERNEL_VERSION(4,1,0)
1832         ret = request_irq(PPE_MAILBOX_IGU1_INT, mailbox_irq_handler, 0, "atm_mailbox_isr", &g_atm_priv_data);
1833 #else
1834         ret = request_irq(PPE_MAILBOX_IGU1_INT, mailbox_irq_handler, IRQF_DISABLED, "atm_mailbox_isr", &g_atm_priv_data);
1835 #endif
1836         if ( ret ) {
1837                 if ( ret == -EBUSY ) {
1838                         pr_err("IRQ may be occupied by other driver, please reconfig to disable it.\n");
1839                 } else {
1840                         pr_err("request_irq fail irq:%d\n", PPE_MAILBOX_IGU1_INT);
1841                 }
1842                 goto REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL;
1843         }
1844         disable_irq(PPE_MAILBOX_IGU1_INT);
1845
1846
1847         ret = ops->start(0);
1848         if ( ret ) {
1849                 pr_err("ifx_pp32_start fail!\n");
1850                 goto PP32_START_FAIL;
1851         }
1852
1853         port_cell.port_num = ATM_PORT_NUMBER;
1854         ifx_mei_atm_showtime_check(&g_showtime, &port_cell, &g_xdata_addr);
1855         if ( g_showtime ) {
1856                 for ( i = 0; i < ATM_PORT_NUMBER; i++ )
1857                         if ( port_cell.tx_link_rate[i] != 0 )
1858                                 break;
1859                 for ( j = 0; j < ATM_PORT_NUMBER; j++ )
1860                         g_atm_priv_data.port[j].tx_max_cell_rate =
1861                                 port_cell.tx_link_rate[j] != 0 ? port_cell.tx_link_rate[j] : port_cell.tx_link_rate[i];
1862         }
1863
1864         qsb_global_set();
1865         validate_oam_htu_entry();
1866
1867         ifx_mei_atm_showtime_enter = atm_showtime_enter;
1868         ifx_mei_atm_showtime_exit  = atm_showtime_exit;
1869
1870         ifx_atm_version(ops, ver_str);
1871         printk(KERN_INFO "%s", ver_str);
1872         platform_set_drvdata(pdev, ops);
1873         printk("ifxmips_atm: ATM init succeed\n");
1874
1875         return 0;
1876
1877 PP32_START_FAIL:
1878         free_irq(PPE_MAILBOX_IGU1_INT, &g_atm_priv_data);
1879 REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL:
1880 ATM_DEV_REGISTER_FAIL:
1881         while ( port_num-- > 0 )
1882                 atm_dev_deregister(g_atm_priv_data.port[port_num].dev);
1883 INIT_PRIV_DATA_FAIL:
1884         clear_priv_data();
1885         printk("ifxmips_atm: ATM init failed\n");
1886         return ret;
1887 }
1888
1889 static int ltq_atm_remove(struct platform_device *pdev)
1890 {
1891         int port_num;
1892         struct ltq_atm_ops *ops = platform_get_drvdata(pdev);
1893
1894         ifx_mei_atm_showtime_enter = NULL;
1895         ifx_mei_atm_showtime_exit  = NULL;
1896
1897         invalidate_oam_htu_entry();
1898
1899         ops->stop(0);
1900
1901         free_irq(PPE_MAILBOX_IGU1_INT, &g_atm_priv_data);
1902
1903         for ( port_num = 0; port_num < ATM_PORT_NUMBER; port_num++ )
1904                 atm_dev_deregister(g_atm_priv_data.port[port_num].dev);
1905
1906         ops->shutdown();
1907
1908         clear_priv_data();
1909
1910         return 0;
1911 }
1912
1913 static struct platform_driver ltq_atm_driver = {
1914         .probe = ltq_atm_probe,
1915         .remove = ltq_atm_remove,
1916         .driver = {
1917                 .name = "atm",
1918                 .owner = THIS_MODULE,
1919                 .of_match_table = ltq_atm_match,
1920         },
1921 };
1922
1923 module_platform_driver(ltq_atm_driver);
1924
1925 MODULE_LICENSE("Dual BSD/GPL");