package/kernel/lantiq/ltq-adsl/patches/100-dsl_compat.patch

   1 Index: drv_dsl_cpe_api-3.24.4.4/src/include/drv_dsl_cpe_device_danube.h
   2 ===================================================================
   3 --- drv_dsl_cpe_api-3.24.4.4.orig/src/include/drv_dsl_cpe_device_danube.h       2009-05-12 20:02:16.000000000 +0200
   4 +++ drv_dsl_cpe_api-3.24.4.4/src/include/drv_dsl_cpe_device_danube.h    2012-11-29 19:47:21.060210322 +0100
   5 @@ -24,7 +24,7 @@
   6     #include "drv_dsl_cpe_simulator_danube.h"
   7  #else
   8  /* Include for the low level driver interface header file */
   9 -#include "asm/ifx/ifx_mei_bsp.h"
  10 +#include "ifxmips_mei_interface.h"
  11  #endif /* defined(DSL_CPE_SIMULATOR_DRIVER) && defined(WIN32)*/
  12
  13  #define DSL_MAX_LINE_NUMBER 1
  14 Index: drv_dsl_cpe_api-3.24.4.4/src/common/drv_dsl_cpe_os_linux.c
  15 ===================================================================
  16 --- drv_dsl_cpe_api-3.24.4.4.orig/src/common/drv_dsl_cpe_os_linux.c     2009-07-13 11:33:43.000000000 +0200
  17 +++ drv_dsl_cpe_api-3.24.4.4/src/common/drv_dsl_cpe_os_linux.c  2012-11-29 19:46:32.700209112 +0100
  18 @@ -11,6 +11,7 @@
  19  #ifdef __LINUX__
  20
  21  #define DSL_INTERN
  22 +#include <linux/device.h>
  23
  24  #include "drv_dsl_cpe_api.h"
  25  #include "drv_dsl_cpe_api_ioctl.h"
  26 @@ -34,9 +35,13 @@
  27  static DSL_ssize_t DSL_DRV_Write(DSL_DRV_file_t *pFile, const DSL_char_t * pBuf,
  28                                   DSL_DRV_size_t nSize, DSL_DRV_offset_t * pLoff);
  29
  30 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36))
  31  static DSL_int_t DSL_DRV_Ioctls(DSL_DRV_inode_t * pINode, DSL_DRV_file_t * pFile,
  32                           DSL_uint_t nCommand, unsigned long nArg);
  33 -
  34 +#else
  35 +static DSL_int_t DSL_DRV_Ioctls(DSL_DRV_file_t * pFile,
  36 +                         DSL_uint_t nCommand, unsigned long nArg);
  37 +#endif
  38  static int DSL_DRV_Open(DSL_DRV_inode_t * ino, DSL_DRV_file_t * fil);
  39
  40  static int DSL_DRV_Release(DSL_DRV_inode_t * ino, DSL_DRV_file_t * fil);
  41 @@ -72,7 +77,11 @@
  42     open:    DSL_DRV_Open,
  43     release: DSL_DRV_Release,
  44     write:   DSL_DRV_Write,
  45 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36))
  46     ioctl:   DSL_DRV_Ioctls,
  47 +#else
  48 +   unlocked_ioctl:   DSL_DRV_Ioctls,
  49 +#endif
  50     poll:    DSL_DRV_Poll
  51  };
  52  #else
  53 @@ -168,10 +177,17 @@
  54     \return  Success or failure.
  55     \ingroup Internal
  56  */
  57 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36))
  58  static DSL_int_t DSL_DRV_Ioctls(DSL_DRV_inode_t * pINode,
  59     DSL_DRV_file_t * pFile,
  60     DSL_uint_t nCommand,
  61     unsigned long nArg)
  62 +#else
  63 +static DSL_int_t DSL_DRV_Ioctls(
  64 +   DSL_DRV_file_t * pFile,
  65 +   DSL_uint_t nCommand,
  66 +   unsigned long nArg)
  67 +#endif
  68  {
  69     DSL_int_t nErr=0;
  70     DSL_boolean_t bIsInKernel;
  71 @@ -216,16 +232,7 @@
  72           }
  73        }
  74     }
  75 -
  76 -   if (pINode == DSL_NULL)
  77 -   {
  78 -      bIsInKernel = DSL_TRUE;
  79 -   }
  80 -   else
  81 -   {
  82 -      bIsInKernel = DSL_FALSE;
  83 -   }
  84 -
  85 +   bIsInKernel = DSL_FALSE;
  86     if ( (_IOC_TYPE(nCommand) == DSL_IOC_MAGIC_CPE_API) ||
  87          (_IOC_TYPE(nCommand) == DSL_IOC_MAGIC_CPE_API_G997) ||
  88          (_IOC_TYPE(nCommand) == DSL_IOC_MAGIC_CPE_API_PM) ||
  89 @@ -1058,6 +1065,7 @@
  90  /* Entry point of driver */
  91  int __init DSL_ModuleInit(void)
  92  {
  93 +   struct class *dsl_class;
  94     DSL_int_t i;
  95
  96     printk(DSL_DRV_CRLF DSL_DRV_CRLF "Infineon CPE API Driver version: %s" DSL_DRV_CRLF,
  97 @@ -1104,7 +1112,8 @@
  98     }
  99
 100     DSL_DRV_DevNodeInit();
 101 -
 102 +   dsl_class = class_create(THIS_MODULE, "dsl_cpe_api");
 103 +   device_create(dsl_class, NULL, MKDEV(DRV_DSL_CPE_API_DEV_MAJOR, 0), NULL, "dsl_cpe_api");
 104     return 0;
 105  }
 106
 107 Index: drv_dsl_cpe_api-3.24.4.4/src/include/drv_dsl_cpe_os_linux.h
 108 ===================================================================
 109 --- drv_dsl_cpe_api-3.24.4.4.orig/src/include/drv_dsl_cpe_os_linux.h    2009-07-03 17:04:51.000000000 +0200
 110 +++ drv_dsl_cpe_api-3.24.4.4/src/include/drv_dsl_cpe_os_linux.h 2012-11-29 19:47:23.092210377 +0100
 111 @@ -17,17 +17,17 @@
 112  #endif
 113
 114  #include <asm/ioctl.h>
 115 -#include <linux/autoconf.h>
 116 +#include <generated/autoconf.h>
 117  #include <linux/module.h>
 118  #include <linux/kernel.h>
 119  #include <linux/init.h>
 120  #include <linux/ctype.h>
 121  #include <linux/version.h>
 122  #include <linux/spinlock.h>
 123 -
 124 +#include <linux/sched.h>
 125
 126  #if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,17))
 127 -   #include <linux/utsrelease.h>
 128 +   #include <generated/utsrelease.h>
 129  #endif
 130
 131  #include <linux/types.h>
 132 Index: drv_dsl_cpe_api-3.24.4.4/src/ifxmips_mei_interface.h
 133 ===================================================================
 134 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
 135 +++ drv_dsl_cpe_api-3.24.4.4/src/ifxmips_mei_interface.h        2012-11-29 19:47:54.972211177 +0100
 136 @@ -0,0 +1,702 @@
 137 +/******************************************************************************
 138 +
 139 +                               Copyright (c) 2009
 140 +                            Infineon Technologies AG
 141 +                     Am Campeon 1-12; 81726 Munich, Germany
 142 +
 143 +  For licensing information, see the file 'LICENSE' in the root folder of
 144 +  this software module.
 145 +
 146 +******************************************************************************/
 147 +
 148 +#ifndef IFXMIPS_MEI_H
 149 +#define IFXMIPS_MEI_H
 150 +
 151 +//#define CONFIG_AMAZON_SE 1
 152 +//#define CONFIG_DANUBE 1
 153 +//#define CONFIG_AR9 1
 154 +
 155 +#if !defined(CONFIG_DANUBE) && !defined(CONFIG_AMAZON_SE) && !defined(CONFIG_AR9) && !defined(CONFIG_VR9)
 156 +#error Platform undefined!!!
 157 +#endif
 158 +
 159 +#ifdef IFX_MEI_BSP
 160 +/** This is the character datatype. */
 161 +typedef char            DSL_char_t;
 162 +/** This is the unsigned 8-bit datatype. */
 163 +typedef unsigned char   DSL_uint8_t;
 164 +/** This is the signed 8-bit datatype. */
 165 +typedef signed char     DSL_int8_t;
 166 +/** This is the unsigned 16-bit datatype. */
 167 +typedef unsigned short  DSL_uint16_t;
 168 +/** This is the signed 16-bit datatype. */
 169 +typedef signed short    DSL_int16_t;
 170 +/** This is the unsigned 32-bit datatype. */
 171 +typedef unsigned long   DSL_uint32_t;
 172 +/** This is the signed 32-bit datatype. */
 173 +typedef signed long     DSL_int32_t;
 174 +/** This is the float datatype. */
 175 +typedef float           DSL_float_t;
 176 +/** This is the void datatype. */
 177 +typedef void            DSL_void_t;
 178 +/** integer type, width is depending on processor arch */
 179 +typedef int             DSL_int_t;
 180 +/** unsigned integer type, width is depending on processor arch */
 181 +typedef unsigned int    DSL_uint_t;
 182 +typedef struct file DSL_DRV_file_t;
 183 +typedef struct inode DSL_DRV_inode_t;
 184 +
 185 +/**
 186 + *    Defines all possible CMV groups
 187 + *    */
 188 +typedef enum {
 189 +   DSL_CMV_GROUP_CNTL = 1,
 190 +   DSL_CMV_GROUP_STAT = 2,
 191 +   DSL_CMV_GROUP_INFO = 3,
 192 +   DSL_CMV_GROUP_TEST = 4,
 193 +   DSL_CMV_GROUP_OPTN = 5,
 194 +   DSL_CMV_GROUP_RATE = 6,
 195 +   DSL_CMV_GROUP_PLAM = 7,
 196 +   DSL_CMV_GROUP_CNFG = 8
 197 +} DSL_CmvGroup_t;
 198 +/**
 199 + *    Defines all opcode types
 200 + *    */
 201 +typedef enum {
 202 +   H2D_CMV_READ = 0x00,
 203 +   H2D_CMV_WRITE = 0x04,
 204 +   H2D_CMV_INDICATE_REPLY = 0x10,
 205 +   H2D_ERROR_OPCODE_UNKNOWN =0x20,
 206 +   H2D_ERROR_CMV_UNKNOWN =0x30,
 207 +
 208 +   D2H_CMV_READ_REPLY =0x01,
 209 +   D2H_CMV_WRITE_REPLY = 0x05,
 210 +   D2H_CMV_INDICATE = 0x11,
 211 +   D2H_ERROR_OPCODE_UNKNOWN = 0x21,
 212 +   D2H_ERROR_CMV_UNKNOWN = 0x31,
 213 +   D2H_ERROR_CMV_READ_NOT_AVAILABLE = 0x41,
 214 +   D2H_ERROR_CMV_WRITE_ONLY = 0x51,
 215 +   D2H_ERROR_CMV_READ_ONLY = 0x61,
 216 +
 217 +   H2D_DEBUG_READ_DM = 0x02,
 218 +   H2D_DEBUG_READ_PM = 0x06,
 219 +   H2D_DEBUG_WRITE_DM = 0x0a,
 220 +   H2D_DEBUG_WRITE_PM = 0x0e,
 221 +
 222 +   D2H_DEBUG_READ_DM_REPLY = 0x03,
 223 +   D2H_DEBUG_READ_FM_REPLY = 0x07,
 224 +   D2H_DEBUG_WRITE_DM_REPLY = 0x0b,
 225 +   D2H_DEBUG_WRITE_FM_REPLY = 0x0f,
 226 +   D2H_ERROR_ADDR_UNKNOWN = 0x33,
 227 +
 228 +   D2H_AUTONOMOUS_MODEM_READY_MSG = 0xf1
 229 +} DSL_CmvOpcode_t;
 230 +
 231 +/* mutex macros */
 232 +#define MEI_MUTEX_INIT(id,flag) \
 233 +        sema_init(&id,flag)
 234 +#define MEI_MUTEX_LOCK(id) \
 235 +        down_interruptible(&id)
 236 +#define MEI_MUTEX_UNLOCK(id) \
 237 +        up(&id)
 238 +#define MEI_WAIT(ms) \
 239 +        {\
 240 +                set_current_state(TASK_INTERRUPTIBLE);\
 241 +                schedule_timeout(ms);\
 242 +        }
 243 +#define MEI_INIT_WAKELIST(name,queue) \
 244 +        init_waitqueue_head(&queue)
 245 +
 246 +/* wait for an event, timeout is measured in ms */
 247 +#define MEI_WAIT_EVENT_TIMEOUT(ev,timeout)\
 248 +        interruptible_sleep_on_timeout(&ev,timeout * HZ / 1000)
 249 +#define MEI_WAKEUP_EVENT(ev)\
 250 +        wake_up_interruptible(&ev)
 251 +#endif /* IFX_MEI_BSP */
 252 +
 253 +/***   Register address offsets, relative to MEI_SPACE_ADDRESS ***/
 254 +#define ME_DX_DATA                             (0x0000)
 255 +#define        ME_VERSION                              (0x0004)
 256 +#define        ME_ARC_GP_STAT                          (0x0008)
 257 +#define ME_DX_STAT                             (0x000C)
 258 +#define        ME_DX_AD                                (0x0010)
 259 +#define ME_DX_MWS                              (0x0014)
 260 +#define        ME_ME2ARC_INT                           (0x0018)
 261 +#define        ME_ARC2ME_STAT                          (0x001C)
 262 +#define        ME_ARC2ME_MASK                          (0x0020)
 263 +#define        ME_DBG_WR_AD                            (0x0024)
 264 +#define ME_DBG_RD_AD                           (0x0028)
 265 +#define        ME_DBG_DATA                             (0x002C)
 266 +#define        ME_DBG_DECODE                           (0x0030)
 267 +#define ME_CONFIG                              (0x0034)
 268 +#define        ME_RST_CTRL                             (0x0038)
 269 +#define        ME_DBG_MASTER                           (0x003C)
 270 +#define        ME_CLK_CTRL                             (0x0040)
 271 +#define        ME_BIST_CTRL                            (0x0044)
 272 +#define        ME_BIST_STAT                            (0x0048)
 273 +#define ME_XDATA_BASE_SH                       (0x004c)
 274 +#define ME_XDATA_BASE                          (0x0050)
 275 +#define ME_XMEM_BAR_BASE                       (0x0054)
 276 +#define ME_XMEM_BAR0                           (0x0054)
 277 +#define ME_XMEM_BAR1                           (0x0058)
 278 +#define ME_XMEM_BAR2                           (0x005C)
 279 +#define ME_XMEM_BAR3                           (0x0060)
 280 +#define ME_XMEM_BAR4                           (0x0064)
 281 +#define ME_XMEM_BAR5                           (0x0068)
 282 +#define ME_XMEM_BAR6                           (0x006C)
 283 +#define ME_XMEM_BAR7                           (0x0070)
 284 +#define ME_XMEM_BAR8                           (0x0074)
 285 +#define ME_XMEM_BAR9                           (0x0078)
 286 +#define ME_XMEM_BAR10                          (0x007C)
 287 +#define ME_XMEM_BAR11                          (0x0080)
 288 +#define ME_XMEM_BAR12                          (0x0084)
 289 +#define ME_XMEM_BAR13                          (0x0088)
 290 +#define ME_XMEM_BAR14                          (0x008C)
 291 +#define ME_XMEM_BAR15                          (0x0090)
 292 +#define ME_XMEM_BAR16                          (0x0094)
 293 +
 294 +#define WHILE_DELAY            20000
 295 +/*
 296 +**     Define where in ME Processor's memory map the Stratify chip lives
 297 +*/
 298 +
 299 +#define MAXSWAPSIZE            (8 * 1024)      //8k *(32bits)
 300 +
 301 +//      Mailboxes
 302 +#define MSG_LENGTH             16      // x16 bits
 303 +#define YES_REPLY                      1
 304 +#define NO_REPLY               0
 305 +
 306 +#define CMV_TIMEOUT            1000    //jiffies
 307 +
 308 +//  Block size per BAR
 309 +#define SDRAM_SEGMENT_SIZE     (64*1024)
 310 +// Number of Bar registers
 311 +#define MAX_BAR_REGISTERS      (17)
 312 +
 313 +#define XDATA_REGISTER         (15)
 314 +
 315 +// ARC register addresss
 316 +#define ARC_STATUS             0x0
 317 +#define ARC_LP_START           0x2
 318 +#define ARC_LP_END             0x3
 319 +#define ARC_DEBUG              0x5
 320 +#define ARC_INT_MASK           0x10A
 321 +
 322 +#define IRAM0_BASE             (0x00000)
 323 +#define IRAM1_BASE             (0x04000)
 324 +#if defined(CONFIG_DANUBE)
 325 +#define BRAM_BASE              (0x0A000)
 326 +#elif defined(CONFIG_AMAZON_SE) || defined(CONFIG_AR9) || defined(CONFIG_VR9)
 327 +#define BRAM_BASE               (0x08000)
 328 +#endif
 329 +#define XRAM_BASE              (0x18000)
 330 +#define YRAM_BASE              (0x1A000)
 331 +#define EXT_MEM_BASE           (0x80000)
 332 +#define ARC_GPIO_CTRL          (0xC030)
 333 +#define ARC_GPIO_DATA          (0xC034)
 334 +
 335 +#define IRAM0_SIZE             (16*1024)
 336 +#define IRAM1_SIZE             (16*1024)
 337 +#define BRAM_SIZE              (12*1024)
 338 +#define XRAM_SIZE              (8*1024)
 339 +#define YRAM_SIZE              (8*1024)
 340 +#define EXT_MEM_SIZE           (1536*1024)
 341 +
 342 +#define ADSL_BASE              (0x20000)
 343 +#define CRI_BASE               (ADSL_BASE + 0x11F00)
 344 +#define CRI_CCR0               (CRI_BASE + 0x00)
 345 +#define CRI_RST                        (CRI_BASE + 0x04*4)
 346 +#define ADSL_DILV_BASE                 (ADSL_BASE+0x20000)
 347 +
 348 +//
 349 +#define IRAM0_ADDR_BIT_MASK    0xFFF
 350 +#define IRAM1_ADDR_BIT_MASK    0xFFF
 351 +#define BRAM_ADDR_BIT_MASK     0xFFF
 352 +#define RX_DILV_ADDR_BIT_MASK  0x1FFF
 353 +
 354 +/***  Bit definitions ***/
 355 +#define ARC_AUX_HALT           (1 << 25)
 356 +#define ARC_DEBUG_HALT         (1 << 1)
 357 +#define FALSE                  0
 358 +#define TRUE                   1
 359 +#define BIT0                   (1<<0)
 360 +#define BIT1                   (1<<1)
 361 +#define BIT2                   (1<<2)
 362 +#define BIT3                   (1<<3)
 363 +#define BIT4                   (1<<4)
 364 +#define BIT5                   (1<<5)
 365 +#define BIT6                   (1<<6)
 366 +#define BIT7                   (1<<7)
 367 +#define BIT8                   (1<<8)
 368 +#define BIT9                   (1<<9)
 369 +#define BIT10                  (1<<10)
 370 +#define BIT11                  (1<<11)
 371 +#define BIT12                  (1<<12)
 372 +#define BIT13                  (1<<13)
 373 +#define BIT14                  (1<<14)
 374 +#define BIT15                  (1<<15)
 375 +#define BIT16                  (1<<16)
 376 +#define BIT17                  (1<<17)
 377 +#define BIT18                  (1<<18)
 378 +#define BIT19                  (1<<19)
 379 +#define BIT20                  (1<<20)
 380 +#define BIT21                  (1<<21)
 381 +#define BIT22                  (1<<22)
 382 +#define BIT23                  (1<<23)
 383 +#define BIT24                  (1<<24)
 384 +#define BIT25                  (1<<25)
 385 +#define BIT26                  (1<<26)
 386 +#define BIT27                  (1<<27)
 387 +#define BIT28                  (1<<28)
 388 +#define BIT29                  (1<<29)
 389 +#define BIT30                  (1<<30)
 390 +#define BIT31                  (1<<31)
 391 +
 392 +// CRI_CCR0 Register definitions
 393 +#define CLK_2M_MODE_ENABLE     BIT6
 394 +#define        ACL_CLK_MODE_ENABLE     BIT4
 395 +#define FDF_CLK_MODE_ENABLE    BIT2
 396 +#define STM_CLK_MODE_ENABLE    BIT0
 397 +
 398 +// CRI_RST Register definitions
 399 +#define FDF_SRST               BIT3
 400 +#define MTE_SRST               BIT2
 401 +#define FCI_SRST               BIT1
 402 +#define AAI_SRST               BIT0
 403 +
 404 +//      MEI_TO_ARC_INTERRUPT Register definitions
 405 +#define        MEI_TO_ARC_INT1         BIT3
 406 +#define        MEI_TO_ARC_INT0         BIT2
 407 +#define MEI_TO_ARC_CS_DONE     BIT1    //need to check
 408 +#define        MEI_TO_ARC_MSGAV        BIT0
 409 +
 410 +//      ARC_TO_MEI_INTERRUPT Register definitions
 411 +#define        ARC_TO_MEI_INT1         BIT8
 412 +#define        ARC_TO_MEI_INT0         BIT7
 413 +#define        ARC_TO_MEI_CS_REQ       BIT6
 414 +#define        ARC_TO_MEI_DBG_DONE     BIT5
 415 +#define        ARC_TO_MEI_MSGACK       BIT4
 416 +#define        ARC_TO_MEI_NO_ACCESS    BIT3
 417 +#define        ARC_TO_MEI_CHECK_AAITX  BIT2
 418 +#define        ARC_TO_MEI_CHECK_AAIRX  BIT1
 419 +#define        ARC_TO_MEI_MSGAV        BIT0
 420 +
 421 +//      ARC_TO_MEI_INTERRUPT_MASK Register definitions
 422 +#define        GP_INT1_EN              BIT8
 423 +#define        GP_INT0_EN              BIT7
 424 +#define        CS_REQ_EN               BIT6
 425 +#define        DBG_DONE_EN             BIT5
 426 +#define        MSGACK_EN               BIT4
 427 +#define        NO_ACC_EN               BIT3
 428 +#define        AAITX_EN                BIT2
 429 +#define        AAIRX_EN                BIT1
 430 +#define        MSGAV_EN                BIT0
 431 +
 432 +#define        MEI_SOFT_RESET          BIT0
 433 +
 434 +#define        HOST_MSTR               BIT0
 435 +
 436 +#define JTAG_MASTER_MODE       0x0
 437 +#define MEI_MASTER_MODE                HOST_MSTR
 438 +
 439 +//      MEI_DEBUG_DECODE Register definitions
 440 +#define MEI_DEBUG_DEC_MASK     (0x3)
 441 +#define MEI_DEBUG_DEC_AUX_MASK (0x0)
 442 +#define ME_DBG_DECODE_DMP1_MASK        (0x1)
 443 +#define MEI_DEBUG_DEC_DMP2_MASK        (0x2)
 444 +#define MEI_DEBUG_DEC_CORE_MASK        (0x3)
 445 +
 446 +#define AUX_STATUS             (0x0)
 447 +#define AUX_ARC_GPIO_CTRL      (0x10C)
 448 +#define AUX_ARC_GPIO_DATA      (0x10D)
 449 +//      ARC_TO_MEI_MAILBOX[11] is a special location used to indicate
 450 +//      page swap requests.
 451 +#if defined(CONFIG_DANUBE)
 452 +#define OMBOX_BASE             0xDF80
 453 +#define        ARC_TO_MEI_MAILBOX      0xDFA0
 454 +#define IMBOX_BASE             0xDFC0
 455 +#define MEI_TO_ARC_MAILBOX     0xDFD0
 456 +#elif defined(CONFIG_AMAZON_SE) || defined(CONFIG_AR9) || defined(CONFIG_VR9)
 457 +#define OMBOX_BASE              0xAF80
 458 +#define ARC_TO_MEI_MAILBOX      0xAFA0
 459 +#define IMBOX_BASE              0xAFC0
 460 +#define MEI_TO_ARC_MAILBOX      0xAFD0
 461 +#endif
 462 +
 463 +#define MEI_TO_ARC_MAILBOXR    (MEI_TO_ARC_MAILBOX + 0x2C)
 464 +#define ARC_MEI_MAILBOXR       (ARC_TO_MEI_MAILBOX + 0x2C)
 465 +#define OMBOX1                 (OMBOX_BASE+0x4)
 466 +
 467 +// Codeswap request messages are indicated by setting BIT31
 468 +#define OMB_CODESWAP_MESSAGE_MSG_TYPE_MASK     (0x80000000)
 469 +
 470 +// Clear Eoc messages received are indicated by setting BIT17
 471 +#define OMB_CLEAREOC_INTERRUPT_CODE            (0x00020000)
 472 +#define OMB_REBOOT_INTERRUPT_CODE               (1 << 18)
 473 +
 474 +/*
 475 +**     Swap page header
 476 +*/
 477 +//      Page must be loaded at boot time if size field has BIT31 set
 478 +#define BOOT_FLAG              (BIT31)
 479 +#define BOOT_FLAG_MASK         ~BOOT_FLAG
 480 +
 481 +#define FREE_RELOAD            1
 482 +#define FREE_SHOWTIME          2
 483 +#define FREE_ALL               3
 484 +
 485 +// marcos
 486 +#define        IFX_MEI_WRITE_REGISTER_L(data,addr)     *((volatile u32*)(addr)) = (u32)(data)
 487 +#define IFX_MEI_READ_REGISTER_L(addr)  (*((volatile u32*)(addr)))
 488 +#define SET_BIT(reg, mask)                     reg |= (mask)
 489 +#define CLEAR_BIT(reg, mask)                   reg &= (~mask)
 490 +#define CLEAR_BITS(reg, mask)                  CLEAR_BIT(reg, mask)
 491 +//#define SET_BITS(reg, mask)                  SET_BIT(reg, mask)
 492 +#define SET_BITFIELD(reg, mask, off, val)      {reg &= (~mask); reg |= (val << off);}
 493 +
 494 +#define ALIGN_SIZE                             ( 1L<<10 )      //1K size align
 495 +#define MEM_ALIGN(addr)                                (((addr) + ALIGN_SIZE - 1) & ~ (ALIGN_SIZE -1) )
 496 +
 497 +// swap marco
 498 +#define MEI_HALF_WORD_SWAP(data)               {data = ((data & 0xffff)<<16) + ((data & 0xffff0000)>>16);}
 499 +#define MEI_BYTE_SWAP(data)                    {data = ((data & 0xff)<<24) + ((data & 0xff00)<<8)+ ((data & 0xff0000)>>8)+ ((data & 0xff000000)>>24);}
 500 +
 501 +
 502 +#ifdef CONFIG_PROC_FS
 503 +typedef struct reg_entry
 504 +{
 505 +   int *flag;
 506 +   char name[30];               /* big enough to hold names */
 507 +   char description[100];       /* big enough to hold description */
 508 +   unsigned short low_ino;
 509 +} reg_entry_t;
 510 +#endif
 511 +//      Swap page header describes size in 32-bit words, load location, and image offset
 512 +//      for program and/or data segments
 513 +typedef struct _arc_swp_page_hdr {
 514 +       u32 p_offset;           //Offset bytes of progseg from beginning of image
 515 +       u32 p_dest;             //Destination addr of progseg on processor
 516 +       u32 p_size;             //Size in 32-bitwords of program segment
 517 +       u32 d_offset;           //Offset bytes of dataseg from beginning of image
 518 +       u32 d_dest;             //Destination addr of dataseg on processor
 519 +       u32 d_size;             //Size in 32-bitwords of data segment
 520 +} ARC_SWP_PAGE_HDR;
 521 +
 522 +/*
 523 +**     Swap image header
 524 +*/
 525 +#define GET_PROG       0       //      Flag used for program mem segment
 526 +#define GET_DATA       1       //      Flag used for data mem segment
 527 +
 528 +//      Image header contains size of image, checksum for image, and count of
 529 +//      page headers. Following that are 'count' page headers followed by
 530 +//      the code and/or data segments to be loaded
 531 +typedef struct _arc_img_hdr {
 532 +       u32 size;               //      Size of binary image in bytes
 533 +       u32 checksum;           //      Checksum for image
 534 +       u32 count;              //      Count of swp pages in image
 535 +       ARC_SWP_PAGE_HDR page[1];       //      Should be "count" pages - '1' to make compiler happy
 536 +} ARC_IMG_HDR;
 537 +
 538 +typedef struct smmu_mem_info {
 539 +       int type;
 540 +       int boot;
 541 +       unsigned long nCopy;
 542 +       unsigned long size;
 543 +       unsigned char *address;
 544 +       unsigned char *org_address;
 545 +} smmu_mem_info_t;
 546 +
 547 +#ifdef __KERNEL__
 548 +typedef struct ifx_mei_device_private {
 549 +       int modem_ready;
 550 +       int arcmsgav;
 551 +       int cmv_reply;
 552 +       int cmv_waiting;
 553 +       // Mei to ARC CMV count, reply count, ARC Indicator count
 554 +       int modem_ready_cnt;
 555 +       int cmv_count;
 556 +       int reply_count;
 557 +       unsigned long image_size;
 558 +       int nBar;
 559 +       u16 Recent_indicator[MSG_LENGTH];
 560 +
 561 +       u16 CMV_RxMsg[MSG_LENGTH] __attribute__ ((aligned (4)));
 562 +
 563 +       smmu_mem_info_t adsl_mem_info[MAX_BAR_REGISTERS];
 564 +       ARC_IMG_HDR *img_hdr;
 565 +       //  to wait for arc cmv reply, sleep on wait_queue_arcmsgav;
 566 +       wait_queue_head_t wait_queue_arcmsgav;
 567 +       wait_queue_head_t wait_queue_modemready;
 568 +       struct semaphore mei_cmv_sema;
 569 +} ifx_mei_device_private_t;
 570 +#endif
 571 +typedef struct winhost_message {
 572 +       union {
 573 +               u16 RxMessage[MSG_LENGTH] __attribute__ ((aligned (4)));
 574 +               u16 TxMessage[MSG_LENGTH] __attribute__ ((aligned (4)));
 575 +       } msg;
 576 +} DSL_DEV_WinHost_Message_t;
 577 +/********************************************************************************************************
 578 + * DSL CPE API Driver Stack Interface Definitions
 579 + * *****************************************************************************************************/
 580 +/** IOCTL codes for bsp driver */
 581 +#define DSL_IOC_MEI_BSP_MAGIC          's'
 582 +
 583 +#define DSL_FIO_BSP_DSL_START          _IO  (DSL_IOC_MEI_BSP_MAGIC, 0)
 584 +#define DSL_FIO_BSP_RUN                        _IO  (DSL_IOC_MEI_BSP_MAGIC, 1)
 585 +#define DSL_FIO_BSP_FREE_RESOURCE      _IO  (DSL_IOC_MEI_BSP_MAGIC, 2)
 586 +#define DSL_FIO_BSP_RESET              _IO  (DSL_IOC_MEI_BSP_MAGIC, 3)
 587 +#define DSL_FIO_BSP_REBOOT             _IO  (DSL_IOC_MEI_BSP_MAGIC, 4)
 588 +#define DSL_FIO_BSP_HALT               _IO  (DSL_IOC_MEI_BSP_MAGIC, 5)
 589 +#define DSL_FIO_BSP_BOOTDOWNLOAD       _IO  (DSL_IOC_MEI_BSP_MAGIC, 6)
 590 +#define DSL_FIO_BSP_JTAG_ENABLE                _IO  (DSL_IOC_MEI_BSP_MAGIC, 7)
 591 +#define DSL_FIO_FREE_RESOURCE          _IO  (DSL_IOC_MEI_BSP_MAGIC, 8)
 592 +#define DSL_FIO_ARC_MUX_TEST           _IO  (DSL_IOC_MEI_BSP_MAGIC, 9)
 593 +#define DSL_FIO_BSP_REMOTE             _IOW (DSL_IOC_MEI_BSP_MAGIC, 10, u32)
 594 +#define DSL_FIO_BSP_GET_BASE_ADDRESS   _IOR (DSL_IOC_MEI_BSP_MAGIC, 11, u32)
 595 +#define DSL_FIO_BSP_IS_MODEM_READY     _IOR (DSL_IOC_MEI_BSP_MAGIC, 12, u32)
 596 +#define DSL_FIO_BSP_GET_VERSION                _IOR (DSL_IOC_MEI_BSP_MAGIC, 13, DSL_DEV_Version_t)
 597 +#define DSL_FIO_BSP_CMV_WINHOST                _IOWR(DSL_IOC_MEI_BSP_MAGIC, 14, DSL_DEV_WinHost_Message_t)
 598 +#define DSL_FIO_BSP_CMV_READ           _IOWR(DSL_IOC_MEI_BSP_MAGIC, 15, DSL_DEV_MeiReg_t)
 599 +#define DSL_FIO_BSP_CMV_WRITE          _IOW (DSL_IOC_MEI_BSP_MAGIC, 16, DSL_DEV_MeiReg_t)
 600 +#define DSL_FIO_BSP_DEBUG_READ         _IOWR(DSL_IOC_MEI_BSP_MAGIC, 17, DSL_DEV_MeiDebug_t)
 601 +#define DSL_FIO_BSP_DEBUG_WRITE                _IOWR(DSL_IOC_MEI_BSP_MAGIC, 18, DSL_DEV_MeiDebug_t)
 602 +#define DSL_FIO_BSP_GET_CHIP_INFO      _IOR (DSL_IOC_MEI_BSP_MAGIC, 19, DSL_DEV_HwVersion_t)
 603 +
 604 +#define DSL_DEV_MEIDEBUG_BUFFER_SIZES  512
 605 +
 606 +typedef struct DSL_DEV_MeiDebug
 607 +{
 608 +       DSL_uint32_t iAddress;
 609 +       DSL_uint32_t iCount;
 610 +       DSL_uint32_t buffer[DSL_DEV_MEIDEBUG_BUFFER_SIZES];
 611 +} DSL_DEV_MeiDebug_t;                  /* meidebug */
 612 +
 613 +/**
 614 + *    Structure is used for debug access only.
 615 + *       Refer to configure option INCLUDE_ADSL_WINHOST_DEBUG */
 616 +typedef struct struct_meireg
 617 +{
 618 +       /*
 619 +       *       Specifies that address for debug access */
 620 +       unsigned long iAddress;
 621 +       /*
 622 +       *       Specifies the pointer to the data that has to be written or returns a
 623 +       *             pointer to the data that has been read out*/
 624 +       unsigned long iData;
 625 +} DSL_DEV_MeiReg_t;                                    /* meireg */
 626 +
 627 +typedef struct DSL_DEV_Device
 628 +{
 629 +       DSL_int_t nInUse;                /* modem state, update by bsp driver, */
 630 +       DSL_void_t *pPriv;
 631 +       DSL_uint32_t base_address;       /* mei base address */
 632 +       DSL_int_t nIrq[2];                  /* irq number */
 633 +#define IFX_DFEIR              0
 634 +#define IFX_DYING_GASP 1
 635 +       DSL_DEV_MeiDebug_t lop_debugwr;  /* dying gasp */
 636 +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0))
 637 +       struct module *owner;
 638 +#endif
 639 +} DSL_DEV_Device_t;                    /* ifx_adsl_device_t */
 640 +
 641 +#define DSL_DEV_PRIVATE(dev)  ((ifx_mei_device_private_t*)(dev->pPriv))
 642 +
 643 +typedef struct DSL_DEV_Version         /* ifx_adsl_bsp_version */
 644 +{
 645 +       unsigned long major;
 646 +       unsigned long minor;
 647 +       unsigned long revision;
 648 +} DSL_DEV_Version_t;                   /* ifx_adsl_bsp_version_t */
 649 +
 650 +typedef struct DSL_DEV_ChipInfo
 651 +{
 652 +       unsigned long major;
 653 +       unsigned long minor;
 654 +} DSL_DEV_HwVersion_t;
 655 +
 656 +typedef struct
 657 +{
 658 +       DSL_uint8_t dummy;
 659 +} DSL_DEV_DeviceConfig_t;
 660 +
 661 +/** error code definitions */
 662 +typedef enum DSL_DEV_MeiError
 663 +{
 664 +       DSL_DEV_MEI_ERR_SUCCESS = 0,
 665 +       DSL_DEV_MEI_ERR_FAILURE = -1,
 666 +       DSL_DEV_MEI_ERR_MAILBOX_FULL = -2,
 667 +       DSL_DEV_MEI_ERR_MAILBOX_EMPTY = -3,
 668 +       DSL_DEV_MEI_ERR_MAILBOX_TIMEOUT = -4
 669 +} DSL_DEV_MeiError_t;                  /* MEI_ERROR */
 670 +
 671 +typedef enum {
 672 +       DSL_BSP_MEMORY_READ=0,
 673 +       DSL_BSP_MEMORY_WRITE,
 674 +} DSL_BSP_MemoryAccessType_t;          /* ifx_adsl_memory_access_type_t */
 675 +
 676 +typedef enum
 677 +{
 678 +       DSL_LED_LINK_ID=0,
 679 +       DSL_LED_DATA_ID
 680 +} DSL_DEV_LedId_t;                     /* ifx_adsl_led_id_t */
 681 +
 682 +typedef enum
 683 +{
 684 +       DSL_LED_LINK_TYPE=0,
 685 +       DSL_LED_DATA_TYPE
 686 +} DSL_DEV_LedType_t;                   /* ifx_adsl_led_type_t */
 687 +
 688 +typedef enum
 689 +{
 690 +       DSL_LED_HD_CPU=0,
 691 +       DSL_LED_HD_FW
 692 +} DSL_DEV_LedHandler_t;                        /* ifx_adsl_led_handler_t */
 693 +
 694 +typedef enum {
 695 +       DSL_LED_ON=0,
 696 +       DSL_LED_OFF,
 697 +       DSL_LED_FLASH,
 698 +} DSL_DEV_LedMode_t;                   /* ifx_adsl_led_mode_t */
 699 +
 700 +typedef enum {
 701 +       DSL_CPU_HALT=0,
 702 +       DSL_CPU_RUN,
 703 +       DSL_CPU_RESET,
 704 +} DSL_DEV_CpuMode_t;                   /* ifx_adsl_cpu_mode_t */
 705 +
 706 +#if 0
 707 +typedef enum {
 708 +       DSL_BSP_EVENT_DYING_GASP = 0,
 709 +       DSL_BSP_EVENT_CEOC_IRQ,
 710 +} DSL_BSP_Event_id_t;                  /* ifx_adsl_event_id_t */
 711 +
 712 +typedef union DSL_BSP_CB_Param
 713 +{
 714 +       DSL_uint32_t nIrqMessage;
 715 +} DSL_BSP_CB_Param_t;                  /* ifx_adsl_cbparam_t */
 716 +
 717 +typedef struct DSL_BSP_CB_Event
 718 +{
 719 +       DSL_BSP_Event_id_t nID;
 720 +       DSL_DEV_Device_t *pDev;
 721 +       DSL_BSP_CB_Param_t *pParam;
 722 +} DSL_BSP_CB_Event_t;                  /* ifx_adsl_cb_event_t */
 723 +#endif
 724 +
 725 +/* external functions (from the BSP Driver) */
 726 +extern DSL_DEV_Device_t* DSL_BSP_DriverHandleGet(int, int);
 727 +extern DSL_int_t DSL_BSP_DriverHandleDelete(DSL_DEV_Device_t *);
 728 +extern DSL_DEV_MeiError_t DSL_BSP_FWDownload(DSL_DEV_Device_t *, const DSL_char_t *, DSL_uint32_t, DSL_int32_t *, DSL_int32_t *);
 729 +extern int DSL_BSP_KernelIoctls(DSL_DEV_Device_t *, unsigned int, unsigned long);
 730 +extern DSL_DEV_MeiError_t DSL_BSP_SendCMV(DSL_DEV_Device_t *, DSL_uint16_t *, DSL_int_t, DSL_uint16_t *);
 731 +extern DSL_DEV_MeiError_t DSL_BSP_AdslLedInit(DSL_DEV_Device_t *, DSL_DEV_LedId_t, DSL_DEV_LedType_t, DSL_DEV_LedHandler_t);
 732 +extern DSL_DEV_MeiError_t DSL_BSP_Showtime(DSL_DEV_Device_t *, DSL_uint32_t, DSL_uint32_t);
 733 +extern int DSL_BSP_ATMLedCBRegister( int (*ifx_adsl_ledcallback)(void));
 734 +extern DSL_DEV_MeiError_t DSL_BSP_MemoryDebugAccess(DSL_DEV_Device_t *, DSL_BSP_MemoryAccessType_t, DSL_uint32_t, DSL_uint32_t *, DSL_uint32_t);
 735 +extern volatile DSL_DEV_Device_t *adsl_dev;
 736 +
 737 +/**
 738 + *    Dummy structure by now to show mechanism of extended data that will be
 739 + *       provided within event callback itself.
 740 + *       */
 741 +typedef struct
 742 +{
 743 +       /**
 744 +       *    Dummy value */
 745 +       DSL_uint32_t nDummy1;
 746 +} DSL_BSP_CB_Event1DataDummy_t;
 747 +
 748 +/**
 749 + *    Dummy structure by now to show mechanism of extended data that will be
 750 + *       provided within event callback itself.
 751 + *       */
 752 +typedef struct
 753 +{
 754 +       /**
 755 +       *    Dummy value */
 756 +       DSL_uint32_t nDummy2;
 757 +} DSL_BSP_CB_Event2DataDummy_t;
 758 +
 759 +/**
 760 + *    encapsulate all data structures that are necessary for status event
 761 + *       callbacks.
 762 + *       */
 763 +typedef union
 764 +{
 765 +       DSL_BSP_CB_Event1DataDummy_t dataEvent1;
 766 +       DSL_BSP_CB_Event2DataDummy_t dataEvent2;
 767 +} DSL_BSP_CB_DATA_Union_t;
 768 +
 769 +
 770 +typedef enum
 771 +{
 772 +       /**
 773 +        *    Informs the upper layer driver (DSL CPE API) about a reboot request from the
 774 +        *       firmware.
 775 +        *          \note This event does NOT include any additional data.
 776 +        *                   More detailed information upon reboot reason has to be requested from
 777 +        *                            upper layer software via CMV (INFO 109) if necessary. */
 778 +       DSL_BSP_CB_FIRST = 0,
 779 +        DSL_BSP_CB_DYING_GASP,
 780 +       DSL_BSP_CB_CEOC_IRQ,
 781 +       DSL_BSP_CB_FIRMWARE_REBOOT,
 782 +       /**
 783 +        *    Delimiter only */
 784 +       DSL_BSP_CB_LAST
 785 +} DSL_BSP_CB_Type_t;
 786 +
 787 +/**
 788 + *    Specifies the common event type that has to be used for registering and
 789 + *       signalling of interrupts/autonomous status events from MEI BSP Driver.
 790 + *
 791 + *    \param pDev
 792 + *    Context pointer from MEI BSP Driver.
 793 + *
 794 + *    \param IFX_ADSL_BSP_CallbackType_t
 795 + *    Specifies the event callback type (reason of callback). Regrading to the
 796 + *    setting of this value the data which is included in the following union
 797 + *    might have different meanings.
 798 + *    Please refer to the description of the union to get information about the
 799 + *    meaning of the included data.
 800 + *
 801 + *    \param pData
 802 + *    Data according to \ref DSL_BSP_CB_DATA_Union_t.
 803 + *    If this pointer is NULL there is no additional data available.
 804 + *
 805 + *    \return depending on event
 806 + */
 807 +typedef int (*DSL_BSP_EventCallback_t)
 808 +(
 809 +       DSL_DEV_Device_t *pDev,
 810 +       DSL_BSP_CB_Type_t nCallbackType,
 811 +       DSL_BSP_CB_DATA_Union_t *pData
 812 +);
 813 +
 814 +typedef struct {
 815 +        DSL_BSP_EventCallback_t function;
 816 +        DSL_BSP_CB_Type_t       event;
 817 +        DSL_BSP_CB_DATA_Union_t *pData;
 818 +} DSL_BSP_EventCallBack_t;
 819 +
 820 +extern int DSL_BSP_EventCBRegister(DSL_BSP_EventCallBack_t *);
 821 +extern int DSL_BSP_EventCBUnregister(DSL_BSP_EventCallBack_t *);
 822 +
 823 +/** Modem states */
 824 +#define DSL_DEV_STAT_InitState              0x0000
 825 +#define DSL_DEV_STAT_ReadyState             0x0001
 826 +#define DSL_DEV_STAT_FailState              0x0002
 827 +#define DSL_DEV_STAT_IdleState              0x0003
 828 +#define DSL_DEV_STAT_QuietState             0x0004
 829 +#define DSL_DEV_STAT_GhsState               0x0005
 830 +#define DSL_DEV_STAT_FullInitState          0x0006
 831 +#define DSL_DEV_STAT_ShowTimeState          0x0007
 832 +#define DSL_DEV_STAT_FastRetrainState       0x0008
 833 +#define DSL_DEV_STAT_LoopDiagMode           0x0009
 834 +#define DSL_DEV_STAT_ShortInit              0x000A     /* Bis short initialization */
 835 +
 836 +#define DSL_DEV_STAT_CODESWAP_COMPLETE     0x0002
 837 +
 838 +#endif //IFXMIPS_MEI_H
 839 --- a/configure.in
 840 +++ b/configure.in
 841 @@ -310,7 +310,7 @@
 842  AC_ARG_ENABLE(kernelbuild,
 843      AC_HELP_STRING(--enable-kernel-build=x,Set the target kernel build path),
 844      [
 845 -        if test -e $enableval/include/linux/autoconf.h; then
 846 +        if test -e $enableval/include/linux/autoconf.h -o -e $enableval/include/generated/autoconf.h; then
 847              AC_SUBST([KERNEL_BUILD_PATH],[$enableval])
 848          else
 849              AC_MSG_ERROR([The kernel build directory is not valid or not configured!])
 850 @@ -333,12 +333,12 @@
 851              echo Set the lib_ifxos include path $enableval
 852              AC_SUBST([IFXOS_INCLUDE_PATH],[$enableval])
 853          else
 854 -            echo -e Set the default lib_ifxos include path $DEFAULT_IFXOS_INCLUDE_PATH
 855 +            echo Set the default lib_ifxos include path $DEFAULT_IFXOS_INCLUDE_PATH
 856              AC_SUBST([IFXOS_INCLUDE_PATH],[$DEFAULT_IFXOS_INCLUDE_PATH])
 857          fi
 858      ],
 859      [
 860 -        echo -e Set the default lib_ifxos include path $DEFAULT_IFXOS_INCLUDE_PATH
 861 +        echo Set the default lib_ifxos include path $DEFAULT_IFXOS_INCLUDE_PATH
 862          AC_SUBST([IFXOS_INCLUDE_PATH],[$DEFAULT_IFXOS_INCLUDE_PATH])
 863      ]
 864  )
 865 @@ -1702,73 +1702,73 @@
 866  AC_SUBST([DISTCHECK_CONFIGURE_PARAMS],[$CONFIGURE_OPTIONS])
 867
 868  AC_CONFIG_COMMANDS_PRE([
 869 -echo -e "------------------------------------------------------------------------"
 870 -echo -e " Configuration for drv_dsl_cpe_api:"
 871 -echo -e "  Configure model type:             $DSL_CONFIG_MODEL_TYPE"
 872 -echo -e "  Source code location:             $srcdir"
 873 -echo -e "  Compiler:                         $CC"
 874 -echo -e "  Compiler c-flags:                 $CFLAGS"
 875 -echo -e "  Extra compiler c-flags:           $EXTRA_DRV_CFLAGS"
 876 -echo -e "  Host System Type:                 $host"
 877 -echo -e "  Install path:                     $prefix"
 878 -echo -e "  Linux kernel include path:        $KERNEL_INCL_PATH"
 879 -echo -e "  Linux kernel build path:          $KERNEL_BUILD_PATH"
 880 -echo -e "  Linux kernel architecture:        $KERNEL_ARCH"
 881 -echo -e "  Include IFXOS:                    $INCLUDE_DSL_CPE_API_IFXOS_SUPPORT"
 882 -echo -e "  IFXOS include path:               $IFXOS_INCLUDE_PATH"
 883 -echo -e "  Driver Include Path               $DSL_DRIVER_INCL_PATH"
 884 -echo -e "  DSL device:                       $DSL_DEVICE_NAME"
 885 -echo -e "  Max device number:                $DSL_DRV_MAX_DEVICE_NUMBER"
 886 -echo -e "  Channels per line:                $DSL_CHANNELS_PER_LINE"
 887 -echo -e "  Build lib (only for kernel 2.6)   $DSL_CPE_API_LIBRARY_BUILD_2_6"
 888 -echo -e "  DSL data led flash frequency:     $DSL_DATA_LED_FLASH_FREQUENCY Hz"
 889 -echo -e "  Disable debug prints:             $DSL_DEBUG_DISABLE"
 890 -echo -e "  Preselection of max. debug level: $DSL_DBG_MAX_LEVEL_SET"
 891 -echo -e "  Preselected max. debug level:     $DSL_DBG_MAX_LEVEL_PRE"
 892 -echo -e "  Include deprecated functions:     $INCLUDE_DEPRECATED"
 893 -echo -e "  Include Device Exception Codes:   $INCLUDE_DEVICE_EXCEPTION_CODES"
 894 -echo -e "  Include FW request support:       $INCLUDE_FW_REQUEST_SUPPORT"
 895 -echo -e "  Include ADSL trace buffer:        $INCLUDE_DSL_CPE_TRACE_BUFFER"
 896 -echo -e "  Include ADSL MIB:                 $INCLUDE_DSL_ADSL_MIB"
 897 -echo -e "  Include ADSL LED:                 $INCLUDE_ADSL_LED"
 898 -echo -e "  Include CEOC:                     $INCLUDE_DSL_CEOC"
 899 -echo -e "  Include config get support:       $INCLUDE_DSL_CONFIG_GET"
 900 -echo -e "  Include System i/f configuration: $INCLUDE_DSL_SYSTEM_INTERFACE"
 901 -echo -e "  Include Resource Statistics:      $INCLUDE_DSL_RESOURCE_STATISTICS"
 902 -echo -e "  Include Framing Parameters:       $INCLUDE_DSL_FRAMING_PARAMETERS"
 903 -echo -e "  Include G997 Line Inventory:      $INCLUDE_DSL_G997_LINE_INVENTORY"
 904 -echo -e "  Include G997 Framing Parameters:  $INCLUDE_DSL_G997_FRAMING_PARAMETERS"
 905 -echo -e "  Include G997 per tone data:       $INCLUDE_DSL_G997_PER_TONE"
 906 -echo -e "  Include G997 status:              $INCLUDE_DSL_G997_STATUS"
 907 -echo -e "  Include G997 alarm:               $INCLUDE_DSL_G997_ALARM"
 908 -echo -e "  Include DSL Bonding:              $INCLUDE_DSL_BONDING"
 909 -echo -e "  Include Misc Line Status          $INCLUDE_DSL_CPE_MISC_LINE_STATUS"
 910 -echo -e "  Include DELT:                     $INCLUDE_DSL_DELT"
 911 -echo -e "  Include DELT data static storage: $DSL_CPE_STATIC_DELT_DATA"
 912 -echo -e "  Include PM:                       $INCLUDE_DSL_PM"
 913 -echo -e "  Include PM config:                $INCLUDE_DSL_CPE_PM_CONFIG"
 914 -echo -e "  Include PM total:                 $INCLUDE_DSL_CPE_PM_TOTAL_COUNTERS"
 915 -echo -e "  Include PM history:               $INCLUDE_DSL_CPE_PM_HISTORY"
 916 -echo -e "  Include PM showtime:              $INCLUDE_DSL_CPE_PM_SHOWTIME_COUNTERS"
 917 -echo -e "  Include PM optional:              $INCLUDE_DSL_CPE_PM_OPTIONAL_PARAMETERS"
 918 -echo -e "  Include PM line:                  $INCLUDE_DSL_CPE_PM_LINE_COUNTERS"
 919 -echo -e "  Include PM line event showtime:   $INCLUDE_DSL_CPE_PM_LINE_EVENT_SHOWTIME_COUNTERS"
 920 -echo -e "  Include PM channel:               $INCLUDE_DSL_CPE_PM_CHANNEL_COUNTERS"
 921 -echo -e "  Include PM channel extended:      $INCLUDE_DSL_CPE_PM_CHANNEL_EXT_COUNTERS"
 922 -echo -e "  Include PM data path:             $INCLUDE_DSL_CPE_PM_DATA_PATH_COUNTERS"
 923 -echo -e "  Include PM data path failure:     $INCLUDE_DSL_CPE_PM_DATA_PATH_FAILURE_COUNTERS"
 924 -echo -e "  Include PM ReTx:                  $INCLUDE_DSL_CPE_PM_RETX_COUNTERS"
 925 -echo -e "  Include PM line threshold:        $INCLUDE_DSL_CPE_PM_LINE_THRESHOLDS"
 926 -echo -e "  Include PM channel threshold:     $INCLUDE_DSL_CPE_PM_CHANNEL_THRESHOLDS"
 927 -echo -e "  Include PM data path threshold:   $INCLUDE_DSL_CPE_PM_DATA_PATH_THRESHOLDS"
 928 -echo -e "  Include PM ReTx threshold:        $INCLUDE_DSL_CPE_PM_RETX_THRESHOLDS"
 929 -echo -e "  Include FW memory free support:   $INCLUDE_DSL_FIRMWARE_MEMORY_FREE"
 930 -echo -e "----------------------- deprectated ! ----------------------------------"
 931 -echo -e "  Include PM line failure:          $INCLUDE_DSL_CPE_PM_LINE_FAILURE_COUNTERS"
 932 -echo -e ""
 933 -echo -e " Settings:"
 934 -echo -e "  Configure options:                $CONFIGURE_OPTIONS"
 935 -echo -e "------------------------------------------------------------------------"
 936 +echo "------------------------------------------------------------------------"
 937 +echo " Configuration for drv_dsl_cpe_api:"
 938 +echo "  Configure model type:             $DSL_CONFIG_MODEL_TYPE"
 939 +echo "  Source code location:             $srcdir"
 940 +echo "  Compiler:                         $CC"
 941 +echo "  Compiler c-flags:                 $CFLAGS"
 942 +echo "  Extra compiler c-flags:           $EXTRA_DRV_CFLAGS"
 943 +echo "  Host System Type:                 $host"
 944 +echo "  Install path:                     $prefix"
 945 +echo "  Linux kernel include path:        $KERNEL_INCL_PATH"
 946 +echo "  Linux kernel build path:          $KERNEL_BUILD_PATH"
 947 +echo "  Linux kernel architecture:        $KERNEL_ARCH"
 948 +echo "  Include IFXOS:                    $INCLUDE_DSL_CPE_API_IFXOS_SUPPORT"
 949 +echo "  IFXOS include path:               $IFXOS_INCLUDE_PATH"
 950 +echo "  Driver Include Path               $DSL_DRIVER_INCL_PATH"
 951 +echo "  DSL device:                       $DSL_DEVICE_NAME"
 952 +echo "  Max device number:                $DSL_DRV_MAX_DEVICE_NUMBER"
 953 +echo "  Channels per line:                $DSL_CHANNELS_PER_LINE"
 954 +echo "  Build lib (only for kernel 2.6)   $DSL_CPE_API_LIBRARY_BUILD_2_6"
 955 +echo "  DSL data led flash frequency:     $DSL_DATA_LED_FLASH_FREQUENCY Hz"
 956 +echo "  Disable debug prints:             $DSL_DEBUG_DISABLE"
 957 +echo "  Preselection of max. debug level: $DSL_DBG_MAX_LEVEL_SET"
 958 +echo "  Preselected max. debug level:     $DSL_DBG_MAX_LEVEL_PRE"
 959 +echo "  Include deprecated functions:     $INCLUDE_DEPRECATED"
 960 +echo "  Include Device Exception Codes:   $INCLUDE_DEVICE_EXCEPTION_CODES"
 961 +echo "  Include FW request support:       $INCLUDE_FW_REQUEST_SUPPORT"
 962 +echo "  Include ADSL trace buffer:        $INCLUDE_DSL_CPE_TRACE_BUFFER"
 963 +echo "  Include ADSL MIB:                 $INCLUDE_DSL_ADSL_MIB"
 964 +echo "  Include ADSL LED:                 $INCLUDE_ADSL_LED"
 965 +echo "  Include CEOC:                     $INCLUDE_DSL_CEOC"
 966 +echo "  Include config get support:       $INCLUDE_DSL_CONFIG_GET"
 967 +echo "  Include System i/f configuration: $INCLUDE_DSL_SYSTEM_INTERFACE"
 968 +echo "  Include Resource Statistics:      $INCLUDE_DSL_RESOURCE_STATISTICS"
 969 +echo "  Include Framing Parameters:       $INCLUDE_DSL_FRAMING_PARAMETERS"
 970 +echo "  Include G997 Line Inventory:      $INCLUDE_DSL_G997_LINE_INVENTORY"
 971 +echo "  Include G997 Framing Parameters:  $INCLUDE_DSL_G997_FRAMING_PARAMETERS"
 972 +echo "  Include G997 per tone data:       $INCLUDE_DSL_G997_PER_TONE"
 973 +echo "  Include G997 status:              $INCLUDE_DSL_G997_STATUS"
 974 +echo "  Include G997 alarm:               $INCLUDE_DSL_G997_ALARM"
 975 +echo "  Include DSL Bonding:              $INCLUDE_DSL_BONDING"
 976 +echo "  Include Misc Line Status          $INCLUDE_DSL_CPE_MISC_LINE_STATUS"
 977 +echo "  Include DELT:                     $INCLUDE_DSL_DELT"
 978 +echo "  Include DELT data static storage: $DSL_CPE_STATIC_DELT_DATA"
 979 +echo "  Include PM:                       $INCLUDE_DSL_PM"
 980 +echo "  Include PM config:                $INCLUDE_DSL_CPE_PM_CONFIG"
 981 +echo "  Include PM total:                 $INCLUDE_DSL_CPE_PM_TOTAL_COUNTERS"
 982 +echo "  Include PM history:               $INCLUDE_DSL_CPE_PM_HISTORY"
 983 +echo "  Include PM showtime:              $INCLUDE_DSL_CPE_PM_SHOWTIME_COUNTERS"
 984 +echo "  Include PM optional:              $INCLUDE_DSL_CPE_PM_OPTIONAL_PARAMETERS"
 985 +echo "  Include PM line:                  $INCLUDE_DSL_CPE_PM_LINE_COUNTERS"
 986 +echo "  Include PM line event showtime:   $INCLUDE_DSL_CPE_PM_LINE_EVENT_SHOWTIME_COUNTERS"
 987 +echo "  Include PM channel:               $INCLUDE_DSL_CPE_PM_CHANNEL_COUNTERS"
 988 +echo "  Include PM channel extended:      $INCLUDE_DSL_CPE_PM_CHANNEL_EXT_COUNTERS"
 989 +echo "  Include PM data path:             $INCLUDE_DSL_CPE_PM_DATA_PATH_COUNTERS"
 990 +echo "  Include PM data path failure:     $INCLUDE_DSL_CPE_PM_DATA_PATH_FAILURE_COUNTERS"
 991 +echo "  Include PM ReTx:                  $INCLUDE_DSL_CPE_PM_RETX_COUNTERS"
 992 +echo "  Include PM line threshold:        $INCLUDE_DSL_CPE_PM_LINE_THRESHOLDS"
 993 +echo "  Include PM channel threshold:     $INCLUDE_DSL_CPE_PM_CHANNEL_THRESHOLDS"
 994 +echo "  Include PM data path threshold:   $INCLUDE_DSL_CPE_PM_DATA_PATH_THRESHOLDS"
 995 +echo "  Include PM ReTx threshold:        $INCLUDE_DSL_CPE_PM_RETX_THRESHOLDS"
 996 +echo "  Include FW memory free support:   $INCLUDE_DSL_FIRMWARE_MEMORY_FREE"
 997 +echo "----------------------- deprectated ! ----------------------------------"
 998 +echo "  Include PM line failure:          $INCLUDE_DSL_CPE_PM_LINE_FAILURE_COUNTERS"
 999 +echo ""
1000 +echo " Settings:"
1001 +echo "  Configure options:                $CONFIGURE_OPTIONS"
1002 +echo "------------------------------------------------------------------------"
1003  ])
1004
1005  AC_CONFIG_FILES([Makefile src/Makefile])
1006 --- a/src/Makefile.am
1007 +++ b/src/Makefile.am
1008 @@ -303,7 +303,7 @@
1009  drv_dsl_cpe_api_OBJS = "$(subst .c,.o,$(filter %.c,$(drv_dsl_cpe_api_SOURCES)))"
1010
1011  drv_dsl_cpe_api.ko: $(drv_dsl_cpe_api_SOURCES)
1012 -       @echo -e "drv_dsl_cpe_api: Making Linux 2.6.x kernel object"
1013 +       @echo "drv_dsl_cpe_api: Making Linux 2.6.x kernel object"
1014         if test ! -e common/drv_dsl_cpe_api.c ; then \
1015                 echo "copy source files (as links only!)"; \
1016                 for f in $(filter %.c,$(drv_dsl_cpe_api_SOURCES)); do \
1017 @@ -311,10 +311,10 @@
1018                         cp -s $(addprefix @abs_srcdir@/,$$f) $(PWD)/`dirname $$f`/ ; \
1019                 done \
1020         fi
1021 -       @echo -e "# drv_dsl_cpe_api: Generated to build Linux 2.6.x kernel object" > $(PWD)/Kbuild
1022 -       @echo -e "obj-m := $(subst .ko,.o,$@)"                  >> $(PWD)/Kbuild
1023 -       @echo -e "$(subst .ko,,$@)-y := $(drv_dsl_cpe_api_OBJS)"        >> $(PWD)/Kbuild
1024 -       @echo -e "EXTRA_CFLAGS := $(CFLAGS) -DHAVE_CONFIG_H $(drv_dsl_cpe_api_CFLAGS) $(DSL_DRIVER_INCL_PATH) $(IFXOS_INCLUDE_PATH) -I@abs_srcdir@/include -I$(PWD)/include"    >> $(PWD)/Kbuild
1025 +       @echo "# drv_dsl_cpe_api: Generated to build Linux 2.6.x kernel object" > $(PWD)/Kbuild
1026 +       @echo "obj-m := $(subst .ko,.o,$@)"                     >> $(PWD)/Kbuild
1027 +       @echo "$(subst .ko,,$@)-y := $(drv_dsl_cpe_api_OBJS)"   >> $(PWD)/Kbuild
1028 +       @echo "EXTRA_CFLAGS := $(CFLAGS) -DHAVE_CONFIG_H $(drv_dsl_cpe_api_CFLAGS) $(DSL_DRIVER_INCL_PATH) $(IFXOS_INCLUDE_PATH) -I@abs_srcdir@/include -I$(PWD)/include"       >> $(PWD)/Kbuild
1029         $(MAKE) ARCH=@KERNEL_ARCH@ -C @KERNEL_BUILD_PATH@ O=@KERNEL_BUILD_PATH@ M=$(PWD) modules
1030
1031  clean-generic:
1032 --- a/src/include/drv_dsl_cpe_os_linux.h
1033 +++ b/src/include/drv_dsl_cpe_os_linux.h
1034 @@ -16,8 +16,6 @@
1035     extern "C" {
1036  #endif
1037
1038 -#include <asm/ioctl.h>
1039 -#include <generated/autoconf.h>
1040  #include <linux/module.h>
1041  #include <linux/kernel.h>
1042  #include <linux/init.h>
1043 @@ -26,8 +24,10 @@
1044  #include <linux/spinlock.h>
1045  #include <linux/sched.h>
1046
1047 -#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,17))
1048 -   #include <generated/utsrelease.h>
1049 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,33))
1050 +#include <linux/utsrelease.h>
1051 +#else
1052 +#include <generated/utsrelease.h>
1053  #endif
1054
1055  #include <linux/types.h>
1056 @@ -39,7 +39,8 @@
1057  #include <linux/delay.h>
1058  #include <linux/poll.h>
1059  #include <asm/uaccess.h>
1060 -#include <linux/smp_lock.h>
1061 +//#include <linux/smp_lock.h>
1062 +#include <asm/ioctl.h>
1063
1064  #ifdef INCLUDE_DSL_CPE_API_IFXOS_SUPPORT
1065  /** IFXOS includes*/