ar71xx: Extend the list of bits in QCA955X_GMAC_REG_ETH_CFG

Signed-off-by: Sven Eckelmann <sven.eckelmann@open-mesh.com>
Backport of r49027

diff --git a/target/linux/ar71xx/patches-3.18/601-MIPS-ath79-add-more-register-defines.patch b/target/linux/ar71xx/patches-3.18/601-MIPS-ath79-add-more-register-defines.patch
index 8bf7658..797977f 100644 (file)
--- a/target/linux/ar71xx/patches-3.18/601-MIPS-ath79-add-more-register-defines.patch
+++ b/target/linux/ar71xx/patches-3.18/601-MIPS-ath79-add-more-register-defines.patch
@@ -207,7 +207,7 @@
  #define AR934X_GPIO_REG_FUNC          0x6c
  
  #define AR71XX_GPIO_COUNT             16
-@@ -560,4 +663,153 @@
+@@ -560,4 +663,170 @@
  #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT        13
  #define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
  
@@ -358,6 +358,23 @@
 +#define QCA955X_GMAC_REG_ETH_CFG      0x00
 +
 +#define QCA955X_ETH_CFG_RGMII_EN      BIT(0)
++#define QCA955X_ETH_CFG_MII_GE0               BIT(1)
++#define QCA955X_ETH_CFG_GMII_GE0      BIT(2)
++#define QCA955X_ETH_CFG_MII_GE0_MASTER        BIT(3)
++#define QCA955X_ETH_CFG_MII_GE0_SLAVE BIT(4)
++#define QCA955X_ETH_CFG_GE0_ERR_EN    BIT(5)
 +#define QCA955X_ETH_CFG_GE0_SGMII     BIT(6)
++#define QCA955X_ETH_CFG_RMII_GE0      BIT(10)
++#define QCA955X_ETH_CFG_MII_CNTL_SPEED        BIT(11)
++#define QCA955X_ETH_CFG_RMII_GE0_MASTER       BIT(12)
++#define QCA955X_ETH_CFG_RXD_DELAY_MASK        0x3
++#define QCA955X_ETH_CFG_RXD_DELAY_SHIFT       14
++#define QCA955X_ETH_CFG_RDV_DELAY     BIT(16)
++#define QCA955X_ETH_CFG_RDV_DELAY_MASK        0x3
++#define QCA955X_ETH_CFG_RDV_DELAY_SHIFT       16
++#define QCA955X_ETH_CFG_TXD_DELAY_MASK        0x3
++#define QCA955X_ETH_CFG_TXD_DELAY_SHIFT       18
++#define QCA955X_ETH_CFG_TXE_DELAY_MASK        0x3
++#define QCA955X_ETH_CFG_TXE_DELAY_SHIFT       20
 +
  #endif /* __ASM_MACH_AR71XX_REGS_H */