target/linux/ramips/patches-3.18/500-alsa.patch

   1 --- a/sound/soc/Kconfig
   2 +++ b/sound/soc/Kconfig
   3 @@ -56,6 +56,7 @@
   4  source "sound/soc/tegra/Kconfig"
   5  source "sound/soc/txx9/Kconfig"
   6  source "sound/soc/ux500/Kconfig"
   7 +source "sound/soc/mtk/Kconfig"
   8
   9  # Supported codecs
  10  source "sound/soc/codecs/Kconfig"
  11 --- a/sound/soc/Makefile
  12 +++ b/sound/soc/Makefile
  13 @@ -33,3 +33,4 @@
  14  obj-$(CONFIG_SND_SOC)  += tegra/
  15  obj-$(CONFIG_SND_SOC)  += txx9/
  16  obj-$(CONFIG_SND_SOC)  += ux500/
  17 +obj-$(CONFIG_SND_SOC)   += mtk/
  18 --- a/sound/soc/codecs/Kconfig
  19 +++ b/sound/soc/codecs/Kconfig
  20 @@ -725,7 +725,7 @@
  21         tristate
  22
  23  config SND_SOC_WM8960
  24 -       tristate
  25 +       tristate "WM8960"
  26
  27  config SND_SOC_WM8961
  28         tristate
  29 --- /dev/null
  30 +++ b/sound/soc/mtk/Kconfig
  31 @@ -0,0 +1,35 @@
  32 +config SND_MT76XX_SOC
  33 +       tristate "SoC Audio for MT76XX APSoC Machine"
  34 +       depends on SND_SOC && (SOC_MT7620 || SOC_MT7621)
  35 +
  36 +       help
  37 +         Say Y or M if you want to add support for codecs attached to
  38 +         the MTK I2S interface.
  39 +
  40 +choice
  41 +       prompt "Selected SoC type"
  42 +       depends on SND_MT76XX_SOC
  43 +       default SND_MT76XX_SOC_MT7620
  44 +
  45 +config SND_MT76XX_SOC_MT7620
  46 +       bool "MT7620"
  47 +       depends on SOC_MT7620
  48 +
  49 +config SND_MT76XX_SOC_MT7628
  50 +       bool "MT7628"
  51 +       depends on SOC_MT7620
  52 +
  53 +config SND_MT76XX_SOC_MT7621
  54 +       bool "MT7621"
  55 +       depends on SOC_MT7621
  56 +
  57 +endchoice
  58 +
  59 +config SND_MT76XX_PCM
  60 +       tristate "MTK SoC Audio PCM Platform"
  61 +       depends on SND_MT76XX_SOC
  62 +
  63 +config SND_MT76XX_I2S
  64 +       tristate "MTK SoC I2S Support"
  65 +       depends on SND_MT76XX_SOC
  66 +
  67 --- /dev/null
  68 +++ b/sound/soc/mtk/Makefile
  69 @@ -0,0 +1,39 @@
  70 +KBUILD_CFLAGS += -I$(srctree)
  71 +
  72 +ifeq ($(CONFIG_SND_MT76XX_SOC_MT7620),y)
  73 +KBUILD_CFLAGS += -DCONFIG_MT7620 -DCONFIG_RALINK_MT7620
  74 +endif
  75 +ifeq ($(CONFIG_SND_MT76XX_SOC_MT7628),y)
  76 +KBUILD_CFLAGS += -DCONFIG_MT7628 -DCONFIG_RALINK_MT7628
  77 +endif
  78 +ifeq ($(CONFIG_SOC_MT7620),y)
  79 +KBUILD_CFLAGS += -DRALINK_SYSCTL_BASE=0xB0000000
  80 +KBUILD_CFLAGS += -DRALINK_INTCL_BASE=0xB0000200
  81 +KBUILD_CFLAGS += -DRALINK_PIO_BASE=0xB0000600
  82 +KBUILD_CFLAGS += -DRALINK_I2S_BASE=0xB0000A00
  83 +KBUILD_CFLAGS += -DRALINK_GDMA_BASE=0xB0002800
  84 +KBUILD_CFLAGS += -DCONFIG_GDMA_EVERYBODY
  85 +KBUILD_CFLAGS += -DCONFIG_SND_MT76XX_SOC
  86 +KBUILD_CFLAGS += -DCONFIG_I2S_WM8960
  87 +KBUILD_CFLAGS += -DCONFIG_I2S_MCLK_12P288MHZ
  88 +KBUILD_CFLAGS += -DCONFIG_GDMA_EVERYBODY
  89 +KBUILD_CFLAGS += -DSURFBOARDINT_DMA=15
  90 +KBUILD_CFLAGS += -DRALINK_INTCTL_DMA=128
  91 +KBUILD_CFLAGS += -DCONFIG_SND_SOC_WM8960
  92 +endif
  93 +
  94 +# MTK APSoC Platform Support
  95 +snd-soc-mt76xx-i2s-ctl-objs := i2s_ctrl.o i2s_debug.o #i2c_wm8960.o
  96 +snd-soc-mt76xx-pcm-objs := mt76xx_pcm.o
  97 +snd-soc-mt76xx-i2s-objs := mt76xx_i2s.o
  98 +
  99 +obj-$(CONFIG_SND_MT76XX_PCM) += snd-soc-mt76xx-pcm.o
 100 +obj-$(CONFIG_SND_MT76XX_I2S) += snd-soc-mt76xx-i2s-ctl.o snd-soc-mt76xx-i2s.o
 101 +
 102 +# MTK APSoC Machine Support
 103 +snd-soc-mt76xx-machine-objs := mt76xx_machine.o
 104 +
 105 +obj-$(CONFIG_SND_MT76XX_SOC) += i2c_wm8960.o ralink_gdma.o snd-soc-mt76xx-machine.o
 106 +
 107 +
 108 +
 109 --- /dev/null
 110 +++ b/sound/soc/mtk/i2c_wm8960.c
 111 @@ -0,0 +1,492 @@
 112 +#include <linux/kernel.h>
 113 +#include <linux/version.h>
 114 +#include <linux/init.h>
 115 +#include <linux/module.h>
 116 +#include <linux/slab.h>
 117 +#include <linux/i2c.h>
 118 +#include <linux/delay.h>
 119 +#include <linux/interrupt.h>
 120 +#include <linux/fs.h>
 121 +#include <linux/fcntl.h>
 122 +#include <linux/cdev.h>
 123 +#if defined(CONFIG_ARCH_MT7623)
 124 +#include <mt_i2c.h>
 125 +#include <mach/mt_gpio.h>
 126 +#endif
 127 +#include "i2c_wm8960.h"
 128 +#include "i2s_ctrl.h"
 129 +
 130 +
 131 +#define BUF_SIZE               20
 132 +
 133 +#undef MSG
 134 +#define MSG printk
 135 +
 136 +
 137 +#if defined(CONFIG_ARCH_MT7623)
 138 +/*FIXME*/
 139 +//static struct i2c_board_info __initdata i2c_devs1 = { I2C_BOARD_INFO("codec_wm8960", (0X34>>1))};
 140 +static struct i2c_board_info __initdata i2c_devs1 = { I2C_BOARD_INFO("codec_wm8960", (0X34))};
 141 +
 142 +#endif
 143 +unsigned long wm_reg_data[56];
 144 +struct wm8960_data *wmio;
 145 +
 146 +struct wm8960_data {
 147 +       struct i2c_client       *client;
 148 +       struct device       *dev;
 149 +       const char                      *name;
 150 +};
 151 +
 152 +
 153 +void i2c_WM8960_write(u32 reg, u32 data)
 154 +{
 155 +       int ret;
 156 +        struct i2c_msg msg;
 157 +       u8 buf[2]={0};
 158 +
 159 +#if defined(CONFIG_ARCH_MT7623)
 160 +       unsigned int ext_flag = 0;
 161 +
 162 +       ext_flag &= 0x7FFFFFFF;
 163 +       ext_flag |= I2C_A_FILTER_MSG;
 164 +       ext_flag |= I2C_POLLING_FLAG;
 165 +#endif
 166 +
 167 +       wm_reg_data[reg] = data;
 168 +
 169 +       buf[0]= (reg<<1)|(0x01&(data>>8));
 170 +       buf[1]= (data&0xFF);
 171 +
 172 +#if defined(CONFIG_ARCH_MT7623)
 173 +       /*FIXME*/
 174 +       //msg.addr = wmio->client->addr;
 175 +       msg.addr = wmio->client->addr>>1;
 176 +
 177 +#else
 178 +        msg.addr = wmio->client->addr>>1;
 179 +#endif
 180 +       msg.flags = 0;
 181 +        msg.buf = (char *)buf;
 182 +       msg.len = 2;
 183 +#if defined(CONFIG_ARCH_MT7623)
 184 +       msg.timing = 80;
 185 +       msg.ext_flag = ext_flag & 0x7FFFFFFF;
 186 +#endif
 187 +
 188 +        ret = i2c_transfer(wmio->client->adapter, &msg, 1);
 189 +       MSG("[WM8960(%02X)=0x%08X]\n",(unsigned int)reg,(unsigned int)data);
 190 +
 191 +        if (ret <= 0)
 192 +                printk("%s: i2c write error!\n", __func__);
 193 +}
 194 +
 195 +
 196 +
 197 +// Reset and power up the WM8960
 198 +void audiohw_preinit(void)
 199 +{
 200 +       memset(wm_reg_data, 0 , sizeof(unsigned long)*55);
 201 +
 202 +       i2c_WM8960_write(RESET, RESET_RESET);    // Reset (0x0F)
 203 +
 204 +       mdelay(50);
 205 +       wm_reg_data[RESET] = 0xFFFF;
 206 +       mdelay(50);
 207 +}
 208 +
 209 +void audiohw_set_apll(int srate)
 210 +{
 211 +       unsigned long data;
 212 +
 213 +       if((srate==8000) || (srate==12000) || (srate==16000) || (srate==24000) || (srate==32000) || (srate==48000))
 214 +       {
 215 +               // Provide 12.288MHz SYSCLK
 216 +               data = wm_reg_data[PLL1];
 217 +               i2c_WM8960_write(PLL1, data | PLL1_OPCLKDIV_1 | PLL1_SDM_FRACTIONAL | PLL1_PLLPRESCALE_1 | PLL1_PLLN(0x8));   // PLL1 (0x34)
 218 +
 219 +               i2c_WM8960_write(PLL2, PLL2_PLLK_23_16(0x31));  // PLL2 (0x35)
 220 +               i2c_WM8960_write(PLL3, PLL3_PLLK_15_8(0x26));  // PLL3 (0x36)
 221 +               i2c_WM8960_write(PLL4, PLL4_PLLK_7_0(0xe9));  // PLL4 (0x37)
 222 +       }
 223 +       else if ((srate==11025) || (srate==22050) || (srate==44100))
 224 +       {
 225 +               //Provide 11.2896MHz SYSCLK
 226 +               data = wm_reg_data[PLL1];
 227 +               i2c_WM8960_write(PLL1, data | PLL1_OPCLKDIV_1 | PLL1_SDM_FRACTIONAL | PLL1_PLLPRESCALE_1 | PLL1_PLLN(0x7));   //PLL1 (0x34)
 228 +
 229 +               i2c_WM8960_write(PLL2, PLL2_PLLK_23_16(0x86));  //PLL2 (0x35)
 230 +               i2c_WM8960_write(PLL3, PLL3_PLLK_15_8(0xc2));  //PLL3 (0x36)
 231 +               i2c_WM8960_write(PLL4, PLL4_PLLK_7_0(0x26));  //PLL4 (0x37)
 232 +       }
 233 +       else
 234 +       {
 235 +               printk("Not support this srate\n");
 236 +       }
 237 +       mdelay(3);
 238 +}
 239 +
 240 +
 241 +void audiohw_set_frequency(int fsel, int pll_en)
 242 +{
 243 +        MSG("audiohw_set_frequency_=0x%08X\n",fsel);
 244 +
 245 +       if (pll_en)
 246 +       {
 247 +               printk("PLL enable\n");
 248 +               i2c_WM8960_write(CLOCKING1, (fsel<<3) | CLOCKING1_SYSCLKDIV_2 | CLOCKING1_CLKSEL_PLL);  //CLOCKING (0x04)=>0x05
 249 +
 250 +       }
 251 +       else
 252 +       {
 253 +               printk("PLL disable\n");
 254 +               i2c_WM8960_write(CLOCKING1, (fsel<<3));//| CLOCKING1_SYSCLKDIV_2);  //CLOCKING (0x04)
 255 +       }
 256 +
 257 +}
 258 +
 259 +//FIXME
 260 +int audiohw_set_lineout_vol(int Aout, int vol_l, int vol_r)
 261 +{
 262 +       MSG("audiohw_set_lineout_vol_\n");
 263 +       switch(Aout)
 264 +       {
 265 +       case 1:
 266 +               //i2c_WM8960_write(LOUT1, LOUT1_LO1VU|LOUT1_LO1ZC|LOUT1_LOUT1VOL(0x7f)); //LOUT1(0x02)
 267 +               //i2c_WM8960_write(ROUT1, ROUT1_RO1VU|ROUT1_RO1ZC|ROUT1_ROUT1VOL(0x7f)); //ROUT1(0x03)
 268 +               i2c_WM8960_write(LOUT1, LOUT1_LO1VU|LOUT1_LO1ZC|LOUT1_LOUT1VOL(vol_l)); //LOUT1(0x02)
 269 +               i2c_WM8960_write(ROUT1, ROUT1_RO1VU|ROUT1_RO1ZC|ROUT1_ROUT1VOL(vol_r)); //ROUT1(0x03)
 270 +               break;
 271 +       case 2:
 272 +               i2c_WM8960_write(LSPK, LSPK_SPKLVU|LSPK_SPKLZC| LSPK_SPKLVOL(vol_l));
 273 +               i2c_WM8960_write(RSPK, RSPK_SPKRVU|RSPK_SPKRZC| RSPK_SPKRVOL(vol_r));
 274 +               break;
 275 +       default:
 276 +               break;
 277 +       }
 278 +       return 0;
 279 +}
 280 +
 281 +//FIXME
 282 +int audiohw_set_linein_vol(int vol_l, int vol_r)
 283 +{
 284 +       MSG("audiohw_set_linein_vol_\n");
 285 +
 286 +    i2c_WM8960_write(LINV, LINV_IPVU|LINV_LINVOL(vol_l)); //LINV(0x00)=>0x12b
 287 +       i2c_WM8960_write(RINV, RINV_IPVU|RINV_RINVOL(vol_r)); //LINV(0x01)=>0x12b
 288 +
 289 +       return 0;
 290 +}
 291 +
 292 +//Set signal path
 293 +int audiohw_postinit(int bSlave, int AIn, int AOut, int pll_en, int wordLen24b)
 294 +{
 295 +
 296 +       int i;
 297 +       unsigned long data;
 298 +
 299 +       if(wm_reg_data[RESET]!=0xFFFF)
 300 +       return 0;
 301 +
 302 +       if(bSlave)
 303 +       {
 304 +               MSG("WM8960 slave.....\n");
 305 +               if(wordLen24b)
 306 +               {
 307 +                       printk("24 bit word length\n");
 308 +                       i2c_WM8960_write(AINTFCE1, AINTFCE1_WL_24 | AINTFCE1_FORMAT_I2S); //AINTFCE1(0x07)
 309 +               }
 310 +               else
 311 +               {
 312 +                       printk("16 bit word length\n");
 313 +                       i2c_WM8960_write(AINTFCE1, AINTFCE1_WL_16 | AINTFCE1_FORMAT_I2S); //AINTFCE1(0x07)
 314 +               }
 315 +       }
 316 +       else
 317 +       {
 318 +               MSG("WM8960 master.....\n");
 319 +               i2c_WM8960_write(CLOCKING2, 0x1c4);//CLOCKING2_BCLKDIV(0x1c4));  //CLOCKING2(0x08)
 320 +
 321 +               if(wordLen24b)
 322 +               {
 323 +                       printk("24 bit word length\n");
 324 +                       i2c_WM8960_write(AINTFCE1, AINTFCE1_MS | AINTFCE1_WL_24 | AINTFCE1_FORMAT_I2S); //AINTFCE1(0x07)
 325 +               }
 326 +               else
 327 +               {
 328 +                       printk("16 bit word length\n");
 329 +                       i2c_WM8960_write(AINTFCE1, AINTFCE1_MS | AINTFCE1_WL_16 | AINTFCE1_FORMAT_I2S); //AINTFCE1(0x07)
 330 +               }
 331 +               mdelay(5);
 332 +       }
 333 +
 334 +
 335 +       //From app notes: allow Vref to stabilize to reduce clicks
 336 +       for(i = 0; i < 1000*HZ; i++);
 337 +
 338 +       if(AIn > 0)
 339 +       {
 340 +                       data = wm_reg_data[PWRMGMT1];
 341 +               i2c_WM8960_write(PWRMGMT1, data|PWRMGMT1_ADCL|PWRMGMT1_ADCR|PWRMGMT1_AINL |PWRMGMT1_AINR);//|PWRMGMT1_MICB);//PWRMGMT1(0x19)
 342 +
 343 +               data = wm_reg_data[ADDITIONAL1];
 344 +               i2c_WM8960_write(ADDITIONAL1, data|ADDITIONAL1_DATSEL(0x01)); //ADDITIONAL1(0x17)
 345 +               i2c_WM8960_write(LADCVOL, LADCVOL_LAVU_EN|LADCVOL_LADCVOL(0xc3)); //LADCVOL(0x15)
 346 +               i2c_WM8960_write(RADCVOL, RADCVOL_RAVU_EN|RADCVOL_RADCVOL(0xc3)); //RADCVOL(0x16)
 347 +               i2c_WM8960_write(ADCLPATH, ADCLPATH_LMN1|ADCLPATH_LMIC2B);//|ADCLPATH_LMICBOOST_13DB); //ADCLPATH(0x20)=>(0x108)
 348 +               i2c_WM8960_write(ADCRPATH, ADCRPATH_RMN1|ADCRPATH_RMIC2B);//|ADCRPATH_RMICBOOST_13DB); //ADCRPATH(0x21)=>(0x108)
 349 +               i2c_WM8960_write(PWRMGMT3, PWRMGMT3_LMIC|PWRMGMT3_RMIC); //PWRMGMT3(0x2f)
 350 +
 351 +               //i2c_WM8960_write(LINBMIX, 0x000); //LINBMIX(0x2B)
 352 +
 353 +               if (AOut<=0)
 354 +               {
 355 +                       i2c_WM8960_write(AINTFCE2, 0x40); //FIXME:(0x09)
 356 +
 357 +                       data = wm_reg_data[PWRMGMT2];
 358 +                       if(pll_en)
 359 +                       {
 360 +                               i2c_WM8960_write(PWRMGMT2, data|PWRMGMT2_PLL_EN|PWRMGMT2_DACL|PWRMGMT2_DACR); //PWRMGMT2(0x1a)
 361 +                       }
 362 +                       else
 363 +                       {
 364 +                               i2c_WM8960_write(PWRMGMT2, data|PWRMGMT2_DACL|PWRMGMT2_DACR); //PWRMGMT2(0x1a)
 365 +
 366 +                       }
 367 +               }
 368 +       }
 369 +       if(AOut>0)
 370 +       {
 371 +               //Power management 2 setting
 372 +               data = wm_reg_data[PWRMGMT2];
 373 +
 374 +               if(pll_en)
 375 +               {
 376 +                       i2c_WM8960_write(PWRMGMT2, data|PWRMGMT2_PLL_EN|PWRMGMT2_DACL|PWRMGMT2_DACR|PWRMGMT2_LOUT1|PWRMGMT2_ROUT1|PWRMGMT2_SPKL|PWRMGMT2_SPKR); //PWRMGMT2(0x1a)
 377 +               }
 378 +               else
 379 +               {
 380 +                       i2c_WM8960_write(PWRMGMT2, data|PWRMGMT2_DACL|PWRMGMT2_DACR|PWRMGMT2_LOUT1|PWRMGMT2_ROUT1|PWRMGMT2_SPKL|PWRMGMT2_SPKR); //PWRMGMT2(0x1a)
 381 +
 382 +               }
 383 +
 384 +               mdelay(10);
 385 +
 386 +               i2c_WM8960_write(AINTFCE2, 0x40); //FIXME:(0x09)
 387 +
 388 +               i2c_WM8960_write(LEFTGAIN, LEFTGAIN_LDVU|LEFTGAIN_LDACVOL(0xff)); //LEFTGAIN(0x0a)
 389 +               i2c_WM8960_write(RIGHTGAIN, RIGHTGAIN_RDVU|RIGHTGAIN_RDACVOL(0xff)); //RIGHTGAIN(0x0b)
 390 +
 391 +               i2c_WM8960_write(LEFTMIX1, 0x100);  //LEFTMIX1(0x22)
 392 +               i2c_WM8960_write(RIGHTMIX2, 0x100); //RIGHTMIX2(0x25)
 393 +
 394 +               data = wm_reg_data[PWRMGMT3]; //FIXME
 395 +               i2c_WM8960_write(PWRMGMT3, data|PWRMGMT3_ROMIX|PWRMGMT3_LOMIX); //PWRMGMT3(0x2f)
 396 +
 397 +               data = wm_reg_data[CLASSDCTRL1]; //CLASSDCTRL1(0x31) SPEAKER FIXME
 398 +               i2c_WM8960_write(CLASSDCTRL1, 0xf7);//data|CLASSDCTRL1_OP_LRSPK);
 399 +
 400 +               data = wm_reg_data[CLASSDCTRL3];        //CLASSDCTRL3(0x33)
 401 +               i2c_WM8960_write(CLASSDCTRL3, 0xad);//data|(0x1b));
 402 +       }
 403 +
 404 +       i2c_WM8960_write(DACCTRL1, 0x000);  //DACCTRL1(0x05)
 405 +
 406 +       data = wm_reg_data[PWRMGMT1];
 407 +       i2c_WM8960_write(PWRMGMT1, data|0x1c0); //FIXME:PWRMGMT1(0x19)
 408 +
 409 +
 410 +       printk("WM8960 All initial ok!\n");
 411 +
 412 +       return 0;
 413 +
 414 +}
 415 +
 416 +void audiohw_micboost(int boostgain)
 417 +{
 418 +       unsigned long data;
 419 +
 420 +       data =  wm_reg_data[ADCLPATH];
 421 +       i2c_WM8960_write(ADCLPATH, data|(boostgain << 4));
 422 +
 423 +       data =  wm_reg_data[ADCRPATH];
 424 +       i2c_WM8960_write(ADCRPATH, data|(boostgain << 4));
 425 +}
 426 +
 427 +void audiohw_micin(int enableMic)
 428 +{
 429 +       unsigned long data;
 430 +
 431 +       if (enableMic==1)
 432 +       {
 433 +               data =  wm_reg_data[PWRMGMT1];
 434 +               i2c_WM8960_write(PWRMGMT1, data|PWRMGMT1_MICB);
 435 +       }
 436 +#if 1
 437 +       else
 438 +       {
 439 +               data =  wm_reg_data[PWRMGMT1];
 440 +               i2c_WM8960_write(PWRMGMT1, data & (~(PWRMGMT1_MICB)));
 441 +       }
 442 +#endif
 443 +}
 444 +
 445 +void audiohw_mute( bool mute)
 446 +{
 447 +    //Mute:   Set DACMU = 1 to soft-mute the audio DACs.
 448 +    //Unmute: Set DACMU = 0 to soft-un-mute the audio DACs.
 449 +    i2c_WM8960_write(DACCTRL1, mute ? DACCTRL1_DACMU : 0);
 450 +}
 451 +
 452 +
 453 +//Nice shutdown of WM8960 codec
 454 +void audiohw_close(void)
 455 +{
 456 +       i2c_WM8960_write(DACCTRL1,DACCTRL1_DACMU); //0x05->0x08
 457 +       i2c_WM8960_write(PWRMGMT1, 0x000); //0x19->0x000
 458 +       mdelay(400);
 459 +       i2c_WM8960_write(PWRMGMT2, 0x000); //0x1a->0x000
 460 +
 461 +}
 462 +
 463 +void audiohw_loopback(int fsel)
 464 +{
 465 +}
 466 +
 467 +void audiohw_codec_exlbk(void)
 468 +{
 469 +       memset(wm_reg_data, 0 , sizeof(unsigned long)*55);
 470 +
 471 +       i2c_WM8960_write(LINV, 0x117); //0x00->0x117
 472 +       i2c_WM8960_write(RINV, 0x117); //0x01->0x117
 473 +       i2c_WM8960_write(LOUT1, 0x179); //0x02->0x179
 474 +       i2c_WM8960_write(ROUT1, 0x179); //0x03->0x179
 475 +       i2c_WM8960_write(CLOCKING1, 0x00); //0x04->0x00
 476 +       //i2c_WM8960_write(CLOCKING1, 0x40); //0x04->0x00
 477 +       i2c_WM8960_write(DACCTRL1, 0x00); //0x05->0x00
 478 +       i2c_WM8960_write(AINTFCE2, 0x41); //0x09->0x41
 479 +       i2c_WM8960_write(LADCVOL, 0x1c3); //0x15->0x1c3
 480 +       i2c_WM8960_write(RADCVOL, 0x1c3); //0x16->0x1c3
 481 +       i2c_WM8960_write(PWRMGMT1, 0xfc); //0x19->0xfc
 482 +       i2c_WM8960_write(PWRMGMT2, 0x1e0); //0x1a->0x1e0
 483 +       i2c_WM8960_write(ADCLPATH, 0x108); //0x20->0x108
 484 +       i2c_WM8960_write(ADCRPATH, 0x108); //0x21->0x108
 485 +       i2c_WM8960_write(LEFTMIX1, 0x150); //0x22->0x150
 486 +       i2c_WM8960_write(RIGHTMIX2, 0x150); //0x25->0x150
 487 +       i2c_WM8960_write(BYPASS1, 0x00); //0x2d->0x00
 488 +       i2c_WM8960_write(BYPASS2, 0x00); //0x2e->0x00
 489 +       i2c_WM8960_write(PWRMGMT3, 0x3c); //0x2f->0x3c
 490 +}
 491 +
 492 +void audiohw_bypass(void)
 493 +{
 494 +       int i;
 495 +
 496 +       memset(wm_reg_data, 0 , sizeof(unsigned long)*55);
 497 +       i2c_WM8960_write(RESET, 0x000);    //0x0f(R15)->0x000
 498 +
 499 +       for(i = 0; i < 1000*HZ; i++);
 500 +
 501 +       i2c_WM8960_write(PWRMGMT1, 0xf0); //0x19(R25)->0xf0
 502 +       i2c_WM8960_write(PWRMGMT2, 0x60); //0x1a(R26)->0x60
 503 +       i2c_WM8960_write(PWRMGMT3, 0x3c); //0x2f(R47)->0x3c
 504 +       i2c_WM8960_write(LINV, 0x117); // 0x00(R0)->0x117
 505 +       i2c_WM8960_write(RINV, 0x117); // 0x01(R1)->0x117
 506 +       i2c_WM8960_write(ADCLPATH, 0x108); //0x20(R32)->0x108
 507 +       i2c_WM8960_write(ADCRPATH, 0x108); //0x21(R33)->0x108
 508 +       i2c_WM8960_write(BYPASS1, 0x80); //0x2d(R45)->0x80
 509 +       i2c_WM8960_write(BYPASS2, 0x80); //0x2e(R46)->0x80
 510 +       i2c_WM8960_write(LOUT1, 0x179); // 0x02(R2)->0x179
 511 +       i2c_WM8960_write(ROUT1, 0x179); // 0x03(R3)->0x179
 512 +}
 513 +EXPORT_SYMBOL(audiohw_set_frequency);
 514 +EXPORT_SYMBOL(audiohw_close);
 515 +EXPORT_SYMBOL(audiohw_postinit);
 516 +EXPORT_SYMBOL(audiohw_preinit);
 517 +EXPORT_SYMBOL(audiohw_set_apll);
 518 +EXPORT_SYMBOL(audiohw_codec_exlbk);
 519 +EXPORT_SYMBOL(audiohw_bypass);
 520 +EXPORT_SYMBOL(audiohw_set_lineout_vol);
 521 +EXPORT_SYMBOL(audiohw_set_linein_vol);
 522 +EXPORT_SYMBOL(audiohw_micin);
 523 +EXPORT_SYMBOL(audiohw_mute);
 524 +EXPORT_SYMBOL(audiohw_loopback);
 525 +EXPORT_SYMBOL(audiohw_micboost);
 526 +
 527 +static int codec_wm8960_i2c_probe(struct i2c_client *client, const struct i2c_device_id *id)
 528 +{
 529 +       struct wm8960_data *wm;
 530 +
 531 +printk("*******Enter %s********\n", __func__);
 532 +
 533 +       if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
 534 +               return -EIO;
 535 +
 536 +       wm = devm_kzalloc(&client->dev, sizeof(struct wm8960_data), GFP_KERNEL);
 537 +       if (!wm)
 538 +               return -ENOMEM;
 539 +
 540 +#if defined(CONFIG_ARCH_MT7623)
 541 +       mt_set_gpio_mode(GPIO242, GPIO_MODE_04);
 542 +        mt_set_gpio_mode(GPIO243, GPIO_MODE_04);
 543 +#endif
 544 +       wm->client = client;
 545 +       wm->dev = &client->dev;
 546 +       wm->name = id->name;
 547 +       i2c_set_clientdata(client, wm);
 548 +       wmio = wm;
 549 +
 550 +       memset(wm_reg_data, 0 , sizeof(unsigned long)*55);
 551 +
 552 +       return 0;
 553 +}
 554 +
 555 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,8,0)
 556 +static int codec_wm8960_i2c_remove(struct i2c_client *client)
 557 +#else
 558 +static int __devexit codec_wm8960_i2c_remove(struct i2c_client *client)
 559 +#endif
 560 +{
 561 +       struct wm8960_data *wm = i2c_get_clientdata(client);
 562 +       kfree(wm);
 563 +
 564 +       return 0;
 565 +}
 566 +
 567 +static const struct i2c_device_id wm8960_id[] = {
 568 +       { "codec_wm8960", 0 },
 569 +       {}
 570 +};
 571 +
 572 +static struct i2c_driver codec_wm8960_i2c_driver = {
 573 +       .driver = {
 574 +               .name   = "codec_wm8960"
 575 +       },
 576 +       .probe  = codec_wm8960_i2c_probe,
 577 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,8,0)
 578 +        .remove = codec_wm8960_i2c_remove,
 579 +#else
 580 +       .remove = __devexit_p(codec_wm8960_i2c_remove),
 581 +#endif
 582 +       .id_table = wm8960_id,
 583 +};
 584 +static int __init wm8960_i2c_init(void)
 585 +{
 586 +#if defined(CONFIG_ARCH_MT7623)
 587 +       i2c_register_board_info(1, &i2c_devs1, 1);
 588 +#endif
 589 +       return i2c_add_driver(&codec_wm8960_i2c_driver);;
 590 +}
 591 +
 592 +static void __exit wm8960_i2c_exit(void)
 593 +{
 594 +       i2c_del_driver(&codec_wm8960_i2c_driver);
 595 +}
 596 +
 597 +module_init(wm8960_i2c_init);
 598 +module_exit(wm8960_i2c_exit);
 599 +
 600 +MODULE_AUTHOR("Ryder Lee <ryder.lee@mediatek.com>");
 601 +MODULE_DESCRIPTION("WM8960 I2C client driver");
 602 +MODULE_LICENSE("GPL");
 603 +
 604 --- /dev/null
 605 +++ b/sound/soc/mtk/i2c_wm8960.h
 606 @@ -0,0 +1,288 @@
 607 +/* wm8960.h  --  WM8960 Soc Audio driver */
 608 +#ifndef _WM8960_H
 609 +#define _WM8960_H
 610 +
 611 +#define bool   unsigned char
 612 +#define false 0
 613 +#define true 1
 614 +
 615 +/* volume/balance/treble/bass interdependency */
 616 +#define VOLUME_MIN     -730
 617 +#define VOLUME_MAX     60
 618 +
 619 +
 620 +/* Register addresses and bits */
 621 +#define OUTPUT_MUTED                   0x2f
 622 +#define OUTPUT_0DB                     0x79
 623 +
 624 +#define LINV                           0x00
 625 +#define LINV_IPVU                      (1 << 8)  /* FIXME */
 626 +#define LINV_LINMUTE                   (1 << 7)
 627 +#define LINV_LIZC                       (1 << 6)
 628 +#define LINV_LINVOL(x)                 ((x) & 0x3f)
 629 +
 630 +#define RINV                           0x01
 631 +#define RINV_IPVU                      (1 << 8) /* FIXME */
 632 +#define RINV_RINMUTE                   (1 << 7)
 633 +#define RINV_RIZC                      (1 << 6)
 634 +#define RINV_RINVOL(x)                 ((x) & 0x3f)
 635 +
 636 +#define LOUT1                          0x02
 637 +#define LOUT1_LO1VU                    (1 << 8)
 638 +#define LOUT1_LO1ZC                    (1 << 7)
 639 +#define LOUT1_LOUT1VOL(x)              ((x) & 0x7f)
 640 +
 641 +#define ROUT1                          0x03
 642 +#define ROUT1_RO1VU                    (1 << 8)
 643 +#define ROUT1_RO1ZC                    (1 << 7)
 644 +#define ROUT1_ROUT1VOL(x)              ((x) & 0x7f)
 645 +
 646 +#define CLOCKING1                      0x04  /* FIXME */
 647 +#define CLOCKING1_ADCDIV(x)            (((x) & 0x7) << 6)
 648 +#define CLOCKING1_DACDIV(x)            (((x) & 0x7) << 3)
 649 +#define CLOCKING1_SYSCLKDIV_1          (0 << 1)
 650 +#define CLOCKING1_SYSCLKDIV_2          (2 << 1)
 651 +#define CLOCKING1_CLKSEL_MCLK          (0 << 0)
 652 +#define CLOCKING1_CLKSEL_PLL           (1 << 0)
 653 +
 654 +#define DACCTRL1                       0x05
 655 +#define DACCTRL1_DATTENUATE             (1 << 7)
 656 +#define DACCTRL1_DACMU                 (1 << 3)
 657 +#define DACCTRL1_DEEMPH_48             (3 << 1)
 658 +#define DACCTRL1_DEEMPH_44             (2 << 1)
 659 +#define DACCTRL1_DEEMPH_32             (1 << 1)
 660 +#define DACCTRL1_DEEMPH_NONE           (0 << 1)
 661 +#define DACCTRL1_DEEMPH(x)             ((x) & (0x3 << 1))
 662 +
 663 +#define DACCTRL2                       0x06
 664 +
 665 +#define AINTFCE1                       0x07
 666 +#define AINTFCE1_BCLKINV               (1 << 7)
 667 +#define AINTFCE1_MS                    (1 << 6)
 668 +#define AINTFCE1_LRSWAP                (1 << 5)
 669 +#define AINTFCE1_LRP                   (1 << 4)
 670 +#define AINTFCE1_WL_32                 (3 << 2)
 671 +#define AINTFCE1_WL_24                  (2 << 2)
 672 +#define AINTFCE1_WL_20                  (1 << 2)
 673 +#define AINTFCE1_WL_16                 (0 << 2)
 674 +#define AINTFCE1_WL(x)                 (((x) & 0x3) << 2)
 675 +#define AINTFCE1_FORMAT_DSP             (3 << 0)
 676 +#define AINTFCE1_FORMAT_I2S             (2 << 0)
 677 +#define AINTFCE1_FORMAT_LJUST           (1 << 0)
 678 +#define AINTFCE1_FORMAT_RJUST          (0 << 0)
 679 +#define AINTFCE1_FORMAT(x)             ((x) & 0x3)
 680 +
 681 +/* FIXME */
 682 +#define CLOCKING2                      0x08
 683 +#define CLOCKING2_DCLKDIV(x)            (((x) & 0x7) << 6)
 684 +#define CLOCKING2_BCLKDIV(x)           (((x) & 0xf) << 0)
 685 +
 686 +#define AINTFCE2                       0x09
 687 +#define AINTFCE2_ALRCGPIO_ALRC         (0 << 6)
 688 +#define        AINTFCE2_ALRCGPIO_GPIO          (1 << 6)
 689 +#define        AINTFCE2_LOOPBACK               (1 << 0)
 690 +
 691 +#define LEFTGAIN                       0x0a
 692 +#define LEFTGAIN_LDVU                   (1 << 8)
 693 +#define LEFTGAIN_LDACVOL(x)            ((x) & 0xff)
 694 +
 695 +#define RIGHTGAIN                      0x0b
 696 +#define RIGHTGAIN_RDVU                  (1 << 8)
 697 +#define RIGHTGAIN_RDACVOL(x)           ((x) & 0xff)
 698 +
 699 +#define RESET                          0x0f
 700 +#define RESET_RESET                    0x000
 701 +
 702 +#define ALC1                           0x11
 703 +#define ALC1_ALCOFF                    (0x0 << 7)
 704 +#define        ALC1_ALCRONLY                   (0x1 << 7)
 705 +#define ALC1_ALCLONLY                  (0x2 << 7)
 706 +#define ALC1_ALCSTEREO                 (0x3 << 7)
 707 +#define ALC1_ALCSEL(x)                 (((x) & 0x3) << 7)
 708 +#define ALC1_SET_MAXGAIN(x)            ((x & 0x7) << 4)
 709 +#define ALC1_GET_MAXGAIN(x)            ((x) & (0x7 << 4))
 710 +#define ALC1_ALCL(x)                   ((x) & 0x0f)
 711 +
 712 +#define ALC2                           0x12
 713 +#define ALC2_MINGAIN(x)                ((x & 0x7) << 4)
 714 +#define ALC2_HLD(x)                    ((x) & 0x0f)
 715 +
 716 +#define ALC3                           0x13
 717 +#define ALC3_SET_DCY(x)                        ((x & 0x0f) << 4)
 718 +#define ALC3_GET_DCY(x)                        ((x) & (0x0f << 4))
 719 +#define ALC3_ATK(x)                    ((x) & 0x0f)
 720 +
 721 +#define NOISEGATE                      0x14
 722 +#define NOISEGATE_SET_NGTH(x)          ((x & 0x1f) << 3)
 723 +#define NOISEGATE_GET_NGTH(x)          ((x) & (0x1f << 3))
 724 +#define NOISEGATE_NGAT_ENABLE          1
 725 +
 726 +#define LADCVOL                                0x15
 727 +#define LADCVOL_LAVU_EN                        (1 << 8)
 728 +#define LADCVOL_LADCVOL(x)             ((x) & 0x0ff)
 729 +
 730 +#define RADCVOL                                0x16
 731 +#define RADCVOL_RAVU_EN                        (1 << 8)
 732 +#define RADCVOL_RADCVOL(x)             ((x) & 0x0ff)
 733 +
 734 +#define ADDITIONAL1                    0x17
 735 +#define ADDITIONAL1_TSDEN               (1 << 8)
 736 +#define ADDITIONAL1_VSEL_LOWEST        (0 << 6)
 737 +#define ADDITIONAL1_VSEL_LOW           (1 << 6)
 738 +#define ADDITIONAL1_VSEL_DEFAULT2      (2 << 6)
 739 +#define ADDITIONAL1_VSEL_DEFAULT       (3 << 6)
 740 +#define ADDITIONAL1_VSEL(x)            (((x) & 0x3) << 6)
 741 +#define ADDITIONAL1_DMONOMIX_STEREO    (0 << 4)
 742 +#define ADDITIONAL1_DMONOMIX_MONO      (1 << 4)
 743 +#define ADDITIONAL1_DATSEL(x)          (((x) & 0x3) << 2)
 744 +#define ADDITIONAL1_TOCLKSEL            (1 << 1)
 745 +#define ADDITIONAL1_TOEN                (1 << 0)
 746 +
 747 +#define ADDITIONAL2                    0x18
 748 +#define ADDITIONAL2_HPSWEN              (1 << 6)
 749 +#define ADDITIONAL2_HPSWPOL             (1 << 5)
 750 +#define ADDITIONAL2_TRIS                (1 << 3)
 751 +#define ADDITIONAL2_LRCM_ON            (1 << 2)
 752 +
 753 +#define PWRMGMT1                       0x19
 754 +#define PWRMGMT1_VMIDSEL_DISABLED      (0 << 7)
 755 +#define PWRMGMT1_VMIDSEL_50K           (1 << 7)
 756 +#define PWRMGMT1_VMIDSEL_250K          (2 << 7)
 757 +#define PWRMGMT1_VMIDSEL_5K            (3 << 7)
 758 +#define PWRMGMT1_VREF                   (1 << 6)
 759 +#define PWRMGMT1_AINL                   (1 << 5)
 760 +#define PWRMGMT1_AINR                   (1 << 4)
 761 +#define PWRMGMT1_ADCL                   (1 << 3)
 762 +#define PWRMGMT1_ADCR                   (1 << 2)
 763 +#define PWRMGMT1_MICB                   (1 << 1)
 764 +#define PWRMGMT1_DIGENB                 (1 << 0)
 765 +
 766 +#define PWRMGMT2                       0x1a
 767 +#define PWRMGMT2_DACL                  (1 << 8)
 768 +#define PWRMGMT2_DACR                   (1 << 7)
 769 +#define PWRMGMT2_LOUT1                  (1 << 6)
 770 +#define PWRMGMT2_ROUT1                  (1 << 5)
 771 +#define PWRMGMT2_SPKL                   (1 << 4)
 772 +#define PWRMGMT2_SPKR                   (1 << 3)
 773 +#define PWRMGMT2_OUT3                   (1 << 1)
 774 +#define PWRMGMT2_PLL_EN                 (1 << 0)
 775 +
 776 +#define ADDITIONAL3                    0x1b
 777 +#define ADDITIONAL3_VROI               (1 << 6)
 778 +#define ADDITIONAL3_OUT3CAP             (1 << 3)
 779 +#define ADDITIONAL3_ADC_ALC_SR(x)       ((x) & 0x7)
 780 +
 781 +#define ANTIPOP1                       0x1c
 782 +#define ANTIPOP2                       0x1d
 783 +
 784 +#define ADCLPATH                       0x20
 785 +#define ADCLPATH_LMN1                  (1 << 8)
 786 +#define ADCLPATH_LMP3                   (1 << 7)
 787 +#define ADCLPATH_LMP2                   (1 << 6)
 788 +#define ADCLPATH_LMICBOOST_29DB         (0x3 << 4)
 789 +#define ADCLPATH_LMICBOOST_20DB         (0x2 << 4)
 790 +#define ADCLPATH_LMICBOOST_13DB         (0x1 << 4)
 791 +#define ADCLPATH_SET_LMICBOOST(x)       ((x & 0x3) << 4)
 792 +#define ADCLPATH_LMIC2B                 (1 << 3)
 793 +
 794 +
 795 +#define ADCRPATH                       0x21
 796 +#define ADCRPATH_RMN1                  (1 << 8)
 797 +#define ADCRPATH_RMP3                   (1 << 7)
 798 +#define ADCRPATH_RMP2                   (1 << 6)
 799 +#define ADCRPATH_RMICBOOST_29DB         (0x3 << 4)
 800 +#define ADCRPATH_RMICBOOST_20DB         (0x2 << 4)
 801 +#define ADCRPATH_RMICBOOST_13DB         (0x1 << 4)
 802 +#define ADCRPATH_SET_RMICBOOST(x)       ((x & 0x3) << 4)
 803 +#define ADCRPATH_RMIC2B                 (1 << 3)
 804 +
 805 +
 806 +#define LEFTMIX1                       0x22
 807 +#define LEFTMIX1_LD2LO                 (1 << 8)
 808 +#define LEFTMIX1_LI2LO                  (1 << 7)
 809 +#define LEFTMIX1_LI2LO_DEFAULT          (5 << 4)
 810 +#define LEFTMIX1_LI2LOVOL(x)            (((x) & 0x7) << 4)
 811 +
 812 +#define RIGHTMIX2                      0x25
 813 +#define RIGHTMIX2_RD2RO                (1 << 8)
 814 +#define RIGHTMIX2_RI2RO                 (1 << 7)
 815 +#define RIGHTMIX2_RI2RO_DEFAULT         (5 << 4)
 816 +#define RIGHTMIX2_RI2ROVOL(x)           (((x) & 0x7) << 4)
 817 +
 818 +#define MONOMIX1                       0x26
 819 +#define MONOMIX1_L2MO                  (1 << 7)
 820 +
 821 +#define MONOMIX2                       0x27
 822 +#define MONOMIX2_R2MO                  (1 << 7)
 823 +
 824 +#define LSPK                           0x28
 825 +#define LSPK_SPKLVU                    (1 << 8)
 826 +#define LSPK_SPKLZC                     (1 << 7)
 827 +#define LSPK_SPKLVOL(x)                 ((x) & 0x7f)
 828 +
 829 +#define RSPK                           0x29
 830 +#define RSPK_SPKRVU                    (1 << 8)
 831 +#define RSPK_SPKRZC                     (1 << 7)
 832 +#define RSPK_SPKRVOL(x)                 ((x) & 0x7f)
 833 +
 834 +#define OUT3V                          0x2a
 835 +#define LINBMIX                                0x2b
 836 +#define RINBMIX                                0x2c
 837 +#define BYPASS1                        0x2d
 838 +#define BYPASS2                                0x2e
 839 +
 840 +#define PWRMGMT3                       0x2f
 841 +#define PWRMGMT3_LMIC                  (1<<5)
 842 +#define PWRMGMT3_RMIC                   (1<<4)
 843 +#define PWRMGMT3_LOMIX                  (1<<3)
 844 +#define PWRMGMT3_ROMIX                  (1<<2)
 845 +
 846 +#define ADDITIONAL4                    0x30
 847 +
 848 +#define CLASSDCTRL1                    0x31
 849 +#define CLASSDCTRL1_OP_OFF             (0<<6)
 850 +#define CLASSDCTRL1_OP_LSPK            (1<<6)
 851 +#define CLASSDCTRL1_OP_RSPK            (2<<6)
 852 +#define CLASSDCTRL1_OP_LRSPK           (3<<6)
 853 +
 854 +#define CLASSDCTRL3                    0x33
 855 +
 856 +#define PLL1                           0x34
 857 +#define PLL1_OPCLKDIV_1                        (0<<6)
 858 +#define PLL1_OPCLKDIV_2                        (1<<6)
 859 +#define PLL1_OPCLKDIV_3                        (2<<6)
 860 +#define PLL1_OPCLKDIV_4                        (3<<6)
 861 +#define        PLL1_OPCLKDIV_5p5               (4<<6)
 862 +#define        PLL1_OPCLKDIV_6                 (5<<6)
 863 +#define PLL1_SDM_INTERGER              (0<<5)
 864 +#define PLL1_SDM_FRACTIONAL            (1<<5)
 865 +#define PLL1_PLLPRESCALE_1             (0<<4)
 866 +#define PLL1_PLLPRESCALE_2             (1<<4)
 867 +#define PLL1_PLLN(x)                   ((x) & 0xf)
 868 +
 869 +#define PLL2                           0x35
 870 +#define        PLL2_PLLK_23_16(x)              ((x) & 0x1ff)
 871 +
 872 +#define PLL3                           0x36
 873 +#define PLL3_PLLK_15_8(x)              ((x) & 0x1ff)
 874 +
 875 +#define PLL4                           0x37
 876 +#define PLL4_PLLK_7_0(x)               ((x) & 0x1ff)
 877 +
 878 +/* codec API */
 879 +void audiohw_preinit(void);
 880 +int audiohw_postinit(int bSlave, int AIn, int AOut, int pll_en, int wordLen24b);
 881 +void audiohw_close(void);
 882 +void audiohw_set_frequency(int fsel, int pll_en);
 883 +void audiohw_mute(bool mute);
 884 +void audiohw_micboost(int boostgain);
 885 +void audiohw_micin(int enableMic);
 886 +void audiohw_set_apll(int srate);
 887 +int audiohw_set_lineout_vol(int Aout, int vol_l, int vol_r);
 888 +int audiohw_set_linein_vol(int vol_l, int vol_r);
 889 +void audiohw_mute( bool mute);
 890 +void audiohw_loopback(int fsel);
 891 +void audiohw_codec_exlbk(void);
 892 +void audiohw_bypass(void);
 893 +
 894 +#endif /* _WM875x_H */
 895 --- /dev/null
 896 +++ b/sound/soc/mtk/i2s_ctrl.c
 897 @@ -0,0 +1,3524 @@
 898 +#include <linux/init.h>
 899 +#include <linux/version.h>
 900 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
 901 +#include <linux/sched.h>
 902 +#endif
 903 +#include <linux/module.h>
 904 +#include <linux/kernel.h> /* _printk() */
 905 +#include <linux/slab.h> /* kmalloc() */
 906 +#include <linux/fs.h> /* everything... */
 907 +#include <linux/errno.h> /* error codes */
 908 +#include <linux/types.h> /* size_t */
 909 +#include <linux/proc_fs.h>
 910 +#include <linux/fcntl.h> /* O_ACCMODE */
 911 +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,10,14)
 912 +#include <asm/system.h> /* cli(), *_flags */
 913 +#endif
 914 +#include <asm/uaccess.h> /* copy_from/to_user */
 915 +#include <linux/interrupt.h>
 916 +#include <linux/mm.h>
 917 +#include <linux/mm_types.h>
 918 +#include <linux/pci.h>
 919 +#include <linux/delay.h>
 920 +#include "ralink_gdma.h"
 921 +#if defined(CONFIG_I2S_WITH_AEC)
 922 +#include "../aec/aec_api.h"
 923 +#endif
 924 +
 925 +#ifdef  CONFIG_DEVFS_FS
 926 +#include <linux/devfs_fs_kernel.h>
 927 +static devfs_handle_t devfs_handle;
 928 +#endif
 929 +
 930 +#include "i2s_ctrl.h"
 931 +
 932 +#if defined(CONFIG_SND_MT76XX_SOC)
 933 +#include <sound/soc/mtk/mt76xx_machine.h>
 934 +#endif
 935 +
 936 +#if defined(CONFIG_I2S_WM8750)
 937 +#include "../codec/i2c_wm8750.h"
 938 +#endif
 939 +#if defined(CONFIG_I2S_WM8751)
 940 +#include "../codec/i2c_wm8751.h"
 941 +#endif
 942 +#if defined(CONFIG_I2S_WM8960)
 943 +#include "i2c_wm8960.h"
 944 +#endif
 945 +
 946 +static int i2sdrv_major =  191;
 947 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
 948 +#else
 949 +static struct class *i2smodule_class;
 950 +#endif
 951 +
 952 +static int _printk(char *fmt, ...)
 953 +{
 954 +       return 0;
 955 +}
 956 +
 957 +/* external functions declarations */
 958 +#if defined(CONFIG_I2S_WM8960)
 959 +extern void audiohw_set_frequency(int fsel, int codec_pll_en);
 960 +void audiohw_set_apll(int srate);
 961 +#elif defined(CONFIG_I2S_WM8750)||defined(CONFIG_I2S_WM8751)
 962 +extern void audiohw_set_frequency(int fsel);
 963 +#endif
 964 +#if defined(CONFIG_I2S_WM8960)||defined(CONFIG_I2S_WM8750)||defined(CONFIG_I2S_WM8751)
 965 +extern int audiohw_set_lineout_vol(int Aout, int vol_l, int vol_r);
 966 +extern int audiohw_set_master_vol(int vol_l, int vol_r);
 967 +extern int audiohw_set_linein_vol(int vol_l, int vol_r);
 968 +#endif
 969 +
 970 +extern void audiohw_micboost(int boostgain);
 971 +
 972 +extern int GdmaI2sTx(uint32_t Src, uint32_t Dst, uint8_t TxNo, uint16_t TransCount,
 973 +                void (*DoneIntCallback)(uint32_t data),
 974 +                void (*UnMaskIntCallback)(uint32_t data));
 975 +
 976 +extern int GdmaI2sRx(uint32_t Src, uint32_t Dst, uint8_t RxNo, uint16_t TransCount,
 977 +                void (*DoneIntCallback)(uint32_t data),
 978 +                void (*UnMaskIntCallback)(uint32_t data));
 979 +
 980 +extern int GdmaMaskChannel(uint32_t ChNum);
 981 +
 982 +extern int GdmaUnMaskChannel(uint32_t ChNum);
 983 +
 984 +/* internal functions declarations */
 985 +irqreturn_t i2s_irq_isr(int irq, void *irqaction);
 986 +int i2s_debug_cmd(unsigned int cmd, unsigned long arg);
 987 +
 988 +/* forward declarations for _fops */
 989 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
 990 +static long i2s_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
 991 +#else
 992 +static int i2s_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg);
 993 +#endif
 994 +static int i2s_mmap(struct file *file, struct vm_area_struct *vma);
 995 +static int i2s_open(struct inode *inode, struct file *file);
 996 +static int i2s_release(struct inode *inode, struct file *file);
 997 +int i2s_mmap_alloc(unsigned long size);
 998 +int i2s_mmap_remap(struct vm_area_struct *vma, unsigned long size);
 999 +
1000 +/* global varable definitions */
1001 +i2s_config_type i2s_config;
1002 +i2s_status_type i2s_status;
1003 +i2s_config_type* pi2s_config = &i2s_config;;
1004 +i2s_status_type* pi2s_status = &i2s_status;;
1005 +
1006 +static inline long
1007 +ugly_hack_sleep_on_timeout(wait_queue_head_t *q, long timeout)
1008 +{
1009 +       unsigned long flags;
1010 +       wait_queue_t wait;
1011 +
1012 +       init_waitqueue_entry(&wait, current);
1013 +
1014 +       __set_current_state(TASK_INTERRUPTIBLE);
1015 +       spin_lock_irqsave(&q->lock, flags);
1016 +       __add_wait_queue(q, &wait);
1017 +       spin_unlock(&q->lock);
1018 +
1019 +       timeout = schedule_timeout(timeout);
1020 +
1021 +       spin_lock_irq(&q->lock);
1022 +       __remove_wait_queue(q, &wait);
1023 +       spin_unlock_irqrestore(&q->lock, flags);
1024 +
1025 +       return timeout;
1026 +}
1027 +
1028 +#define interruptible_sleep_on(x) \
1029 +       ugly_hack_sleep_on_timeout(x, MAX_SCHEDULE_TIMEOUT);
1030 +
1031 +
1032 +#if defined(ARM_ARCH)
1033 +static dma_addr_t i2s_txdma_addr0, i2s_txdma_addr1;
1034 +static dma_addr_t i2s_rxdma_addr0, i2s_rxdma_addr1;
1035 +#define I2S_TX_FIFO_WREG_PHY (I2S_TX_FIFO_WREG & 0x1FFFFFFF)
1036 +#define I2S_RX_FIFO_RREG_PHY (I2S_RX_FIFO_RREG & 0x1FFFFFFF)
1037 +#else
1038 +static dma_addr_t i2s_txdma_addr, i2s_rxdma_addr;
1039 +#endif
1040 +static dma_addr_t i2s_mmap_addr[MAX_I2S_PAGE*2];
1041 +                                     /* 8khz 11.025khz 12khz  16khz 22.05khz 24Khz  32khz 44.1khz 48khz 88.2khz 96khz*/
1042 +unsigned long i2s_inclk_15p625Mhz[11] = {60<<8, 43<<8,  40<<8, 30<<8, 21<<8,  19<<8, 14<<8, 10<<8, 9<<8,  7<<8,  4<<8};
1043 +unsigned long i2s_exclk_12p288Mhz[11] = {47<<8, 34<<8,  31<<8, 23<<8, 16<<8,  15<<8, 11<<8,  8<<8, 7<<8,  5<<8,  3<<8};
1044 +unsigned long i2s_exclk_12Mhz[11]     = {46<<8, 33<<8,  30<<8, 22<<8, 16<<8,  15<<8, 11<<8,  8<<8, 7<<8,  5<<8,  3<<8};
1045 +#if defined(CONFIG_I2S_WM8750) || defined(CONFIG_SND_SOC_WM8750)
1046 +                                       /* 8k  11.025k  12k   16k  22.05k  24k  32k   44.1k   48k  88.2k   96k*/
1047 +unsigned long i2s_codec_12p288Mhz[11]  = {0x0C,  0x00, 0x10, 0x14,  0x38, 0x38, 0x18,  0x20, 0x00,  0x00, 0x1C};
1048 +unsigned long i2s_codec_12Mhz[11]      = {0x0C,  0x32, 0x10, 0x14,  0x37, 0x38, 0x18,  0x22, 0x00,  0x3E, 0x1C};
1049 +unsigned long i2s_codec_24p576Mhz[11]  = {0x4C,  0x00, 0x50, 0x54,  0x00, 0x78, 0x58,  0x00, 0x40,  0x00, 0x5C};
1050 +unsigned long i2s_codec_18p432Mhz[11]  = {0x0e,  0x32, 0x12, 0x16,  0x36, 0x3a, 0x1a,  0x22, 0x02,  0x3e, 0x1e};
1051 +#endif
1052 +#if defined(CONFIG_I2S_WM8751) || defined(CONFIG_SND_SOC_WM8751)
1053 +unsigned long i2s_codec_12p288Mhz[11]  = {0x04,  0x00, 0x10, 0x14,  0x38, 0x38, 0x18,  0x20, 0x00,  0x00, 0x1C};
1054 +unsigned long i2s_codec_12Mhz[11]      = {0x04,  0x32, 0x10, 0x14,  0x37, 0x38, 0x18,  0x22, 0x00,  0x3E, 0x1C};
1055 +#endif
1056 +#if defined(CONFIG_I2S_WM8960) || defined(CONFIG_SND_SOC_WM8960)
1057 +unsigned long i2s_codec_12p288Mhz[11]  = {0x36,  0x24, 0x24, 0x1b,  0x12, 0x12, 0x09,  0x00, 0x00,  0x00, 0x00};
1058 +unsigned long i2s_codec_12Mhz[11]      = {0x36,  0x24, 0x24, 0x1b,  0x12, 0x12, 0x09,  0x00, 0x00,  0x00, 0x00};
1059 +#endif
1060 +EXPORT_SYMBOL(i2s_codec_12p288Mhz);
1061 +EXPORT_SYMBOL(i2s_codec_12Mhz);
1062 +
1063 +#if defined(CONFIG_RALINK_RT6855A)
1064 +                                  /* 8K  11.025k  12k   16k  22.05k   24k   32k  44.1K   48k  88.2k  96k */
1065 +unsigned long i2s_inclk_int[11]  = {  97,    70,    65,   48,    35,    32,   24,   17,    16,   12,    8};
1066 +unsigned long i2s_inclk_comp[11] = { 336,   441,    53,  424,   220,   282,  212,  366,   141,  185,   70};
1067 +#elif defined (CONFIG_RALINK_MT7621)
1068 +#ifdef MT7621_ASIC_BOARD
1069 +#if defined (CONFIG_I2S_MCLK_12P288MHZ)
1070 +unsigned long i2s_inclk_int[11]  = { 576,   384,    0,   288,   192,   192,  144,   96,    96,   48,   48};
1071 +unsigned long i2s_inclk_comp[11] = {   0,     0,    0,     0,     0,     0,    0,    0,     0,    0,    0};
1072 +#elif defined(CONFIG_I2S_MCLK_12MHZ)
1073 +unsigned long i2s_inclk_int[11] =  {1171,   850,    0,   585,   425,   390,  292,  212,   195,   106,   97};
1074 +unsigned long i2s_inclk_comp[11] = { 448,   174,    0,   480,    87,   320,  496,  299,   160,   149,  336};
1075 +#endif
1076 +#else //MT7621_FPGA_BOARD
1077 +unsigned long i2s_inclk_int[11] =  { 529,   384,    0,   264,   192,   176,  132,   96,    88,    48,   44};
1078 +unsigned long i2s_inclk_comp[11] = { 102,     0,    0,   307,     0,   204,  153,    0,   102,     0,   51};
1079 +#endif
1080 +#elif defined (CONFIG_RALINK_MT7628)
1081 +#ifdef MT7628_ASIC_BOARD
1082 +                                      /* 8K  11.025k 12k  16k 22.05k 24k  32k 44.1K  48k  88.2k 96k  176k 192k */
1083 +unsigned long i2s_inclk_int_16bit[13] = {937,  680,   0,  468,  340, 312, 234, 170,  156,   85, 78,   42,  39};
1084 +unsigned long i2s_inclk_comp_16bit[13]= {256,  139,   0,  384,   69, 256, 192,  34,  128,   17, 64,  267,  32};
1085 +unsigned long i2s_inclk_int_24bit[13] = {625,  404,   0,  312,  226, 208, 156, 113,  104,   56, 52,   28,  26};
1086 +unsigned long i2s_inclk_comp_24bit[13]= {  0,  404,   0,  256,  387, 170, 128, 193,   85,  352, 42,  176,  21};
1087 +#else
1088 +                                     /* 8K  11.025k 12k  16k 22.05k 24k  32k 44.1K  48k  88.2k 96k  176k 192k */
1089 +unsigned long i2s_inclk_int_16bit[13] = {468,  340,   0,  234,  170, 156, 117,  85,   78,   42, 39,   21,  19};
1090 +unsigned long i2s_inclk_comp_16bit[13]= {384,   69,   0,  192,   34, 128,  96,  17,   64,  264, 32,  133, 272};
1091 +unsigned long i2s_inclk_int_24bit[13] = {312,  202,   0,  156,  113, 104,  78,  56,   52,   28, 26,   14,  13};
1092 +unsigned long i2s_inclk_comp_24bit[13]= {256,  202,   0,  128,  193,  85,  64, 352,   42,  176,  21,  88,  10};
1093 +#endif
1094 +#elif defined (CONFIG_ARCH_MT7623)
1095 +#if defined MT7623_ASIC_BOARD
1096 +                                     /* 8K  11.025k 12k  16k 22.05k 24k  32k 44.1K  48k  88.2k 96k  176k 192k */
1097 +unsigned long i2s_inclk_int_16bit[13] = {576,  384,   0,  288,  192, 192, 144,  96,  96,    48, 48,   24,  24};
1098 +unsigned long i2s_inclk_comp_16bit[13]= { 0,    0,    0,    0,   0,    0,   0,   0,   0,     0,  0,    0,   0};
1099 +unsigned long i2s_inclk_int_24bit[13] = {384,  256,   0,  192,  128, 128,  96,  64,  64,    32, 32,   16,  16};
1100 +unsigned long i2s_inclk_comp_24bit[13]= { 0,    0,    0,    0,   0,    0,   0,   0,   0,     0,  0,    0,   0};
1101 +#else
1102 +                                     /* 8K  11.025k 12k  16k 22.05k 24k  32k 44.1K  48k  88.2k 96k  176k 192k */
1103 +unsigned long i2s_inclk_int_16bit[13] = {72,   48,    0,   36,  24,   24,  18,  12,   12,    6,  6,    3,   3};
1104 +unsigned long i2s_inclk_comp_16bit[13]= { 0,    0,    0,    0,   0,    0,   0,   0,    0,    0,  0,    0,   0};
1105 +unsigned long i2s_inclk_int_24bit[13] = {48,   32,    0,   24,  16,   16,  12,   8,    8,    4,  4,    2,   2};
1106 +unsigned long i2s_inclk_comp_24bit[13]= { 0,    0,    0,    0,   0,    0,   0,   0,    0,    0,  0,    0,   0};
1107 +#endif
1108 +#else
1109 +                                 /* 8K  11.025k 12k  16k  22.05k  24k  32k  44.1K  48k  88.2k  96k */
1110 +unsigned long i2s_inclk_int[11]  = { 78,    56,   52,  39,   28,    26,  19,   14,   13,   9,    6};
1111 +unsigned long i2s_inclk_comp[11] = { 64,   352,   42,  32,  176,    21, 272,   88,   10, 455,  261};
1112 +#endif
1113 +
1114 +#if defined(CONFIG_I2S_WITH_AEC)
1115 +aecFuncTbl_t *aecFuncP;
1116 +#endif
1117 +/* USB mode 22.05Khz register value in datasheet is 0x36 but will cause slow clock, 0x37 is correct value */
1118 +/* USB mode 44.1Khz register value in datasheet is 0x22 but will cause slow clock, 0x23 is correct value */
1119 +
1120 +struct tasklet_struct i2s_tx_tasklet;
1121 +struct tasklet_struct i2s_rx_tasklet;
1122 +EXPORT_SYMBOL(i2s_tx_tasklet);
1123 +EXPORT_SYMBOL(i2s_rx_tasklet);
1124 +
1125 +char test_buf[I2S_PAGE_SIZE];
1126 +char test_buf_1[I2S_PAGE_SIZE];
1127 +char test_buf_2[I2S_PAGE_SIZE];
1128 +
1129 +static const struct file_operations i2s_fops = {
1130 +       owner           : THIS_MODULE,
1131 +       mmap            : i2s_mmap,
1132 +       open            : i2s_open,
1133 +       release         : i2s_release,
1134 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
1135 +       unlocked_ioctl:     i2s_ioctl,
1136 +#else
1137 +       ioctl           : i2s_ioctl,
1138 +#endif
1139 +};
1140 +
1141 +int __init i2s_mod_init(void)
1142 +{
1143 +       int result;
1144 +
1145 +       _printk("******* i2s module init **********\n");
1146 +       /* register device with kernel */
1147 +#ifdef  CONFIG_DEVFS_FS
1148 +       if(devfs_register_chrdev(i2sdrv_major, I2SDRV_DEVNAME , &i2s_fops)) {
1149 +               _printk(KERN_WARNING " i2s: can't create device node - %s\n", I2SDRV_DEVNAME);
1150 +               return -EIO;
1151 +       }
1152 +
1153 +       devfs_handle = devfs_register(NULL, I2SDRV_DEVNAME, DEVFS_FL_DEFAULT, i2sdrv_major, 0,
1154 +           S_IFCHR | S_IRUGO | S_IWUGO, &i2s_fops, NULL);
1155 +#else
1156 +       result = register_chrdev(i2sdrv_major, I2SDRV_DEVNAME, &i2s_fops);
1157 +       if (result < 0) {
1158 +               _printk(KERN_WARNING "i2s: can't get major %d\n",i2sdrv_major);
1159 +               return result;
1160 +       }
1161 +
1162 +       if (i2sdrv_major == 0) {
1163 +               i2sdrv_major = result; /* dynamic */
1164 +       }
1165 +#endif
1166 +
1167 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
1168 +#else
1169 +       i2smodule_class=class_create(THIS_MODULE, I2SDRV_DEVNAME);
1170 +       if (IS_ERR(i2smodule_class))
1171 +               return -EFAULT;
1172 +       device_create(i2smodule_class, NULL, MKDEV(i2sdrv_major, 0), I2SDRV_DEVNAME);
1173 +#endif
1174 +
1175 +#if defined(CONFIG_I2S_WITH_AEC)
1176 +       _printk("AEC FuncP init \n");
1177 +       /*Add by mtk04880*/
1178 +       aecFuncP = kmalloc(sizeof(aecFuncTbl_t), GFP_KERNEL);
1179 +       /*If aecFuncP cannot request memory,it will be ignored in I2S module. Since AEC & I2S are independent
1180 +        * when AEC module is inserted,It will return err message (but I2S will keep running without AEC support)
1181 +        * */
1182 +       if(aecFuncP){
1183 +               memset(aecFuncP,0,sizeof(aecFuncTbl_t));
1184 +       }
1185 +#endif
1186 +
1187 +       return 0;
1188 +}
1189 +
1190 +void i2s_mod_exit(void)
1191 +{
1192 +       _printk("************ i2s module exit *************\n");
1193 +#ifdef  CONFIG_DEVFS_FS
1194 +       devfs_unregister_chrdev(i2sdrv_major, I2SDRV_DEVNAME);
1195 +       devfs_unregister(devfs_handle);
1196 +#else
1197 +       unregister_chrdev(i2sdrv_major, I2SDRV_DEVNAME);
1198 +#endif
1199 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
1200 +#else
1201 +       device_destroy(i2smodule_class,MKDEV(i2sdrv_major, 0));
1202 +       class_destroy(i2smodule_class);
1203 +#endif
1204 +       return ;
1205 +}
1206 +
1207 +
1208 +int i2s_open(struct inode *inode, struct file *filp)
1209 +{
1210 +#if defined(I2S_HW_INTERRUPT_EN)&&(I2S_SW_IRQ_EN)
1211 +       int Ret;
1212 +#endif
1213 +       int minor = iminor(inode);
1214 +
1215 +       if (minor >= I2S_MAX_DEV)
1216 +               return -ENODEV;
1217 +
1218 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
1219 +       MOD_INC_USE_COUNT;
1220 +#else
1221 +       try_module_get(THIS_MODULE);
1222 +#endif
1223 +
1224 +       if (filp->f_flags & O_NONBLOCK) {
1225 +               MSG("filep->f_flags O_NONBLOCK set\n");
1226 +               return -EAGAIN;
1227 +       }
1228 +
1229 +       /* set i2s_config */
1230 +       filp->private_data = pi2s_config;
1231 +       memset(pi2s_config, 0, sizeof(i2s_config_type));
1232 +#ifdef I2S_STATISTIC
1233 +       memset(pi2s_status, 0, sizeof(i2s_status_type));
1234 +#endif
1235 +       i2s_param_init(pi2s_config);
1236 +
1237 +#if defined(I2S_HW_INTERRUPT_EN)&&(I2S_SW_IRQ_EN)
1238 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
1239 +       Ret = request_irq(SURFBOARDINT_I2S, i2s_irq_isr, IRQF_DISABLED, "Ralink_I2S", NULL);
1240 +#else
1241 +       Ret = request_irq(SURFBOARDINT_I2S, i2s_irq_isr, SA_INTERRUPT, "Ralink_I2S", NULL);
1242 +#endif
1243 +
1244 +       if(Ret){
1245 +               MSG("IRQ %d is not free.\n", SURFBOARDINT_I2S);
1246 +               i2s_release(inode, filp);
1247 +               return -1;
1248 +       }
1249 +#endif
1250 +
1251 +       init_waitqueue_head(&(pi2s_config->i2s_tx_qh));
1252 +       init_waitqueue_head(&(pi2s_config->i2s_rx_qh));
1253 +       spin_lock_init(&pi2s_config->lock);
1254 +
1255 +       return 0;
1256 +}
1257 +
1258 +
1259 +static int i2s_release(struct inode *inode, struct file *filp)
1260 +{
1261 +       i2s_config_type* ptri2s_config;
1262 +
1263 +       /* decrement usage count */
1264 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
1265 +       MOD_DEC_USE_COUNT;
1266 +#else
1267 +       module_put(THIS_MODULE);
1268 +#endif
1269 +
1270 +#if defined(I2S_HW_INTERRUPT_EN)&&(I2S_SW_IRQ_EN)
1271 +       free_irq(SURFBOARDINT_I2S, NULL);
1272 +#endif
1273 +
1274 +       ptri2s_config = filp->private_data;
1275 +       if(ptri2s_config==NULL)
1276 +               goto EXIT;
1277 +#ifdef CONFIG_I2S_MMAP
1278 +       i2s_mem_unmap(ptri2s_config);
1279 +#else
1280 +       i2s_txbuf_free(ptri2s_config);
1281 +       i2s_rxbuf_free(ptri2s_config);
1282 +#endif
1283 +       /* free buffer */
1284 +       i2s_txPagebuf_free(ptri2s_config);
1285 +       i2s_rxPagebuf_free(ptri2s_config);
1286 +EXIT:
1287 +       MSG("i2s_release succeeds\n");
1288 +       return 0;
1289 +}
1290 +
1291 +int i2s_mmap_alloc(unsigned long size)
1292 +{
1293 +       int i;
1294 +       u32 page_size;
1295 +               int first_index;
1296 +
1297 +       page_size = I2S_PAGE_SIZE;
1298 +
1299 +       if ((pi2s_config->mmap_index == 0) || (pi2s_config->mmap_index == MAX_I2S_PAGE))
1300 +       {
1301 +               MSG("mmap_index=%d\n", pi2s_config->mmap_index);
1302 +
1303 +               first_index = pi2s_config->mmap_index;
1304 +       pi2s_config->pMMAPBufPtr[pi2s_config->mmap_index] = kmalloc(size, GFP_DMA);
1305 +       i2s_mmap_addr[pi2s_config->mmap_index] = (dma_addr_t)dma_map_single(NULL, pi2s_config->pMMAPBufPtr[pi2s_config->mmap_index], size, DMA_BIDIRECTIONAL);
1306 +
1307 +       if( pi2s_config->pMMAPBufPtr[pi2s_config->mmap_index] == NULL )
1308 +       {
1309 +               MSG("i2s_mmap failed\n");
1310 +               return -1;
1311 +       }
1312 +       }
1313 +       else
1314 +       {
1315 +               _printk("illegal index:%d\n", pi2s_config->mmap_index);
1316 +               return -1;
1317 +       }
1318 +
1319 +       _printk("MMAP[%d]=0x%08X, i2s_mmap_addr[%d]=0x%08x\n",
1320 +               pi2s_config->mmap_index, (u32)pi2s_config->pMMAPBufPtr[pi2s_config->mmap_index],
1321 +                pi2s_config->mmap_index, i2s_mmap_addr[pi2s_config->mmap_index]);
1322 +
1323 +       memset(pi2s_config->pMMAPBufPtr[pi2s_config->mmap_index], 0, size);
1324 +       pi2s_config->mmap_index++;
1325 +
1326 +       for (i=1; i<MAX_I2S_PAGE; i++)
1327 +       {
1328 +               i2s_mmap_addr[pi2s_config->mmap_index] = i2s_mmap_addr[first_index] + i*page_size;
1329 +               pi2s_config->pMMAPBufPtr[pi2s_config->mmap_index] = pi2s_config->pMMAPBufPtr[first_index] + i*page_size;
1330 +
1331 +               _printk("MMAP[%d]=0x%08X, i2s_mmap_addr[%d]=0x%08x\n",pi2s_config->mmap_index, (u32)pi2s_config->pMMAPBufPtr[pi2s_config->mmap_index], pi2s_config->mmap_index, i2s_mmap_addr[pi2s_config->mmap_index]);
1332 +
1333 +               /* Notice: The last mmap_index's value should be MAX_I2S_PAGE or MAX_I2S_PAGE*2 */
1334 +               pi2s_config->mmap_index++;
1335 +       }
1336 +
1337 +       return 0;
1338 +}
1339 +
1340 +int i2s_mmap_remap(struct vm_area_struct *vma, unsigned long size)
1341 +{
1342 +       int nRet;
1343 +
1344 +       if((pi2s_config->pMMAPBufPtr[0]!=NULL) && (pi2s_config->mmap_index == MAX_I2S_PAGE))
1345 +       {
1346 +               MSG("i2s_mmap_remap:0\n");
1347 +               nRet = remap_pfn_range(vma, vma->vm_start, virt_to_phys((void *)pi2s_config->pMMAPBufPtr[0]) >> PAGE_SHIFT,  size, vma->vm_page_prot);
1348 +
1349 +               if( nRet != 0 )
1350 +               {
1351 +                       _printk("i2s_mmap->remap_pfn_range failed\n");
1352 +                       return -EIO;
1353 +               }
1354 +       }
1355 +
1356 +       if((pi2s_config->pMMAPBufPtr[MAX_I2S_PAGE]!=NULL) && (pi2s_config->mmap_index == MAX_I2S_PAGE*2))
1357 +       {
1358 +               MSG("i2s_mmap_remap:%d\n", MAX_I2S_PAGE);
1359 +
1360 +               nRet = remap_pfn_range(vma, vma->vm_start, virt_to_phys((void *)pi2s_config->pMMAPBufPtr[MAX_I2S_PAGE]) >> PAGE_SHIFT,  size, vma->vm_page_prot);
1361 +
1362 +               if( nRet != 0 )
1363 +               {
1364 +                       _printk("i2s_mmap->remap_pfn_range failed\n");
1365 +                       return -EIO;
1366 +               }
1367 +       }
1368 +
1369 +       return 0;
1370 +}
1371 +
1372 +static int i2s_mmap(struct file *filp, struct vm_area_struct *vma)
1373 +{
1374 +       unsigned long size = vma->vm_end-vma->vm_start;
1375 +       _printk("page_size=%d, ksize=%lu\n", I2S_PAGE_SIZE, size);
1376 +
1377 +       if((pi2s_config->pMMAPBufPtr[0]==NULL)&&(pi2s_config->mmap_index!=0))
1378 +               pi2s_config->mmap_index = 0;
1379 +
1380 +       _printk("%s: vm_start=%08X,vm_end=%08X\n", __func__, (u32)vma->vm_start, (u32)vma->vm_end);
1381 +
1382 +       /* Do memory allocate and dma sync */
1383 +       i2s_mmap_alloc(size);
1384 +
1385 +       i2s_mmap_remap(vma, size);
1386 +
1387 +
1388 +       return 0;
1389 +}
1390 +
1391 +int i2s_mem_unmap(i2s_config_type* ptri2s_config)
1392 +{
1393 +       u32 page_size;
1394 +
1395 +       page_size = I2S_PAGE_SIZE;
1396 +
1397 +       if(ptri2s_config->pMMAPBufPtr[0])
1398 +       {
1399 +               _printk("ummap MMAP[0]=0x%08X\n", (u32)ptri2s_config->pMMAPBufPtr[0]);
1400 +               dma_unmap_single(NULL, i2s_mmap_addr[0], MAX_I2S_PAGE*page_size, DMA_BIDIRECTIONAL);
1401 +               kfree(ptri2s_config->pMMAPBufPtr[0]);
1402 +       }
1403 +
1404 +       if(ptri2s_config->pMMAPBufPtr[MAX_I2S_PAGE])
1405 +       {
1406 +               _printk("ummap MMAP[%d]=0x%08X\n", MAX_I2S_PAGE, (u32)ptri2s_config->pMMAPBufPtr[MAX_I2S_PAGE]);
1407 +               dma_unmap_single(NULL, i2s_mmap_addr[MAX_I2S_PAGE], MAX_I2S_PAGE*page_size, DMA_BIDIRECTIONAL);
1408 +               kfree(ptri2s_config->pMMAPBufPtr[MAX_I2S_PAGE]);
1409 +       }
1410 +
1411 +       ptri2s_config->mmap_index = 0;
1412 +
1413 +       return 0;
1414 +}
1415 +
1416 +int i2s_param_init(i2s_config_type* ptri2s_config)
1417 +{
1418 +       ptri2s_config->dmach = GDMA_I2S_TX0;
1419 +       ptri2s_config->tx_ff_thres = CONFIG_I2S_TFF_THRES;
1420 +       ptri2s_config->tx_ch_swap = CONFIG_I2S_CH_SWAP;
1421 +       ptri2s_config->rx_ff_thres = CONFIG_I2S_TFF_THRES;
1422 +       ptri2s_config->rx_ch_swap = CONFIG_I2S_CH_SWAP;
1423 +       ptri2s_config->slave_en = CONFIG_I2S_SLAVE_EN;
1424 +       ptri2s_config->codec_pll_en = CONFIG_I2S_CODEC_PLL_EN;
1425 +
1426 +       ptri2s_config->bRxDMAEnable = 0;
1427 +       ptri2s_config->bTxDMAEnable = 0;
1428 +       //ptri2s_config->bALSAEnable = 0;
1429 +       ptri2s_config->srate = 44100;
1430 +       ptri2s_config->txvol = 0;
1431 +       ptri2s_config->rxvol = 0;
1432 +       ptri2s_config->lbk = 0;
1433 +       ptri2s_config->extlbk = 0;
1434 +       ptri2s_config->txrx_coexist = 0;
1435 +       ptri2s_config->wordlen_24b = 0;
1436 +#if defined(CONFIG_RALINK_MT7628) || defined(CONFIG_ARCH_MT7623)
1437 +       ptri2s_config->sys_endian = 0;
1438 +       ptri2s_config->fmt = 0;
1439 +#endif
1440 +       ptri2s_config->micboost = 0;
1441 +       ptri2s_config->micin = 0;
1442 +
1443 +       return 0;
1444 +}
1445 +
1446 +int i2s_txbuf_alloc(i2s_config_type* ptri2s_config)
1447 +{
1448 +       int i;
1449 +
1450 +       for( i = 0 ; i < MAX_I2S_PAGE ; i ++ )
1451 +        {
1452 +#if defined(CONFIG_I2S_MMAP)
1453 +               ptri2s_config->pMMAPTxBufPtr[i] = ptri2s_config->pMMAPBufPtr[i];
1454 +#else
1455 +                if(ptri2s_config->pMMAPTxBufPtr[i]==NULL)
1456 +                       ptri2s_config->pMMAPTxBufPtr[i] = kmalloc(I2S_PAGE_SIZE, GFP_KERNEL);
1457 +#endif
1458 +               memset(ptri2s_config->pMMAPTxBufPtr[i], 0, I2S_PAGE_SIZE);
1459 +       }
1460 +
1461 +       return 0;
1462 +}
1463 +
1464 +int i2s_rxbuf_alloc(i2s_config_type* ptri2s_config)
1465 +{
1466 +       int i;
1467 +
1468 +       for( i = 0 ; i < MAX_I2S_PAGE ; i ++ )
1469 +        {
1470 +#if defined(CONFIG_I2S_MMAP)
1471 +               ptri2s_config->pMMAPRxBufPtr[i] = ptri2s_config->pMMAPBufPtr[i+(ptri2s_config->mmap_index-MAX_I2S_PAGE)];
1472 +#else
1473 +                if(ptri2s_config->pMMAPRxBufPtr[i]==NULL)
1474 +                       ptri2s_config->pMMAPRxBufPtr[i] = kmalloc(I2S_PAGE_SIZE, GFP_KERNEL);
1475 +#endif
1476 +               memset(ptri2s_config->pMMAPRxBufPtr[i], 0, I2S_PAGE_SIZE);
1477 +        }
1478 +
1479 +       return 0;
1480 +}
1481 +
1482 +int i2s_txPagebuf_alloc(i2s_config_type* ptri2s_config)
1483 +{
1484 +#if defined(ARM_ARCH)
1485 +       ptri2s_config->pPage0TxBuf8ptr = (u8*)pci_alloc_consistent(NULL, I2S_PAGE_SIZE , &i2s_txdma_addr0);
1486 +       ptri2s_config->pPage1TxBuf8ptr = (u8*)pci_alloc_consistent(NULL, I2S_PAGE_SIZE , &i2s_txdma_addr1);
1487 +       if(ptri2s_config->pPage0TxBuf8ptr==NULL)
1488 +        {
1489 +               MSG("Allocate Tx Page0 Buffer Failed\n");
1490 +                return -1;
1491 +        }
1492 +       if(ptri2s_config->pPage1TxBuf8ptr==NULL)
1493 +        {
1494 +               MSG("Allocate Tx Page1 Buffer Failed\n");
1495 +                return -1;
1496 +        }
1497 +#else
1498 +       ptri2s_config->pPage0TxBuf8ptr = (u8*)pci_alloc_consistent(NULL, I2S_PAGE_SIZE*2 , &i2s_txdma_addr);
1499 +        if(ptri2s_config->pPage0TxBuf8ptr==NULL)
1500 +        {
1501 +               MSG("Allocate Tx Page Buffer Failed\n");
1502 +                return -1;
1503 +        }
1504 +        ptri2s_config->pPage1TxBuf8ptr = ptri2s_config->pPage0TxBuf8ptr + I2S_PAGE_SIZE;
1505 +#endif
1506 +       return 0;
1507 +}
1508 +
1509 +int i2s_rxPagebuf_alloc(i2s_config_type* ptri2s_config)
1510 +{
1511 +#if defined(ARM_ARCH)
1512 +       ptri2s_config->pPage0RxBuf8ptr = (u8*)pci_alloc_consistent(NULL, I2S_PAGE_SIZE, &i2s_rxdma_addr0);
1513 +       ptri2s_config->pPage1RxBuf8ptr = (u8*)pci_alloc_consistent(NULL, I2S_PAGE_SIZE, &i2s_rxdma_addr1);
1514 +       if(ptri2s_config->pPage0RxBuf8ptr==NULL)
1515 +       {
1516 +               MSG("Allocate Rx Page Buffer Failed\n");
1517 +               return -1;
1518 +       }
1519 +       if(ptri2s_config->pPage1RxBuf8ptr==NULL)
1520 +       {
1521 +               MSG("Allocate Rx Page Buffer Failed\n");
1522 +               return -1;
1523 +       }
1524 +#else
1525 +       ptri2s_config->pPage0RxBuf8ptr = (u8*)pci_alloc_consistent(NULL, I2S_PAGE_SIZE*2 , &i2s_rxdma_addr);
1526 +       if(ptri2s_config->pPage0RxBuf8ptr==NULL)
1527 +       {
1528 +               MSG("Allocate Rx Page Buffer Failed\n");
1529 +               return -1;
1530 +       }
1531 +       ptri2s_config->pPage1RxBuf8ptr = ptri2s_config->pPage0RxBuf8ptr + I2S_PAGE_SIZE;
1532 +#endif
1533 +       return 0;
1534 +}
1535 +
1536 +int i2s_txbuf_free(i2s_config_type* ptri2s_config)
1537 +{
1538 +       int i;
1539 +
1540 +       for(i = 0 ; i < MAX_I2S_PAGE ; i ++)
1541 +       {
1542 +               if(ptri2s_config->pMMAPTxBufPtr[i] != NULL)
1543 +               {
1544 +#if defined(CONFIG_I2S_MMAP)
1545 +                        ptri2s_config->pMMAPTxBufPtr[i] = NULL;
1546 +#else
1547 +                       kfree(ptri2s_config->pMMAPTxBufPtr[i]);
1548 +                       ptri2s_config->pMMAPTxBufPtr[i] = NULL;
1549 +#endif
1550 +               }
1551 +       }
1552 +       return 0;
1553 +}
1554 +
1555 +int i2s_rxbuf_free(i2s_config_type* ptri2s_config)
1556 +{
1557 +       int i;
1558 +
1559 +       for(i = 0 ; i < MAX_I2S_PAGE ; i ++)
1560 +       {
1561 +               if(ptri2s_config->pMMAPRxBufPtr[i] != NULL)
1562 +               {
1563 +#if defined(CONFIG_I2S_MMAP)
1564 +                        ptri2s_config->pMMAPRxBufPtr[i] = NULL;
1565 +#else
1566 +                       kfree(ptri2s_config->pMMAPRxBufPtr[i]);
1567 +                       ptri2s_config->pMMAPRxBufPtr[i] = NULL;
1568 +#endif
1569 +               }
1570 +       }
1571 +
1572 +       return 0;
1573 +}
1574 +
1575 +int i2s_txPagebuf_free(i2s_config_type* ptri2s_config)
1576 +{
1577 +#if defined(ARM_ARCH)
1578 +       if (ptri2s_config->pPage0TxBuf8ptr)
1579 +       {
1580 +               pci_free_consistent(NULL, I2S_PAGE_SIZE, ptri2s_config->pPage0TxBuf8ptr, i2s_txdma_addr0);
1581 +               ptri2s_config->pPage0TxBuf8ptr = NULL;
1582 +       }
1583 +
1584 +       if (ptri2s_config->pPage1TxBuf8ptr)
1585 +       {
1586 +               pci_free_consistent(NULL, I2S_PAGE_SIZE, ptri2s_config->pPage1TxBuf8ptr, i2s_txdma_addr1);
1587 +               ptri2s_config->pPage1TxBuf8ptr = NULL;
1588 +       }
1589 +       _printk("Free tx page buffer\n");
1590 +#else
1591 +       if (ptri2s_config->pPage0TxBuf8ptr)
1592 +       {
1593 +               pci_free_consistent(NULL, I2S_PAGE_SIZE*2, ptri2s_config->pPage0TxBuf8ptr, i2s_txdma_addr);
1594 +               ptri2s_config->pPage0TxBuf8ptr = NULL;
1595 +       }
1596 +#endif
1597 +       return 0;
1598 +
1599 +}
1600 +
1601 +int i2s_rxPagebuf_free(i2s_config_type* ptri2s_config)
1602 +{
1603 +#if defined(ARM_ARCH)
1604 +       if (ptri2s_config->pPage0RxBuf8ptr)
1605 +       {
1606 +               pci_free_consistent(NULL, I2S_PAGE_SIZE, ptri2s_config->pPage0RxBuf8ptr, i2s_rxdma_addr0);
1607 +               ptri2s_config->pPage0RxBuf8ptr = NULL;
1608 +       }
1609 +       if (ptri2s_config->pPage1RxBuf8ptr)
1610 +       {
1611 +               pci_free_consistent(NULL, I2S_PAGE_SIZE, ptri2s_config->pPage1RxBuf8ptr, i2s_rxdma_addr1);
1612 +               ptri2s_config->pPage1RxBuf8ptr = NULL;
1613 +       }
1614 +       _printk("Free rx page buffer\n");
1615 +#else
1616 +       if (ptri2s_config->pPage0RxBuf8ptr)
1617 +       {
1618 +               pci_free_consistent(NULL, I2S_PAGE_SIZE*2, ptri2s_config->pPage0RxBuf8ptr, i2s_rxdma_addr);
1619 +               ptri2s_config->pPage0RxBuf8ptr = NULL;
1620 +       }
1621 +#endif
1622 +       return 0;
1623 +}
1624 +
1625 +int i2s_reset_tx_param(i2s_config_type* ptri2s_config)
1626 +{
1627 +       ptri2s_config->tx_isr_cnt = 0;
1628 +       ptri2s_config->tx_w_idx = 0;
1629 +       ptri2s_config->tx_r_idx = 0;
1630 +       ptri2s_config->enLable = 0;
1631 +       ptri2s_config->tx_pause_en = 0;
1632 +       ptri2s_config->end_cnt = 0;
1633 +       ptri2s_config->tx_stop_cnt = 0;
1634 +
1635 +#ifdef I2S_STATISTIC
1636 +       pi2s_status->txbuffer_unrun = 0;
1637 +       pi2s_status->txbuffer_ovrun = 0;
1638 +       pi2s_status->txdmafault = 0;
1639 +       pi2s_status->txovrun = 0;
1640 +       pi2s_status->txunrun = 0;
1641 +       pi2s_status->txthres = 0;
1642 +       pi2s_status->txbuffer_len = 0;
1643 +#endif
1644 +
1645 +       return 0;
1646 +}
1647 +
1648 +int i2s_reset_rx_param(i2s_config_type* ptri2s_config)
1649 +{
1650 +       ptri2s_config->rx_isr_cnt = 0;
1651 +       ptri2s_config->rx_w_idx = 0;
1652 +       ptri2s_config->rx_r_idx = 0;
1653 +       ptri2s_config->enLable = 0;
1654 +       ptri2s_config->rx_pause_en = 0;
1655 +       ptri2s_config->rx_stop_cnt = 0;
1656 +
1657 +#ifdef I2S_STATISTIC
1658 +       pi2s_status->rxbuffer_unrun = 0;
1659 +       pi2s_status->rxbuffer_ovrun = 0;
1660 +       pi2s_status->rxdmafault = 0;
1661 +       pi2s_status->rxovrun = 0;
1662 +       pi2s_status->rxunrun = 0;
1663 +       pi2s_status->rxthres = 0;
1664 +       pi2s_status->rxbuffer_len = 0;
1665 +#endif
1666 +
1667 +       return 0;
1668 +}
1669 +#ifdef MT7621_ASIC_BOARD
1670 +int i2s_pll_config_mt7621(unsigned long index)
1671 +{
1672 +        unsigned long data;
1673 +       unsigned long regValue;
1674 +       bool xtal_20M_en = 0;
1675 +//     bool xtal_25M_en = 0;
1676 +       bool xtal_40M_en = 0;
1677 +
1678 +       regValue = i2s_inw(RALINK_SYSCTL_BASE + 0x10);
1679 +               regValue = (regValue >> 6) & 0x7;
1680 +       if (regValue < 3)
1681 +       {
1682 +               xtal_20M_en = 1;
1683 +               MSG("Xtal is 20MHz. \n");
1684 +       }
1685 +       else if (regValue < 6)
1686 +       {
1687 +               xtal_40M_en = 1;
1688 +               MSG("Xtal is 40M.\n");
1689 +       }
1690 +       else
1691 +       {
1692 +               //xtal_25M_en = 1;
1693 +               MSG("Xtal is 25M.\n");
1694 +       }
1695 +
1696 +#if defined (CONFIG_I2S_MCLK_12P288MHZ)
1697 +       _printk("MT7621 provide 12.288M/11.298MHz REFCLK\n");
1698 +       /* Firstly, reset all required register to default value */
1699 +       i2s_outw(RALINK_ANA_CTRL_BASE, 0x00008000);
1700 +       i2s_outw(RALINK_ANA_CTRL_BASE+0x0014, 0x01001d61);//0x01401d61);
1701 +       i2s_outw(RALINK_ANA_CTRL_BASE+0x0018, 0x38233d0e);
1702 +       i2s_outw(RALINK_ANA_CTRL_BASE+0x001c, 0x80100004);//0x80120004);
1703 +       i2s_outw(RALINK_ANA_CTRL_BASE+0x0020, 0x1c7dbf48);
1704 +
1705 +        /* toggle RG_XPTL_CHG */
1706 +        i2s_outw(RALINK_ANA_CTRL_BASE, 0x00008800);
1707 +        i2s_outw(RALINK_ANA_CTRL_BASE, 0x00008c00);
1708 +
1709 +        data = i2s_inw(RALINK_ANA_CTRL_BASE+0x0014);
1710 +        data &= ~(0x0000ffc0);
1711 +       if ((xtal_40M_en) || (xtal_20M_en))
1712 +       {
1713 +               data |= REGBIT(0x1d, 8); /* for 40M or 20M */
1714 +       }
1715 +       else
1716 +       {
1717 +               data |= REGBIT(0x17, 8); /* for 25M */
1718 +       }
1719 +
1720 +       if (xtal_40M_en)
1721 +       {
1722 +               data |= REGBIT(0x1, 6);  /* for 40M */
1723 +       }
1724 +       i2s_outw(RALINK_ANA_CTRL_BASE+0x0014, data);
1725 +
1726 +
1727 +        data = i2s_inw(RALINK_ANA_CTRL_BASE+0x0018);
1728 +        data &= ~(0xf0773f00);
1729 +        data |= REGBIT(0x3, 28);
1730 +        data |= REGBIT(0x2, 20);
1731 +       if ((xtal_40M_en) || (xtal_20M_en))
1732 +       {
1733 +               data |= REGBIT(0x3, 16); /* for 40M or 20M */
1734 +       }
1735 +       else
1736 +       {
1737 +               data |= REGBIT(0x2, 16); /* for 25M */
1738 +       }
1739 +        data |= REGBIT(0x3, 12);
1740 +       if ((xtal_40M_en) || (xtal_20M_en))
1741 +       {
1742 +               data |= REGBIT(0xd, 8); /* for 40M or 20M */
1743 +       }
1744 +       else
1745 +       {
1746 +               data |= REGBIT(0x7, 8); /* for 25M */
1747 +       }
1748 +        i2s_outw(RALINK_ANA_CTRL_BASE+0x0018, data);
1749 +
1750 +        if((index==1)|(index==4)|(index==7)|(index==9))// 270 MHz for 22.05K, 44.1K, 88.2K, 176.4K
1751 +        {
1752 +               if ((xtal_40M_en) || (xtal_20M_en))
1753 +               {
1754 +                       i2s_outw(RALINK_ANA_CTRL_BASE+0x0020, 0x1a18548a); /* for 40M or 20M */
1755 +               }
1756 +               else
1757 +               {
1758 +                       i2s_outw(RALINK_ANA_CTRL_BASE+0x0020, 0x14ad106e); /* for 25M */
1759 +               }
1760 +        }
1761 +        else if ((index==0)|(index==3)|(index==5)|(index==6)|(index==8)|(index==10))// 294 MHZ for 24K, 48K, 96K, 192K
1762 +        {
1763 +               if ((xtal_40M_en) || (xtal_20M_en))
1764 +               {
1765 +                       i2s_outw(RALINK_ANA_CTRL_BASE+0x0020, 0x1c7dbf48); /* for 40M or 20M */
1766 +               }
1767 +               else
1768 +               {
1769 +                       i2s_outw(RALINK_ANA_CTRL_BASE+0x0020, 0x1697cc39); /* for 25M */
1770 +               }
1771 +        }
1772 +       else if (index==2)
1773 +       {
1774 +               _printk("Not support 12KHz sampling rate!\n");
1775 +               return -1;
1776 +       }
1777 +        else
1778 +        {
1779 +                _printk("Wrong sampling rate!\n");
1780 +                return -1;
1781 +        }
1782 +
1783 +        //*Common setting - Set PLLGP_CTRL_4 *//
1784 +       /* 1. Bit 31 */
1785 +        data = i2s_inw(RALINK_ANA_CTRL_BASE+0x001c);
1786 +        data &= ~(REGBIT(0x1, 31));
1787 +        i2s_outw(RALINK_ANA_CTRL_BASE+0x001c, data);
1788 +       ndelay(10);
1789 +
1790 +        /* 2. Bit 0 */
1791 +        data = i2s_inw(RALINK_ANA_CTRL_BASE+0x001c);
1792 +        data |= REGBIT(0x1, 0);
1793 +        i2s_outw(RALINK_ANA_CTRL_BASE+0x001c, data);
1794 +       udelay(200);
1795 +
1796 +        /* 3. Bit 3 */
1797 +        data = i2s_inw(RALINK_ANA_CTRL_BASE+0x001c);
1798 +        data |= REGBIT(0x1, 3);
1799 +        i2s_outw(RALINK_ANA_CTRL_BASE+0x001c, data);
1800 +       udelay(1);
1801 +
1802 +        /* 4. Bit 8 */
1803 +        data = i2s_inw(RALINK_ANA_CTRL_BASE+0x001c);
1804 +        data |= REGBIT(0x1, 8);
1805 +        i2s_outw(RALINK_ANA_CTRL_BASE+0x001c, data);
1806 +       ndelay(40);
1807 +
1808 +        /* 5. Bit 6 */
1809 +        data = i2s_inw(RALINK_ANA_CTRL_BASE+0x001c);
1810 +        data |= REGBIT(0x1, 6);
1811 +        i2s_outw(RALINK_ANA_CTRL_BASE+0x001c, data);
1812 +       ndelay(40);
1813 +
1814 +        /* 6. Bit 5 & Bit 7*/
1815 +        data = i2s_inw(RALINK_ANA_CTRL_BASE+0x001c);
1816 +        data |= REGBIT(0x1, 5);
1817 +       data |= REGBIT(0x1, 7);
1818 +        i2s_outw(RALINK_ANA_CTRL_BASE+0x001c, data);
1819 +       udelay(1);
1820 +
1821 +        /* 7. Bit 17 */
1822 +        data = i2s_inw(RALINK_ANA_CTRL_BASE+0x001c);
1823 +        data |= REGBIT(0x1, 17);
1824 +        i2s_outw(RALINK_ANA_CTRL_BASE+0x001c, data);
1825 +
1826 +#elif defined(CONFIG_I2S_MCLK_12MHZ)
1827 +       _printk("MT7621 provide 12MHz REFCLK\n");
1828 +       /* Firstly, reset all required register to default value */
1829 +       i2s_outw(RALINK_ANA_CTRL_BASE+0x0014, 0x01401d61);//0x01401d61);
1830 +       i2s_outw(RALINK_ANA_CTRL_BASE+0x001c, 0x80120004);//0x80100004);
1831 +       i2s_outw(RALINK_ANA_CTRL_BASE+0x0018, 0x38233d0e);
1832 +
1833 +       if (xtal_40M_en)
1834 +       {
1835 +               data = i2s_inw(RALINK_ANA_CTRL_BASE+0x001c);
1836 +               data &= ~REGBIT(0x1, 17);
1837 +               i2s_outw(RALINK_ANA_CTRL_BASE+0x001c, data);
1838 +
1839 +               data = i2s_inw(RALINK_ANA_CTRL_BASE+0x0014);
1840 +               data &= ~REGBIT(0x3, 4);
1841 +               data |= REGBIT(0x1, 4);
1842 +               i2s_outw(RALINK_ANA_CTRL_BASE+0x0014, data);
1843 +
1844 +               data = i2s_inw(RALINK_ANA_CTRL_BASE+0x001c);
1845 +               data &= ~REGBIT(0x1, 31);
1846 +               i2s_outw(RALINK_ANA_CTRL_BASE+0x001c, data);
1847 +       }
1848 +       else if (xtal_20M_en)
1849 +       {
1850 +               data = i2s_inw(RALINK_ANA_CTRL_BASE+0x001c);
1851 +               data &= ~REGBIT(0x1, 17);
1852 +               i2s_outw(RALINK_ANA_CTRL_BASE+0x001c, data);
1853 +
1854 +               data = i2s_inw(RALINK_ANA_CTRL_BASE+0x0014);
1855 +               data &= ~REGBIT(0x3, 6);
1856 +               i2s_outw(RALINK_ANA_CTRL_BASE+0x0014, data);
1857 +
1858 +               data = i2s_inw(RALINK_ANA_CTRL_BASE+0x0014);
1859 +               data &= ~REGBIT(0x3, 4);
1860 +               data |= REGBIT(0x1, 4);
1861 +               i2s_outw(RALINK_ANA_CTRL_BASE+0x0014, data);
1862 +
1863 +               data = i2s_inw(RALINK_ANA_CTRL_BASE+0x001c);
1864 +               data &= ~REGBIT(0x1, 31);
1865 +               i2s_outw(RALINK_ANA_CTRL_BASE+0x001c, data);
1866 +       }
1867 +       else
1868 +       {
1869 +               data = i2s_inw(RALINK_ANA_CTRL_BASE+0x001c);
1870 +               data &= ~REGBIT(0x1, 17);
1871 +               i2s_outw(RALINK_ANA_CTRL_BASE+0x001c, data);
1872 +
1873 +               data = i2s_inw(RALINK_ANA_CTRL_BASE+0x0014);
1874 +               data &= ~REGBIT(0x7f, 8);
1875 +               data |= REGBIT(0x17, 8);
1876 +               i2s_outw(RALINK_ANA_CTRL_BASE+0x0014, data);
1877 +
1878 +               data = i2s_inw(RALINK_ANA_CTRL_BASE+0x0014);
1879 +               data &= ~REGBIT(0x3, 6);
1880 +               i2s_outw(RALINK_ANA_CTRL_BASE+0x0014, data);
1881 +
1882 +               data = i2s_inw(RALINK_ANA_CTRL_BASE+0x0018);
1883 +               data &= ~REGBIT(0x7, 16);
1884 +               data |= REGBIT(0x2, 16);
1885 +               i2s_outw(RALINK_ANA_CTRL_BASE+0x0018, data);
1886 +
1887 +               data = i2s_inw(RALINK_ANA_CTRL_BASE+0x0018);
1888 +               data &= ~REGBIT(0xf, 8);
1889 +               data |= REGBIT(0x7, 8);
1890 +               i2s_outw(RALINK_ANA_CTRL_BASE+0x0018, data);
1891 +
1892 +
1893 +               data = i2s_inw(RALINK_ANA_CTRL_BASE+0x0014);
1894 +               data &= ~REGBIT(0x3, 4);
1895 +               data |= REGBIT(0x1, 4);
1896 +               i2s_outw(RALINK_ANA_CTRL_BASE+0x0014, data);
1897 +
1898 +               data = i2s_inw(RALINK_ANA_CTRL_BASE+0x001c);
1899 +               data &= ~REGBIT(0x1, 31);
1900 +               i2s_outw(RALINK_ANA_CTRL_BASE+0x001c, data);
1901 +
1902 +       }
1903 +#endif
1904 +        return 0;
1905 +}
1906 +#if defined(CONFIG_I2S_IN_MCLK)
1907 +int i2s_pll_refclk_set(void)
1908 +{
1909 +       unsigned long data;
1910 +
1911 +       /* Set APLL register for REFCLK */
1912 +        data = i2s_inw(RALINK_SYSCTL_BASE+0x90);
1913 +        data &= ~(0x0000f000);
1914 +        data |= REGBIT(0x1, 12);
1915 +        i2s_outw(RALINK_SYSCTL_BASE+0x0090, data);
1916 +
1917 +        data = i2s_inw(RALINK_SYSCTL_BASE+0x0090);
1918 +        data &= ~(0x00000300);
1919 +        i2s_outw(RALINK_SYSCTL_BASE+0x0090, data);
1920 +        MSG("Set 0x90 register\n");
1921 +
1922 +       return 0;
1923 +}
1924 +#endif
1925 +#endif
1926 +
1927 +#ifdef MT7623_ASIC_BOARD
1928 +int i2s_pll_config_mt7623(unsigned long index)
1929 +{
1930 +       unsigned long data;
1931 +
1932 +       /* xPLL PWR ON */
1933 +       data = i2s_inw(AUD2PLL_PWR_CON0);
1934 +       data |= 0x1;
1935 +       i2s_outw(AUD2PLL_PWR_CON0, data);
1936 +       udelay(5);
1937 +
1938 +       /* xPLL ISO Disable */
1939 +       data = i2s_inw(AUD2PLL_PWR_CON0);
1940 +       data &= ~(0x2);
1941 +       i2s_outw(AUD2PLL_PWR_CON0, data);
1942 +
1943 +       /* xPLL Frequency Set */
1944 +       data = i2s_inw(AUD2PLL_CON0);
1945 +       data |= 0x1;
1946 +       i2s_outw(AUD2PLL_CON0, data);
1947 +
1948 +       /* AUD1PLL Frequency Set(change from 98.304MHz to 294.912MHz) */
1949 +       i2s_outw(AUD1PLL_CON0, 0x121);
1950 +       i2s_outw(AUD1PLL_CON1, 0xad5efee6);
1951 +       udelay(40);
1952 +
1953 +       /* Audio clock setting */
1954 +       if((index==1)|(index==4)|(index==7)|(index==9)|(index==11))// for 22.05K, 44.1K, 88.2K, 176.4K
1955 +       {
1956 +               _printk("\n*****%s:index=%d(270MHz)*****\n", __func__, (int)index);
1957 +               data = i2s_inw(0xFB00002c);
1958 +               //data &= ~REGBIT(0x8, 1);
1959 +               data &= ~(0x80);
1960 +               i2s_outw(0xFB00002C, data); /* AUD1PLL 270.9204MHz */
1961 +       }
1962 +       else if ((index==0)|(index==3)|(index==5)|(index==6)|(index==8)|(index==10)|(index==12)) //for 24K, 48K, 96K, 192K
1963 +       {
1964 +               _printk("\n*****%s:index=%d(294MHz)*****\n", __func__, (int)index);
1965 +               data = i2s_inw(0xFB00002c);
1966 +               //data |= REGBIT(0x8, 1);
1967 +               data |= (0x80);
1968 +               i2s_outw(0xFB00002c, data); /* AUD1PLL 294.912MHz */
1969 +       }
1970 +       else if (index==2)
1971 +       {
1972 +               _printk("Not support 12KHz sampling rate!\n");
1973 +               return -1;
1974 +       }
1975 +        else
1976 +        {
1977 +                _printk("Wrong sampling rate!\n");
1978 +                return -1;
1979 +        }
1980 +       return 0;
1981 +}
1982 +#endif
1983 +
1984 +#if defined(MT7628_ASIC_BOARD) || defined(CONFIG_ARCH_MT7623)
1985 +int i2s_driving_strength_adjust(void)
1986 +{
1987 +#if defined(MT7628_ASIC_BOARD)
1988 +        unsigned long data;
1989 +
1990 +        MSG("Adjust MT7628 current's driving strngth\n");
1991 +        /* Adjust REFCLK0's driving strength of current which can avoid
1992 +         * the glitch of REFCKL0
1993 +         * E4 = 0xb0001354[5]; E8 = 0xb0001364[5]
1994 +         * (E4,E8)=(0,0)-> 4 mA;
1995 +         *        =(1,0)-> 8 mA;
1996 +         *        =(0,1)-> 12 mA;
1997 +         *        =(1,1)-> 16 mA*/
1998 +
1999 +        /* Set to 12mA */
2000 +        data = i2s_inw(0xb0001354);
2001 +        data &= ~(0x1<<5);
2002 +        i2s_outw(0xb0001354, data);
2003 +
2004 +        data = i2s_inw(0xb0001364);
2005 +        data |= (0x1<<5);
2006 +        i2s_outw(0xb0001364, data);
2007 +#endif
2008 +#if defined(CONFIG_ARCH_MT7623)
2009 +       MSG("Adjust MT7623 current's driving strngth\n");
2010 +
2011 +       i2s_outw(0xF0005F80, 0x7777);
2012 +#endif
2013 +
2014 +        return 0;
2015 +}
2016 +#endif
2017 +
2018 +#if defined(CONFIG_I2S_IN_MCLK)
2019 +#if defined(CONFIG_I2S_MCLK_12MHZ)
2020 +int i2s_refclk_12m_enable(void)
2021 +{
2022 +       unsigned long data;
2023 +
2024 +       MSG("Enable SoC MCLK 12Mhz\n");
2025 +
2026 +#if defined(CONFIG_RALINK_RT6855A)
2027 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x860);
2028 +       data |= (0x1<<17);
2029 +       data &= ~(0x7<<18);
2030 +       data |= (0x1<<18);
2031 +       i2s_outw(RALINK_SYSCTL_BASE+0x860, data);
2032 +#elif defined(CONFIG_RALINK_RT3350)
2033 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x2c);
2034 +       data |= (0x1<<8);
2035 +       i2s_outw(RALINK_SYSCTL_BASE+0x2c, data);
2036 +#elif defined(CONFIG_RALINK_RT3883)
2037 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x2c);
2038 +       data &= ~(0x03<<13);
2039 +       data |= (0x1<<13);
2040 +       i2s_outw(RALINK_SYSCTL_BASE+0x2c, data);
2041 +#elif defined(CONFIG_RALINK_RT3352)||defined(CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855)
2042 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x2c);
2043 +       data &= ~(0x0F<<8);
2044 +       data |= (0x3<<8);
2045 +       i2s_outw(RALINK_SYSCTL_BASE+0x2c, data);
2046 +#elif defined(CONFIG_RALINK_MT7620)
2047 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x2c);
2048 +       data &= ~(0x07<<9);
2049 +       data |= (1<<9);
2050 +       i2s_outw(RALINK_SYSCTL_BASE+0x2c, data);
2051 +#elif defined(CONFIG_RALINK_MT7621)
2052 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x2c);
2053 +       data &= ~(0x1f<<18);
2054 +       data |= REGBIT(0x19, 18);
2055 +       data &= ~(0x1f<<12);
2056 +       data |= REGBIT(0x1, 12);
2057 +       data &= ~(0x7<<9);
2058 +       data |= REGBIT(0x5, 9);
2059 +       i2s_outw(RALINK_SYSCTL_BASE+0x2c, data);
2060 +#elif defined(CONFIG_RALINK_MT7628)
2061 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x2c);
2062 +       MSG("turn on REFCLK output for MCLK1\n");
2063 +       data &= ~(0x7<<9);
2064 +       data |= (0x1<<9);  /* output for MCLK */
2065 +       i2s_outw(RALINK_SYSCTL_BASE+0x2c, data);
2066 +#else
2067 +       #error "This SoC does not provide 12MHz clock to audio codec\n");
2068 +#endif
2069 +       i2s_refclk_gpio_out_config();
2070 +
2071 +       return 0;
2072 +}
2073 +#endif
2074 +
2075 +#if defined(CONFIG_I2S_MCLK_12P288MHZ)
2076 +int i2s_refclk_12p288m_enable(void)
2077 +{
2078 +       unsigned long data;
2079 +       MSG("Enable SoC MCLK 12.288Mhz\n");
2080 +
2081 +#if defined(CONFIG_RALINK_RT3352)||defined(CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855)
2082 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x2c);
2083 +       data &= ~(0x01F<<18);
2084 +       data |= 31<<18;
2085 +       data &= ~(0x01F<<12);
2086 +       data |= 1<<12;
2087 +       data |= (0xF<<8);
2088 +       i2s_outw(RALINK_SYSCTL_BASE+0x2c, data);
2089 +#elif defined(CONFIG_RALINK_MT7621)
2090 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x2c);
2091 +       data &= ~(0x1f<<18);
2092 +       data |= REGBIT(0xc, 18);
2093 +       data &= ~(0x1f<<12);
2094 +       data |= REGBIT(0x1, 12);
2095 +       data &= ~(0x7<<9);
2096 +       data |= REGBIT(0x5, 9);
2097 +       i2s_outw(RALINK_SYSCTL_BASE+0x2c, data);
2098 +       _printk("MT7621 provide REFCLK 12.288MHz/11.289MHz\n");
2099 +#elif defined(CONFIG_ARCH_MT7623)
2100 +       /* MT7623 does not need to set divider for REFCLK */
2101 +       /* GPIO126 - I2S0_MCLK */
2102 +       data = i2s_inw(0xF00058F0);
2103 +       data &= ~(0x7<<3);
2104 +       data |= (0x6<<3);
2105 +       i2s_outw(0xF00058F0, data);
2106 +       /* GPIO_DIR8: OUT */
2107 +       data = i2s_inw(0xF0005070);
2108 +       data |= (0x1<<14);
2109 +       i2s_outw(0xF0005070, data);
2110 +#else
2111 +       #error "This SoC does not provide 12.288Mhz clock to audio codec\n");
2112 +#endif
2113 +
2114 +       return 0;
2115 +}
2116 +#endif
2117 +
2118 +#if defined(CONFIG_I2S_MCLK_18P432MHZ)
2119 +int i2s_refclk_18p432m_enable(unsigned long index)
2120 +{
2121 +       unsigned long data;
2122 +       MSG("Enable SoC MCLK 18.432MHz/16.934MHz");
2123 +
2124 +       if((index==1)|(index==4)|(index==7)|(index==9))// 16.934MHz for 22.05K, 44.1K, 88.2K, 176.4K
2125 +        {
2126 +               data = i2s_inw(ETHDMASYS_SYSCTL_BASE+0x2c);
2127 +               data &= ~(0x1<<7);
2128 +               i2s_outw(ETHDMASYS_SYSCTL_BASE+0x2c, data);
2129 +       }
2130 +       else if((index==0)|(index==3)|(index==5)|(index==6)|(index==8)|(index==10))// 18.432MHZ for 24K, 48K, 96K, 192K
2131 +        {
2132 +               data = i2s_inw(ETHDMASYS_SYSCTL_BASE+0x2c);
2133 +               data |= (0x1<<7);
2134 +               i2s_outw(ETHDMASYS_SYSCTL_BASE+0x2c, data);
2135 +       }
2136 +
2137 +       data = i2s_inw(ETHDMASYS_SYSCTL_BASE+0x30);
2138 +       data |= (0x1<<17);
2139 +       i2s_outw(ETHDMASYS_SYSCTL_BASE+0x30, data);
2140 +
2141 +       return 0;
2142 +}
2143 +#endif
2144 +#endif
2145 +
2146 +int i2s_refclk_disable(void)
2147 +{
2148 +       unsigned long data;
2149 +
2150 +#if defined(CONFIG_RALINK_RT6855A)
2151 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x860);
2152 +       data &= ~(1<<17);
2153 +       i2s_outw(RALINK_SYSCTL_BASE+0x860, data);
2154 +#elif defined(CONFIG_RALINK_RT3350)
2155 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x2c);
2156 +       data &= ~(0x1<<8);
2157 +       i2s_outw(RALINK_SYSCTL_BASE+0x2c, data);
2158 +#elif defined(CONFIG_RALINK_RT3883)
2159 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x2c);
2160 +        data &= ~(0x0F<<13);
2161 +       i2s_outw(RALINK_SYSCTL_BASE+0x2c, data);
2162 +#elif defined(CONFIG_RALINK_RT3352)||defined(CONFIG_RALINK_RT5350)||defined (CONFIG_RALINK_RT6855)
2163 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x2c);
2164 +       data &= ~(0x0F<<8);
2165 +       i2s_outw(RALINK_SYSCTL_BASE+0x2c, data);
2166 +#elif defined (CONFIG_RALINK_MT7620)||defined (CONFIG_RALINK_MT7621)||defined (CONFIG_RALINK_MT7628)
2167 +       _printk("turn off REFCLK output from internal CLK\n");
2168 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x2c);
2169 +       data &= ~(0x07<<9);
2170 +       i2s_outw(RALINK_SYSCTL_BASE+0x2c, data);
2171 +#elif defined (CONFIG_ARCH_MT7623) /*FIXME:2*/
2172 +#ifdef MT7623_ASIC_BOARD
2173 +       _printk("turn off REFCLK output from internal CLK\n");
2174 +       /* GPIO126 - I2S0_MCLK */
2175 +        data = i2s_inw(0xF00058F0);
2176 +        data &= ~(0x7<<3);
2177 +       //data |= (0x2<<3);
2178 +        i2s_outw(0xF00058F0, data);
2179 +       /* GPIO126 => GPIO_DIR8: IN */
2180 +       data = i2s_inw(0xF0005070);
2181 +       data &= ~(0x1<<14);
2182 +       i2s_outw(0xF0005070, data);
2183 +#else
2184 +       _printk("turn off REFCLK output from internal CLK\n");
2185 +       data = i2s_inw(ETHDMASYS_SYSCTL_BASE+0x30);
2186 +       data &= ~(0x1<<17);
2187 +       i2s_outw(ETHDMASYS_SYSCTL_BASE+0x30, data);
2188 +#endif
2189 +#endif
2190 +       return 0;
2191 +}
2192 +
2193 +int i2s_refclk_gpio_out_config(void)
2194 +{
2195 +#ifndef CONFIG_ARCH_MT7623
2196 +       unsigned long data; /* FIXME */
2197 +#endif
2198 +
2199 +       /* Set REFCLK GPIO pin as REFCLK mode*/
2200 +#if defined(CONFIG_RALINK_MT7620)
2201 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x60);
2202 +       data &= ~(0x03<<21);  /* WDT */
2203 +       data |= (1<<21);
2204 +       //data &= ~(0x03<<16);  /* PERST */
2205 +       //data |= (1<<16);
2206 +       i2s_outw(RALINK_SYSCTL_BASE+0x60, data);
2207 +#endif
2208 +#if defined(CONFIG_RALINK_MT7621)
2209 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x60);
2210 +       //data &= ~(0x3<<10); /* PERST */
2211 +       //data |= (0x2<<10);
2212 +       data &= ~(0x3<<8); /* WDT */
2213 +       data |= (0x2<<8);
2214 +       i2s_outw(RALINK_SYSCTL_BASE+0x60, data);
2215 +       MSG("Set 0x60 register\n");
2216 +#endif
2217 +#if defined(CONFIG_RALINK_MT7628)
2218 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x60);
2219 +       data &= ~(0x1<<18);
2220 +       i2s_outw(RALINK_SYSCTL_BASE+0x60, data);
2221 +#endif
2222 +
2223 +       return 0;
2224 +}
2225 +
2226 +int i2s_refclk_gpio_in_config(void)
2227 +{
2228 +#ifndef CONFIG_ARCH_MT7623
2229 +       unsigned long data; /* FIXME */
2230 +#endif
2231 +
2232 +#if defined (CONFIG_RALINK_MT7620)
2233 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x60);
2234 +       data &= ~(0x03<<21);  /* WDT */
2235 +       data |= (1<<21);
2236 +       //data &= ~(0x03<<16);  /* PERST */
2237 +       //data |= (1<<16);
2238 +       i2s_outw(RALINK_SYSCTL_BASE+0x60, data);
2239 +
2240 +       data = i2s_inw(RALINK_PIO_BASE);
2241 +       data &= ~(0x1<<17); /* GPIO share ping 17 for WDT */
2242 +       i2s_outw(RALINK_PIO_BASE, data);
2243 +
2244 +       //data = i2s_inw(RALINK_PIO_BASE+0x04);
2245 +       //data &= ~(0x1<<4); /* GPIO share ping 36 for PERST */
2246 +       //i2s_outw(RALINK_PIO_BASE+0x04, data);
2247 +#endif
2248 +#if defined (CONFIG_RALINK_MT7621)
2249 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x60);
2250 +       //data &= ~(0x3<<10); /* PERST */
2251 +       //data |= (0x1<<10);
2252 +       data &= ~(0x3<<8); /* WDT */
2253 +       data |= (0x1<<8);
2254 +       i2s_outw(RALINK_SYSCTL_BASE+0x60, data);
2255 +
2256 +       data = i2s_inw(RALINK_PIO_BASE);
2257 +       //data &= ~(0x1<<19); /* GPIO share ping 19 for RERST */
2258 +       data &= ~(0x1<<18); /* GPIO share ping 18 for WDT */
2259 +       i2s_outw(RALINK_PIO_BASE, data);
2260 +#endif
2261 +#if defined (CONFIG_RALINK_MT7628)
2262 +       /* To use external OSC, set REFCLK_GPIO ping as GPIO mode and set it as input direction */
2263 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x60);
2264 +       data |= (0x1<<18);
2265 +       i2s_outw(RALINK_SYSCTL_BASE+0x60, data);
2266 +
2267 +       data = i2s_inw(RALINK_PIO_BASE+0x04);
2268 +       data &= ~(0x1<<5); /* GPIO share ping 37*/
2269 +       i2s_outw(RALINK_PIO_BASE+0x04, data);
2270 +#endif
2271 +
2272 +       return 0;
2273 +}
2274 +
2275 +int i2s_slave_clock_gpio_in_mt7623(void)
2276 +{
2277 +       unsigned long data;
2278 +
2279 +       /* GPIO74(I2S0_BCLK)=>GPIO_DIR5: IN */
2280 +       data = i2s_inw(0xF0005040);
2281 +       data &= ~(0x1<<10);
2282 +       i2s_outw(0xF0005040, data);
2283 +
2284 +       /* GPIO73(I2S0_LRCK)=>GPIO_DIR5: IN */
2285 +       data = i2s_inw(0xF0005040);
2286 +       data &= ~(0x1<<9);
2287 +       i2s_outw(0xF0005040, data);
2288 +
2289 +       _printk("i2s_slave_clock_gpio_in_mt7623\n");
2290 +
2291 +       return 0;
2292 +}
2293 +
2294 +int i2s_master_clock_gpio_out_mt7623(void)
2295 +{
2296 +       unsigned long data;
2297 +
2298 +       /* GPIO74(I2S0_BCLK)=>GPIO_DIR5: OUT */
2299 +       data = i2s_inw(0xF0005040);
2300 +       data |= (0x1<<10);
2301 +       i2s_outw(0xF0005040, data);
2302 +
2303 +       /* GPIO73(I2S0_LRCK)=>GPIO_DIR5: OUT */
2304 +       data = i2s_inw(0xF0005040);
2305 +       data |= (0x1<<9);
2306 +       i2s_outw(0xF0005040, data);
2307 +
2308 +       _printk("i2s_master_clock_gpio_out_mt7623\n");
2309 +
2310 +       return 0;
2311 +}
2312 +
2313 +int i2s_share_pin_mt7623(i2s_config_type* ptri2s_config)
2314 +{
2315 +       unsigned long data;
2316 +
2317 +       _printk("\nConfig MT7623 I2S pinmux\n");
2318 +       /* GPIO74 - I2S0_BCLK */
2319 +       data = i2s_inw(0xF0005840);
2320 +       data &= ~(0x7<<12);
2321 +       data |= (0x6<<12);
2322 +       i2s_outw(0xF0005840, data);
2323 +
2324 +       /* GPIO73 - I2S0_LRCK */
2325 +       data = i2s_inw(0xF0005840);
2326 +       data &= ~(0x7<<9);
2327 +       data |= (0x6<<9);
2328 +       i2s_outw(0xF0005840, data);
2329 +
2330 +       if(ptri2s_config->slave_en==0)
2331 +               i2s_master_clock_gpio_out_mt7623();
2332 +       else
2333 +               i2s_slave_clock_gpio_in_mt7623();
2334 +
2335 +       /* GPIO49 - I2S0_DATA */
2336 +       data = i2s_inw(0xF00057F0);
2337 +       data &= ~(0x7<<12);
2338 +       data |= (0x6<<12);
2339 +       i2s_outw(0xF00057F0, data);
2340 +       /* GPIO_DIR4: OUT */
2341 +       data = i2s_inw(0xF0005030);
2342 +       data |= (0x1<<1);
2343 +       i2s_outw(0xF0005030, data);
2344 +
2345 +       /* GPIO72 - I2S0_DATA_IN */
2346 +       data = i2s_inw(0xF0005840);
2347 +       data &= ~(0x7<<6);
2348 +       data |= (0x6<<6);
2349 +       i2s_outw(0xF0005840, data);
2350 +       /* GPIO_DIR5: IN */
2351 +       data = i2s_inw(0xF0005040);
2352 +       data &= ~(0x1<<8);
2353 +       i2s_outw(0xF0005040, data);
2354 +
2355 +       return 0;
2356 +}
2357 +
2358 +int i2s_share_pin_config(i2s_config_type* ptri2s_config)
2359 +{
2360 +#ifndef CONFIG_ARCH_MT7623
2361 +       unsigned long data; /*FIXME*/
2362 +#endif
2363 +
2364 +       /* set share pins to i2s/gpio mode and i2c mode */
2365 +#if defined(CONFIG_RALINK_RT6855A)
2366 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x860);
2367 +       data |= 0x00008080;
2368 +       i2s_outw(RALINK_SYSCTL_BASE+0x860, data);
2369 +#elif defined(CONFIG_RALINK_MT7621)
2370 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x60);
2371 +       data &= 0xFFFFFFE3;
2372 +       data |= 0x00000010;
2373 +       i2s_outw(RALINK_SYSCTL_BASE+0x60, data);
2374 +#elif defined(CONFIG_RALINK_MT7628)
2375 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x60);
2376 +       data &= ~(0x3<<6);    /* I2S_MODE */
2377 +       data &= ~(0x3<<20);   /* I2C_MODE */
2378 +       i2s_outw(RALINK_SYSCTL_BASE+0x60, data);
2379 +#elif defined(CONFIG_ARCH_MT7623)
2380 +       i2s_share_pin_mt7623(ptri2s_config);
2381 +#else
2382 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x60);
2383 +       data &= 0xFFFFFFE2;
2384 +       data |= 0x00000018;
2385 +       i2s_outw(RALINK_SYSCTL_BASE+0x60, data);
2386 +#endif
2387 +       return 0;
2388 +}
2389 +
2390 +int i2s_ws_config(i2s_config_type* ptri2s_config, unsigned long index)
2391 +{
2392 +       unsigned long data;
2393 +       unsigned long* pTable;
2394 +
2395 +#if defined(CONFIG_I2S_IN_CLK)
2396 +       /* REFCLK is 15.625Mhz or 40Mhz(fractional division) */
2397 +#if defined(CONFIG_I2S_FRAC_DIV)
2398 +       MSG("Internal REFCLK with fractional division\n");
2399 +#if defined(CONFIG_RALINK_MT7628) || defined(CONFIG_ARCH_MT7623)
2400 +       if (ptri2s_config->wordlen_24b == 1)
2401 +       {
2402 +               MSG("24 bit int table\n");
2403 +               pTable = i2s_inclk_int_24bit;
2404 +       }
2405 +       else
2406 +       {
2407 +               MSG("16 bit int table\n");
2408 +               pTable = i2s_inclk_int_16bit;
2409 +       }
2410 +#else
2411 +       pTable = i2s_inclk_int;
2412 +#endif /* CONFIG_RALINK_MT7628 */
2413 +
2414 +       data = (unsigned long)(pTable[index]);
2415 +       i2s_outw(I2S_DIVINT_CFG, data);
2416 +
2417 +#if defined(CONFIG_RALINK_MT7628) || defined(CONFIG_ARCH_MT7623)
2418 +       if (ptri2s_config->wordlen_24b == 1)
2419 +       {
2420 +               MSG("24 bit comp table\n");
2421 +               pTable = i2s_inclk_comp_24bit;
2422 +       }
2423 +       else
2424 +       {
2425 +               MSG("16 bit comp table\n");
2426 +               pTable = i2s_inclk_comp_16bit;
2427 +       }
2428 +#else
2429 +       pTable = i2s_inclk_comp;
2430 +#endif /* CONFIG_RALINK_MT7628 */
2431 +
2432 +       data = (unsigned long)(pTable[index]);
2433 +       data |= REGBIT(1, I2S_CLKDIV_EN);
2434 +       i2s_outw(I2S_DIVCOMP_CFG, data);
2435 +#else
2436 +       MSG("Internal REFCLK 15.625Mhz \n");
2437 +       pTable = i2s_inclk_15p625Mhz;
2438 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x30);
2439 +       data &= 0xFFFF00FF;
2440 +       data |= (unsigned long)(pTable[index]);
2441 +       data |= 0x00008000;
2442 +       i2s_outw(RALINK_SYSCTL_BASE+0x30, data);
2443 +#endif /* CONFIG_I2S_FRAC_DIV */
2444 +#else
2445 +#if defined(CONFIG_I2S_MCLK_12MHZ)
2446 +       /* REFCLK = MCLK = 12Mhz */
2447 +       MSG("External REFCLK 12Mhz \n");
2448 +       pTable = i2s_exclk_12Mhz;
2449 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x30);
2450 +       data &= 0xFFFF00FF;
2451 +       data |= (unsigned long)(pTable[index]);
2452 +       data |= 0x0000C000;
2453 +       i2s_outw(RALINK_SYSCTL_BASE+0x30, data);
2454 +#else
2455 +       /* REFCLK = MCLK = 12.288Mhz */
2456 +       pTable = i2s_exclk_12p288Mhz;
2457 +       MSG("External REFCLK 12.288Mhz \n");
2458 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x30);
2459 +       data &= 0xFFFF00FF;
2460 +       data |= (unsigned long)(pTable[index]);
2461 +       data |= 0x0000C000;
2462 +       i2s_outw(RALINK_SYSCTL_BASE+0x30, data);
2463 +#endif /* CONFIG_I2S_MCLK_12MHZ */
2464 +#endif /* Not CONFIG_I2S_IN_CLK */
2465 +
2466 +#if defined(CONFIG_I2S_WS_EDGE)
2467 +       data = i2s_inw(I2S_I2SCFG);
2468 +       data |= REGBIT(0x1, I2S_WS_INV);
2469 +       i2s_outw(I2S_I2SCFG, data);
2470 +#endif
2471 +
2472 +       return 0;
2473 +}
2474 +
2475 +int i2s_mode_config(u32 slave_en)
2476 +{
2477 +       unsigned long data;
2478 +
2479 +       if(slave_en==0)
2480 +       {
2481 +               /* Master mode*/
2482 +               _printk("This SoC is in Master mode\n");
2483 +#if defined(CONFIG_RALINK_RT3052)
2484 +               data = i2s_inw(I2S_I2SCFG);
2485 +               data &= ~REGBIT(0x1, I2S_SLAVE_EN);
2486 +               data &= ~REGBIT(0x1, I2S_CLK_OUT_DIS);
2487 +               i2s_outw(I2S_I2SCFG, data);
2488 +#elif defined(CONFIG_RALINK_RT3883)||defined(CONFIG_RALINK_RT3352)||\
2489 +       defined(CONFIG_RALINK_RT5350)||defined(CONFIG_RALINK_RT6855)||\
2490 +       defined(CONFIG_RALINK_MT7620)||defined(CONFIG_RALINK_RT6855A)||\
2491 +       defined(CONFIG_RALINK_MT7621)||defined(CONFIG_RALINK_MT7628)||\
2492 +       defined(CONFIG_ARCH_MT7623)
2493 +               data = i2s_inw(I2S_I2SCFG);
2494 +               data &= ~REGBIT(0x1, I2S_SLAVE_MODE);
2495 +               i2s_outw(I2S_I2SCFG, data);
2496 +#else
2497 +       #error "a strange clock mode"
2498 +#endif
2499 +       }
2500 +       else
2501 +       {
2502 +               /* Slave mode */
2503 +               _printk("This SoC is in Slave mode\n");
2504 +#if defined(CONFIG_RALINK_RT3052)
2505 +               data = i2s_inw(I2S_I2SCFG);
2506 +               data |= REGBIT(0x1, I2S_SLAVE_EN);
2507 +               data |= REGBIT(0x1, I2S_CLK_OUT_DIS);
2508 +               i2s_outw(I2S_I2SCFG, data);
2509 +#elif defined(CONFIG_RALINK_RT3883)||defined(CONFIG_RALINK_RT3352)||\
2510 +       defined(CONFIG_RALINK_RT5350)||defined(CONFIG_RALINK_RT6855)||\
2511 +       defined(CONFIG_RALINK_MT7620)||defined(CONFIG_RALINK_RT6855A)||\
2512 +       defined(CONFIG_RALINK_MT7621)||defined(CONFIG_RALINK_MT7628)||\
2513 +       defined(CONFIG_ARCH_MT7623)
2514 +               data = i2s_inw(I2S_I2SCFG);
2515 +               data |= REGBIT(0x1, I2S_SLAVE_MODE);
2516 +               i2s_outw(I2S_I2SCFG, data);
2517 +#else
2518 +               #error "a strange clock mode "
2519 +#endif
2520 +       }
2521 +
2522 +       return 0;
2523 +}
2524 +
2525 +int i2s_codec_frequency_config(i2s_config_type* ptri2s_config, unsigned long index)
2526 +{
2527 +#if defined(CONFIG_I2S_WM8960)||defined(CONFIG_I2S_WM8750)||defined(CONFIG_I2S_WM8751)
2528 +       unsigned long data;
2529 +       unsigned long* pTable;
2530 +#endif
2531 +
2532 +#if defined(CONFIG_I2S_MCLK_12MHZ)
2533 +#if defined(CONFIG_I2S_WM8960)||defined(CONFIG_I2S_WM8750)||defined(CONFIG_I2S_WM8751)
2534 +       pTable = i2s_codec_12Mhz;
2535 +       data = pTable[index];
2536 +#endif
2537 +#if defined(CONFIG_I2S_WM8960)
2538 +       audiohw_set_frequency(data, ptri2s_config->codec_pll_en);
2539 +#elif defined(CONFIG_I2S_WM8750)||defined(CONFIG_I2S_WM8751)
2540 +       audiohw_set_frequency(data|0x01);
2541 +#endif
2542 +#else
2543 +#if defined(CONFIG_I2S_WM8960)||defined(CONFIG_I2S_WM8750)||defined(CONFIG_I2S_WM8751)
2544 +#if defined(MT7623_FPGA_BOARD) && defined(CONFIG_I2S_WM8750)
2545 +       pTable = i2s_codec_18p432Mhz;
2546 +#else
2547 +       pTable = i2s_codec_12p288Mhz;
2548 +#endif
2549 +       data = pTable[index];
2550 +#endif
2551 +#if defined(CONFIG_I2S_WM8960)
2552 +       audiohw_set_frequency(data, ptri2s_config->codec_pll_en);
2553 +#elif defined(CONFIG_I2S_WM8750)||defined(CONFIG_I2S_WM8751)
2554 +       audiohw_set_frequency(data);
2555 +#endif
2556 +#endif
2557 +       return 0;
2558 +}
2559 +
2560 +/*
2561 + *  Ralink Audio System Clock Enable
2562 + *
2563 + *  I2S_WS : signal direction opposite to/same as I2S_CLK
2564 + *
2565 + *  I2S_CLK : Integer division or fractional division
2566 + *                       REFCLK from Internal or External (external REFCLK not support for fractional division)
2567 + *                       Suppose external REFCLK always be the same as external MCLK
2568 + *
2569 + *  MCLK : External OSC or internal generation
2570 + *
2571 + */
2572 +int i2s_clock_enable(i2s_config_type* ptri2s_config)
2573 +{
2574 +       unsigned long index;
2575 +       /* audio sampling rate decision */
2576 +       switch(ptri2s_config->srate)
2577 +       {
2578 +               case 8000:
2579 +                       index = 0;
2580 +                       break;
2581 +               case 11025:
2582 +                       index = 1;
2583 +                       break;
2584 +               case 12000:
2585 +                       index = 2;
2586 +                       break;
2587 +               case 16000:
2588 +                       index = 3;
2589 +                       break;
2590 +               case 22050:
2591 +                       index = 4;
2592 +                       break;
2593 +               case 24000:
2594 +                       index = 5;
2595 +                       break;
2596 +               case 32000:
2597 +                       index = 6;
2598 +                       break;
2599 +               case 44100:
2600 +                       index = 7;
2601 +                       break;
2602 +               case 48000:
2603 +                       index = 8;
2604 +                       break;
2605 +               case 88200:
2606 +                       index = 9;
2607 +                       break;
2608 +               case 96000:
2609 +                       index = 10;
2610 +                       break;
2611 +#if defined(CONFIG_RALINK_MT7628) || defined(CONFIG_ARCH_MT7623)
2612 +               case 176000:
2613 +                       index = 11;
2614 +                       break;
2615 +               case 192000:
2616 +                       index = 12;
2617 +                       break;
2618 +#endif
2619 +               default:
2620 +                       index = 7;
2621 +       }
2622 +#ifdef MT7621_ASIC_BOARD
2623 +        /* Set pll config  */
2624 +        i2s_pll_config_mt7621(index);
2625 +#endif
2626 +#ifdef MT7623_ASIC_BOARD
2627 +        /* Set pll config  */
2628 +        i2s_pll_config_mt7623(index);
2629 +#endif
2630 +
2631 +       /* enable internal MCLK */
2632 +#if defined(CONFIG_I2S_IN_MCLK)
2633 +#if defined(CONFIG_RALINK_MT7621)
2634 +       i2s_pll_refclk_set();
2635 +#endif
2636 +#if defined(CONFIG_I2S_MCLK_12MHZ)
2637 +#if defined(MT7628_ASIC_BOARD) || defined(CONFIG_ARCH_MT7623)
2638 +        i2s_driving_strength_adjust();
2639 +#endif
2640 +       i2s_refclk_12m_enable();
2641 +#endif /* MCLK_12MHZ */
2642 +#if defined(CONFIG_I2S_MCLK_12P288MHZ)
2643 +       i2s_refclk_12p288m_enable();
2644 +#endif /* MCLK_12P288MHZ */
2645 +#if defined(CONFIG_I2S_MCLK_18P432MHZ)
2646 +       i2s_refclk_18p432m_enable(index);
2647 +#endif
2648 +       i2s_refclk_gpio_out_config();
2649 +
2650 +#else
2651 +       MSG("Disable SoC MCLK, use external OSC\n");
2652 +       i2s_refclk_disable();
2653 +       i2s_refclk_gpio_in_config();
2654 +#endif /* CONFIG_I2S_IN_MCLK */
2655 +
2656 +       i2s_share_pin_config(ptri2s_config);
2657 +
2658 +       if(ptri2s_config->slave_en==0)
2659 +       {
2660 +               /* Setup I2S_WS and I2S_CLK */
2661 +               i2s_ws_config(ptri2s_config, index);
2662 +       }
2663 +
2664 +       i2s_mode_config(ptri2s_config->slave_en);
2665 +
2666 +       if(!ptri2s_config->bALSAEnable)
2667 +       {
2668 +#if defined(CONFIG_I2S_WM8750) || defined(CONFIG_I2S_WM8751)|| defined(CONFIG_I2S_WM8960)
2669 +       i2s_codec_enable(ptri2s_config);
2670 +#endif
2671 +       i2s_codec_frequency_config(ptri2s_config,index);
2672 +       }
2673 +
2674 +       return 0;
2675 +}
2676 +
2677 +int i2s_clock_disable(i2s_config_type* ptri2s_config)
2678 +{
2679 +       if(!ptri2s_config->bALSAEnable)
2680 +       {
2681 +#if defined(CONFIG_I2S_WM8960) || defined(CONFIG_I2S_WM8750) || defined(CONFIG_I2S_WM8751)
2682 +       i2s_codec_disable(ptri2s_config);
2683 +#endif
2684 +       }
2685 +
2686 +       /* disable internal MCLK */
2687 +#if defined(CONFIG_I2S_IN_MCLK)
2688 +       i2s_refclk_disable();
2689 +       i2s_refclk_gpio_in_config();
2690 +#endif
2691 +       return 0;
2692 +}
2693 +
2694 +
2695 +int i2s_codec_enable(i2s_config_type* ptri2s_config)
2696 +{
2697 +
2698 +       int AIn = 0, AOut = 0;
2699 +#if 1
2700 +#if defined(CONFIG_I2S_WM8960) || defined(CONFIG_I2S_WM8750) || defined(CONFIG_I2S_WM8751)
2701 +       /* Codec initialization */
2702 +       audiohw_preinit();
2703 +#endif
2704 +#endif
2705 +
2706 +#if defined(CONFIG_I2S_WM8960)
2707 +       if(ptri2s_config->codec_pll_en)
2708 +       {
2709 +               MSG("Codec PLL EN = %d\n", pi2s_config->codec_pll_en);
2710 +               audiohw_set_apll(ptri2s_config->srate);
2711 +       }
2712 +#endif
2713 +
2714 +#if defined(CONFIG_I2S_TXRX)
2715 +       if((ptri2s_config->bTxDMAEnable) || (ptri2s_config->txrx_coexist))
2716 +               AOut = 1;
2717 +       if((ptri2s_config->bRxDMAEnable) || (ptri2s_config->txrx_coexist))
2718 +               AIn = 1;
2719 +#if defined(CONFIG_I2S_WM8960)
2720 +       audiohw_postinit(!(ptri2s_config->slave_en), AIn, AOut, ptri2s_config->codec_pll_en, ptri2s_config->wordlen_24b);
2721 +       audiohw_micboost(ptri2s_config->micboost);
2722 +       audiohw_micin(ptri2s_config->micin);
2723 +#elif defined(CONFIG_I2S_WM8750)
2724 +       audiohw_postinit(!(ptri2s_config->slave_en), AIn, AOut, ptri2s_config->wordlen_24b);
2725 +#endif
2726 +       MSG("AOut=%d, AIn=%d\n", AOut, AIn);
2727 +#else
2728 +#if defined(CONFIG_I2S_WM8750)
2729 +       audiohw_postinit(!(ptri2s_config->slave_en), 0, 1);
2730 +#elif defined(CONFIG_I2S_WM8960)
2731 +       audiohw_postinit(!(ptri2s_config->slave_en), 1, 1, ptri2s_config->codec_pll_en);
2732 +#elif defined(CONFIG_I2S_WM8751)
2733 +       if(ptri2s_config->slave_en==0)
2734 +               audiohw_postinit(1,1);
2735 +       else
2736 +               audiohw_postinit(0,1);
2737 +#endif
2738 +#endif
2739 +       return 0;
2740 +}
2741 +
2742 +int i2s_codec_disable(i2s_config_type* ptri2s_config)
2743 +{
2744 +#if defined(CONFIG_I2S_WM8960) || defined(CONFIG_I2S_WM8750) || defined(CONFIG_I2S_WM8751)
2745 +       audiohw_close();
2746 +#endif
2747 +       return 0;
2748 +}
2749 +
2750 +int i2s_reset_config(i2s_config_type* ptri2s_config)
2751 +{
2752 +       unsigned long data;
2753 +
2754 +       /* RESET bit: write 1 clear */
2755 +#if defined(CONFIG_RALINK_RT6855A)
2756 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x834);
2757 +       data |= (1<<17);
2758 +       i2s_outw(RALINK_SYSCTL_BASE+0x834, data);
2759 +
2760 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x834);
2761 +       data &= ~(1<<17);
2762 +       i2s_outw(RALINK_SYSCTL_BASE+0x834, data);
2763 +#elif defined(CONFIG_ARCH_MT7623)
2764 +       data = i2s_inw(0xFB000000+0x34);
2765 +       data |= (1<<17);
2766 +       i2s_outw(0xFB000000+0x34, data);
2767 +
2768 +       data = i2s_inw(0xFB000000+0x34);
2769 +       data &= ~(1<<17);
2770 +       i2s_outw(0xFB000000+0x34, data);
2771 +#else
2772 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x34);
2773 +       data |= (1<<17);
2774 +       i2s_outw(RALINK_SYSCTL_BASE+0x34, data);
2775 +
2776 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x34);
2777 +       data &= ~(1<<17);
2778 +       i2s_outw(RALINK_SYSCTL_BASE+0x34, data);
2779 +
2780 +#if 0  /* Reset GDMA */
2781 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x34);
2782 +       data |= (1<<14);
2783 +       i2s_outw(RALINK_SYSCTL_BASE+0x34, data);
2784 +
2785 +       data = i2s_inw(RALINK_SYSCTL_BASE+0x34);
2786 +       data &= ~(1<<14);
2787 +       i2s_outw(RALINK_SYSCTL_BASE+0x34, data);
2788 +#endif
2789 +#endif
2790 +       _printk("I2S reset complete!!\n");
2791 +       return 0;
2792 +}
2793 +
2794 +int i2s_tx_config(i2s_config_type* ptri2s_config)
2795 +{
2796 +       unsigned long data;
2797 +       /* set I2S_I2SCFG */
2798 +       data = i2s_inw(I2S_I2SCFG);
2799 +       data &= 0xFFFFFF81;
2800 +       data |= REGBIT(ptri2s_config->tx_ff_thres, I2S_TX_FF_THRES);
2801 +       data |= REGBIT(ptri2s_config->tx_ch_swap, I2S_TX_CH_SWAP);
2802 +#if defined(CONFIG_RALINK_RT6855A)
2803 +       data |= REGBIT(1, I2S_BYTE_SWAP);
2804 +#endif
2805 +#if defined(CONFIG_RALINK_MT7628) || defined(CONFIG_ARCH_MT7623)
2806 +       MSG("TX:wordLen=%d, sysEndian=%d\n", ptri2s_config->wordlen_24b, ptri2s_config->sys_endian);
2807 +       data |= REGBIT(ptri2s_config->wordlen_24b, I2S_DATA_24BIT);
2808 +       data |= REGBIT(ptri2s_config->sys_endian, I2S_SYS_ENDIAN);
2809 +       data |= REGBIT(ptri2s_config->little_edn, I2S_LITTLE_ENDIAN);
2810 +#endif
2811 +       data &= ~REGBIT(1, I2S_TX_CH0_OFF);
2812 +       data &= ~REGBIT(1, I2S_TX_CH1_OFF);
2813 +       i2s_outw(I2S_I2SCFG, data);
2814 +
2815 +       /* set I2S_I2SCFG1 */
2816 +       MSG("internal loopback: %d\n", ptri2s_config->lbk);
2817 +       data = i2s_inw(I2S_I2SCFG1);
2818 +       data |= REGBIT(ptri2s_config->lbk, I2S_LBK_EN);
2819 +       data |= REGBIT(ptri2s_config->extlbk, I2S_EXT_LBK_EN);
2820 +       data &= 0xFFFFFFFC;
2821 +#if defined(CONFIG_RALINK_MT7628) || defined(CONFIG_ARCH_MT7623)
2822 +       data |= REGBIT(ptri2s_config->fmt, I2S_DATA_FMT);
2823 +#endif
2824 +       i2s_outw(I2S_I2SCFG1, data);
2825 +
2826 +       return 0;
2827 +}
2828 +
2829 +int i2s_rx_config(i2s_config_type* ptri2s_config)
2830 +{
2831 +       unsigned long data;
2832 +       /* set I2S_I2SCFG */
2833 +       data = i2s_inw(I2S_I2SCFG);
2834 +       data &= 0xFFFF81FF;
2835 +       data |= REGBIT(ptri2s_config->rx_ff_thres, I2S_RX_FF_THRES);
2836 +       data |= REGBIT(ptri2s_config->rx_ch_swap, I2S_RX_CH_SWAP);
2837 +       data &= ~REGBIT(1, I2S_RX_CH0_OFF);
2838 +       data &= ~REGBIT(1, I2S_RX_CH1_OFF);
2839 +#if defined(CONFIG_RALINK_MT7628) || defined(CONFIG_ARCH_MT7623)
2840 +       MSG("RX:wordLen=%d, sysEndian=%d\n", ptri2s_config->wordlen_24b, ptri2s_config->sys_endian);
2841 +       data |= REGBIT(ptri2s_config->wordlen_24b, I2S_DATA_24BIT);
2842 +       data |= REGBIT(ptri2s_config->sys_endian, I2S_SYS_ENDIAN);
2843 +       data |= REGBIT(ptri2s_config->little_edn, I2S_LITTLE_ENDIAN);
2844 +#endif
2845 +       i2s_outw(I2S_I2SCFG, data);
2846 +
2847 +       /* set I2S_I2SCFG1 */
2848 +       data = i2s_inw(I2S_I2SCFG1);
2849 +       data |= REGBIT(ptri2s_config->lbk, I2S_LBK_EN);
2850 +       data |= REGBIT(ptri2s_config->extlbk, I2S_EXT_LBK_EN);
2851 +#if defined(CONFIG_RALINK_MT7628) || defined(CONFIG_ARCH_MT7623)
2852 +       data &= 0xFFFFFFFC;
2853 +       data |= REGBIT(ptri2s_config->fmt, I2S_DATA_FMT);
2854 +#endif
2855 +       i2s_outw(I2S_I2SCFG1, data);
2856 +
2857 +       return 0;
2858 +}
2859 +
2860 +/* Turn On Tx DMA and INT */
2861 +int i2s_tx_enable(i2s_config_type* ptri2s_config)
2862 +{
2863 +       unsigned long data;
2864 +
2865 +#if defined(I2S_HW_INTERRUPT_EN)
2866 +       data = i2s_inw(I2S_INT_EN);
2867 +       data |= REGBIT(0x1, I2S_TX_INT3_EN);  /* FIFO DMA fault */
2868 +       data |= REGBIT(0x1, I2S_TX_INT2_EN);  /* FIFO overrun */
2869 +       data |= REGBIT(0x1, I2S_TX_INT1_EN);  /* FIFO underrun */
2870 +       data |= REGBIT(0x1, I2S_TX_INT0_EN);  /* FIFO below threshold */
2871 +       i2s_outw(I2S_INT_EN, data);
2872 +#endif
2873 +
2874 +       data = i2s_inw(I2S_I2SCFG);
2875 +#if defined(CONFIG_I2S_TXRX)
2876 +       data |= REGBIT(0x1, I2S_TX_EN);
2877 +#endif
2878 +       data |= REGBIT(0x1, I2S_DMA_EN);
2879 +       i2s_outw(I2S_I2SCFG, data);
2880 +
2881 +       data = i2s_inw(I2S_I2SCFG);
2882 +       data |= REGBIT(0x1, I2S_EN);
2883 +       i2s_outw(I2S_I2SCFG, data);
2884 +
2885 +       MSG("i2s_tx_enable done\n");
2886 +       return I2S_OK;
2887 +}
2888 +
2889 +/* Turn On Rx DMA and INT */
2890 +int i2s_rx_enable(i2s_config_type* ptri2s_config)
2891 +{
2892 +       unsigned long data;
2893 +
2894 +#if defined(I2S_HW_INTERRUPT_EN)
2895 +       data = i2s_inw(I2S_INT_EN);
2896 +       data |= REGBIT(0x1, I2S_RX_INT3_EN);  /* FIFO DMA fault */
2897 +       data |= REGBIT(0x1, I2S_RX_INT2_EN);  /* FIFO overrun */
2898 +       data |= REGBIT(0x1, I2S_RX_INT1_EN);  /* FIFO underrun */
2899 +       data |= REGBIT(0x1, I2S_RX_INT0_EN);  /* FIFO below threshold */
2900 +       i2s_outw(I2S_INT_EN, data);
2901 +#endif
2902 +
2903 +       data = i2s_inw(I2S_I2SCFG);
2904 +#if defined(CONFIG_I2S_TXRX)
2905 +       data |= REGBIT(0x1, I2S_RX_EN);
2906 +#endif
2907 +       data |= REGBIT(0x1, I2S_DMA_EN);
2908 +       i2s_outw(I2S_I2SCFG, data);
2909 +
2910 +       data = i2s_inw(I2S_I2SCFG);
2911 +       data |= REGBIT(0x1, I2S_EN);
2912 +       i2s_outw(I2S_I2SCFG, data);
2913 +
2914 +       MSG("i2s_rx_enable done\n");
2915 +       return I2S_OK;
2916 +}
2917 +/* Turn Off Tx DMA and INT */
2918 +int i2s_tx_disable(i2s_config_type* ptri2s_config)
2919 +{
2920 +       unsigned long data;
2921 +
2922 +#if defined(I2S_HW_INTERRUPT_EN)
2923 +       data = i2s_inw(I2S_INT_EN);
2924 +       data &= ~REGBIT(0x1, I2S_TX_INT3_EN);
2925 +       data &= ~REGBIT(0x1, I2S_TX_INT2_EN);
2926 +       data &= ~REGBIT(0x1, I2S_TX_INT1_EN);
2927 +       data &= ~REGBIT(0x1, I2S_TX_INT0_EN);
2928 +       i2s_outw(I2S_INT_EN, data);
2929 +#endif
2930 +
2931 +       data = i2s_inw(I2S_I2SCFG);
2932 +#if defined(CONFIG_I2S_TXRX)
2933 +       data &= ~REGBIT(0x1, I2S_TX_EN);
2934 +#endif
2935 +       if(ptri2s_config->bRxDMAEnable==0)
2936 +       {
2937 +               ptri2s_config->bTxDMAEnable = 0;
2938 +               data &= ~REGBIT(0x1, I2S_DMA_EN);
2939 +                data &= ~REGBIT(0x1, I2S_EN);
2940 +       }
2941 +       i2s_outw(I2S_I2SCFG, data);
2942 +       return I2S_OK;
2943 +}
2944 +/* Turn Off Rx DMA and INT */
2945 +int i2s_rx_disable(i2s_config_type* ptri2s_config)
2946 +{
2947 +       unsigned long data;
2948 +
2949 +#if defined(I2S_HW_INTERRUPT_EN)
2950 +       data = i2s_inw(I2S_INT_EN);
2951 +       data &= ~REGBIT(0x1, I2S_RX_INT3_EN);
2952 +       data &= ~REGBIT(0x1, I2S_RX_INT2_EN);
2953 +       data &= ~REGBIT(0x1, I2S_RX_INT1_EN);
2954 +       data &= ~REGBIT(0x1, I2S_RX_INT0_EN);
2955 +       i2s_outw(I2S_INT_EN, data);
2956 +#endif
2957 +
2958 +       data = i2s_inw(I2S_I2SCFG);
2959 +#if defined(CONFIG_I2S_TXRX)
2960 +       data &= ~REGBIT(0x1, I2S_RX_EN);
2961 +#endif
2962 +       if(ptri2s_config->bTxDMAEnable==0)
2963 +       {
2964 +               ptri2s_config->bRxDMAEnable = 0;
2965 +               data &= ~REGBIT(0x1, I2S_DMA_EN);
2966 +                data &= ~REGBIT(0x1, I2S_EN);
2967 +       }
2968 +       i2s_outw(I2S_I2SCFG, data);
2969 +       return I2S_OK;
2970 +}
2971 +
2972 +int i2s_dma_tx_transf_data(i2s_config_type* ptri2s_config, u32 dma_ch)
2973 +{
2974 +       int tx_r_idx;
2975 +
2976 +       if ((pi2s_config->bALSAEnable==1) && (pi2s_config->bALSAMMAPEnable==1))
2977 +               tx_r_idx = (pi2s_config->tx_r_idx + ALSA_MMAP_IDX_SHIFT)%MAX_I2S_PAGE;
2978 +       else
2979 +               tx_r_idx = pi2s_config->tx_r_idx;
2980 +
2981 +       if(dma_ch==GDMA_I2S_TX0)
2982 +        {
2983 +#if defined(CONFIG_I2S_MMAP)
2984 +               dma_sync_single_for_device(NULL,  i2s_mmap_addr[tx_r_idx], I2S_PAGE_SIZE, DMA_TO_DEVICE);
2985 +#if defined(ARM_ARCH)
2986 +               GdmaI2sTx(i2s_mmap_addr[tx_r_idx], I2S_TX_FIFO_WREG_PHY, 0, I2S_PAGE_SIZE, i2s_dma_tx_handler, i2s_dma_tx_unmask_handler);
2987 +#else
2988 +                GdmaI2sTx((u32)(pi2s_config->pMMAPTxBufPtr[tx_r_idx]), I2S_TX_FIFO_WREG, 0, I2S_PAGE_SIZE, i2s_dma_tx_handler, i2s_dma_tx_unmask_handler);
2989 +#endif
2990 +#else
2991 +                memcpy(pi2s_config->pPage0TxBuf8ptr,  pi2s_config->pMMAPTxBufPtr[tx_r_idx], I2S_PAGE_SIZE);
2992 +#if defined(ARM_ARCH)
2993 +               GdmaI2sTx(i2s_txdma_addr0, I2S_TX_FIFO_WREG_PHY, 0, I2S_PAGE_SIZE, i2s_dma_tx_handler, i2s_dma_tx_unmask_handler);
2994 +#else
2995 +                GdmaI2sTx((u32)(pi2s_config->pPage0TxBuf8ptr), I2S_TX_FIFO_WREG, 0, I2S_PAGE_SIZE, i2s_dma_tx_handler, i2s_dma_tx_unmask_handler);
2996 +#endif
2997 +#endif
2998 +                pi2s_config->dmach = GDMA_I2S_TX0;
2999 +                pi2s_config->tx_r_idx = (pi2s_config->tx_r_idx+1)%MAX_I2S_PAGE;
3000 +       }
3001 +        else
3002 +        {
3003 +#if defined(CONFIG_I2S_MMAP)
3004 +               dma_sync_single_for_device(NULL,  i2s_mmap_addr[tx_r_idx], I2S_PAGE_SIZE, DMA_TO_DEVICE);
3005 +#if defined(ARM_ARCH)
3006 +               GdmaI2sTx(i2s_mmap_addr[tx_r_idx], I2S_TX_FIFO_WREG_PHY, 1, I2S_PAGE_SIZE, i2s_dma_tx_handler, i2s_dma_tx_unmask_handler);
3007 +#else
3008 +                GdmaI2sTx((u32)(pi2s_config->pMMAPTxBufPtr[tx_r_idx]), I2S_TX_FIFO_WREG, 1, I2S_PAGE_SIZE, i2s_dma_tx_handler, i2s_dma_tx_unmask_handler);
3009 +#endif
3010 +#else
3011 +                memcpy(pi2s_config->pPage1TxBuf8ptr,  pi2s_config->pMMAPTxBufPtr[tx_r_idx], I2S_PAGE_SIZE);
3012 +#if defined(ARM_ARCH)
3013 +               GdmaI2sTx(i2s_txdma_addr1, I2S_TX_FIFO_WREG_PHY, 1, I2S_PAGE_SIZE, i2s_dma_tx_handler, i2s_dma_tx_unmask_handler);
3014 +#else
3015 +                GdmaI2sTx((u32)(pi2s_config->pPage1TxBuf8ptr), I2S_TX_FIFO_WREG, 1, I2S_PAGE_SIZE, i2s_dma_tx_handler, i2s_dma_tx_unmask_handler);
3016 +#endif
3017 +#endif
3018 +                pi2s_config->dmach = GDMA_I2S_TX1;
3019 +                pi2s_config->tx_r_idx = (pi2s_config->tx_r_idx+1)%MAX_I2S_PAGE;
3020 +       }
3021 +#if defined(CONFIG_I2S_WITH_AEC)
3022 +       if(aecFuncP->AECFeEnq){
3023 +               aecFuncP->AECFeEnq(0,pi2s_config->pMMAPTxBufPtr[pi2s_config->tx_r_idx],I2S_PAGE_SIZE);
3024 +       }
3025 +#endif
3026 +       return 0;
3027 +}
3028 +
3029 +int i2s_dma_tx_transf_zero(i2s_config_type* ptri2s_config, u32 dma_ch)
3030 +{
3031 +       if(dma_ch==GDMA_I2S_TX0)
3032 +        {
3033 +               memset(pi2s_config->pPage0TxBuf8ptr, 0, I2S_PAGE_SIZE);
3034 +#if defined(ARM_ARCH)
3035 +               GdmaI2sTx(i2s_txdma_addr0, I2S_TX_FIFO_WREG_PHY, 0, I2S_PAGE_SIZE, i2s_dma_tx_handler, i2s_dma_tx_unmask_handler);
3036 +#else
3037 +                GdmaI2sTx((u32)pi2s_config->pPage0TxBuf8ptr, I2S_TX_FIFO_WREG, 0, I2S_PAGE_SIZE, i2s_dma_tx_handler, i2s_dma_tx_unmask_handler);
3038 +#endif
3039 +        }
3040 +        else
3041 +        {
3042 +                memset(pi2s_config->pPage1TxBuf8ptr, 0, I2S_PAGE_SIZE);
3043 +#if defined(ARM_ARCH)
3044 +               GdmaI2sTx(i2s_txdma_addr1, I2S_TX_FIFO_WREG_PHY, 1, I2S_PAGE_SIZE, i2s_dma_tx_handler, i2s_dma_tx_unmask_handler);
3045 +#else
3046 +                GdmaI2sTx((u32)pi2s_config->pPage1TxBuf8ptr, I2S_TX_FIFO_WREG, 1, I2S_PAGE_SIZE, i2s_dma_tx_handler, i2s_dma_tx_unmask_handler);
3047 +#endif
3048 +        }
3049 +       return 0;
3050 +}
3051 +
3052 +int i2s_dma_rx_transf_data(i2s_config_type* ptri2s_config, u32 dma_ch)
3053 +{
3054 +       int rx_w_idx;
3055 +
3056 +       pi2s_config->rx_w_idx = (pi2s_config->rx_w_idx+1)%MAX_I2S_PAGE;
3057 +
3058 +       if ((pi2s_config->bALSAEnable==1) && (pi2s_config->bALSAMMAPEnable==1))
3059 +               rx_w_idx = (pi2s_config->rx_w_idx+ALSA_MMAP_IDX_SHIFT)%MAX_I2S_PAGE;
3060 +       else
3061 +               rx_w_idx = (pi2s_config->rx_w_idx)%MAX_I2S_PAGE;
3062 +
3063 +       if(dma_ch==GDMA_I2S_RX0)
3064 +        {
3065 +
3066 +#ifdef CONFIG_I2S_MMAP
3067 +                dma_sync_single_for_device(NULL,  i2s_mmap_addr[rx_w_idx+(pi2s_config->mmap_index-MAX_I2S_PAGE)], I2S_PAGE_SIZE, DMA_FROM_DEVICE);
3068 +#if defined(ARM_ARCH)
3069 +               GdmaI2sRx(I2S_RX_FIFO_RREG_PHY, (u32)i2s_mmap_addr[rx_w_idx+(pi2s_config->mmap_index-MAX_I2S_PAGE)], 0, I2S_PAGE_SIZE, i2s_dma_rx_handler, i2s_dma_rx_unmask_handler);
3070 +#else
3071 +                GdmaI2sRx(I2S_RX_FIFO_RREG, (u32)(pi2s_config->pMMAPRxBufPtr[rx_w_idx]), 0, I2S_PAGE_SIZE, i2s_dma_rx_handler, i2s_dma_rx_unmask_handler);
3072 +#endif
3073 +#else
3074 +                memcpy(pi2s_config->pMMAPRxBufPtr[rx_w_idx], pi2s_config->pPage0RxBuf8ptr, I2S_PAGE_SIZE);
3075 +#if defined(ARM_ARCH)
3076 +               GdmaI2sRx(I2S_RX_FIFO_RREG_PHY, i2s_rxdma_addr0, 0, I2S_PAGE_SIZE, i2s_dma_rx_handler, i2s_dma_rx_unmask_handler);
3077 +#else
3078 +                GdmaI2sRx(I2S_RX_FIFO_RREG, (u32)(pi2s_config->pPage0RxBuf8ptr), 0, I2S_PAGE_SIZE, i2s_dma_rx_handler, i2s_dma_rx_unmask_handler);
3079 +#endif
3080 +#endif
3081 +                pi2s_config->dmach = GDMA_I2S_RX0;
3082 +        }
3083 +       else
3084 +        {
3085 +
3086 +#ifdef CONFIG_I2S_MMAP
3087 +                dma_sync_single_for_device(NULL,  i2s_mmap_addr[rx_w_idx+(pi2s_config->mmap_index-MAX_I2S_PAGE)], I2S_PAGE_SIZE, DMA_FROM_DEVICE);
3088 +#if defined(ARM_ARCH)
3089 +               GdmaI2sRx(I2S_RX_FIFO_RREG_PHY, (u32)i2s_mmap_addr[rx_w_idx+(pi2s_config->mmap_index-MAX_I2S_PAGE)], 1, I2S_PAGE_SIZE, i2s_dma_rx_handler, i2s_dma_rx_unmask_handler);
3090 +#else
3091 +                GdmaI2sRx(I2S_RX_FIFO_RREG, (u32)(pi2s_config->pMMAPRxBufPtr[rx_w_idx]), 1, I2S_PAGE_SIZE, i2s_dma_rx_handler, i2s_dma_rx_unmask_handler);
3092 +#endif
3093 +#else
3094 +                memcpy(pi2s_config->pMMAPRxBufPtr[rx_w_idx], pi2s_config->pPage1RxBuf8ptr, I2S_PAGE_SIZE);
3095 +#if defined(ARM_ARCH)
3096 +               GdmaI2sRx(I2S_RX_FIFO_RREG_PHY, i2s_rxdma_addr1, 1, I2S_PAGE_SIZE, i2s_dma_rx_handler, i2s_dma_rx_unmask_handler);
3097 +#else
3098 +                GdmaI2sRx(I2S_RX_FIFO_RREG, (u32)(pi2s_config->pPage1RxBuf8ptr), 1, I2S_PAGE_SIZE, i2s_dma_rx_handler, i2s_dma_rx_unmask_handler);
3099 +#endif
3100 +#endif
3101 +                pi2s_config->dmach = GDMA_I2S_RX1;
3102 +
3103 +        }
3104 +#if defined(CONFIG_I2S_WITH_AEC)
3105 +               if(aecFuncP->AECNeEnq){
3106 +                       aecFuncP->AECNeEnq(0,pi2s_config->pMMAPRxBufPtr[rx_w_idx],I2S_PAGE_SIZE);
3107 +               }
3108 +#endif
3109 +       return 0;
3110 +}
3111 +
3112 +int i2s_dma_rx_transf_zero(i2s_config_type* ptri2s_config, u32 dma_ch)
3113 +{
3114 +       if(dma_ch==GDMA_I2S_RX0)
3115 +        {
3116 +               memset(pi2s_config->pPage0RxBuf8ptr, 0, I2S_PAGE_SIZE);
3117 +#if defined(ARM_ARCH)
3118 +               GdmaI2sRx(I2S_RX_FIFO_RREG_PHY, i2s_rxdma_addr0, 0, I2S_PAGE_SIZE, i2s_dma_rx_handler, i2s_dma_rx_unmask_handler);
3119 +#else
3120 +               GdmaI2sRx(I2S_RX_FIFO_RREG, (u32)pi2s_config->pPage0RxBuf8ptr, 0, I2S_PAGE_SIZE, i2s_dma_rx_handler, i2s_dma_rx_unmask_handler);
3121 +#endif
3122 +        }
3123 +        else
3124 +               {
3125 +               memset(pi2s_config->pPage1RxBuf8ptr, 0, I2S_PAGE_SIZE);
3126 +#if defined(ARM_ARCH)
3127 +               GdmaI2sRx(I2S_RX_FIFO_RREG_PHY, i2s_rxdma_addr1, 1, I2S_PAGE_SIZE, i2s_dma_rx_handler, i2s_dma_rx_unmask_handler);
3128 +#else
3129 +                GdmaI2sRx(I2S_RX_FIFO_RREG, (u32)pi2s_config->pPage1RxBuf8ptr, 1, I2S_PAGE_SIZE, i2s_dma_rx_handler, i2s_dma_rx_unmask_handler);
3130 +#endif
3131 +        }
3132 +       return 0;
3133 +}
3134 +
3135 +void i2s_dma_tx_handler(u32 dma_ch)
3136 +{
3137 +       pi2s_config->enLable = 1; /* TX:enLabel=1; RX:enLabel=2 */
3138 +
3139 +       if(pi2s_config->bTxDMAEnable==0)
3140 +       {
3141 +               if(pi2s_config->end_cnt != 0)
3142 +               {
3143 +                       i2s_dma_tx_transf_data(pi2s_config, dma_ch);
3144 +                       pi2s_config->end_cnt --;
3145 +                       MSG("end_cnt = %d, r_idx = %d\n", pi2s_config->end_cnt, pi2s_config->tx_r_idx);
3146 +               }
3147 +               else
3148 +               {
3149 +                       pi2s_config->tx_stop_cnt++;
3150 +                       i2s_dma_tx_soft_stop(pi2s_config, dma_ch);
3151 +                       MSG("tx_stop=%d, ch=%d\n", pi2s_config->tx_stop_cnt, dma_ch);
3152 +                       if (pi2s_config->tx_stop_cnt == 3)
3153 +                       {
3154 +                               wake_up_interruptible(&(pi2s_config->i2s_tx_qh));
3155 +                               _printk("T:wake up!!\n");
3156 +                       }
3157 +               }
3158 +               return;
3159 +       }
3160 +
3161 +       pi2s_config->tx_isr_cnt++;
3162 +
3163 +#ifdef         I2S_STATISTIC
3164 +       i2s_int_status(dma_ch);
3165 +#endif
3166 +       /* FIXME */
3167 +       if(pi2s_config->bALSAEnable)
3168 +       {
3169 +               if(pi2s_config->dmaStat[STREAM_PLAYBACK])
3170 +               {
3171 +                       if(!pi2s_config->bTrigger[STREAM_PLAYBACK]){
3172 +                               //_printk("trigger stop: rIdx:%d widx:%d\n", pi2s_config->tx_r_idx,pi2s_config->tx_w_idx);
3173 +                                i2s_dma_tx_transf_zero(pi2s_config, dma_ch);
3174 +                                if(pi2s_config->bPreTrigger[STREAM_PLAYBACK]){
3175 +                                        /* mtk04880 commented:
3176 +                                         * for corner case, there are cases which ALSA Trigger stop before disabling DMA.
3177 +                                         * For which case, it needs to keep call snd_pcm_elapased to keep ALSA hw ptr updating.
3178 +                                         * It is so called post stop handlment.
3179 +                                         */
3180 +                                        //_printk("post-stop\n");
3181 +                                        goto EXIT;
3182 +                                }
3183 +                                else{
3184 +                                        //_printk("pre-stop\n");
3185 +                                        wake_up_interruptible(&(pi2s_config->i2s_tx_qh));
3186 +                                        return;
3187 +                                }
3188 +                        }
3189 +                        else{
3190 +                                if(!pi2s_config->bPreTrigger[STREAM_PLAYBACK])
3191 +                                        pi2s_config->bPreTrigger[STREAM_PLAYBACK] = 1;
3192 +
3193 +                       }
3194 +               }
3195 +       }
3196 +       else
3197 +       {
3198 +               if(pi2s_config->tx_r_idx==pi2s_config->tx_w_idx)
3199 +               {
3200 +                       /* Buffer Empty */
3201 +                       MSG("TXBE r=%d w=%d[i=%u,c=%u]\n",pi2s_config->tx_r_idx,pi2s_config->tx_w_idx,pi2s_config->tx_isr_cnt,dma_ch);
3202 +#ifdef I2S_STATISTIC
3203 +                       pi2s_status->txbuffer_unrun++;
3204 +#endif
3205 +                       i2s_dma_tx_transf_zero(pi2s_config, dma_ch);
3206 +                       goto EXIT;
3207 +               }
3208 +       }
3209 +
3210 +       if(pi2s_config->pMMAPTxBufPtr[pi2s_config->tx_r_idx]==NULL)
3211 +       {
3212 +               MSG("mmap buf NULL [%d]\n",pi2s_config->tx_r_idx);
3213 +               i2s_dma_tx_transf_zero(pi2s_config, dma_ch);
3214 +
3215 +               goto EXIT;
3216 +       }
3217 +
3218 +       if(pi2s_config->tx_pause_en == 1)
3219 +       {
3220 +               /* Enable PAUSE */
3221 +               MSG("TX pause now\n");
3222 +               i2s_dma_tx_transf_zero(pi2s_config, dma_ch);
3223 +
3224 +               goto EXIT;
3225 +       }
3226 +
3227 +#ifdef I2S_STATISTIC
3228 +       pi2s_status->txbuffer_len--;
3229 +#endif
3230 +       i2s_dma_tx_transf_data(pi2s_config, dma_ch);
3231 +
3232 +EXIT:
3233 +#if defined(CONFIG_SND_MT76XX_SOC)
3234 +       if(pi2s_config->bALSAEnable == 1){
3235 +               if(pi2s_config->pss[STREAM_PLAYBACK])
3236 +                       snd_pcm_period_elapsed(pi2s_config->pss[STREAM_PLAYBACK]);
3237 +       }
3238 +#endif
3239 +       wake_up_interruptible(&(pi2s_config->i2s_tx_qh));
3240 +       return;
3241 +}
3242 +
3243 +void i2s_dma_rx_handler(u32 dma_ch)
3244 +{
3245 +       pi2s_config->enLable = 2; /* TX:enLabel=1; RX:enLabel=2 */
3246 +#if defined(CONFIG_I2S_TXRX)
3247 +       if(pi2s_config->rx_isr_cnt==0)
3248 +       {
3249 +               pi2s_config->next_p0_idx = 0;
3250 +               pi2s_config->next_p1_idx = 1;
3251 +       }
3252 +       pi2s_config->rx_isr_cnt++;
3253 +
3254 +#ifdef  I2S_STATISTIC
3255 +       i2s_int_status(dma_ch);
3256 +#endif
3257 +
3258 +       if (pi2s_config->bRxDMAEnable==0)
3259 +       {
3260 +               pi2s_config->rx_stop_cnt++;
3261 +               i2s_dma_rx_soft_stop(pi2s_config, dma_ch);
3262 +               MSG("rx_stop=%d\n", pi2s_config->rx_stop_cnt);
3263 +
3264 +               if(pi2s_config->rx_stop_cnt == 2)
3265 +               {
3266 +                       wake_up_interruptible(&(pi2s_config->i2s_rx_qh));
3267 +                       _printk("R:wake up!!\n");
3268 +               }
3269 +               return;
3270 +       }
3271 +
3272 +       if(pi2s_config->bALSAEnable)
3273 +       {
3274 +                if(pi2s_config->dmaStat[STREAM_CAPTURE]){
3275 +                       if(!pi2s_config->bTrigger[STREAM_CAPTURE]){
3276 +                                MSG("trigger stop: rIdx:%d widx:%d\n", pi2s_config->rx_r_idx,pi2s_config->rx_w_idx);
3277 +                               i2s_dma_rx_transf_zero(pi2s_config, dma_ch);
3278 +                                wake_up_interruptible(&(pi2s_config->i2s_rx_qh));
3279 +                                return;
3280 +                       }
3281 +                }
3282 +       }
3283 +       else
3284 +       {
3285 +               if(((pi2s_config->rx_w_idx+1)%MAX_I2S_PAGE)==pi2s_config->rx_r_idx){
3286 +                       /* Buffer Full */
3287 +                       MSG("RXBF r=%d w=%d[i=%u,c=%u]\n",pi2s_config->rx_r_idx,pi2s_config->rx_w_idx,pi2s_config->rx_isr_cnt,dma_ch);
3288 +#ifdef I2S_STATISTIC
3289 +                       pi2s_status->rxbuffer_unrun++;
3290 +#endif
3291 +                       i2s_dma_rx_transf_zero(pi2s_config, dma_ch);
3292 +                       goto EXIT;
3293 +               }
3294 +       }
3295 +
3296 +       if(pi2s_config->rx_pause_en == 1)
3297 +       {
3298 +               /* Enable PAUSE */
3299 +               i2s_dma_rx_transf_zero(pi2s_config, dma_ch);
3300 +
3301 +               goto EXIT;
3302 +       }
3303 +
3304 +#ifdef I2S_STATISTIC
3305 +       pi2s_status->rxbuffer_len++;
3306 +#endif
3307 +       i2s_dma_rx_transf_data(pi2s_config, dma_ch);
3308 +
3309 +EXIT:
3310 +#if defined(CONFIG_SND_MT76XX_SOC)
3311 +       if(pi2s_config->bALSAEnable == 1){
3312 +               if(pi2s_config->pss[STREAM_CAPTURE])
3313 +                       snd_pcm_period_elapsed(pi2s_config->pss[STREAM_CAPTURE]);
3314 +       }
3315 +#endif
3316 +       wake_up_interruptible(&(pi2s_config->i2s_rx_qh));
3317 +#endif
3318 +       return;
3319 +}
3320 +
3321 +#ifdef I2S_STATISTIC
3322 +void i2s_int_status(u32 dma_ch)
3323 +{
3324 +       u32 i2s_status;
3325 +
3326 +       if((pi2s_config->tx_isr_cnt>0)||(pi2s_config->rx_isr_cnt>0))
3327 +       {
3328 +               i2s_status = i2s_inw(I2S_INT_STATUS);
3329 +
3330 +               if(i2s_status&REGBIT(1, I2S_TX_DMA_FAULT))
3331 +               {
3332 +                       pi2s_status->txdmafault++;
3333 +               }
3334 +               if(i2s_status&REGBIT(1, I2S_TX_OVRUN))
3335 +               {
3336 +                       pi2s_status->txovrun++;
3337 +               }
3338 +               if(i2s_status&REGBIT(1, I2S_TX_UNRUN))
3339 +               {
3340 +                       pi2s_status->txunrun++;
3341 +               }
3342 +               if(i2s_status&REGBIT(1, I2S_TX_THRES))
3343 +               {
3344 +                       pi2s_status->txthres++;
3345 +               }
3346 +               if(i2s_status&REGBIT(1, I2S_RX_DMA_FAULT))
3347 +               {
3348 +                       pi2s_status->rxdmafault++;
3349 +               }
3350 +               if(i2s_status&REGBIT(1, I2S_RX_OVRUN))
3351 +               {
3352 +                       pi2s_status->rxovrun++;
3353 +               }
3354 +               if(i2s_status&REGBIT(1, I2S_RX_UNRUN))
3355 +               {
3356 +                       pi2s_status->rxunrun++;
3357 +               }
3358 +               if(i2s_status&REGBIT(1, I2S_RX_THRES))
3359 +               {
3360 +                       pi2s_status->rxthres++;
3361 +               }
3362 +       }
3363 +#if 0
3364 +       if(pi2s_config->enLable == 1)
3365 +       {
3366 +               if((pi2s_config->tx_isr_cnt>0) && (pi2s_config->tx_isr_cnt%40==0))
3367 +               {
3368 +                       MSG("tisr i=%u,ch=%u,o=%u,u=%d,s=%X [r=%d,w=%d]\n",\
3369 +                               pi2s_config->tx_isr_cnt,dma_ch,pi2s_status->txovrun,pi2s_status->txunrun,\
3370 +                               i2s_inw(I2S_INT_STATUS),pi2s_config->tx_r_idx,pi2s_config->tx_w_idx);
3371 +               }
3372 +       }
3373 +
3374 +       if(pi2s_config->enLable == 2)
3375 +       {
3376 +               if((pi2s_config->rx_isr_cnt>0) && (pi2s_config->rx_isr_cnt%40==0))
3377 +               {
3378 +                       MSG("risr i=%u,ch=%u,o=%u,u=%d,s=%X [r=%d,w=%d]\n",\
3379 +                               pi2s_config->rx_isr_cnt,dma_ch,pi2s_status->rxovrun,pi2s_status->rxunrun,\
3380 +                               i2s_inw(I2S_INT_STATUS),pi2s_config->rx_r_idx,pi2s_config->rx_w_idx);
3381 +               }
3382 +       }
3383 +#endif
3384 +
3385 +       *(unsigned long*)(I2S_INT_STATUS) = 0xFFFFFFFF;
3386 +}
3387 +#endif
3388 +
3389 +#if defined(I2S_HW_INTERRUPT_EN)&&(I2S_SW_IRQ_EN)
3390 +irqreturn_t i2s_irq_isr(int irq, void *irqaction)
3391 +{
3392 +       u32 i2s_status;
3393 +
3394 +       //MSG("i2s_irq_isr [0x%08X]\n",i2s_inw(I2S_INT_STATUS));
3395 +       if((pi2s_config->tx_isr_cnt>0)||(pi2s_config->rx_isr_cnt>0))
3396 +       {
3397 +               i2s_status = i2s_inw(I2S_INT_STATUS);
3398 +               MSG("i2s_irq_isr [0x%08X]\n",i2s_status);
3399 +       }
3400 +       else
3401 +               return IRQ_HANDLED;
3402 +
3403 +       if(i2s_status&REGBIT(1, I2S_TX_DMA_FAULT))
3404 +       {
3405 +#ifdef I2S_STATISTIC
3406 +               pi2s_status->txdmafault++;
3407 +#endif
3408 +       }
3409 +       if(i2s_status&REGBIT(1, I2S_TX_OVRUN))
3410 +       {
3411 +#ifdef I2S_STATISTIC
3412 +               pi2s_status->txovrun++;
3413 +#endif
3414 +       }
3415 +       if(i2s_status&REGBIT(1, I2S_TX_UNRUN))
3416 +       {
3417 +#ifdef I2S_STATISTIC
3418 +               pi2s_status->txunrun++;
3419 +#endif
3420 +       }
3421 +       if(i2s_status&REGBIT(1, I2S_TX_THRES))
3422 +       {
3423 +#ifdef I2S_STATISTIC
3424 +               pi2s_status->txthres++;
3425 +#endif
3426 +       }
3427 +       if(i2s_status&REGBIT(1, I2S_RX_DMA_FAULT))
3428 +       {
3429 +#ifdef I2S_STATISTIC
3430 +               pi2s_status->rxdmafault++;
3431 +#endif
3432 +       }
3433 +       if(i2s_status&REGBIT(1, I2S_RX_OVRUN))
3434 +       {
3435 +#ifdef I2S_STATISTIC
3436 +               pi2s_status->rxovrun++;
3437 +#endif
3438 +       }
3439 +       if(i2s_status&REGBIT(1, I2S_RX_UNRUN))
3440 +       {
3441 +#ifdef I2S_STATISTIC
3442 +               pi2s_status->rxunrun++;
3443 +#endif
3444 +       }
3445 +       if(i2s_status&REGBIT(1, I2S_RX_THRES))
3446 +       {
3447 +#ifdef I2S_STATISTIC
3448 +               pi2s_status->rxthres++;
3449 +#endif
3450 +       }
3451 +       i2s_outw(I2S_INT_STATUS, 0xFFFFFFFF);
3452 +       return IRQ_HANDLED;
3453 +}
3454 +#endif
3455 +
3456 +void i2s_tx_task(unsigned long pData)
3457 +{
3458 +       unsigned long flags;
3459 +       spin_lock_irqsave(&pi2s_config->lock, flags);
3460 +       //if (pi2s_config->bTxDMAEnable!=0)
3461 +       {
3462 +               if (pi2s_config->tx_unmask_ch!=0)
3463 +               {
3464 +                       u32 dmach = pi2s_config->tx_unmask_ch;
3465 +                       u32 ch;
3466 +                       for (ch = 0; ch < 16; ch++)
3467 +                       {
3468 +                               if (dmach& (1<<ch))
3469 +                               {
3470 +                                       MSG("do unmask ch%d tisr=%d in tx_isr\n",ch,pi2s_config->tx_isr_cnt);
3471 +                                       GdmaUnMaskChannel(ch);
3472 +                               }
3473 +                       }
3474 +                       pi2s_config->tx_unmask_ch = 0;
3475 +               }
3476 +       }
3477 +       spin_unlock_irqrestore(&pi2s_config->lock, flags);
3478 +}
3479 +
3480 +void i2s_rx_task(unsigned long pData)
3481 +{
3482 +       unsigned long flags;
3483 +       spin_lock_irqsave(&pi2s_config->lock, flags);
3484 +       //if (pi2s_config->bRxDMAEnable!=0)
3485 +       {
3486 +               if (pi2s_config->rx_unmask_ch!=0)
3487 +               {
3488 +                       u32 dmach = pi2s_config->rx_unmask_ch;
3489 +                       u32 ch;
3490 +                       for (ch = 0; ch < 16; ch++)
3491 +                       {
3492 +                               if (dmach& (1<<ch))
3493 +                               {
3494 +                                       MSG("do unmask ch%d risr=%d in rx_isr\n",ch,pi2s_config->rx_isr_cnt);
3495 +                                       GdmaUnMaskChannel(ch);
3496 +                               }
3497 +                       }
3498 +                       pi2s_config->rx_unmask_ch = 0;
3499 +
3500 +               }
3501 +       }
3502 +       spin_unlock_irqrestore(&pi2s_config->lock, flags);
3503 +}
3504 +
3505 +
3506 +void i2s_dma_unmask_handler(u32 dma_ch)
3507 +{
3508 +       MSG("i2s_dma_unmask_handler ch=%d\n",dma_ch);
3509 +
3510 +       GdmaUnMaskChannel(dma_ch);
3511 +
3512 +       return;
3513 +}
3514 +
3515 +void i2s_dma_tx_unmask_handler(u32 dma_ch)
3516 +{
3517 +       MSG("i2s_dma_tx_unmask_handler ch=%d\n",dma_ch);
3518 +       pi2s_config->tx_unmask_ch |= (1<<dma_ch);
3519 +       tasklet_hi_schedule(&i2s_tx_tasklet);
3520 +       return;
3521 +}
3522 +
3523 +void i2s_dma_rx_unmask_handler(u32 dma_ch)
3524 +{
3525 +       MSG("i2s_dma_rx_unmask_handler ch=%d\n",dma_ch);
3526 +       pi2s_config->rx_unmask_ch |= (1<<dma_ch);
3527 +       tasklet_hi_schedule(&i2s_rx_tasklet);
3528 +       return;
3529 +}
3530 +
3531 +void i2s_dma_mask_handler(u32 dma_ch)
3532 +{
3533 +        MSG("i2s_dma_mask_handler ch=%d\n", dma_ch);
3534 +        GdmaMaskChannel(dma_ch);
3535 +        return;
3536 +}
3537 +
3538 +void i2s_dma_tx_init(i2s_config_type* ptri2s_config)
3539 +{
3540 +       memset(pi2s_config->pPage0TxBuf8ptr, 0, I2S_PAGE_SIZE);
3541 +       memset(pi2s_config->pPage1TxBuf8ptr, 0, I2S_PAGE_SIZE);
3542 +#if defined(ARM_ARCH)
3543 +       GdmaI2sTx(i2s_txdma_addr0, I2S_TX_FIFO_WREG_PHY, 0, I2S_PAGE_SIZE, i2s_dma_tx_handler, i2s_dma_tx_unmask_handler);
3544 +       GdmaI2sTx(i2s_txdma_addr1, I2S_TX_FIFO_WREG_PHY, 1, I2S_PAGE_SIZE, i2s_dma_tx_handler, i2s_dma_tx_unmask_handler);
3545 +#else
3546 +       GdmaI2sTx((u32)ptri2s_config->pPage0TxBuf8ptr, I2S_FIFO_WREG, 0, I2S_PAGE_SIZE, i2s_dma_tx_handler, i2s_dma_tx_unmask_handler);
3547 +       GdmaI2sTx((u32)ptri2s_config->pPage1TxBuf8ptr, I2S_FIFO_WREG, 1, I2S_PAGE_SIZE, i2s_dma_tx_handler, i2s_dma_tx_unmask_handler);
3548 +#endif
3549 +
3550 +       return;
3551 +}
3552 +
3553 +void i2s_dma_rx_init(i2s_config_type* ptri2s_config)
3554 +{
3555 +       memset(pi2s_config->pPage0RxBuf8ptr, 0, I2S_PAGE_SIZE);
3556 +       memset(pi2s_config->pPage1RxBuf8ptr, 0, I2S_PAGE_SIZE);
3557 +
3558 +#if defined(ARM_ARCH)
3559 +       GdmaI2sRx(I2S_RX_FIFO_RREG_PHY, i2s_rxdma_addr0, 0, I2S_PAGE_SIZE, i2s_dma_rx_handler, i2s_dma_rx_unmask_handler);
3560 +       GdmaI2sRx(I2S_RX_FIFO_RREG_PHY, i2s_rxdma_addr1, 1, I2S_PAGE_SIZE, i2s_dma_rx_handler, i2s_dma_rx_unmask_handler);
3561 +#else
3562 +       GdmaI2sRx(I2S_RX_FIFO_RREG, (u32)ptri2s_config->pPage0RxBuf8ptr, 0, I2S_PAGE_SIZE, i2s_dma_rx_handler, i2s_dma_rx_unmask_handler);
3563 +       GdmaI2sRx(I2S_RX_FIFO_RREG, (u32)ptri2s_config->pPage1RxBuf8ptr, 1, I2S_PAGE_SIZE, i2s_dma_rx_handler, i2s_dma_rx_unmask_handler);
3564 +#endif
3565 +
3566 +       return;
3567 +}
3568 +
3569 +void i2s_dma_tx_end_handle(i2s_config_type* ptri2s_config)
3570 +{
3571 +       if (ptri2s_config->tx_w_idx < ptri2s_config->tx_r_idx)
3572 +        {
3573 +               ptri2s_config->end_cnt = (ptri2s_config->tx_w_idx + MAX_I2S_PAGE)-ptri2s_config->tx_r_idx;
3574 +                _printk("case1: w=%d, r=%d, end=%d\n", ptri2s_config->tx_w_idx, ptri2s_config->tx_r_idx, ptri2s_config->end_cnt);
3575 +        }
3576 +        else if (ptri2s_config->tx_w_idx > ptri2s_config->tx_r_idx)
3577 +        {
3578 +                ptri2s_config->end_cnt = ptri2s_config->tx_w_idx-ptri2s_config->tx_r_idx;
3579 +                _printk("case2: w=%d, r=%d, end=%d\n", ptri2s_config->tx_w_idx, ptri2s_config->tx_r_idx, ptri2s_config->end_cnt);
3580 +        }
3581 +       else
3582 +       {
3583 +               _printk("case3: w=%d, r=%d, end=%d\n", ptri2s_config->tx_w_idx, ptri2s_config->tx_r_idx, ptri2s_config->end_cnt);
3584 +
3585 +       }
3586 +
3587 +       if (ptri2s_config->end_cnt > 0)
3588 +       {
3589 +               interruptible_sleep_on(&(ptri2s_config->i2s_tx_qh));
3590 +       }
3591 +
3592 +       return;
3593 +}
3594 +
3595 +void i2s_tx_end_sleep_on(i2s_config_type* ptri2s_config)
3596 +{
3597 +       while(ptri2s_config->tx_stop_cnt<3)
3598 +               interruptible_sleep_on(&(ptri2s_config->i2s_tx_qh));
3599 +
3600 +       return;
3601 +}
3602 +
3603 +void i2s_rx_end_sleep_on(i2s_config_type* ptri2s_config)
3604 +{
3605 +       while(ptri2s_config->rx_stop_cnt<2)
3606 +               interruptible_sleep_on(&(ptri2s_config->i2s_rx_qh));
3607 +       return;
3608 +}
3609 +
3610 +int i2s_dma_tx_soft_stop(i2s_config_type* ptri2s_config, u32 dma_ch)
3611 +{
3612 +       if(dma_ch==GDMA_I2S_TX0)
3613 +        {
3614 +#if defined(ARM_ARCH)
3615 +               GdmaI2sTx(i2s_txdma_addr0, I2S_TX_FIFO_WREG_PHY, 0, 4, i2s_dma_tx_handler, i2s_dma_tx_unmask_handler);
3616 +#else
3617 +               GdmaI2sTx((u32)pi2s_config->pPage0TxBuf8ptr, I2S_TX_FIFO_WREG, 0, 4, i2s_dma_tx_handler, i2s_dma_tx_unmask_handler);
3618 +#endif
3619 +        }
3620 +        else
3621 +        {
3622 +#if defined(ARM_ARCH)
3623 +               GdmaI2sTx(i2s_txdma_addr1, I2S_TX_FIFO_WREG_PHY, 1, 4, i2s_dma_tx_handler, i2s_dma_tx_unmask_handler);
3624 +#else
3625 +                GdmaI2sTx((u32)pi2s_config->pPage1TxBuf8ptr, I2S_TX_FIFO_WREG, 1, 4, i2s_dma_tx_handler, i2s_dma_tx_unmask_handler);
3626 +#endif
3627 +        }
3628 +
3629 +       return 0;
3630 +}
3631 +
3632 +int i2s_dma_rx_soft_stop(i2s_config_type* ptri2s_config, u32 dma_ch)
3633 +{
3634 +       if(dma_ch==GDMA_I2S_RX0)
3635 +        {
3636 +               memset(pi2s_config->pPage0RxBuf8ptr, 0, I2S_PAGE_SIZE);
3637 +#if defined(ARM_ARCH)
3638 +               GdmaI2sRx(I2S_RX_FIFO_RREG_PHY, i2s_rxdma_addr0, 0, 4, i2s_dma_rx_handler, i2s_dma_rx_unmask_handler);
3639 +#else
3640 +               GdmaI2sRx(I2S_RX_FIFO_RREG, (u32)pi2s_config->pPage0RxBuf8ptr, 0, 4, i2s_dma_rx_handler, i2s_dma_rx_unmask_handler);
3641 +#endif
3642 +        }
3643 +        else
3644 +        {
3645 +               memset(pi2s_config->pPage1RxBuf8ptr, 0, I2S_PAGE_SIZE);
3646 +#if defined(ARM_ARCH)
3647 +               GdmaI2sRx(I2S_RX_FIFO_RREG_PHY, i2s_rxdma_addr1, 1, 4, i2s_dma_rx_handler, i2s_dma_rx_unmask_handler);
3648 +#else
3649 +                GdmaI2sRx(I2S_RX_FIFO_RREG, (u32)pi2s_config->pPage1RxBuf8ptr, 1, 4, i2s_dma_rx_handler, i2s_dma_rx_unmask_handler);
3650 +#endif
3651 +        }
3652 +
3653 +       return 0;
3654 +}
3655 +
3656 +void i2s_gen_test_pattern(void)
3657 +{
3658 +       int i;
3659 +       for (i=0; i<I2S_PAGE_SIZE; i++)
3660 +       {
3661 +               test_buf[i] = 0x5A;
3662 +               test_buf_1[i] = 0x11;
3663 +               test_buf_2[i] = 0x22;
3664 +
3665 +       }
3666 +}
3667 +
3668 +int i2s_put_audio(i2s_config_type* ptri2s_config, unsigned long arg)
3669 +{
3670 +       unsigned long flags;
3671 +       int tx_w_idx;
3672 +
3673 +       do{
3674 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
3675 +
3676 +               if(((ptri2s_config->tx_w_idx+4)%MAX_I2S_PAGE)!=ptri2s_config->tx_r_idx)
3677 +               {
3678 +                       ptri2s_config->tx_w_idx = (ptri2s_config->tx_w_idx+1)%MAX_I2S_PAGE;
3679 +                       tx_w_idx = ptri2s_config->tx_w_idx;
3680 +                       spin_unlock_irqrestore(&ptri2s_config->lock, flags);
3681 +                       //_printk("put TB[%d] for user write\n",ptri2s_config->tx_w_idx);
3682 +#if defined(CONFIG_I2S_MMAP)
3683 +                       put_user(tx_w_idx, (int*)arg);
3684 +#else
3685 +                       copy_from_user(ptri2s_config->pMMAPTxBufPtr[tx_w_idx], (char*)arg, I2S_PAGE_SIZE);
3686 +#endif
3687 +                       pi2s_status->txbuffer_len++;
3688 +                       //spin_unlock_irqrestore(&ptri2s_config->lock, flags);
3689 +                       break;
3690 +               }
3691 +               else
3692 +               {
3693 +                       /* Buffer Full */
3694 +                       //_printk("TBF tr=%d, tw=%d\n", ptri2s_config->tx_r_idx, ptri2s_config->tx_w_idx);
3695 +                       pi2s_status->txbuffer_ovrun++;
3696 +                       spin_unlock_irqrestore(&ptri2s_config->lock, flags);
3697 +                       interruptible_sleep_on(&(ptri2s_config->i2s_tx_qh));
3698 +                       if (ptri2s_config->bTxDMAEnable==0 && ptri2s_config->end_cnt==0)
3699 +                       {
3700 +                               _printk("wake up for exit i2s driver\n");
3701 +                               put_user(-1, (int*)arg);
3702 +                               break;
3703 +                       }
3704 +               }
3705 +       }while(1);
3706 +
3707 +       return 0;
3708 +}
3709 +
3710 +int i2s_get_audio(i2s_config_type* ptri2s_config, unsigned long arg)
3711 +{
3712 +       unsigned long flags;
3713 +       int rx_r_idx;
3714 +
3715 +       do{
3716 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
3717 +               //_printk("GA rr=%d, rw=%d,i=%d\n", ptri2s_config->rx_r_idx, ptri2s_config->rx_w_idx,ptri2s_config->rx_isr_cnt);
3718 +               if(((ptri2s_config->rx_r_idx+2)%MAX_I2S_PAGE)!=ptri2s_config->rx_w_idx)
3719 +               {
3720 +                       rx_r_idx = ptri2s_config->rx_r_idx;
3721 +                       ptri2s_config->rx_r_idx = (ptri2s_config->rx_r_idx+1)%MAX_I2S_PAGE;
3722 +                       spin_unlock_irqrestore(&ptri2s_config->lock, flags);
3723 +#if defined(CONFIG_I2S_MMAP)
3724 +                       put_user(rx_r_idx, (int*)arg);
3725 +#else
3726 +                       copy_to_user((char*)arg, ptri2s_config->pMMAPRxBufPtr[rx_r_idx], I2S_PAGE_SIZE);
3727 +#endif
3728 +                       //_printk("rx_r_idx=%d\n", ptri2s_config->rx_r_idx);
3729 +                       //ptri2s_config->rx_r_idx = (ptri2s_config->rx_r_idx+1)%MAX_I2S_PAGE;
3730 +                       pi2s_status->rxbuffer_len--;
3731 +                       //spin_unlock_irqrestore(&ptri2s_config->lock, flags);
3732 +                       break;
3733 +               }
3734 +               else
3735 +               {
3736 +                       /* Buffer Full */
3737 +                       //_printk("RBF rr=%d, rw=%d\n", ptri2s_config->rx_r_idx, ptri2s_config->rx_w_idx);
3738 +                       pi2s_status->rxbuffer_ovrun++;
3739 +                       spin_unlock_irqrestore(&ptri2s_config->lock, flags);
3740 +                       interruptible_sleep_on(&(ptri2s_config->i2s_rx_qh));
3741 +               }
3742 +#if defined(CONFIG_I2S_WITH_AEC)
3743 +               if(aecFuncP->AECECDeq){
3744 +                       aecFuncP->AECECDeq(0,pi2s_config->pMMAPRxBufPtr[ptri2s_config->rx_r_idx],I2S_PAGE_SIZE);
3745 +               }
3746 +#endif
3747 +       }while(1);
3748 +
3749 +       return 0;
3750 +}
3751 +
3752 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
3753 +long i2s_ioctl (struct file *filp, unsigned int cmd, unsigned long arg)
3754 +#else
3755 +int i2s_ioctl (struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg)
3756 +#endif
3757 +{
3758 +       int i ;
3759 +       i2s_config_type* ptri2s_config;
3760 +       unsigned long flags;
3761 +
3762 +       ptri2s_config = filp->private_data;
3763 +       switch (cmd) {
3764 +       case I2S_RESET:
3765 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
3766 +               i2s_reset_config(ptri2s_config);
3767 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
3768 +               break;
3769 +       case I2S_SRATE:
3770 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
3771 +#if defined(CONFIG_I2S_WM8960)
3772 +               if((arg>MAX_SRATE_HZ)||(arg<MIN_SRATE_HZ))
3773 +               {
3774 +                       MSG("Audio sampling rate %u should be %d ~ %d Hz. Set SRate to 48000Hz\n", (u32)arg, MIN_SRATE_HZ, MAX_SRATE_HZ);
3775 +                       ptri2s_config->srate = 48000;
3776 +                       spin_unlock(&ptri2s_config->lock);
3777 +                       break;
3778 +               }
3779 +#elif defined(CONFIG_I2S_WM8750)
3780 +               if((arg>MAX_SRATE_HZ)||(arg<MIN_SRATE_HZ))
3781 +               {
3782 +                       MSG("Audio sampling rate %u should be %d ~ %d Hz. Set SRate to 96000Hz\n", (u32)arg, MIN_SRATE_HZ, MAX_SRATE_HZ);
3783 +                       ptri2s_config->srate = 96000;
3784 +                       spin_unlock(&ptri2s_config->lock);
3785 +                       break;
3786 +               }
3787 +#endif
3788 +               ptri2s_config->srate = arg;
3789 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
3790 +               MSG("set audio sampling rate to %d Hz\n", ptri2s_config->srate);
3791 +               break;
3792 +       case I2S_TX_VOL:
3793 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
3794 +
3795 +               if((int)arg > 127)
3796 +                       ptri2s_config->txvol = 127;
3797 +               else if((int)arg < 48)
3798 +                       ptri2s_config->txvol = 48;
3799 +               else
3800 +                       ptri2s_config->txvol = arg;
3801 +
3802 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
3803 +
3804 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
3805 +#if (defined(CONFIG_I2S_WM8750) || defined(CONFIG_I2S_WM8751))
3806 +               audiohw_set_master_vol(arg,arg);
3807 +#elif defined(CONFIG_I2S_WM8960)
3808 +               audiohw_set_lineout_vol(1, ptri2s_config->txvol, ptri2s_config->txvol);
3809 +#endif
3810 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
3811 +               break;
3812 +       case I2S_RX_VOL:
3813 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
3814 +
3815 +               if((int)arg > 63)
3816 +                       ptri2s_config->rxvol = 63;
3817 +               else if((int)arg < 0)
3818 +                       ptri2s_config->rxvol = 0;
3819 +               else
3820 +                       ptri2s_config->rxvol = arg;
3821 +
3822 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
3823 +               break;
3824 +#if defined (CONFIG_RALINK_MT7628) || defined(CONFIG_ARCH_MT7623)
3825 +       case I2S_WORD_LEN:
3826 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
3827 +               if((int)arg == 16)
3828 +               {
3829 +                       ptri2s_config->wordlen_24b = 0;
3830 +                       MSG("Enable 16 bit word length.\n");
3831 +               }
3832 +               else if ((int)arg == 24)
3833 +               {
3834 +                       ptri2s_config->wordlen_24b = 1;
3835 +                       MSG("Enable 24 bit word length.\n");
3836 +               }
3837 +               else
3838 +               {
3839 +                       MSG("MT7628 only support 16bit/24bit word length.\n");
3840 +                       spin_unlock(&ptri2s_config->lock);
3841 +                       break;
3842 +               }
3843 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
3844 +               break;
3845 +       case I2S_ENDIAN_FMT:
3846 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
3847 +               if((int)arg == 1)
3848 +               {
3849 +                       ptri2s_config->little_edn = 1;
3850 +                       MSG("Little endian format.\n");
3851 +               }
3852 +               else
3853 +               {
3854 +                       ptri2s_config->little_edn = 0;
3855 +                       MSG("Big endian format.\n");
3856 +               }
3857 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
3858 +               break;
3859 +#endif
3860 +       case I2S_INTERNAL_LBK:
3861 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
3862 +               if((int)arg == 1)
3863 +               {
3864 +                       ptri2s_config->lbk = 1;
3865 +                       MSG("Enable internal loopback.\n");
3866 +               }
3867 +               else
3868 +               {
3869 +                       ptri2s_config->lbk = 0;
3870 +                       MSG("Disable internal loopback.\n");
3871 +               }
3872 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
3873 +               break;
3874 +       case I2S_EXTERNAL_LBK:
3875 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
3876 +               if((int)arg == 1)
3877 +               {
3878 +                       ptri2s_config->extlbk = 1;
3879 +                       MSG("Enable external loopback.\n");
3880 +               }
3881 +               else
3882 +               {
3883 +                       ptri2s_config->extlbk = 0;
3884 +                       MSG("Disable external loopback.\n");
3885 +               }
3886 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
3887 +               break;
3888 +       case I2S_TXRX_COEXIST:
3889 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
3890 +               if((int)arg == 1)
3891 +               {
3892 +                       ptri2s_config->txrx_coexist = 1;
3893 +                       MSG("TX/RX coexist.\n");
3894 +               }
3895 +               else
3896 +               {
3897 +                       ptri2s_config->txrx_coexist = 0;
3898 +                       MSG("TX/RX coexist.\n");
3899 +               }
3900 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
3901 +               break;
3902 +
3903 +       case I2S_TX_ENABLE:
3904 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
3905 +               MSG("I2S_TXENABLE\n");
3906 +
3907 +               pi2s_config->tx_unmask_ch = 0;
3908 +               tasklet_init(&i2s_tx_tasklet, i2s_tx_task, (u32)pi2s_config);
3909 +
3910 +               pi2s_config->dis_match = 0;
3911 +               pi2s_config->start_cnt = 0;
3912 +               i2s_gen_test_pattern();
3913 +
3914 +               /* allocate tx buffer */
3915 +               i2s_txPagebuf_alloc(ptri2s_config);
3916 +               i2s_txbuf_alloc(ptri2s_config);
3917 +
3918 +               /* Init two dma channels */
3919 +               i2s_dma_tx_init(ptri2s_config);
3920 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
3921 +
3922 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
3923 +               /* Init & config all tx param */
3924 +               i2s_reset_tx_param(ptri2s_config);
3925 +               ptri2s_config->bTxDMAEnable = 1;
3926 +               /* Clear all ALSA related config */
3927 +               ptri2s_config->bALSAEnable = 0;
3928 +               ptri2s_config->bALSAMMAPEnable = 0;
3929 +
3930 +               i2s_tx_config(ptri2s_config);
3931 +
3932 +               if(ptri2s_config->bRxDMAEnable==0)
3933 +                       i2s_clock_enable(ptri2s_config);
3934 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
3935 +
3936 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
3937 +#if defined(CONFIG_I2S_WM8960)||defined(CONFIG_I2S_WM8750)||defined(CONFIG_I2S_WM8751)
3938 +               audiohw_set_lineout_vol(1, ptri2s_config->txvol, ptri2s_config->txvol);
3939 +#endif
3940 +               GdmaUnMaskChannel(GDMA_I2S_TX0);
3941 +
3942 +               i2s_tx_enable(ptri2s_config);
3943 +
3944 +               /* Kick off dma channel */
3945 +               //GdmaUnMaskChannel(GDMA_I2S_TX0);
3946 +
3947 +               MSG("I2S_TXENABLE done\n");
3948 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
3949 +               break;
3950 +       case I2S_TX_DISABLE:
3951 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
3952 +               MSG("I2S_TXDISABLE\n");
3953 +
3954 +               //tasklet_kill(&i2s_tx_tasklet);
3955 +
3956 +               /* Handle tx end data */
3957 +               ptri2s_config->bTxDMAEnable = 0;
3958 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
3959 +
3960 +               i2s_tx_end_sleep_on(ptri2s_config);
3961 +
3962 +               tasklet_kill(&i2s_tx_tasklet);
3963 +
3964 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
3965 +               i2s_reset_tx_param(ptri2s_config);
3966 +               i2s_tx_disable(ptri2s_config);
3967 +               if((ptri2s_config->bRxDMAEnable==0)&&(ptri2s_config->bTxDMAEnable==0))
3968 +                       i2s_clock_disable(ptri2s_config);
3969 +
3970 +               i2s_txbuf_free(ptri2s_config);
3971 +               if(ptri2s_config->mmap_index <= MAX_I2S_PAGE)
3972 +                       ptri2s_config->mmap_index = 0;
3973 +
3974 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
3975 +               break;
3976 +       case I2S_RX_ENABLE:
3977 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
3978 +               MSG("I2S_RXENABLE\n");
3979 +               pi2s_config->rx_unmask_ch = 0;
3980 +               tasklet_init(&i2s_rx_tasklet, i2s_rx_task, (u32)pi2s_config);
3981 +
3982 +               /* allocate rx buffer */
3983 +               i2s_rxPagebuf_alloc(ptri2s_config);
3984 +               i2s_rxbuf_alloc(ptri2s_config);
3985 +
3986 +               /* Init two dma channels */
3987 +               i2s_dma_rx_init(ptri2s_config);
3988 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
3989 +
3990 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
3991 +               /* Init & config all rx param */
3992 +               i2s_reset_rx_param(ptri2s_config);
3993 +               ptri2s_config->bRxDMAEnable = 1;
3994 +               ptri2s_config->bALSAEnable = 0;
3995 +               ptri2s_config->bALSAMMAPEnable = 0;
3996 +
3997 +               i2s_rx_config(ptri2s_config);
3998 +
3999 +               if(ptri2s_config->bTxDMAEnable==0)
4000 +                       i2s_clock_enable(ptri2s_config);
4001 +
4002 +#if defined(CONFIG_I2S_TXRX)
4003 +#if defined(CONFIG_I2S_WM8960)||defined(CONFIG_I2S_WM8750)||defined(CONFIG_I2S_WM8751)
4004 +               audiohw_set_linein_vol(ptri2s_config->rxvol,  ptri2s_config->rxvol);
4005 +#endif
4006 +#endif
4007 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
4008 +
4009 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
4010 +               /* Kick off dma channel */
4011 +               GdmaUnMaskChannel(GDMA_I2S_RX0);
4012 +
4013 +               i2s_rx_enable(ptri2s_config);
4014 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
4015 +               break;
4016 +       case I2S_RX_DISABLE:
4017 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
4018 +               MSG("I2S_RXDISABLE\n");
4019 +               //tasklet_kill(&i2s_rx_tasklet);
4020 +
4021 +               ptri2s_config->bRxDMAEnable = 0;
4022 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
4023 +
4024 +               i2s_rx_end_sleep_on(ptri2s_config);
4025 +               tasklet_kill(&i2s_rx_tasklet);
4026 +
4027 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
4028 +               i2s_reset_rx_param(ptri2s_config);
4029 +               i2s_rx_disable(ptri2s_config);
4030 +               if((ptri2s_config->bRxDMAEnable==0)&&(ptri2s_config->bTxDMAEnable==0))
4031 +                       i2s_clock_disable(ptri2s_config);
4032 +
4033 +               i2s_rxbuf_free(ptri2s_config);
4034 +               if(ptri2s_config->mmap_index <= MAX_I2S_PAGE)
4035 +                       ptri2s_config->mmap_index = 0;
4036 +               //i2s_rxPagebuf_free(ptri2s_config);
4037 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
4038 +               break;
4039 +       case I2S_PUT_AUDIO:
4040 +               i2s_put_audio(ptri2s_config, arg);
4041 +               break;
4042 +       case I2S_GET_AUDIO:
4043 +               i2s_get_audio(ptri2s_config, arg);
4044 +               break;
4045 +       case I2S_TX_STOP:
4046 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
4047 +               MSG("TxGDMA STOP\n");
4048 +               ptri2s_config->bTxDMAEnable = 0;
4049 +               ptri2s_config->end_cnt = 0;
4050 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
4051 +
4052 +               while(ptri2s_config->tx_stop_cnt<3)
4053 +                        interruptible_sleep_on(&(ptri2s_config->i2s_tx_qh));
4054 +
4055 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
4056 +               i2s_reset_tx_param(ptri2s_config);
4057 +               i2s_tx_disable(ptri2s_config);
4058 +               if((ptri2s_config->bRxDMAEnable==0)&&(ptri2s_config->bTxDMAEnable==0))
4059 +                       i2s_clock_disable(ptri2s_config);
4060 +
4061 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
4062 +
4063 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
4064 +               i2s_txbuf_free(ptri2s_config);
4065 +               if(ptri2s_config->mmap_index <= MAX_I2S_PAGE)
4066 +                       ptri2s_config->mmap_index = 0;
4067 +               //i2s_txPagebuf_free(ptri2s_config);
4068 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
4069 +               break;
4070 +       case I2S_TX_PAUSE:
4071 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
4072 +                ptri2s_config->tx_pause_en = 1;
4073 +               MSG("* tx_pause_en = 1 *\n");
4074 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
4075 +                break;
4076 +       case I2S_TX_RESUME:
4077 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
4078 +                ptri2s_config->tx_pause_en = 0;
4079 +               MSG("# tx_pause_en = 0 #\n");
4080 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
4081 +                break;
4082 +       case I2S_RX_STOP:
4083 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
4084 +               MSG("I2S_RX_STOP\n");
4085 +               ptri2s_config->bRxDMAEnable = 0;
4086 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
4087 +
4088 +               while(ptri2s_config->rx_stop_cnt<2)
4089 +                        interruptible_sleep_on(&(ptri2s_config->i2s_rx_qh));
4090 +
4091 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
4092 +               i2s_reset_rx_param(ptri2s_config);
4093 +               i2s_rx_disable(ptri2s_config);
4094 +               if((ptri2s_config->bRxDMAEnable==0)&&(ptri2s_config->bTxDMAEnable==0))
4095 +                       i2s_clock_disable(ptri2s_config);
4096 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
4097 +
4098 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
4099 +               i2s_rxbuf_free(ptri2s_config);
4100 +               if(ptri2s_config->mmap_index <= MAX_I2S_PAGE)
4101 +                       ptri2s_config->mmap_index = 0;
4102 +               //i2s_rxPagebuf_free(ptri2s_config);
4103 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
4104 +               break;
4105 +       case I2S_RX_PAUSE:
4106 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
4107 +                ptri2s_config->rx_pause_en = 1;
4108 +               MSG("* rx_pause_en = 1 *\n");
4109 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
4110 +                break;
4111 +       case I2S_RX_RESUME:
4112 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
4113 +                ptri2s_config->rx_pause_en = 0;
4114 +               MSG("# rx_pause_en = 0 #\n");
4115 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
4116 +                break;
4117 +       case I2S_CODEC_MIC_BOOST:
4118 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
4119 +               if((int)arg > 3)
4120 +                       ptri2s_config->micboost = 3;
4121 +               else if((int)arg < 0)
4122 +                       ptri2s_config->micboost = 0;
4123 +               else
4124 +                       ptri2s_config->micboost = arg;
4125 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
4126 +               break;
4127 +       case I2S_CODEC_MIC_IN:
4128 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
4129 +               if((int)arg == 1)
4130 +                       ptri2s_config->micin = 1;
4131 +               else
4132 +                       ptri2s_config->micin = 0;
4133 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
4134 +               break;
4135 +        case I2S_CLOCK_ENABLE:
4136 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
4137 +                i2s_clock_disable(ptri2s_config);
4138 +#if defined(CONFIG_RALINK_MT7628) || defined(CONFIG_ARCH_MT7623)
4139 +                ptri2s_config->wordlen_24b = 1;
4140 +#endif
4141 +                i2s_tx_config(ptri2s_config);
4142 +                i2s_clock_enable(ptri2s_config);
4143 +                i2s_tx_enable(ptri2s_config);
4144 +                spin_unlock_irqrestore(&ptri2s_config->lock, flags);
4145 +                break;
4146 +       case I2S_DEBUG_CODEC:
4147 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
4148 +               for (i=0; i<10; i++)
4149 +               {
4150 +                       _printk("### i=%d ###\n", i);
4151 +                       i2s_clock_enable(ptri2s_config);
4152 +                       i2s_clock_disable(ptri2s_config);
4153 +               }
4154 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
4155 +               break;
4156 +#if defined(CONFIG_I2S_MS_CTRL)
4157 +       case I2S_MS_MODE_CTRL:
4158 +               spin_lock_irqsave(&ptri2s_config->lock, flags);
4159 +               if((int)arg == 1)
4160 +               {
4161 +                       ptri2s_config->slave_en = 1;
4162 +                       _printk("I2S in slave mode.\n");
4163 +               }
4164 +               else
4165 +               {
4166 +                       ptri2s_config->slave_en = 0;
4167 +                       _printk("I2S in master mode.\n");
4168 +               }
4169 +               spin_unlock_irqrestore(&ptri2s_config->lock, flags);
4170 +               break;
4171 +#endif
4172 +       case I2S_DEBUG_CLKGEN:
4173 +       case I2S_DEBUG_INLBK:
4174 +       case I2S_DEBUG_EXLBK:
4175 +       case I2S_DEBUG_CODECBYPASS:
4176 +       case I2S_DEBUG_FMT:
4177 +#if defined(CONFIG_I2S_WM8960)
4178 +       case I2S_DEBUG_CODEC_EXLBK:
4179 +#endif
4180 +       case I2S_DEBUG_RESET:
4181 +               i2s_debug_cmd(cmd, arg);
4182 +               break;
4183 +       default :
4184 +               MSG("i2s_ioctl: command format error\n");
4185 +       }
4186 +
4187 +       return 0;
4188 +}
4189 +
4190 +/************************
4191 + *      API for ALSA    *
4192 + *                      *
4193 + ************************/
4194 +char* i2s_memPool_Alloc(i2s_config_type* ptri2s_config,int dir)
4195 +{
4196 +        //_printk("%s\n",__func__);
4197 +        if(!ptri2s_config)
4198 +                return NULL;
4199 +        if(dir == STREAM_PLAYBACK){
4200 +#if defined(CONFIG_I2S_MMAP)
4201 +                i2s_mmap_alloc(I2S_TOTAL_PAGE_SIZE);
4202 +#endif
4203 +                i2s_txbuf_alloc(ptri2s_config);
4204 +               return ptri2s_config->pMMAPTxBufPtr[0];
4205 +        }else{
4206 +#if defined(CONFIG_I2S_MMAP)
4207 +                i2s_mmap_alloc(I2S_TOTAL_PAGE_SIZE);
4208 +#endif
4209 +               i2s_rxbuf_alloc(ptri2s_config);
4210 +               return ptri2s_config->pMMAPRxBufPtr[0];
4211 +       }
4212 +        return NULL;
4213 +}
4214 +
4215 +void i2s_memPool_free(i2s_config_type* ptri2s_config,int dir)
4216 +{
4217 +        if(!ptri2s_config)
4218 +                return;
4219 +        if(dir == STREAM_PLAYBACK){
4220 +#if defined(CONFIG_I2S_MMAP)
4221 +               i2s_mem_unmap(ptri2s_config);
4222 +#endif
4223 +               i2s_txbuf_free(ptri2s_config);
4224 +        }else{
4225 +#if defined(CONFIG_I2S_MMAP)
4226 +               i2s_mem_unmap(ptri2s_config);
4227 +#endif
4228 +               i2s_rxbuf_free(ptri2s_config);
4229 +        }
4230 +
4231 +        return;
4232 +}
4233 +
4234 +int i2s_page_prepare(i2s_config_type* ptri2s_config,int dir)
4235 +{
4236 +        if(dir == STREAM_PLAYBACK){
4237 +                /* allocate tx buffer */
4238 +                i2s_txPagebuf_alloc(ptri2s_config);
4239 +               i2s_dma_tx_init(ptri2s_config);
4240 +       }else{
4241 +                /* allocate rx buffer */
4242 +               i2s_rxPagebuf_alloc(ptri2s_config);
4243 +               i2s_dma_rx_init(ptri2s_config);
4244 +        }
4245 +        return 0;
4246 +}
4247 +
4248 +int i2s_page_release(i2s_config_type* ptri2s_config,int dir)
4249 +{
4250 +        if(!ptri2s_config)
4251 +                return (-1);
4252 +        if(dir == STREAM_PLAYBACK)
4253 +               i2s_txPagebuf_free(ptri2s_config);
4254 +        else
4255 +               i2s_rxPagebuf_free(ptri2s_config);
4256 +
4257 +       return 0;
4258 +}
4259 +
4260 +int i2s_startup(void)
4261 +{
4262 +       memset(pi2s_config, 0, sizeof(i2s_config_type));
4263 +
4264 +#ifdef I2S_STATISTIC
4265 +       memset(pi2s_status, 0, sizeof(i2s_status_type));
4266 +#endif
4267 +
4268 +       i2s_param_init(pi2s_config);
4269 +       pi2s_config->bALSAEnable = 1;
4270 +#if defined(CONFIG_I2S_MMAP)
4271 +       pi2s_config->bALSAMMAPEnable = 1;
4272 +#endif
4273 +
4274 +#if defined (CONFIG_RALINK_MT7628) || defined(CONFIG_ARCH_MT7623)
4275 +       pi2s_config->little_edn = 1;
4276 +#endif
4277 +
4278 +       init_waitqueue_head(&(pi2s_config->i2s_tx_qh));
4279 +       init_waitqueue_head(&(pi2s_config->i2s_rx_qh));
4280 +       spin_lock_init(&pi2s_config->lock);
4281 +
4282 +       return 0;
4283 +}
4284 +
4285 +int gdma_En_Switch(i2s_config_type* ptri2s_config,int dir,int enabled){
4286 +        if(!ptri2s_config)
4287 +                return (-1);
4288 +        if(dir == STREAM_PLAYBACK){
4289 +                ptri2s_config->bTxDMAEnable = enabled;
4290 +                //MSG("%s:%d\n",__func__,ptri2s_config->bTxDMAEnable);
4291 +        }else{
4292 +                ptri2s_config->bRxDMAEnable = enabled;
4293 +        }
4294 +        return 0;
4295 +}
4296 +
4297 +int i2s_audio_exchange(i2s_config_type* ptri2s_config,int dir,unsigned long arg)
4298 +{
4299 +        //MSG("I2S_PUT_AUDIO\n");
4300 +        if(!ptri2s_config)
4301 +                return (-1);
4302 +        if(dir == STREAM_PLAYBACK){
4303 +               i2s_put_audio(ptri2s_config, arg);
4304 +       }else{
4305 +               i2s_get_audio(ptri2s_config, arg);
4306 +        }
4307 +        return 0;
4308 +}
4309 +
4310 +void gdma_mask_handler(u32 dma_ch)
4311 +{
4312 +       i2s_dma_mask_handler(dma_ch);
4313 +        return;
4314 +}
4315 +
4316 +void gdma_unmask_handler(u32 dma_ch)
4317 +{
4318 +        i2s_dma_unmask_handler(dma_ch);
4319 +       return;
4320 +}
4321 +
4322 +u32 i2s_mmap_phys_addr(i2s_config_type* ptri2s_config)
4323 +{
4324 +       if((ptri2s_config->pMMAPBufPtr[0]!=NULL) && (ptri2s_config->mmap_index == MAX_I2S_PAGE))
4325 +               return (dma_addr_t)i2s_mmap_addr[0];
4326 +       else if((ptri2s_config->pMMAPBufPtr[MAX_I2S_PAGE]!=NULL) && (ptri2s_config->mmap_index == MAX_I2S_PAGE*2))
4327 +               return (dma_addr_t)i2s_mmap_addr[MAX_I2S_PAGE];
4328 +       else
4329 +               return -1;
4330 +}
4331 +
4332 +EXPORT_SYMBOL(i2s_startup);
4333 +EXPORT_SYMBOL(i2s_mem_unmap);
4334 +EXPORT_SYMBOL(i2s_mmap_alloc);
4335 +EXPORT_SYMBOL(i2s_mmap_remap);
4336 +EXPORT_SYMBOL(i2s_param_init);
4337 +EXPORT_SYMBOL(i2s_txbuf_alloc);
4338 +EXPORT_SYMBOL(i2s_rxbuf_alloc);
4339 +EXPORT_SYMBOL(i2s_txPagebuf_alloc);
4340 +EXPORT_SYMBOL(i2s_rxPagebuf_alloc);
4341 +EXPORT_SYMBOL(i2s_txbuf_free);
4342 +EXPORT_SYMBOL(i2s_rxbuf_free);
4343 +EXPORT_SYMBOL(i2s_txPagebuf_free);
4344 +EXPORT_SYMBOL(i2s_rxPagebuf_free);
4345 +EXPORT_SYMBOL(i2s_rx_disable);
4346 +EXPORT_SYMBOL(i2s_tx_disable);
4347 +EXPORT_SYMBOL(i2s_rx_enable);
4348 +EXPORT_SYMBOL(i2s_tx_enable);
4349 +EXPORT_SYMBOL(i2s_rx_config);
4350 +EXPORT_SYMBOL(i2s_tx_config);
4351 +EXPORT_SYMBOL(i2s_reset_config);
4352 +EXPORT_SYMBOL(i2s_clock_disable);
4353 +EXPORT_SYMBOL(i2s_clock_enable);
4354 +EXPORT_SYMBOL(i2s_reset_rx_param);
4355 +EXPORT_SYMBOL(i2s_reset_tx_param);
4356 +EXPORT_SYMBOL(i2s_dma_rx_handler);
4357 +EXPORT_SYMBOL(i2s_dma_tx_handler);
4358 +EXPORT_SYMBOL(i2s_dma_unmask_handler);
4359 +EXPORT_SYMBOL(i2s_dma_tx_unmask_handler);
4360 +EXPORT_SYMBOL(i2s_dma_rx_unmask_handler);
4361 +EXPORT_SYMBOL(i2s_dma_mask_handler);
4362 +EXPORT_SYMBOL(i2s_dma_tx_init);
4363 +EXPORT_SYMBOL(i2s_dma_rx_init);
4364 +EXPORT_SYMBOL(i2s_tx_end_sleep_on);
4365 +EXPORT_SYMBOL(i2s_rx_end_sleep_on);
4366 +EXPORT_SYMBOL(i2s_mmap_phys_addr);
4367 +EXPORT_SYMBOL(i2s_open);
4368 +EXPORT_SYMBOL(pi2s_config);
4369 +#if defined(CONFIG_I2S_IN_MCLK)
4370 +#if defined(CONFIG_I2S_MCLK_12MHZ)
4371 +EXPORT_SYMBOL(i2s_refclk_12m_enable);
4372 +#endif
4373 +#if defined(CONFIG_I2S_MCLK_12P288MHZ)
4374 +EXPORT_SYMBOL(i2s_refclk_12p288m_enable);
4375 +#endif
4376 +#endif
4377 +#if defined(MT7628_ASIC_BOARD) || defined(CONFIG_ARCH_MT7623)
4378 +EXPORT_SYMBOL(i2s_driving_strength_adjust);
4379 +#endif
4380 +EXPORT_SYMBOL(i2s_refclk_disable);
4381 +EXPORT_SYMBOL(i2s_refclk_gpio_out_config);
4382 +EXPORT_SYMBOL(i2s_refclk_gpio_in_config);
4383 +EXPORT_SYMBOL(i2s_share_pin_config);
4384 +EXPORT_SYMBOL(i2s_share_pin_mt7623);
4385 +EXPORT_SYMBOL(i2s_ws_config);
4386 +EXPORT_SYMBOL(i2s_mode_config);
4387 +EXPORT_SYMBOL(i2s_codec_frequency_config);
4388 +EXPORT_SYMBOL(i2s_dma_tx_transf_data);
4389 +EXPORT_SYMBOL(i2s_dma_tx_transf_zero);
4390 +EXPORT_SYMBOL(i2s_dma_rx_transf_data);
4391 +EXPORT_SYMBOL(i2s_dma_rx_transf_zero);
4392 +EXPORT_SYMBOL(i2s_dma_tx_end_handle);
4393 +EXPORT_SYMBOL(i2s_dma_tx_soft_stop);
4394 +EXPORT_SYMBOL(i2s_dma_rx_soft_stop);
4395 +EXPORT_SYMBOL(i2s_tx_task);
4396 +EXPORT_SYMBOL(i2s_rx_task);
4397 +
4398 +EXPORT_SYMBOL(i2s_memPool_Alloc);
4399 +EXPORT_SYMBOL(i2s_memPool_free);
4400 +EXPORT_SYMBOL(i2s_page_prepare);
4401 +EXPORT_SYMBOL(i2s_page_release);
4402 +EXPORT_SYMBOL(gdma_En_Switch);
4403 +EXPORT_SYMBOL(i2s_audio_exchange);
4404 +EXPORT_SYMBOL(gdma_mask_handler);
4405 +EXPORT_SYMBOL(gdma_unmask_handler);
4406 +#if defined(CONFIG_I2S_WITH_AEC)
4407 +EXPORT_SYMBOL(aecFuncP);
4408 +#endif
4409 +module_init(i2s_mod_init);
4410 +module_exit(i2s_mod_exit);
4411 +
4412 +MODULE_DESCRIPTION("Ralink SoC I2S Controller Module");
4413 +MODULE_AUTHOR("Qwert Chin <qwert.chin@ralinktech.com.tw>");
4414 +MODULE_SUPPORTED_DEVICE("I2S");
4415 +MODULE_VERSION(I2S_MOD_VERSION);
4416 +MODULE_LICENSE("GPL");
4417 +#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,12)
4418 +MODULE_PARM (i2sdrv_major, "i");
4419 +#else
4420 +module_param (i2sdrv_major, int, 0);
4421 +#endif
4422 --- /dev/null
4423 +++ b/sound/soc/mtk/i2s_ctrl.h
4424 @@ -0,0 +1,523 @@
4425 +#ifndef __RALINK_I2S_H_
4426 +#define __RALINK_I2S_H_
4427 +
4428 +#ifdef __KERNEL__
4429 +//#include <asm/rt2880/rt_mmap.h>
4430 +#endif
4431 +
4432 +#if defined(CONFIG_I2S_WITH_AEC)
4433 +#include "aec/aec_api.h"
4434 +#endif
4435 +
4436 +#define I2S_MAX_DEV                    1
4437 +#define I2S_MOD_VERSION                        "0.1"
4438 +#define phys_to_bus(a) (a & 0x1FFFFFFF)
4439 +
4440 +#ifndef u32
4441 +#define u32 unsigned int
4442 +#endif
4443 +
4444 +#ifndef u16
4445 +#define u16 unsigned short
4446 +#endif
4447 +
4448 +#ifndef u8
4449 +#define u8 unsigned char
4450 +#endif
4451 +
4452 +#ifndef REGBIT
4453 +#define REGBIT(x, n)           (x << n)
4454 +#endif
4455 +
4456 +#define Virtual2Physical(x)             (((int)x) & 0x1fffffff)
4457 +#define Physical2Virtual(x)             (((int)x) | 0x80000000)
4458 +#define Virtual2NonCache(x)             (((int)x) | 0x20000000)
4459 +#define Physical2NonCache(x)            (((int)x) | 0xa0000000)
4460 +#define NonCache2Virtual(x)             (((int)x) & 0xDFFFFFFF)
4461 +
4462 +#if defined(CONFIG_I2S_MCLK_12MHZ)
4463 +#define CONFIG_I2S_CODEC_PLL_EN                1
4464 +#else
4465 +#define CONFIG_I2S_CODEC_PLL_EN                0
4466 +#endif
4467 +
4468 +//#define CONFIG_I2S_MS_CTRL
4469 +//#define CONFIG_I2S_MS_MODE
4470 +//#define memory_test
4471 +
4472 +#if defined (CONFIG_ARCH_MT7623)
4473 +#define MT7623_ASIC_BOARD
4474 +#define ARM_ARCH
4475 +#endif
4476 +
4477 +#if defined (CONFIG_RALINK_MT7621)
4478 +#define MT7621_ASIC_BOARD
4479 +#endif
4480 +
4481 +#if defined (CONFIG_RALINK_MT7628)
4482 +#define MT7628_ASIC_BOARD
4483 +#endif
4484 +
4485 +//#define I2S_DEBUG_PRN
4486 +#ifdef I2S_DEBUG_PRN
4487 +#define MSG(fmt, args...) printk("I2S: " fmt, ## args)
4488 +#else
4489 +#define MSG(fmt, args...) { }
4490 +#endif
4491 +
4492 +#ifdef I2S_DEBUG_PRN
4493 +#define i2s_outw(address, value)       do{printk("0x%08X = 0x%08X\n",(u32)address,(u32)value);*((volatile uint32_t *)(address)) = cpu_to_le32(value);}while(0)
4494 +#else
4495 +#define i2s_outw(address, value)       *((volatile uint32_t *)(address)) = cpu_to_le32(value)
4496 +#endif
4497 +#define i2s_inw(address)               le32_to_cpu(*(volatile u32 *)(address))
4498 +
4499 +/* HW feature definiations */
4500 +#if defined(CONFIG_RALINK_RT3883)
4501 +#define CONFIG_I2S_TXRX                        1
4502 +#define CONFIG_I2S_IN_MCLK             1
4503 +//#define CONFIG_I2S_WS_EDGE           1
4504 +#define CONFIG_I2S_FRAC_DIV            1
4505 +#define CONFIG_I2S_IN_CLK              1
4506 +#define CONFIG_I2S_MS_MODE             1
4507 +#endif
4508 +
4509 +#if defined(CONFIG_RALINK_RT3352)||defined(CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) \
4510 +       || defined(CONFIG_RALINK_RT6855A) || defined(CONFIG_RALINK_MT7620) || defined(CONFIG_RALINK_MT7621) \
4511 +       || defined (CONFIG_RALINK_MT7628) || defined(CONFIG_ARCH_MT7623)
4512 +#define CONFIG_I2S_TXRX                        1
4513 +//#define CONFIG_I2S_WS_EDGE           1
4514 +#define CONFIG_I2S_FRAC_DIV            1
4515 +#define CONFIG_I2S_IN_CLK              1
4516 +#endif
4517 +
4518 +#if defined(CONFIG_RALINK_RT3350)
4519 +#define CONFIG_I2S_IN_MCLK             1
4520 +#endif
4521 +
4522 +#if defined(CONFIG_RALINK_RT3052)
4523 +#define CONFIG_I2S_MS_MODE             1
4524 +#endif
4525 +
4526 +/* This is decided in menuconfig */
4527 +#define CONFIG_I2S_MMAP                1
4528 +
4529 +/* For MT7623 ASIC PLL Setting */
4530 +#if defined(CONFIG_ARCH_MT7623)
4531 +#define AUD1PLL_CON0           (0xF0209270)
4532 +#define AUD1PLL_CON1           (0xF0209274)
4533 +#define AUD1PLL_CON2           (0xF0209278)
4534 +#define AUD1PLL_PWR_CON0       (0xF020927C)
4535 +#define AUD2PLL_CON0           (0xF02092C0)
4536 +#define AUD2PLL_CON1           (0xF02092C4)
4537 +#define AUD2PLL_CON2           (0xF02092C8)
4538 +#define AUD2PLL_PWR_CON0       (0xF02092CC)
4539 +#endif
4540 +
4541 +/* Register Map, Ref to RT3052 Data Sheet */
4542 +
4543 +/* Register Map Detail */
4544 +#if defined(CONFIG_ARCH_MT7623)
4545 +#define I2S_I2SCFG                     (ETHDMASYS_I2S_BASE+0x0000)
4546 +#define I2S_INT_STATUS                 (ETHDMASYS_I2S_BASE+0x0004)
4547 +#define I2S_INT_EN                     (ETHDMASYS_I2S_BASE+0x0008)
4548 +#define I2S_FF_STATUS                  (ETHDMASYS_I2S_BASE+0x000c)
4549 +#define I2S_FIFO_WREG                  (ETHDMASYS_I2S_BASE+0x0010)
4550 +#define I2S_TX_FIFO_WREG               I2S_FIFO_WREG
4551 +#define I2S_RX_FIFO_RREG               (ETHDMASYS_I2S_BASE+0x0014)
4552 +#define I2S_I2SCFG1                    (ETHDMASYS_I2S_BASE+0x0018)
4553 +#define I2S_DIVINT_CFG                 (ETHDMASYS_I2S_BASE+0x0024)
4554 +#define I2S_DIVCOMP_CFG                        (ETHDMASYS_I2S_BASE+0x0020)
4555 +#else
4556 +#define I2S_I2SCFG                     (RALINK_I2S_BASE+0x0000)
4557 +#define I2S_INT_STATUS                 (RALINK_I2S_BASE+0x0004)
4558 +#define I2S_INT_EN                     (RALINK_I2S_BASE+0x0008)
4559 +#define I2S_FF_STATUS                  (RALINK_I2S_BASE+0x000c)
4560 +#define I2S_FIFO_WREG                  (RALINK_I2S_BASE+0x0010)
4561 +#define I2S_TX_FIFO_WREG               I2S_FIFO_WREG
4562 +#define I2S_RX_FIFO_RREG               (RALINK_I2S_BASE+0x0014)
4563 +#define I2S_I2SCFG1                    (RALINK_I2S_BASE+0x0018)
4564 +#define I2S_DIVINT_CFG                 (RALINK_I2S_BASE+0x0024)
4565 +#define I2S_DIVCOMP_CFG                        (RALINK_I2S_BASE+0x0020)
4566 +#endif
4567 +
4568 +
4569 +/* I2SCFG bit field */
4570 +#define I2S_EN                 31
4571 +#define I2S_DMA_EN             30
4572 +#if defined(CONFIG_RALINK_MT7628) || defined(CONFIG_ARCH_MT7623)
4573 +#define I2S_LITTLE_ENDIAN      29
4574 +#define I2S_SYS_ENDIAN         28
4575 +#elif defined(CONFIG_RALINK_RT6855A)
4576 +#define I2S_BYTE_SWAP          28
4577 +#endif
4578 +#define I2S_TX_EN              24
4579 +#define I2S_RX_EN              20
4580 +#if defined(CONFIG_RALINK_MT7628) || defined(CONFIG_ARCH_MT7623)
4581 +#define I2S_NORM_24BIT         18
4582 +#define I2S_DATA_24BIT         17
4583 +#endif
4584 +#define I2S_SLAVE_MODE         16
4585 +#define I2S_RX_FF_THRES                12
4586 +#define I2S_RX_CH_SWAP         11
4587 +#define I2S_RX_CH1_OFF         10
4588 +#define I2S_RX_CH0_OFF         9
4589 +#if defined(CONFIG_RALINK_RT3052)
4590 +#define I2S_CLK_OUT_DIS                8
4591 +#endif
4592 +#define I2S_TX_FF_THRES                4
4593 +#define I2S_TX_CH_SWAP         3
4594 +#define I2S_TX_CH1_OFF         2
4595 +#define I2S_TX_CH0_OFF         1
4596 +#if defined(CONFIG_RALINK_RT3052)
4597 +#define I2S_SLAVE_EN            0
4598 +#else
4599 +#define I2S_WS_INV             0
4600 +#endif
4601 +/* INT_EN bit field */
4602 +#define I2S_RX_INT3_EN         7
4603 +#define I2S_RX_INT2_EN         6
4604 +#define I2S_RX_INT1_EN         5
4605 +#define I2S_RX_INT0_EN         4
4606 +#define I2S_TX_INT3_EN         3
4607 +#define I2S_TX_INT2_EN         2
4608 +#define I2S_TX_INT1_EN         1
4609 +#define I2S_TX_INT0_EN         0
4610 +
4611 +/* INT_STATUS bit field */
4612 +#define I2S_RX_DMA_FAULT       7
4613 +#define I2S_RX_OVRUN           6
4614 +#define I2S_RX_UNRUN           5
4615 +#define I2S_RX_THRES           4
4616 +#define I2S_TX_DMA_FAULT       3
4617 +#define I2S_TX_OVRUN           2
4618 +#define I2S_TX_UNRUN           1
4619 +#define I2S_TX_THRES           0
4620 +
4621 +/* FF_STATUS bit field */
4622 +#define I2S_RX_EPCNT           4
4623 +#define I2S_TX_EPCNT           0
4624 +/* I2S_DIVCOMP_CFG bit field */
4625 +#define I2S_CLKDIV_EN          31
4626 +
4627 +/* I2S_CFG1 bit field */
4628 +#define I2S_LBK_EN             31
4629 +#define I2S_EXT_LBK_EN         30
4630 +#if defined(CONFIG_RALINK_MT7628) || defined(CONFIG_ARCH_MT7623)
4631 +#define I2S_DATA_FMT           0
4632 +#endif
4633 +
4634 +/* FIFO_WREG bit field */
4635 +#define I2S_FIFO_WDATA         0
4636 +
4637 +/* Constant definition */
4638 +#define NFF_THRES              4
4639 +#define I2S_PAGE_SIZE          3072//(3*4096)//(1152*2*2*2)
4640 +#define I2S_MIN_PAGE_SIZE      4096
4641 +#define MAX_I2S_PAGE           8
4642 +#define I2S_TOTAL_PAGE_SIZE    (I2S_PAGE_SIZE*MAX_I2S_PAGE)
4643 +
4644 +#if defined(CONFIG_I2S_WM8960)
4645 +#define MAX_SRATE_HZ            48000
4646 +#define MIN_SRATE_HZ            8000
4647 +#elif defined(CONFIG_I2S_WM8750)
4648 +#define MAX_SRATE_HZ           96000
4649 +#define MIN_SRATE_HZ           8000
4650 +#endif
4651 +
4652 +#define MAX_VOL_DB             +0
4653 +#define MIN_VOL_DB             -127
4654 +
4655 +#define ALSA_MMAP_IDX_SHIFT    2
4656 +#if defined(CONFIG_SND_MT76XX_SOC)
4657 +#define STREAM_PLAYBACK                SNDRV_PCM_STREAM_PLAYBACK
4658 +#define STREAM_CAPTURE         SNDRV_PCM_STREAM_CAPTURE
4659 +#else
4660 +#define STREAM_PLAYBACK                0
4661 +#define STREAM_CAPTURE         1
4662 +#endif
4663 +
4664 +/* I2S I/O command */
4665 +#define I2S_SRATE              0
4666 +#define I2S_VOL                        1
4667 +#define I2S_ENABLE             2
4668 +#define I2S_DISABLE            3
4669 +#define I2S_TX_ENABLE          27
4670 +#define I2S_TX_DISABLE         3
4671 +#define I2S_GET_WBUF           4
4672 +#define I2S_PUT_WBUF           5
4673 +#define I2S_RX_ENABLE          6
4674 +#define I2S_RX_DISABLE         7
4675 +#define I2S_PUT_AUDIO          4
4676 +#define I2S_GET_AUDIO          5
4677 +#define I2S_TX_VOL             1
4678 +#define I2S_RX_VOL             8
4679 +#define I2S_WORD_LEN           9
4680 +#define I2S_ENDIAN_FMT         10
4681 +#define I2S_INTERNAL_LBK       11
4682 +#define I2S_TX_STOP             12
4683 +#define I2S_DEBUG_CODEC                13
4684 +#define I2S_MS_MODE_CTRL       14
4685 +#define I2S_TX_PAUSE           15
4686 +#define I2S_TX_RESUME          16
4687 +#define I2S_RESET              17
4688 +#define I2S_RX_STOP            18
4689 +#define I2S_EXTERNAL_LBK       19
4690 +#define I2S_TXRX_COEXIST       20
4691 +#define I2S_RX_PAUSE           21
4692 +#define I2S_RX_RESUME          22
4693 +#define I2S_CODEC_MIC_BOOST    23
4694 +#define I2S_CODEC_MIC_IN       24
4695 +#define I2S_CLOCK_ENABLE       25
4696 +#define I2S_TEST_TEST          26
4697 +
4698 +#define I2S_DEBUG              30
4699 +#define I2S_DEBUG_CLKGEN       30
4700 +#define I2S_DEBUG_INLBK                31
4701 +#define I2S_DEBUG_EXLBK                32
4702 +#define I2S_DEBUG_FMT          33
4703 +#define I2S_DEBUG_RESET                34
4704 +#define I2S_DEBUG_CODECBYPASS  35
4705 +#if defined(CONFIG_I2S_WM8960)
4706 +#define I2S_DEBUG_CODEC_EXLBK  36
4707 +#endif
4708 +
4709 +/* configuration */
4710 +#define CONFIG_I2S_TFF_THRES   NFF_THRES
4711 +#define CONFIG_I2S_CH_SWAP     0
4712 +#if defined(CONFIG_I2S_MS_MODE)
4713 +#define CONFIG_I2S_SLAVE_EN    0
4714 +#else
4715 +#define CONFIG_I2S_SLAVE_EN    1
4716 +#endif
4717 +
4718 +/* driver status definition */
4719 +#define I2S_OK                 0
4720 +#define I2S_OUTOFMEM           0x01
4721 +#define I2S_GDMAFAILED         0x02
4722 +#define I2S_REQUEST_IRQ_FAILED 0x04
4723 +#define I2S_REG_SETUP_FAILED   0x08
4724 +
4725 +#define I2S_STATISTIC
4726 +//#define I2S_HW_INTERRUPT_EN
4727 +//#define I2S_SW_IRQ_EN
4728 +#define I2S_MAJOR              234
4729 +
4730 +/* parameter for ALSA */
4731 +/*GDMA for I2S Status*/
4732 +#define GDMA_I2S_DIS (0)
4733 +#define GDMA_I2S_EN (1)
4734 +
4735 +
4736 +typedef struct i2s_status_t
4737 +{
4738 +       u32 txdmafault;
4739 +       u32 txovrun;
4740 +       u32 txunrun;
4741 +       u32 txthres;
4742 +       int txbuffer_unrun;
4743 +       int txbuffer_ovrun;
4744 +       int txbuffer_len;
4745 +
4746 +       u32 rxdmafault;
4747 +       u32 rxovrun;
4748 +       u32 rxunrun;
4749 +       u32 rxthres;
4750 +       int rxbuffer_unrun;
4751 +       int rxbuffer_ovrun;
4752 +       int rxbuffer_len;
4753 +}i2s_status_type;
4754 +
4755 +
4756 +typedef struct i2s_config_t
4757 +{
4758 +
4759 +       int srate;
4760 +       int txvol;
4761 +       int rxvol;
4762 +       u32 pos;
4763 +       u32 tx_isr_cnt;
4764 +       u32 rx_isr_cnt;
4765 +       int bSleep;
4766 +       int bTxDMAEnable;
4767 +       int bRxDMAEnable;
4768 +       int enLable;
4769 +       int micboost;
4770 +       int micin;
4771 +
4772 +       /* parameters fo ALSA */
4773 +       int bALSAEnable;
4774 +       int bALSAMMAPEnable;
4775 +       unsigned char bTrigger[2];
4776 +       unsigned char bPreTrigger[2];
4777 +       unsigned char dmaStat[2];
4778 +       unsigned char i2sStat[2];
4779 +       unsigned int hw_base_frame[2];
4780 +       struct snd_pcm_substream *pss[2];
4781 +
4782 +#ifdef __KERNEL__
4783 +       spinlock_t lock;
4784 +       wait_queue_head_t i2s_tx_qh, i2s_rx_qh;
4785 +#endif
4786 +       u32 dmach;
4787 +       u32 tx_unmask_ch;
4788 +       u32 rx_unmask_ch;
4789 +       u32 dma_unmask_status;
4790 +       u32 dma_done_status;
4791 +       u32 tx_ff_thres;
4792 +       u32 tx_ch_swap;
4793 +       u32 rx_ff_thres;
4794 +       u32 rx_ch_swap;
4795 +       u32 slave_en;
4796 +
4797 +       u32 dis_match;
4798 +       int start_cnt;
4799 +#if defined (CONFIG_RALINK_MT7628) || defined(CONFIG_ARCH_MT7623)
4800 +       int little_edn;  /* test file's fmt: little endian->1; big endian->0 */
4801 +        int sys_endian;  /* kernal' system fmt: little endian->0; big endian->1 */
4802 +#endif
4803 +       int wordlen_24b;
4804 +       int codec_pll_en;
4805 +       int codec_num;
4806 +       int tx_pause_en;
4807 +       int rx_pause_en;
4808 +       int end_cnt;
4809 +       int txrx_coexist;
4810 +       int tx_stop_cnt;
4811 +       int rx_stop_cnt;
4812 +       /* for I2S_CFG1 */
4813 +       u32 lbk;
4814 +       u32 extlbk;
4815 +       u32 fmt;
4816 +
4817 +       int w_idx;
4818 +       int r_idx;
4819 +
4820 +       int tx_w_idx;
4821 +       int tx_r_idx;
4822 +       int rx_w_idx;
4823 +       int rx_r_idx;
4824 +       int mmap_index;
4825 +       int next_p0_idx;
4826 +       int next_p1_idx;
4827 +
4828 +       u8* buf8ptr;
4829 +       char* pMMAPBufPtr[MAX_I2S_PAGE*2];
4830 +       char* pMMAPTxBufPtr[MAX_I2S_PAGE];
4831 +       char* pMMAPRxBufPtr[MAX_I2S_PAGE];
4832 +
4833 +       union {
4834 +               u16* pPage0TxBuf16Ptr;
4835 +               u8* pPage0TxBuf8ptr;
4836 +       };
4837 +       union {
4838 +               u16* pPage1TxBuf16Ptr;
4839 +               u8* pPage1TxBuf8ptr;
4840 +       };
4841 +
4842 +       union {
4843 +               u16* pPage0RxBuf16Ptr;
4844 +               u8* pPage0RxBuf8ptr;
4845 +       };
4846 +       union {
4847 +               u16* pPage1RxBuf16Ptr;
4848 +               u8* pPage1RxBuf8ptr;
4849 +       };
4850 +
4851 +}i2s_config_type;
4852 +
4853 +
4854 +void i2s_gen_test_pattern(void);
4855 +int i2s_mem_unmap(i2s_config_type* ptri2s_config);
4856 +int i2s_param_init(i2s_config_type* ptri2s_config);
4857 +int i2s_txbuf_alloc(i2s_config_type* ptri2s_config);
4858 +int i2s_rxbuf_alloc(i2s_config_type* ptri2s_config);
4859 +int i2s_txPagebuf_alloc(i2s_config_type* ptri2s_config);
4860 +int i2s_rxPagebuf_alloc(i2s_config_type* ptri2s_config);
4861 +int i2s_txbuf_free(i2s_config_type* ptri2s_config);
4862 +int i2s_rxbuf_free(i2s_config_type* ptri2s_config);
4863 +int i2s_txPagebuf_free(i2s_config_type* ptri2s_config);
4864 +int i2s_rxPagebuf_free(i2s_config_type* ptri2s_config);
4865 +int i2s_reset_tx_param(i2s_config_type* ptri2s_config);
4866 +int i2s_reset_rx_param(i2s_config_type* ptri2s_config);
4867 +int i2s_tx_config(i2s_config_type* ptri2s_config);
4868 +int i2s_rx_config(i2s_config_type* ptri2s_config);
4869 +int i2s_tx_enable(i2s_config_type* ptri2s_config);
4870 +int i2s_tx_disable(i2s_config_type* ptri2s_config);
4871 +int i2s_rx_enable(i2s_config_type* ptri2s_config);
4872 +int i2s_rx_disable(i2s_config_type* ptri2s_config);
4873 +int i2s_codec_enable(i2s_config_type* ptri2s_config);
4874 +int i2s_codec_disable(i2s_config_type* ptri2s_config);
4875 +int i2s_clock_enable(i2s_config_type* ptri2s_config);
4876 +int i2s_clock_disable(i2s_config_type* ptri2s_config);
4877 +int i2s_reset_config(i2s_config_type* ptri2s_config);
4878 +int i2s_refclk_disable(void);
4879 +int i2s_refclk_gpio_out_config(void);
4880 +int i2s_refclk_gpio_in_config(void);
4881 +int i2s_share_pin_config(i2s_config_type* ptri2s_config);
4882 +int i2s_share_pin_mt7623(i2s_config_type* ptri2s_config);
4883 +int i2s_master_clock_gpio_out_mt7623(void);
4884 +int i2s_slave_clock_gpio_in_mt7623(void);
4885 +int i2s_ws_config(i2s_config_type* ptri2s_config, unsigned long index);
4886 +int i2s_mode_config(u32 slave_en);
4887 +int i2s_codec_frequency_config(i2s_config_type* ptri2s_config, unsigned long index);
4888 +void i2s_tx_end_sleep_on(i2s_config_type* ptri2s_config);
4889 +void i2s_rx_end_sleep_on(i2s_config_type* ptri2s_config);
4890 +
4891 +#if defined(CONFIG_I2S_MCLK_12MHZ)
4892 +int i2s_refclk_12m_enable(void);
4893 +#endif
4894 +#if defined(CONFIG_I2S_MCLK_12P288MHZ)
4895 +int i2s_refclk_12p288m_enable(void);
4896 +#endif
4897 +
4898 +#if defined(MT7621_ASIC_BOARD)
4899 +int i2s_pll_config_mt7621(unsigned long index);
4900 +int i2s_pll_refclk_set(void);
4901 +#endif
4902 +#if defined(MT7623_ASIC_BOARD)
4903 +int i2s_pll_config_mt7623(unsigned long index);
4904 +#endif
4905 +#if defined(MT7628_ASIC_BOARD) || defined(CONFIG_ARCH_MT7623)
4906 +int i2s_driving_strength_adjust(void);
4907 +#endif
4908 +#if defined(I2S_STATISTIC)
4909 +void i2s_int_status(u32 dma_ch);
4910 +#endif
4911 +void i2s_dma_tx_handler(u32 dma_ch);
4912 +void i2s_dma_rx_handler(u32 dma_ch);
4913 +void i2s_dma_unmask_handler(u32 dma_ch);
4914 +void i2s_dma_mask_handler(u32 dma_ch);
4915 +void i2s_dma_tx_init(i2s_config_type* ptri2s_config);
4916 +void i2s_dma_rx_init(i2s_config_type* ptri2s_config);
4917 +void i2s_tx_task(unsigned long pData);
4918 +void i2s_rx_task(unsigned long pData);
4919 +void i2s_dma_tx_unmask_handler(u32 dma_ch);
4920 +void i2s_dma_rx_unmask_handler(u32 dma_ch);
4921 +int i2s_dma_tx_transf_data(i2s_config_type* ptri2s_config, u32 dma_ch);
4922 +int i2s_dma_tx_transf_zero(i2s_config_type* ptri2s_config, u32 dma_ch);
4923 +int i2s_dma_rx_transf_data(i2s_config_type* ptri2s_config, u32 dma_ch);
4924 +int i2s_dma_rx_transf_zero(i2s_config_type* ptri2s_config, u32 dma_ch);
4925 +void i2s_dma_tx_end_handle(i2s_config_type* ptri2s_config);
4926 +int i2s_dma_tx_soft_stop(i2s_config_type* ptri2s_config, u32 dma_ch);
4927 +int i2s_dma_rx_soft_stop(i2s_config_type* ptri2s_config, u32 dma_ch);
4928 +
4929 +int i2s_page_prepare(i2s_config_type* ptri2s_config,int dir);
4930 +int i2s_page_release(i2s_config_type* ptri2s_config,int dir);
4931 +int gdma_En_Switch(i2s_config_type* ptri2s_config,int dir,int enabled);
4932 +int i2s_startup(void);
4933 +int i2s_audio_exchange(i2s_config_type* ptri2s_config,int dir,unsigned long arg);
4934 +void gdma_unmask_handler(u32 dma_ch);
4935 +char* i2s_memPool_Alloc(i2s_config_type* ptri2s_config,int dir);
4936 +void i2s_memPool_free(i2s_config_type* ptri2s_config,int dir);
4937 +u32 i2s_mmap_phys_addr(i2s_config_type* ptri2s_config);
4938 +
4939 +#if !defined(CONFIG_I2S_TXRX)
4940 +#define GdmaI2sRx      //GdmaI2sRx
4941 +#endif
4942 +
4943 +#define RALINK_I2S_VERSION     "1.0"
4944 +#define I2SDRV_DEVNAME         "i2s0"
4945 +
4946 +#endif /* __RALINK_I2S_H_ */
4947 +
4948 --- /dev/null
4949 +++ b/sound/soc/mtk/mt76xx_i2s.c
4950 @@ -0,0 +1,309 @@
4951 +/*
4952 + * mtk_audio_drv.c
4953 + *
4954 + *  Created on: 2013/8/20
4955 + *      Author: MTK04880
4956 + */
4957 +#include <linux/init.h>
4958 +#include <linux/version.h>
4959 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
4960 +#include <linux/sched.h>
4961 +#endif
4962 +#include <linux/module.h>
4963 +#include <linux/kernel.h> /* printk() */
4964 +#include <linux/slab.h> /* kmalloc() */
4965 +#include <linux/fs.h> /* everything... */
4966 +#include <linux/errno.h> /* error codes */
4967 +#include <linux/types.h> /* size_t */
4968 +#include <linux/proc_fs.h>
4969 +#include <linux/fcntl.h> /* O_ACCMODE */
4970 +#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,36)
4971 +#include <asm/system.h> /* cli(), *_flags */
4972 +#endif
4973 +#include <asm/uaccess.h> /* copy_from/to_user */
4974 +#include <linux/interrupt.h>
4975 +#include <linux/mm.h>
4976 +#include <linux/dma-mapping.h>
4977 +#include <sound/core.h>
4978 +#include <linux/pci.h>
4979 +#include <sound/pcm.h>
4980 +#include <sound/pcm_params.h>
4981 +#include <sound/soc.h>
4982 +#include <sound/soc-dapm.h>
4983 +#include <sound/initval.h>
4984 +#include "ralink_gdma.h"
4985 +#include "mt76xx_i2s.h"
4986 +
4987 +/****************************/
4988 +/*GLOBAL VARIABLE DEFINITION*/
4989 +/****************************/
4990 +extern i2s_config_type* pi2s_config;
4991 +
4992 +/****************************/
4993 +/*FUNCTION DECLRATION          */
4994 +/****************************/
4995 +static int mt76xx_i2s_set_fmt(struct snd_soc_dai *cpu_dai,\
4996 +               unsigned int fmt);
4997 +
4998 +//static int  mt76xx_i2s_shutdown(struct snd_pcm_substream *substream,
4999 +//                    struct snd_soc_dai *dai);
5000 +static int  mt76xx_i2s_startup(struct snd_pcm_substream *substream,
5001 +                      struct snd_soc_dai *dai);
5002 +static int mt76xx_i2s_hw_params(struct snd_pcm_substream *substream,\
5003 +                               struct snd_pcm_hw_params *params,\
5004 +                               struct snd_soc_dai *dai);
5005 +static int mt76xx_i2s_play_prepare(struct snd_pcm_substream *substream,struct snd_soc_dai *dai);
5006 +static int mt76xx_i2s_rec_prepare(struct snd_pcm_substream *substream,struct snd_soc_dai *dai);
5007 +static int mt76xx_i2s_hw_free(struct snd_pcm_substream *substream,struct snd_soc_dai *dai);
5008 +static int mt76xx_i2s_prepare(struct snd_pcm_substream *substream, struct snd_soc_dai *dai);
5009 +
5010 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,20)
5011 +static int mt76xx_i2s_drv_probe(struct platform_device *pdev);
5012 +static int mt76xx_i2s_drv_remove(struct platform_device *pdev);
5013 +#endif
5014 +/****************************/
5015 +/*STRUCTURE DEFINITION         */
5016 +/****************************/
5017 +
5018 +
5019 +static struct snd_soc_dai_ops mt76xx_i2s_dai_ops = {
5020 +       .startup   = mt76xx_i2s_startup,
5021 +       .hw_params = mt76xx_i2s_hw_params,
5022 +       .hw_free   = mt76xx_i2s_hw_free,
5023 +       //.shutdown = mt76xx_i2s_shutdown,
5024 +       .prepare   = mt76xx_i2s_prepare,
5025 +       .set_fmt   = mt76xx_i2s_set_fmt,
5026 +       //.set_sysclk = mt76xx_i2s_set_sysclk,
5027 +};
5028 +
5029 +const struct snd_soc_component_driver mt76xx_i2s_component = {
5030 +       .name           = "mt76xx-i2s",
5031 +};
5032 +
5033 +struct snd_soc_dai_driver mt76xx_i2s_dai = {
5034 +       .playback = {
5035 +               .channels_min = 1,
5036 +               .channels_max = 2,
5037 +               .rates = (SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_11025|\
5038 +               SNDRV_PCM_RATE_16000|SNDRV_PCM_RATE_22050|SNDRV_PCM_RATE_32000|\
5039 +               SNDRV_PCM_RATE_44100|SNDRV_PCM_RATE_48000),
5040 +
5041 +               .formats = (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
5042 +                               SNDRV_PCM_FMTBIT_S24_LE),
5043 +       },
5044 +       .capture = {
5045 +               .channels_min = 1,
5046 +               .channels_max = 2,
5047 +               .rates = (SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_11025|\
5048 +                               SNDRV_PCM_RATE_16000|SNDRV_PCM_RATE_22050|SNDRV_PCM_RATE_32000|\
5049 +                               SNDRV_PCM_RATE_44100|SNDRV_PCM_RATE_48000),
5050 +               .formats = (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
5051 +                               SNDRV_PCM_FMTBIT_S24_LE),
5052 +       },
5053 +       .ops = &mt76xx_i2s_dai_ops,
5054 +       .symmetric_rates = 1,
5055 +};
5056 +
5057 +/****************************/
5058 +/*FUNCTION BODY                                */
5059 +/****************************/
5060 +
5061 +static int mt76xx_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
5062 +               unsigned int fmt)
5063 +{//TODO
5064 +
5065 +       //printk("******* %s *******\n", __func__);
5066 +       return 0;
5067 +}
5068 +
5069 +static int mt76xx_i2s_play_prepare(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
5070 +{
5071 +       //printk("******* %s *******\n", __func__);
5072 +       i2s_config_type* rtd = (i2s_config_type*)substream->runtime->private_data;
5073 +       rtd->pss[SNDRV_PCM_STREAM_PLAYBACK] = substream;
5074 +       if(! rtd->i2sStat[SNDRV_PCM_STREAM_PLAYBACK]){
5075 +               i2s_reset_tx_param( rtd);
5076 +               i2s_tx_config( rtd);
5077 +               gdma_En_Switch(rtd, STREAM_PLAYBACK, GDMA_I2S_EN);
5078 +
5079 +               if( rtd->bRxDMAEnable==0)
5080 +                       i2s_clock_enable( rtd);
5081 +
5082 +               i2s_tx_enable( rtd);
5083 +               rtd->i2sStat[SNDRV_PCM_STREAM_PLAYBACK] = 1;
5084 +               MSG("I2S_TXENABLE done\n");
5085 +       }
5086 +
5087 +       return 0;
5088 +}
5089 +
5090 +static int mt76xx_i2s_rec_prepare(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
5091 +{
5092 +
5093 +       //printk("******* %s *******\n", __func__);
5094 +       i2s_config_type* rtd = (i2s_config_type*)substream->runtime->private_data;
5095 +       rtd->pss[SNDRV_PCM_STREAM_CAPTURE] = substream;
5096 +       if(! rtd->i2sStat[SNDRV_PCM_STREAM_CAPTURE]) {
5097 +               i2s_reset_rx_param(rtd);
5098 +               i2s_rx_config(rtd);
5099 +               gdma_En_Switch(rtd, STREAM_CAPTURE, GDMA_I2S_EN);
5100 +
5101 +               if(rtd->bTxDMAEnable==0)
5102 +                       i2s_clock_enable(rtd);
5103 +
5104 +               i2s_rx_enable(rtd);
5105 +               rtd->i2sStat[SNDRV_PCM_STREAM_CAPTURE] = 1;
5106 +       }
5107 +       return 0;
5108 +}
5109 +
5110 +/*static int  mt76xx_i2s_shutdown(struct snd_pcm_substream *substream,
5111 +                      struct snd_soc_dai *dai)
5112 +{
5113 +       //i2s_config_type* rtd = (i2s_config_type*)substream->runtime->private_data;
5114 +       //printk("******* %s *******\n", __func__);
5115 +       return 0;
5116 +}
5117 +*/
5118 +static int  mt76xx_i2s_startup(struct snd_pcm_substream *substream,
5119 +                      struct snd_soc_dai *dai)
5120 +{
5121 +
5122 +       //printk("******* %s *******\n", __func__);
5123 +       if((!pi2s_config->i2sStat[SNDRV_PCM_STREAM_PLAYBACK]) && (!pi2s_config->i2sStat[SNDRV_PCM_STREAM_CAPTURE])){
5124 +               i2s_startup();
5125 +               if(!pi2s_config)
5126 +                       return -1;
5127 +               i2s_reset_config(pi2s_config);
5128 +       }
5129 +       substream->runtime->private_data = pi2s_config;
5130 +       return 0;
5131 +}
5132 +
5133 +static int mt76xx_i2s_hw_params(struct snd_pcm_substream *substream,\
5134 +                               struct snd_pcm_hw_params *params,\
5135 +                               struct snd_soc_dai *dai){
5136 +       unsigned int srate = 0;
5137 +       //unsigned long data;
5138 +       struct snd_pcm_runtime *runtime = substream->runtime;
5139 +       i2s_config_type* rtd = runtime->private_data;
5140 +
5141 +       printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
5142 +       //printk("******* %s *******\n", __func__);
5143 +       switch(params_rate(params)){
5144 +       case 8000:
5145 +               srate = 8000;
5146 +               break;
5147 +       case 16000:
5148 +               srate = 16000;
5149 +               break;
5150 +       case 32000:
5151 +               srate = 32000;
5152 +               break;
5153 +       case 44100:
5154 +               printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
5155 +               srate = 44100;
5156 +               break;
5157 +       case 48000:
5158 +               srate = 48000;
5159 +               break;
5160 +       default:
5161 +               srate = 44100;
5162 +               //MSG("audio sampling rate %u should be %d ~ %d Hz\n", (u32)params_rate(params), MIN_SRATE_HZ, MAX_SRATE_HZ);
5163 +               break;
5164 +       }
5165 +       if(srate){
5166 +               printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
5167 +               if((rtd->bRxDMAEnable != GDMA_I2S_EN) && (rtd->bTxDMAEnable != GDMA_I2S_EN)){
5168 +                       printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
5169 +                       rtd->srate = srate;
5170 +                       MSG("set audio sampling rate to %d Hz\n", rtd->srate);
5171 +               }
5172 +       }
5173 +
5174 +       return 0;
5175 +}
5176 +static int mt76xx_i2s_hw_free(struct snd_pcm_substream *substream,struct snd_soc_dai *dai){
5177 +
5178 +       //printk("******* %s *******\n", __func__);
5179 +       i2s_config_type* rtd = (i2s_config_type*)substream->runtime->private_data;
5180 +       if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK){
5181 +               if(rtd->i2sStat[SNDRV_PCM_STREAM_PLAYBACK]){
5182 +                       MSG("I2S_TXDISABLE\n");
5183 +                       i2s_reset_tx_param(rtd);
5184 +
5185 +                       if((rtd->bRxDMAEnable==0)&&(rtd->bTxDMAEnable==0)){
5186 +                               i2s_clock_disable(rtd);
5187 +                       }
5188 +                       rtd->i2sStat[SNDRV_PCM_STREAM_PLAYBACK] = 0;
5189 +               }
5190 +       }
5191 +       else{
5192 +               if(rtd->i2sStat[SNDRV_PCM_STREAM_CAPTURE]){
5193 +                       MSG("I2S_RXDISABLE\n");
5194 +                       i2s_reset_rx_param(rtd);
5195 +
5196 +                       if((rtd->bRxDMAEnable==0)&&(rtd->bTxDMAEnable==0)){
5197 +                               i2s_clock_disable(rtd);
5198 +                       }
5199 +                       rtd->i2sStat[SNDRV_PCM_STREAM_CAPTURE] = 0;
5200 +               }
5201 +       }
5202 +       return 0;
5203 +}
5204 +static int mt76xx_i2s_prepare(struct snd_pcm_substream *substream,struct snd_soc_dai *dai)
5205 +{
5206 +
5207 +       //printk("******* %s *******\n", __func__);
5208 +       if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5209 +               return mt76xx_i2s_play_prepare(substream, dai);
5210 +       else
5211 +               return mt76xx_i2s_rec_prepare(substream, dai);
5212 +
5213 +       return 0;
5214 +}
5215 +
5216 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,20)
5217 +static int mt76xx_i2s_drv_probe(struct platform_device *pdev)
5218 +{
5219 +       //printk("****** %s ******\n", __func__);
5220 +       printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
5221 +       return snd_soc_register_component(&pdev->dev, &mt76xx_i2s_component,
5222 +                                       &mt76xx_i2s_dai, 1);
5223 +}
5224 +
5225 +static int mt76xx_i2s_drv_remove(struct platform_device *pdev)
5226 +{
5227 +       snd_soc_unregister_component(&pdev->dev);
5228 +       return 0;
5229 +}
5230 +
5231 +static struct platform_driver mt76xx_i2s_driver = {
5232 +       .probe  = mt76xx_i2s_drv_probe,
5233 +       .remove = mt76xx_i2s_drv_remove,
5234 +       .driver = {
5235 +               .name  = "mt76xx-i2s",
5236 +               .owner = THIS_MODULE,
5237 +       },
5238 +};
5239 +
5240 +static int __init mt76xx_i2s_init(void)
5241 +{
5242 +
5243 +       //printk("****** %s ******\n", __func__);
5244 +       return platform_driver_register(&mt76xx_i2s_driver);
5245 +}
5246 +
5247 +static void __exit mt76xx_i2s_exit(void)
5248 +{
5249 +       //printk("****** %s ******\n", __func__);
5250 +       platform_driver_unregister(&mt76xx_i2s_driver);
5251 +}
5252 +
5253 +module_init(mt76xx_i2s_init);
5254 +module_exit(mt76xx_i2s_exit);
5255 +
5256 +MODULE_AUTHOR("Dora Chen");
5257 +MODULE_DESCRIPTION("Stretch MT76xx I2S Interface");
5258 +MODULE_LICENSE("GPL");
5259 +#endif
5260 --- /dev/null
5261 +++ b/sound/soc/mtk/mt76xx_i2s.h
5262 @@ -0,0 +1,18 @@
5263 +/*
5264 + * mtk_i2s.h
5265 + *
5266 + *  Created on: 2013/8/20
5267 + *      Author: MTK04880
5268 + */
5269 +
5270 +#ifndef MTK_I2S_H_
5271 +#define MTK_I2S_H_
5272 +
5273 +
5274 +#ifdef __KERNEL__
5275 +//#include <asm/rt2880/rt_mmap.h>
5276 +#include <linux/fs.h>
5277 +#endif
5278 +
5279 +#include "i2s_ctrl.h"
5280 +#endif /* MTK_I2S_H_ */
5281 --- /dev/null
5282 +++ b/sound/soc/mtk/mt76xx_machine.c
5283 @@ -0,0 +1,319 @@
5284 +/*
5285 + * mt76xx_machine.c
5286 + *
5287 + */
5288 +#include <linux/init.h>
5289 +#include <linux/version.h>
5290 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
5291 +#include <linux/sched.h>
5292 +#endif
5293 +#include <linux/module.h>
5294 +#include <linux/kernel.h> /* printk() */
5295 +#include <linux/slab.h> /* kmalloc() */
5296 +#include <linux/fs.h> /* everything... */
5297 +#include <linux/errno.h> /* error codes */
5298 +#include <linux/types.h> /* size_t */
5299 +#include <linux/proc_fs.h>
5300 +#include <linux/fcntl.h> /* O_ACCMODE */
5301 +#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,36)
5302 +#include <asm/system.h> /* cli(), *_flags */
5303 +#endif
5304 +#include <asm/uaccess.h> /* copy_from/to_user */
5305 +#include <linux/interrupt.h>
5306 +#include <linux/mm.h>
5307 +#include <linux/dma-mapping.h>
5308 +#include <sound/core.h>
5309 +#include <linux/pci.h>
5310 +#include <sound/pcm.h>
5311 +#include <sound/pcm_params.h>
5312 +#include <sound/soc.h>
5313 +#include <sound/soc-dapm.h>
5314 +#include <sound/initval.h>
5315 +#include <linux/i2c.h>
5316 +#include <linux/ioport.h>
5317 +#include <linux/delay.h>
5318 +#include "ralink_gdma.h"
5319 +#include "mt76xx_i2s.h"
5320 +#include "mt76xx_machine.h"
5321 +#if defined(CONFIG_SND_SOC_WM8960)
5322 +#include "../codecs/wm8960.h"
5323 +#endif
5324 +
5325 +#define I2C_AUDIO_DEV_ID       (0)
5326 +/****************************/
5327 +/*FUNCTION DECLRATION          */
5328 +/****************************/
5329 +extern unsigned long i2s_codec_12p288Mhz[11];
5330 +extern unsigned long i2s_codec_12Mhz[11];
5331 +
5332 +
5333 +static int mt76xx_codec_clock_hwparams(struct snd_pcm_substream *substream,\
5334 +                               struct snd_pcm_hw_params *params);
5335 +static int mt76xx_codec_startup(struct snd_pcm_substream *substream);
5336 +static int mt76xx_codec_init(struct snd_soc_pcm_runtime *rtd);
5337 +extern struct snd_soc_dai_driver mt76xx_i2s_dai;
5338 +extern struct snd_soc_platform_driver mt76xx_soc_platform;
5339 +struct platform_device *mt76xx_audio_device;
5340 +
5341 +#if defined(CONFIG_SND_SOC_WM8960)
5342 +extern struct snd_soc_dai wm8960_dai;
5343 +extern struct snd_soc_codec_device soc_codec_dev_wm8960;
5344 +#endif
5345 +
5346 +static struct snd_soc_ops mtk_audio_ops = {
5347 +       .hw_params = mt76xx_codec_clock_hwparams,
5348 +       .startup = mt76xx_codec_startup,
5349 +};
5350 +
5351 +static struct snd_soc_dai_link mtk_audio_dai = {
5352 +       .name = "mtk_dai",
5353 +       .stream_name = "WMserious PCM",
5354 +       .cpu_dai_name   = "mt76xx-i2s",
5355 +       .codec_dai_name = "wm8960-hifi",
5356 +       .codec_name     = "wm8960.0-001a",
5357 +       .platform_name  = "mt76xx-pcm",
5358 +       .ignore_pmdown_time = true,
5359 +       .init = mt76xx_codec_init,
5360 +       .ops = &mtk_audio_ops,
5361 +};
5362 +
5363 +static struct snd_soc_card mtk_audio_card = {
5364 +       .name = "MTK APSoC I2S",
5365 +       .owner = THIS_MODULE,
5366 +       .dai_link = &mtk_audio_dai,//I2S/Codec
5367 +       .num_links = 1,
5368 +};
5369 +
5370 +static int mt76xx_codec_clock_hwparams(struct snd_pcm_substream *substream,
5371 +                               struct snd_pcm_hw_params *params)
5372 +{
5373 +       struct snd_soc_pcm_runtime *p = substream->private_data;
5374 +       struct snd_soc_dai *codec_dai = p->codec_dai;
5375 +       struct snd_pcm_runtime *runtime = substream->runtime;
5376 +       i2s_config_type* rtd = runtime->private_data;
5377 +       unsigned long data,index = 0;
5378 +       unsigned long* pTable;
5379 +       int mclk,ret,targetClk = 0;
5380 +
5381 +       printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
5382 +       /*For duplex mode, avoid setting twice.*/
5383 +       if((rtd->bRxDMAEnable == GDMA_I2S_EN) || (rtd->bTxDMAEnable == GDMA_I2S_EN))
5384 +               return 0;
5385 +       //printk("%s:%d \n",__func__,__LINE__);
5386 +#if defined(CONFIG_I2S_MCLK_12MHZ)
5387 +       mclk = 12000000;
5388 +#elif defined(CONFIG_I2S_MCLK_12P288MHZ)
5389 +       mclk = 12288000;
5390 +#else
5391 +       mclk = 12000000;
5392 +#endif
5393 +       //snd_soc_dai_set_sysclk(codec_dai,0,mclk, SND_SOC_CLOCK_IN);
5394 +
5395 +       printk("%s:%s[%d]%d\n", __FILE__, __func__, __LINE__, params_rate(params));
5396 +       switch(params_rate(params)){
5397 +       case 8000:
5398 +               index = 0;
5399 +               targetClk = 12288000;
5400 +               break;
5401 +       case 12000:
5402 +               index = 2;
5403 +               targetClk = 12288000;
5404 +               break;
5405 +       case 16000:
5406 +               index = 3;
5407 +               targetClk = 12288000;
5408 +               break;
5409 +       case 24000:
5410 +               index = 5;
5411 +               targetClk = 12288000;
5412 +               break;
5413 +       case 32000:
5414 +               index = 6;
5415 +               targetClk = 12288000;
5416 +               break;
5417 +       case 48000:
5418 +               index = 8;
5419 +               targetClk = 12288000;
5420 +               break;
5421 +       case 11025:
5422 +               index = 1;
5423 +               targetClk = 11289600;
5424 +               break;
5425 +       case 22050:
5426 +               index = 4;
5427 +               targetClk = 11289600;
5428 +               break;
5429 +       case 44100:
5430 +               index = 7;
5431 +               targetClk = 11289600;
5432 +               break;
5433 +       case 88200:
5434 +               index = 9;
5435 +               targetClk = 11289600;
5436 +               break;
5437 +       case 96000:
5438 +               index = 10;
5439 +               targetClk = 11289600;
5440 +               break;
5441 +       default:
5442 +               index = 7;
5443 +               targetClk = 12288000;
5444 +               //MSG("audio sampling rate %u should be %d ~ %d Hz\n", (u32)params_rate(params), MIN_SRATE_HZ, MAX_SRATE_HZ);
5445 +               break;
5446 +       }
5447 +printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
5448 +#if defined(CONFIG_SND_SOC_WM8960)
5449 +       /*
5450 +        * There is a fixed divide by 4 in the PLL and a selectable
5451 +        * divide by N after the PLL which should be set to divide by 2 to meet this requirement.
5452 +        * */
5453 +       printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
5454 +       ret = snd_soc_dai_set_pll(codec_dai, 0, 0,mclk, targetClk*2);
5455 +       /* From app notes: allow Vref to stabilize to reduce clicks */
5456 +       if(rtd->slave_en){
5457 +               printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
5458 +               //printk("WM8960 is in master mode\n");
5459 +               ret = snd_soc_dai_set_clkdiv(codec_dai, WM8960_DCLKDIV, 0x1c4);
5460 +               ret = snd_soc_dai_set_clkdiv(codec_dai, WM8960_SYSCLKDIV, 0x5);
5461 +       }
5462 +
5463 +#endif
5464 +       if(!rtd->slave_en)
5465 +               snd_soc_dai_set_fmt(codec_dai,SND_SOC_DAIFMT_CBS_CFS|SND_SOC_DAIFMT_I2S|SND_SOC_DAIFMT_NB_NF);
5466 +       else{
5467 +               snd_soc_dai_set_fmt(codec_dai,SND_SOC_DAIFMT_CBM_CFM|SND_SOC_DAIFMT_I2S|SND_SOC_DAIFMT_NB_NF);
5468 +       }
5469 +       mdelay(5);
5470 +
5471 +#if defined(CONFIG_SND_SOC_WM8960)
5472 +#if defined(CONFIG_I2S_MCLK_12MHZ)
5473 +       pTable = i2s_codec_12Mhz;
5474 +       data = pTable[index];
5475 +#else
5476 +       pTable = i2s_codec_12p288Mhz;
5477 +       data = pTable[index];
5478 +#endif
5479 +       printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
5480 +       if(rtd->codec_pll_en)
5481 +               ret = snd_soc_dai_set_clkdiv(codec_dai, WM8960_DACDIV, (data<<3)|0x5);
5482 +       else
5483 +               ret = snd_soc_dai_set_clkdiv(codec_dai, WM8960_DACDIV, (data<<3|0x4));
5484 +printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
5485 +#endif
5486 +
5487 +       return 0;
5488 +}
5489 +
5490 +static int mt76xx_codec_startup(struct snd_pcm_substream *substream)
5491 +{
5492 +       //printk("******* %s *******\n", __func__);
5493 +       return 0;
5494 +}
5495 +static int mt76xx_codec_init(struct snd_soc_pcm_runtime *rtd)
5496 +{
5497 +
5498 +       //printk("******* %s *******\n", __func__);
5499 +       return 0;
5500 +}
5501 +
5502 +static struct i2c_board_info i2c_board_info[] = {
5503 +       {
5504 +#if defined(CONFIG_SND_SOC_WM8750)
5505 +               I2C_BOARD_INFO("wm8750", (0x36 >> 1)),
5506 +#elif defined(CONFIG_SND_SOC_WM8960)
5507 +       //      I2C_BOARD_INFO("wm8960", (0x34 >> 1)),
5508 +               I2C_BOARD_INFO("codec_wm8960", (0x34)),
5509 +#endif
5510 +       },
5511 +};
5512 +
5513 +static struct platform_device *soc_mtk_i2s_dev;
5514 +static struct platform_device *soc_mtk_pcm_dev;
5515 +
5516 +static int __init mt76xx_machine_init(void)
5517 +{
5518 +       //struct snd_soc_device *socdev = &mtk_audio_devdata;
5519 +       //struct i2c_adapter *adapter = NULL;
5520 +       //struct i2c_client *client = NULL;
5521 +       int ret = 0;
5522 +       struct i2c_adapter *adapter = NULL;
5523 +        struct i2c_client *client = NULL;
5524 +
5525 +       adapter = i2c_get_adapter(I2C_AUDIO_DEV_ID);
5526 +       if (!adapter)
5527 +               return -ENODEV;
5528 +       client = i2c_new_device(adapter, i2c_board_info);
5529 +       if (!client)
5530 +               return -ENODEV;
5531 +
5532 +       i2c_put_adapter(adapter);
5533 +       i2c_get_clientdata(client);
5534 +
5535 +       soc_mtk_i2s_dev =
5536 +               platform_device_register_simple("mt76xx-i2s", -1, NULL, 0);
5537 +       if (IS_ERR(soc_mtk_i2s_dev))
5538 +               return PTR_ERR(soc_mtk_i2s_dev);
5539 +
5540 +       soc_mtk_pcm_dev =
5541 +               platform_device_register_simple("mt76xx-pcm", -1, NULL, 0);
5542 +       if (IS_ERR(soc_mtk_pcm_dev))
5543 +               return PTR_ERR(soc_mtk_pcm_dev);
5544 +
5545 +       mt76xx_audio_device = platform_device_alloc("soc-audio",-1);
5546 +       if (mt76xx_audio_device == NULL) {
5547 +               ret = -ENOMEM;
5548 +               goto err_device_alloc;
5549 +       }
5550 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38)
5551 +       platform_set_drvdata(mt76xx_audio_device, &mtk_audio_card);
5552 +#else
5553 +       platform_set_drvdata(mt76xx_audio_device, &mtk_audio_devdata);
5554 +       mtk_audio_devdata.dev = &mt76xx_audio_device->dev;
5555 +#endif
5556 +
5557 +       /*Ralink I2S register process end*/
5558 +       ret = platform_device_add(mt76xx_audio_device);
5559 +       if (ret) {
5560 +               printk("mtk audio device : platform_device_add failed (%d)\n",ret);
5561 +               goto err_device_add;
5562 +       }
5563 +
5564 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38)
5565 +#else
5566 +       snd_soc_register_dai(&mt76xx_i2s_dai);
5567 +#endif
5568 +
5569 +       return 0;
5570 +
5571 +err_device_add:
5572 +       if (mt76xx_audio_device!= NULL) {
5573 +               platform_device_put(mt76xx_audio_device);
5574 +               mt76xx_audio_device = NULL;
5575 +       }
5576 +err_device_alloc:
5577 +       return ret;
5578 +}
5579 +
5580 +
5581 +static void __exit mt76xx_machine_exit(void)
5582 +{
5583 +
5584 +       platform_device_unregister(mt76xx_audio_device);
5585 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,20)
5586 +       /* Do nothing */
5587 +#elif LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38)
5588 +       snd_soc_unregister_platform(&mt76xx_audio_device->dev);
5589 +#else
5590 +       snd_soc_unregister_platform(&mt76xx_soc_platform);
5591 +#endif
5592 +       platform_device_unregister(soc_mtk_i2s_dev);
5593 +       platform_device_unregister(soc_mtk_pcm_dev);
5594 +
5595 +       mt76xx_audio_device = NULL;
5596 +}
5597 +
5598 +//module_init(mt76xx_machine_init);
5599 +late_initcall(mt76xx_machine_init);
5600 +module_exit(mt76xx_machine_exit);
5601 +//EXPORT_SYMBOL_GPL(mt76xx_soc_platform);
5602 +MODULE_LICENSE("GPL");
5603 --- /dev/null
5604 +++ b/sound/soc/mtk/mt76xx_machine.h
5605 @@ -0,0 +1,21 @@
5606 +/*
5607 + * mtk_audio_device.h
5608 + *
5609 + *  Created on: 2013/10/23
5610 + *      Author: MTK04880
5611 + */
5612 +
5613 +#ifndef MT76XX_MACHINE_H_
5614 +#define MT76XX_MACHINE_H_
5615 +#include <sound/pcm.h>
5616 +#include <sound/pcm_params.h>
5617 +#include <sound/soc.h>
5618 +#include <sound/soc-dapm.h>
5619 +
5620 +#if 0
5621 +#ifdef CONFIG_I2S_MMAP
5622 +#undef CONFIG_I2S_MMAP
5623 +#endif
5624 +#endif
5625 +
5626 +#endif /* MT76XX_MACHINE_H_ */
5627 --- /dev/null
5628 +++ b/sound/soc/mtk/mt76xx_pcm.c
5629 @@ -0,0 +1,499 @@
5630 +/*
5631 + * mt76xx_pcm.c
5632 + *
5633 + *  Created on: 2013/9/6
5634 + *      Author: MTK04880
5635 + */
5636 +
5637 +#include <linux/init.h>
5638 +#include <linux/version.h>
5639 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
5640 +#include <linux/sched.h>
5641 +#endif
5642 +#include <linux/module.h>
5643 +#include <linux/kernel.h> /* printk() */
5644 +#include <linux/slab.h> /* kmalloc() */
5645 +#include <linux/fs.h> /* everything... */
5646 +#include <linux/errno.h> /* error codes */
5647 +#include <linux/types.h> /* size_t */
5648 +#include <linux/proc_fs.h>
5649 +#include <linux/fcntl.h> /* O_ACCMODE */
5650 +#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,36)
5651 +#include <asm/system.h> /* cli(), *_flags */
5652 +#endif
5653 +#include <asm/uaccess.h> /* copy_from/to_user */
5654 +#include <linux/interrupt.h>
5655 +#include <linux/mm.h>
5656 +#include <linux/dma-mapping.h>
5657 +#include <sound/core.h>
5658 +#include <linux/pci.h>
5659 +#include <sound/pcm.h>
5660 +#include <sound/pcm_params.h>
5661 +#include <sound/soc.h>
5662 +#include <sound/soc-dapm.h>
5663 +#include <sound/initval.h>
5664 +#include "ralink_gdma.h"
5665 +#include "mt76xx_i2s.h"
5666 +
5667 +#define GDMA_PAGE_SIZE                 I2S_PAGE_SIZE
5668 +#define GDMA_PAGE_NUM          MAX_I2S_PAGE
5669 +#define GDMA_TOTAL_PAGE_SIZE   I2S_TOTAL_PAGE_SIZE
5670 +
5671 +dma_addr_t i2s_txdma_addr, i2s_rxdma_addr;
5672 +dma_addr_t i2s_mmap_addr[GDMA_PAGE_NUM*2];
5673 +
5674 +extern struct tasklet_struct i2s_tx_tasklet;
5675 +extern struct tasklet_struct i2s_rx_tasklet;
5676 +extern int i2s_mmap_remap(struct vm_area_struct *vma, unsigned long size);
5677 +extern void i2s_tx_end_sleep_on(i2s_config_type* ptri2s_config);
5678 +extern void i2s_rx_end_sleep_on(i2s_config_type* ptri2s_config);
5679 +
5680 +static int mt76xx_pcm_open(struct snd_pcm_substream *substream);
5681 +static int mt76xx_pcm_new(struct snd_soc_pcm_runtime *rtd);
5682 +static void mt76xx_pcm_free(struct snd_pcm *pcm);
5683 +static int mt76xx_pcm_close(struct snd_pcm_substream *substream);
5684 +static snd_pcm_uframes_t mt76xx_pcm_pointer(struct snd_pcm_substream *substream);
5685 +static int mt76xx_pcm_trigger(struct snd_pcm_substream *substream, int cmd);
5686 +static int mt76xx_pcm_prepare(struct snd_pcm_substream *substream);
5687 +static int mt76xx_pcm_hw_params(struct snd_pcm_substream *substream,\
5688 +                                struct snd_pcm_hw_params *hw_params);
5689 +static int mt76xx_pcm_copy(struct snd_pcm_substream *substream, int channel,\
5690 +               snd_pcm_uframes_t pos,void __user *buf, snd_pcm_uframes_t count);
5691 +static int mt76xx_pcm_mmap(struct snd_pcm_substream *substream, struct vm_area_struct *vma);
5692 +static int mt76xx_pcm_hw_free(struct snd_pcm_substream *substream);
5693 +
5694 +static int mt76xx_pcm_free_dma_buffer(struct snd_pcm_substream *substream,int stream);
5695 +static int mt76xx_pcm_allocate_dma_buffer(struct snd_pcm_substream *substream,int stream);
5696 +
5697 +#if LINUX_VERSION_CODE > KERNEL_VERSION(3,10,20)
5698 +static int mt76xx_platform_drv_probe(struct platform_device *pdev);
5699 +static int mt76xx_platform_drv_remove(struct platform_device *pdev);
5700 +#endif
5701 +
5702 +static const struct snd_pcm_hardware mt76xx_pcm_hwparam = {
5703 +#if defined(CONFIG_I2S_MMAP)
5704 +       .info                   = (SNDRV_PCM_INFO_INTERLEAVED |
5705 +                               SNDRV_PCM_INFO_PAUSE |
5706 +                               SNDRV_PCM_INFO_RESUME |
5707 +                               SNDRV_PCM_INFO_MMAP |
5708 +                               SNDRV_PCM_INFO_MMAP_VALID),
5709 +#else
5710 +       .info                   = (SNDRV_PCM_INFO_INTERLEAVED |
5711 +                               SNDRV_PCM_INFO_PAUSE |
5712 +                               SNDRV_PCM_INFO_RESUME),
5713 +#endif
5714 +       .formats                = SNDRV_PCM_FMTBIT_S16_LE,
5715 +       .period_bytes_min       = GDMA_PAGE_SIZE,
5716 +       .period_bytes_max       = GDMA_PAGE_SIZE,
5717 +       .periods_min            = 1,
5718 +       .periods_max            = GDMA_PAGE_NUM,
5719 +       .buffer_bytes_max       = GDMA_TOTAL_PAGE_SIZE,
5720 +};
5721 +
5722 +static struct snd_pcm_ops mt76xx_pcm_ops = {
5723 +
5724 +       .open =         mt76xx_pcm_open,
5725 +       .ioctl =        snd_pcm_lib_ioctl,
5726 +       .hw_params =    mt76xx_pcm_hw_params,
5727 +       .hw_free =      mt76xx_pcm_hw_free,
5728 +       .trigger =      mt76xx_pcm_trigger,
5729 +       .prepare =      mt76xx_pcm_prepare,
5730 +       .pointer =      mt76xx_pcm_pointer,
5731 +       .close =        mt76xx_pcm_close,
5732 +#if defined(CONFIG_I2S_MMAP)
5733 +       .mmap = mt76xx_pcm_mmap,
5734 +#endif
5735 +       .copy = mt76xx_pcm_copy,
5736 +};
5737 +#if LINUX_VERSION_CODE > KERNEL_VERSION(3,10,0)
5738 +struct snd_soc_platform_driver mt76xx_soc_platform = {
5739 +       .ops            = &mt76xx_pcm_ops,
5740 +       .pcm_new        = mt76xx_pcm_new,
5741 +       .pcm_free       = mt76xx_pcm_free,
5742 +};
5743 +#else
5744 +struct snd_soc_platform mt76xx_soc_platform = {
5745 +       .name           = "mtk-dma",
5746 +       .pcm_ops        = &mt76xx_pcm_ops,
5747 +       .pcm_new        = mt76xx_pcm_new,
5748 +       .pcm_free       = mt76xx_pcm_free,
5749 +};
5750 +#endif
5751 +
5752 +static int mt76xx_pcm_close(struct snd_pcm_substream *substream){
5753 +
5754 +       //printk("******* %s *********\n", __func__);
5755 +       return 0;
5756 +}
5757 +
5758 +static snd_pcm_uframes_t mt76xx_pcm_pointer(struct snd_pcm_substream *substream)
5759 +{
5760 +       struct snd_pcm_runtime *runtime = substream->runtime;
5761 +       i2s_config_type* rtd = runtime->private_data;
5762 +       unsigned int offset = 0;
5763 +       //int buff_frame_bond = bytes_to_frames(runtime, GDMA_PAGE_SIZE);
5764 +       //printk("\n******* %s *********\n", __func__);
5765 +
5766 +       if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK){
5767 +               offset = bytes_to_frames(runtime, GDMA_PAGE_SIZE*rtd->tx_r_idx);
5768 +               //printk("r:%d w:%d (%d) \n",rtd->tx_r_idx,rtd->tx_w_idx,(runtime->control->appl_ptr/buff_frame_bond)%GDMA_PAGE_NUM);
5769 +       }
5770 +       else{
5771 +               offset = bytes_to_frames(runtime, GDMA_PAGE_SIZE*rtd->rx_w_idx);
5772 +               //printk("w:%d r:%d appl_ptr:%x\n",rtd->rx_w_idx,rtd->rx_r_idx,(runtime->control->appl_ptr/buff_frame_bond)%GDMA_PAGE_NUM);
5773 +       }
5774 +       return offset;
5775 +}
5776 +
5777 +
5778 +static int mt76xx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
5779 +{
5780 +       int ret = 0;
5781 +       i2s_config_type* rtd = (i2s_config_type*)substream->runtime->private_data;
5782 +       //struct snd_pcm_runtime *runtime= substream->runtime;
5783 +
5784 +       //printk("******* %s *********\n", __func__);
5785 +/*     printk("trigger cmd:%s\n",(cmd==SNDRV_PCM_TRIGGER_START)?"START":\
5786 +                       (cmd==SNDRV_PCM_TRIGGER_RESUME)?"RESUME":\
5787 +                       (cmd==SNDRV_PCM_TRIGGER_PAUSE_RELEASE)?"PAUSE_RELEASE":\
5788 +                       (cmd==SNDRV_PCM_TRIGGER_STOP)?"STOP":\
5789 +                       (cmd==SNDRV_PCM_TRIGGER_SUSPEND)?"SUSPEND":\
5790 +                       (cmd==SNDRV_PCM_TRIGGER_PAUSE_PUSH)?"PAUSE_PUSH":"default");
5791 +*/
5792 +       switch (cmd) {
5793 +       case SNDRV_PCM_TRIGGER_START:
5794 +               if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5795 +                       rtd->bTrigger[SNDRV_PCM_STREAM_PLAYBACK] = 1;
5796 +               } else {
5797 +                       rtd->bTrigger[SNDRV_PCM_STREAM_CAPTURE] = 1;
5798 +               }
5799 +               break;
5800 +       case SNDRV_PCM_TRIGGER_STOP:
5801 +               if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5802 +                       rtd->bTrigger[SNDRV_PCM_STREAM_PLAYBACK] = 0;
5803 +               } else {
5804 +                       rtd->bTrigger[SNDRV_PCM_STREAM_CAPTURE] = 0;
5805 +               }
5806 +               break;
5807 +       case SNDRV_PCM_TRIGGER_RESUME:
5808 +       case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
5809 +               if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK){
5810 +                       rtd->tx_pause_en = 0;
5811 +               } else {
5812 +                       rtd->rx_pause_en = 0;
5813 +               }
5814 +               break;
5815 +
5816 +       case SNDRV_PCM_TRIGGER_SUSPEND:
5817 +       case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
5818 +               if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK){
5819 +                       rtd->tx_pause_en = 1;
5820 +               } else {
5821 +                       rtd->rx_pause_en = 1;
5822 +               }
5823 +               break;
5824 +       default:
5825 +               ret = -EINVAL;
5826 +               break;
5827 +       }
5828 +       return ret;
5829 +}
5830 +
5831 +static int mt76xx_pcm_copy(struct snd_pcm_substream *substream, int channel,\
5832 +               snd_pcm_uframes_t pos,void __user *buf, snd_pcm_uframes_t count)
5833 +{
5834 +       struct snd_pcm_runtime *runtime= substream->runtime;
5835 +       i2s_config_type* rtd = runtime->private_data;
5836 +       int tx_w_idx = 0;
5837 +        int rx_r_idx = 0;
5838 +        char *hwbuf = NULL;
5839 +
5840 +       //printk("******* %s *********\n", __func__);
5841 +       hwbuf = runtime->dma_area + frames_to_bytes(runtime, pos);
5842 +       //MSG("%s bur:%x\n",__func__,hwbuf);
5843 +       //printk("hw_ptr:%d, buffer_size:%d, appl_prt:%d, boundary:%d\n",
5844 +       //              runtime->status->hw_ptr, runtime->buffer_size, runtime->control->appl_ptr, runtime->boundary);
5845 +
5846 +       if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK){
5847 +               rtd->tx_w_idx = (rtd->tx_w_idx+1)%MAX_I2S_PAGE;
5848 +                tx_w_idx = rtd->tx_w_idx;
5849 +                //printk("put TB[%d - %x] for user write\n",rtd->tx_w_idx,pos);
5850 +                copy_from_user(rtd->pMMAPTxBufPtr[tx_w_idx], (char*)buf, I2S_PAGE_SIZE);
5851 +       }
5852 +       else{
5853 +               rx_r_idx = rtd->rx_r_idx;
5854 +                rtd->rx_r_idx = (rtd->rx_r_idx+1)%MAX_I2S_PAGE;
5855 +                copy_to_user((char*)buf, rtd->pMMAPRxBufPtr[rx_r_idx], I2S_PAGE_SIZE);
5856 +       }
5857 +       return 0;
5858 +}
5859 +
5860 +static int mt76xx_pcm_mmap(struct snd_pcm_substream *substream, struct vm_area_struct *vma)
5861 +{
5862 +        int ret;
5863 +        unsigned long size;
5864 +
5865 +        size = vma->vm_end-vma->vm_start;
5866 +        printk("******* %s: size :%lx end:%lx start:%lx *******\n", __func__,size,vma->vm_end,vma->vm_start);
5867 +        ret = i2s_mmap_remap(vma, size);
5868 +
5869 +        return ret;
5870 +}
5871 +
5872 +
5873 +static int mt76xx_pcm_prepare(struct snd_pcm_substream *substream)
5874 +{
5875 +       struct snd_pcm_runtime *runtime= substream->runtime;
5876 +       i2s_config_type *rtd = (i2s_config_type*)runtime->private_data;
5877 +       //runtime->buffer_size = GDMA_PAGE_NUM*GDMA_PAGE_SIZE;
5878 +       //runtime->boundary = (GDMA_PAGE_NUM*GDMA_PAGE_SIZE)/4;
5879 +
5880 +       //printk("******* %s *******\n", __func__);
5881 +       if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK){
5882 +               //printk("===== %s:%s:%d =====\n", __FILE__, __func__, __LINE__);
5883 +               mt76xx_pcm_allocate_dma_buffer(substream,SNDRV_PCM_STREAM_PLAYBACK);
5884 +
5885 +               if(! rtd->dmaStat[SNDRV_PCM_STREAM_PLAYBACK]){
5886 +                       i2s_page_prepare(rtd,STREAM_PLAYBACK);
5887 +                       tasklet_init(&i2s_tx_tasklet, i2s_tx_task, (u32)rtd);
5888 +                       rtd->dmaStat[SNDRV_PCM_STREAM_PLAYBACK] = 1;
5889 +                       gdma_unmask_handler(GDMA_I2S_TX0);
5890 +               }
5891 +       } else {
5892 +               mt76xx_pcm_allocate_dma_buffer(substream,SNDRV_PCM_STREAM_CAPTURE);
5893 +
5894 +               if(! rtd->dmaStat[SNDRV_PCM_STREAM_CAPTURE]){
5895 +                       i2s_page_prepare(rtd,STREAM_CAPTURE); /* TX:enLabel=1; RX:enLabel=2 */
5896 +                       tasklet_init(&i2s_rx_tasklet, i2s_rx_task, (u32)rtd);
5897 +                       rtd->dmaStat[SNDRV_PCM_STREAM_CAPTURE] = 1;
5898 +                       gdma_unmask_handler(GDMA_I2S_RX0);
5899 +               }
5900 +       }
5901 +
5902 +       return 0;
5903 +}
5904 +
5905 +
5906 +static int mt76xx_pcm_hw_params(struct snd_pcm_substream *substream,
5907 +                                struct snd_pcm_hw_params *hw_params)
5908 +{
5909 +       /*struct snd_pcm_runtime *runtime = substream->runtime;
5910 +       i2s_config_type *rtd = (i2s_config_type*)runtime->private_data;
5911 +       */
5912 +       int ret,i;
5913 +       ret = i = 0;
5914 +
5915 +       //printk("******* %s *******\n", __func__);
5916 +       if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK){
5917 +               //i2s_page_prepare(rtd,STREAM_PLAYBACK);
5918 +       } else {
5919 +               //i2s_page_prepare(rtd,STREAM_CAPTURE);
5920 +       }
5921 +
5922 +       return ret;
5923 +}
5924 +
5925 +static int mt76xx_pcm_hw_free(struct snd_pcm_substream *substream)
5926 +{
5927 +       i2s_config_type* rtd = (i2s_config_type*)substream->runtime->private_data;
5928 +       //struct snd_dma_buffer *buf = &substream->dma_buffer;
5929 +
5930 +       //printk("******* %s *******\n", __func__);
5931 +       if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK){
5932 +               if(rtd->dmaStat[SNDRV_PCM_STREAM_PLAYBACK]){
5933 +
5934 +                       gdma_En_Switch(rtd,STREAM_PLAYBACK,GDMA_I2S_DIS);
5935 +                       i2s_tx_end_sleep_on(rtd);
5936 +                       tasklet_kill(&i2s_tx_tasklet);
5937 +                       i2s_tx_disable(rtd);
5938 +                       //mt76xx_pcm_free_dma_buffer(substream,substream->stream);
5939 +                       i2s_page_release(rtd,STREAM_PLAYBACK);
5940 +                       rtd->dmaStat[SNDRV_PCM_STREAM_PLAYBACK] = 0;
5941 +               }
5942 +               mt76xx_pcm_free_dma_buffer(substream,substream->stream);
5943 +       }
5944 +       else{
5945 +               if(rtd->dmaStat[SNDRV_PCM_STREAM_CAPTURE]){
5946 +
5947 +                       gdma_En_Switch(rtd,STREAM_CAPTURE,GDMA_I2S_DIS);
5948 +                       i2s_tx_end_sleep_on(rtd);
5949 +                       tasklet_kill(&i2s_rx_tasklet);
5950 +                       i2s_rx_disable(rtd);
5951 +                       //mt76xx_pcm_free_dma_buffer(substream,substream->stream);
5952 +                       i2s_page_release(rtd,STREAM_CAPTURE);
5953 +                       rtd->dmaStat[SNDRV_PCM_STREAM_CAPTURE] = 0;
5954 +               }
5955 +               mt76xx_pcm_free_dma_buffer(substream,substream->stream);
5956 +       }
5957 +       return 0;
5958 +}
5959 +
5960 +static int mt76xx_pcm_free_dma_buffer(struct snd_pcm_substream *substream,
5961 +       int stream)
5962 +{
5963 +
5964 +       //struct snd_pcm_substream *substream = pcm->streams[stream].substream;
5965 +       struct snd_dma_buffer *buf = &substream->dma_buffer;
5966 +       i2s_config_type* rtd = (i2s_config_type*)substream->runtime->private_data;
5967 +
5968 +       //printk("******* %s *******\n", __func__);
5969 +       if (!buf->area)
5970 +               return 0;
5971 +       if(substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5972 +               i2s_memPool_free(rtd,STREAM_PLAYBACK);
5973 +       else
5974 +               i2s_memPool_free(rtd,STREAM_CAPTURE);
5975 +       buf->area = NULL;
5976 +       snd_pcm_set_runtime_buffer(substream, NULL);
5977 +       return 0;
5978 +}
5979 +
5980 +static int mt76xx_pcm_allocate_dma_buffer(struct snd_pcm_substream *substream,
5981 +       int stream)
5982 +{
5983 +       //struct snd_pcm_substream *substream = pcm->streams[stream].substream;
5984 +       struct snd_dma_buffer *buf = &substream->dma_buffer;
5985 +       i2s_config_type* rtd = (i2s_config_type*)substream->runtime->private_data;
5986 +
5987 +       //printk("******* %s *******\n", __func__);
5988 +       if(!buf->area){
5989 +#if defined(CONFIG_I2S_MMAP)
5990 +               printk("\n############## MMAP ##############\n");
5991 +               buf->dev.type = SNDRV_DMA_TYPE_DEV;
5992 +#else
5993 +               buf->dev.type = SNDRV_DMA_TYPE_UNKNOWN;
5994 +#endif
5995 +               buf->dev.dev = NULL;
5996 +               buf->private_data = NULL;
5997 +               if(stream == SNDRV_PCM_STREAM_PLAYBACK)
5998 +                       buf->area = i2s_memPool_Alloc(rtd,STREAM_PLAYBACK);
5999 +               else
6000 +                       buf->area = i2s_memPool_Alloc(rtd,STREAM_CAPTURE);
6001 +
6002 +               if (!buf->area)
6003 +                       return -ENOMEM;
6004 +               buf->bytes = GDMA_TOTAL_PAGE_SIZE;
6005 +#if defined(CONFIG_I2S_MMAP)
6006 +               buf->addr = i2s_mmap_phys_addr(rtd);
6007 +#endif
6008 +               snd_pcm_set_runtime_buffer(substream, buf);
6009 +       } else{
6010 +               //printk("Buffer have been allocated!\n");
6011 +       }
6012 +
6013 +       return 0;
6014 +}
6015 +
6016 +static int mt76xx_pcm_open(struct snd_pcm_substream *substream)
6017 +{
6018 +       struct snd_pcm_runtime *runtime= substream->runtime;
6019 +       struct snd_dma_buffer *buf = &substream->dma_buffer;
6020 +       int stream = substream->stream;
6021 +       int ret = 0;
6022 +
6023 +       //printk("******* %s *******\n", __func__);
6024 +       snd_soc_set_runtime_hwparams(substream, &mt76xx_pcm_hwparam);
6025 +       /* ensure that buffer size is a multiple of period size */
6026 +       ret = snd_pcm_hw_constraint_integer(runtime,
6027 +                                               SNDRV_PCM_HW_PARAM_PERIODS);
6028 +       if (ret < 0)
6029 +               goto out;
6030 +
6031 +#if 1
6032 +       if(stream == SNDRV_PCM_STREAM_PLAYBACK){
6033 +               ret = mt76xx_pcm_allocate_dma_buffer(substream,
6034 +                               SNDRV_PCM_STREAM_PLAYBACK);
6035 +       }
6036 +       else{
6037 +               ret = mt76xx_pcm_allocate_dma_buffer(substream,
6038 +                               SNDRV_PCM_STREAM_CAPTURE);
6039 +       }
6040 +#endif
6041 +
6042 +       if (ret)
6043 +               goto out;
6044 +
6045 +       if(buf)
6046 +               memset(buf->area,0,sizeof(I2S_PAGE_SIZE*MAX_I2S_PAGE));
6047 +
6048 + out:
6049 +       return ret;
6050 +}
6051 +
6052 +
6053 +
6054 +static int mt76xx_pcm_new(struct snd_soc_pcm_runtime *rtd)
6055 +{
6056 +//     int ret = 0;
6057 +
6058 +       //printk("******* %s *******\n", __func__);
6059 +       return 0;
6060 +}
6061 +
6062 +static void mt76xx_pcm_free(struct snd_pcm *pcm)
6063 +{
6064 +       /*struct snd_pcm_substream *substream;
6065 +       struct snd_dma_buffer *buf;
6066 +       i2s_config_type* rtd;
6067 +       int stream;
6068 +*/
6069 +       //printk("******* %s *******\n", __func__);
6070 +       //return 0;
6071 +}
6072 +
6073 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,20)
6074 +static int mt76xx_platform_drv_probe(struct platform_device *pdev)
6075 +{
6076 +       //printk("******* %s *******\n", __func__);
6077 +       return snd_soc_register_platform(&pdev->dev, &mt76xx_soc_platform);
6078 +}
6079 +
6080 +static int mt76xx_platform_drv_remove(struct platform_device *pdev)
6081 +{
6082 +       //printk("******* %s *******\n", __func__);
6083 +       snd_soc_unregister_platform(&pdev->dev);
6084 +       return 0;
6085 +}
6086 +
6087 +static struct platform_driver mt76xx_pcm_driver = {
6088 +       .driver = {
6089 +               .name = "mt76xx-pcm",
6090 +               .owner = THIS_MODULE,
6091 +       },
6092 +
6093 +       .probe = mt76xx_platform_drv_probe,
6094 +       .remove = mt76xx_platform_drv_remove,
6095 +};
6096 +
6097 +static int __init mt76xx_pcm_init(void)
6098 +{
6099 +
6100 +       printk("******* %s *******\n", __func__);
6101 +       return platform_driver_register(&mt76xx_pcm_driver);
6102 +}
6103 +
6104 +static void __exit mt76xx_pcm_exit(void)
6105 +{
6106 +       platform_driver_unregister(&mt76xx_pcm_driver);
6107 +}
6108 +#else
6109 +static int __init mt76xx_pcm_init(void)
6110 +{
6111 +
6112 +       printk("******* %s *******\n", __func__);
6113 +       return snd_soc_register_platform(&mt76xx_soc_platform);
6114 +}
6115 +
6116 +static void __exit mt76xx_pcm_exit(void)
6117 +{
6118 +       printk("******* %s *******\n", __func__);
6119 +       snd_soc_unregister_platform(&mt76xx_soc_platform);
6120 +}
6121 +#endif
6122 +module_init(mt76xx_pcm_init);
6123 +module_exit(mt76xx_pcm_exit);
6124 +
6125 +MODULE_AUTHOR("Dora Chen");
6126 +MODULE_DESCRIPTION("MTK APSoC I2S DMA driver");
6127 +MODULE_LICENSE("GPL");
6128 +
6129 --- /dev/null
6130 +++ b/sound/soc/mtk/ralink_gdma.c
6131 @@ -0,0 +1,918 @@
6132 +/*
6133 + ***************************************************************************
6134 + * Ralink Tech Inc.
6135 + * 5F., No.36, Taiyuan St., Jhubei City,
6136 + * Hsinchu County 302,
6137 + * Taiwan, R.O.C.
6138 + *
6139 + * (c) Copyright, Ralink Technology, Inc.
6140 + *
6141 + *  This program is free software; you can redistribute  it and/or modify it
6142 + *  under  the terms of  the GNU General  Public License as published by the
6143 + *  Free Software Foundation;  either version 2 of the  License, or (at your
6144 + *  option) any later version.
6145 + *
6146 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
6147 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
6148 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
6149 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
6150 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6151 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
6152 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6153 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
6154 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6155 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6156 + *
6157 + *  You should have received a copy of the  GNU General Public License along
6158 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
6159 + *  675 Mass Ave, Cambridge, MA 02139, USA.
6160 + *
6161 + *
6162 + ***************************************************************************
6163 + *
6164 +  Module Name:
6165 +  ralink_gdma.c
6166 +
6167 +  Abstract:
6168 +
6169 +  Revision History:
6170 +  Who         When            What
6171 +  --------    ----------      ----------------------------------------------
6172 +  Name        Date            Modification logs
6173 +  Steven Liu  2009-03-24      Support RT3883
6174 + *
6175 + */
6176 +#include <linux/init.h>
6177 +#include <linux/version.h>
6178 +#include <linux/module.h>
6179 +#include <linux/kernel.h>
6180 +#include <linux/interrupt.h>
6181 +#include <linux/fs.h>
6182 +#if defined (CONFIG_MIPS)
6183 +  #include <asm/uaccess.h>
6184 +  #include <asm/addrspace.h>
6185 +#endif
6186 +
6187 +#include "ralink_gdma.h"
6188 +
6189 +/*
6190 + * RT305x:
6191 + * Ch0 : Pcm0_Rx0 | Pcm0_Rx0 | ALL
6192 + * Ch1 : Pcm0_Rx1 | Pcm0_Rx1 | ALL
6193 + * Ch2 : Pcm0_Tx0 | Pcm0_Tx0 | ALL
6194 + * Ch3 : Pcm0_Tx1 | Pcm0_Tx1 | ALL
6195 + * Ch4 : Pcm1_Rx0 | I2S_Tx0  | ALL
6196 + * Ch5 : Pcm1_Rx1 | I2S_Tx1  | ALL
6197 + * Ch6 : Pcm1_Tx0 |  ALL     | ALL
6198 + * Ch7 : Pcm1_Tx1 |  ALL     | ALL
6199 + *
6200 + * RT3883:
6201 + * Ch0  : Pcm0_Rx0 | Pcm0_Rx0 | ALL
6202 + * Ch1  : Pcm0_Rx1 | Pcm0_Rx1 | ALL
6203 + * Ch2  : Pcm0_Tx0 | Pcm0_Tx0 | ALL
6204 + * Ch3  : Pcm0_Tx1 | Pcm0_Tx1 | ALL
6205 + * Ch4  : Pcm1_Rx0 | I2S_Tx0  | ALL
6206 + * Ch5  : Pcm1_Rx1 | I2S_Tx1  | ALL
6207 + * Ch6  : Pcm1_Tx0 | I2S_Rx0  | ALL
6208 + * Ch7  : Pcm1_Tx1 | I2S_Rx1  | ALL
6209 + * Ch8  : ALL     |  ALL     | ALL
6210 + * Ch9  : ALL     |  ALL     | ALL
6211 + * Ch10 : ALL     |  ALL     | ALL
6212 + * Ch11 : ALL     |  ALL     | ALL
6213 + * Ch12 : ALL     |  ALL     | ALL PCI TX
6214 + * Ch13 : ALL     |  ALL     | ALL PCI RX
6215 + * Ch14 : ALL     |  ALL     | ALL
6216 + * Ch15 : ALL     |  ALL     | ALL
6217 + *
6218 + */
6219 +
6220 +spinlock_t  gdma_lock;
6221 +spinlock_t  gdma_lock_mem;
6222 +spinlock_t  gdma_int_lock;
6223 +void (*GdmaDoneIntCallback[MAX_GDMA_CHANNEL])(uint32_t);
6224 +void (*GdmaUnMaskIntCallback[MAX_GDMA_CHANNEL])(uint32_t);
6225 +
6226 +
6227 +/**
6228 + * @brief Get free GDMA channel
6229 + *
6230 + * @param  ChNum   GDMA channel number
6231 + * @retval 1      channel is available
6232 + * @retval 0      channels are all busy
6233 + */
6234 +int _GdmaGetFreeCh(uint32_t *ChNum)
6235 +{
6236 +    unsigned long flags;
6237 +    uint32_t Data=0;
6238 +    uint32_t Ch=0;
6239 +#if defined (CONFIG_GDMA_DEBUG)
6240 +    static uint32_t Ch_RR=0;
6241 +#endif
6242 +
6243 +    spin_lock_irqsave(&gdma_lock, flags);
6244 +
6245 +#if defined (CONFIG_GDMA_PCM_ONLY)
6246 +#if defined (CONFIG_RALINK_RT3883) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A) || defined (CONFIG_RALINK_MT7620)  ||  defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628) || defined (CONFIG_ARCH_MT7623)
6247 +    for(Ch=14; Ch<MAX_GDMA_CHANNEL;Ch++)  //channel 14~max_channe, channel 0~13 be usedl
6248 +#else
6249 +    for(Ch=MAX_GDMA_CHANNEL; Ch<MAX_GDMA_CHANNEL;Ch++)  //no free channel
6250 +#endif
6251 +#elif defined (CONFIG_GDMA_PCM_I2S_OTHERS)
6252 +#if defined (CONFIG_RALINK_RT3883) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A) || defined (CONFIG_RALINK_MT7620)  ||  defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628) || defined (CONFIG_ARCH_MT7623)
6253 +    for(Ch=14; Ch<MAX_GDMA_CHANNEL;Ch++)  //channel 14~max_channe, channel 0~13 be usedl
6254 +#else
6255 +    for(Ch=6; Ch<MAX_GDMA_CHANNEL;Ch++)  //channel 6~max_channel
6256 +#endif
6257 +#elif defined (CONFIG_GDMA_EVERYBODY)
6258 +    for(Ch=0; Ch<MAX_GDMA_CHANNEL;Ch++)  //all channel
6259 +#elif defined (CONFIG_GDMA_DEBUG)
6260 +    for(Ch=(Ch_RR++)%MAX_GDMA_CHANNEL; Ch<MAX_GDMA_CHANNEL;Ch++)  //round robin
6261 +#endif
6262 +    {
6263 +       Data=GDMA_READ_REG(GDMA_CTRL_REG(Ch));
6264 +
6265 +       /* hardware will reset this bit if transaction is done.
6266 +        * It means channel is free */
6267 +       if((Data & (0x01<<CH_EBL_OFFSET))==0) {
6268 +           *ChNum = Ch;
6269 +           spin_unlock_irqrestore(&gdma_lock, flags);
6270 +           return 1; //Channel is free
6271 +       }
6272 +    }
6273 +
6274 +    spin_unlock_irqrestore(&gdma_lock, flags);
6275 +    return 0; // Channels are all busy
6276 +
6277 +}
6278 +
6279 +/**
6280 + * @brief Set channel is masked
6281 + *
6282 + * When channel is masked, the GDMA transaction will stop.
6283 + * When GDMA controller comes back from another channel (chain feature)
6284 + *
6285 + * >> Channel Mask=0: It's strange, and turns on related bit in GDMA interrupt
6286 + * status register (16:23 Unmasked)
6287 + *
6288 + * >> Channel Mask=1: It'll start GDMA transation, and clear this bit.
6289 + *
6290 + * @param  ChNum       GDMA channel number
6291 + * @retval 1           success
6292 + * @retval 0           fail
6293 + */
6294 +int GdmaMaskChannel(uint32_t ChNum)
6295 +{
6296 +    uint32_t Data=0;
6297 +
6298 +    Data=GDMA_READ_REG(GDMA_CTRL_REG1(ChNum));
6299 +    Data |= ( 0x01 << CH_MASK_OFFSET);
6300 +    GDMA_WRITE_REG(GDMA_CTRL_REG1(ChNum), Data);
6301 +    GDMA_PRINT("%s: Write %0X to %X\n", __FUNCTION__, Data, GDMA_CTRL_REG1(ChNum));
6302 +
6303 +    return 1;
6304 +}
6305 +
6306 +/**
6307 + * @brief Set channel is unmasked
6308 + *
6309 + * You can unmask the channel to start GDMA transaction.
6310 + *
6311 + * When GDMA controller comes back from another channel (chain feature)
6312 + *
6313 + * >> Channel Mask=0: It's strange, and turns on related bit in GDMA interrupt
6314 + * status register (16:23 Unmasked)
6315 + *
6316 + * >> Channel Mask=1: It'll start GDMA transation, and clear this bit.
6317 + *
6318 + * @param  ChNum       GDMA channel number
6319 + * @retval 1           success
6320 + * @retval 0           fail
6321 + */
6322 +int GdmaUnMaskChannel(uint32_t ChNum)
6323 +{
6324 +    uint32_t Data=0;
6325 +
6326 +    Data=GDMA_READ_REG(GDMA_CTRL_REG1(ChNum));
6327 +    Data &= ~( 0x01 << CH_MASK_OFFSET);
6328 +    GDMA_WRITE_REG(GDMA_CTRL_REG1(ChNum), Data);
6329 +    GDMA_PRINT("%s: Write %0X to %X\n", __FUNCTION__, Data, GDMA_CTRL_REG1(ChNum));
6330 +
6331 +    return 1;
6332 +}
6333 +
6334 +/**
6335 + * @brief Insert new GDMA entry to start GDMA transaction
6336 + *
6337 + * @param  ChNum       GDMA channel number
6338 + * @retval 1           success
6339 + * @retval 0           fail
6340 + */
6341 +int GdmaReqQuickIns(uint32_t ChNum)
6342 +{
6343 +    uint32_t Data=0;
6344 +
6345 +    //Mask Channel
6346 +    Data = GDMA_READ_REG(GDMA_CTRL_REG1(ChNum));
6347 +    Data |= ( 0x1 << CH_MASK_OFFSET);
6348 +    GDMA_WRITE_REG(GDMA_CTRL_REG1(ChNum), Data);
6349 +
6350 +    //Channel Enable
6351 +    Data = GDMA_READ_REG(GDMA_CTRL_REG(ChNum));
6352 +    Data |= (0x01<<CH_EBL_OFFSET);
6353 +    GDMA_WRITE_REG(GDMA_CTRL_REG(ChNum), Data);
6354 +
6355 +    return 1;
6356 +
6357 +}
6358 +
6359 +int _GdmaReqEntryIns(GdmaReqEntry *NewEntry)
6360 +{
6361 +    uint32_t Data=0;
6362 +
6363 +    GDMA_PRINT("== << GDMA Control Reg (Channel=%d) >> ===\n", NewEntry->ChNum);
6364 +    GDMA_PRINT(" Channel Source Addr = %x \n", NewEntry->Src);
6365 +    GDMA_PRINT(" Channel Dest Addr = %x \n", NewEntry->Dst);
6366 +    GDMA_PRINT(" Transfer Count=%d\n", NewEntry->TransCount);
6367 +    GDMA_PRINT(" Source DMA Req= DMA_REQ%d\n", NewEntry->SrcReqNum);
6368 +    GDMA_PRINT(" Dest DMA Req= DMA_REQ%d\n", NewEntry->DstReqNum);
6369 +    GDMA_PRINT(" Source Burst Mode=%s\n", NewEntry->SrcBurstMode ? "Fix" : "Inc");
6370 +    GDMA_PRINT(" Dest Burst Mode=%s\n", NewEntry->DstBurstMode ? "Fix" : "Inc");
6371 +    GDMA_PRINT(" Burst Size=%s\n", NewEntry->BurstSize ==0 ? "1 transfer" : \
6372 +           NewEntry->BurstSize ==1 ? "2 transfer" :\
6373 +           NewEntry->BurstSize ==2 ? "4 transfer" :\
6374 +           NewEntry->BurstSize ==3 ? "8 transfer" :\
6375 +           NewEntry->BurstSize ==4 ? "16 transfer" :\
6376 +           "Error");
6377 +    GDMA_PRINT(" Hardware/Software Mode = %s\n", NewEntry->SoftMode ?
6378 +           "Soft" : "Hw");
6379 +    GDMA_PRINT("== << GDMA Control Reg1 (Channel=%d) >> =\n", NewEntry->ChNum);
6380 +    GDMA_PRINT("Channel Done Interrput=%s\n", (NewEntry->DoneIntCallback!=NULL) ?
6381 +           "Enable" : "Disable");
6382 +    GDMA_PRINT("Channel Unmasked Int=%s\n", (NewEntry->UnMaskIntCallback!=NULL) ?
6383 +           "Enable" : "Disable");
6384 +#if !defined (CONFIG_RALINK_RT3052) && !defined (CONFIG_RALINK_RT3883)
6385 +    GDMA_PRINT("Coherent Interrupt =%s\n", (NewEntry->CoherentIntEbl==1)?
6386 +           "Enable" : "Disable");
6387 +#endif
6388 +    GDMA_PRINT("Next Unmasked Channel=%d\n", NewEntry->NextUnMaskCh);
6389 +    GDMA_PRINT("Channel Mask=%d\n", NewEntry->ChMask);
6390 +    GDMA_PRINT("========================================\n");
6391 +
6392 +    GDMA_WRITE_REG(GDMA_SRC_REG(NewEntry->ChNum), NewEntry->Src);
6393 +    GDMA_PRINT("SrcAddr: Write %0X to %X\n", \
6394 +           NewEntry->Src, GDMA_SRC_REG(NewEntry->ChNum));
6395 +
6396 +    GDMA_WRITE_REG(GDMA_DST_REG(NewEntry->ChNum), NewEntry->Dst);
6397 +    GDMA_PRINT("DstAddr: Write %0X to %X\n", \
6398 +           NewEntry->Dst, GDMA_DST_REG(NewEntry->ChNum));
6399 +
6400 +    Data |= ( (NewEntry->NextUnMaskCh) << NEXT_UNMASK_CH_OFFSET);
6401 +    Data |= ( NewEntry->ChMask << CH_MASK_OFFSET);
6402 +#if !defined (CONFIG_RALINK_RT3052) && !defined (CONFIG_RALINK_RT3883)
6403 +    Data |= ( NewEntry->CoherentIntEbl << COHERENT_INT_EBL_OFFSET);
6404 +#endif
6405 +
6406 +    if(NewEntry->UnMaskIntCallback!=NULL) {
6407 +       Data |= (0x01<<CH_UNMASKINT_EBL_OFFSET);
6408 +       GdmaUnMaskIntCallback[NewEntry->ChNum] = NewEntry->UnMaskIntCallback;
6409 +    }
6410 +
6411 +#if defined (CONFIG_RALINK_RT3883) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A) || defined (CONFIG_RALINK_MT7620)  ||  defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628) || defined (CONFIG_ARCH_MT7623)
6412 +    Data |= (NewEntry->SrcReqNum << SRC_DMA_REQ_OFFSET);
6413 +    Data |= (NewEntry->DstReqNum << DST_DMA_REQ_OFFSET);
6414 +#endif
6415 +
6416 +    GDMA_WRITE_REG(GDMA_CTRL_REG1(NewEntry->ChNum), Data);
6417 +    GDMA_PRINT("CTRL1: Write %08X to %8X\n", Data, GDMA_CTRL_REG1(NewEntry->ChNum));
6418 +
6419 +    Data = ((NewEntry->TransCount) << TRANS_CNT_OFFSET);
6420 +#if defined (CONFIG_RALINK_RT3052)
6421 +    Data |= (NewEntry->SrcReqNum << SRC_DMA_REQ_OFFSET);
6422 +    Data |= (NewEntry->DstReqNum << DST_DMA_REQ_OFFSET);
6423 +#endif
6424 +    Data |= (NewEntry->SrcBurstMode << SRC_BRST_MODE_OFFSET);
6425 +    Data |= (NewEntry->DstBurstMode << DST_BRST_MODE_OFFSET);
6426 +    Data |= (NewEntry->BurstSize << BRST_SIZE_OFFSET);
6427 +
6428 +    if(NewEntry->DoneIntCallback!=NULL) {
6429 +       Data |= (0x01<<CH_DONEINT_EBL_OFFSET);
6430 +       GdmaDoneIntCallback[NewEntry->ChNum] = NewEntry->DoneIntCallback;
6431 +    }
6432 +
6433 +    if(NewEntry->SoftMode) {
6434 +       Data |= (0x01<<MODE_SEL_OFFSET);
6435 +    }
6436 +
6437 +    Data |= (0x01<<CH_EBL_OFFSET);
6438 +    GDMA_WRITE_REG(GDMA_CTRL_REG(NewEntry->ChNum), Data);
6439 +    //GDMA_READ_REG(GDMA_CTRL_REG(NewEntry->ChNum));
6440 +    GDMA_PRINT("CTRL: Write %08X to %8X\n", Data, GDMA_CTRL_REG(NewEntry->ChNum));
6441 +     //if there is no interrupt handler, this function will
6442 +    //return 1 until GDMA done.
6443 +    if(NewEntry->DoneIntCallback==NULL) {
6444 +       //wait for GDMA processing done
6445 +#if defined (CONFIG_RALINK_RT3052)
6446 +       while((GDMA_READ_REG(RALINK_GDMAISTS) &
6447 +                   (0x1<<NewEntry->ChNum))==0);
6448 +       //write 1 clear
6449 +       GDMA_WRITE_REG(RALINK_GDMAISTS, 1<< NewEntry->ChNum);
6450 +#elif defined (CONFIG_RALINK_RT3883) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A) || defined (CONFIG_RALINK_MT7620)  ||  defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628) || defined (CONFIG_ARCH_MT7623)
6451 +       while((GDMA_READ_REG(RALINK_GDMA_DONEINT) &
6452 +                   (0x1<<NewEntry->ChNum))==0);
6453 +       //write 1 clear
6454 +       GDMA_WRITE_REG(RALINK_GDMA_DONEINT, 1<< NewEntry->ChNum);
6455 +#endif
6456 +    }
6457 +
6458 +    return 1;
6459 +
6460 +}
6461 +
6462 +#if defined(CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628) || defined (CONFIG_ARCH_MT7623)
6463 +/**
6464 + * @brief Start GDMA transaction for sending data to SPI
6465 + *
6466 + * @param  *Src        source address
6467 + * @param  *Dst        destination address
6468 +
6469 + * @param  TransCount          data length
6470 + * @param  *DoneIntCallback  callback function when transcation is done
6471 + * @param  *UnMaskIntCallback  callback func when ch mask field is incorrect
6472 + * @retval 1           success
6473 + * @retval 0           fail
6474 + */
6475 +int GdmaSpiTx(
6476 +       uint32_t Src,
6477 +       uint32_t Dst,
6478 +       uint16_t TransCount,
6479 +       void (*DoneIntCallback)(uint32_t data),
6480 +       void (*UnMaskIntCallback)(uint32_t data)
6481 +       )
6482 +{
6483 +    GdmaReqEntry Entry;
6484 +
6485 +       #if defined (CONFIG_MIPS)
6486 +    Entry.Src= (Src & 0x1FFFFFFF);
6487 +    Entry.Dst= (Dst & 0x1FFFFFFF);
6488 +  #else
6489 +    Entry.Src= Src;
6490 +    Entry.Dst= Dst;
6491 +  #endif
6492 +    Entry.TransCount = TransCount;
6493 +    Entry.SrcBurstMode=INC_MODE;
6494 +    Entry.DstBurstMode=FIX_MODE;
6495 +    Entry.BurstSize=BUSTER_SIZE_4B;
6496 +    Entry.SrcReqNum=DMA_MEM_REQ;
6497 +    Entry.DstReqNum=DMA_SPI_TX_REQ;
6498 +    Entry.DoneIntCallback=DoneIntCallback;
6499 +    Entry.UnMaskIntCallback=UnMaskIntCallback;
6500 +    Entry.SoftMode=0;
6501 +    Entry.ChMask=0;
6502 +    Entry.CoherentIntEbl=0;
6503 +
6504 +       //enable chain feature
6505 +       Entry.ChNum = GDMA_SPI_TX;
6506 +       Entry.NextUnMaskCh = GDMA_SPI_TX;
6507 +
6508 +    return _GdmaReqEntryIns(&Entry);
6509 +}
6510 +
6511 +int GdmaSpiRx(
6512 +       uint32_t Src,
6513 +       uint32_t Dst,
6514 +       uint16_t TransCount,
6515 +       void (*DoneIntCallback)(uint32_t data),
6516 +       void (*UnMaskIntCallback)(uint32_t data)
6517 +       )
6518 +{
6519 +    GdmaReqEntry Entry;
6520 +
6521 +       #if defined (CONFIG_MIPS)
6522 +    Entry.Src= (Src & 0x1FFFFFFF);
6523 +    Entry.Dst= (Dst & 0x1FFFFFFF);
6524 +  #else
6525 +    Entry.Src= Src;
6526 +    Entry.Dst= Dst;
6527 +  #endif
6528 +    Entry.TransCount = TransCount;
6529 +    Entry.SrcBurstMode=FIX_MODE;
6530 +    Entry.DstBurstMode=INC_MODE;
6531 +    Entry.BurstSize=BUSTER_SIZE_4B;
6532 +    Entry.SrcReqNum=DMA_SPI_RX_REQ;
6533 +    Entry.DstReqNum=DMA_MEM_REQ;
6534 +    Entry.DoneIntCallback=DoneIntCallback;
6535 +    Entry.UnMaskIntCallback=UnMaskIntCallback;
6536 +    Entry.SoftMode=0;
6537 +    Entry.ChMask=0;
6538 +    Entry.CoherentIntEbl=1;
6539 +
6540 +
6541 +       //enable chain feature
6542 +       Entry.ChNum=GDMA_SPI_RX;
6543 +       Entry.NextUnMaskCh=GDMA_SPI_RX;
6544 +
6545 +
6546 +    return _GdmaReqEntryIns(&Entry);
6547 +
6548 +}
6549 +#endif
6550 +
6551 +
6552 +/**
6553 + * @brief Start GDMA transaction for sending data to I2S
6554 + *
6555 + * @param  *Src        source address
6556 + * @param  *Dst        destination address
6557 + * @param  TxNo        I2S Tx number
6558 + * @param  TransCount          data length
6559 + * @param  *DoneIntCallback  callback function when transcation is done
6560 + * @param  *UnMaskIntCallback  callback func when ch mask field is incorrect
6561 + * @retval 1           success
6562 + * @retval 0           fail
6563 + */
6564 +int GdmaI2sTx(
6565 +       uint32_t Src,
6566 +       uint32_t Dst,
6567 +       uint8_t TxNo,
6568 +       uint16_t TransCount,
6569 +       void (*DoneIntCallback)(uint32_t data),
6570 +       void (*UnMaskIntCallback)(uint32_t data)
6571 +       )
6572 +{
6573 +    GdmaReqEntry Entry;
6574 +
6575 +       #if defined (CONFIG_MIPS)
6576 +    Entry.Src= (Src & 0x1FFFFFFF);
6577 +    Entry.Dst= (Dst & 0x1FFFFFFF);
6578 +  #else
6579 +    Entry.Src= Src;
6580 +    Entry.Dst= Dst;
6581 +  #endif
6582 +    Entry.TransCount = TransCount;
6583 +    Entry.SrcBurstMode=INC_MODE;
6584 +    Entry.DstBurstMode=FIX_MODE;
6585 +    Entry.BurstSize=BUSTER_SIZE_4B;
6586 +    Entry.SrcReqNum=DMA_MEM_REQ;
6587 +    Entry.DstReqNum=DMA_I2S_TX_REQ;
6588 +    Entry.DoneIntCallback=DoneIntCallback;
6589 +    Entry.UnMaskIntCallback=UnMaskIntCallback;
6590 +    Entry.SoftMode=0;
6591 +    Entry.ChMask=1;
6592 +    Entry.CoherentIntEbl=0;
6593 +
6594 +    if(TxNo==0) { //TX0
6595 +       //enable chain feature
6596 +       Entry.ChNum=GDMA_I2S_TX0;
6597 +       Entry.NextUnMaskCh= (TransCount==4) ?  GDMA_I2S_TX0 : GDMA_I2S_TX1;
6598 +    }else if(TxNo==1) { //TX1
6599 +       //enable chain feature
6600 +       Entry.ChNum=GDMA_I2S_TX1;
6601 +       Entry.NextUnMaskCh= (TransCount==4) ? GDMA_I2S_TX1 : GDMA_I2S_TX0;
6602 +    }else {
6603 +       GDMA_PRINT("I2S Tx Number %x is invalid\n", TxNo);
6604 +       return 0;
6605 +    }
6606 +
6607 +    return _GdmaReqEntryIns(&Entry);
6608 +
6609 +}
6610 +
6611 +
6612 +#if defined (CONFIG_RALINK_RT3883) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A) || defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628) || defined (CONFIG_ARCH_MT7623)
6613 +/**
6614 + * @brief Start GDMA transaction for receiving data to I2S
6615 + *
6616 + * @param  *Src        source address
6617 + * @param  *Dst        destination address
6618 + * @param  TxNo        I2S Tx number
6619 + * @param  TransCount          data length
6620 + * @param  *DoneIntCallback  callback function when transcation is done
6621 + * @param  *UnMaskIntCallback  callback func when ch mask field is incorrect
6622 + * @retval 1           success
6623 + * @retval 0           fail
6624 + */
6625 +int GdmaI2sRx(
6626 +       uint32_t Src,
6627 +       uint32_t Dst,
6628 +       uint8_t RxNo,
6629 +       uint16_t TransCount,
6630 +       void (*DoneIntCallback)(uint32_t data),
6631 +       void (*UnMaskIntCallback)(uint32_t data)
6632 +       )
6633 +{
6634 +    GdmaReqEntry Entry;
6635 +       #if defined (CONFIG_MIPS)
6636 +    Entry.Src= (Src & 0x1FFFFFFF);
6637 +    Entry.Dst= (Dst & 0x1FFFFFFF);
6638 +  #else
6639 +    Entry.Src= Src;
6640 +    Entry.Dst= Dst;
6641 +  #endif
6642 +    Entry.TransCount = TransCount;
6643 +    Entry.SrcBurstMode=FIX_MODE;
6644 +    Entry.DstBurstMode=INC_MODE;
6645 +    Entry.BurstSize=BUSTER_SIZE_4B;
6646 +    Entry.SrcReqNum=DMA_I2S_RX_REQ;
6647 +    Entry.DstReqNum=DMA_MEM_REQ;
6648 +    Entry.DoneIntCallback=DoneIntCallback;
6649 +    Entry.UnMaskIntCallback=UnMaskIntCallback;
6650 +    Entry.SoftMode=0;
6651 +    Entry.ChMask=1;
6652 +    Entry.CoherentIntEbl=1;
6653 +
6654 +    if(RxNo==0) { //RX0
6655 +       //enable chain feature
6656 +       Entry.ChNum=GDMA_I2S_RX0;
6657 +       Entry.NextUnMaskCh=(TransCount==4) ? GDMA_I2S_RX0 : GDMA_I2S_RX1;
6658 +    }else if(RxNo==1) { //RX1
6659 +       //enable chain feature
6660 +       Entry.ChNum=GDMA_I2S_RX1;
6661 +       Entry.NextUnMaskCh=(TransCount==4) ? GDMA_I2S_RX1 : GDMA_I2S_RX0;
6662 +    }else {
6663 +       GDMA_PRINT("I2S Rx Number %x is invalid\n", RxNo);
6664 +       return 0;
6665 +    }
6666 +
6667 +    return _GdmaReqEntryIns(&Entry);
6668 +
6669 +}
6670 +
6671 +#endif
6672 +
6673 +/**
6674 + * @brief Start GDMA transaction for receiving data from PCM
6675 + *
6676 + * @param  *Src        source address
6677 + * @param  *Dst        destination address
6678 + * @param  TransCount   data length
6679 + * @param  PcmNo       PCM channel
6680 + * @param  RxNo        PCM Rx number
6681 + * @param  *DoneIntCallback  callback function when transcation is done
6682 + * @param  *UnMaskIntCallback  callback func when ch mask field is incorrect
6683 + * @retval 1           success
6684 + * @retval 0           fail
6685 + */
6686 +int GdmaPcmRx(
6687 +       uint32_t Src,
6688 +       uint32_t Dst,
6689 +       uint8_t PcmNo,
6690 +       uint8_t RxNo,
6691 +       uint16_t TransCount,
6692 +       void (*DoneIntCallback)(uint32_t data),
6693 +       void (*UnMaskIntCallback)(uint32_t data)
6694 +       )
6695 +{
6696 +    GdmaReqEntry Entry;
6697 +
6698 +       #if defined (CONFIG_MIPS)
6699 +    Entry.Src= (Src & 0x1FFFFFFF);
6700 +    Entry.Dst= (Dst & 0x1FFFFFFF);
6701 +  #else
6702 +    Entry.Src= Src;
6703 +    Entry.Dst= Dst;
6704 +  #endif
6705 +    Entry.TransCount = TransCount;
6706 +    Entry.SrcBurstMode=FIX_MODE;
6707 +    Entry.DstBurstMode=INC_MODE;
6708 +    Entry.BurstSize=BUSTER_SIZE_4B;
6709 +    Entry.DstReqNum=DMA_MEM_REQ;
6710 +    Entry.DoneIntCallback=DoneIntCallback;
6711 +    Entry.UnMaskIntCallback=UnMaskIntCallback;
6712 +    Entry.SoftMode=0;
6713 +    Entry.ChMask=1;
6714 +    Entry.CoherentIntEbl=1;
6715 +
6716 +       if(RxNo > 2) {
6717 +               GDMA_PRINT("PCM Rx Number %x is invalid\n", RxNo);
6718 +               return 0;
6719 +       }
6720 +
6721 +       switch(PcmNo)
6722 +       {
6723 +       case 0:
6724 +               Entry.SrcReqNum=DMA_PCM_RX0_REQ;
6725 +               break;
6726 +       case 1:
6727 +               Entry.SrcReqNum=DMA_PCM_RX1_REQ;
6728 +               break;
6729 +#if defined(CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628) || defined (CONFIG_ARCH_MT7623)
6730 +       case 2:
6731 +               Entry.SrcReqNum=DMA_PCM_RX2_REQ;
6732 +               break;
6733 +       case 3:
6734 +               Entry.SrcReqNum=DMA_PCM_RX3_REQ;
6735 +               break;
6736 +#endif
6737 +       default:
6738 +               GDMA_PRINT("PCM Channel %x is invalid\n", PcmNo);
6739 +               return 0;
6740 +       }
6741 +       Entry.ChNum=GDMA_PCM_RX(PcmNo,RxNo);
6742 +       Entry.NextUnMaskCh=GDMA_PCM_RX(PcmNo,1-RxNo);
6743 +
6744 +    return _GdmaReqEntryIns(&Entry);
6745 +
6746 +}
6747 +
6748 +/**
6749 + * @brief Start GDMA transaction for sending data to PCM
6750 + *
6751 + * @param  *Src                    source address
6752 + * @param  *Dst                    destination address
6753 + * @param  TransCount      data length
6754 + * @param  PcmNo           PCM channel
6755 + * @param  TxNo                    PCM Tx number
6756 + * @param  *DoneIntCallback  callback func when transcation is done
6757 + * @param  *UnMaskIntCallback  callback func when ch mask field is incorrect
6758 + * @retval 1               success
6759 + * @retval 0               fail
6760 + */
6761 +int GdmaPcmTx(
6762 +       uint32_t Src,
6763 +       uint32_t Dst,
6764 +       uint8_t PcmNo,
6765 +       uint8_t TxNo,
6766 +       uint16_t TransCount,
6767 +       void (*DoneIntCallback)(uint32_t data),
6768 +       void (*UnMaskIntCallback)(uint32_t data)
6769 +       )
6770 +{
6771 +    GdmaReqEntry Entry;
6772 +
6773 +       #if defined (CONFIG_MIPS)
6774 +    Entry.Src= (Src & 0x1FFFFFFF);
6775 +    Entry.Dst= (Dst & 0x1FFFFFFF);
6776 +  #else
6777 +    Entry.Src= Src;
6778 +    Entry.Dst= Dst;
6779 +  #endif
6780 +    Entry.TransCount = TransCount;
6781 +    Entry.SrcBurstMode=INC_MODE;
6782 +    Entry.DstBurstMode=FIX_MODE;
6783 +    Entry.BurstSize=BUSTER_SIZE_4B;
6784 +    Entry.SrcReqNum=DMA_MEM_REQ;
6785 +    Entry.DoneIntCallback=DoneIntCallback;
6786 +    Entry.UnMaskIntCallback=UnMaskIntCallback;
6787 +    Entry.SoftMode=0; //Hardware Mode
6788 +    Entry.ChMask=1;
6789 +    Entry.CoherentIntEbl=0;
6790 +
6791 +       if(TxNo > 2) {
6792 +        GDMA_PRINT("PCM Tx Number %x is invalid\n", TxNo);
6793 +               return 0;
6794 +       }
6795 +       switch(PcmNo)
6796 +       {
6797 +       case 0:
6798 +               Entry.DstReqNum=DMA_PCM_TX0_REQ;
6799 +               break;
6800 +       case 1:
6801 +               Entry.DstReqNum=DMA_PCM_TX1_REQ;
6802 +               break;
6803 +#if defined(CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628) || defined (CONFIG_ARCH_MT7623)
6804 +       case 2:
6805 +               Entry.DstReqNum=DMA_PCM_TX2_REQ;
6806 +               break;
6807 +       case 3:
6808 +               Entry.DstReqNum=DMA_PCM_TX3_REQ;
6809 +               break;
6810 +#endif
6811 +       default:
6812 +               GDMA_PRINT("PCM Channel %x is invalid\n", PcmNo);
6813 +               return 0;
6814 +       }
6815 +       Entry.ChNum=GDMA_PCM_TX(PcmNo,TxNo);
6816 +       Entry.NextUnMaskCh=GDMA_PCM_TX(PcmNo,1-TxNo);
6817 +
6818 +    return _GdmaReqEntryIns(&Entry);
6819 +
6820 +}
6821 +
6822 +
6823 +/**
6824 + * @brief Start GDMA transaction for memory to memory copy
6825 + *
6826 + * @param  *Src                    source address
6827 + * @param  *Dst                    destination address
6828 + * @param  TransCount      data length
6829 + * @param  *DoneIntCallback  callback function when transcation is done
6830 + * @retval 1               success
6831 + * @retval 0               fail
6832 + */
6833 +int GdmaMem2Mem(
6834 +       uint32_t Src,
6835 +       uint32_t Dst,
6836 +       uint16_t TransCount,
6837 +       void (*DoneIntCallback)(uint32_t data)
6838 +       )
6839 +
6840 +{
6841 +
6842 +    GdmaReqEntry Entry;
6843 +       #if defined (CONFIG_MIPS)
6844 +    Entry.Src= (Src & 0x1FFFFFFF);
6845 +    Entry.Dst= (Dst & 0x1FFFFFFF);
6846 +  #else
6847 +    Entry.Src= Src;
6848 +    Entry.Dst= Dst;
6849 +  #endif
6850 +
6851 +    //Entry.Src= virt_to_phys(Src);
6852 +    //Entry.Dst= virt_to_phys(Dst);
6853 +
6854 +
6855 +
6856 +    Entry.TransCount = TransCount;
6857 +    Entry.SrcBurstMode=INC_MODE;
6858 +    Entry.DstBurstMode=INC_MODE;
6859 +    Entry.BurstSize=BUSTER_SIZE_64B;
6860 +    Entry.SrcReqNum=DMA_MEM_REQ;
6861 +    Entry.DstReqNum=DMA_MEM_REQ;
6862 +    Entry.DoneIntCallback=DoneIntCallback;
6863 +    Entry.UnMaskIntCallback=NULL;
6864 +    Entry.SoftMode=1;
6865 +    Entry.ChMask=0;
6866 +
6867 +    Entry.CoherentIntEbl=1;
6868 +
6869 +    //No reserved channel for Memory to Memory GDMA,
6870 +    //get free channel on demand
6871 +    if(!_GdmaGetFreeCh(&Entry.ChNum)) {
6872 +                       GDMA_PRINT("GDMA Channels are all busy\n");
6873 +                       return 0;
6874 +    }
6875 +
6876 +
6877 +    //set next channel to their own channel
6878 +    //to disable chain feature
6879 +    Entry.NextUnMaskCh= Entry.ChNum;
6880 +      //printk ("ChNum = %d\n", Entry.ChNum);
6881 +    //set next channel to another channel
6882 +    //to enable chain feature
6883 +    //Entry.NextUnMaskCh= (Entry.ChNum+1) % MAX_GDMA_CHANNEL;
6884 +
6885 +    return _GdmaReqEntryIns(&Entry);
6886 +
6887 +
6888 +}
6889 +
6890 +/**
6891 + * @brief GDMA interrupt handler
6892 + *
6893 + * When GDMA transcation is done, call related handler
6894 + * to do the remain job.
6895 + *
6896 + */
6897 +irqreturn_t GdmaIrqHandler(
6898 +       int irq,
6899 +       void *irqaction
6900 +       )
6901 +{
6902 +
6903 +    u32 Ch=0;
6904 +    unsigned long flags;
6905 +#if defined (CONFIG_RALINK_RT3052)
6906 +    u32 GdmaUnMaskStatus=GDMA_READ_REG(RALINK_GDMAISTS) & 0xFF0000;
6907 +    u32 GdmaDoneStatus=GDMA_READ_REG(RALINK_GDMAISTS) & 0xFF;
6908 +#elif defined (CONFIG_RALINK_RT3883) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A) || defined (CONFIG_RALINK_MT7620)  ||  defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628) || defined (CONFIG_ARCH_MT7623)
6909 +    u32 GdmaUnMaskStatus=GDMA_READ_REG(RALINK_GDMA_UNMASKINT);
6910 +    u32 GdmaDoneStatus=GDMA_READ_REG(RALINK_GDMA_DONEINT);
6911 +#endif
6912 +    //printk("********GDMA Interrupt*******************\n");
6913 +
6914 +    //GDMA_PRINT("========================================\n");
6915 +    //GDMA_PRINT("GdmaUnMask Interrupt=%x\n",GdmaUnMaskStatus);
6916 +    //GDMA_PRINT("GdmaDone Interrupt=%x\n",GdmaDoneStatus);
6917 +    //GDMA_PRINT("========================================\n");
6918 +
6919 +    spin_lock_irqsave(&gdma_int_lock, flags);
6920 +
6921 +    //write 1 clear
6922 +#if defined (CONFIG_RALINK_RT3052)
6923 +    GDMA_WRITE_REG(RALINK_GDMAISTS, GdmaUnMaskStatus);
6924 +#elif defined (CONFIG_RALINK_RT3883) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A) || defined (CONFIG_RALINK_MT7620)  ||  defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628) || defined (CONFIG_ARCH_MT7623)
6925 +    GDMA_WRITE_REG(RALINK_GDMA_UNMASKINT, GdmaUnMaskStatus);
6926 +#endif
6927 +
6928 +    //UnMask error
6929 +    for(Ch=0;Ch<MAX_GDMA_CHANNEL;Ch++) {
6930 +
6931 +       if(GdmaUnMaskStatus & (0x1 << (UNMASK_INT_STATUS(Ch))) ) {
6932 +           if(GdmaUnMaskIntCallback[Ch] != NULL) {
6933 +               GdmaUnMaskIntCallback[Ch](Ch);
6934 +             // printk("GdmaUnMaskIntCallback \n");
6935 +           }
6936 +       }
6937 +     }
6938 +
6939 +    //write 1 clear
6940 +#if defined (CONFIG_RALINK_RT3052)
6941 +     GDMA_WRITE_REG(RALINK_GDMAISTS, GdmaDoneStatus);
6942 +#elif defined (CONFIG_RALINK_RT3883) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A) || defined (CONFIG_RALINK_MT7620)  ||  defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628) || defined (CONFIG_ARCH_MT7623)
6943 +     GDMA_WRITE_REG(RALINK_GDMA_DONEINT, GdmaDoneStatus);
6944 +#endif
6945 +
6946 +     //printk("interrupt status = %x \n", GdmaDoneStatus);
6947 +     //processing done
6948 +     for(Ch=0;Ch<MAX_GDMA_CHANNEL;Ch++) {
6949 +                       if(GdmaDoneStatus & (0x1<<Ch)) {
6950 +               if(GdmaDoneIntCallback[Ch] != NULL) {
6951 +                       //printk("*************Interrupt Ch=%d***********\n", Ch);
6952 +                                       GdmaDoneIntCallback[Ch](Ch);
6953 +               }
6954 +                       }
6955 +    }
6956 +
6957 +//printk("interrupt status clear = %x \n", GDMA_READ_REG(RALINK_GDMA_DONEINT));
6958 +    spin_unlock_irqrestore(&gdma_int_lock, flags);
6959 +
6960 +    return IRQ_HANDLED;
6961 +
6962 +}
6963 +
6964 +static int RalinkGdmaInit(void)
6965 +{
6966 +
6967 +    uint32_t Ret=0;
6968 +    uint32_t val = 0;
6969 +    printk("Enable Ralink GDMA Controller Module \n");
6970 +#if defined (CONFIG_RALINK_RT3883) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A) || defined (CONFIG_RALINK_MT7620)  ||  defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628) || defined (CONFIG_ARCH_MT7623)
6971 +    printk("GDMA IP Version=%d\n", GET_GDMA_IP_VER);
6972 +#endif
6973 +spin_lock_init(&gdma_int_lock);
6974 +spin_lock_init(&gdma_lock);
6975 +//spin_lock_init(&gdma_lock_mem);
6976 +
6977 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
6978 +       #if defined (CONFIG_MIPS)
6979 +           Ret = request_irq(SURFBOARDINT_DMA, GdmaIrqHandler, \
6980 +                   IRQF_DISABLED, "Ralink_DMA", NULL);
6981 +       #else
6982 +           Ret = request_irq(SURFBOARDINT_DMA, GdmaIrqHandler, \
6983 +                   IRQF_TRIGGER_LOW, "Ralink_DMA", NULL);
6984 +       #endif
6985 +#else
6986 +    Ret = request_irq(SURFBOARDINT_DMA, GdmaIrqHandler, \
6987 +           SA_INTERRUPT, "Ralink_DMA", NULL);
6988 +#endif
6989 +
6990 +/*
6991 +    Ret = request_irq(131, GdmaIrqHandler, \
6992 +           IRQF_TRIGGER_LOW, "Ralink_DMA", NULL);
6993 +           */
6994 +    if(Ret){
6995 +       GDMA_PRINT("IRQ %d is not free.\n", SURFBOARDINT_DMA);
6996 +       return 1;
6997 +    }
6998 +
6999 +#if defined (CONFIG_MIPS)
7000 +    //Enable GDMA interrupt
7001 +    val = le32_to_cpu(*(volatile u32 *)(RALINK_REG_INTENA));
7002 +    val |= RALINK_INTCTL_DMA;
7003 +    GDMA_WRITE_REG(RALINK_REG_INTENA, val);
7004 +#endif
7005 +
7006 +    //Channel0~Channel7 are round-robin
7007 +#if defined (CONFIG_RALINK_RT3052)
7008 +    GDMA_WRITE_REG(RALINK_GDMAGCT, 0x01);
7009 +#elif defined (CONFIG_RALINK_RT3883) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A) || defined (CONFIG_RALINK_MT7620)  ||  defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628) || defined (CONFIG_ARCH_MT7623)
7010 +    GDMA_WRITE_REG(RALINK_GDMA_GCT, 0x01);
7011 +#else
7012 +#error Please Choose System Type
7013 +#endif
7014 +
7015 +    return 0;
7016 +}
7017 +
7018 +static void __exit RalinkGdmaExit(void)
7019 +{
7020 +
7021 +    printk("Disable Ralink GDMA Controller Module\n");
7022 +#if defined (CONFIG_MIPS)
7023 +    //Disable GDMA interrupt
7024 +    GDMA_WRITE_REG(RALINK_REG_INTDIS, RALINK_INTCTL_DMA);
7025 +#endif
7026 +    free_irq(SURFBOARDINT_DMA, NULL);
7027 +}
7028 +
7029 +module_init(RalinkGdmaInit);
7030 +module_exit(RalinkGdmaExit);
7031 +
7032 +EXPORT_SYMBOL(GdmaI2sRx);
7033 +EXPORT_SYMBOL(GdmaI2sTx);
7034 +EXPORT_SYMBOL(GdmaPcmRx);
7035 +EXPORT_SYMBOL(GdmaPcmTx);
7036 +#if defined(CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628) || defined (CONFIG_ARCH_MT7623)
7037 +EXPORT_SYMBOL(GdmaSpiRx);
7038 +EXPORT_SYMBOL(GdmaSpiTx);
7039 +#endif
7040 +EXPORT_SYMBOL(GdmaMem2Mem);
7041 +EXPORT_SYMBOL(GdmaReqQuickIns);
7042 +EXPORT_SYMBOL(GdmaMaskChannel);
7043 +EXPORT_SYMBOL(GdmaUnMaskChannel);
7044 +
7045 +
7046 +MODULE_DESCRIPTION("Ralink SoC GDMA Controller API Module");
7047 +MODULE_AUTHOR("Steven Liu <steven_liu@ralinktech.com.tw>");
7048 +MODULE_LICENSE("GPL");
7049 +MODULE_VERSION(MOD_VERSION);
7050 --- /dev/null
7051 +++ b/sound/soc/mtk/ralink_gdma.h
7052 @@ -0,0 +1,326 @@
7053 +/*
7054 + ***************************************************************************
7055 + * Ralink Tech Inc.
7056 + * 5F., No.36, Taiyuan St., Jhubei City,
7057 + * Hsinchu County 302,
7058 + * Taiwan, R.O.C.
7059 + *
7060 + * (c) Copyright, Ralink Technology, Inc.
7061 + *
7062 + *  This program is free software; you can redistribute  it and/or modify it
7063 + *  under  the terms of  the GNU General  Public License as published by the
7064 + *  Free Software Foundation;  either version 2 of the  License, or (at your
7065 + *  option) any later version.
7066 + *
7067 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
7068 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
7069 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
7070 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
7071 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7072 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
7073 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7074 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
7075 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7076 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7077 + *
7078 + *  You should have received a copy of the  GNU General Public License along
7079 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
7080 + *  675 Mass Ave, Cambridge, MA 02139, USA.
7081 + *
7082 + *
7083 + ***************************************************************************
7084 + */
7085 +
7086 +#ifndef __RALINK_DMA_CTRL_H__
7087 +#define __RALINK_DMA_CTRL_H__
7088 +
7089 +//#include <asm/rt2880/rt_mmap.h>
7090 +
7091 +/*
7092 + * DEFINITIONS AND MACROS
7093 + */
7094 +#define MOD_VERSION                    "0.4"
7095 +
7096 +#if defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623)
7097 +#define MAX_GDMA_CHANNEL               16
7098 +#elif defined (CONFIG_RALINK_RT3052)
7099 +#define MAX_GDMA_CHANNEL               8
7100 +#elif defined (CONFIG_RALINK_RT3883) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A) || defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7628)
7101 +#define MAX_GDMA_CHANNEL               16
7102 +#else
7103 +#error Please Choose System Type
7104 +#endif
7105 +
7106 +
7107 +#define RALINK_GDMA_CTRL_BASE          (RALINK_GDMA_BASE)
7108 +#if defined (CONFIG_RALINK_RT3052)
7109 +#define RALINK_GDMAISTS                        (RALINK_GDMA_BASE + 0x80)
7110 +#define RALINK_GDMAGCT                 (RALINK_GDMA_BASE + 0x88)
7111 +#elif defined (CONFIG_RALINK_RT3883) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A) || defined (CONFIG_RALINK_MT7620)  ||  defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628) || defined (CONFIG_ARCH_MT7623)
7112 +#define RALINK_GDMA_UNMASKINT          (RALINK_GDMA_BASE + 0x200)
7113 +#define RALINK_GDMA_DONEINT            (RALINK_GDMA_BASE + 0x204)
7114 +#define RALINK_GDMA_GCT                        (RALINK_GDMA_BASE + 0x220)
7115 +#endif
7116 +
7117 +#define KSEG1                   0xa0000000
7118 +#define PHYS_TO_VIRT(x)         ((void *)((x) | KSEG1))
7119 +#define VIRT_TO_PHYS(x)         ((unsigned long)(x) & ~KSEG1)
7120 +
7121 +
7122 +
7123 +
7124 +#if defined (CONFIG_ARCH_MT7623)
7125 +#include <mach/sync_write.h>
7126 +#define GDMA_READ_REG(phys)            (*(volatile unsigned int *)((phys)))
7127 +#define GDMA_WRITE_REG(phys, val)      mt65xx_reg_sync_writel((val), (phys))
7128 +
7129 +#else
7130 +#define GDMA_READ_REG(addr)            (le32_to_cpu(*(volatile u32 *)(addr)))
7131 +#define GDMA_WRITE_REG(addr, val)      *((volatile uint32_t *)(addr)) = cpu_to_le32(val)
7132 +
7133 +
7134 +
7135 +#endif
7136 +
7137 +
7138 +#define GET_GDMA_IP_VER                        (GDMA_READ_REG(RALINK_GDMA_GCT) & 0x6) >> 1 //GDMA_GCT[2:1]
7139 +
7140 +#define RALINK_IRQ_ADDR                 RALINK_INTCL_BASE
7141 +#if defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7628)
7142 +#define RALINK_REG_INTENA               (RALINK_IRQ_ADDR + 0x80)
7143 +#define RALINK_REG_INTDIS               (RALINK_IRQ_ADDR + 0x78)
7144 +#else
7145 +#define RALINK_REG_INTENA               (RALINK_IRQ_ADDR + 0x34)
7146 +#define RALINK_REG_INTDIS               (RALINK_IRQ_ADDR + 0x38)
7147 +#endif
7148 +
7149 +/*
7150 + * 12bytes=GDMA Channel n Source Address(4) +
7151 + *         GDMA Channel n Destination Address(4) +
7152 + *         GDMA Channel n Control Register(4)
7153 + *
7154 + */
7155 +#define GDMA_SRC_REG(ch)               (RALINK_GDMA_BASE + ch*16)
7156 +#define GDMA_DST_REG(ch)               (GDMA_SRC_REG(ch) + 4)
7157 +#define GDMA_CTRL_REG(ch)              (GDMA_DST_REG(ch) + 4)
7158 +#define GDMA_CTRL_REG1(ch)             (GDMA_CTRL_REG(ch) + 4)
7159 +
7160 +//GDMA Interrupt Status Register
7161 +#if defined (CONFIG_RALINK_RT3052)
7162 +#define UNMASK_INT_STATUS(ch)           (ch+16)
7163 +#elif defined (CONFIG_RALINK_RT3883) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A) || defined (CONFIG_RALINK_MT7620)  ||  defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628) || defined (CONFIG_ARCH_MT7623)
7164 +#define UNMASK_INT_STATUS(ch)           (ch)
7165 +#endif
7166 +#define TXDONE_INT_STATUS(ch)           (ch)
7167 +
7168 +//Control Reg0
7169 +#define MODE_SEL_OFFSET                        0
7170 +#define CH_EBL_OFFSET                  1
7171 +#define CH_DONEINT_EBL_OFFSET          2
7172 +#define BRST_SIZE_OFFSET               3
7173 +#define DST_BRST_MODE_OFFSET           6
7174 +#define SRC_BRST_MODE_OFFSET           7
7175 +#define TRANS_CNT_OFFSET               16
7176 +
7177 +//Control Reg1
7178 +#if defined (CONFIG_RALINK_RT3052)
7179 +#define CH_UNMASKINT_EBL_OFFSET                4
7180 +#define NEXT_UNMASK_CH_OFFSET          1
7181 +#elif defined (CONFIG_RALINK_RT3883) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A) || defined (CONFIG_RALINK_MT7620)  ||  defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628) || defined (CONFIG_ARCH_MT7623)
7182 +#define CH_UNMASKINT_EBL_OFFSET                1
7183 +#define NEXT_UNMASK_CH_OFFSET          3
7184 +#endif
7185 +#define COHERENT_INT_EBL_OFFSET                2
7186 +#define CH_MASK_OFFSET                 0
7187 +
7188 +
7189 +#if defined (CONFIG_RALINK_RT3052)
7190 +//Control Reg0
7191 +#define DST_DMA_REQ_OFFSET             8
7192 +#define SRC_DMA_REQ_OFFSET             12
7193 +#elif defined (CONFIG_RALINK_RT3883) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A) || defined (CONFIG_RALINK_MT7620)  ||  defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628) || defined (CONFIG_ARCH_MT7623)
7194 +//Control Reg1
7195 +#define DST_DMA_REQ_OFFSET             8
7196 +#define SRC_DMA_REQ_OFFSET             16
7197 +#endif
7198 +
7199 +#define GDMA_PCM0_RX0                  0
7200 +#define GDMA_PCM0_RX1                  1
7201 +#define GDMA_PCM0_TX0                  2
7202 +#define GDMA_PCM0_TX1                  3
7203 +
7204 +#define GDMA_PCM1_RX0                  4
7205 +#define GDMA_PCM1_RX1                  5
7206 +#define GDMA_PCM1_TX0                  6
7207 +#define GDMA_PCM1_TX1                  7
7208 +
7209 +#define GDMA_PCM_RX(i,j)               (0+((i)<<2)+j)
7210 +#define GDMA_PCM_TX(i,j)        (2+((i)<<2)+j)
7211 +
7212 +#define GDMA_I2S_TX0                   4
7213 +#define GDMA_I2S_TX1                   5
7214 +#define GDMA_I2S_RX0                   6
7215 +#define GDMA_I2S_RX1                   7
7216 +
7217 +#define GDMA_SPI_TX       13
7218 +#define GDMA_SPI_RX       12
7219 +
7220 +
7221 +//#define GDMA_DEBUG
7222 +#ifdef GDMA_DEBUG
7223 +#define GDMA_PRINT(fmt, args...) printk(KERN_INFO "GDMA: " fmt, ## args)
7224 +#else
7225 +#define GDMA_PRINT(fmt, args...) { }
7226 +#endif
7227 +
7228 +/*
7229 + * TYPEDEFS AND STRUCTURES
7230 + */
7231 +
7232 +enum GdmaBusterMode {
7233 +       INC_MODE=0,
7234 +       FIX_MODE=1
7235 +};
7236 +
7237 +enum GdmaBusterSize {
7238 +       BUSTER_SIZE_4B=0,       /* 1 transfer */
7239 +       BUSTER_SIZE_8B=1,       /* 2 transfer */
7240 +       BUSTER_SIZE_16B=2,      /* 4 transfer */
7241 +       BUSTER_SIZE_32B=3,      /* 8 transfer */
7242 +       BUSTER_SIZE_64B=4       /* 16 transfer */
7243 +};
7244 +
7245 +enum GdmaDmaReqNum {
7246 +#if defined (CONFIG_RALINK_RT3052)
7247 +       DMA_REQ0=0,
7248 +       DMA_NAND_REQ=1,
7249 +       DMA_I2S_TX_REQ=2,
7250 +       DMA_PCM_RX0_REQ=3,
7251 +       DMA_PCM_RX1_REQ=4,
7252 +       DMA_PCM_TX0_REQ=5,
7253 +       DMA_PCM_TX1_REQ=6,
7254 +       DMA_REG7=7,
7255 +       DMA_MEM_REQ=8
7256 +#elif defined (CONFIG_RALINK_RT3883) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855)
7257 +       DMA_REQ0=0,
7258 +       DMA_NAND_REQ=1,
7259 +       DMA_I2S_TX_REQ=2,
7260 +       DMA_I2S_RX_REQ=3,
7261 +       DMA_PCM_RX0_REQ=4,
7262 +       DMA_PCM_RX1_REQ=5,
7263 +       DMA_PCM_TX0_REQ=6,
7264 +       DMA_PCM_TX1_REQ=7,
7265 +       DMA_CODEC0_REQ8=8,
7266 +       DMA_CODEC1_REQ9=9,
7267 +       DMA_REQ10=10,
7268 +       DMA_REQ11=11,
7269 +       DMA_REQ12=12,
7270 +       DMA_REQ13=13,
7271 +       DMA_REQ14=14,
7272 +       DMA_REQ15=15,
7273 +
7274 +       #if defined (CONFIG_RALINK_RT3883)
7275 +               DMA_MEM_REQ=16
7276 +       #elif defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855)
7277 +               DMA_MEM_REQ=32
7278 +       #endif
7279 +
7280 +#elif defined(CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628) || defined (CONFIG_ARCH_MT7623)
7281 +       DMA_REQ0=0,
7282 +       DMA_NAND_REQ=1,
7283 +       DMA_I2S_TX_REQ=2,
7284 +       DMA_I2S_RX_REQ=3,
7285 +       DMA_PCM_RX0_REQ=4,
7286 +       DMA_PCM_RX1_REQ=5,
7287 +       DMA_PCM_TX0_REQ=6,
7288 +       DMA_PCM_TX1_REQ=7,
7289 +       DMA_PCM_RX2_REQ=8,
7290 +       DMA_PCM_RX3_REQ=9,
7291 +       DMA_PCM_TX2_REQ=10,
7292 +       DMA_PCM_TX3_REQ=11,
7293 +       DMA_SPI_RX_REQ=12,
7294 +       DMA_SPI_TX_REQ=13,
7295 +       DMA_MEM_REQ=32
7296 +
7297 +#elif defined (CONFIG_RALINK_RT6855A)
7298 +       DMA_NAND_REQ=0,
7299 +       DMA_I2S_TX_REQ=1,
7300 +       DMA_I2S_RX_REQ=2,
7301 +       DMA_REQ0=3,
7302 +       DMA_PCM_RX0_REQ=4,
7303 +       DMA_PCM_RX1_REQ=5,
7304 +       DMA_PCM_TX0_REQ=6,
7305 +       DMA_PCM_TX1_REQ=7,
7306 +       DMA_CODEC0_REQ8=8,
7307 +       DMA_CODEC1_REQ9=9,
7308 +       DMA_REQ10=10,
7309 +       DMA_REQ11=11,
7310 +       DMA_REQ12=12,
7311 +       DMA_REQ13=13,
7312 +       DMA_REQ14=14,
7313 +       DMA_REQ15=15,
7314 +       DMA_MEM_REQ=32
7315 +#else
7316 +#error Please Choose System Type
7317 +#endif
7318 +};
7319 +
7320 +
7321 +
7322 +typedef struct {
7323 +       uint32_t Src;
7324 +       uint32_t Dst;
7325 +       uint16_t TransCount;
7326 +       uint8_t  SoftMode;
7327 +       uint8_t  NextUnMaskCh;
7328 +       uint8_t  ChMask;
7329 +       uint8_t  CoherentIntEbl;
7330 +       uint32_t  ChNum;
7331 +       enum GdmaDmaReqNum SrcReqNum;
7332 +       enum GdmaDmaReqNum DstReqNum;
7333 +       enum GdmaBusterMode SrcBurstMode;
7334 +       enum GdmaBusterMode DstBurstMode;
7335 +       enum GdmaBusterSize BurstSize;
7336 +       void (*DoneIntCallback)(uint32_t);
7337 +       void (*UnMaskIntCallback)(uint32_t);
7338 +} GdmaReqEntry;
7339 +
7340 +/*
7341 + * EXPORT FUNCTION
7342 + */
7343 +int GdmaI2sTx(uint32_t Src, uint32_t Dst, uint8_t TxNo, uint16_t TransCount,
7344 +               void (*DoneIntCallback)(uint32_t data),
7345 +               void (*UnMaskIntCallback)(uint32_t data));
7346 +
7347 +int GdmaI2sRx(uint32_t Src, uint32_t Dst, uint8_t RxNo, uint16_t TransCount,
7348 +               void (*DoneIntCallback)(uint32_t data),
7349 +               void (*UnMaskIntCallback)(uint32_t data));
7350 +
7351 +int GdmaPcmRx(uint32_t Src, uint32_t Dst, uint8_t PcmNo, uint8_t RxNo, uint16_t TransCount,
7352 +               void (*DoneIntCallback)(uint32_t data),
7353 +               void (*UnMaskIntCallback)(uint32_t data));
7354 +
7355 +int GdmaPcmTx(uint32_t Src, uint32_t Dst, uint8_t PcmNo, uint8_t TxNo, uint16_t TransCount,
7356 +               void (*DoneIntCallback)(uint32_t data),
7357 +               void (*UnMaskIntCallback)(uint32_t data));
7358 +
7359 +int GdmaSpiTx(uint32_t Src, uint32_t Dst, uint16_t TransCount,
7360 +       void (*DoneIntCallback)(uint32_t data),
7361 +       void (*UnMaskIntCallback)(uint32_t data));
7362 +
7363 +int GdmaSpiRx(uint32_t Src, uint32_t Dst, uint16_t TransCount,
7364 +       void (*DoneIntCallback)(uint32_t data),
7365 +       void (*UnMaskIntCallback)(uint32_t data));
7366 +
7367 +
7368 +int GdmaMem2Mem(uint32_t Src, uint32_t Dst, uint16_t TransCount,
7369 +               void (*DoneIntCallback)(uint32_t data));
7370 +
7371 +int GdmaMaskChannel(uint32_t ChNum);
7372 +
7373 +int GdmaUnMaskChannel(uint32_t ChNum);
7374 +
7375 +int GdmaReqQuickIns(uint32_t ChNum);
7376 +
7377 +
7378 +#endif
7379 --- a/sound/soc/soc-core.c
7380 +++ b/sound/soc/soc-core.c
7381 @@ -1851,7 +1851,8 @@
7382         /* Bodge while we unpick instantiation */
7383         card->dev = &pdev->dev;
7384
7385 -       return snd_soc_register_card(card);
7386 +       snd_soc_register_card(card);
7387 +       return 0;
7388  }
7389
7390  static int soc_cleanup_card_resources(struct snd_soc_card *card)
7391 --- /dev/null
7392 +++ b/sound/soc/mtk/i2s_debug.c
7393 @@ -0,0 +1,698 @@
7394 +#include <linux/init.h>
7395 +#include <linux/version.h>
7396 +#include <linux/module.h>
7397 +#include <linux/kernel.h> /* printk() */
7398 +#include "i2s_ctrl.h"
7399 +#include <linux/delay.h>
7400 +#include <linux/jiffies.h>
7401 +#include <linux/random.h>
7402 +#include <linux/slab.h>
7403 +#include <asm/uaccess.h> /* copy_from/to_user */
7404 +
7405 +#if defined(CONFIG_SND_RALINK_SOC)
7406 +#include <sound/soc/mtk/mtk_audio_device.h>
7407 +#endif
7408 +
7409 +#if defined(CONFIG_I2S_WM8750)
7410 +#include "../codec/i2c_wm8750.h"
7411 +#endif
7412 +#if defined(CONFIG_I2S_WM8751)
7413 +#include "../codec/i2c_wm8751.h"
7414 +#endif
7415 +#if defined(CONFIG_I2S_WM8960)
7416 +#include "i2c_wm8960.h"
7417 +#endif
7418 +
7419 +
7420 +//#define INTERNAL_LOOPBACK_DEBUG
7421 +
7422 +extern unsigned long i2s_codec_12p288Mhz[11];
7423 +extern unsigned long i2s_codec_12Mhz[11];
7424 +#if defined(CONFIG_RALINK_MT7628) || defined(CONFIG_ARCH_MT7623)
7425 +extern unsigned long i2s_inclk_int_16bit[13];
7426 +extern unsigned long i2s_inclk_comp_16bit[13];
7427 +extern unsigned long i2s_inclk_int_24bit[13];
7428 +extern unsigned long i2s_inclk_comp_24bit[13];
7429 +#else
7430 +extern unsigned long i2s_inclk_int[11];
7431 +extern unsigned long i2s_inclk_comp[11];
7432 +#endif
7433 +extern int i2s_pll_config_mt7621(unsigned long index);
7434 +extern int i2s_pll_config_mt7623(unsigned long index);
7435 +
7436 +#if defined(CONFIG_I2S_WM8960) || defined(CONFIG_I2S_WM8750) || defined(CONFIG_I2S_WM8751)
7437 +extern void audiohw_loopback(int fsel);
7438 +extern void audiohw_bypass(void);
7439 +extern int audiohw_set_lineout_vol(int Aout, int vol_l, int vol_r);
7440 +extern int audiohw_set_linein_vol(int vol_l, int vol_r);
7441 +#endif
7442 +
7443 +#if defined(CONFIG_I2S_WM8960)
7444 +extern void audiohw_codec_exlbk(void);
7445 +#endif
7446 +
7447 +unsigned long txbuffer[512] = {
7448 +                               0x01020304, 0x05060708, 0x090a0b0c, 0x0d0e0f10, 0x11121314, 0x15161718, 0x191a1b1c, 0x1d1e1f20,
7449 +                               0x21222324, 0x25262728, 0x292a2b2c, 0x2d2e2f30, 0x31323334, 0x35363738, 0x393a3b3c, 0x3d3e3f40,
7450 +                               0x41424344, 0x45464748, 0x494a4b4c, 0x4d4e4f50, 0x51525354, 0x55565758, 0x595a5b5c, 0x5d5e5f60,
7451 +                               0x61626364, 0x65666768, 0x696a6b6c, 0x6d6e6f70, 0x71727374, 0x75767778, 0x797a7b7c, 0x7d7e7f80,
7452 +                               0x81828384, 0x85868788, 0x898a8b8c, 0x8d8e8f90, 0x91929394, 0x95969798, 0x999a9b9c, 0x9d9e9fa0,
7453 +                               0xa1a2a3a4, 0xa5a6a7a8, 0xa9aaabac, 0xadaeafb0, 0xb1b2b3b4, 0xb5b6b7b8, 0xb9babbbc, 0xbdbebfc0,
7454 +                               0xc1c2c3c4, 0xc5c6c7c8, 0xc9cacbcc, 0xcdcecfd0, 0xd1d2d3d4, 0xd5d6d7d8, 0xd9dadbdc, 0xdddedfe0,
7455 +                               0xe1e2e3e4, 0xe5e6e7e8, 0xe9eaebec, 0xedeeeff0, 0xf1f2f3f4, 0xf5f6f7f8, 0xf9fafbfc, 0xfdfeff00, //round 1
7456 +0x01020304, 0x05060708, 0x090a0b0c, 0x0d0e0f10, 0x11121314, 0x15161718, 0x191a1b1c, 0x1d1e1f20,
7457 +                               0x21222324, 0x25262728, 0x292a2b2c, 0x2d2e2f30, 0x31323334, 0x35363738, 0x393a3b3c, 0x3d3e3f40,
7458 +                               0x41424344, 0x45464748, 0x494a4b4c, 0x4d4e4f50, 0x51525354, 0x55565758, 0x595a5b5c, 0x5d5e5f60,
7459 +                               0x61626364, 0x65666768, 0x696a6b6c, 0x6d6e6f70, 0x71727374, 0x75767778, 0x797a7b7c, 0x7d7e7f80,
7460 +                               0x81828384, 0x85868788, 0x898a8b8c, 0x8d8e8f90, 0x91929394, 0x95969798, 0x999a9b9c, 0x9d9e9fa0,
7461 +                               0xa1a2a3a4, 0xa5a6a7a8, 0xa9aaabac, 0xadaeafb0, 0xb1b2b3b4, 0xb5b6b7b8, 0xb9babbbc, 0xbdbebfc0,
7462 +                               0xc1c2c3c4, 0xc5c6c7c8, 0xc9cacbcc, 0xcdcecfd0, 0xd1d2d3d4, 0xd5d6d7d8, 0xd9dadbdc, 0xdddedfe0,
7463 +                               0xe1e2e3e4, 0xe5e6e7e8, 0xe9eaebec, 0xedeeeff0, 0xf1f2f3f4, 0xf5f6f7f8, 0xf9fafbfc, 0xfdfeff00, //round 2
7464 +0x01020304, 0x05060708, 0x090a0b0c, 0x0d0e0f10, 0x11121314, 0x15161718, 0x191a1b1c, 0x1d1e1f20,
7465 +                               0x21222324, 0x25262728, 0x292a2b2c, 0x2d2e2f30, 0x31323334, 0x35363738, 0x393a3b3c, 0x3d3e3f40,
7466 +                               0x41424344, 0x45464748, 0x494a4b4c, 0x4d4e4f50, 0x51525354, 0x55565758, 0x595a5b5c, 0x5d5e5f60,
7467 +                               0x61626364, 0x65666768, 0x696a6b6c, 0x6d6e6f70, 0x71727374, 0x75767778, 0x797a7b7c, 0x7d7e7f80,
7468 +                               0x81828384, 0x85868788, 0x898a8b8c, 0x8d8e8f90, 0x91929394, 0x95969798, 0x999a9b9c, 0x9d9e9fa0,
7469 +                               0xa1a2a3a4, 0xa5a6a7a8, 0xa9aaabac, 0xadaeafb0, 0xb1b2b3b4, 0xb5b6b7b8, 0xb9babbbc, 0xbdbebfc0,
7470 +                               0xc1c2c3c4, 0xc5c6c7c8, 0xc9cacbcc, 0xcdcecfd0, 0xd1d2d3d4, 0xd5d6d7d8, 0xd9dadbdc, 0xdddedfe0,
7471 +                               0xe1e2e3e4, 0xe5e6e7e8, 0xe9eaebec, 0xedeeeff0, 0xf1f2f3f4, 0xf5f6f7f8, 0xf9fafbfc, 0xfdfeff00, //round 3
7472 +0x01020304, 0x05060708, 0x090a0b0c, 0x0d0e0f10, 0x11121314, 0x15161718, 0x191a1b1c, 0x1d1e1f20,
7473 +                               0x21222324, 0x25262728, 0x292a2b2c, 0x2d2e2f30, 0x31323334, 0x35363738, 0x393a3b3c, 0x3d3e3f40,
7474 +                               0x41424344, 0x45464748, 0x494a4b4c, 0x4d4e4f50, 0x51525354, 0x55565758, 0x595a5b5c, 0x5d5e5f60,
7475 +                               0x61626364, 0x65666768, 0x696a6b6c, 0x6d6e6f70, 0x71727374, 0x75767778, 0x797a7b7c, 0x7d7e7f80,
7476 +                               0x81828384, 0x85868788, 0x898a8b8c, 0x8d8e8f90, 0x91929394, 0x95969798, 0x999a9b9c, 0x9d9e9fa0,
7477 +                               0xa1a2a3a4, 0xa5a6a7a8, 0xa9aaabac, 0xadaeafb0, 0xb1b2b3b4, 0xb5b6b7b8, 0xb9babbbc, 0xbdbebfc0,
7478 +                               0xc1c2c3c4, 0xc5c6c7c8, 0xc9cacbcc, 0xcdcecfd0, 0xd1d2d3d4, 0xd5d6d7d8, 0xd9dadbdc, 0xdddedfe0,
7479 +                               0xe1e2e3e4, 0xe5e6e7e8, 0xe9eaebec, 0xedeeeff0, 0xf1f2f3f4, 0xf5f6f7f8, 0xf9fafbfc, 0xfdfeff00, //round 4
7480 +0x01020304, 0x05060708, 0x090a0b0c, 0x0d0e0f10, 0x11121314, 0x15161718, 0x191a1b1c, 0x1d1e1f20,
7481 +                               0x21222324, 0x25262728, 0x292a2b2c, 0x2d2e2f30, 0x31323334, 0x35363738, 0x393a3b3c, 0x3d3e3f40,
7482 +                               0x41424344, 0x45464748, 0x494a4b4c, 0x4d4e4f50, 0x51525354, 0x55565758, 0x595a5b5c, 0x5d5e5f60,
7483 +                               0x61626364, 0x65666768, 0x696a6b6c, 0x6d6e6f70, 0x71727374, 0x75767778, 0x797a7b7c, 0x7d7e7f80,
7484 +                               0x81828384, 0x85868788, 0x898a8b8c, 0x8d8e8f90, 0x91929394, 0x95969798, 0x999a9b9c, 0x9d9e9fa0,
7485 +                               0xa1a2a3a4, 0xa5a6a7a8, 0xa9aaabac, 0xadaeafb0, 0xb1b2b3b4, 0xb5b6b7b8, 0xb9babbbc, 0xbdbebfc0,
7486 +                               0xc1c2c3c4, 0xc5c6c7c8, 0xc9cacbcc, 0xcdcecfd0, 0xd1d2d3d4, 0xd5d6d7d8, 0xd9dadbdc, 0xdddedfe0,
7487 +                               0xe1e2e3e4, 0xe5e6e7e8, 0xe9eaebec, 0xedeeeff0, 0xf1f2f3f4, 0xf5f6f7f8, 0xf9fafbfc, 0xfdfeff00, //round 5
7488 +0x01020304, 0x05060708, 0x090a0b0c, 0x0d0e0f10, 0x11121314, 0x15161718, 0x191a1b1c, 0x1d1e1f20,
7489 +                               0x21222324, 0x25262728, 0x292a2b2c, 0x2d2e2f30, 0x31323334, 0x35363738, 0x393a3b3c, 0x3d3e3f40,
7490 +                               0x41424344, 0x45464748, 0x494a4b4c, 0x4d4e4f50, 0x51525354, 0x55565758, 0x595a5b5c, 0x5d5e5f60,
7491 +                               0x61626364, 0x65666768, 0x696a6b6c, 0x6d6e6f70, 0x71727374, 0x75767778, 0x797a7b7c, 0x7d7e7f80,
7492 +                               0x81828384, 0x85868788, 0x898a8b8c, 0x8d8e8f90, 0x91929394, 0x95969798, 0x999a9b9c, 0x9d9e9fa0,
7493 +                               0xa1a2a3a4, 0xa5a6a7a8, 0xa9aaabac, 0xadaeafb0, 0xb1b2b3b4, 0xb5b6b7b8, 0xb9babbbc, 0xbdbebfc0,
7494 +                               0xc1c2c3c4, 0xc5c6c7c8, 0xc9cacbcc, 0xcdcecfd0, 0xd1d2d3d4, 0xd5d6d7d8, 0xd9dadbdc, 0xdddedfe0,
7495 +                               0xe1e2e3e4, 0xe5e6e7e8, 0xe9eaebec, 0xedeeeff0, 0xf1f2f3f4, 0xf5f6f7f8, 0xf9fafbfc, 0xfdfeff00, //round 6
7496 +0x01020304, 0x05060708, 0x090a0b0c, 0x0d0e0f10, 0x11121314, 0x15161718, 0x191a1b1c, 0x1d1e1f20,
7497 +                               0x21222324, 0x25262728, 0x292a2b2c, 0x2d2e2f30, 0x31323334, 0x35363738, 0x393a3b3c, 0x3d3e3f40,
7498 +                               0x41424344, 0x45464748, 0x494a4b4c, 0x4d4e4f50, 0x51525354, 0x55565758, 0x595a5b5c, 0x5d5e5f60,
7499 +                               0x61626364, 0x65666768, 0x696a6b6c, 0x6d6e6f70, 0x71727374, 0x75767778, 0x797a7b7c, 0x7d7e7f80,
7500 +                               0x81828384, 0x85868788, 0x898a8b8c, 0x8d8e8f90, 0x91929394, 0x95969798, 0x999a9b9c, 0x9d9e9fa0,
7501 +                               0xa1a2a3a4, 0xa5a6a7a8, 0xa9aaabac, 0xadaeafb0, 0xb1b2b3b4, 0xb5b6b7b8, 0xb9babbbc, 0xbdbebfc0,
7502 +                               0xc1c2c3c4, 0xc5c6c7c8, 0xc9cacbcc, 0xcdcecfd0, 0xd1d2d3d4, 0xd5d6d7d8, 0xd9dadbdc, 0xdddedfe0,
7503 +                               0xe1e2e3e4, 0xe5e6e7e8, 0xe9eaebec, 0xedeeeff0, 0xf1f2f3f4, 0xf5f6f7f8, 0xf9fafbfc, 0xfdfeff00, //round 7
7504 +0x01020304, 0x05060708, 0x090a0b0c, 0x0d0e0f10, 0x11121314, 0x15161718, 0x191a1b1c, 0x1d1e1f20,
7505 +                               0x21222324, 0x25262728, 0x292a2b2c, 0x2d2e2f30, 0x31323334, 0x35363738, 0x393a3b3c, 0x3d3e3f40,
7506 +                               0x41424344, 0x45464748, 0x494a4b4c, 0x4d4e4f50, 0x51525354, 0x55565758, 0x595a5b5c, 0x5d5e5f60,
7507 +                               0x61626364, 0x65666768, 0x696a6b6c, 0x6d6e6f70, 0x71727374, 0x75767778, 0x797a7b7c, 0x7d7e7f80,
7508 +                               0x81828384, 0x85868788, 0x898a8b8c, 0x8d8e8f90, 0x91929394, 0x95969798, 0x999a9b9c, 0x9d9e9fa0,
7509 +                               0xa1a2a3a4, 0xa5a6a7a8, 0xa9aaabac, 0xadaeafb0, 0xb1b2b3b4, 0xb5b6b7b8, 0xb9babbbc, 0xbdbebfc0,
7510 +                               0xc1c2c3c4, 0xc5c6c7c8, 0xc9cacbcc, 0xcdcecfd0, 0xd1d2d3d4, 0xd5d6d7d8, 0xd9dadbdc, 0xdddedfe0,
7511 +                               0xe1e2e3e4, 0xe5e6e7e8, 0xe9eaebec, 0xedeeeff0, 0xf1f2f3f4, 0xf5f6f7f8, 0xf9fafbfc, 0xfdfeff00  //round 8
7512 +                               };
7513 +
7514 +int i2s_debug_cmd(unsigned int cmd, unsigned long arg)
7515 +{
7516 +       unsigned long data, index;
7517 +       unsigned long *pTable;
7518 +       int i;
7519 +
7520 +       switch(cmd)
7521 +       {
7522 +               case I2S_DEBUG_CLKGEN:
7523 +                       MSG("I2S_DEBUG_CLKGEN\n");
7524 +#if defined(CONFIG_RALINK_RT3052)
7525 +                       *(volatile unsigned long*)(0xB0000060) = 0x00000016;
7526 +                       *(volatile unsigned long*)(0xB0000030) = 0x00009E00;
7527 +                       *(volatile unsigned long*)(0xB0000A00) = 0xC0000040;
7528 +#elif defined(CONFIG_RALINK_RT3350)
7529 +                       *(volatile unsigned long*)(0xB0000060) = 0x00000018;
7530 +                       *(volatile unsigned long*)(0xB000002C) = 0x00000100;
7531 +                       *(volatile unsigned long*)(0xB0000030) = 0x00009E00;
7532 +                       *(volatile unsigned long*)(0xB0000A00) = 0xC0000040;
7533 +#elif defined(CONFIG_RALINK_RT3883)
7534 +                       *(volatile unsigned long*)(0xB0000060) = 0x00000018;
7535 +                       *(volatile unsigned long*)(0xB000002C) = 0x00003000;
7536 +                       *(volatile unsigned long*)(0xB0000A00) = 0xC1104040;
7537 +                       *(volatile unsigned long*)(0xB0000A24) = 0x00000027;
7538 +                       *(volatile unsigned long*)(0xB0000A20) = 0x80000020;
7539 +#elif (defined(CONFIG_RALINK_RT3352)||defined(CONFIG_RALINK_RT5350)) || defined (CONFIG_RALINK_RT6855)
7540 +                       *(volatile unsigned long*)(0xB0000060) = 0x00000018;
7541 +                       *(volatile unsigned long*)(0xB000002C) = 0x00000300;
7542 +                       *(volatile unsigned long*)(0xB0000A00) = 0xC1104040;
7543 +                       *(volatile unsigned long*)(0xB0000A24) = 0x00000027;
7544 +                       *(volatile unsigned long*)(0xB0000A20) = 0x80000020;
7545 +#elif defined(CONFIG_RALINK_RT6855A)
7546 +                       *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x860) = 0x00008080;
7547 +                       *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x82C) = 0x00000300;
7548 +                       *(volatile unsigned long*)(RALINK_I2S_BASE+0x00) = 0xC1104040;
7549 +                       *(volatile unsigned long*)(RALINK_I2S_BASE+0x24) = 0x00000027;
7550 +                       *(volatile unsigned long*)(RALINK_I2S_BASE+0x20) = 0x80000020;
7551 +#else
7552 +//#error "I2S debug mode not support this Chip"
7553 +#endif
7554 +                       break;
7555 +               case I2S_DEBUG_INLBK:
7556 +                       MSG("I2S_DEBUG_INLBK\n");
7557 +#if defined(CONFIG_RALINK_MT7621)
7558 +                        switch(96000)
7559 +                        {
7560 +                                case 8000:
7561 +                                        index = 0;
7562 +                                        break;
7563 +                                case 11025:
7564 +                                        index = 1;
7565 +                                        break;
7566 +                                case 12000:
7567 +                                        index = 2;
7568 +                                        break;
7569 +                                case 16000:
7570 +                                        index = 3;
7571 +                                        break;
7572 +                                case 22050:
7573 +                                        index = 4;
7574 +                                        break;
7575 +                                case 24000:
7576 +                                        index = 5;
7577 +                                        break;
7578 +                                case 32000:
7579 +                                        index = 6;
7580 +                                        break;
7581 +                                case 44100:
7582 +                                        index = 7;
7583 +                                        break;
7584 +                                case 48000:
7585 +                                        index = 8;
7586 +                                        break;
7587 +                                case 88200:
7588 +                                        index = 9;
7589 +                                        break;
7590 +                                case 96000:
7591 +                                        index = 10;
7592 +                                        break;
7593 +                               case 192000:
7594 +                                        index = 11;
7595 +                                        break;
7596 +                                default:
7597 +                                        index = 7;
7598 +                        }
7599 +                        i2s_pll_config_mt7621(index);
7600 +#elif defined(CONFIG_ARCH_MT7623)
7601 +                       i2s_pll_config_mt7623(11);
7602 +#endif
7603 +
7604 +
7605 +#if defined(CONFIG_RALINK_RT3052)
7606 +                       break;
7607 +#endif
7608 +#if defined(CONFIG_RALINK_RT6855A)
7609 +                       *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x834) |= 0x00020000;
7610 +                       *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x834) &= 0xFFFDFFFF;
7611 +                       *(volatile unsigned long*)(RALINK_I2S_BASE+0x0) &= 0x7FFFFFFF;  //Rest I2S to default vaule
7612 +                       *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x860) |= 0x00008080;
7613 +                       *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x82C) = 0x00000300;
7614 +#elif defined(CONFIG_RALINK_MT7621)
7615 +                        *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x34) |= 0x00020000;
7616 +                        *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x34) &= 0xFFFDFFFF;
7617 +                        *(volatile unsigned long*)(RALINK_I2S_BASE+0x0) &= 0x7FFFFFFF;   //Rest I2S to default vaule
7618 +                        *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x60) = 0x00000010;     //GPIO purpose selection
7619 +#elif defined(CONFIG_RALINK_MT7628)
7620 +                        *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x34) |= 0x00020000;
7621 +                        *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x34) &= 0xFFFDFFFF;
7622 +                        *(volatile unsigned long*)(RALINK_I2S_BASE+0x0) &= 0x7FFFFFFF;   //Rest I2S to default vaule
7623 +                        *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x60) &= ~((0x3)<<6);     //GPIO purpose selection /*FIXME*/
7624 +#elif defined(CONFIG_ARCH_MT7623)
7625 +                       *(volatile unsigned long*)(0xFB000034) |= 0x00020000;
7626 +                       *(volatile unsigned long*)(0xFB000034) &= 0xFFFDFFFF;
7627 +                       *(volatile unsigned long*)(ETHDMASYS_I2S_BASE+0x0) &= 0x7FFFFFFF;   //Rest I2S to default vaule
7628 +
7629 +                       *(volatile unsigned long*)(0xF0005840) &= ~((0x7)<<12);
7630 +                       *(volatile unsigned long*)(0xF0005840) |= ((0x6)<<12);
7631 +                       *(volatile unsigned long*)(0xF0005840) &= ~((0x7)<<9);
7632 +                       *(volatile unsigned long*)(0xF0005840) |= ((0x6)<<9);
7633 +                       *(volatile unsigned long*)(0xF0005040) |= ((0x1)<<10);
7634 +                       *(volatile unsigned long*)(0xF0005040) |= ((0x1)<<9);
7635 +
7636 +                       *(volatile unsigned long*)(0xF00057F0) &= ~((0x7)<<12);
7637 +                       *(volatile unsigned long*)(0xF00057F0) |= ((0x6)<<12);
7638 +                       *(volatile unsigned long*)(0xF0005030) |= ((0x1)<<1);
7639 +
7640 +                       *(volatile unsigned long*)(0xF0005840) &= ~((0x7)<<6);
7641 +                       *(volatile unsigned long*)(0xF0005840) |= ((0x6)<<6);
7642 +                       *(volatile unsigned long*)(0xF0005040) &= ~((0x1)<<8);
7643 +
7644 +                       *(volatile unsigned long*)(0xF00058F0) &= ~((0x7)<<3);
7645 +                       *(volatile unsigned long*)(0xF00058F0) |= ((0x6)<<3);
7646 +                       *(volatile unsigned long*)(0xF0005070) |= ((0x1)<<14);
7647 +
7648 +
7649 +#else
7650 +                       *(volatile unsigned long*)(0xB0000034) |= 0x00020000;
7651 +                       *(volatile unsigned long*)(0xB0000034) &= 0xFFFDFFFF;
7652 +                       *(volatile unsigned long*)(0xB0000A00) &= 0x7FFFFFFF;   //Rest I2S to default vaule
7653 +                       *(volatile unsigned long*)(0xB0000060) = 0x00000018;
7654 +
7655 +#if defined(CONFIG_RALINK_RT3883)
7656 +                       *(volatile unsigned long*)(0xB000002C) = 0x00003000;
7657 +#elif defined(CONFIG_ARCH_MT7623)
7658 +
7659 +#else
7660 +                       *(volatile unsigned long*)(0xB000002C) = 0x00000300;
7661 +#endif
7662 +#endif
7663 +#if defined(CONFIG_RALINK_MT7621)
7664 +                        *(volatile unsigned long*)(RALINK_I2S_BASE+0x18) = 0x80000000;
7665 +                        *(volatile unsigned long*)(RALINK_I2S_BASE+0x00) = 0xc1104040;
7666 +
7667 +                        pTable = i2s_inclk_int;
7668 +                        data = pTable[index];
7669 +                        //*(volatile unsigned long*)(RALINK_I2S_BASE+0x24) = data;
7670 +                        i2s_outw(RALINK_I2S_BASE+0x24, data);
7671 +
7672 +                        pTable = i2s_inclk_comp;
7673 +                        data = pTable[index];
7674 +                        //*(volatile unsigned long*)(RALINK_I2S_BASE+0x20) = data;
7675 +                        i2s_outw(RALINK_I2S_BASE+0x20, (data|0x80000000));
7676 +#elif defined(CONFIG_RALINK_MT7628)
7677 +                       index =11;  /* SR: 192k */
7678 +                       *(volatile unsigned long*)(RALINK_I2S_BASE+0x18) = 0x80000000;
7679 +                        *(volatile unsigned long*)(RALINK_I2S_BASE+0x00) = 0xc1104040;
7680 +
7681 +                        pTable = i2s_inclk_int_16bit;
7682 +                       //pTable = i2s_inclk_int_24bit;
7683 +                        data = pTable[index];
7684 +                        //*(volatile unsigned long*)(RALINK_I2S_BASE+0x24) = data;
7685 +                        i2s_outw(RALINK_I2S_BASE+0x24, data);
7686 +
7687 +                        pTable = i2s_inclk_comp_16bit;
7688 +                       //pTable = i2s_inclk_comp_24bit;
7689 +                        data = pTable[index];
7690 +                        //*(volatile unsigned long*)(RALINK_I2S_BASE+0x20) = data;
7691 +                        i2s_outw(RALINK_I2S_BASE+0x20, (data|0x80000000));
7692 +                       mdelay(5);
7693 +#elif defined(CONFIG_ARCH_MT7623)
7694 +                       index = 11;
7695 +                       *(volatile unsigned long*)(I2S_I2SCFG1) = 0x80000000;
7696 +                       *(volatile unsigned long*)(I2S_I2SCFG) = 0xE1104040;
7697 +                       *(volatile unsigned long*)(ETHDMASYS_SYSCTL_BASE+0x30) |= 0x00020000;
7698 +                       *(volatile unsigned long*)(ETHDMASYS_SYSCTL_BASE+0x2c) |= 0x00000080;
7699 +
7700 +                       pTable = i2s_inclk_int_16bit;
7701 +                       //pTable = i2s_inclk_int_24bit;
7702 +                        data = pTable[index];
7703 +                        i2s_outw(I2S_DIVINT_CFG, data);
7704 +
7705 +                        pTable = i2s_inclk_comp_16bit;
7706 +                       //pTable = i2s_inclk_comp_24bit;
7707 +                        data = pTable[index];
7708 +                        i2s_outw(I2S_DIVCOMP_CFG, (data|0x80000000));
7709 +                       mdelay(5);
7710 +#else
7711 +                       *(volatile unsigned long*)(RALINK_I2S_BASE+0x18) = 0x80000000;
7712 +                       *(volatile unsigned long*)(RALINK_I2S_BASE+0x00) = 0xC1104040;
7713 +                       *(volatile unsigned long*)(RALINK_I2S_BASE+0x24) = 0x00000006;
7714 +                       *(volatile unsigned long*)(RALINK_I2S_BASE+0x20) = 0x80000105;
7715 +#endif
7716 +                       {
7717 +                               int count = 0;
7718 +                               int k=0;
7719 +                               int enable_cnt=0;
7720 +                               unsigned long param[4];
7721 +                               unsigned long data;
7722 +                               //unsigned long data_tmp;
7723 +                               unsigned long ff_status;
7724 +                               //unsigned long* txbuffer;
7725 +#if 0
7726 +                               int j=0;
7727 +                               int temp = 0;
7728 +#endif
7729 +#if defined (INTERNAL_LOOPBACK_DEBUG)
7730 +                               int count2 = 0;
7731 +#endif
7732 +                               memset(param, 0, 4*sizeof(unsigned long) );
7733 +                               copy_from_user(param, (unsigned long*)arg, sizeof(long)*2);
7734 +#if 0
7735 +                               txbuffer = (unsigned long*)kcalloc(param[0], sizeof(unsigned long), GFP_KERNEL);
7736 +                               if(txbuffer == NULL)
7737 +                                       return -1;
7738 +#endif
7739 +
7740 +                               //ff_status = *(volatile unsigned long*)(RALINK_I2S_BASE+0x0C);
7741 +                               ff_status = *(volatile unsigned long*)(I2S_FF_STATUS);
7742 +                               printk("ff status=[0x%08X]\n",(u32)ff_status);
7743 +
7744 +#if 0
7745 +                               for(i = 0; i < param[0]; i++)
7746 +                               {
7747 +                                       if (i==0)
7748 +                                       {
7749 +                                               txbuffer[i] = 0x555A555A;
7750 +                                               printk("%d: 0x%8lx\n", i, txbuffer[i]);
7751 +                                       }
7752 +                                       else
7753 +                                       {
7754 +                                               #if LINUX_VERSION_CODE < KERNEL_VERSION(3,10,14)
7755 +                                               srandom32(jiffies);
7756 +                                               txbuffer[i] = random32()%(0x555A555A)+1;
7757 +                                               //printk("%d: 0x%8x\n", i, txbuffer[i]);
7758 +                                               #else
7759 +                                               //TODO:do we need to implement random32()
7760 +                                               txbuffer[i] = 0x01010101;
7761 +                                               #endif
7762 +                                       }
7763 +                               }
7764 +#endif
7765 +
7766 +                               for( i = 0 ; i < param[0] ; i ++ )
7767 +                               {
7768 +                                       ff_status = *(volatile unsigned long*)(I2S_FF_STATUS);
7769 +                               #if defined(CONFIG_RALINK_MT7628) || defined(CONFIG_ARCH_MT7623)
7770 +                                       if((ff_status&0xFF) > 0)
7771 +                               #else
7772 +                                       if((ff_status&0x0F) > 0)
7773 +                               #endif
7774 +                                       {
7775 +                                               *(volatile unsigned long*)(I2S_TX_FIFO_WREG) = txbuffer[i];
7776 +                                               mdelay(1);
7777 +                                       }
7778 +                                       else
7779 +                                       {
7780 +                                               mdelay(1);
7781 +                                               printk("[%d]NO TX FREE FIFO ST=[0x%08X]\n", i, (u32)ff_status);
7782 +                                               continue;
7783 +                                       }
7784 +
7785 +                                       //if(i >= 16)
7786 +                                       {
7787 +
7788 +                                               ff_status = *(volatile unsigned long*)(I2S_FF_STATUS);
7789 +                                       #if defined(CONFIG_RALINK_MT7628)
7790 +                                               if(((ff_status>>8)&0xFF) > 0)
7791 +                                       #else
7792 +                                               if(((ff_status>>4)&0x0F) > 0)
7793 +                                       #endif
7794 +                                               {
7795 +                                                       data = *(volatile unsigned long*)(I2S_RX_FIFO_RREG);
7796 +                                                       //data_tmp = *(volatile unsigned long*)(I2S_RX_FIFO_RREG);
7797 +                                                       //MSG("[0x%08X] vs [0x%08X]\n", (u32)data, (u32)data_tmp);
7798 +                                               }
7799 +                                               else
7800 +                                               {
7801 +                                                       printk("*[%d]NO RX FREE FIFO ST=[0x%08X]\n", i, (u32)ff_status);
7802 +                                                       continue;
7803 +                                               }
7804 +
7805 +                                               if (data == txbuffer[0])
7806 +                                               {
7807 +                                                       k = i;
7808 +                                                       enable_cnt = 1;
7809 +                                               }
7810 +                                               if (enable_cnt==1)
7811 +                                               {
7812 +                                                       if(data!= txbuffer[i-k])
7813 +                                                       {
7814 +                                                               MSG("[%d][0x%08X] vs [0x%08X]\n", (i-k), (u32)data, (u32)txbuffer[i-k]);
7815 +                                                       }
7816 +                                                       else
7817 +                                                       {
7818 +                                                               //MSG("**[%d][0x%08X] vs [0x%08X]\n" ,(i-k), (u32)data , (u32)txbuffer[i-k]);
7819 +                                                               count++;
7820 +                                                               data=0;
7821 +                                                       }
7822 +                                               }
7823 +
7824 +                                       }
7825 +                               }
7826 +#if 0
7827 +                               temp = i-k;
7828 +                               for (j=0; j<k; j++)
7829 +                               {
7830 +
7831 +                                       //ff_status = *(volatile unsigned long*)(RALINK_I2S_BASE+0x0C);
7832 +                                       ff_status = *(volatile unsigned long*)(I2S_FF_STATUS);
7833 +                               #if defined(CONFIG_RALINK_MT7628) || defined(CONFIG_ARCH_MT7623)
7834 +                                       if(((ff_status>>8)&0xFF) > 0)
7835 +                               #else
7836 +                                       if(((ff_status>>4)&0x0F) > 0)
7837 +                               #endif
7838 +                                       {
7839 +                                               //data = *(volatile unsigned long*)(RALINK_I2S_BASE+0x14);
7840 +                                               data = *(volatile unsigned long*)(I2S_RX_FIFO_RREG);
7841 +                                       }
7842 +                                       else
7843 +                                       {
7844 +                                               printk("*NO RX FREE FIFO ST=[0x%08X]\n", (u32)ff_status);
7845 +                                               continue;
7846 +                                       }
7847 +
7848 +                                       if(data!= txbuffer[temp+j])
7849 +                                       {
7850 +                                               MSG("[%d][0x%08X] vs [0x%08X]\n", (temp+j), (u32)data, (u32)txbuffer[temp+j]);
7851 +                                       }
7852 +                                       else
7853 +                                       {
7854 +                                               //MSG("&&[%d][0x%08X] vs [0x%08X]\n" ,(temp+j), (u32)data , (u32)txbuffer[temp+j]);
7855 +                                               count++;
7856 +                                               data=0;
7857 +                                       }
7858 +                                       if ((temp+j)==128)
7859 +                                       {
7860 +                                               //ff_status = *(volatile unsigned long*)(RALINK_I2S_BASE+0x0C);
7861 +                                               ff_status = *(volatile unsigned long*)(I2S_FF_STATUS);
7862 +                                               //printk("[%d]FIFO ST=[0x%08X]\n", (temp+j), (u32)ff_status);
7863 +                                       }
7864 +                               }
7865 +#endif
7866 +
7867 +#if defined (INTERNAL_LOOPBACK_DEBUG)
7868 +                               for( i = 0 ; i < param[0] ; i ++ )
7869 +                               {
7870 +                                       //ff_status = *(volatile unsigned long*)(RALINK_I2S_BASE+0x0C);
7871 +                                       ff_status = *(volatile unsigned long*)(I2S_FF_STATUS);
7872 +                               #if defined(CONFIG_RALINK_MT7628)|| defined(CONFIG_ARCH_MT7623)
7873 +                                       if((ff_status&0xFF) > 0)
7874 +                               #else
7875 +                                       if((ff_status&0x0F) > 0)
7876 +                               #endif
7877 +                                       {
7878 +                                               //*(volatile unsigned long*)(RALINK_I2S_BASE+0x10) = txbuffer[i];
7879 +                                               *(volatile unsigned long*)(I2S_TX_FIFO_WREG) = txbuffer[i];
7880 +                                               mdelay(1);
7881 +                                       }
7882 +                                       else
7883 +                                       {
7884 +                                               mdelay(1);
7885 +                                               printk("[%d]NO TX FREE FIFO ST=[0x%08X]\n", i, (u32)ff_status);
7886 +                                               continue;
7887 +                                       }
7888 +
7889 +                                       //if(i >= 16)
7890 +                                       {
7891 +
7892 +                                               //ff_status = *(volatile unsigned long*)(RALINK_I2S_BASE+0x0C);
7893 +                                               ff_status = *(volatile unsigned long*)(I2S_FF_STATUS);
7894 +                                       #if defined(CONFIG_RALINK_MT7628)|| defined(CONFIG_ARCH_MT7623)
7895 +                                               if(((ff_status>>8)&0xFF) > 0)
7896 +                                       #else
7897 +                                               if(((ff_status>>4)&0x0F) > 0)
7898 +                                       #endif
7899 +                                               {
7900 +                                                       //data = *(volatile unsigned long*)(RALINK_I2S_BASE+0x14);
7901 +                                                       data = *(volatile unsigned long*)(I2S_RX_FIFO_RREG);
7902 +                                               }
7903 +                                               else
7904 +                                               {
7905 +                                                       printk("*[%d]NO RX FREE FIFO ST=[0x%08X]\n", i, (u32)ff_status);
7906 +                                                       continue;
7907 +                                               }
7908 +
7909 +                                               {
7910 +                                                       if(data!= txbuffer[i])
7911 +                                                       {
7912 +                                                               MSG("[%d][0x%08X] vs [0x%08X]\n", (i), (u32)data, (u32)txbuffer[i]);
7913 +                                                       }
7914 +                                                       else
7915 +                                                       {
7916 +                                                               MSG("**[%d][0x%08X] vs [0x%08X]\n" ,(i), (u32)data , (u32)txbuffer[i]);
7917 +                                                               count2++;
7918 +                                                               data=0;
7919 +                                                       }
7920 +                                               }
7921 +
7922 +                                       }
7923 +                               }
7924 +                               printk("Pattern match done count2=%d.\n", count2);
7925 +#endif
7926 +                               printk("Pattern match done count=%d.\n", count);
7927 +
7928 +                       }
7929 +#if defined(CONFIG_ARCH_MT7623)
7930 +                       *(volatile unsigned long*)(0xFB000034) |= 0x00020000;
7931 +                       *(volatile unsigned long*)(0xFB000034) &= 0xFFFDFFFF;
7932 +                       *(volatile unsigned long*)(ETHDMASYS_I2S_BASE+0x0) &= 0x7FFFFFFF;   //Rest I2S to default vaule
7933 +#endif
7934 +
7935 +#if !defined(CONFIG_RALINK_RT3052)
7936 +                       break;
7937 +#endif
7938 +               case I2S_DEBUG_EXLBK:
7939 +                       MSG("I2S_DEBUG_EXLBK\n");
7940 +#if !defined(CONFIG_ARCH_MT7623)
7941 +                       switch(arg)
7942 +                       {
7943 +                               case 8000:
7944 +                                       index = 0;
7945 +                                       break;
7946 +                               case 11025:
7947 +                                       index = 1;
7948 +                                       break;
7949 +                               case 12000:
7950 +                                       index = 2;
7951 +                                       break;
7952 +                               case 16000:
7953 +                                       index = 3;
7954 +                                       break;
7955 +                               case 22050:
7956 +                                       index = 4;
7957 +                                       break;
7958 +                               case 24000:
7959 +                                       index = 5;
7960 +                                       break;
7961 +                               case 32000:
7962 +                                       index = 6;
7963 +                                       break;
7964 +                               case 44100:
7965 +                                       index = 7;
7966 +                                       break;
7967 +                               case 48000:
7968 +                                       index = 8;
7969 +                                       break;
7970 +                               case 88200:
7971 +                                       index = 9;
7972 +                                       break;
7973 +                               case 96000:
7974 +                                       index = 10;
7975 +                                       break;
7976 +                               default:
7977 +                                       index = 7;
7978 +                       }
7979 +#if defined(CONFIG_RALINK_RT3052)
7980 +                       break;
7981 +#endif
7982 +#if defined(CONFIG_RALINK_RT6855A)
7983 +                       *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x860) = 0x00008080;
7984 +                       //*(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x82C) = 0x00000300;
7985 +#else
7986 +                       *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x60) = 0x00000018;
7987 +#if defined(CONFIG_RALINK_RT3883)
7988 +                       *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x2C) = 0x00003000;
7989 +#else
7990 +                       *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x2C) = 0x00000300;
7991 +#endif
7992 +#endif
7993 +
7994 +                       *(volatile unsigned long*)(RALINK_I2S_BASE+0x18) = 0x40000000;
7995 +                       *(volatile unsigned long*)(RALINK_I2S_BASE+0x00) = 0x81104040;
7996 +#if defined(CONFIG_RALINK_MT7628)
7997 +                       pTable = i2s_inclk_int_16bit;
7998 +#else
7999 +                       pTable = i2s_inclk_int;
8000 +#endif
8001 +                       data = (volatile unsigned long)(pTable[index]);
8002 +                       i2s_outw(I2S_DIVINT_CFG, data);
8003 +#if defined(CONFIG_RALINK_MT7628)
8004 +                       pTable = i2s_inclk_comp_16bit;
8005 +#else
8006 +                       pTable = i2s_inclk_comp;
8007 +#endif
8008 +                       data = (volatile unsigned long)(pTable[index]);
8009 +                       data |= REGBIT(1, I2S_CLKDIV_EN);
8010 +                       i2s_outw(I2S_DIVCOMP_CFG, data);
8011 +
8012 +               #if defined(CONFIG_I2S_MCLK_12MHZ)
8013 +                       pTable = i2s_codec_12Mhz;
8014 +                       #if defined(CONFIG_I2S_WM8960)
8015 +                               data = pTable[index];
8016 +                       #else
8017 +                               data = pTable[index]|0x01;
8018 +                       #endif
8019 +               #else
8020 +                       pTable = i2s_codec_12p288Mhz;
8021 +                       data = pTable[index];
8022 +               #endif
8023 +
8024 +               #if defined(CONFIG_I2S_WM8960) || defined(CONFIG_I2S_WM8750) || defined(CONFIG_I2S_WM8751)
8025 +                       audiohw_preinit();
8026 +               #endif
8027 +
8028 +
8029 +               #if defined (CONFIG_I2S_WM8960)
8030 +                       audiohw_postinit(1, 1, 1, 1, 0); // for codec apll enable, 16 bit word length
8031 +               #elif defined(CONFIG_I2S_WM8750) || defined(CONFIG_I2S_WM8751)
8032 +                       audiohw_postinit(1, 1, 1, 0); // for 16 bit word length
8033 +               #endif
8034 +
8035 +
8036 +               #if defined (CONFIG_I2S_WM8960)
8037 +                       audiohw_set_frequency(data, 1); // for codec apll enable
8038 +               #elif defined(CONFIG_I2S_WM8750) || defined(CONFIG_I2S_WM8751)
8039 +                       audiohw_set_frequency(data|0x1);
8040 +               #endif
8041 +
8042 +
8043 +               #if defined(CONFIG_I2S_WM8960) || defined(CONFIG_I2S_WM8750) || defined(CONFIG_I2S_WM8751)
8044 +                       audiohw_set_lineout_vol(1, 100, 100);
8045 +                       audiohw_set_linein_vol(100, 100);
8046 +               #endif
8047 +
8048 +
8049 +               #if defined(CONFIG_I2S_TXRX)
8050 +                       //audiohw_loopback(data);
8051 +               #endif
8052 +               #if !defined(CONFIG_RALINK_RT3052)
8053 +                       break;
8054 +               #endif
8055 +#endif
8056 +               case I2S_DEBUG_CODECBYPASS:
8057 +               #if defined(CONFIG_I2S_TXRX)
8058 +               #if defined(CONFIG_RALINK_MT7628)
8059 +                       data = i2s_inw(RALINK_SYSCTL_BASE+0x60);
8060 +                       //data &= ~(0x3<<4);
8061 +                       data &= ~(0x3<<6);
8062 +                       data &= ~(0x3<<16);
8063 +                       data &= ~(0x1<<14);
8064 +                       i2s_outw(RALINK_SYSCTL_BASE+0x60, data);
8065 +
8066 +                       data = i2s_inw(RALINK_SYSCTL_BASE+0x2c);
8067 +                       data &= ~(0x07<<9);
8068 +                       i2s_outw(RALINK_SYSCTL_BASE+0x2c, data);
8069 +               #endif
8070 +
8071 +               #if defined(CONFIG_I2S_WM8960) || defined(CONFIG_I2S_WM8750) || defined(CONFIG_I2S_WM8751)
8072 +                       audiohw_bypass();       /* did not work */
8073 +               #endif
8074 +               #endif
8075 +                       break;
8076 +               case I2S_DEBUG_FMT:
8077 +                       break;
8078 +               case I2S_DEBUG_RESET:
8079 +                       break;
8080 +#if defined(CONFIG_I2S_WM8960)
8081 +               case I2S_DEBUG_CODEC_EXLBK:
8082 +                       audiohw_codec_exlbk();
8083 +                       break;
8084 +#endif
8085 +               default:
8086 +                       MSG("Not support this debug cmd [%d]\n", cmd);
8087 +                       break;
8088 +       }
8089 +
8090 +       return 0;
8091 +}
8092 --- a/sound/soc/codecs/wm8960.c
8093 +++ b/sound/soc/codecs/wm8960.c
8094 @@ -26,6 +26,7 @@
8095  #include <sound/wm8960.h>
8096
8097  #include "wm8960.h"
8098 +#include "../mtk/i2c_wm8960.h"
8099
8100  /* R25 - Power 1 */
8101  #define WM8960_VMID_MASK 0x180
8102 @@ -53,10 +54,10 @@
8103   * using 2 wire for device control, so we cache them instead.
8104   */
8105  static const struct reg_default wm8960_reg_defaults[] = {
8106 -       {  0x0, 0x00a7 },
8107 -       {  0x1, 0x00a7 },
8108 -       {  0x2, 0x0000 },
8109 -       {  0x3, 0x0000 },
8110 +       {  0x0, 0x002b },
8111 +       {  0x1, 0x002b },
8112 +       {  0x2, 0x00ff },
8113 +       {  0x3, 0x00ff },
8114         {  0x4, 0x0000 },
8115         {  0x5, 0x0008 },
8116         {  0x6, 0x0000 },
8117 @@ -88,8 +89,8 @@
8118         { 0x25, 0x0050 },
8119         { 0x26, 0x0000 },
8120         { 0x27, 0x0000 },
8121 -       { 0x28, 0x0000 },
8122 -       { 0x29, 0x0000 },
8123 +       { 0x28, 0x007b },
8124 +       { 0x29, 0x007b },
8125         { 0x2a, 0x0040 },
8126         { 0x2b, 0x0000 },
8127         { 0x2c, 0x0000 },
8128 @@ -127,8 +128,15 @@
8129         int playback_fs;
8130  };
8131
8132 +#if 1
8133 +#define wm8960_reset(c)        do{ \
8134 +       int i = 0;\
8135 +       snd_soc_write(c, WM8960_RESET, 0);\
8136 +       for(i = 0; i < 1000*HZ; i++);\
8137 +       }while(0)
8138 +#else
8139  #define wm8960_reset(c)        snd_soc_write(c, WM8960_RESET, 0)
8140 -
8141 +#endif
8142  /* enumerated controls */
8143  static const char *wm8960_polarity[] = {"No Inversion", "Left Inverted",
8144         "Right Inverted", "Stereo Inversion"};
8145 @@ -181,8 +189,8 @@
8146         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
8147         struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
8148
8149 -       ucontrol->value.integer.value[0] = wm8960->deemph;
8150 -       return 0;
8151 +       //ucontrol->value.integer.value[0] = wm8960->deemph;
8152 +       return wm8960->deemph;
8153  }
8154
8155  static int wm8960_put_deemph(struct snd_kcontrol *kcontrol,
8156 @@ -200,6 +208,70 @@
8157         return wm8960_set_deemph(codec);
8158  }
8159
8160 +static int wm8960_preinit(struct snd_soc_codec *codec)
8161 +{
8162 +       //printk("****** %s ******\n", __func__);
8163 +       snd_soc_write(codec, WM8960_RESET, 0);
8164 +       mdelay(500);
8165 +
8166 +       return 0;
8167 +}
8168 +
8169 +static int wm8960_postinit(struct snd_soc_codec *codec)
8170 +{
8171 +       u32 data;
8172 +       //printk("****** %s ******\n", __func__);
8173 +       // In
8174 +       data = snd_soc_read(codec, WM8960_POWER1);
8175 +       snd_soc_write(codec, WM8960_POWER1, data|WM8960_PWR1_ADCL|WM8960_PWR1_ADCR|WM8960_PWR1_AINL |WM8960_PWR1_AINR|WM8960_PWR1_MICB);//0x19
8176 +       data = snd_soc_read(codec, WM8960_ADDCTL1);
8177 +       snd_soc_write(codec, WM8960_ADDCTL1, data|ADDITIONAL1_DATSEL(0x01));//0x17
8178 +       snd_soc_write(codec, WM8960_LADC, LEFTGAIN_LDVU|LEFTGAIN_LDACVOL(0xc3));//0x15
8179 +       snd_soc_write(codec, WM8960_RADC, LEFTGAIN_LDVU|LEFTGAIN_LDACVOL(0xc3));//0x16
8180 +       snd_soc_write(codec, WM8960_LINPATH, 0x148);//0x20
8181 +       snd_soc_write(codec, WM8960_RINPATH, 0x148);//0x21
8182 +       snd_soc_write(codec, WM8960_POWER3, WM8960_PWR3_LMIC|WM8960_PWR3_RMIC);//0x2f
8183 +
8184 +       // Out
8185 +       data = snd_soc_read(codec, WM8960_POWER2);
8186 +       snd_soc_write(codec, WM8960_POWER2, data|WM8960_PWR2_DACL|WM8960_PWR2_DACR|WM8960_PWR2_LOUT1|WM8960_PWR2_ROUT1|WM8960_PWR2_SPKL|WM8960_PWR2_SPKR);//0x1a
8187 +       mdelay(10);
8188 +       snd_soc_write(codec, WM8960_IFACE2, 0x40);
8189 +       snd_soc_write(codec, WM8960_LDAC, LEFTGAIN_LDVU|LEFTGAIN_LDACVOL(0xff));//0x0a
8190 +       snd_soc_write(codec, WM8960_RDAC, RIGHTGAIN_RDVU|RIGHTGAIN_RDACVOL(0xff));//0x0b
8191 +       snd_soc_write(codec, WM8960_LOUTMIX, 0x100);//0x22
8192 +       snd_soc_write(codec, WM8960_ROUTMIX, 0x100);//0x25
8193 +
8194 +       data = snd_soc_read(codec, WM8960_POWER3);
8195 +       snd_soc_write(codec, WM8960_POWER3, data|WM8960_PWR3_ROMIX|WM8960_PWR3_LOMIX);//0x2f
8196 +
8197 +       snd_soc_write(codec, WM8960_CLASSD1, 0xf7);//0x31
8198 +       snd_soc_write(codec, WM8960_CLASSD3, 0xad);//0x33
8199 +       snd_soc_write(codec, WM8960_DACCTL1,  0x000);//0x05
8200 +
8201 +       data = snd_soc_read(codec, WM8960_POWER1);
8202 +       snd_soc_write(codec, WM8960_POWER1,  data|0x1c0);//0x19
8203 +
8204 +
8205 +       snd_soc_write(codec, WM8960_LOUT1, LOUT1_LO1VU|LOUT1_LO1ZC|LOUT1_LOUT1VOL(115));//0x02
8206 +       snd_soc_write(codec, WM8960_ROUT1, ROUT1_RO1VU|ROUT1_RO1ZC|ROUT1_ROUT1VOL(115));//0x03
8207 +
8208 +       snd_soc_write(codec, WM8960_LINVOL, LINV_IPVU|LINV_LINVOL(110)); //LINV(0x00)=>0x12b
8209 +       snd_soc_write(codec, WM8960_RINVOL, RINV_IPVU|RINV_RINVOL(110)); //LINV(0x01)=>0x12b
8210 +
8211 +       return 0;
8212 +}
8213 +
8214 +static int wm8960_close(struct snd_soc_codec *codec)
8215 +{
8216 +       snd_soc_write(codec, WM8960_DACCTL1,0x8); //0x05->0x08
8217 +       snd_soc_write(codec, WM8960_POWER1, 0x000); //0x19->0x000
8218 +       mdelay(300);
8219 +       snd_soc_write(codec, WM8960_POWER2, 0x000); //0x1a->0x000
8220 +
8221 +       return 0;
8222 +}
8223 +
8224  static const DECLARE_TLV_DB_SCALE(adc_tlv, -9700, 50, 0);
8225  static const DECLARE_TLV_DB_SCALE(dac_tlv, -12700, 50, 1);
8226  static const DECLARE_TLV_DB_SCALE(bypass_tlv, -2100, 300, 0);
8227 @@ -542,6 +614,7 @@
8228
8229         /* set iface */
8230         snd_soc_write(codec, WM8960_IFACE1, iface);
8231 +       wm8960_postinit(codec);
8232         return 0;
8233  }
8234
8235 @@ -623,11 +696,16 @@
8236                 break;
8237
8238         case SND_SOC_BIAS_PREPARE:
8239 +#if 0
8240                 /* Set VMID to 2x50k */
8241                 snd_soc_update_bits(codec, WM8960_POWER1, 0x180, 0x80);
8242 +#endif
8243                 break;
8244
8245         case SND_SOC_BIAS_STANDBY:
8246 +#if 1
8247 +               wm8960_preinit(codec);
8248 +#else
8249                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
8250                         regcache_sync(wm8960->regmap);
8251
8252 @@ -650,9 +728,13 @@
8253
8254                 /* Set VMID to 2x250k */
8255                 snd_soc_update_bits(codec, WM8960_POWER1, 0x180, 0x100);
8256 +#endif
8257                 break;
8258
8259         case SND_SOC_BIAS_OFF:
8260 +#if 1
8261 +               wm8960_close(codec);
8262 +#else
8263                 /* Enable anti-pop features */
8264                 snd_soc_write(codec, WM8960_APOP1,
8265                              WM8960_POBCTRL | WM8960_SOFT_ST |
8266 @@ -661,6 +743,7 @@
8267                 /* Disable VMID and VREF, let them discharge */
8268                 snd_soc_write(codec, WM8960_POWER1, 0);
8269                 msleep(600);
8270 +#endif
8271                 break;
8272         }
8273
8274 @@ -853,10 +936,15 @@
8275
8276         if (pll_div.k) {
8277                 reg |= 0x20;
8278 -
8279 +#if 1
8280                 snd_soc_write(codec, WM8960_PLL2, (pll_div.k >> 16) & 0xff);
8281                 snd_soc_write(codec, WM8960_PLL3, (pll_div.k >> 8) & 0xff);
8282                 snd_soc_write(codec, WM8960_PLL4, pll_div.k & 0xff);
8283 +#else
8284 +               snd_soc_write(codec, WM8960_PLL2, (pll_div.k >> 16) & 0xff);
8285 +               snd_soc_write(codec, WM8960_PLL3, (pll_div.k >> 8) & 0xff);
8286 +               snd_soc_write(codec, WM8960_PLL4, pll_div.k & 0xff);
8287 +#endif
8288         }
8289         snd_soc_write(codec, WM8960_PLL1, reg);
8290
8291 @@ -876,19 +964,27 @@
8292
8293         switch (div_id) {
8294         case WM8960_SYSCLKDIV:
8295 +               printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
8296                 reg = snd_soc_read(codec, WM8960_CLOCK1) & 0x1f9;
8297                 snd_soc_write(codec, WM8960_CLOCK1, reg | div);
8298                 break;
8299         case WM8960_DACDIV:
8300                 reg = snd_soc_read(codec, WM8960_CLOCK1) & 0x1c7;
8301 +               printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
8302                 snd_soc_write(codec, WM8960_CLOCK1, reg | div);
8303                 break;
8304         case WM8960_OPCLKDIV:
8305                 reg = snd_soc_read(codec, WM8960_PLL1) & 0x03f;
8306 +               printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
8307                 snd_soc_write(codec, WM8960_PLL1, reg | div);
8308                 break;
8309         case WM8960_DCLKDIV:
8310 +#if 1
8311 +               printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
8312                 reg = snd_soc_read(codec, WM8960_CLOCK2) & 0x03f;
8313 +#else
8314 +               reg = snd_soc_read(codec, WM8960_CLOCK2) & 0x03f;
8315 +#endif
8316                 snd_soc_write(codec, WM8960_CLOCK2, reg | div);
8317                 break;
8318         case WM8960_TOCLKSEL:
8319 @@ -962,7 +1058,7 @@
8320  {
8321         struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
8322         struct wm8960_data *pdata = dev_get_platdata(codec->dev);
8323 -       int ret;
8324 +       int ret = 0;
8325
8326         wm8960->set_bias_level = wm8960_set_bias_level_out3;
8327
8328 @@ -973,11 +1069,7 @@
8329                         wm8960->set_bias_level = wm8960_set_bias_level_capless;
8330         }
8331
8332 -       ret = wm8960_reset(codec);
8333 -       if (ret < 0) {
8334 -               dev_err(codec->dev, "Failed to issue reset\n");
8335 -               return ret;
8336 -       }
8337 +       wm8960_reset(codec);
8338
8339         wm8960->set_bias_level(codec, SND_SOC_BIAS_STANDBY);
8340
8341 --- a/sound/soc/codecs/wm8960.h
8342 +++ b/sound/soc/codecs/wm8960.h
8343 @@ -110,4 +110,68 @@
8344  #define WM8960_OPCLK_DIV_5_5           (4 << 0)
8345  #define WM8960_OPCLK_DIV_6             (5 << 0)
8346
8347 +/*
8348 + * WM8960 Power management
8349 +  */
8350 +#define WM8960_PWR1_VMIDSEL_DISABLED    (0 << 7)
8351 +#define WM8960_PWR1_VMIDSEL_50K         (1 << 7)
8352 +#define WM8960_PWR1_VMIDSEL_250K        (2 << 7)
8353 +#define WM8960_PWR1_VMIDSEL_5K          (3 << 7)
8354 +#define WM8960_PWR1_VREF                (1 << 6)
8355 +#define WM8960_PWR1_AINL                (1 << 5)
8356 +#define WM8960_PWR1_AINR                (1 << 4)
8357 +#define WM8960_PWR1_ADCL                (1 << 3)
8358 +#define WM8960_PWR1_ADCR                (1 << 2)
8359 +#define WM8960_PWR1_MICB                (1 << 1)
8360 +#define WM8960_PWR1_DIGENB              (1 << 0)
8361 +
8362 +#define WM8960_PWR2_DACL                (1 << 8)
8363 +#define WM8960_PWR2_DACR                (1 << 7)
8364 +//#define WM8960_PWR2_LOUT1               (1 << 6)
8365 +//#define WM8960_PWR2_ROUT1               (1 << 5)
8366 +#define WM8960_PWR2_SPKL                (1 << 4)
8367 +#define WM8960_PWR2_SPKR                (1 << 3)
8368 +//#define WM8960_PWR2_OUT3                (1 << 1)
8369 +#define WM8960_PWR2_PLL_EN              (1 << 0)
8370 +
8371 +#define WM8960_PWR3_LMIC                                (1 << 5)
8372 +#define WM8960_PWR3_RMIC                                (1 << 4)
8373 +#define WM8960_PWR3_LOMIX                               (1 << 3)
8374 +#define WM8960_PWR3_ROMIX                               (1 << 2)
8375 +
8376 +#define LEFTGAIN                        0x0a
8377 +#define LEFTGAIN_LDVU                   (1 << 8)
8378 +#define LEFTGAIN_LDACVOL(x)             ((x) & 0xff)
8379 +
8380 +#define RIGHTGAIN                       0x0b
8381 +#define RIGHTGAIN_RDVU                  (1 << 8)
8382 +#define RIGHTGAIN_RDACVOL(x)            ((x) & 0xff)
8383 +
8384 +#define ADDITIONAL1_DATSEL(x)           (((x) & 0x3) << 2)
8385 +
8386 +#define AINTFCE1_WL_32                  (3 << 2)
8387 +#define AINTFCE1_WL_24                  (2 << 2)
8388 +#define AINTFCE1_WL_20                  (1 << 2)
8389 +#define AINTFCE1_WL_16                  (0 << 2)
8390 +#define AINTFCE1_FORMAT_I2S             (2 << 0)
8391 +
8392 +#define LOUT1_LO1VU                     (1 << 8)
8393 +#define LOUT1_LO1ZC                     (1 << 7)
8394 +#define LOUT1_LOUT1VOL(x)               ((x) & 0x7f)
8395 +
8396 +#define ROUT1_RO1VU                     (1 << 8)
8397 +#define ROUT1_RO1ZC                     (1 << 7)
8398 +#define ROUT1_ROUT1VOL(x)               ((x) & 0x7f)
8399 +
8400 +#define LINV_IPVU                       (1 << 8)  /* FIXME */
8401 +
8402 +#define LINV_LINMUTE                    (1 << 7)
8403 +#define LINV_LIZC                       (1 << 6)
8404 +#define LINV_LINVOL(x)                  ((x) & 0x3f)
8405 +
8406 +#define RINV_IPVU                       (1 << 8) /* FIXME */
8407 +#define RINV_RINMUTE                    (1 << 7)
8408 +#define RINV_RIZC                       (1 << 6)
8409 +#define RINV_RINVOL(x)                  ((x) & 0x3f)
8410 +
8411  #endif