target/linux/ramips/patches-3.18/0037-USB-phy-add-ralink-SoC-driver.patch

   1 --- a/drivers/phy/Kconfig
   2 +++ b/drivers/phy/Kconfig
   3 @@ -239,6 +239,11 @@ config PHY_XGENE
   4         help
   5           This option enables support for APM X-Gene SoC multi-purpose PHY.
   6
   7 +config PHY_RALINK_USB
   8 +       tristate "Ralink USB PHY driver"
   9 +       select GENERIC_PHY
  10 +       depends on RALINK
  11 +
  12  config PHY_STIH407_USB
  13         tristate "STMicroelectronics USB2 picoPHY driver for STiH407 family"
  14         depends on RESET_CONTROLLER
  15 --- a/drivers/phy/Makefile
  16 +++ b/drivers/phy/Makefile
  17 @@ -31,3 +31,4 @@ obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY)  +=
  18  obj-$(CONFIG_PHY_XGENE)                        += phy-xgene.o
  19  obj-$(CONFIG_PHY_STIH407_USB)          += phy-stih407-usb.o
  20  obj-$(CONFIG_PHY_STIH41X_USB)          += phy-stih41x-usb.o
  21 +obj-$(CONFIG_PHY_RALINK_USB)           += phy-ralink-usb.o
  22 --- /dev/null
  23 +++ b/drivers/phy/phy-ralink-usb.c
  24 @@ -0,0 +1,228 @@
  25 +/*
  26 + * Allwinner ralink USB phy driver
  27 + *
  28 + * Copyright (C) 2016 John Crispin <blogic@openwrt.org>
  29 + *
  30 + * Based on code from
  31 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
  32 + *
  33 + * This program is free software; you can redistribute it and/or modify
  34 + * it under the terms of the GNU General Public License as published by
  35 + * the Free Software Foundation; either version 2 of the License, or
  36 + * (at your option) any later version.
  37 + *
  38 + * This program is distributed in the hope that it will be useful,
  39 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  40 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  41 + * GNU General Public License for more details.
  42 + */
  43 +
  44 +#include <linux/delay.h>
  45 +#include <linux/err.h>
  46 +#include <linux/io.h>
  47 +#include <linux/kernel.h>
  48 +#include <linux/module.h>
  49 +#include <linux/mutex.h>
  50 +#include <linux/phy/phy.h>
  51 +#include <linux/platform_device.h>
  52 +#include <linux/reset.h>
  53 +#include <linux/of_platform.h>
  54 +
  55 +#include <asm/mach-ralink/ralink_regs.h>
  56 +
  57 +#define RT_SYSC_REG_SYSCFG1            0x014
  58 +#define RT_SYSC_REG_CLKCFG1            0x030
  59 +#define RT_SYSC_REG_USB_PHY_CFG                0x05c
  60 +
  61 +#define OFS_U2_PHY_AC0                  0x800
  62 +#define OFS_U2_PHY_AC1                  0x804
  63 +#define OFS_U2_PHY_AC2                  0x808
  64 +#define OFS_U2_PHY_ACR0                 0x810
  65 +#define OFS_U2_PHY_ACR1                 0x814
  66 +#define OFS_U2_PHY_ACR2                 0x818
  67 +#define OFS_U2_PHY_ACR3                 0x81C
  68 +#define OFS_U2_PHY_ACR4                 0x820
  69 +#define OFS_U2_PHY_AMON0                0x824
  70 +#define OFS_U2_PHY_DCR0                 0x860
  71 +#define OFS_U2_PHY_DCR1                 0x864
  72 +#define OFS_U2_PHY_DTM0                 0x868
  73 +#define OFS_U2_PHY_DTM1                 0x86C
  74 +
  75 +#define RT_RSTCTRL_UDEV                        BIT(25)
  76 +#define RT_RSTCTRL_UHST                        BIT(22)
  77 +#define RT_SYSCFG1_USB0_HOST_MODE      BIT(10)
  78 +
  79 +#define MT7620_CLKCFG1_UPHY0_CLK_EN    BIT(25)
  80 +#define MT7620_CLKCFG1_UPHY1_CLK_EN    BIT(22)
  81 +#define RT_CLKCFG1_UPHY1_CLK_EN                BIT(20)
  82 +#define RT_CLKCFG1_UPHY0_CLK_EN                BIT(18)
  83 +
  84 +#define USB_PHY_UTMI_8B60M             BIT(1)
  85 +#define UDEV_WAKEUP                    BIT(0)
  86 +
  87 +struct ralink_usb_phy {
  88 +       struct reset_control    *rstdev;
  89 +       struct reset_control    *rsthost;
  90 +       u32                     clk;
  91 +       struct phy              *phy;
  92 +       void __iomem            *base;
  93 +};
  94 +
  95 +static void u2_phy_w32(struct ralink_usb_phy *phy, u32 val, u32 reg)
  96 +{
  97 +       iowrite32(val, phy->base + reg);
  98 +}
  99 +
 100 +static u32 u2_phy_r32(struct ralink_usb_phy *phy, u32 reg)
 101 +{
 102 +       return ioread32(phy->base + reg);
 103 +}
 104 +
 105 +static void
 106 +u2_phy_init(struct ralink_usb_phy *phy)
 107 +{
 108 +       u2_phy_r32(phy, OFS_U2_PHY_AC2);
 109 +       u2_phy_r32(phy, OFS_U2_PHY_ACR0);
 110 +       u2_phy_r32(phy, OFS_U2_PHY_DCR0);
 111 +
 112 +       u2_phy_w32(phy, 0x00ffff02, OFS_U2_PHY_DCR0);
 113 +       u2_phy_r32(phy, OFS_U2_PHY_DCR0);
 114 +       u2_phy_w32(phy, 0x00555502, OFS_U2_PHY_DCR0);
 115 +       u2_phy_r32(phy, OFS_U2_PHY_DCR0);
 116 +       u2_phy_w32(phy, 0x00aaaa02, OFS_U2_PHY_DCR0);
 117 +       u2_phy_r32(phy, OFS_U2_PHY_DCR0);
 118 +       u2_phy_w32(phy, 0x00000402, OFS_U2_PHY_DCR0);
 119 +       u2_phy_r32(phy, OFS_U2_PHY_DCR0);
 120 +       u2_phy_w32(phy, 0x0048086a, OFS_U2_PHY_AC0);
 121 +       u2_phy_w32(phy, 0x4400001c, OFS_U2_PHY_AC1);
 122 +       u2_phy_w32(phy, 0xc0200000, OFS_U2_PHY_ACR3);
 123 +       u2_phy_w32(phy, 0x02000000, OFS_U2_PHY_DTM0);
 124 +}
 125 +
 126 +static int ralink_usb_phy_power_on(struct phy *_phy)
 127 +{
 128 +       struct ralink_usb_phy *phy = phy_get_drvdata(_phy);
 129 +       u32 t;
 130 +
 131 +       /* enable the phy */
 132 +       rt_sysc_m32(0, phy->clk, RT_SYSC_REG_CLKCFG1);
 133 +
 134 +       /* setup host mode */
 135 +       rt_sysc_m32(0, RT_SYSCFG1_USB0_HOST_MODE, RT_SYSC_REG_SYSCFG1);
 136 +
 137 +       /* deassert the reset lines */
 138 +       reset_control_deassert(phy->rsthost);
 139 +       reset_control_deassert(phy->rstdev);
 140 +
 141 +       /*
 142 +        * The SDK kernel had a delay of 100ms. however on device
 143 +        * testing showed that 10ms is enough
 144 +        */
 145 +       mdelay(10);
 146 +
 147 +       if (!IS_ERR(phy->base))
 148 +               u2_phy_init(phy);
 149 +
 150 +       /* print some status info */
 151 +       t = rt_sysc_r32(RT_SYSC_REG_USB_PHY_CFG);
 152 +       dev_info(&phy->phy->dev, "remote usb device wakeup %s\n",
 153 +               (t & UDEV_WAKEUP) ? ("enabled") : ("disabled"));
 154 +       if (t & USB_PHY_UTMI_8B60M)
 155 +               dev_info(&phy->phy->dev, "UTMI 8bit 60MHz\n");
 156 +       else
 157 +               dev_info(&phy->phy->dev, "UTMI 16bit 30MHz\n");
 158 +
 159 +       return 0;
 160 +}
 161 +
 162 +static int ralink_usb_phy_power_off(struct phy *_phy)
 163 +{
 164 +       struct ralink_usb_phy *phy = phy_get_drvdata(_phy);
 165 +
 166 +       /* assert the reset lines */
 167 +       reset_control_assert(phy->rstdev);
 168 +       reset_control_assert(phy->rsthost);
 169 +
 170 +       /* disable the phy */
 171 +       rt_sysc_m32(phy->clk, 0, RT_SYSC_REG_CLKCFG1);
 172 +
 173 +       return 0;
 174 +}
 175 +
 176 +static struct phy_ops ralink_usb_phy_ops = {
 177 +       .power_on       = ralink_usb_phy_power_on,
 178 +       .power_off      = ralink_usb_phy_power_off,
 179 +       .owner          = THIS_MODULE,
 180 +};
 181 +
 182 +static const struct of_device_id ralink_usb_phy_of_match[] = {
 183 +       {
 184 +               .compatible = "ralink,rt3xxx-usbphy",
 185 +               .data = (void *) (RT_CLKCFG1_UPHY1_CLK_EN |
 186 +                                 RT_CLKCFG1_UPHY0_CLK_EN)
 187 +       },
 188 +       {
 189 +               .compatible = "ralink,mt7620a-usbphy",
 190 +               .data = (void *) (MT7620_CLKCFG1_UPHY1_CLK_EN |
 191 +                                 MT7620_CLKCFG1_UPHY0_CLK_EN) },
 192 +       { },
 193 +};
 194 +MODULE_DEVICE_TABLE(of, ralink_usb_phy_of_match);
 195 +
 196 +static int ralink_usb_phy_probe(struct platform_device *pdev)
 197 +{
 198 +       struct resource *res;
 199 +       struct device *dev = &pdev->dev;
 200 +       struct phy_provider *phy_provider;
 201 +       const struct of_device_id *match;
 202 +       struct ralink_usb_phy *phy;
 203 +
 204 +       phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
 205 +       if (!phy)
 206 +               return -ENOMEM;
 207 +
 208 +       match = of_match_device(ralink_usb_phy_of_match, &pdev->dev);
 209 +       if (!match)
 210 +               return -ENODEV;
 211 +
 212 +       phy->clk = (int) match->data;
 213 +
 214 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 215 +       phy->base = devm_ioremap_resource(&pdev->dev, res);
 216 +
 217 +       phy->rsthost = devm_reset_control_get(&pdev->dev, "host");
 218 +       if (IS_ERR(phy->rsthost)) {
 219 +               dev_err(dev, "host reset is missing\n");
 220 +               return PTR_ERR(phy->rsthost);
 221 +       }
 222 +
 223 +       phy->rstdev = devm_reset_control_get(&pdev->dev, "device");
 224 +       if (IS_ERR(phy->rstdev)) {
 225 +               dev_err(dev, "device reset is missing\n");
 226 +               return PTR_ERR(phy->rstdev);
 227 +       }
 228 +
 229 +       phy->phy = devm_phy_create(dev, NULL, &ralink_usb_phy_ops, NULL);
 230 +       if (IS_ERR(phy->phy)) {
 231 +               dev_err(dev, "failed to create PHY\n");
 232 +               return PTR_ERR(phy->phy);
 233 +       }
 234 +       phy_set_drvdata(phy->phy, phy);
 235 +
 236 +       phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
 237 +
 238 +       return PTR_ERR_OR_ZERO(phy_provider);
 239 +}
 240 +
 241 +static struct platform_driver ralink_usb_phy_driver = {
 242 +       .probe  = ralink_usb_phy_probe,
 243 +       .driver = {
 244 +               .of_match_table = ralink_usb_phy_of_match,
 245 +               .name  = "ralink-usb-phy",
 246 +       }
 247 +};
 248 +module_platform_driver(ralink_usb_phy_driver);
 249 +
 250 +MODULE_DESCRIPTION("Ralink USB phy driver");
 251 +MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
 252 +MODULE_LICENSE("GPL v2");