target/linux/brcm2708/patches-3.18/0019-Add-Chris-Boot-s-i2c-and-spi-drivers.patch

   1 From 66ea263246ca6dd9f63dce8fb22157fa83693300 Mon Sep 17 00:00:00 2001
   2 From: popcornmix <popcornmix@gmail.com>
   3 Date: Mon, 4 Nov 2013 18:56:10 +0000
   4 Subject: [PATCH 019/114] Add Chris Boot's i2c and spi drivers.
   5
   6 i2c-bcm2708: fixed baudrate
   7
   8 Fixed issue where the wrong CDIV value was set for baudrates below 3815 Hz (for 250MHz bus clock).
   9 In that case the computed CDIV value was more than 0xffff. However the CDIV register width is only 16 bits.
  10 This resulted in incorrect setting of CDIV and higher baudrate than intended.
  11 Example: 3500Hz -> CDIV=0x11704 -> CDIV(16bit)=0x1704 -> 42430Hz
  12 After correction: 3500Hz -> CDIV=0x11704 -> CDIV(16bit)=0xffff -> 3815Hz
  13 The correct baudrate is shown in the log after the cdiv > 0xffff correction.
  14 ---
  15  arch/arm/configs/bcmrpi_defconfig |   7 +
  16  arch/arm/mach-bcm2708/Kconfig     |   7 +
  17  arch/arm/mach-bcm2708/bcm2708.c   | 104 ++++++-
  18  drivers/i2c/busses/Kconfig        |  19 ++
  19  drivers/i2c/busses/Makefile       |   1 +
  20  drivers/i2c/busses/i2c-bcm2708.c  | 420 +++++++++++++++++++++++++
  21  drivers/spi/Kconfig               |   8 +
  22  drivers/spi/Makefile              |   1 +
  23  drivers/spi/spi-bcm2708.c         | 626 ++++++++++++++++++++++++++++++++++++++
  24  9 files changed, 1191 insertions(+), 2 deletions(-)
  25  create mode 100644 drivers/i2c/busses/i2c-bcm2708.c
  26  create mode 100644 drivers/spi/spi-bcm2708.c
  27
  28 --- a/arch/arm/configs/bcmrpi_defconfig
  29 +++ b/arch/arm/configs/bcmrpi_defconfig
  30 @@ -195,6 +195,13 @@ CONFIG_SERIAL_AMBA_PL011=y
  31  CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
  32  # CONFIG_HW_RANDOM is not set
  33  CONFIG_RAW_DRIVER=y
  34 +CONFIG_I2C=y
  35 +CONFIG_I2C_CHARDEV=m
  36 +CONFIG_I2C_BCM2708=m
  37 +CONFIG_SPI=y
  38 +CONFIG_SPI_BCM2708=m
  39 +CONFIG_SPI_SPIDEV=m
  40 +CONFIG_GPIO_SYSFS=y
  41  # CONFIG_HWMON is not set
  42  CONFIG_WATCHDOG=y
  43  CONFIG_FB=y
  44 --- a/arch/arm/mach-bcm2708/Kconfig
  45 +++ b/arch/arm/mach-bcm2708/Kconfig
  46 @@ -31,4 +31,11 @@ config BCM2708_NOL2CACHE
  47          help
  48            Do not allow ARM to use GPU's L2 cache. Requires disable_l2cache in config.txt.
  49
  50 +config BCM2708_SPIDEV
  51 +       bool "Bind spidev to SPI0 master"
  52 +       depends on MACH_BCM2708
  53 +       depends on SPI
  54 +       default y
  55 +       help
  56 +         Binds spidev driver to the SPI0 master
  57  endmenu
  58 --- a/arch/arm/mach-bcm2708/bcm2708.c
  59 +++ b/arch/arm/mach-bcm2708/bcm2708.c
  60 @@ -31,6 +31,7 @@
  61  #include <linux/cnt32_to_63.h>
  62  #include <linux/io.h>
  63  #include <linux/module.h>
  64 +#include <linux/spi/spi.h>
  65
  66  #include <linux/version.h>
  67  #include <linux/clkdev.h>
  68 @@ -205,7 +206,6 @@ static struct clk osc_clk = {
  69
  70  /* warning - the USB needs a clock > 34MHz */
  71
  72 -#ifdef CONFIG_MMC_BCM2708
  73  static struct clk sdhost_clk = {
  74  #ifdef CONFIG_ARCH_BCM2708_CHIPIT
  75         .rate = 4000000,        /* 4MHz */
  76 @@ -213,7 +213,6 @@ static struct clk sdhost_clk = {
  77         .rate = 250000000,      /* 250MHz */
  78  #endif
  79  };
  80 -#endif
  81
  82  static struct clk_lookup lookups[] = {
  83         {                       /* UART0 */
  84 @@ -223,6 +222,15 @@ static struct clk_lookup lookups[] = {
  85         {                       /* USB */
  86          .dev_id = "bcm2708_usb",
  87          .clk = &osc_clk,
  88 +        }, {   /* SPI */
  89 +                .dev_id = "bcm2708_spi.0",
  90 +                .clk = &sdhost_clk,
  91 +        }, {   /* BSC0 */
  92 +                .dev_id = "bcm2708_i2c.0",
  93 +                .clk = &sdhost_clk,
  94 +        }, {   /* BSC1 */
  95 +                .dev_id = "bcm2708_i2c.1",
  96 +                .clk = &sdhost_clk,
  97          }
  98  };
  99
 100 @@ -455,6 +463,89 @@ static struct platform_device bcm2708_al
 101                },
 102  };
 103
 104 +static struct resource bcm2708_spi_resources[] = {
 105 +       {
 106 +               .start = SPI0_BASE,
 107 +               .end = SPI0_BASE + SZ_256 - 1,
 108 +               .flags = IORESOURCE_MEM,
 109 +       }, {
 110 +               .start = IRQ_SPI,
 111 +               .end = IRQ_SPI,
 112 +               .flags = IORESOURCE_IRQ,
 113 +       }
 114 +};
 115 +
 116 +
 117 +static u64 bcm2708_spi_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
 118 +static struct platform_device bcm2708_spi_device = {
 119 +       .name = "bcm2708_spi",
 120 +       .id = 0,
 121 +       .num_resources = ARRAY_SIZE(bcm2708_spi_resources),
 122 +       .resource = bcm2708_spi_resources,
 123 +       .dev = {
 124 +               .dma_mask = &bcm2708_spi_dmamask,
 125 +               .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON)},
 126 +};
 127 +
 128 +#ifdef CONFIG_BCM2708_SPIDEV
 129 +static struct spi_board_info bcm2708_spi_devices[] = {
 130 +#ifdef CONFIG_SPI_SPIDEV
 131 +       {
 132 +               .modalias = "spidev",
 133 +               .max_speed_hz = 500000,
 134 +               .bus_num = 0,
 135 +               .chip_select = 0,
 136 +               .mode = SPI_MODE_0,
 137 +       }, {
 138 +               .modalias = "spidev",
 139 +               .max_speed_hz = 500000,
 140 +               .bus_num = 0,
 141 +               .chip_select = 1,
 142 +               .mode = SPI_MODE_0,
 143 +       }
 144 +#endif
 145 +};
 146 +#endif
 147 +
 148 +static struct resource bcm2708_bsc0_resources[] = {
 149 +       {
 150 +               .start = BSC0_BASE,
 151 +               .end = BSC0_BASE + SZ_256 - 1,
 152 +               .flags = IORESOURCE_MEM,
 153 +       }, {
 154 +               .start = INTERRUPT_I2C,
 155 +               .end = INTERRUPT_I2C,
 156 +               .flags = IORESOURCE_IRQ,
 157 +       }
 158 +};
 159 +
 160 +static struct platform_device bcm2708_bsc0_device = {
 161 +       .name = "bcm2708_i2c",
 162 +       .id = 0,
 163 +       .num_resources = ARRAY_SIZE(bcm2708_bsc0_resources),
 164 +       .resource = bcm2708_bsc0_resources,
 165 +};
 166 +
 167 +
 168 +static struct resource bcm2708_bsc1_resources[] = {
 169 +       {
 170 +               .start = BSC1_BASE,
 171 +               .end = BSC1_BASE + SZ_256 - 1,
 172 +               .flags = IORESOURCE_MEM,
 173 +       }, {
 174 +               .start = INTERRUPT_I2C,
 175 +               .end = INTERRUPT_I2C,
 176 +               .flags = IORESOURCE_IRQ,
 177 +       }
 178 +};
 179 +
 180 +static struct platform_device bcm2708_bsc1_device = {
 181 +       .name = "bcm2708_i2c",
 182 +       .id = 1,
 183 +       .num_resources = ARRAY_SIZE(bcm2708_bsc1_resources),
 184 +       .resource = bcm2708_bsc1_resources,
 185 +};
 186 +
 187  static struct platform_device bcm2835_hwmon_device = {
 188         .name = "bcm2835_hwmon",
 189  };
 190 @@ -571,6 +662,10 @@ void __init bcm2708_init(void)
 191         for (i = 0; i < ARRAY_SIZE(bcm2708_alsa_devices); i++)
 192                 bcm_register_device(&bcm2708_alsa_devices[i]);
 193
 194 +       bcm_register_device(&bcm2708_spi_device);
 195 +       bcm_register_device(&bcm2708_bsc0_device);
 196 +       bcm_register_device(&bcm2708_bsc1_device);
 197 +
 198         bcm_register_device(&bcm2835_hwmon_device);
 199         bcm_register_device(&bcm2835_thermal_device);
 200
 201 @@ -580,6 +675,11 @@ void __init bcm2708_init(void)
 202         }
 203         system_rev = boardrev;
 204         system_serial_low = serial;
 205 +
 206 +#ifdef CONFIG_BCM2708_SPIDEV
 207 +       spi_register_board_info(bcm2708_spi_devices,
 208 +                       ARRAY_SIZE(bcm2708_spi_devices));
 209 +#endif
 210  }
 211
 212  static void timer_set_mode(enum clock_event_mode mode,
 213 --- a/drivers/i2c/busses/Kconfig
 214 +++ b/drivers/i2c/busses/Kconfig
 215 @@ -371,6 +371,25 @@ config I2C_BCM2835
 216           This support is also available as a module.  If so, the module
 217           will be called i2c-bcm2835.
 218
 219 +config I2C_BCM2708
 220 +       tristate "BCM2708 BSC"
 221 +       depends on MACH_BCM2708
 222 +       help
 223 +         Enabling this option will add BSC (Broadcom Serial Controller)
 224 +         support for the BCM2708. BSC is a Broadcom proprietary bus compatible
 225 +         with I2C/TWI/SMBus.
 226 +
 227 +config I2C_BCM2708_BAUDRATE
 228 +       prompt "BCM2708 I2C baudrate"
 229 +       depends on I2C_BCM2708
 230 +       int
 231 +       default 100000
 232 +       help
 233 +         Set the I2C baudrate. This will alter the default value. A
 234 +         different baudrate can be set by using a module parameter as well. If
 235 +         no parameter is provided when loading, this is the value that will be
 236 +         used.
 237 +
 238  config I2C_BCM_KONA
 239         tristate "BCM Kona I2C adapter"
 240         depends on ARCH_BCM_MOBILE
 241 --- a/drivers/i2c/busses/Makefile
 242 +++ b/drivers/i2c/busses/Makefile
 243 @@ -33,6 +33,7 @@ obj-$(CONFIG_I2C_AT91)                += i2c-at91.o
 244  obj-$(CONFIG_I2C_AU1550)       += i2c-au1550.o
 245  obj-$(CONFIG_I2C_AXXIA)                += i2c-axxia.o
 246  obj-$(CONFIG_I2C_BCM2835)      += i2c-bcm2835.o
 247 +obj-$(CONFIG_I2C_BCM2708)      += i2c-bcm2708.o
 248  obj-$(CONFIG_I2C_BLACKFIN_TWI) += i2c-bfin-twi.o
 249  obj-$(CONFIG_I2C_CADENCE)      += i2c-cadence.o
 250  obj-$(CONFIG_I2C_CBUS_GPIO)    += i2c-cbus-gpio.o
 251 --- /dev/null
 252 +++ b/drivers/i2c/busses/i2c-bcm2708.c
 253 @@ -0,0 +1,420 @@
 254 +/*
 255 + * Driver for Broadcom BCM2708 BSC Controllers
 256 + *
 257 + * Copyright (C) 2012 Chris Boot & Frank Buss
 258 + *
 259 + * This driver is inspired by:
 260 + * i2c-ocores.c, by Peter Korsgaard <jacmet@sunsite.dk>
 261 + *
 262 + * This program is free software; you can redistribute it and/or modify
 263 + * it under the terms of the GNU General Public License as published by
 264 + * the Free Software Foundation; either version 2 of the License, or
 265 + * (at your option) any later version.
 266 + *
 267 + * This program is distributed in the hope that it will be useful,
 268 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 269 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 270 + * GNU General Public License for more details.
 271 + *
 272 + * You should have received a copy of the GNU General Public License
 273 + * along with this program; if not, write to the Free Software
 274 + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 275 + */
 276 +
 277 +#include <linux/kernel.h>
 278 +#include <linux/module.h>
 279 +#include <linux/spinlock.h>
 280 +#include <linux/clk.h>
 281 +#include <linux/err.h>
 282 +#include <linux/platform_device.h>
 283 +#include <linux/io.h>
 284 +#include <linux/slab.h>
 285 +#include <linux/i2c.h>
 286 +#include <linux/interrupt.h>
 287 +#include <linux/sched.h>
 288 +#include <linux/wait.h>
 289 +
 290 +/* BSC register offsets */
 291 +#define BSC_C                  0x00
 292 +#define BSC_S                  0x04
 293 +#define BSC_DLEN               0x08
 294 +#define BSC_A                  0x0c
 295 +#define BSC_FIFO               0x10
 296 +#define BSC_DIV                        0x14
 297 +#define BSC_DEL                        0x18
 298 +#define BSC_CLKT               0x1c
 299 +
 300 +/* Bitfields in BSC_C */
 301 +#define BSC_C_I2CEN            0x00008000
 302 +#define BSC_C_INTR             0x00000400
 303 +#define BSC_C_INTT             0x00000200
 304 +#define BSC_C_INTD             0x00000100
 305 +#define BSC_C_ST               0x00000080
 306 +#define BSC_C_CLEAR_1          0x00000020
 307 +#define BSC_C_CLEAR_2          0x00000010
 308 +#define BSC_C_READ             0x00000001
 309 +
 310 +/* Bitfields in BSC_S */
 311 +#define BSC_S_CLKT             0x00000200
 312 +#define BSC_S_ERR              0x00000100
 313 +#define BSC_S_RXF              0x00000080
 314 +#define BSC_S_TXE              0x00000040
 315 +#define BSC_S_RXD              0x00000020
 316 +#define BSC_S_TXD              0x00000010
 317 +#define BSC_S_RXR              0x00000008
 318 +#define BSC_S_TXW              0x00000004
 319 +#define BSC_S_DONE             0x00000002
 320 +#define BSC_S_TA               0x00000001
 321 +
 322 +#define I2C_TIMEOUT_MS 150
 323 +
 324 +#define DRV_NAME       "bcm2708_i2c"
 325 +
 326 +static unsigned int baudrate = CONFIG_I2C_BCM2708_BAUDRATE;
 327 +module_param(baudrate, uint, S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP);
 328 +MODULE_PARM_DESC(baudrate, "The I2C baudrate");
 329 +
 330 +
 331 +struct bcm2708_i2c {
 332 +       struct i2c_adapter adapter;
 333 +
 334 +       spinlock_t lock;
 335 +       void __iomem *base;
 336 +       int irq;
 337 +       struct clk *clk;
 338 +
 339 +       struct completion done;
 340 +
 341 +       struct i2c_msg *msg;
 342 +       int pos;
 343 +       int nmsgs;
 344 +       bool error;
 345 +};
 346 +
 347 +/*
 348 + * This function sets the ALT mode on the I2C pins so that we can use them with
 349 + * the BSC hardware.
 350 + *
 351 + * FIXME: This is a hack. Use pinmux / pinctrl.
 352 + */
 353 +static void bcm2708_i2c_init_pinmode(int id)
 354 +{
 355 +#define INP_GPIO(g) *(gpio+((g)/10)) &= ~(7<<(((g)%10)*3))
 356 +#define SET_GPIO_ALT(g,a) *(gpio+(((g)/10))) |= (((a)<=3?(a)+4:(a)==4?3:2)<<(((g)%10)*3))
 357 +
 358 +       int pin;
 359 +       u32 *gpio = ioremap(GPIO_BASE, SZ_16K);
 360 +
 361 +        BUG_ON(id != 0 && id != 1);
 362 +       /* BSC0 is on GPIO 0 & 1, BSC1 is on GPIO 2 & 3 */
 363 +       for (pin = id*2+0; pin <= id*2+1; pin++) {
 364 +printk("bcm2708_i2c_init_pinmode(%d,%d)\n", id, pin);
 365 +               INP_GPIO(pin);          /* set mode to GPIO input first */
 366 +               SET_GPIO_ALT(pin, 0);   /* set mode to ALT 0 */
 367 +       }
 368 +
 369 +       iounmap(gpio);
 370 +
 371 +#undef INP_GPIO
 372 +#undef SET_GPIO_ALT
 373 +}
 374 +
 375 +static inline u32 bcm2708_rd(struct bcm2708_i2c *bi, unsigned reg)
 376 +{
 377 +       return readl(bi->base + reg);
 378 +}
 379 +
 380 +static inline void bcm2708_wr(struct bcm2708_i2c *bi, unsigned reg, u32 val)
 381 +{
 382 +       writel(val, bi->base + reg);
 383 +}
 384 +
 385 +static inline void bcm2708_bsc_reset(struct bcm2708_i2c *bi)
 386 +{
 387 +       bcm2708_wr(bi, BSC_C, 0);
 388 +       bcm2708_wr(bi, BSC_S, BSC_S_CLKT | BSC_S_ERR | BSC_S_DONE);
 389 +}
 390 +
 391 +static inline void bcm2708_bsc_fifo_drain(struct bcm2708_i2c *bi)
 392 +{
 393 +       while ((bcm2708_rd(bi, BSC_S) & BSC_S_RXD) && (bi->pos < bi->msg->len))
 394 +               bi->msg->buf[bi->pos++] = bcm2708_rd(bi, BSC_FIFO);
 395 +}
 396 +
 397 +static inline void bcm2708_bsc_fifo_fill(struct bcm2708_i2c *bi)
 398 +{
 399 +       while ((bcm2708_rd(bi, BSC_S) & BSC_S_TXD) && (bi->pos < bi->msg->len))
 400 +               bcm2708_wr(bi, BSC_FIFO, bi->msg->buf[bi->pos++]);
 401 +}
 402 +
 403 +static inline void bcm2708_bsc_setup(struct bcm2708_i2c *bi)
 404 +{
 405 +       unsigned long bus_hz;
 406 +       u32 cdiv;
 407 +       u32 c = BSC_C_I2CEN | BSC_C_INTD | BSC_C_ST | BSC_C_CLEAR_1;
 408 +
 409 +       bus_hz = clk_get_rate(bi->clk);
 410 +       cdiv = bus_hz / baudrate;
 411 +       if (cdiv > 0xffff)
 412 +               cdiv = 0xffff;
 413 +
 414 +       if (bi->msg->flags & I2C_M_RD)
 415 +               c |= BSC_C_INTR | BSC_C_READ;
 416 +       else
 417 +               c |= BSC_C_INTT;
 418 +
 419 +       bcm2708_wr(bi, BSC_DIV, cdiv);
 420 +       bcm2708_wr(bi, BSC_A, bi->msg->addr);
 421 +       bcm2708_wr(bi, BSC_DLEN, bi->msg->len);
 422 +       bcm2708_wr(bi, BSC_C, c);
 423 +}
 424 +
 425 +static irqreturn_t bcm2708_i2c_interrupt(int irq, void *dev_id)
 426 +{
 427 +       struct bcm2708_i2c *bi = dev_id;
 428 +       bool handled = true;
 429 +       u32 s;
 430 +
 431 +       spin_lock(&bi->lock);
 432 +
 433 +       /* we may see camera interrupts on the "other" I2C channel
 434 +           Just return if we've not sent anything */
 435 +        if (!bi->nmsgs || !bi->msg )
 436 +               goto early_exit;
 437 +
 438 +       s = bcm2708_rd(bi, BSC_S);
 439 +
 440 +       if (s & (BSC_S_CLKT | BSC_S_ERR)) {
 441 +               bcm2708_bsc_reset(bi);
 442 +               bi->error = true;
 443 +
 444 +               /* wake up our bh */
 445 +               complete(&bi->done);
 446 +       } else if (s & BSC_S_DONE) {
 447 +               bi->nmsgs--;
 448 +
 449 +               if (bi->msg->flags & I2C_M_RD)
 450 +                       bcm2708_bsc_fifo_drain(bi);
 451 +
 452 +               bcm2708_bsc_reset(bi);
 453 +
 454 +               if (bi->nmsgs) {
 455 +                       /* advance to next message */
 456 +                       bi->msg++;
 457 +                       bi->pos = 0;
 458 +                       bcm2708_bsc_setup(bi);
 459 +               } else {
 460 +                       /* wake up our bh */
 461 +                       complete(&bi->done);
 462 +               }
 463 +       } else if (s & BSC_S_TXW) {
 464 +               bcm2708_bsc_fifo_fill(bi);
 465 +       } else if (s & BSC_S_RXR) {
 466 +               bcm2708_bsc_fifo_drain(bi);
 467 +       } else {
 468 +               handled = false;
 469 +       }
 470 +
 471 +early_exit:
 472 +       spin_unlock(&bi->lock);
 473 +
 474 +       return handled ? IRQ_HANDLED : IRQ_NONE;
 475 +}
 476 +
 477 +static int bcm2708_i2c_master_xfer(struct i2c_adapter *adap,
 478 +       struct i2c_msg *msgs, int num)
 479 +{
 480 +       struct bcm2708_i2c *bi = adap->algo_data;
 481 +       unsigned long flags;
 482 +       int ret;
 483 +
 484 +       spin_lock_irqsave(&bi->lock, flags);
 485 +
 486 +       reinit_completion(&bi->done);
 487 +       bi->msg = msgs;
 488 +       bi->pos = 0;
 489 +       bi->nmsgs = num;
 490 +       bi->error = false;
 491 +
 492 +       bcm2708_bsc_setup(bi);
 493 +
 494 +       /* unlockig _after_ the setup to avoid races with the interrupt routine */
 495 +       spin_unlock_irqrestore(&bi->lock, flags);
 496 +
 497 +       ret = wait_for_completion_timeout(&bi->done,
 498 +                       msecs_to_jiffies(I2C_TIMEOUT_MS));
 499 +       if (ret == 0) {
 500 +               dev_err(&adap->dev, "transfer timed out\n");
 501 +               spin_lock_irqsave(&bi->lock, flags);
 502 +               bcm2708_bsc_reset(bi);
 503 +               spin_unlock_irqrestore(&bi->lock, flags);
 504 +               return -ETIMEDOUT;
 505 +       }
 506 +
 507 +       return bi->error ? -EIO : num;
 508 +}
 509 +
 510 +static u32 bcm2708_i2c_functionality(struct i2c_adapter *adap)
 511 +{
 512 +       return I2C_FUNC_I2C | /*I2C_FUNC_10BIT_ADDR |*/ I2C_FUNC_SMBUS_EMUL;
 513 +}
 514 +
 515 +static struct i2c_algorithm bcm2708_i2c_algorithm = {
 516 +       .master_xfer = bcm2708_i2c_master_xfer,
 517 +       .functionality = bcm2708_i2c_functionality,
 518 +};
 519 +
 520 +static int bcm2708_i2c_probe(struct platform_device *pdev)
 521 +{
 522 +       struct resource *regs;
 523 +       int irq, err = -ENOMEM;
 524 +       struct clk *clk;
 525 +       struct bcm2708_i2c *bi;
 526 +       struct i2c_adapter *adap;
 527 +       unsigned long bus_hz;
 528 +       u32 cdiv;
 529 +
 530 +       regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 531 +       if (!regs) {
 532 +               dev_err(&pdev->dev, "could not get IO memory\n");
 533 +               return -ENXIO;
 534 +       }
 535 +
 536 +       irq = platform_get_irq(pdev, 0);
 537 +       if (irq < 0) {
 538 +               dev_err(&pdev->dev, "could not get IRQ\n");
 539 +               return irq;
 540 +       }
 541 +
 542 +       clk = clk_get(&pdev->dev, NULL);
 543 +       if (IS_ERR(clk)) {
 544 +               dev_err(&pdev->dev, "could not find clk: %ld\n", PTR_ERR(clk));
 545 +               return PTR_ERR(clk);
 546 +       }
 547 +
 548 +       bcm2708_i2c_init_pinmode(pdev->id);
 549 +
 550 +       bi = kzalloc(sizeof(*bi), GFP_KERNEL);
 551 +       if (!bi)
 552 +               goto out_clk_put;
 553 +
 554 +       platform_set_drvdata(pdev, bi);
 555 +
 556 +       adap = &bi->adapter;
 557 +       adap->class = I2C_CLASS_HWMON | I2C_CLASS_DDC;
 558 +       adap->algo = &bcm2708_i2c_algorithm;
 559 +       adap->algo_data = bi;
 560 +       adap->dev.parent = &pdev->dev;
 561 +       adap->nr = pdev->id;
 562 +       strlcpy(adap->name, dev_name(&pdev->dev), sizeof(adap->name));
 563 +
 564 +       switch (pdev->id) {
 565 +       case 0:
 566 +               adap->class = I2C_CLASS_HWMON;
 567 +               break;
 568 +       case 1:
 569 +               adap->class = I2C_CLASS_DDC;
 570 +               break;
 571 +       default:
 572 +               dev_err(&pdev->dev, "can only bind to BSC 0 or 1\n");
 573 +               err = -ENXIO;
 574 +               goto out_free_bi;
 575 +       }
 576 +
 577 +       spin_lock_init(&bi->lock);
 578 +       init_completion(&bi->done);
 579 +
 580 +       bi->base = ioremap(regs->start, resource_size(regs));
 581 +       if (!bi->base) {
 582 +               dev_err(&pdev->dev, "could not remap memory\n");
 583 +               goto out_free_bi;
 584 +       }
 585 +
 586 +       bi->irq = irq;
 587 +       bi->clk = clk;
 588 +
 589 +       err = request_irq(irq, bcm2708_i2c_interrupt, IRQF_SHARED,
 590 +                       dev_name(&pdev->dev), bi);
 591 +       if (err) {
 592 +               dev_err(&pdev->dev, "could not request IRQ: %d\n", err);
 593 +               goto out_iounmap;
 594 +       }
 595 +
 596 +       bcm2708_bsc_reset(bi);
 597 +
 598 +       err = i2c_add_numbered_adapter(adap);
 599 +       if (err < 0) {
 600 +               dev_err(&pdev->dev, "could not add I2C adapter: %d\n", err);
 601 +               goto out_free_irq;
 602 +       }
 603 +
 604 +       bus_hz = clk_get_rate(bi->clk);
 605 +       cdiv = bus_hz / baudrate;
 606 +       if (cdiv > 0xffff) {
 607 +               cdiv = 0xffff;
 608 +               baudrate = bus_hz / cdiv;
 609 +       }
 610 +
 611 +       dev_info(&pdev->dev, "BSC%d Controller at 0x%08lx (irq %d) (baudrate %d)\n",
 612 +               pdev->id, (unsigned long)regs->start, irq, baudrate);
 613 +
 614 +       return 0;
 615 +
 616 +out_free_irq:
 617 +       free_irq(bi->irq, bi);
 618 +out_iounmap:
 619 +       iounmap(bi->base);
 620 +out_free_bi:
 621 +       kfree(bi);
 622 +out_clk_put:
 623 +       clk_put(clk);
 624 +       return err;
 625 +}
 626 +
 627 +static int bcm2708_i2c_remove(struct platform_device *pdev)
 628 +{
 629 +       struct bcm2708_i2c *bi = platform_get_drvdata(pdev);
 630 +
 631 +       platform_set_drvdata(pdev, NULL);
 632 +
 633 +       i2c_del_adapter(&bi->adapter);
 634 +       free_irq(bi->irq, bi);
 635 +       iounmap(bi->base);
 636 +       clk_disable(bi->clk);
 637 +       clk_put(bi->clk);
 638 +       kfree(bi);
 639 +
 640 +       return 0;
 641 +}
 642 +
 643 +static struct platform_driver bcm2708_i2c_driver = {
 644 +       .driver         = {
 645 +               .name   = DRV_NAME,
 646 +               .owner  = THIS_MODULE,
 647 +       },
 648 +       .probe          = bcm2708_i2c_probe,
 649 +       .remove         = bcm2708_i2c_remove,
 650 +};
 651 +
 652 +// module_platform_driver(bcm2708_i2c_driver);
 653 +
 654 +
 655 +static int __init bcm2708_i2c_init(void)
 656 +{
 657 +       return platform_driver_register(&bcm2708_i2c_driver);
 658 +}
 659 +
 660 +static void __exit bcm2708_i2c_exit(void)
 661 +{
 662 +       platform_driver_unregister(&bcm2708_i2c_driver);
 663 +}
 664 +
 665 +module_init(bcm2708_i2c_init);
 666 +module_exit(bcm2708_i2c_exit);
 667 +
 668 +
 669 +
 670 +MODULE_DESCRIPTION("BSC controller driver for Broadcom BCM2708");
 671 +MODULE_AUTHOR("Chris Boot <bootc@bootc.net>");
 672 +MODULE_LICENSE("GPL v2");
 673 +MODULE_ALIAS("platform:" DRV_NAME);
 674 --- a/drivers/spi/Kconfig
 675 +++ b/drivers/spi/Kconfig
 676 @@ -86,6 +86,14 @@ config SPI_BCM2835
 677           is for the regular SPI controller. Slave mode operation is not also
 678           not supported.
 679
 680 +config SPI_BCM2708
 681 +       tristate "BCM2708 SPI controller driver (SPI0)"
 682 +       depends on MACH_BCM2708
 683 +       help
 684 +         This selects a driver for the Broadcom BCM2708 SPI master (SPI0). This
 685 +         driver is not compatible with the "Universal SPI Master" or the SPI slave
 686 +         device.
 687 +
 688  config SPI_BFIN5XX
 689         tristate "SPI controller driver for ADI Blackfin5xx"
 690         depends on BLACKFIN && !BF60x
 691 --- a/drivers/spi/Makefile
 692 +++ b/drivers/spi/Makefile
 693 @@ -20,6 +20,7 @@ obj-$(CONFIG_SPI_BCM63XX)             += spi-bcm63x
 694  obj-$(CONFIG_SPI_BCM63XX_HSSPI)                += spi-bcm63xx-hsspi.o
 695  obj-$(CONFIG_SPI_BFIN5XX)              += spi-bfin5xx.o
 696  obj-$(CONFIG_SPI_ADI_V3)                += spi-adi-v3.o
 697 +obj-$(CONFIG_SPI_BCM2708)              += spi-bcm2708.o
 698  obj-$(CONFIG_SPI_BFIN_SPORT)           += spi-bfin-sport.o
 699  obj-$(CONFIG_SPI_BITBANG)              += spi-bitbang.o
 700  obj-$(CONFIG_SPI_BUTTERFLY)            += spi-butterfly.o
 701 --- /dev/null
 702 +++ b/drivers/spi/spi-bcm2708.c
 703 @@ -0,0 +1,626 @@
 704 +/*
 705 + * Driver for Broadcom BCM2708 SPI Controllers
 706 + *
 707 + * Copyright (C) 2012 Chris Boot
 708 + *
 709 + * This driver is inspired by:
 710 + * spi-ath79.c, Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
 711 + * spi-atmel.c, Copyright (C) 2006 Atmel Corporation
 712 + *
 713 + * This program is free software; you can redistribute it and/or modify
 714 + * it under the terms of the GNU General Public License as published by
 715 + * the Free Software Foundation; either version 2 of the License, or
 716 + * (at your option) any later version.
 717 + *
 718 + * This program is distributed in the hope that it will be useful,
 719 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 720 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 721 + * GNU General Public License for more details.
 722 + *
 723 + * You should have received a copy of the GNU General Public License
 724 + * along with this program; if not, write to the Free Software
 725 + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 726 + */
 727 +
 728 +#include <linux/kernel.h>
 729 +#include <linux/module.h>
 730 +#include <linux/spinlock.h>
 731 +#include <linux/clk.h>
 732 +#include <linux/err.h>
 733 +#include <linux/platform_device.h>
 734 +#include <linux/io.h>
 735 +#include <linux/spi/spi.h>
 736 +#include <linux/interrupt.h>
 737 +#include <linux/delay.h>
 738 +#include <linux/log2.h>
 739 +#include <linux/sched.h>
 740 +#include <linux/wait.h>
 741 +
 742 +/* SPI register offsets */
 743 +#define SPI_CS                 0x00
 744 +#define SPI_FIFO               0x04
 745 +#define SPI_CLK                        0x08
 746 +#define SPI_DLEN               0x0c
 747 +#define SPI_LTOH               0x10
 748 +#define SPI_DC                 0x14
 749 +
 750 +/* Bitfields in CS */
 751 +#define SPI_CS_LEN_LONG                0x02000000
 752 +#define SPI_CS_DMA_LEN         0x01000000
 753 +#define SPI_CS_CSPOL2          0x00800000
 754 +#define SPI_CS_CSPOL1          0x00400000
 755 +#define SPI_CS_CSPOL0          0x00200000
 756 +#define SPI_CS_RXF             0x00100000
 757 +#define SPI_CS_RXR             0x00080000
 758 +#define SPI_CS_TXD             0x00040000
 759 +#define SPI_CS_RXD             0x00020000
 760 +#define SPI_CS_DONE            0x00010000
 761 +#define SPI_CS_LEN             0x00002000
 762 +#define SPI_CS_REN             0x00001000
 763 +#define SPI_CS_ADCS            0x00000800
 764 +#define SPI_CS_INTR            0x00000400
 765 +#define SPI_CS_INTD            0x00000200
 766 +#define SPI_CS_DMAEN           0x00000100
 767 +#define SPI_CS_TA              0x00000080
 768 +#define SPI_CS_CSPOL           0x00000040
 769 +#define SPI_CS_CLEAR_RX                0x00000020
 770 +#define SPI_CS_CLEAR_TX                0x00000010
 771 +#define SPI_CS_CPOL            0x00000008
 772 +#define SPI_CS_CPHA            0x00000004
 773 +#define SPI_CS_CS_10           0x00000002
 774 +#define SPI_CS_CS_01           0x00000001
 775 +
 776 +#define SPI_TIMEOUT_MS 150
 777 +
 778 +#define DRV_NAME       "bcm2708_spi"
 779 +
 780 +struct bcm2708_spi {
 781 +       spinlock_t lock;
 782 +       void __iomem *base;
 783 +       int irq;
 784 +       struct clk *clk;
 785 +       bool stopping;
 786 +
 787 +       struct list_head queue;
 788 +       struct workqueue_struct *workq;
 789 +       struct work_struct work;
 790 +       struct completion done;
 791 +
 792 +       const u8 *tx_buf;
 793 +       u8 *rx_buf;
 794 +       int len;
 795 +};
 796 +
 797 +struct bcm2708_spi_state {
 798 +       u32 cs;
 799 +       u16 cdiv;
 800 +};
 801 +
 802 +/*
 803 + * This function sets the ALT mode on the SPI pins so that we can use them with
 804 + * the SPI hardware.
 805 + *
 806 + * FIXME: This is a hack. Use pinmux / pinctrl.
 807 + */
 808 +static void bcm2708_init_pinmode(void)
 809 +{
 810 +#define INP_GPIO(g) *(gpio+((g)/10)) &= ~(7<<(((g)%10)*3))
 811 +#define SET_GPIO_ALT(g,a) *(gpio+(((g)/10))) |= (((a)<=3?(a)+4:(a)==4?3:2)<<(((g)%10)*3))
 812 +
 813 +       int pin;
 814 +       u32 *gpio = ioremap(GPIO_BASE, SZ_16K);
 815 +
 816 +       /* SPI is on GPIO 7..11 */
 817 +       for (pin = 7; pin <= 11; pin++) {
 818 +               INP_GPIO(pin);          /* set mode to GPIO input first */
 819 +               SET_GPIO_ALT(pin, 0);   /* set mode to ALT 0 */
 820 +       }
 821 +
 822 +       iounmap(gpio);
 823 +
 824 +#undef INP_GPIO
 825 +#undef SET_GPIO_ALT
 826 +}
 827 +
 828 +static inline u32 bcm2708_rd(struct bcm2708_spi *bs, unsigned reg)
 829 +{
 830 +       return readl(bs->base + reg);
 831 +}
 832 +
 833 +static inline void bcm2708_wr(struct bcm2708_spi *bs, unsigned reg, u32 val)
 834 +{
 835 +       writel(val, bs->base + reg);
 836 +}
 837 +
 838 +static inline void bcm2708_rd_fifo(struct bcm2708_spi *bs, int len)
 839 +{
 840 +       u8 byte;
 841 +
 842 +       while (len--) {
 843 +               byte = bcm2708_rd(bs, SPI_FIFO);
 844 +               if (bs->rx_buf)
 845 +                       *bs->rx_buf++ = byte;
 846 +       }
 847 +}
 848 +
 849 +static inline void bcm2708_wr_fifo(struct bcm2708_spi *bs, int len)
 850 +{
 851 +       u8 byte;
 852 +       u16 val;
 853 +
 854 +       if (len > bs->len)
 855 +               len = bs->len;
 856 +
 857 +       if (unlikely(bcm2708_rd(bs, SPI_CS) & SPI_CS_LEN)) {
 858 +               /* LoSSI mode */
 859 +               if (unlikely(len % 2)) {
 860 +                       printk(KERN_ERR"bcm2708_wr_fifo: length must be even, skipping.\n");
 861 +                       bs->len = 0;
 862 +                       return;
 863 +               }
 864 +               while (len) {
 865 +                       if (bs->tx_buf) {
 866 +                               val = *(const u16 *)bs->tx_buf;
 867 +                               bs->tx_buf += 2;
 868 +                       } else
 869 +                               val = 0;
 870 +                       bcm2708_wr(bs, SPI_FIFO, val);
 871 +                       bs->len -= 2;
 872 +                       len -= 2;
 873 +               }
 874 +               return;
 875 +       }
 876 +
 877 +       while (len--) {
 878 +               byte = bs->tx_buf ? *bs->tx_buf++ : 0;
 879 +               bcm2708_wr(bs, SPI_FIFO, byte);
 880 +               bs->len--;
 881 +       }
 882 +}
 883 +
 884 +static irqreturn_t bcm2708_spi_interrupt(int irq, void *dev_id)
 885 +{
 886 +       struct spi_master *master = dev_id;
 887 +       struct bcm2708_spi *bs = spi_master_get_devdata(master);
 888 +       u32 cs;
 889 +
 890 +       spin_lock(&bs->lock);
 891 +
 892 +       cs = bcm2708_rd(bs, SPI_CS);
 893 +
 894 +       if (cs & SPI_CS_DONE) {
 895 +               if (bs->len) { /* first interrupt in a transfer */
 896 +                       /* fill the TX fifo with up to 16 bytes */
 897 +                       bcm2708_wr_fifo(bs, 16);
 898 +               } else { /* transfer complete */
 899 +                       /* disable interrupts */
 900 +                       cs &= ~(SPI_CS_INTR | SPI_CS_INTD);
 901 +                       bcm2708_wr(bs, SPI_CS, cs);
 902 +
 903 +                       /* drain RX FIFO */
 904 +                       while (cs & SPI_CS_RXD) {
 905 +                               bcm2708_rd_fifo(bs, 1);
 906 +                               cs = bcm2708_rd(bs, SPI_CS);
 907 +                       }
 908 +
 909 +                       /* wake up our bh */
 910 +                       complete(&bs->done);
 911 +               }
 912 +       } else if (cs & SPI_CS_RXR) {
 913 +               /* read 12 bytes of data */
 914 +               bcm2708_rd_fifo(bs, 12);
 915 +
 916 +               /* write up to 12 bytes */
 917 +               bcm2708_wr_fifo(bs, 12);
 918 +       }
 919 +
 920 +       spin_unlock(&bs->lock);
 921 +
 922 +       return IRQ_HANDLED;
 923 +}
 924 +
 925 +static int bcm2708_setup_state(struct spi_master *master,
 926 +               struct device *dev, struct bcm2708_spi_state *state,
 927 +               u32 hz, u8 csel, u8 mode, u8 bpw)
 928 +{
 929 +       struct bcm2708_spi *bs = spi_master_get_devdata(master);
 930 +       int cdiv;
 931 +       unsigned long bus_hz;
 932 +       u32 cs = 0;
 933 +
 934 +       bus_hz = clk_get_rate(bs->clk);
 935 +
 936 +       if (hz >= bus_hz) {
 937 +               cdiv = 2; /* bus_hz / 2 is as fast as we can go */
 938 +       } else if (hz) {
 939 +               cdiv = DIV_ROUND_UP(bus_hz, hz);
 940 +
 941 +               /* CDIV must be a power of 2, so round up */
 942 +               cdiv = roundup_pow_of_two(cdiv);
 943 +
 944 +               if (cdiv > 65536) {
 945 +                       dev_dbg(dev,
 946 +                               "setup: %d Hz too slow, cdiv %u; min %ld Hz\n",
 947 +                               hz, cdiv, bus_hz / 65536);
 948 +                       return -EINVAL;
 949 +               } else if (cdiv == 65536) {
 950 +                       cdiv = 0;
 951 +               } else if (cdiv == 1) {
 952 +                       cdiv = 2; /* 1 gets rounded down to 0; == 65536 */
 953 +               }
 954 +       } else {
 955 +               cdiv = 0;
 956 +       }
 957 +
 958 +       switch (bpw) {
 959 +       case 8:
 960 +               break;
 961 +       case 9:
 962 +               /* Reading in LoSSI mode is a special case. See 'BCM2835 ARM Peripherals' datasheet */
 963 +               cs |= SPI_CS_LEN;
 964 +               break;
 965 +       default:
 966 +               dev_dbg(dev, "setup: invalid bits_per_word %u (must be 8 or 9)\n",
 967 +                       bpw);
 968 +               return -EINVAL;
 969 +       }
 970 +
 971 +       if (mode & SPI_CPOL)
 972 +               cs |= SPI_CS_CPOL;
 973 +       if (mode & SPI_CPHA)
 974 +               cs |= SPI_CS_CPHA;
 975 +
 976 +       if (!(mode & SPI_NO_CS)) {
 977 +               if (mode & SPI_CS_HIGH) {
 978 +                       cs |= SPI_CS_CSPOL;
 979 +                       cs |= SPI_CS_CSPOL0 << csel;
 980 +               }
 981 +
 982 +               cs |= csel;
 983 +       } else {
 984 +               cs |= SPI_CS_CS_10 | SPI_CS_CS_01;
 985 +       }
 986 +
 987 +       if (state) {
 988 +               state->cs = cs;
 989 +               state->cdiv = cdiv;
 990 +               dev_dbg(dev, "setup: want %d Hz; "
 991 +                       "bus_hz=%lu / cdiv=%u == %lu Hz; "
 992 +                       "mode %u: cs 0x%08X\n",
 993 +                       hz, bus_hz, cdiv, bus_hz/cdiv, mode, cs);
 994 +       }
 995 +
 996 +       return 0;
 997 +}
 998 +
 999 +static int bcm2708_process_transfer(struct bcm2708_spi *bs,
1000 +               struct spi_message *msg, struct spi_transfer *xfer)
1001 +{
1002 +       struct spi_device *spi = msg->spi;
1003 +       struct bcm2708_spi_state state, *stp;
1004 +       int ret;
1005 +       u32 cs;
1006 +
1007 +       if (bs->stopping)
1008 +               return -ESHUTDOWN;
1009 +
1010 +       if (xfer->bits_per_word || xfer->speed_hz) {
1011 +               ret = bcm2708_setup_state(spi->master, &spi->dev, &state,
1012 +                       xfer->speed_hz ? xfer->speed_hz : spi->max_speed_hz,
1013 +                       spi->chip_select, spi->mode,
1014 +                       xfer->bits_per_word ? xfer->bits_per_word :
1015 +                               spi->bits_per_word);
1016 +               if (ret)
1017 +                       return ret;
1018 +
1019 +               stp = &state;
1020 +       } else {
1021 +               stp = spi->controller_state;
1022 +       }
1023 +
1024 +       reinit_completion(&bs->done);
1025 +       bs->tx_buf = xfer->tx_buf;
1026 +       bs->rx_buf = xfer->rx_buf;
1027 +       bs->len = xfer->len;
1028 +
1029 +       cs = stp->cs | SPI_CS_INTR | SPI_CS_INTD | SPI_CS_TA;
1030 +
1031 +       bcm2708_wr(bs, SPI_CLK, stp->cdiv);
1032 +       bcm2708_wr(bs, SPI_CS, cs);
1033 +
1034 +       ret = wait_for_completion_timeout(&bs->done,
1035 +                       msecs_to_jiffies(SPI_TIMEOUT_MS));
1036 +       if (ret == 0) {
1037 +               dev_err(&spi->dev, "transfer timed out\n");
1038 +               return -ETIMEDOUT;
1039 +       }
1040 +
1041 +       if (xfer->delay_usecs)
1042 +               udelay(xfer->delay_usecs);
1043 +
1044 +       if (list_is_last(&xfer->transfer_list, &msg->transfers) ||
1045 +                       xfer->cs_change) {
1046 +               /* clear TA and interrupt flags */
1047 +               bcm2708_wr(bs, SPI_CS, stp->cs);
1048 +       }
1049 +
1050 +       msg->actual_length += (xfer->len - bs->len);
1051 +
1052 +       return 0;
1053 +}
1054 +
1055 +static void bcm2708_work(struct work_struct *work)
1056 +{
1057 +       struct bcm2708_spi *bs = container_of(work, struct bcm2708_spi, work);
1058 +       unsigned long flags;
1059 +       struct spi_message *msg;
1060 +       struct spi_transfer *xfer;
1061 +       int status = 0;
1062 +
1063 +       spin_lock_irqsave(&bs->lock, flags);
1064 +       while (!list_empty(&bs->queue)) {
1065 +               msg = list_first_entry(&bs->queue, struct spi_message, queue);
1066 +               list_del_init(&msg->queue);
1067 +               spin_unlock_irqrestore(&bs->lock, flags);
1068 +
1069 +               list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1070 +                       status = bcm2708_process_transfer(bs, msg, xfer);
1071 +                       if (status)
1072 +                               break;
1073 +               }
1074 +
1075 +               msg->status = status;
1076 +               msg->complete(msg->context);
1077 +
1078 +               spin_lock_irqsave(&bs->lock, flags);
1079 +       }
1080 +       spin_unlock_irqrestore(&bs->lock, flags);
1081 +}
1082 +
1083 +static int bcm2708_spi_setup(struct spi_device *spi)
1084 +{
1085 +       struct bcm2708_spi *bs = spi_master_get_devdata(spi->master);
1086 +       struct bcm2708_spi_state *state;
1087 +       int ret;
1088 +
1089 +       if (bs->stopping)
1090 +               return -ESHUTDOWN;
1091 +
1092 +       if (!(spi->mode & SPI_NO_CS) &&
1093 +                       (spi->chip_select > spi->master->num_chipselect)) {
1094 +               dev_dbg(&spi->dev,
1095 +                       "setup: invalid chipselect %u (%u defined)\n",
1096 +                       spi->chip_select, spi->master->num_chipselect);
1097 +               return -EINVAL;
1098 +       }
1099 +
1100 +       state = spi->controller_state;
1101 +       if (!state) {
1102 +               state = kzalloc(sizeof(*state), GFP_KERNEL);
1103 +               if (!state)
1104 +                       return -ENOMEM;
1105 +
1106 +               spi->controller_state = state;
1107 +       }
1108 +
1109 +       ret = bcm2708_setup_state(spi->master, &spi->dev, state,
1110 +               spi->max_speed_hz, spi->chip_select, spi->mode,
1111 +               spi->bits_per_word);
1112 +       if (ret < 0) {
1113 +               kfree(state);
1114 +               spi->controller_state = NULL;
1115 +                return ret;
1116 +       }
1117 +
1118 +       dev_dbg(&spi->dev,
1119 +               "setup: cd %d: %d Hz, bpw %u, mode 0x%x -> CS=%08x CDIV=%04x\n",
1120 +               spi->chip_select, spi->max_speed_hz, spi->bits_per_word,
1121 +               spi->mode, state->cs, state->cdiv);
1122 +
1123 +       return 0;
1124 +}
1125 +
1126 +static int bcm2708_spi_transfer(struct spi_device *spi, struct spi_message *msg)
1127 +{
1128 +       struct bcm2708_spi *bs = spi_master_get_devdata(spi->master);
1129 +       struct spi_transfer *xfer;
1130 +       int ret;
1131 +       unsigned long flags;
1132 +
1133 +       if (unlikely(list_empty(&msg->transfers)))
1134 +               return -EINVAL;
1135 +
1136 +       if (bs->stopping)
1137 +               return -ESHUTDOWN;
1138 +
1139 +       list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1140 +               if (!(xfer->tx_buf || xfer->rx_buf) && xfer->len) {
1141 +                       dev_dbg(&spi->dev, "missing rx or tx buf\n");
1142 +                       return -EINVAL;
1143 +               }
1144 +
1145 +               if (!xfer->bits_per_word || xfer->speed_hz)
1146 +                       continue;
1147 +
1148 +               ret = bcm2708_setup_state(spi->master, &spi->dev, NULL,
1149 +                       xfer->speed_hz ? xfer->speed_hz : spi->max_speed_hz,
1150 +                       spi->chip_select, spi->mode,
1151 +                       xfer->bits_per_word ? xfer->bits_per_word :
1152 +                               spi->bits_per_word);
1153 +               if (ret)
1154 +                       return ret;
1155 +       }
1156 +
1157 +       msg->status = -EINPROGRESS;
1158 +       msg->actual_length = 0;
1159 +
1160 +       spin_lock_irqsave(&bs->lock, flags);
1161 +       list_add_tail(&msg->queue, &bs->queue);
1162 +       queue_work(bs->workq, &bs->work);
1163 +       spin_unlock_irqrestore(&bs->lock, flags);
1164 +
1165 +       return 0;
1166 +}
1167 +
1168 +static void bcm2708_spi_cleanup(struct spi_device *spi)
1169 +{
1170 +       if (spi->controller_state) {
1171 +               kfree(spi->controller_state);
1172 +               spi->controller_state = NULL;
1173 +       }
1174 +}
1175 +
1176 +static int bcm2708_spi_probe(struct platform_device *pdev)
1177 +{
1178 +       struct resource *regs;
1179 +       int irq, err = -ENOMEM;
1180 +       struct clk *clk;
1181 +       struct spi_master *master;
1182 +       struct bcm2708_spi *bs;
1183 +
1184 +       regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1185 +       if (!regs) {
1186 +               dev_err(&pdev->dev, "could not get IO memory\n");
1187 +               return -ENXIO;
1188 +       }
1189 +
1190 +       irq = platform_get_irq(pdev, 0);
1191 +       if (irq < 0) {
1192 +               dev_err(&pdev->dev, "could not get IRQ\n");
1193 +               return irq;
1194 +       }
1195 +
1196 +       clk = clk_get(&pdev->dev, NULL);
1197 +       if (IS_ERR(clk)) {
1198 +               dev_err(&pdev->dev, "could not find clk: %ld\n", PTR_ERR(clk));
1199 +               return PTR_ERR(clk);
1200 +       }
1201 +
1202 +       bcm2708_init_pinmode();
1203 +
1204 +       master = spi_alloc_master(&pdev->dev, sizeof(*bs));
1205 +       if (!master) {
1206 +               dev_err(&pdev->dev, "spi_alloc_master() failed\n");
1207 +               goto out_clk_put;
1208 +       }
1209 +
1210 +       /* the spi->mode bits understood by this driver: */
1211 +       master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_NO_CS;
1212 +
1213 +       master->bus_num = pdev->id;
1214 +       master->num_chipselect = 3;
1215 +       master->setup = bcm2708_spi_setup;
1216 +       master->transfer = bcm2708_spi_transfer;
1217 +       master->cleanup = bcm2708_spi_cleanup;
1218 +       platform_set_drvdata(pdev, master);
1219 +
1220 +       bs = spi_master_get_devdata(master);
1221 +
1222 +       spin_lock_init(&bs->lock);
1223 +       INIT_LIST_HEAD(&bs->queue);
1224 +       init_completion(&bs->done);
1225 +       INIT_WORK(&bs->work, bcm2708_work);
1226 +
1227 +       bs->base = ioremap(regs->start, resource_size(regs));
1228 +       if (!bs->base) {
1229 +               dev_err(&pdev->dev, "could not remap memory\n");
1230 +               goto out_master_put;
1231 +       }
1232 +
1233 +       bs->workq = create_singlethread_workqueue(dev_name(&pdev->dev));
1234 +       if (!bs->workq) {
1235 +               dev_err(&pdev->dev, "could not create workqueue\n");
1236 +               goto out_iounmap;
1237 +       }
1238 +
1239 +       bs->irq = irq;
1240 +       bs->clk = clk;
1241 +       bs->stopping = false;
1242 +
1243 +       err = request_irq(irq, bcm2708_spi_interrupt, 0, dev_name(&pdev->dev),
1244 +                       master);
1245 +       if (err) {
1246 +               dev_err(&pdev->dev, "could not request IRQ: %d\n", err);
1247 +               goto out_workqueue;
1248 +       }
1249 +
1250 +       /* initialise the hardware */
1251 +       clk_enable(clk);
1252 +       bcm2708_wr(bs, SPI_CS, SPI_CS_REN | SPI_CS_CLEAR_RX | SPI_CS_CLEAR_TX);
1253 +
1254 +       err = spi_register_master(master);
1255 +       if (err) {
1256 +               dev_err(&pdev->dev, "could not register SPI master: %d\n", err);
1257 +               goto out_free_irq;
1258 +       }
1259 +
1260 +       dev_info(&pdev->dev, "SPI Controller at 0x%08lx (irq %d)\n",
1261 +               (unsigned long)regs->start, irq);
1262 +
1263 +       return 0;
1264 +
1265 +out_free_irq:
1266 +       free_irq(bs->irq, master);
1267 +out_workqueue:
1268 +       destroy_workqueue(bs->workq);
1269 +out_iounmap:
1270 +       iounmap(bs->base);
1271 +out_master_put:
1272 +       spi_master_put(master);
1273 +out_clk_put:
1274 +       clk_put(clk);
1275 +       return err;
1276 +}
1277 +
1278 +static int bcm2708_spi_remove(struct platform_device *pdev)
1279 +{
1280 +       struct spi_master *master = platform_get_drvdata(pdev);
1281 +       struct bcm2708_spi *bs = spi_master_get_devdata(master);
1282 +
1283 +       /* reset the hardware and block queue progress */
1284 +       spin_lock_irq(&bs->lock);
1285 +       bs->stopping = true;
1286 +       bcm2708_wr(bs, SPI_CS, SPI_CS_CLEAR_RX | SPI_CS_CLEAR_TX);
1287 +       spin_unlock_irq(&bs->lock);
1288 +
1289 +       flush_work(&bs->work);
1290 +
1291 +       clk_disable(bs->clk);
1292 +       clk_put(bs->clk);
1293 +       free_irq(bs->irq, master);
1294 +       iounmap(bs->base);
1295 +
1296 +       spi_unregister_master(master);
1297 +
1298 +       return 0;
1299 +}
1300 +
1301 +static struct platform_driver bcm2708_spi_driver = {
1302 +       .driver         = {
1303 +               .name   = DRV_NAME,
1304 +               .owner  = THIS_MODULE,
1305 +       },
1306 +       .probe          = bcm2708_spi_probe,
1307 +       .remove         = bcm2708_spi_remove,
1308 +};
1309 +
1310 +
1311 +static int __init bcm2708_spi_init(void)
1312 +{
1313 +       return platform_driver_probe(&bcm2708_spi_driver, bcm2708_spi_probe);
1314 +}
1315 +module_init(bcm2708_spi_init);
1316 +
1317 +static void __exit bcm2708_spi_exit(void)
1318 +{
1319 +       platform_driver_unregister(&bcm2708_spi_driver);
1320 +}
1321 +module_exit(bcm2708_spi_exit);
1322 +
1323 +
1324 +//module_platform_driver(bcm2708_spi_driver);
1325 +
1326 +MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2708");
1327 +MODULE_AUTHOR("Chris Boot <bootc@bootc.net>");
1328 +MODULE_LICENSE("GPL v2");
1329 +MODULE_ALIAS("platform:" DRV_NAME);