target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c

   1 /*
   2  *  Atheros AR71xx SoC platform devices
   3  *
   4  *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
   5  *  Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
   6  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   7  *
   8  *  Parts of this file are based on Atheros 2.6.15 BSP
   9  *  Parts of this file are based on Atheros 2.6.31 BSP
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License version 2 as published
  13  *  by the Free Software Foundation.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/delay.h>
  19 #include <linux/etherdevice.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/serial_8250.h>
  22 #include <linux/clk.h>
  23 #include <linux/sizes.h>
  24
  25 #include <asm/mach-ath79/ath79.h>
  26 #include <asm/mach-ath79/ar71xx_regs.h>
  27 #include <asm/mach-ath79/irq.h>
  28
  29 #include "common.h"
  30 #include "dev-eth.h"
  31
  32 unsigned char ath79_mac_base[ETH_ALEN] __initdata;
  33
  34 static struct resource ath79_mdio0_resources[] = {
  35         {
  36                 .name   = "mdio_base",
  37                 .flags  = IORESOURCE_MEM,
  38                 .start  = AR71XX_GE0_BASE,
  39                 .end    = AR71XX_GE0_BASE + 0x200 - 1,
  40         }
  41 };
  42
  43 struct ag71xx_mdio_platform_data ath79_mdio0_data;
  44
  45 struct platform_device ath79_mdio0_device = {
  46         .name           = "ag71xx-mdio",
  47         .id             = 0,
  48         .resource       = ath79_mdio0_resources,
  49         .num_resources  = ARRAY_SIZE(ath79_mdio0_resources),
  50         .dev = {
  51                 .platform_data = &ath79_mdio0_data,
  52         },
  53 };
  54
  55 static struct resource ath79_mdio1_resources[] = {
  56         {
  57                 .name   = "mdio_base",
  58                 .flags  = IORESOURCE_MEM,
  59                 .start  = AR71XX_GE1_BASE,
  60                 .end    = AR71XX_GE1_BASE + 0x200 - 1,
  61         }
  62 };
  63
  64 struct ag71xx_mdio_platform_data ath79_mdio1_data;
  65
  66 struct platform_device ath79_mdio1_device = {
  67         .name           = "ag71xx-mdio",
  68         .id             = 1,
  69         .resource       = ath79_mdio1_resources,
  70         .num_resources  = ARRAY_SIZE(ath79_mdio1_resources),
  71         .dev = {
  72                 .platform_data = &ath79_mdio1_data,
  73         },
  74 };
  75
  76 static void ath79_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift)
  77 {
  78         void __iomem *base;
  79         u32 t;
  80
  81         base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
  82
  83         t = __raw_readl(base + cfg_reg);
  84         t &= ~(3 << shift);
  85         t |=  (2 << shift);
  86         __raw_writel(t, base + cfg_reg);
  87         udelay(100);
  88
  89         __raw_writel(pll_val, base + pll_reg);
  90
  91         t |= (3 << shift);
  92         __raw_writel(t, base + cfg_reg);
  93         udelay(100);
  94
  95         t &= ~(3 << shift);
  96         __raw_writel(t, base + cfg_reg);
  97         udelay(100);
  98
  99         printk(KERN_DEBUG "ar71xx: pll_reg %#x: %#x\n",
 100                 (unsigned int)(base + pll_reg), __raw_readl(base + pll_reg));
 101
 102         iounmap(base);
 103 }
 104
 105 static void __init ath79_mii_ctrl_set_if(unsigned int reg,
 106                                           unsigned int mii_if)
 107 {
 108         void __iomem *base;
 109         u32 t;
 110
 111         base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
 112
 113         t = __raw_readl(base + reg);
 114         t &= ~(AR71XX_MII_CTRL_IF_MASK);
 115         t |= (mii_if & AR71XX_MII_CTRL_IF_MASK);
 116         __raw_writel(t, base + reg);
 117
 118         iounmap(base);
 119 }
 120
 121 static void ath79_mii_ctrl_set_speed(unsigned int reg, unsigned int speed)
 122 {
 123         void __iomem *base;
 124         unsigned int mii_speed;
 125         u32 t;
 126
 127         switch (speed) {
 128         case SPEED_10:
 129                 mii_speed =  AR71XX_MII_CTRL_SPEED_10;
 130                 break;
 131         case SPEED_100:
 132                 mii_speed =  AR71XX_MII_CTRL_SPEED_100;
 133                 break;
 134         case SPEED_1000:
 135                 mii_speed =  AR71XX_MII_CTRL_SPEED_1000;
 136                 break;
 137         default:
 138                 BUG();
 139         }
 140
 141         base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
 142
 143         t = __raw_readl(base + reg);
 144         t &= ~(AR71XX_MII_CTRL_SPEED_MASK << AR71XX_MII_CTRL_SPEED_SHIFT);
 145         t |= mii_speed  << AR71XX_MII_CTRL_SPEED_SHIFT;
 146         __raw_writel(t, base + reg);
 147
 148         iounmap(base);
 149 }
 150
 151 static unsigned long ar934x_get_mdio_ref_clock(void)
 152 {
 153         void __iomem *base;
 154         unsigned long ret;
 155         u32 t;
 156
 157         base = ioremap(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
 158
 159         ret = 0;
 160         t = __raw_readl(base + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
 161         if (t & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL) {
 162                 ret = 100 * 1000 * 1000;
 163         } else {
 164                 struct clk *clk;
 165
 166                 clk = clk_get(NULL, "ref");
 167                 if (!IS_ERR(clk))
 168                         ret = clk_get_rate(clk);
 169         }
 170
 171         iounmap(base);
 172
 173         return ret;
 174 }
 175
 176 void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
 177 {
 178         struct platform_device *mdio_dev;
 179         struct ag71xx_mdio_platform_data *mdio_data;
 180         unsigned int max_id;
 181
 182         if (ath79_soc == ATH79_SOC_AR9341 ||
 183             ath79_soc == ATH79_SOC_AR9342 ||
 184             ath79_soc == ATH79_SOC_AR9344 ||
 185             ath79_soc == ATH79_SOC_QCA9556 ||
 186             ath79_soc == ATH79_SOC_QCA9558)
 187                 max_id = 1;
 188         else
 189                 max_id = 0;
 190
 191         if (id > max_id) {
 192                 printk(KERN_ERR "ar71xx: invalid MDIO id %u\n", id);
 193                 return;
 194         }
 195
 196         switch (ath79_soc) {
 197         case ATH79_SOC_AR7241:
 198         case ATH79_SOC_AR9330:
 199         case ATH79_SOC_AR9331:
 200         case ATH79_SOC_QCA9533:
 201         case ATH79_SOC_QCA9561:
 202         case ATH79_SOC_TP9343:
 203                 mdio_dev = &ath79_mdio1_device;
 204                 mdio_data = &ath79_mdio1_data;
 205                 break;
 206
 207         case ATH79_SOC_AR9341:
 208         case ATH79_SOC_AR9342:
 209         case ATH79_SOC_AR9344:
 210         case ATH79_SOC_QCA9556:
 211         case ATH79_SOC_QCA9558:
 212                 if (id == 0) {
 213                         mdio_dev = &ath79_mdio0_device;
 214                         mdio_data = &ath79_mdio0_data;
 215                 } else {
 216                         mdio_dev = &ath79_mdio1_device;
 217                         mdio_data = &ath79_mdio1_data;
 218                 }
 219                 break;
 220
 221         case ATH79_SOC_AR7242:
 222                 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG,
 223                                AR7242_PLL_REG_ETH0_INT_CLOCK, 0x62000000,
 224                                AR71XX_ETH0_PLL_SHIFT);
 225                 /* fall through */
 226         default:
 227                 mdio_dev = &ath79_mdio0_device;
 228                 mdio_data = &ath79_mdio0_data;
 229                 break;
 230         }
 231
 232         mdio_data->phy_mask = phy_mask;
 233
 234         switch (ath79_soc) {
 235         case ATH79_SOC_AR7240:
 236                 mdio_data->is_ar7240 = 1;
 237                 /* fall through */
 238         case ATH79_SOC_AR7241:
 239                 mdio_data->builtin_switch = 1;
 240                 break;
 241
 242         case ATH79_SOC_AR9330:
 243                 mdio_data->is_ar9330 = 1;
 244                 /* fall through */
 245         case ATH79_SOC_AR9331:
 246                 mdio_data->builtin_switch = 1;
 247                 break;
 248
 249         case ATH79_SOC_AR9341:
 250         case ATH79_SOC_AR9342:
 251         case ATH79_SOC_AR9344:
 252                 if (id == 1) {
 253                         mdio_data->builtin_switch = 1;
 254                         mdio_data->ref_clock = ar934x_get_mdio_ref_clock();
 255                         mdio_data->mdio_clock = 6250000;
 256                 }
 257                 mdio_data->is_ar934x = 1;
 258                 break;
 259
 260         case ATH79_SOC_QCA9533:
 261         case ATH79_SOC_QCA9561:
 262         case ATH79_SOC_TP9343:
 263                 mdio_data->builtin_switch = 1;
 264                 break;
 265
 266         case ATH79_SOC_QCA9556:
 267         case ATH79_SOC_QCA9558:
 268                 mdio_data->is_ar934x = 1;
 269                 break;
 270
 271         default:
 272                 break;
 273         }
 274
 275         platform_device_register(mdio_dev);
 276 }
 277
 278 struct ath79_eth_pll_data ath79_eth0_pll_data;
 279 struct ath79_eth_pll_data ath79_eth1_pll_data;
 280
 281 static u32 ath79_get_eth_pll(unsigned int mac, int speed)
 282 {
 283         struct ath79_eth_pll_data *pll_data;
 284         u32 pll_val;
 285
 286         switch (mac) {
 287         case 0:
 288                 pll_data = &ath79_eth0_pll_data;
 289                 break;
 290         case 1:
 291                 pll_data = &ath79_eth1_pll_data;
 292                 break;
 293         default:
 294                 BUG();
 295         }
 296
 297         switch (speed) {
 298         case SPEED_10:
 299                 pll_val = pll_data->pll_10;
 300                 break;
 301         case SPEED_100:
 302                 pll_val = pll_data->pll_100;
 303                 break;
 304         case SPEED_1000:
 305                 pll_val = pll_data->pll_1000;
 306                 break;
 307         default:
 308                 BUG();
 309         }
 310
 311         return pll_val;
 312 }
 313
 314 static void ath79_set_speed_ge0(int speed)
 315 {
 316         u32 val = ath79_get_eth_pll(0, speed);
 317
 318         ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK,
 319                         val, AR71XX_ETH0_PLL_SHIFT);
 320         ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
 321 }
 322
 323 static void ath79_set_speed_ge1(int speed)
 324 {
 325         u32 val = ath79_get_eth_pll(1, speed);
 326
 327         ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK,
 328                          val, AR71XX_ETH1_PLL_SHIFT);
 329         ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
 330 }
 331
 332 static void ar7242_set_speed_ge0(int speed)
 333 {
 334         u32 val = ath79_get_eth_pll(0, speed);
 335         void __iomem *base;
 336
 337         base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
 338         __raw_writel(val, base + AR7242_PLL_REG_ETH0_INT_CLOCK);
 339         iounmap(base);
 340 }
 341
 342 static void ar91xx_set_speed_ge0(int speed)
 343 {
 344         u32 val = ath79_get_eth_pll(0, speed);
 345
 346         ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH0_INT_CLOCK,
 347                          val, AR913X_ETH0_PLL_SHIFT);
 348         ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
 349 }
 350
 351 static void ar91xx_set_speed_ge1(int speed)
 352 {
 353         u32 val = ath79_get_eth_pll(1, speed);
 354
 355         ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH1_INT_CLOCK,
 356                          val, AR913X_ETH1_PLL_SHIFT);
 357         ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
 358 }
 359
 360 static void ar934x_set_speed_ge0(int speed)
 361 {
 362         void __iomem *base;
 363         u32 val = ath79_get_eth_pll(0, speed);
 364
 365         base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
 366         __raw_writel(val, base + AR934X_PLL_ETH_XMII_CONTROL_REG);
 367         iounmap(base);
 368 }
 369
 370 static void qca955x_set_speed_xmii(int speed)
 371 {
 372         void __iomem *base;
 373         u32 val = ath79_get_eth_pll(0, speed);
 374
 375         base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
 376         __raw_writel(val, base + QCA955X_PLL_ETH_XMII_CONTROL_REG);
 377         iounmap(base);
 378 }
 379
 380 static void qca955x_set_speed_sgmii(int speed)
 381 {
 382         void __iomem *base;
 383         u32 val = ath79_get_eth_pll(1, speed);
 384
 385         base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
 386         __raw_writel(val, base + QCA955X_PLL_ETH_SGMII_CONTROL_REG);
 387         iounmap(base);
 388 }
 389
 390 static void ath79_set_speed_dummy(int speed)
 391 {
 392 }
 393
 394 static void ath79_ddr_no_flush(void)
 395 {
 396 }
 397
 398 static void ath79_ddr_flush_ge0(void)
 399 {
 400         ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE0);
 401 }
 402
 403 static void ath79_ddr_flush_ge1(void)
 404 {
 405         ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE1);
 406 }
 407
 408 static void ar724x_ddr_flush_ge0(void)
 409 {
 410         ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE0);
 411 }
 412
 413 static void ar724x_ddr_flush_ge1(void)
 414 {
 415         ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE1);
 416 }
 417
 418 static void ar91xx_ddr_flush_ge0(void)
 419 {
 420         ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE0);
 421 }
 422
 423 static void ar91xx_ddr_flush_ge1(void)
 424 {
 425         ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE1);
 426 }
 427
 428 static void ar933x_ddr_flush_ge0(void)
 429 {
 430         ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE0);
 431 }
 432
 433 static void ar933x_ddr_flush_ge1(void)
 434 {
 435         ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE1);
 436 }
 437
 438 static struct resource ath79_eth0_resources[] = {
 439         {
 440                 .name   = "mac_base",
 441                 .flags  = IORESOURCE_MEM,
 442                 .start  = AR71XX_GE0_BASE,
 443                 .end    = AR71XX_GE0_BASE + 0x200 - 1,
 444         }, {
 445                 .name   = "mac_irq",
 446                 .flags  = IORESOURCE_IRQ,
 447                 .start  = ATH79_CPU_IRQ(4),
 448                 .end    = ATH79_CPU_IRQ(4),
 449         },
 450 };
 451
 452 struct ag71xx_platform_data ath79_eth0_data = {
 453         .reset_bit      = AR71XX_RESET_GE0_MAC,
 454 };
 455
 456 struct platform_device ath79_eth0_device = {
 457         .name           = "ag71xx",
 458         .id             = 0,
 459         .resource       = ath79_eth0_resources,
 460         .num_resources  = ARRAY_SIZE(ath79_eth0_resources),
 461         .dev = {
 462                 .platform_data = &ath79_eth0_data,
 463         },
 464 };
 465
 466 static struct resource ath79_eth1_resources[] = {
 467         {
 468                 .name   = "mac_base",
 469                 .flags  = IORESOURCE_MEM,
 470                 .start  = AR71XX_GE1_BASE,
 471                 .end    = AR71XX_GE1_BASE + 0x200 - 1,
 472         }, {
 473                 .name   = "mac_irq",
 474                 .flags  = IORESOURCE_IRQ,
 475                 .start  = ATH79_CPU_IRQ(5),
 476                 .end    = ATH79_CPU_IRQ(5),
 477         },
 478 };
 479
 480 struct ag71xx_platform_data ath79_eth1_data = {
 481         .reset_bit      = AR71XX_RESET_GE1_MAC,
 482 };
 483
 484 struct platform_device ath79_eth1_device = {
 485         .name           = "ag71xx",
 486         .id             = 1,
 487         .resource       = ath79_eth1_resources,
 488         .num_resources  = ARRAY_SIZE(ath79_eth1_resources),
 489         .dev = {
 490                 .platform_data = &ath79_eth1_data,
 491         },
 492 };
 493
 494 struct ag71xx_switch_platform_data ath79_switch_data;
 495
 496 #define AR71XX_PLL_VAL_1000     0x00110000
 497 #define AR71XX_PLL_VAL_100      0x00001099
 498 #define AR71XX_PLL_VAL_10       0x00991099
 499
 500 #define AR724X_PLL_VAL_1000     0x00110000
 501 #define AR724X_PLL_VAL_100      0x00001099
 502 #define AR724X_PLL_VAL_10       0x00991099
 503
 504 #define AR7242_PLL_VAL_1000     0x16000000
 505 #define AR7242_PLL_VAL_100      0x00000101
 506 #define AR7242_PLL_VAL_10       0x00001616
 507
 508 #define AR913X_PLL_VAL_1000     0x1a000000
 509 #define AR913X_PLL_VAL_100      0x13000a44
 510 #define AR913X_PLL_VAL_10       0x00441099
 511
 512 #define AR933X_PLL_VAL_1000     0x00110000
 513 #define AR933X_PLL_VAL_100      0x00001099
 514 #define AR933X_PLL_VAL_10       0x00991099
 515
 516 #define AR934X_PLL_VAL_1000     0x16000000
 517 #define AR934X_PLL_VAL_100      0x00000101
 518 #define AR934X_PLL_VAL_10       0x00001616
 519
 520 static void __init ath79_init_eth_pll_data(unsigned int id)
 521 {
 522         struct ath79_eth_pll_data *pll_data;
 523         u32 pll_10, pll_100, pll_1000;
 524
 525         switch (id) {
 526         case 0:
 527                 pll_data = &ath79_eth0_pll_data;
 528                 break;
 529         case 1:
 530                 pll_data = &ath79_eth1_pll_data;
 531                 break;
 532         default:
 533                 BUG();
 534         }
 535
 536         switch (ath79_soc) {
 537         case ATH79_SOC_AR7130:
 538         case ATH79_SOC_AR7141:
 539         case ATH79_SOC_AR7161:
 540                 pll_10 = AR71XX_PLL_VAL_10;
 541                 pll_100 = AR71XX_PLL_VAL_100;
 542                 pll_1000 = AR71XX_PLL_VAL_1000;
 543                 break;
 544
 545         case ATH79_SOC_AR7240:
 546         case ATH79_SOC_AR7241:
 547                 pll_10 = AR724X_PLL_VAL_10;
 548                 pll_100 = AR724X_PLL_VAL_100;
 549                 pll_1000 = AR724X_PLL_VAL_1000;
 550                 break;
 551
 552         case ATH79_SOC_AR7242:
 553                 pll_10 = AR7242_PLL_VAL_10;
 554                 pll_100 = AR7242_PLL_VAL_100;
 555                 pll_1000 = AR7242_PLL_VAL_1000;
 556                 break;
 557
 558         case ATH79_SOC_AR9130:
 559         case ATH79_SOC_AR9132:
 560                 pll_10 = AR913X_PLL_VAL_10;
 561                 pll_100 = AR913X_PLL_VAL_100;
 562                 pll_1000 = AR913X_PLL_VAL_1000;
 563                 break;
 564
 565         case ATH79_SOC_AR9330:
 566         case ATH79_SOC_AR9331:
 567                 pll_10 = AR933X_PLL_VAL_10;
 568                 pll_100 = AR933X_PLL_VAL_100;
 569                 pll_1000 = AR933X_PLL_VAL_1000;
 570                 break;
 571
 572         case ATH79_SOC_AR9341:
 573         case ATH79_SOC_AR9342:
 574         case ATH79_SOC_AR9344:
 575         case ATH79_SOC_QCA9533:
 576         case ATH79_SOC_QCA9556:
 577         case ATH79_SOC_QCA9558:
 578         case ATH79_SOC_QCA9561:
 579         case ATH79_SOC_TP9343:
 580                 pll_10 = AR934X_PLL_VAL_10;
 581                 pll_100 = AR934X_PLL_VAL_100;
 582                 pll_1000 = AR934X_PLL_VAL_1000;
 583                 break;
 584
 585         default:
 586                 BUG();
 587         }
 588
 589         if (!pll_data->pll_10)
 590                 pll_data->pll_10 = pll_10;
 591
 592         if (!pll_data->pll_100)
 593                 pll_data->pll_100 = pll_100;
 594
 595         if (!pll_data->pll_1000)
 596                 pll_data->pll_1000 = pll_1000;
 597 }
 598
 599 static int __init ath79_setup_phy_if_mode(unsigned int id,
 600                                            struct ag71xx_platform_data *pdata)
 601 {
 602         unsigned int mii_if;
 603
 604         switch (id) {
 605         case 0:
 606                 switch (ath79_soc) {
 607                 case ATH79_SOC_AR7130:
 608                 case ATH79_SOC_AR7141:
 609                 case ATH79_SOC_AR7161:
 610                 case ATH79_SOC_AR9130:
 611                 case ATH79_SOC_AR9132:
 612                         switch (pdata->phy_if_mode) {
 613                         case PHY_INTERFACE_MODE_MII:
 614                                 mii_if = AR71XX_MII0_CTRL_IF_MII;
 615                                 break;
 616                         case PHY_INTERFACE_MODE_GMII:
 617                                 mii_if = AR71XX_MII0_CTRL_IF_GMII;
 618                                 break;
 619                         case PHY_INTERFACE_MODE_RGMII:
 620                                 mii_if = AR71XX_MII0_CTRL_IF_RGMII;
 621                                 break;
 622                         case PHY_INTERFACE_MODE_RMII:
 623                                 mii_if = AR71XX_MII0_CTRL_IF_RMII;
 624                                 break;
 625                         default:
 626                                 return -EINVAL;
 627                         }
 628                         ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII0_CTRL, mii_if);
 629                         break;
 630
 631                 case ATH79_SOC_AR7240:
 632                 case ATH79_SOC_AR7241:
 633                 case ATH79_SOC_AR9330:
 634                 case ATH79_SOC_AR9331:
 635                 case ATH79_SOC_QCA9533:
 636                 case ATH79_SOC_QCA9561:
 637                 case ATH79_SOC_TP9343:
 638                         pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
 639                         break;
 640
 641                 case ATH79_SOC_AR7242:
 642                         /* FIXME */
 643
 644                 case ATH79_SOC_AR9341:
 645                 case ATH79_SOC_AR9342:
 646                 case ATH79_SOC_AR9344:
 647                         switch (pdata->phy_if_mode) {
 648                         case PHY_INTERFACE_MODE_MII:
 649                         case PHY_INTERFACE_MODE_GMII:
 650                         case PHY_INTERFACE_MODE_RGMII:
 651                         case PHY_INTERFACE_MODE_RMII:
 652                                 break;
 653                         default:
 654                                 return -EINVAL;
 655                         }
 656                         break;
 657
 658                 case ATH79_SOC_QCA9556:
 659                 case ATH79_SOC_QCA9558:
 660                         switch (pdata->phy_if_mode) {
 661                         case PHY_INTERFACE_MODE_MII:
 662                         case PHY_INTERFACE_MODE_RGMII:
 663                         case PHY_INTERFACE_MODE_SGMII:
 664                                 break;
 665                         default:
 666                                 return -EINVAL;
 667                         }
 668                         break;
 669
 670                 default:
 671                         BUG();
 672                 }
 673                 break;
 674         case 1:
 675                 switch (ath79_soc) {
 676                 case ATH79_SOC_AR7130:
 677                 case ATH79_SOC_AR7141:
 678                 case ATH79_SOC_AR7161:
 679                 case ATH79_SOC_AR9130:
 680                 case ATH79_SOC_AR9132:
 681                         switch (pdata->phy_if_mode) {
 682                         case PHY_INTERFACE_MODE_RMII:
 683                                 mii_if = AR71XX_MII1_CTRL_IF_RMII;
 684                                 break;
 685                         case PHY_INTERFACE_MODE_RGMII:
 686                                 mii_if = AR71XX_MII1_CTRL_IF_RGMII;
 687                                 break;
 688                         default:
 689                                 return -EINVAL;
 690                         }
 691                         ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII1_CTRL, mii_if);
 692                         break;
 693
 694                 case ATH79_SOC_AR7240:
 695                 case ATH79_SOC_AR7241:
 696                 case ATH79_SOC_AR9330:
 697                 case ATH79_SOC_AR9331:
 698                 case ATH79_SOC_QCA9561:
 699                 case ATH79_SOC_TP9343:
 700                         pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
 701                         break;
 702
 703                 case ATH79_SOC_AR7242:
 704                         /* FIXME */
 705
 706                 case ATH79_SOC_AR9341:
 707                 case ATH79_SOC_AR9342:
 708                 case ATH79_SOC_AR9344:
 709                 case ATH79_SOC_QCA9533:
 710                         switch (pdata->phy_if_mode) {
 711                         case PHY_INTERFACE_MODE_MII:
 712                         case PHY_INTERFACE_MODE_GMII:
 713                                 break;
 714                         default:
 715                                 return -EINVAL;
 716                         }
 717                         break;
 718
 719                 case ATH79_SOC_QCA9556:
 720                 case ATH79_SOC_QCA9558:
 721                         switch (pdata->phy_if_mode) {
 722                         case PHY_INTERFACE_MODE_MII:
 723                         case PHY_INTERFACE_MODE_RGMII:
 724                         case PHY_INTERFACE_MODE_SGMII:
 725                                 break;
 726                         default:
 727                                 return -EINVAL;
 728                         }
 729                         break;
 730
 731                 default:
 732                         BUG();
 733                 }
 734                 break;
 735         }
 736
 737         return 0;
 738 }
 739
 740 void __init ath79_setup_ar933x_phy4_switch(bool mac, bool mdio)
 741 {
 742         void __iomem *base;
 743         u32 t;
 744
 745         base = ioremap(AR933X_GMAC_BASE, AR933X_GMAC_SIZE);
 746
 747         t = __raw_readl(base + AR933X_GMAC_REG_ETH_CFG);
 748         t &= ~(AR933X_ETH_CFG_SW_PHY_SWAP | AR933X_ETH_CFG_SW_PHY_ADDR_SWAP);
 749         if (mac)
 750                 t |= AR933X_ETH_CFG_SW_PHY_SWAP;
 751         if (mdio)
 752                 t |= AR933X_ETH_CFG_SW_PHY_ADDR_SWAP;
 753         __raw_writel(t, base + AR933X_GMAC_REG_ETH_CFG);
 754
 755         iounmap(base);
 756 }
 757
 758 void __init ath79_setup_ar934x_eth_cfg(u32 mask)
 759 {
 760         void __iomem *base;
 761         u32 t;
 762
 763         base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
 764
 765         t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
 766
 767         t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 |
 768                AR934X_ETH_CFG_MII_GMAC0 |
 769                AR934X_ETH_CFG_GMII_GMAC0 |
 770                AR934X_ETH_CFG_SW_ONLY_MODE |
 771                AR934X_ETH_CFG_SW_PHY_SWAP);
 772
 773         t |= mask;
 774
 775         __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
 776         /* flush write */
 777         __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
 778
 779         iounmap(base);
 780 }
 781
 782 void __init ath79_setup_ar934x_eth_rx_delay(unsigned int rxd,
 783                                             unsigned int rxdv)
 784 {
 785         void __iomem *base;
 786         u32 t;
 787
 788         rxd &= AR934X_ETH_CFG_RXD_DELAY_MASK;
 789         rxdv &= AR934X_ETH_CFG_RDV_DELAY_MASK;
 790
 791         base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
 792
 793         t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
 794
 795         t &= ~(AR934X_ETH_CFG_RXD_DELAY_MASK << AR934X_ETH_CFG_RXD_DELAY_SHIFT |
 796                AR934X_ETH_CFG_RDV_DELAY_MASK << AR934X_ETH_CFG_RDV_DELAY_SHIFT);
 797
 798         t |= (rxd << AR934X_ETH_CFG_RXD_DELAY_SHIFT |
 799               rxdv << AR934X_ETH_CFG_RDV_DELAY_SHIFT);
 800
 801         __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
 802         /* flush write */
 803         __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
 804
 805         iounmap(base);
 806 }
 807
 808 void __init ath79_setup_qca955x_eth_cfg(u32 mask)
 809 {
 810         void __iomem *base;
 811         u32 t;
 812
 813         base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
 814
 815         t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);
 816
 817         t &= ~(QCA955X_ETH_CFG_RGMII_EN | QCA955X_ETH_CFG_GE0_SGMII);
 818
 819         t |= mask;
 820
 821         __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
 822
 823         iounmap(base);
 824 }
 825
 826 static int ath79_eth_instance __initdata;
 827 void __init ath79_register_eth(unsigned int id)
 828 {
 829         struct platform_device *pdev;
 830         struct ag71xx_platform_data *pdata;
 831         int err;
 832
 833         if (id > 1) {
 834                 printk(KERN_ERR "ar71xx: invalid ethernet id %d\n", id);
 835                 return;
 836         }
 837
 838         ath79_init_eth_pll_data(id);
 839
 840         if (id == 0)
 841                 pdev = &ath79_eth0_device;
 842         else
 843                 pdev = &ath79_eth1_device;
 844
 845         pdata = pdev->dev.platform_data;
 846
 847         pdata->max_frame_len = 1540;
 848         pdata->desc_pktlen_mask = 0xfff;
 849
 850         err = ath79_setup_phy_if_mode(id, pdata);
 851         if (err) {
 852                 printk(KERN_ERR
 853                        "ar71xx: invalid PHY interface mode for GE%u\n", id);
 854                 return;
 855         }
 856
 857         switch (ath79_soc) {
 858         case ATH79_SOC_AR7130:
 859                 if (id == 0) {
 860                         pdata->ddr_flush = ath79_ddr_flush_ge0;
 861                         pdata->set_speed = ath79_set_speed_ge0;
 862                 } else {
 863                         pdata->ddr_flush = ath79_ddr_flush_ge1;
 864                         pdata->set_speed = ath79_set_speed_ge1;
 865                 }
 866                 break;
 867
 868         case ATH79_SOC_AR7141:
 869         case ATH79_SOC_AR7161:
 870                 if (id == 0) {
 871                         pdata->ddr_flush = ath79_ddr_flush_ge0;
 872                         pdata->set_speed = ath79_set_speed_ge0;
 873                 } else {
 874                         pdata->ddr_flush = ath79_ddr_flush_ge1;
 875                         pdata->set_speed = ath79_set_speed_ge1;
 876                 }
 877                 pdata->has_gbit = 1;
 878                 break;
 879
 880         case ATH79_SOC_AR7242:
 881                 if (id == 0) {
 882                         pdata->reset_bit |= AR724X_RESET_GE0_MDIO |
 883                                             AR71XX_RESET_GE0_PHY;
 884                         pdata->ddr_flush = ar724x_ddr_flush_ge0;
 885                         pdata->set_speed = ar7242_set_speed_ge0;
 886                 } else {
 887                         pdata->reset_bit |= AR724X_RESET_GE1_MDIO |
 888                                             AR71XX_RESET_GE1_PHY;
 889                         pdata->ddr_flush = ar724x_ddr_flush_ge1;
 890                         pdata->set_speed = ath79_set_speed_dummy;
 891                 }
 892                 pdata->has_gbit = 1;
 893                 pdata->is_ar724x = 1;
 894
 895                 if (!pdata->fifo_cfg1)
 896                         pdata->fifo_cfg1 = 0x0010ffff;
 897                 if (!pdata->fifo_cfg2)
 898                         pdata->fifo_cfg2 = 0x015500aa;
 899                 if (!pdata->fifo_cfg3)
 900                         pdata->fifo_cfg3 = 0x01f00140;
 901                 break;
 902
 903         case ATH79_SOC_AR7241:
 904                 if (id == 0)
 905                         pdata->reset_bit |= AR724X_RESET_GE0_MDIO;
 906                 else
 907                         pdata->reset_bit |= AR724X_RESET_GE1_MDIO;
 908                 /* fall through */
 909         case ATH79_SOC_AR7240:
 910                 if (id == 0) {
 911                         pdata->reset_bit |= AR71XX_RESET_GE0_PHY;
 912                         pdata->ddr_flush = ar724x_ddr_flush_ge0;
 913                         pdata->set_speed = ath79_set_speed_dummy;
 914
 915                         pdata->phy_mask = BIT(4);
 916                 } else {
 917                         pdata->reset_bit |= AR71XX_RESET_GE1_PHY;
 918                         pdata->ddr_flush = ar724x_ddr_flush_ge1;
 919                         pdata->set_speed = ath79_set_speed_dummy;
 920
 921                         pdata->speed = SPEED_1000;
 922                         pdata->duplex = DUPLEX_FULL;
 923                         pdata->switch_data = &ath79_switch_data;
 924
 925                         ath79_switch_data.phy_poll_mask |= BIT(4);
 926                 }
 927                 pdata->has_gbit = 1;
 928                 pdata->is_ar724x = 1;
 929                 if (ath79_soc == ATH79_SOC_AR7240)
 930                         pdata->is_ar7240 = 1;
 931
 932                 if (!pdata->fifo_cfg1)
 933                         pdata->fifo_cfg1 = 0x0010ffff;
 934                 if (!pdata->fifo_cfg2)
 935                         pdata->fifo_cfg2 = 0x015500aa;
 936                 if (!pdata->fifo_cfg3)
 937                         pdata->fifo_cfg3 = 0x01f00140;
 938                 break;
 939
 940         case ATH79_SOC_AR9130:
 941                 if (id == 0) {
 942                         pdata->ddr_flush = ar91xx_ddr_flush_ge0;
 943                         pdata->set_speed = ar91xx_set_speed_ge0;
 944                 } else {
 945                         pdata->ddr_flush = ar91xx_ddr_flush_ge1;
 946                         pdata->set_speed = ar91xx_set_speed_ge1;
 947                 }
 948                 pdata->is_ar91xx = 1;
 949                 break;
 950
 951         case ATH79_SOC_AR9132:
 952                 if (id == 0) {
 953                         pdata->ddr_flush = ar91xx_ddr_flush_ge0;
 954                         pdata->set_speed = ar91xx_set_speed_ge0;
 955                 } else {
 956                         pdata->ddr_flush = ar91xx_ddr_flush_ge1;
 957                         pdata->set_speed = ar91xx_set_speed_ge1;
 958                 }
 959                 pdata->is_ar91xx = 1;
 960                 pdata->has_gbit = 1;
 961                 break;
 962
 963         case ATH79_SOC_AR9330:
 964         case ATH79_SOC_AR9331:
 965                 if (id == 0) {
 966                         pdata->reset_bit = AR933X_RESET_GE0_MAC |
 967                                            AR933X_RESET_GE0_MDIO;
 968                         pdata->ddr_flush = ar933x_ddr_flush_ge0;
 969                         pdata->set_speed = ath79_set_speed_dummy;
 970
 971                         pdata->phy_mask = BIT(4);
 972                 } else {
 973                         pdata->reset_bit = AR933X_RESET_GE1_MAC |
 974                                            AR933X_RESET_GE1_MDIO;
 975                         pdata->ddr_flush = ar933x_ddr_flush_ge1;
 976                         pdata->set_speed = ath79_set_speed_dummy;
 977
 978                         pdata->speed = SPEED_1000;
 979                         pdata->has_gbit = 1;
 980                         pdata->duplex = DUPLEX_FULL;
 981                         pdata->switch_data = &ath79_switch_data;
 982
 983                         ath79_switch_data.phy_poll_mask |= BIT(4);
 984                 }
 985
 986                 pdata->is_ar724x = 1;
 987
 988                 if (!pdata->fifo_cfg1)
 989                         pdata->fifo_cfg1 = 0x0010ffff;
 990                 if (!pdata->fifo_cfg2)
 991                         pdata->fifo_cfg2 = 0x015500aa;
 992                 if (!pdata->fifo_cfg3)
 993                         pdata->fifo_cfg3 = 0x01f00140;
 994                 break;
 995
 996         case ATH79_SOC_AR9341:
 997         case ATH79_SOC_AR9342:
 998         case ATH79_SOC_AR9344:
 999         case ATH79_SOC_QCA9533:
1000                 if (id == 0) {
1001                         pdata->reset_bit = AR934X_RESET_GE0_MAC |
1002                                            AR934X_RESET_GE0_MDIO;
1003                         pdata->set_speed = ar934x_set_speed_ge0;
1004                 } else {
1005                         pdata->reset_bit = AR934X_RESET_GE1_MAC |
1006                                            AR934X_RESET_GE1_MDIO;
1007                         pdata->set_speed = ath79_set_speed_dummy;
1008
1009                         pdata->switch_data = &ath79_switch_data;
1010
1011                         /* reset the built-in switch */
1012                         ath79_device_reset_set(AR934X_RESET_ETH_SWITCH);
1013                         ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH);
1014                 }
1015
1016                 pdata->ddr_flush = ath79_ddr_no_flush;
1017                 pdata->has_gbit = 1;
1018                 pdata->is_ar724x = 1;
1019
1020                 pdata->max_frame_len = SZ_16K - 1;
1021                 pdata->desc_pktlen_mask = SZ_16K - 1;
1022
1023                 if (!pdata->fifo_cfg1)
1024                         pdata->fifo_cfg1 = 0x0010ffff;
1025                 if (!pdata->fifo_cfg2)
1026                         pdata->fifo_cfg2 = 0x015500aa;
1027                 if (!pdata->fifo_cfg3)
1028                         pdata->fifo_cfg3 = 0x01f00140;
1029                 break;
1030
1031         case ATH79_SOC_QCA9561:
1032         case ATH79_SOC_TP9343:
1033                 if (id == 0) {
1034                         pdata->reset_bit = AR933X_RESET_GE0_MAC |
1035                                            AR933X_RESET_GE0_MDIO;
1036                         pdata->set_speed = ath79_set_speed_dummy;
1037
1038                         pdata->phy_mask = BIT(4);
1039                 } else {
1040                         pdata->reset_bit = AR933X_RESET_GE1_MAC |
1041                                            AR933X_RESET_GE1_MDIO;
1042                         pdata->set_speed = ath79_set_speed_dummy;
1043
1044                         pdata->speed = SPEED_1000;
1045                         pdata->duplex = DUPLEX_FULL;
1046                         pdata->switch_data = &ath79_switch_data;
1047
1048                         ath79_switch_data.phy_poll_mask |= BIT(4);
1049                 }
1050
1051                 pdata->ddr_flush = ath79_ddr_no_flush;
1052                 pdata->has_gbit = 1;
1053                 pdata->is_ar724x = 1;
1054
1055                 if (!pdata->fifo_cfg1)
1056                         pdata->fifo_cfg1 = 0x0010ffff;
1057                 if (!pdata->fifo_cfg2)
1058                         pdata->fifo_cfg2 = 0x015500aa;
1059                 if (!pdata->fifo_cfg3)
1060                         pdata->fifo_cfg3 = 0x01f00140;
1061                 break;
1062
1063         case ATH79_SOC_QCA9556:
1064         case ATH79_SOC_QCA9558:
1065                 if (id == 0) {
1066                         pdata->reset_bit = QCA955X_RESET_GE0_MAC |
1067                                            QCA955X_RESET_GE0_MDIO;
1068                         pdata->set_speed = qca955x_set_speed_xmii;
1069                 } else {
1070                         pdata->reset_bit = QCA955X_RESET_GE1_MAC |
1071                                            QCA955X_RESET_GE1_MDIO;
1072                         pdata->set_speed = qca955x_set_speed_sgmii;
1073                 }
1074
1075                 pdata->ddr_flush = ath79_ddr_no_flush;
1076                 pdata->has_gbit = 1;
1077                 pdata->is_ar724x = 1;
1078
1079                 /*
1080                  * Limit the maximum frame length to 4095 bytes.
1081                  * Although the documentation says that the hardware
1082                  * limit is 16383 bytes but that does not work in
1083                  * practice. It seems that the hardware only updates
1084                  * the lowest 12 bits of the packet length field
1085                  * in the RX descriptor.
1086                  */
1087                 pdata->max_frame_len = SZ_4K - 1;
1088                 pdata->desc_pktlen_mask = SZ_16K - 1;
1089
1090                 if (!pdata->fifo_cfg1)
1091                         pdata->fifo_cfg1 = 0x0010ffff;
1092                 if (!pdata->fifo_cfg2)
1093                         pdata->fifo_cfg2 = 0x015500aa;
1094                 if (!pdata->fifo_cfg3)
1095                         pdata->fifo_cfg3 = 0x01f00140;
1096                 break;
1097
1098         default:
1099                 BUG();
1100         }
1101
1102         switch (pdata->phy_if_mode) {
1103         case PHY_INTERFACE_MODE_GMII:
1104         case PHY_INTERFACE_MODE_RGMII:
1105         case PHY_INTERFACE_MODE_SGMII:
1106                 if (!pdata->has_gbit) {
1107                         printk(KERN_ERR "ar71xx: no gbit available on eth%d\n",
1108                                         id);
1109                         return;
1110                 }
1111                 /* fallthrough */
1112         default:
1113                 break;
1114         }
1115
1116         if (!is_valid_ether_addr(pdata->mac_addr)) {
1117                 random_ether_addr(pdata->mac_addr);
1118                 printk(KERN_DEBUG
1119                         "ar71xx: using random MAC address for eth%d\n",
1120                         ath79_eth_instance);
1121         }
1122
1123         if (pdata->mii_bus_dev == NULL) {
1124                 switch (ath79_soc) {
1125                 case ATH79_SOC_AR9341:
1126                 case ATH79_SOC_AR9342:
1127                 case ATH79_SOC_AR9344:
1128                         if (id == 0)
1129                                 pdata->mii_bus_dev = &ath79_mdio0_device.dev;
1130                         else
1131                                 pdata->mii_bus_dev = &ath79_mdio1_device.dev;
1132                         break;
1133
1134                 case ATH79_SOC_AR7241:
1135                 case ATH79_SOC_AR9330:
1136                 case ATH79_SOC_AR9331:
1137                 case ATH79_SOC_QCA9533:
1138                 case ATH79_SOC_QCA9561:
1139                 case ATH79_SOC_TP9343:
1140                         pdata->mii_bus_dev = &ath79_mdio1_device.dev;
1141                         break;
1142
1143                 case ATH79_SOC_QCA9556:
1144                 case ATH79_SOC_QCA9558:
1145                         /* don't assign any MDIO device by default */
1146                         break;
1147
1148                 default:
1149                         pdata->mii_bus_dev = &ath79_mdio0_device.dev;
1150                         break;
1151                 }
1152         }
1153
1154         /* Reset the device */
1155         ath79_device_reset_set(pdata->reset_bit);
1156         msleep(100);
1157
1158         ath79_device_reset_clear(pdata->reset_bit);
1159         msleep(100);
1160
1161         platform_device_register(pdev);
1162         ath79_eth_instance++;
1163 }
1164
1165 void __init ath79_set_mac_base(unsigned char *mac)
1166 {
1167         memcpy(ath79_mac_base, mac, ETH_ALEN);
1168 }
1169
1170 void __init ath79_parse_ascii_mac(char *mac_str, u8 *mac)
1171 {
1172         int t;
1173
1174         t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
1175                    &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5]);
1176
1177         if (t != ETH_ALEN)
1178                 t = sscanf(mac_str, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
1179                         &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5]);
1180
1181         if (t != ETH_ALEN || !is_valid_ether_addr(mac)) {
1182                 memset(mac, 0, ETH_ALEN);
1183                 printk(KERN_DEBUG "ar71xx: invalid mac address \"%s\"\n",
1184                        mac_str);
1185         }
1186 }
1187
1188 static void __init ath79_set_mac_base_ascii(char *str)
1189 {
1190         u8 mac[ETH_ALEN];
1191
1192         ath79_parse_ascii_mac(str, mac);
1193         ath79_set_mac_base(mac);
1194 }
1195
1196 static int __init ath79_ethaddr_setup(char *str)
1197 {
1198         ath79_set_mac_base_ascii(str);
1199         return 1;
1200 }
1201 __setup("ethaddr=", ath79_ethaddr_setup);
1202
1203 static int __init ath79_kmac_setup(char *str)
1204 {
1205         ath79_set_mac_base_ascii(str);
1206         return 1;
1207 }
1208 __setup("kmac=", ath79_kmac_setup);
1209
1210 void __init ath79_init_mac(unsigned char *dst, const unsigned char *src,
1211                             int offset)
1212 {
1213         int t;
1214
1215         if (!dst)
1216                 return;
1217
1218         if (!src || !is_valid_ether_addr(src)) {
1219                 memset(dst, '\0', ETH_ALEN);
1220                 return;
1221         }
1222
1223         t = (((u32) src[3]) << 16) + (((u32) src[4]) << 8) + ((u32) src[5]);
1224         t += offset;
1225
1226         dst[0] = src[0];
1227         dst[1] = src[1];
1228         dst[2] = src[2];
1229         dst[3] = (t >> 16) & 0xff;
1230         dst[4] = (t >> 8) & 0xff;
1231         dst[5] = t & 0xff;
1232 }
1233
1234 void __init ath79_init_local_mac(unsigned char *dst, const unsigned char *src)
1235 {
1236         int i;
1237
1238         if (!dst)
1239                 return;
1240
1241         if (!src || !is_valid_ether_addr(src)) {
1242                 memset(dst, '\0', ETH_ALEN);
1243                 return;
1244         }
1245
1246         for (i = 0; i < ETH_ALEN; i++)
1247                 dst[i] = src[i];
1248         dst[0] |= 0x02;
1249 }