1 /*******************************************************************
5 * Description: Declarations for DDR routines and data objects
7 * Author: Julien Margetts
9 * Copyright: Oxford Semiconductor Ltd, 2009
12 #include <asm/arch/clock.h>
16 typedef unsigned int UINT;
18 // DDR TIMING PARAMETERS
20 unsigned int holdoff_cmd_A;
21 unsigned int holdoff_cmd_ARW;
22 unsigned int holdoff_cmd_N;
23 unsigned int holdoff_cmd_LM;
24 unsigned int holdoff_cmd_R;
25 unsigned int holdoff_cmd_W;
26 unsigned int holdoff_cmd_PC;
27 unsigned int holdoff_cmd_RF;
28 unsigned int holdoff_bank_R;
29 unsigned int holdoff_bank_W;
30 unsigned int holdoff_dir_RW;
31 unsigned int holdoff_dir_WR;
32 unsigned int holdoff_FAW;
33 unsigned int latency_CAS;
34 unsigned int latency_WL;
35 unsigned int recovery_WR;
36 unsigned int width_update;
37 unsigned int odt_offset;
38 unsigned int odt_drive_all;
39 unsigned int use_fixed_re;
40 unsigned int delay_wr_to_re;
41 unsigned int wr_slave_ratio;
42 unsigned int rd_slave_ratio0;
43 unsigned int rd_slave_ratio1;
44 } T_DDR_TIMING_PARAMETERS;
46 // DDR CONFIG PARAMETERS
49 unsigned int ddr_mode;
56 unsigned int cmd_mode_wr_cl_bl;
57 } T_DDR_CONFIG_PARAMETERS;
60 //when SDR : cmd_mode_wr_cl_bl = 0x80200002 + (latency_CAS_RAM * 16) + (recovery_WR - 1) * 512; -- Sets write rec XX, CL=XX; BL=8
61 //else cmd_mode_wr_cl_bl = 0x80200003 + (latency_CAS_RAM * 16) + (recovery_WR - 1) * 512; -- Sets write rec XX, CL=XX; BL=8
63 // cmd_ bank_ dir_ lat_ rec_ width_ odt_ odt_ fix delay ratio
64 // A F C update offset all re re_to_we w r0 r1
65 // R L P R R W A A W W
66 //Timing Parameters A W N M R W C F R W W R W S L R
67 static const T_DDR_TIMING_PARAMETERS C_TP_DDR2_25E_CL5_1GB = { 4, 5, 0, 2, 4, 4,
68 5, 51, 23, 24, 9, 11, 18, 5, 4, 6, 3, 2, 0, 1, 2, 75, 56, 56 }; //elida device.
69 static const T_DDR_TIMING_PARAMETERS C_TP_DDR2_25E_CL5_2GB = { 4, 5, 0, 2, 4, 4,
70 5, 79, 22, 24, 9, 11, 20, 5, 4, 6, 3, 2, 0, 1, 2, 75, 56, 56 };
71 static const T_DDR_TIMING_PARAMETERS C_TP_DDR2_25_CL6_1GB = { 4, 5, 0, 2, 4, 4,
72 4, 51, 22, 26, 10, 12, 18, 6, 5, 6, 3, 2, 0, 1, 2, 75, 56, 56 }; // 400MHz, Speedgrade 25 timings (1Gb parts)
76 //Config Parameters R D C 8 M Z D CMD_MODE
77 //static const T_DDR_CONFIG_PARAMETERS C_CP_DDR2_25E_CL5 = { 2,16, 1, 0, 1, 32,25,0x80200A53}; // 64 MByte
78 static const T_DDR_CONFIG_PARAMETERS C_CP_DDR2_25E_CL5 = { 2, 16, 1, 1, 1, 64,
79 25, 0x80200A53 }; // 128 MByte
80 static const T_DDR_CONFIG_PARAMETERS C_CP_DDR2_25_CL6 = { 2, 16, 1, 1, 1, 128,
81 25, 0x80200A63 }; // 256 MByte
83 static void ddr_phy_poll_until_locked(void)
85 volatile UINT reg_tmp = 0;
86 volatile UINT locked = 0;
88 //Extra read to put in delay before starting to poll...
89 reg_tmp = *(volatile UINT *) C_DDR_REG_PHY2; // read
91 //POLL C_DDR_PHY2_REG register until clock and flock
92 //!!! Ideally have a timeout on this.
94 reg_tmp = *(volatile UINT *) C_DDR_REG_PHY2; // read
96 //locked when bits 30 and 31 are set
97 if (reg_tmp & 0xC0000000) {
103 static void ddr_poll_until_not_busy(void)
105 volatile UINT reg_tmp = 0;
106 volatile UINT busy = 1;
108 //Extra read to put in delay before starting to poll...
109 reg_tmp = *(volatile UINT *) C_DDR_STAT_REG; // read
111 //POLL DDR_STAT register until no longer busy
112 //!!! Ideally have a timeout on this.
114 reg_tmp = *(volatile UINT *) C_DDR_STAT_REG; // read
116 //when bit 31 is clear - core is no longer busy
117 if ((reg_tmp & 0x80000000) == 0x00000000) {
123 static void ddr_issue_command(int commmand)
125 *(volatile UINT *) C_DDR_CMD_REG = commmand;
126 ddr_poll_until_not_busy();
129 static void ddr_timing_initialisation(
130 const T_DDR_TIMING_PARAMETERS *ddr_timing_parameters)
132 volatile UINT reg_tmp = 0;
133 /* update the DDR controller registers for timing parameters */
134 reg_tmp = (ddr_timing_parameters->holdoff_cmd_A << 0);
135 reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_cmd_ARW << 4);
136 reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_cmd_N << 8);
137 reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_cmd_LM << 12);
138 reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_cmd_R << 16);
139 reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_cmd_W << 20);
140 reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_cmd_PC << 24);
141 *(volatile UINT *) C_DDR_REG_TIMING0 = reg_tmp;
143 reg_tmp = (ddr_timing_parameters->holdoff_cmd_RF << 0);
144 reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_bank_R << 8);
145 reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_bank_W << 16);
146 reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_dir_RW << 24);
147 reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_dir_WR << 28);
148 *(volatile UINT *) C_DDR_REG_TIMING1 = reg_tmp;
150 reg_tmp = (ddr_timing_parameters->latency_CAS << 0);
151 reg_tmp = reg_tmp + (ddr_timing_parameters->latency_WL << 4);
152 reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_FAW << 8);
153 reg_tmp = reg_tmp + (ddr_timing_parameters->width_update << 16);
154 reg_tmp = reg_tmp + (ddr_timing_parameters->odt_offset << 21);
155 reg_tmp = reg_tmp + (ddr_timing_parameters->odt_drive_all << 24);
157 *(volatile UINT *) C_DDR_REG_TIMING2 = reg_tmp;
159 /* Program the timing parameters in the PHY too */
160 reg_tmp = (ddr_timing_parameters->use_fixed_re << 16)
161 | (ddr_timing_parameters->delay_wr_to_re << 8)
162 | (ddr_timing_parameters->latency_WL << 4)
163 | (ddr_timing_parameters->latency_CAS << 0);
165 *(volatile UINT *) C_DDR_REG_PHY_TIMING = reg_tmp;
167 reg_tmp = ddr_timing_parameters->wr_slave_ratio;
169 *(volatile UINT *) C_DDR_REG_PHY_WR_RATIO = reg_tmp;
171 reg_tmp = ddr_timing_parameters->rd_slave_ratio0;
172 reg_tmp += ddr_timing_parameters->rd_slave_ratio1 << 8;
174 *(volatile UINT *) C_DDR_REG_PHY_RD_RATIO = reg_tmp;
178 static void ddr_normal_initialisation(
179 const T_DDR_CONFIG_PARAMETERS *ddr_config_parameters, int mhz)
182 volatile UINT tmp = 0;
183 volatile UINT reg_tmp = 0;
184 volatile UINT emr_cmd = 0;
187 //Total size of memory in Mbits...
188 tmp = ddr_config_parameters->rams * ddr_config_parameters->asize
189 * ddr_config_parameters->width;
190 //Deduce value to program into DDR_CFG register...
193 reg_tmp = 0x00020000 * 1;
196 reg_tmp = 0x00020000 * 2;
199 reg_tmp = 0x00020000 * 3;
202 reg_tmp = 0x00020000 * 4;
205 reg_tmp = 0x00020000 * 5;
208 reg_tmp = 0x00020000 * 6;
211 reg_tmp = 0x00020000 * 7;
214 reg_tmp = 0x00020000 * 8;
217 reg_tmp = 0; //forces sims not to work if badly configured
221 tmp = ddr_config_parameters->rams * ddr_config_parameters->width;
224 reg_tmp = reg_tmp + 0x00400000;
227 reg_tmp = reg_tmp + 0x00200000;
230 reg_tmp = reg_tmp + 0x00000000;
233 reg_tmp = 0; //forces sims not to work if badly configured
237 switch (ddr_config_parameters->ddr_mode) {
239 reg_tmp = reg_tmp + 0x00000000;
242 reg_tmp = reg_tmp + 0x40000000;
245 reg_tmp = reg_tmp + 0x80000000;
248 reg_tmp = 0; //forces sims not to work if badly configured
252 if (ddr_config_parameters->banks8 == 1) {
253 reg_tmp = reg_tmp + 0x00800000;
256 //Program DDR_CFG register...
257 *(volatile UINT *) C_DDR_CFG_REG = reg_tmp;
259 //Configure PHY0 reg - se_mode is bit 1,
260 //needs to be 1 for DDR (single_ended drive)
261 switch (ddr_config_parameters->ddr_mode) {
263 reg_tmp = 2 + (0 << 4);
266 reg_tmp = 2 + (4 << 4);
269 reg_tmp = 0 + (4 << 4);
275 //Program DDR_PHY0 register...
276 *(volatile UINT *) C_DDR_REG_PHY0 = reg_tmp;
278 //Read DDR_PHY* registers to exercise paths for vcd
279 reg_tmp = *(volatile UINT *) C_DDR_REG_PHY3;
280 reg_tmp = *(volatile UINT *) C_DDR_REG_PHY2;
281 reg_tmp = *(volatile UINT *) C_DDR_REG_PHY1;
282 reg_tmp = *(volatile UINT *) C_DDR_REG_PHY0;
284 //Start up sequences - Different dependant on DDR mode
285 switch (ddr_config_parameters->ddr_mode) {
287 //Start-up sequence: follows procedure described in Micron datasheet.
288 //start up DDR PHY DLL
289 reg_tmp = 0x00022828; // dll on, start point and inc = h28
290 *(volatile UINT *) C_DDR_REG_PHY2 = reg_tmp;
292 reg_tmp = 0x00032828; // start on, dll on, start point and inc = h28
293 *(volatile UINT *) C_DDR_REG_PHY2 = reg_tmp;
295 ddr_phy_poll_until_locked();
300 //!!! Software: CK should be running for 200us before wake-up
301 ddr_issue_command( C_CMD_WAKE_UP);
302 ddr_issue_command( C_CMD_NOP);
303 ddr_issue_command( C_CMD_PRECHARGE_ALL);
304 ddr_issue_command( C_CMD_DDR2_EMR2);
305 ddr_issue_command( C_CMD_DDR2_EMR3);
307 emr_cmd = C_CMD_DDR2_EMR1 + C_CMD_ODT_75 + C_CMD_REDUCED_DRIVE
310 ddr_issue_command(emr_cmd);
311 //Sets CL=3; BL=8 but also reset DLL to trigger a DLL initialisation...
314 ddr_config_parameters->cmd_mode_wr_cl_bl
318 //!!! Software: Wait 200 CK cycles before...
319 //for(i=1; i<=2; i++) {
320 ddr_issue_command(C_CMD_PRECHARGE_ALL);
321 // !!! Software: Wait here at least 8 CK cycles
323 //need a wait here to ensure PHY DLL lock before the refresh is issued
325 for (i = 1; i <= 2; i++) {
326 ddr_issue_command( C_CMD_AUTO_REFRESH);
327 //!!! Software: Wait here at least 8 CK cycles to satify tRFC
330 //As before but without 'RESET_DLL' bit set...
331 ddr_issue_command(ddr_config_parameters->cmd_mode_wr_cl_bl);
334 ddr_issue_command(emr_cmd + C_CMD_MODE_DDR2_OCD_DFLT);
335 ddr_issue_command(emr_cmd + C_CMD_MODE_DDR2_OCD_EXIT);
342 //Enable auto-refresh
344 // 8192 Refreshes required every 64ms, so maximum refresh period is 7.8125 us
345 // We have a 400 MHz DDR clock (2.5ns period) so max period is 3125 cycles
346 // Our core now does 8 refreshes in a go, so we multiply this period by 8
348 refresh = (64000 * mhz) / 8192; // Refresh period in clocks
350 reg_tmp = *(volatile UINT *) C_DDR_CFG_REG; // read
351 #ifdef BURST_REFRESH_ENABLE
352 reg_tmp |= C_CFG_REFRESH_ENABLE | (refresh * 8);
353 reg_tmp |= C_CFG_BURST_REFRESH_ENABLE;
355 reg_tmp |= C_CFG_REFRESH_ENABLE | (refresh * 1);
356 reg_tmp &= ~C_CFG_BURST_REFRESH_ENABLE;
358 *(volatile UINT *) C_DDR_CFG_REG = reg_tmp;
360 //Verify register contents
361 reg_tmp = *(volatile UINT *) C_DDR_REG_PHY2; // read
362 //printf("Warning XXXXXXXXXXXXXXXXXXXXXX - get bad read data from C_DDR_PHY2_REG, though it looks OK on bus XXXXXXXXXXXXXXXXXX");
363 //TBD Check_data (read_data, dll_reg, "Error: bad C_DDR_PHY2_REG read", tb_pass);
364 reg_tmp = *(volatile UINT *) C_DDR_CFG_REG; // read
365 //TBD Check_data (read_data, cfg_reg, "Error: bad DDR_CFG read", tb_pass);
367 //disable optimised wrapping
368 if (ddr_config_parameters->ddr_mode == 2) {
369 reg_tmp = 0xFFFF0000;
370 *(volatile UINT *) C_DDR_REG_IGNORE = reg_tmp;
373 //enable midbuffer followon
374 reg_tmp = *(volatile UINT *) C_DDR_ARB_REG; // read
375 reg_tmp = 0xFFFF0000 | reg_tmp;
376 *(volatile UINT *) C_DDR_ARB_REG = reg_tmp;
378 // Enable write behind coherency checking for all clients
380 reg_tmp = 0xFFFF0000;
381 *(volatile UINT *) C_DDR_AHB4_REG = reg_tmp;
383 //Wait for 200 clock cycles for SDRAM DLL to lock...
387 // Function used to Setup DDR core
389 void ddr_setup(int mhz)
391 static const T_DDR_TIMING_PARAMETERS *ddr_timing_parameters =
392 &C_TP_DDR2_25_CL6_1GB;
393 static const T_DDR_CONFIG_PARAMETERS *ddr_config_parameters =
396 //Bring core out of Reset
397 *(volatile UINT *) C_DDR_BLKEN_REG = C_BLKEN_DDR_ON;
399 //DDR TIMING INITIALISTION
400 ddr_timing_initialisation(ddr_timing_parameters);
402 //DDR NORMAL INITIALISATION
403 ddr_normal_initialisation(ddr_config_parameters, mhz);
405 // route all writes through one client
406 *(volatile UINT *) C_DDR_TRANSACTION_ROUTING = (0
407 << DDR_ROUTE_CPU0_INSTR_SHIFT)
408 | (1 << DDR_ROUTE_CPU0_RDDATA_SHIFT)
409 | (3 << DDR_ROUTE_CPU0_WRDATA_SHIFT)
410 | (2 << DDR_ROUTE_CPU1_INSTR_SHIFT)
411 | (3 << DDR_ROUTE_CPU1_RDDATA_SHIFT)
412 | (3 << DDR_ROUTE_CPU1_WRDATA_SHIFT);
414 //Bring all clients out of reset
415 *(volatile UINT *) C_DDR_BLKEN_REG = C_BLKEN_DDR_ON + 0x0000FFFF;
419 void set_ddr_timing(unsigned int w, unsigned int i)
422 unsigned int wnow = 16;
423 unsigned int inow = 32;
425 /* reset all timing controls to known value (31) */
426 writel(DDR_PHY_TIMING_W_RST | DDR_PHY_TIMING_I_RST, DDR_PHY_TIMING);
427 writel(DDR_PHY_TIMING_W_RST | DDR_PHY_TIMING_I_RST | DDR_PHY_TIMING_CK,
429 writel(DDR_PHY_TIMING_W_RST | DDR_PHY_TIMING_I_RST, DDR_PHY_TIMING);
431 /* step up or down read delay to the requested value */
434 reg = DDR_PHY_TIMING_INC;
440 writel(DDR_PHY_TIMING_W_CE | reg, DDR_PHY_TIMING);
441 writel(DDR_PHY_TIMING_CK | DDR_PHY_TIMING_W_CE | reg,
443 writel(DDR_PHY_TIMING_W_CE | reg, DDR_PHY_TIMING);
446 /* now write delay */
449 reg = DDR_PHY_TIMING_INC;
455 writel(DDR_PHY_TIMING_I_CE | reg, DDR_PHY_TIMING);
456 writel(DDR_PHY_TIMING_CK | DDR_PHY_TIMING_I_CE | reg,
458 writel(DDR_PHY_TIMING_I_CE | reg, DDR_PHY_TIMING);
462 //Function used to Setup SDRAM in DDR/SDR mode
463 void init_ddr(int mhz)
466 enable_clock(SYS_CTRL_CLK_DDRPHY);
467 enable_clock(SYS_CTRL_CLK_DDR);
468 enable_clock(SYS_CTRL_CLK_DDRCK);
470 /* bring phy and core out of reset */
471 reset_block(SYS_CTRL_RST_DDR_PHY, 0);
472 reset_block(SYS_CTRL_RST_DDR, 0);
474 /* DDR runs at half the speed of the CPU */