package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/sysctl.h

   1 #ifndef _NAS782X_SYSCTL_H
   2 #define _NAS782X_SYSCTL_H
   3
   4 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
   5 #include <asm/types.h>
   6 #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
   7
   8 #include <asm/arch/hardware.h>
   9
  10 /**
  11  * System block reset and clock control
  12  */
  13 #define SYS_CTRL_PCI_STAT               (SYS_CONTROL_BASE + 0x20)
  14 #define SYS_CTRL_CLK_SET_CTRL           (SYS_CONTROL_BASE + 0x2C)
  15 #define SYS_CTRL_CLK_CLR_CTRL           (SYS_CONTROL_BASE + 0x30)
  16 #define SYS_CTRL_RST_SET_CTRL           (SYS_CONTROL_BASE + 0x34)
  17 #define SYS_CTRL_RST_CLR_CTRL           (SYS_CONTROL_BASE + 0x38)
  18 #define SYS_CTRL_PLLSYS_CTRL            (SYS_CONTROL_BASE + 0x48)
  19 #define SYS_CTRL_PLLSYS_KEY_CTRL        (SYS_CONTROL_BASE + 0x6C)
  20 #define SYS_CTRL_GMAC_CTRL              (SYS_CONTROL_BASE + 0x78)
  21
  22 /* Scratch registers */
  23 #define SYS_CTRL_SCRATCHWORD0           (SYS_CONTROL_BASE + 0xc4)
  24 #define SYS_CTRL_SCRATCHWORD1           (SYS_CONTROL_BASE + 0xc8)
  25 #define SYS_CTRL_SCRATCHWORD2           (SYS_CONTROL_BASE + 0xcc)
  26 #define SYS_CTRL_SCRATCHWORD3           (SYS_CONTROL_BASE + 0xd0)
  27
  28 #define SYS_CTRL_PLLA_CTRL0             (SYS_CONTROL_BASE + 0x1F0)
  29 #define SYS_CTRL_PLLA_CTRL1             (SYS_CONTROL_BASE + 0x1F4)
  30 #define SYS_CTRL_PLLA_CTRL2             (SYS_CONTROL_BASE + 0x1F8)
  31 #define SYS_CTRL_PLLA_CTRL3             (SYS_CONTROL_BASE + 0x1FC)
  32
  33 #define SYS_CTRL_GMAC_AUTOSPEED         3
  34 #define SYS_CTRL_GMAC_RGMII             2
  35 #define SYS_CTRL_GMAC_SIMPLE_MUX        1
  36 #define SYS_CTRL_GMAC_CKEN_GTX          0
  37
  38 #define SYS_CTRL_CKCTRL_CTRL_ADDR       (SYS_CONTROL_BASE + 0x64)
  39
  40 #define SYS_CTRL_CKCTRL_PCI_DIV_BIT     0
  41 #define SYS_CTRL_CKCTRL_SLOW_BIT        8
  42
  43
  44 #define SYS_CTRL_USBHSMPH_CTRL          (SYS_CONTROL_BASE + 0x40)
  45 #define SYS_CTRL_USBHSMPH_STAT          (SYS_CONTROL_BASE + 0x44)
  46 #define SYS_CTRL_REF300_DIV             (SYS_CONTROL_BASE + 0xF8)
  47 #define SYS_CTRL_USBHSPHY_CTRL          (SYS_CONTROL_BASE + 0x84)
  48 #define SYS_CTRL_USB_CTRL               (SYS_CONTROL_BASE + 0x90)
  49
  50 /* System control multi-function pin function selection */
  51 #define SYS_CTRL_SECONDARY_SEL          (SYS_CONTROL_BASE + 0x14)
  52 #define SYS_CTRL_TERTIARY_SEL           (SYS_CONTROL_BASE + 0x8c)
  53 #define SYS_CTRL_QUATERNARY_SEL         (SYS_CONTROL_BASE + 0x94)
  54 #define SYS_CTRL_DEBUG_SEL              (SYS_CONTROL_BASE + 0x9c)
  55 #define SYS_CTRL_ALTERNATIVE_SEL        (SYS_CONTROL_BASE + 0xa4)
  56 #define SYS_CTRL_PULLUP_SEL             (SYS_CONTROL_BASE + 0xac)
  57
  58 /* Secure control multi-function pin function selection */
  59 #define SEC_CTRL_SECONDARY_SEL          (SEC_CONTROL_BASE + 0x14)
  60 #define SEC_CTRL_TERTIARY_SEL           (SEC_CONTROL_BASE + 0x8c)
  61 #define SEC_CTRL_QUATERNARY_SEL         (SEC_CONTROL_BASE + 0x94)
  62 #define SEC_CTRL_DEBUG_SEL              (SEC_CONTROL_BASE + 0x9c)
  63 #define SEC_CTRL_ALTERNATIVE_SEL        (SEC_CONTROL_BASE + 0xa4)
  64 #define SEC_CTRL_PULLUP_SEL             (SEC_CONTROL_BASE + 0xac)
  65
  66 #define SEC_CTRL_COPRO_CTRL             (SEC_CONTROL_BASE + 0x68)
  67 #define SEC_CTRL_SECURE_CTRL            (SEC_CONTROL_BASE + 0x98)
  68 #define SEC_CTRL_LEON_DEBUG             (SEC_CONTROL_BASE + 0xF0)
  69 #define SEC_CTRL_PLLB_DIV_CTRL          (SEC_CONTROL_BASE + 0xF8)
  70 #define SEC_CTRL_PLLB_CTRL0             (SEC_CONTROL_BASE + 0x1F0)
  71 #define SEC_CTRL_PLLB_CTRL1             (SEC_CONTROL_BASE + 0x1F4)
  72 #define SEC_CTRL_PLLB_CTRL8             (SEC_CONTROL_BASE + 0x1F4)
  73
  74 #define REF300_DIV_INT_SHIFT            8
  75 #define REF300_DIV_FRAC_SHIFT           0
  76 #define REF300_DIV_INT(val)             ((val) << REF300_DIV_INT_SHIFT)
  77 #define REF300_DIV_FRAC(val)            ((val) << REF300_DIV_FRAC_SHIFT)
  78
  79 #define USBHSPHY_SUSPENDM_MANUAL_ENABLE         16
  80 #define USBHSPHY_SUSPENDM_MANUAL_STATE          15
  81 #define USBHSPHY_ATE_ESET                       14
  82 #define USBHSPHY_TEST_DIN                       6
  83 #define USBHSPHY_TEST_ADD                       2
  84 #define USBHSPHY_TEST_DOUT_SEL                  1
  85 #define USBHSPHY_TEST_CLK                       0
  86
  87 #define USB_CTRL_USBAPHY_CKSEL_SHIFT    5
  88 #define USB_CLK_XTAL0_XTAL1             (0 << USB_CTRL_USBAPHY_CKSEL_SHIFT)
  89 #define USB_CLK_XTAL0                   (1 << USB_CTRL_USBAPHY_CKSEL_SHIFT)
  90 #define USB_CLK_INTERNAL                (2 << USB_CTRL_USBAPHY_CKSEL_SHIFT)
  91
  92 #define USBAMUX_DEVICE                  BIT(4)
  93
  94 #define USBPHY_REFCLKDIV_SHIFT          2
  95 #define USB_PHY_REF_12MHZ               (0 << USBPHY_REFCLKDIV_SHIFT)
  96 #define USB_PHY_REF_24MHZ               (1 << USBPHY_REFCLKDIV_SHIFT)
  97 #define USB_PHY_REF_48MHZ               (2 << USBPHY_REFCLKDIV_SHIFT)
  98
  99 #define USB_CTRL_USB_CKO_SEL_BIT        0
 100
 101 #define USB_INT_CLK_XTAL                0
 102 #define USB_INT_CLK_REF300              2
 103 #define USB_INT_CLK_PLLB                3
 104
 105 #define SYS_CTRL_GMAC_AUTOSPEED         3
 106 #define SYS_CTRL_GMAC_RGMII             2
 107 #define SYS_CTRL_GMAC_SIMPLE_MUX        1
 108 #define SYS_CTRL_GMAC_CKEN_GTX          0
 109
 110
 111 #define PLLB_ENSAT                      3
 112 #define PLLB_OUTDIV                     4
 113 #define PLLB_REFDIV                     8
 114 #define PLLB_DIV_INT_SHIFT              8
 115 #define PLLB_DIV_FRAC_SHIFT             0
 116 #define PLLB_DIV_INT(val)               ((val) << PLLB_DIV_INT_SHIFT)
 117 #define PLLB_DIV_FRAC(val)              ((val) << PLLB_DIV_FRAC_SHIFT)
 118
 119 #ifndef __KERNEL_STRICT_NAMES
 120 #ifndef __ASSEMBLY__
 121
 122 #endif /* __ASSEMBLY__ */
 123 #endif /* __KERNEL_STRICT_NAMES */
 124
 125 #endif /* _NAS782X_SYSCTL_H */