1 From a18f994f373db4467a4680f83ead997c8122908e Mon Sep 17 00:00:00 2001
2 From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
3 Date: Wed, 22 May 2013 17:48:08 +0200
4 Subject: MIPS: add board support for ZyXEL P-661HNU-Fx
6 Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
9 +++ b/board/zyxel/p661hnufx/Makefile
12 +# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
14 +# SPDX-License-Identifier: GPL-2.0+
17 +include $(TOPDIR)/config.mk
19 +LIB = $(obj)lib$(BOARD).o
23 +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
24 +OBJS := $(addprefix $(obj),$(COBJS))
25 +SOBJS := $(addprefix $(obj),$(SOBJS))
27 +$(LIB): $(obj).depend $(OBJS) $(SOBJS)
28 + $(call cmd_link_o_target, $(OBJS) $(SOBJS))
30 +#########################################################################
32 +# defines $(obj).depend target
33 +include $(SRCTREE)/rules.mk
35 +sinclude $(obj).depend
37 +#########################################################################
39 +++ b/board/zyxel/p661hnufx/config.mk
42 +# Copyright (C) 2012-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
44 +# SPDX-License-Identifier: GPL-2.0+
47 +PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
49 +++ b/board/zyxel/p661hnufx/ddr_settings.h
52 + * Copyright (C) 2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
54 + * The values have been extracted from original ZyXEL U-Boot.
56 + * SPDX-License-Identifier: GPL-2.0+
59 +#define MC_DC00_VALUE 0x1B1B
60 +#define MC_DC01_VALUE 0x0
61 +#define MC_DC02_VALUE 0x0
62 +#define MC_DC03_VALUE 0x0
63 +#define MC_DC04_VALUE 0x0
64 +#define MC_DC05_VALUE 0x200
65 +#define MC_DC06_VALUE 0x307
66 +#define MC_DC07_VALUE 0x303
67 +#define MC_DC08_VALUE 0x103
68 +#define MC_DC09_VALUE 0x80B
69 +#define MC_DC10_VALUE 0x203
70 +#define MC_DC11_VALUE 0xE02
71 +#define MC_DC12_VALUE 0x2C8
72 +#define MC_DC13_VALUE 0x1
73 +#define MC_DC14_VALUE 0x0
74 +#define MC_DC15_VALUE 0x100
75 +#define MC_DC16_VALUE 0xC800
76 +#define MC_DC17_VALUE 0xF
77 +#define MC_DC18_VALUE 0x301
78 +#define MC_DC19_VALUE 0x200
79 +#define MC_DC20_VALUE 0xA04
80 +#define MC_DC21_VALUE 0x1600
81 +#define MC_DC22_VALUE 0x1616
82 +#define MC_DC23_VALUE 0x0
83 +#define MC_DC24_VALUE 0x5D
84 +#define MC_DC25_VALUE 0x0
85 +#define MC_DC26_VALUE 0x0
86 +#define MC_DC27_VALUE 0x0
87 +#define MC_DC28_VALUE 0x5FB
88 +#define MC_DC29_VALUE 0x35DF
89 +#define MC_DC30_VALUE 0x99E9
90 +#define MC_DC31_VALUE 0x0
91 +#define MC_DC32_VALUE 0x0
92 +#define MC_DC33_VALUE 0x0
93 +#define MC_DC34_VALUE 0x0
94 +#define MC_DC35_VALUE 0x0
95 +#define MC_DC36_VALUE 0x0
96 +#define MC_DC37_VALUE 0x0
97 +#define MC_DC38_VALUE 0x0
98 +#define MC_DC39_VALUE 0x0
99 +#define MC_DC40_VALUE 0x0
100 +#define MC_DC41_VALUE 0x0
101 +#define MC_DC42_VALUE 0x0
102 +#define MC_DC43_VALUE 0x0
103 +#define MC_DC44_VALUE 0x0
104 +#define MC_DC45_VALUE 0x600
105 +#define MC_DC46_VALUE 0x0
107 +++ b/board/zyxel/p661hnufx/p661hnufx.c
110 + * Copyright (C) 2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
112 + * SPDX-License-Identifier: GPL-2.0+
118 +#include <asm/gpio.h>
119 +#include <asm/lantiq/eth.h>
120 +#include <asm/lantiq/reset.h>
121 +#include <asm/lantiq/chipid.h>
123 +static void gpio_init(void)
125 + /* SPI CS 0.4 to serial flash */
126 + gpio_direction_output(10, 1);
129 +int board_early_init_f(void)
136 +int checkboard(void)
138 + puts("Board: " CONFIG_BOARD_NAME "\n");
139 + ltq_chip_print_info();
144 +static const struct ltq_eth_port_config eth_port_config[] = {
145 + /* MAC0: Lantiq Tantos switch */
146 + { 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_RMII },
148 + { 1, 0x0, LTQ_ETH_PORT_NONE, PHY_INTERFACE_MODE_NONE },
151 +static const struct ltq_eth_board_config eth_board_config = {
152 + .ports = eth_port_config,
153 + .num_ports = ARRAY_SIZE(eth_port_config),
156 +int board_eth_init(bd_t *bis)
158 + return ltq_eth_initialize(ð_board_config);
161 +static struct switch_device psb697x_dev = {
167 +int board_switch_init(void)
169 + printf("%s\n", __func__);
172 + ltq_reset_once(LTQ_RESET_HARD, 200000);
176 + return switch_device_register(&psb697x_dev);
179 +int spi_cs_is_valid(unsigned int bus, unsigned int cs)
190 +void spi_cs_activate(struct spi_slave *slave)
192 + switch (slave->cs) {
194 + gpio_set_value(10, 0);
201 +void spi_cs_deactivate(struct spi_slave *slave)
203 + switch (slave->cs) {
205 + gpio_set_value(10, 1);
213 @@ -499,6 +499,9 @@ Active mips mips32 -
214 Active mips mips32 arx100 zte zxv10h201l zxv10h201l_nor zxv10h201l:SYS_BOOT_NOR Luka Perkov <luka@openwrt.org>
215 Active mips mips32 arx100 zte zxv10h201l zxv10h201l_ram zxv10h201l:SYS_BOOT_RAM Luka Perkov <luka@openwrt.org>
216 Active mips mips32 arx100 zte zxv10h201l zxv10h201l_zte zxv10h201l:SYS_BOOT_ZTE Luka Perkov <luka@openwrt.org>
217 +Active mips mips32 arx100 zyxel p661hnufx p661hnufx_ram p661hnufx:SYS_BOOT_RAM Luka Perkov <luka@openwrt.org>
218 +Active mips mips32 arx100 zyxel p661hnufx p661hnufx_sfspl p661hnufx:SYS_BOOT_SFSPL Luka Perkov <luka@openwrt.org>
219 +Active mips mips32 arx100 zyxel p661hnufx p661hnufx_zyxel p661hnufx:SYS_BOOT_ZYXEL Luka Perkov <luka@openwrt.org>
220 Active mips mips32 au1x00 - dbau1x00 dbau1000 dbau1x00:DBAU1000 Thomas Lange <thomas@corelatus.se>
221 Active mips mips32 au1x00 - dbau1x00 dbau1100 dbau1x00:DBAU1100 Thomas Lange <thomas@corelatus.se>
222 Active mips mips32 au1x00 - dbau1x00 dbau1500 dbau1x00:DBAU1500 Thomas Lange <thomas@corelatus.se>
224 +++ b/include/configs/p661hnufx.h
227 + * Copyright (C) 2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
229 + * SPDX-License-Identifier: GPL-2.0+
235 +#define CONFIG_MACH_TYPE "P-661HNU-Fx"
236 +#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE
237 +#define CONFIG_BOARD_NAME "ZyXEL P-661HNU-Fx"
240 +#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */
242 +#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */
244 +#define CONFIG_LTQ_SUPPORT_SPI_FLASH
245 +#define CONFIG_SPI_FLASH_MACRONIX /* Supports Macronix serial flash */
246 +#define CONFIG_SPI_FLASH_4BYTE_MODE
248 +#define CONFIG_LTQ_SUPPORT_SPL_SPI_FLASH /* Build SPI flash SPL */
249 +#define CONFIG_LTQ_SPL_COMP_LZO /* Compress SPL with LZO */
250 +#define CONFIG_LTQ_SPL_CONSOLE /* Enable SPL console */
252 +#define CONFIG_SPL_SPI_BUS 0
253 +#define CONFIG_SPL_SPI_CS 4
254 +#define CONFIG_SPL_SPI_MAX_HZ 25000000
255 +#define CONFIG_SPL_SPI_MODE 0
257 +/* Switch devices */
258 +#define CONFIG_SWITCH_MULTI
259 +#define CONFIG_SWITCH_PSB697X
262 +#define CONFIG_ENV_SPI_BUS CONFIG_SPL_SPI_BUS
263 +#define CONFIG_ENV_SPI_CS CONFIG_SPL_SPI_CS
264 +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SPL_SPI_MAX_HZ
265 +#define CONFIG_ENV_SPI_MODE CONFIG_SPL_SPI_MODE
267 +#if defined(CONFIG_SYS_BOOT_SFSPL)
268 +#define CONFIG_ENV_IS_IN_SPI_FLASH
269 +#define CONFIG_ENV_OVERWRITE
270 +#define CONFIG_ENV_OFFSET (512 * 1024)
271 +#define CONFIG_ENV_SECT_SIZE (256 * 1024)
273 +#define CONFIG_ENV_IS_NOWHERE
276 +#define CONFIG_ENV_SIZE (8 * 1024)
277 +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
279 +#if defined(CONFIG_SYS_BOOT_ZYXEL)
280 +#define CONFIG_SYS_TEXT_BASE 0x80800000
281 +#define CONFIG_SKIP_LOWLEVEL_INIT
285 +#define CONFIG_LTQ_ADVANCED_CONSOLE
286 +#define CONFIG_BAUDRATE 115200
287 +#define CONFIG_CONSOLE_ASC 1
288 +#define CONFIG_CONSOLE_DEV "ttyLTQ1"
290 +/* Pull in default board configs for Lantiq XWAY Danube */
291 +#include <asm/lantiq/config.h>
292 +#include <asm/arch/config.h>
294 +/* Pull in default OpenWrt configs for Lantiq SoC */
295 +#include "openwrt-lantiq-common.h"
297 +#define CONFIG_ENV_UPDATE_UBOOT_SF \
298 + "update-uboot-sf=run load-uboot-sfspl-lzo write-uboot-sf\0"
300 +#define CONFIG_EXTRA_ENV_SETTINGS \
301 + CONFIG_ENV_LANTIQ_DEFAULTS \
302 + CONFIG_ENV_UPDATE_UBOOT_SF
304 +#endif /* __CONFIG_H */