target/linux/generic/files/drivers/net/phy/ar8216.c

   1 /*
   2  * ar8216.c: AR8216 switch driver
   3  *
   4  * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
   5  * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * as published by the Free Software Foundation; either version 2
  10  * of the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/if.h>
  19 #include <linux/module.h>
  20 #include <linux/init.h>
  21 #include <linux/list.h>
  22 #include <linux/if_ether.h>
  23 #include <linux/skbuff.h>
  24 #include <linux/netdevice.h>
  25 #include <linux/netlink.h>
  26 #include <linux/bitops.h>
  27 #include <net/genetlink.h>
  28 #include <linux/switch.h>
  29 #include <linux/delay.h>
  30 #include <linux/phy.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/lockdep.h>
  34 #include <linux/ar8216_platform.h>
  35 #include <linux/workqueue.h>
  36 #include <linux/of_device.h>
  37 #include <linux/leds.h>
  38 #include <linux/gpio.h>
  39 #include <linux/version.h>
  40
  41 #include "ar8216.h"
  42
  43 /* size of the vlan table */
  44 #define AR8X16_MAX_VLANS        128
  45 #define AR8X16_PROBE_RETRIES    10
  46 #define AR8X16_MAX_PORTS        8
  47
  48 #define AR8XXX_MIB_WORK_DELAY   2000 /* msecs */
  49
  50 struct ar8xxx_priv;
  51
  52 #define AR8XXX_CAP_GIGE                 BIT(0)
  53 #define AR8XXX_CAP_MIB_COUNTERS         BIT(1)
  54
  55 #define AR8XXX_NUM_PHYS         5
  56
  57 enum {
  58         AR8XXX_VER_AR8216 = 0x01,
  59         AR8XXX_VER_AR8236 = 0x03,
  60         AR8XXX_VER_AR8316 = 0x10,
  61         AR8XXX_VER_AR8327 = 0x12,
  62         AR8XXX_VER_AR8337 = 0x13,
  63 };
  64
  65 struct ar8xxx_mib_desc {
  66         unsigned int size;
  67         unsigned int offset;
  68         const char *name;
  69 };
  70
  71 struct ar8xxx_chip {
  72         unsigned long caps;
  73         bool config_at_probe;
  74
  75         int (*hw_init)(struct ar8xxx_priv *priv);
  76         void (*cleanup)(struct ar8xxx_priv *priv);
  77
  78         void (*init_globals)(struct ar8xxx_priv *priv);
  79         void (*init_port)(struct ar8xxx_priv *priv, int port);
  80         void (*setup_port)(struct ar8xxx_priv *priv, int port, u32 members);
  81         u32 (*read_port_status)(struct ar8xxx_priv *priv, int port);
  82         int (*atu_flush)(struct ar8xxx_priv *priv);
  83         void (*vtu_flush)(struct ar8xxx_priv *priv);
  84         void (*vtu_load_vlan)(struct ar8xxx_priv *priv, u32 vid, u32 port_mask);
  85         void (*phy_fixup)(struct ar8xxx_priv *priv, int phy);
  86
  87         const struct ar8xxx_mib_desc *mib_decs;
  88         unsigned num_mibs;
  89         unsigned mib_func;
  90 };
  91
  92 enum ar8327_led_pattern {
  93         AR8327_LED_PATTERN_OFF = 0,
  94         AR8327_LED_PATTERN_BLINK,
  95         AR8327_LED_PATTERN_ON,
  96         AR8327_LED_PATTERN_RULE,
  97 };
  98
  99 struct ar8327_led_entry {
 100         unsigned reg;
 101         unsigned shift;
 102 };
 103
 104 struct ar8327_led {
 105         struct led_classdev cdev;
 106         struct ar8xxx_priv *sw_priv;
 107
 108         char *name;
 109         bool active_low;
 110         u8 led_num;
 111         enum ar8327_led_mode mode;
 112
 113         struct mutex mutex;
 114         spinlock_t lock;
 115         struct work_struct led_work;
 116         bool enable_hw_mode;
 117         enum ar8327_led_pattern pattern;
 118 };
 119
 120 struct ar8327_data {
 121         u32 port0_status;
 122         u32 port6_status;
 123
 124         struct ar8327_led **leds;
 125         unsigned int num_leds;
 126 };
 127
 128 struct ar8xxx_priv {
 129         struct switch_dev dev;
 130         struct mii_bus *mii_bus;
 131         struct phy_device *phy;
 132
 133         u32 (*read)(struct ar8xxx_priv *priv, int reg);
 134         void (*write)(struct ar8xxx_priv *priv, int reg, u32 val);
 135         u32 (*rmw)(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val);
 136
 137         int (*get_port_link)(unsigned port);
 138
 139         const struct net_device_ops *ndo_old;
 140         struct net_device_ops ndo;
 141         struct mutex reg_mutex;
 142         u8 chip_ver;
 143         u8 chip_rev;
 144         const struct ar8xxx_chip *chip;
 145         union {
 146                 struct ar8327_data ar8327;
 147         } chip_data;
 148         bool initialized;
 149         bool port4_phy;
 150         char buf[2048];
 151
 152         bool init;
 153         bool mii_lo_first;
 154
 155         struct mutex mib_lock;
 156         struct delayed_work mib_work;
 157         int mib_next_port;
 158         u64 *mib_stats;
 159
 160         struct list_head list;
 161         unsigned int use_count;
 162
 163         /* all fields below are cleared on reset */
 164         bool vlan;
 165         u16 vlan_id[AR8X16_MAX_VLANS];
 166         u8 vlan_table[AR8X16_MAX_VLANS];
 167         u8 vlan_tagged;
 168         u16 pvid[AR8X16_MAX_PORTS];
 169
 170         /* mirroring */
 171         bool mirror_rx;
 172         bool mirror_tx;
 173         int source_port;
 174         int monitor_port;
 175 };
 176
 177 #define MIB_DESC(_s , _o, _n)   \
 178         {                       \
 179                 .size = (_s),   \
 180                 .offset = (_o), \
 181                 .name = (_n),   \
 182         }
 183
 184 static const struct ar8xxx_mib_desc ar8216_mibs[] = {
 185         MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
 186         MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
 187         MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
 188         MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
 189         MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
 190         MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
 191         MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
 192         MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
 193         MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
 194         MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
 195         MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
 196         MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
 197         MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
 198         MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
 199         MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
 200         MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
 201         MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
 202         MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
 203         MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
 204         MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
 205         MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
 206         MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
 207         MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
 208         MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
 209         MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
 210         MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
 211         MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
 212         MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
 213         MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
 214         MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
 215         MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
 216         MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
 217         MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
 218         MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
 219         MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
 220         MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
 221         MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
 222 };
 223
 224 static const struct ar8xxx_mib_desc ar8236_mibs[] = {
 225         MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
 226         MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
 227         MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"),
 228         MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
 229         MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
 230         MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"),
 231         MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
 232         MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
 233         MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
 234         MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
 235         MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
 236         MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
 237         MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
 238         MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
 239         MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
 240         MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
 241         MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
 242         MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
 243         MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"),
 244         MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"),
 245         MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"),
 246         MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"),
 247         MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
 248         MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
 249         MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
 250         MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
 251         MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
 252         MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
 253         MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
 254         MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
 255         MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
 256         MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"),
 257         MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
 258         MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
 259         MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
 260         MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
 261         MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
 262         MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"),
 263         MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
 264 };
 265
 266 static DEFINE_MUTEX(ar8xxx_dev_list_lock);
 267 static LIST_HEAD(ar8xxx_dev_list);
 268
 269 static inline struct ar8xxx_priv *
 270 swdev_to_ar8xxx(struct switch_dev *swdev)
 271 {
 272         return container_of(swdev, struct ar8xxx_priv, dev);
 273 }
 274
 275 static inline bool ar8xxx_has_gige(struct ar8xxx_priv *priv)
 276 {
 277         return priv->chip->caps & AR8XXX_CAP_GIGE;
 278 }
 279
 280 static inline bool ar8xxx_has_mib_counters(struct ar8xxx_priv *priv)
 281 {
 282         return priv->chip->caps & AR8XXX_CAP_MIB_COUNTERS;
 283 }
 284
 285 static inline bool chip_is_ar8216(struct ar8xxx_priv *priv)
 286 {
 287         return priv->chip_ver == AR8XXX_VER_AR8216;
 288 }
 289
 290 static inline bool chip_is_ar8236(struct ar8xxx_priv *priv)
 291 {
 292         return priv->chip_ver == AR8XXX_VER_AR8236;
 293 }
 294
 295 static inline bool chip_is_ar8316(struct ar8xxx_priv *priv)
 296 {
 297         return priv->chip_ver == AR8XXX_VER_AR8316;
 298 }
 299
 300 static inline bool chip_is_ar8327(struct ar8xxx_priv *priv)
 301 {
 302         return priv->chip_ver == AR8XXX_VER_AR8327;
 303 }
 304
 305 static inline bool chip_is_ar8337(struct ar8xxx_priv *priv)
 306 {
 307         return priv->chip_ver == AR8XXX_VER_AR8337;
 308 }
 309
 310 static inline void
 311 split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
 312 {
 313         regaddr >>= 1;
 314         *r1 = regaddr & 0x1e;
 315
 316         regaddr >>= 5;
 317         *r2 = regaddr & 0x7;
 318
 319         regaddr >>= 3;
 320         *page = regaddr & 0x1ff;
 321 }
 322
 323 /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
 324 static int
 325 ar8xxx_phy_poll_reset(struct mii_bus *bus)
 326 {
 327         unsigned int sleep_msecs = 20;
 328         int ret, elapsed, i;
 329
 330         for (elapsed = sleep_msecs; elapsed <= 600;
 331              elapsed += sleep_msecs) {
 332                 msleep(sleep_msecs);
 333                 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
 334                         ret = mdiobus_read(bus, i, MII_BMCR);
 335                         if (ret < 0)
 336                                 return ret;
 337                         if (ret & BMCR_RESET)
 338                                 break;
 339                         if (i == AR8XXX_NUM_PHYS - 1) {
 340                                 usleep_range(1000, 2000);
 341                                 return 0;
 342                         }
 343                 }
 344         }
 345         return -ETIMEDOUT;
 346 }
 347
 348 static int
 349 ar8xxx_phy_check_aneg(struct phy_device *phydev)
 350 {
 351         int ret;
 352
 353         if (phydev->autoneg != AUTONEG_ENABLE)
 354                 return 0;
 355         /*
 356          * BMCR_ANENABLE might have been cleared
 357          * by phy_init_hw in certain kernel versions
 358          * therefore check for it
 359          */
 360         ret = phy_read(phydev, MII_BMCR);
 361         if (ret < 0)
 362                 return ret;
 363         if (ret & BMCR_ANENABLE)
 364                 return 0;
 365
 366         dev_info(&phydev->dev, "ANEG disabled, re-enabling ...\n");
 367         ret |= BMCR_ANENABLE | BMCR_ANRESTART;
 368         return phy_write(phydev, MII_BMCR, ret);
 369 }
 370
 371 static void
 372 ar8xxx_phy_init(struct ar8xxx_priv *priv)
 373 {
 374         int i;
 375         struct mii_bus *bus;
 376
 377         bus = priv->mii_bus;
 378         for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
 379                 if (priv->chip->phy_fixup)
 380                         priv->chip->phy_fixup(priv, i);
 381
 382                 /* initialize the port itself */
 383                 mdiobus_write(bus, i, MII_ADVERTISE,
 384                         ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
 385                 if (ar8xxx_has_gige(priv))
 386                         mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
 387                 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
 388         }
 389
 390         ar8xxx_phy_poll_reset(bus);
 391 }
 392
 393 static u32
 394 ar8xxx_mii_read(struct ar8xxx_priv *priv, int reg)
 395 {
 396         struct mii_bus *bus = priv->mii_bus;
 397         u16 r1, r2, page;
 398         u16 lo, hi;
 399
 400         split_addr((u32) reg, &r1, &r2, &page);
 401
 402         mutex_lock(&bus->mdio_lock);
 403
 404         bus->write(bus, 0x18, 0, page);
 405         usleep_range(1000, 2000); /* wait for the page switch to propagate */
 406         lo = bus->read(bus, 0x10 | r2, r1);
 407         hi = bus->read(bus, 0x10 | r2, r1 + 1);
 408
 409         mutex_unlock(&bus->mdio_lock);
 410
 411         return (hi << 16) | lo;
 412 }
 413
 414 static void
 415 ar8xxx_mii_write(struct ar8xxx_priv *priv, int reg, u32 val)
 416 {
 417         struct mii_bus *bus = priv->mii_bus;
 418         u16 r1, r2, r3;
 419         u16 lo, hi;
 420
 421         split_addr((u32) reg, &r1, &r2, &r3);
 422         lo = val & 0xffff;
 423         hi = (u16) (val >> 16);
 424
 425         mutex_lock(&bus->mdio_lock);
 426
 427         bus->write(bus, 0x18, 0, r3);
 428         usleep_range(1000, 2000); /* wait for the page switch to propagate */
 429         if (priv->mii_lo_first) {
 430                 bus->write(bus, 0x10 | r2, r1, lo);
 431                 bus->write(bus, 0x10 | r2, r1 + 1, hi);
 432         } else {
 433                 bus->write(bus, 0x10 | r2, r1 + 1, hi);
 434                 bus->write(bus, 0x10 | r2, r1, lo);
 435         }
 436
 437         mutex_unlock(&bus->mdio_lock);
 438 }
 439
 440 static u32
 441 ar8xxx_mii_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
 442 {
 443         struct mii_bus *bus = priv->mii_bus;
 444         u16 r1, r2, page;
 445         u16 lo, hi;
 446         u32 ret;
 447
 448         split_addr((u32) reg, &r1, &r2, &page);
 449
 450         mutex_lock(&bus->mdio_lock);
 451
 452         bus->write(bus, 0x18, 0, page);
 453         usleep_range(1000, 2000); /* wait for the page switch to propagate */
 454
 455         lo = bus->read(bus, 0x10 | r2, r1);
 456         hi = bus->read(bus, 0x10 | r2, r1 + 1);
 457
 458         ret = hi << 16 | lo;
 459         ret &= ~mask;
 460         ret |= val;
 461
 462         lo = ret & 0xffff;
 463         hi = (u16) (ret >> 16);
 464
 465         if (priv->mii_lo_first) {
 466                 bus->write(bus, 0x10 | r2, r1, lo);
 467                 bus->write(bus, 0x10 | r2, r1 + 1, hi);
 468         } else {
 469                 bus->write(bus, 0x10 | r2, r1 + 1, hi);
 470                 bus->write(bus, 0x10 | r2, r1, lo);
 471         }
 472
 473         mutex_unlock(&bus->mdio_lock);
 474
 475         return ret;
 476 }
 477
 478
 479 static void
 480 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
 481                      u16 dbg_addr, u16 dbg_data)
 482 {
 483         struct mii_bus *bus = priv->mii_bus;
 484
 485         mutex_lock(&bus->mdio_lock);
 486         bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
 487         bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
 488         mutex_unlock(&bus->mdio_lock);
 489 }
 490
 491 static void
 492 ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 data)
 493 {
 494         struct mii_bus *bus = priv->mii_bus;
 495
 496         mutex_lock(&bus->mdio_lock);
 497         bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
 498         bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
 499         mutex_unlock(&bus->mdio_lock);
 500 }
 501
 502 static inline u32
 503 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
 504 {
 505         return priv->rmw(priv, reg, mask, val);
 506 }
 507
 508 static inline void
 509 ar8xxx_reg_set(struct ar8xxx_priv *priv, int reg, u32 val)
 510 {
 511         priv->rmw(priv, reg, 0, val);
 512 }
 513
 514 static int
 515 ar8xxx_reg_wait(struct ar8xxx_priv *priv, u32 reg, u32 mask, u32 val,
 516                 unsigned timeout)
 517 {
 518         int i;
 519
 520         for (i = 0; i < timeout; i++) {
 521                 u32 t;
 522
 523                 t = priv->read(priv, reg);
 524                 if ((t & mask) == val)
 525                         return 0;
 526
 527                 usleep_range(1000, 2000);
 528         }
 529
 530         return -ETIMEDOUT;
 531 }
 532
 533 static int
 534 ar8xxx_mib_op(struct ar8xxx_priv *priv, u32 op)
 535 {
 536         unsigned mib_func = priv->chip->mib_func;
 537         int ret;
 538
 539         lockdep_assert_held(&priv->mib_lock);
 540
 541         /* Capture the hardware statistics for all ports */
 542         ar8xxx_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
 543
 544         /* Wait for the capturing to complete. */
 545         ret = ar8xxx_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
 546         if (ret)
 547                 goto out;
 548
 549         ret = 0;
 550
 551 out:
 552         return ret;
 553 }
 554
 555 static int
 556 ar8xxx_mib_capture(struct ar8xxx_priv *priv)
 557 {
 558         return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
 559 }
 560
 561 static int
 562 ar8xxx_mib_flush(struct ar8xxx_priv *priv)
 563 {
 564         return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
 565 }
 566
 567 static void
 568 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush)
 569 {
 570         unsigned int base;
 571         u64 *mib_stats;
 572         int i;
 573
 574         WARN_ON(port >= priv->dev.ports);
 575
 576         lockdep_assert_held(&priv->mib_lock);
 577
 578         if (chip_is_ar8327(priv) || chip_is_ar8337(priv))
 579                 base = AR8327_REG_PORT_STATS_BASE(port);
 580         else if (chip_is_ar8236(priv) ||
 581                  chip_is_ar8316(priv))
 582                 base = AR8236_REG_PORT_STATS_BASE(port);
 583         else
 584                 base = AR8216_REG_PORT_STATS_BASE(port);
 585
 586         mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
 587         for (i = 0; i < priv->chip->num_mibs; i++) {
 588                 const struct ar8xxx_mib_desc *mib;
 589                 u64 t;
 590
 591                 mib = &priv->chip->mib_decs[i];
 592                 t = priv->read(priv, base + mib->offset);
 593                 if (mib->size == 2) {
 594                         u64 hi;
 595
 596                         hi = priv->read(priv, base + mib->offset + 4);
 597                         t |= hi << 32;
 598                 }
 599
 600                 if (flush)
 601                         mib_stats[i] = 0;
 602                 else
 603                         mib_stats[i] += t;
 604         }
 605 }
 606
 607 static void
 608 ar8216_read_port_link(struct ar8xxx_priv *priv, int port,
 609                       struct switch_port_link *link)
 610 {
 611         u32 status;
 612         u32 speed;
 613
 614         memset(link, '\0', sizeof(*link));
 615
 616         status = priv->chip->read_port_status(priv, port);
 617
 618         link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
 619         if (link->aneg) {
 620                 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
 621         } else {
 622                 link->link = true;
 623
 624                 if (priv->get_port_link) {
 625                         int err;
 626
 627                         err = priv->get_port_link(port);
 628                         if (err >= 0)
 629                                 link->link = !!err;
 630                 }
 631         }
 632
 633         if (!link->link)
 634                 return;
 635
 636         link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
 637         link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
 638         link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
 639
 640         speed = (status & AR8216_PORT_STATUS_SPEED) >>
 641                  AR8216_PORT_STATUS_SPEED_S;
 642
 643         switch (speed) {
 644         case AR8216_PORT_SPEED_10M:
 645                 link->speed = SWITCH_PORT_SPEED_10;
 646                 break;
 647         case AR8216_PORT_SPEED_100M:
 648                 link->speed = SWITCH_PORT_SPEED_100;
 649                 break;
 650         case AR8216_PORT_SPEED_1000M:
 651                 link->speed = SWITCH_PORT_SPEED_1000;
 652                 break;
 653         default:
 654                 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
 655                 break;
 656         }
 657 }
 658
 659 static struct sk_buff *
 660 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
 661 {
 662         struct ar8xxx_priv *priv = dev->phy_ptr;
 663         unsigned char *buf;
 664
 665         if (unlikely(!priv))
 666                 goto error;
 667
 668         if (!priv->vlan)
 669                 goto send;
 670
 671         if (unlikely(skb_headroom(skb) < 2)) {
 672                 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
 673                         goto error;
 674         }
 675
 676         buf = skb_push(skb, 2);
 677         buf[0] = 0x10;
 678         buf[1] = 0x80;
 679
 680 send:
 681         return skb;
 682
 683 error:
 684         dev_kfree_skb_any(skb);
 685         return NULL;
 686 }
 687
 688 static void
 689 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
 690 {
 691         struct ar8xxx_priv *priv;
 692         unsigned char *buf;
 693         int port, vlan;
 694
 695         priv = dev->phy_ptr;
 696         if (!priv)
 697                 return;
 698
 699         /* don't strip the header if vlan mode is disabled */
 700         if (!priv->vlan)
 701                 return;
 702
 703         /* strip header, get vlan id */
 704         buf = skb->data;
 705         skb_pull(skb, 2);
 706
 707         /* check for vlan header presence */
 708         if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
 709                 return;
 710
 711         port = buf[0] & 0xf;
 712
 713         /* no need to fix up packets coming from a tagged source */
 714         if (priv->vlan_tagged & (1 << port))
 715                 return;
 716
 717         /* lookup port vid from local table, the switch passes an invalid vlan id */
 718         vlan = priv->vlan_id[priv->pvid[port]];
 719
 720         buf[14 + 2] &= 0xf0;
 721         buf[14 + 2] |= vlan >> 8;
 722         buf[15 + 2] = vlan & 0xff;
 723 }
 724
 725 static int
 726 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
 727 {
 728         int timeout = 20;
 729         u32 t = 0;
 730
 731         while (1) {
 732                 t = priv->read(priv, reg);
 733                 if ((t & mask) == val)
 734                         return 0;
 735
 736                 if (timeout-- <= 0)
 737                         break;
 738
 739                 udelay(10);
 740         }
 741
 742         pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
 743                (unsigned int) reg, t, mask, val);
 744         return -ETIMEDOUT;
 745 }
 746
 747 static void
 748 ar8216_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
 749 {
 750         if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
 751                 return;
 752         if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
 753                 val &= AR8216_VTUDATA_MEMBER;
 754                 val |= AR8216_VTUDATA_VALID;
 755                 priv->write(priv, AR8216_REG_VTU_DATA, val);
 756         }
 757         op |= AR8216_VTU_ACTIVE;
 758         priv->write(priv, AR8216_REG_VTU, op);
 759 }
 760
 761 static void
 762 ar8216_vtu_flush(struct ar8xxx_priv *priv)
 763 {
 764         ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
 765 }
 766
 767 static void
 768 ar8216_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
 769 {
 770         u32 op;
 771
 772         op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
 773         ar8216_vtu_op(priv, op, port_mask);
 774 }
 775
 776 static int
 777 ar8216_atu_flush(struct ar8xxx_priv *priv)
 778 {
 779         int ret;
 780
 781         ret = ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0);
 782         if (!ret)
 783                 priv->write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH);
 784
 785         return ret;
 786 }
 787
 788 static u32
 789 ar8216_read_port_status(struct ar8xxx_priv *priv, int port)
 790 {
 791         return priv->read(priv, AR8216_REG_PORT_STATUS(port));
 792 }
 793
 794 static void
 795 ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
 796 {
 797         u32 header;
 798         u32 egress, ingress;
 799         u32 pvid;
 800
 801         if (priv->vlan) {
 802                 pvid = priv->vlan_id[priv->pvid[port]];
 803                 if (priv->vlan_tagged & (1 << port))
 804                         egress = AR8216_OUT_ADD_VLAN;
 805                 else
 806                         egress = AR8216_OUT_STRIP_VLAN;
 807                 ingress = AR8216_IN_SECURE;
 808         } else {
 809                 pvid = port;
 810                 egress = AR8216_OUT_KEEP;
 811                 ingress = AR8216_IN_PORT_ONLY;
 812         }
 813
 814         if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
 815                 header = AR8216_PORT_CTRL_HEADER;
 816         else
 817                 header = 0;
 818
 819         ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
 820                    AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
 821                    AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
 822                    AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
 823                    AR8216_PORT_CTRL_LEARN | header |
 824                    (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
 825                    (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
 826
 827         ar8xxx_rmw(priv, AR8216_REG_PORT_VLAN(port),
 828                    AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
 829                    AR8216_PORT_VLAN_DEFAULT_ID,
 830                    (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
 831                    (ingress << AR8216_PORT_VLAN_MODE_S) |
 832                    (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
 833 }
 834
 835 static int
 836 ar8216_hw_init(struct ar8xxx_priv *priv)
 837 {
 838         if (priv->initialized)
 839                 return 0;
 840
 841         ar8xxx_phy_init(priv);
 842
 843         priv->initialized = true;
 844         return 0;
 845 }
 846
 847 static void
 848 ar8216_init_globals(struct ar8xxx_priv *priv)
 849 {
 850         /* standard atheros magic */
 851         priv->write(priv, 0x38, 0xc000050e);
 852
 853         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
 854                    AR8216_GCTRL_MTU, 1518 + 8 + 2);
 855 }
 856
 857 static void
 858 ar8216_init_port(struct ar8xxx_priv *priv, int port)
 859 {
 860         /* Enable port learning and tx */
 861         priv->write(priv, AR8216_REG_PORT_CTRL(port),
 862                 AR8216_PORT_CTRL_LEARN |
 863                 (4 << AR8216_PORT_CTRL_STATE_S));
 864
 865         priv->write(priv, AR8216_REG_PORT_VLAN(port), 0);
 866
 867         if (port == AR8216_PORT_CPU) {
 868                 priv->write(priv, AR8216_REG_PORT_STATUS(port),
 869                         AR8216_PORT_STATUS_LINK_UP |
 870                         (ar8xxx_has_gige(priv) ?
 871                                 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
 872                         AR8216_PORT_STATUS_TXMAC |
 873                         AR8216_PORT_STATUS_RXMAC |
 874                         (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
 875                         (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
 876                         AR8216_PORT_STATUS_DUPLEX);
 877         } else {
 878                 priv->write(priv, AR8216_REG_PORT_STATUS(port),
 879                         AR8216_PORT_STATUS_LINK_AUTO);
 880         }
 881 }
 882
 883 static const struct ar8xxx_chip ar8216_chip = {
 884         .caps = AR8XXX_CAP_MIB_COUNTERS,
 885
 886         .hw_init = ar8216_hw_init,
 887         .init_globals = ar8216_init_globals,
 888         .init_port = ar8216_init_port,
 889         .setup_port = ar8216_setup_port,
 890         .read_port_status = ar8216_read_port_status,
 891         .atu_flush = ar8216_atu_flush,
 892         .vtu_flush = ar8216_vtu_flush,
 893         .vtu_load_vlan = ar8216_vtu_load_vlan,
 894
 895         .num_mibs = ARRAY_SIZE(ar8216_mibs),
 896         .mib_decs = ar8216_mibs,
 897         .mib_func = AR8216_REG_MIB_FUNC
 898 };
 899
 900 static void
 901 ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
 902 {
 903         u32 egress, ingress;
 904         u32 pvid;
 905
 906         if (priv->vlan) {
 907                 pvid = priv->vlan_id[priv->pvid[port]];
 908                 if (priv->vlan_tagged & (1 << port))
 909                         egress = AR8216_OUT_ADD_VLAN;
 910                 else
 911                         egress = AR8216_OUT_STRIP_VLAN;
 912                 ingress = AR8216_IN_SECURE;
 913         } else {
 914                 pvid = port;
 915                 egress = AR8216_OUT_KEEP;
 916                 ingress = AR8216_IN_PORT_ONLY;
 917         }
 918
 919         ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
 920                    AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
 921                    AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
 922                    AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
 923                    AR8216_PORT_CTRL_LEARN |
 924                    (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
 925                    (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
 926
 927         ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN(port),
 928                    AR8236_PORT_VLAN_DEFAULT_ID,
 929                    (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
 930
 931         ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN2(port),
 932                    AR8236_PORT_VLAN2_VLAN_MODE |
 933                    AR8236_PORT_VLAN2_MEMBER,
 934                    (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
 935                    (members << AR8236_PORT_VLAN2_MEMBER_S));
 936 }
 937
 938 static void
 939 ar8236_init_globals(struct ar8xxx_priv *priv)
 940 {
 941         /* enable jumbo frames */
 942         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
 943                    AR8316_GCTRL_MTU, 9018 + 8 + 2);
 944
 945         /* Enable MIB counters */
 946         ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
 947                    (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
 948                    AR8236_MIB_EN);
 949 }
 950
 951 static const struct ar8xxx_chip ar8236_chip = {
 952         .caps = AR8XXX_CAP_MIB_COUNTERS,
 953         .hw_init = ar8216_hw_init,
 954         .init_globals = ar8236_init_globals,
 955         .init_port = ar8216_init_port,
 956         .setup_port = ar8236_setup_port,
 957         .read_port_status = ar8216_read_port_status,
 958         .atu_flush = ar8216_atu_flush,
 959         .vtu_flush = ar8216_vtu_flush,
 960         .vtu_load_vlan = ar8216_vtu_load_vlan,
 961
 962         .num_mibs = ARRAY_SIZE(ar8236_mibs),
 963         .mib_decs = ar8236_mibs,
 964         .mib_func = AR8216_REG_MIB_FUNC
 965 };
 966
 967 static int
 968 ar8316_hw_init(struct ar8xxx_priv *priv)
 969 {
 970         u32 val, newval;
 971
 972         val = priv->read(priv, AR8316_REG_POSTRIP);
 973
 974         if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
 975                 if (priv->port4_phy) {
 976                         /* value taken from Ubiquiti RouterStation Pro */
 977                         newval = 0x81461bea;
 978                         pr_info("ar8316: Using port 4 as PHY\n");
 979                 } else {
 980                         newval = 0x01261be2;
 981                         pr_info("ar8316: Using port 4 as switch port\n");
 982                 }
 983         } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
 984                 /* value taken from AVM Fritz!Box 7390 sources */
 985                 newval = 0x010e5b71;
 986         } else {
 987                 /* no known value for phy interface */
 988                 pr_err("ar8316: unsupported mii mode: %d.\n",
 989                        priv->phy->interface);
 990                 return -EINVAL;
 991         }
 992
 993         if (val == newval)
 994                 goto out;
 995
 996         priv->write(priv, AR8316_REG_POSTRIP, newval);
 997
 998         if (priv->port4_phy &&
 999             priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
1000                 /* work around for phy4 rgmii mode */
1001                 ar8xxx_phy_dbg_write(priv, 4, 0x12, 0x480c);
1002                 /* rx delay */
1003                 ar8xxx_phy_dbg_write(priv, 4, 0x0, 0x824e);
1004                 /* tx delay */
1005                 ar8xxx_phy_dbg_write(priv, 4, 0x5, 0x3d47);
1006                 msleep(1000);
1007         }
1008
1009         ar8xxx_phy_init(priv);
1010
1011 out:
1012         priv->initialized = true;
1013         return 0;
1014 }
1015
1016 static void
1017 ar8316_init_globals(struct ar8xxx_priv *priv)
1018 {
1019         /* standard atheros magic */
1020         priv->write(priv, 0x38, 0xc000050e);
1021
1022         /* enable cpu port to receive multicast and broadcast frames */
1023         priv->write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
1024
1025         /* enable jumbo frames */
1026         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
1027                    AR8316_GCTRL_MTU, 9018 + 8 + 2);
1028
1029         /* Enable MIB counters */
1030         ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
1031                    (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
1032                    AR8236_MIB_EN);
1033 }
1034
1035 static const struct ar8xxx_chip ar8316_chip = {
1036         .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1037         .hw_init = ar8316_hw_init,
1038         .init_globals = ar8316_init_globals,
1039         .init_port = ar8216_init_port,
1040         .setup_port = ar8216_setup_port,
1041         .read_port_status = ar8216_read_port_status,
1042         .atu_flush = ar8216_atu_flush,
1043         .vtu_flush = ar8216_vtu_flush,
1044         .vtu_load_vlan = ar8216_vtu_load_vlan,
1045
1046         .num_mibs = ARRAY_SIZE(ar8236_mibs),
1047         .mib_decs = ar8236_mibs,
1048         .mib_func = AR8216_REG_MIB_FUNC
1049 };
1050
1051 static u32
1052 ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
1053 {
1054         u32 t;
1055
1056         if (!cfg)
1057                 return 0;
1058
1059         t = 0;
1060         switch (cfg->mode) {
1061         case AR8327_PAD_NC:
1062                 break;
1063
1064         case AR8327_PAD_MAC2MAC_MII:
1065                 t = AR8327_PAD_MAC_MII_EN;
1066                 if (cfg->rxclk_sel)
1067                         t |= AR8327_PAD_MAC_MII_RXCLK_SEL;
1068                 if (cfg->txclk_sel)
1069                         t |= AR8327_PAD_MAC_MII_TXCLK_SEL;
1070                 break;
1071
1072         case AR8327_PAD_MAC2MAC_GMII:
1073                 t = AR8327_PAD_MAC_GMII_EN;
1074                 if (cfg->rxclk_sel)
1075                         t |= AR8327_PAD_MAC_GMII_RXCLK_SEL;
1076                 if (cfg->txclk_sel)
1077                         t |= AR8327_PAD_MAC_GMII_TXCLK_SEL;
1078                 break;
1079
1080         case AR8327_PAD_MAC_SGMII:
1081                 t = AR8327_PAD_SGMII_EN;
1082
1083                 /*
1084                  * WAR for the QUalcomm Atheros AP136 board.
1085                  * It seems that RGMII TX/RX delay settings needs to be
1086                  * applied for SGMII mode as well, The ethernet is not
1087                  * reliable without this.
1088                  */
1089                 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
1090                 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
1091                 if (cfg->rxclk_delay_en)
1092                         t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
1093                 if (cfg->txclk_delay_en)
1094                         t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
1095
1096                 if (cfg->sgmii_delay_en)
1097                         t |= AR8327_PAD_SGMII_DELAY_EN;
1098
1099                 break;
1100
1101         case AR8327_PAD_MAC2PHY_MII:
1102                 t = AR8327_PAD_PHY_MII_EN;
1103                 if (cfg->rxclk_sel)
1104                         t |= AR8327_PAD_PHY_MII_RXCLK_SEL;
1105                 if (cfg->txclk_sel)
1106                         t |= AR8327_PAD_PHY_MII_TXCLK_SEL;
1107                 break;
1108
1109         case AR8327_PAD_MAC2PHY_GMII:
1110                 t = AR8327_PAD_PHY_GMII_EN;
1111                 if (cfg->pipe_rxclk_sel)
1112                         t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL;
1113                 if (cfg->rxclk_sel)
1114                         t |= AR8327_PAD_PHY_GMII_RXCLK_SEL;
1115                 if (cfg->txclk_sel)
1116                         t |= AR8327_PAD_PHY_GMII_TXCLK_SEL;
1117                 break;
1118
1119         case AR8327_PAD_MAC_RGMII:
1120                 t = AR8327_PAD_RGMII_EN;
1121                 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
1122                 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
1123                 if (cfg->rxclk_delay_en)
1124                         t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
1125                 if (cfg->txclk_delay_en)
1126                         t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
1127                 break;
1128
1129         case AR8327_PAD_PHY_GMII:
1130                 t = AR8327_PAD_PHYX_GMII_EN;
1131                 break;
1132
1133         case AR8327_PAD_PHY_RGMII:
1134                 t = AR8327_PAD_PHYX_RGMII_EN;
1135                 break;
1136
1137         case AR8327_PAD_PHY_MII:
1138                 t = AR8327_PAD_PHYX_MII_EN;
1139                 break;
1140         }
1141
1142         return t;
1143 }
1144
1145 static void
1146 ar8327_phy_fixup(struct ar8xxx_priv *priv, int phy)
1147 {
1148         switch (priv->chip_rev) {
1149         case 1:
1150                 /* For 100M waveform */
1151                 ar8xxx_phy_dbg_write(priv, phy, 0, 0x02ea);
1152                 /* Turn on Gigabit clock */
1153                 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x68a0);
1154                 break;
1155
1156         case 2:
1157                 ar8xxx_phy_mmd_write(priv, phy, 0x7, 0x3c);
1158                 ar8xxx_phy_mmd_write(priv, phy, 0x4007, 0x0);
1159                 /* fallthrough */
1160         case 4:
1161                 ar8xxx_phy_mmd_write(priv, phy, 0x3, 0x800d);
1162                 ar8xxx_phy_mmd_write(priv, phy, 0x4003, 0x803f);
1163
1164                 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x6860);
1165                 ar8xxx_phy_dbg_write(priv, phy, 0x5, 0x2c46);
1166                 ar8xxx_phy_dbg_write(priv, phy, 0x3c, 0x6000);
1167                 break;
1168         }
1169 }
1170
1171 static u32
1172 ar8327_get_port_init_status(struct ar8327_port_cfg *cfg)
1173 {
1174         u32 t;
1175
1176         if (!cfg->force_link)
1177                 return AR8216_PORT_STATUS_LINK_AUTO;
1178
1179         t = AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC;
1180         t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0;
1181         t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0;
1182         t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0;
1183
1184         switch (cfg->speed) {
1185         case AR8327_PORT_SPEED_10:
1186                 t |= AR8216_PORT_SPEED_10M;
1187                 break;
1188         case AR8327_PORT_SPEED_100:
1189                 t |= AR8216_PORT_SPEED_100M;
1190                 break;
1191         case AR8327_PORT_SPEED_1000:
1192                 t |= AR8216_PORT_SPEED_1000M;
1193                 break;
1194         }
1195
1196         return t;
1197 }
1198
1199 #define AR8327_LED_ENTRY(_num, _reg, _shift) \
1200         [_num] = { .reg = (_reg), .shift = (_shift) }
1201
1202 static const struct ar8327_led_entry
1203 ar8327_led_map[AR8327_NUM_LEDS] = {
1204         AR8327_LED_ENTRY(AR8327_LED_PHY0_0, 0, 14),
1205         AR8327_LED_ENTRY(AR8327_LED_PHY0_1, 1, 14),
1206         AR8327_LED_ENTRY(AR8327_LED_PHY0_2, 2, 14),
1207
1208         AR8327_LED_ENTRY(AR8327_LED_PHY1_0, 3, 8),
1209         AR8327_LED_ENTRY(AR8327_LED_PHY1_1, 3, 10),
1210         AR8327_LED_ENTRY(AR8327_LED_PHY1_2, 3, 12),
1211
1212         AR8327_LED_ENTRY(AR8327_LED_PHY2_0, 3, 14),
1213         AR8327_LED_ENTRY(AR8327_LED_PHY2_1, 3, 16),
1214         AR8327_LED_ENTRY(AR8327_LED_PHY2_2, 3, 18),
1215
1216         AR8327_LED_ENTRY(AR8327_LED_PHY3_0, 3, 20),
1217         AR8327_LED_ENTRY(AR8327_LED_PHY3_1, 3, 22),
1218         AR8327_LED_ENTRY(AR8327_LED_PHY3_2, 3, 24),
1219
1220         AR8327_LED_ENTRY(AR8327_LED_PHY4_0, 0, 30),
1221         AR8327_LED_ENTRY(AR8327_LED_PHY4_1, 1, 30),
1222         AR8327_LED_ENTRY(AR8327_LED_PHY4_2, 2, 30),
1223 };
1224
1225 static void
1226 ar8327_set_led_pattern(struct ar8xxx_priv *priv, unsigned int led_num,
1227                        enum ar8327_led_pattern pattern)
1228 {
1229         const struct ar8327_led_entry *entry;
1230
1231         entry = &ar8327_led_map[led_num];
1232         ar8xxx_rmw(priv, AR8327_REG_LED_CTRL(entry->reg),
1233                    (3 << entry->shift), pattern << entry->shift);
1234 }
1235
1236 static void
1237 ar8327_led_work_func(struct work_struct *work)
1238 {
1239         struct ar8327_led *aled;
1240         u8 pattern;
1241
1242         aled = container_of(work, struct ar8327_led, led_work);
1243
1244         spin_lock(&aled->lock);
1245         pattern = aled->pattern;
1246         spin_unlock(&aled->lock);
1247
1248         ar8327_set_led_pattern(aled->sw_priv, aled->led_num,
1249                                pattern);
1250 }
1251
1252 static void
1253 ar8327_led_schedule_change(struct ar8327_led *aled, u8 pattern)
1254 {
1255         if (aled->pattern == pattern)
1256                 return;
1257
1258         aled->pattern = pattern;
1259         schedule_work(&aled->led_work);
1260 }
1261
1262 static inline struct ar8327_led *
1263 led_cdev_to_ar8327_led(struct led_classdev *led_cdev)
1264 {
1265         return container_of(led_cdev, struct ar8327_led, cdev);
1266 }
1267
1268 static int
1269 ar8327_led_blink_set(struct led_classdev *led_cdev,
1270                      unsigned long *delay_on,
1271                      unsigned long *delay_off)
1272 {
1273         struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1274
1275         if (*delay_on == 0 && *delay_off == 0) {
1276                 *delay_on = 125;
1277                 *delay_off = 125;
1278         }
1279
1280         if (*delay_on != 125 || *delay_off != 125) {
1281                 /*
1282                  * The hardware only supports blinking at 4Hz. Fall back
1283                  * to software implementation in other cases.
1284                  */
1285                 return -EINVAL;
1286         }
1287
1288         spin_lock(&aled->lock);
1289
1290         aled->enable_hw_mode = false;
1291         ar8327_led_schedule_change(aled, AR8327_LED_PATTERN_BLINK);
1292
1293         spin_unlock(&aled->lock);
1294
1295         return 0;
1296 }
1297
1298 static void
1299 ar8327_led_set_brightness(struct led_classdev *led_cdev,
1300                           enum led_brightness brightness)
1301 {
1302         struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1303         u8 pattern;
1304         bool active;
1305
1306         active = (brightness != LED_OFF);
1307         active ^= aled->active_low;
1308
1309         pattern = (active) ? AR8327_LED_PATTERN_ON :
1310                              AR8327_LED_PATTERN_OFF;
1311
1312         spin_lock(&aled->lock);
1313
1314         aled->enable_hw_mode = false;
1315         ar8327_led_schedule_change(aled, pattern);
1316
1317         spin_unlock(&aled->lock);
1318 }
1319
1320 static ssize_t
1321 ar8327_led_enable_hw_mode_show(struct device *dev,
1322                                struct device_attribute *attr,
1323                                char *buf)
1324 {
1325         struct led_classdev *led_cdev = dev_get_drvdata(dev);
1326         struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1327         ssize_t ret = 0;
1328
1329         spin_lock(&aled->lock);
1330         ret += sprintf(buf, "%d\n", aled->enable_hw_mode);
1331         spin_unlock(&aled->lock);
1332
1333         return ret;
1334 }
1335
1336 static ssize_t
1337 ar8327_led_enable_hw_mode_store(struct device *dev,
1338                                 struct device_attribute *attr,
1339                                 const char *buf,
1340                                 size_t size)
1341 {
1342         struct led_classdev *led_cdev = dev_get_drvdata(dev);
1343         struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1344         u8 pattern;
1345         u8 value;
1346         int ret;
1347
1348         ret = kstrtou8(buf, 10, &value);
1349         if (ret < 0)
1350                 return -EINVAL;
1351
1352         spin_lock(&aled->lock);
1353
1354         aled->enable_hw_mode = !!value;
1355         if (aled->enable_hw_mode)
1356                 pattern = AR8327_LED_PATTERN_RULE;
1357         else
1358                 pattern = AR8327_LED_PATTERN_OFF;
1359
1360         ar8327_led_schedule_change(aled, pattern);
1361
1362         spin_unlock(&aled->lock);
1363
1364         return size;
1365 }
1366
1367 static DEVICE_ATTR(enable_hw_mode,  S_IRUGO | S_IWUSR,
1368                    ar8327_led_enable_hw_mode_show,
1369                    ar8327_led_enable_hw_mode_store);
1370
1371 static int
1372 ar8327_led_register(struct ar8xxx_priv *priv, struct ar8327_led *aled)
1373 {
1374         int ret;
1375
1376         ret = led_classdev_register(NULL, &aled->cdev);
1377         if (ret < 0)
1378                 return ret;
1379
1380         if (aled->mode == AR8327_LED_MODE_HW) {
1381                 ret = device_create_file(aled->cdev.dev,
1382                                          &dev_attr_enable_hw_mode);
1383                 if (ret)
1384                         goto err_unregister;
1385         }
1386
1387         return 0;
1388
1389 err_unregister:
1390         led_classdev_unregister(&aled->cdev);
1391         return ret;
1392 }
1393
1394 static void
1395 ar8327_led_unregister(struct ar8327_led *aled)
1396 {
1397         if (aled->mode == AR8327_LED_MODE_HW)
1398                 device_remove_file(aled->cdev.dev, &dev_attr_enable_hw_mode);
1399
1400         led_classdev_unregister(&aled->cdev);
1401         cancel_work_sync(&aled->led_work);
1402 }
1403
1404 static int
1405 ar8327_led_create(struct ar8xxx_priv *priv,
1406                   const struct ar8327_led_info *led_info)
1407 {
1408         struct ar8327_data *data = &priv->chip_data.ar8327;
1409         struct ar8327_led *aled;
1410         int ret;
1411
1412         if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
1413                 return 0;
1414
1415         if (!led_info->name)
1416                 return -EINVAL;
1417
1418         if (led_info->led_num >= AR8327_NUM_LEDS)
1419                 return -EINVAL;
1420
1421         aled = kzalloc(sizeof(*aled) + strlen(led_info->name) + 1,
1422                        GFP_KERNEL);
1423         if (!aled)
1424                 return -ENOMEM;
1425
1426         aled->sw_priv = priv;
1427         aled->led_num = led_info->led_num;
1428         aled->active_low = led_info->active_low;
1429         aled->mode = led_info->mode;
1430
1431         if (aled->mode == AR8327_LED_MODE_HW)
1432                 aled->enable_hw_mode = true;
1433
1434         aled->name = (char *)(aled + 1);
1435         strcpy(aled->name, led_info->name);
1436
1437         aled->cdev.name = aled->name;
1438         aled->cdev.brightness_set = ar8327_led_set_brightness;
1439         aled->cdev.blink_set = ar8327_led_blink_set;
1440         aled->cdev.default_trigger = led_info->default_trigger;
1441
1442         spin_lock_init(&aled->lock);
1443         mutex_init(&aled->mutex);
1444         INIT_WORK(&aled->led_work, ar8327_led_work_func);
1445
1446         ret = ar8327_led_register(priv, aled);
1447         if (ret)
1448                 goto err_free;
1449
1450         data->leds[data->num_leds++] = aled;
1451
1452         return 0;
1453
1454 err_free:
1455         kfree(aled);
1456         return ret;
1457 }
1458
1459 static void
1460 ar8327_led_destroy(struct ar8327_led *aled)
1461 {
1462         ar8327_led_unregister(aled);
1463         kfree(aled);
1464 }
1465
1466 static void
1467 ar8327_leds_init(struct ar8xxx_priv *priv)
1468 {
1469         struct ar8327_data *data;
1470         unsigned i;
1471
1472         if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
1473                 return;
1474
1475         data = &priv->chip_data.ar8327;
1476
1477         for (i = 0; i < data->num_leds; i++) {
1478                 struct ar8327_led *aled;
1479
1480                 aled = data->leds[i];
1481
1482                 if (aled->enable_hw_mode)
1483                         aled->pattern = AR8327_LED_PATTERN_RULE;
1484                 else
1485                         aled->pattern = AR8327_LED_PATTERN_OFF;
1486
1487                 ar8327_set_led_pattern(priv, aled->led_num, aled->pattern);
1488         }
1489 }
1490
1491 static void
1492 ar8327_leds_cleanup(struct ar8xxx_priv *priv)
1493 {
1494         struct ar8327_data *data = &priv->chip_data.ar8327;
1495         unsigned i;
1496
1497         if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
1498                 return;
1499
1500         for (i = 0; i < data->num_leds; i++) {
1501                 struct ar8327_led *aled;
1502
1503                 aled = data->leds[i];
1504                 ar8327_led_destroy(aled);
1505         }
1506
1507         kfree(data->leds);
1508 }
1509
1510 static int
1511 ar8327_hw_config_pdata(struct ar8xxx_priv *priv,
1512                        struct ar8327_platform_data *pdata)
1513 {
1514         struct ar8327_led_cfg *led_cfg;
1515         struct ar8327_data *data;
1516         u32 pos, new_pos;
1517         u32 t;
1518
1519         if (!pdata)
1520                 return -EINVAL;
1521
1522         priv->get_port_link = pdata->get_port_link;
1523
1524         data = &priv->chip_data.ar8327;
1525
1526         data->port0_status = ar8327_get_port_init_status(&pdata->port0_cfg);
1527         data->port6_status = ar8327_get_port_init_status(&pdata->port6_cfg);
1528
1529         t = ar8327_get_pad_cfg(pdata->pad0_cfg);
1530         if (chip_is_ar8337(priv))
1531                 t |= AR8337_PAD_MAC06_EXCHANGE_EN;
1532
1533         priv->write(priv, AR8327_REG_PAD0_MODE, t);
1534         t = ar8327_get_pad_cfg(pdata->pad5_cfg);
1535         priv->write(priv, AR8327_REG_PAD5_MODE, t);
1536         t = ar8327_get_pad_cfg(pdata->pad6_cfg);
1537         priv->write(priv, AR8327_REG_PAD6_MODE, t);
1538
1539         pos = priv->read(priv, AR8327_REG_POWER_ON_STRIP);
1540         new_pos = pos;
1541
1542         led_cfg = pdata->led_cfg;
1543         if (led_cfg) {
1544                 if (led_cfg->open_drain)
1545                         new_pos |= AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1546                 else
1547                         new_pos &= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1548
1549                 priv->write(priv, AR8327_REG_LED_CTRL0, led_cfg->led_ctrl0);
1550                 priv->write(priv, AR8327_REG_LED_CTRL1, led_cfg->led_ctrl1);
1551                 priv->write(priv, AR8327_REG_LED_CTRL2, led_cfg->led_ctrl2);
1552                 priv->write(priv, AR8327_REG_LED_CTRL3, led_cfg->led_ctrl3);
1553
1554                 if (new_pos != pos)
1555                         new_pos |= AR8327_POWER_ON_STRIP_POWER_ON_SEL;
1556         }
1557
1558         if (pdata->sgmii_cfg) {
1559                 t = pdata->sgmii_cfg->sgmii_ctrl;
1560                 if (priv->chip_rev == 1)
1561                         t |= AR8327_SGMII_CTRL_EN_PLL |
1562                              AR8327_SGMII_CTRL_EN_RX |
1563                              AR8327_SGMII_CTRL_EN_TX;
1564                 else
1565                         t &= ~(AR8327_SGMII_CTRL_EN_PLL |
1566                                AR8327_SGMII_CTRL_EN_RX |
1567                                AR8327_SGMII_CTRL_EN_TX);
1568
1569                 priv->write(priv, AR8327_REG_SGMII_CTRL, t);
1570
1571                 if (pdata->sgmii_cfg->serdes_aen)
1572                         new_pos &= ~AR8327_POWER_ON_STRIP_SERDES_AEN;
1573                 else
1574                         new_pos |= AR8327_POWER_ON_STRIP_SERDES_AEN;
1575         }
1576
1577         priv->write(priv, AR8327_REG_POWER_ON_STRIP, new_pos);
1578
1579         if (pdata->leds && pdata->num_leds) {
1580                 int i;
1581
1582                 data->leds = kzalloc(pdata->num_leds * sizeof(void *),
1583                                      GFP_KERNEL);
1584                 if (!data->leds)
1585                         return -ENOMEM;
1586
1587                 for (i = 0; i < pdata->num_leds; i++)
1588                         ar8327_led_create(priv, &pdata->leds[i]);
1589         }
1590
1591         return 0;
1592 }
1593
1594 #ifdef CONFIG_OF
1595 static int
1596 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
1597 {
1598         const __be32 *paddr;
1599         int len;
1600         int i;
1601
1602         paddr = of_get_property(np, "qca,ar8327-initvals", &len);
1603         if (!paddr || len < (2 * sizeof(*paddr)))
1604                 return -EINVAL;
1605
1606         len /= sizeof(*paddr);
1607
1608         for (i = 0; i < len - 1; i += 2) {
1609                 u32 reg;
1610                 u32 val;
1611
1612                 reg = be32_to_cpup(paddr + i);
1613                 val = be32_to_cpup(paddr + i + 1);
1614
1615                 switch (reg) {
1616                 case AR8327_REG_PORT_STATUS(0):
1617                         priv->chip_data.ar8327.port0_status = val;
1618                         break;
1619                 case AR8327_REG_PORT_STATUS(6):
1620                         priv->chip_data.ar8327.port6_status = val;
1621                         break;
1622                 default:
1623                         priv->write(priv, reg, val);
1624                         break;
1625                 }
1626         }
1627
1628         return 0;
1629 }
1630 #else
1631 static inline int
1632 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
1633 {
1634         return -EINVAL;
1635 }
1636 #endif
1637
1638 static int
1639 ar8327_hw_init(struct ar8xxx_priv *priv)
1640 {
1641         int ret;
1642
1643         if (priv->phy->dev.of_node)
1644                 ret = ar8327_hw_config_of(priv, priv->phy->dev.of_node);
1645         else
1646                 ret = ar8327_hw_config_pdata(priv,
1647                                              priv->phy->dev.platform_data);
1648
1649         if (ret)
1650                 return ret;
1651
1652         ar8327_leds_init(priv);
1653
1654         ar8xxx_phy_init(priv);
1655
1656         return 0;
1657 }
1658
1659 static void
1660 ar8327_cleanup(struct ar8xxx_priv *priv)
1661 {
1662         ar8327_leds_cleanup(priv);
1663 }
1664
1665 static void
1666 ar8327_init_globals(struct ar8xxx_priv *priv)
1667 {
1668         u32 t;
1669
1670         /* enable CPU port and disable mirror port */
1671         t = AR8327_FWD_CTRL0_CPU_PORT_EN |
1672             AR8327_FWD_CTRL0_MIRROR_PORT;
1673         priv->write(priv, AR8327_REG_FWD_CTRL0, t);
1674
1675         /* forward multicast and broadcast frames to CPU */
1676         t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) |
1677             (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) |
1678             (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S);
1679         priv->write(priv, AR8327_REG_FWD_CTRL1, t);
1680
1681         /* enable jumbo frames */
1682         ar8xxx_rmw(priv, AR8327_REG_MAX_FRAME_SIZE,
1683                    AR8327_MAX_FRAME_SIZE_MTU, 9018 + 8 + 2);
1684
1685         /* Enable MIB counters */
1686         ar8xxx_reg_set(priv, AR8327_REG_MODULE_EN,
1687                        AR8327_MODULE_EN_MIB);
1688
1689         /* Disable EEE on all ports due to stability issues */
1690         t = priv->read(priv, AR8327_REG_EEE_CTRL);
1691         t |= AR8327_EEE_CTRL_DISABLE_PHY(0) |
1692              AR8327_EEE_CTRL_DISABLE_PHY(1) |
1693              AR8327_EEE_CTRL_DISABLE_PHY(2) |
1694              AR8327_EEE_CTRL_DISABLE_PHY(3) |
1695              AR8327_EEE_CTRL_DISABLE_PHY(4);
1696         priv->write(priv, AR8327_REG_EEE_CTRL, t);
1697 }
1698
1699 static void
1700 ar8327_init_port(struct ar8xxx_priv *priv, int port)
1701 {
1702         u32 t;
1703
1704         if (port == AR8216_PORT_CPU)
1705                 t = priv->chip_data.ar8327.port0_status;
1706         else if (port == 6)
1707                 t = priv->chip_data.ar8327.port6_status;
1708         else
1709                 t = AR8216_PORT_STATUS_LINK_AUTO;
1710
1711         priv->write(priv, AR8327_REG_PORT_STATUS(port), t);
1712         priv->write(priv, AR8327_REG_PORT_HEADER(port), 0);
1713
1714         t = 1 << AR8327_PORT_VLAN0_DEF_SVID_S;
1715         t |= 1 << AR8327_PORT_VLAN0_DEF_CVID_S;
1716         priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1717
1718         t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S;
1719         priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1720
1721         t = AR8327_PORT_LOOKUP_LEARN;
1722         t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1723         priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1724 }
1725
1726 static u32
1727 ar8327_read_port_status(struct ar8xxx_priv *priv, int port)
1728 {
1729         return priv->read(priv, AR8327_REG_PORT_STATUS(port));
1730 }
1731
1732 static int
1733 ar8327_atu_flush(struct ar8xxx_priv *priv)
1734 {
1735         int ret;
1736
1737         ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
1738                               AR8327_ATU_FUNC_BUSY, 0);
1739         if (!ret)
1740                 priv->write(priv, AR8327_REG_ATU_FUNC,
1741                             AR8327_ATU_FUNC_OP_FLUSH);
1742
1743         return ret;
1744 }
1745
1746 static void
1747 ar8327_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
1748 {
1749         if (ar8216_wait_bit(priv, AR8327_REG_VTU_FUNC1,
1750                             AR8327_VTU_FUNC1_BUSY, 0))
1751                 return;
1752
1753         if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD)
1754                 priv->write(priv, AR8327_REG_VTU_FUNC0, val);
1755
1756         op |= AR8327_VTU_FUNC1_BUSY;
1757         priv->write(priv, AR8327_REG_VTU_FUNC1, op);
1758 }
1759
1760 static void
1761 ar8327_vtu_flush(struct ar8xxx_priv *priv)
1762 {
1763         ar8327_vtu_op(priv, AR8327_VTU_FUNC1_OP_FLUSH, 0);
1764 }
1765
1766 static void
1767 ar8327_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
1768 {
1769         u32 op;
1770         u32 val;
1771         int i;
1772
1773         op = AR8327_VTU_FUNC1_OP_LOAD | (vid << AR8327_VTU_FUNC1_VID_S);
1774         val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL;
1775         for (i = 0; i < AR8327_NUM_PORTS; i++) {
1776                 u32 mode;
1777
1778                 if ((port_mask & BIT(i)) == 0)
1779                         mode = AR8327_VTU_FUNC0_EG_MODE_NOT;
1780                 else if (priv->vlan == 0)
1781                         mode = AR8327_VTU_FUNC0_EG_MODE_KEEP;
1782                 else if ((priv->vlan_tagged & BIT(i)) || (priv->vlan_id[priv->pvid[i]] != vid))
1783                         mode = AR8327_VTU_FUNC0_EG_MODE_TAG;
1784                 else
1785                         mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG;
1786
1787                 val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i);
1788         }
1789         ar8327_vtu_op(priv, op, val);
1790 }
1791
1792 static void
1793 ar8327_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
1794 {
1795         u32 t;
1796         u32 egress, ingress;
1797         u32 pvid = priv->vlan_id[priv->pvid[port]];
1798
1799         if (priv->vlan) {
1800                 egress = AR8327_PORT_VLAN1_OUT_MODE_UNMOD;
1801                 ingress = AR8216_IN_SECURE;
1802         } else {
1803                 egress = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;
1804                 ingress = AR8216_IN_PORT_ONLY;
1805         }
1806
1807         t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S;
1808         t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S;
1809         priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1810
1811         t = AR8327_PORT_VLAN1_PORT_VLAN_PROP;
1812         t |= egress << AR8327_PORT_VLAN1_OUT_MODE_S;
1813         priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1814
1815         t = members;
1816         t |= AR8327_PORT_LOOKUP_LEARN;
1817         t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S;
1818         t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1819         priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1820 }
1821
1822 static const struct ar8xxx_chip ar8327_chip = {
1823         .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1824         .config_at_probe = true,
1825         .hw_init = ar8327_hw_init,
1826         .cleanup = ar8327_cleanup,
1827         .init_globals = ar8327_init_globals,
1828         .init_port = ar8327_init_port,
1829         .setup_port = ar8327_setup_port,
1830         .read_port_status = ar8327_read_port_status,
1831         .atu_flush = ar8327_atu_flush,
1832         .vtu_flush = ar8327_vtu_flush,
1833         .vtu_load_vlan = ar8327_vtu_load_vlan,
1834         .phy_fixup = ar8327_phy_fixup,
1835
1836         .num_mibs = ARRAY_SIZE(ar8236_mibs),
1837         .mib_decs = ar8236_mibs,
1838         .mib_func = AR8327_REG_MIB_FUNC
1839 };
1840
1841 static int
1842 ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1843                    struct switch_val *val)
1844 {
1845         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1846         priv->vlan = !!val->value.i;
1847         return 0;
1848 }
1849
1850 static int
1851 ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1852                    struct switch_val *val)
1853 {
1854         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1855         val->value.i = priv->vlan;
1856         return 0;
1857 }
1858
1859
1860 static int
1861 ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
1862 {
1863         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1864
1865         /* make sure no invalid PVIDs get set */
1866
1867         if (vlan >= dev->vlans)
1868                 return -EINVAL;
1869
1870         priv->pvid[port] = vlan;
1871         return 0;
1872 }
1873
1874 static int
1875 ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
1876 {
1877         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1878         *vlan = priv->pvid[port];
1879         return 0;
1880 }
1881
1882 static int
1883 ar8xxx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
1884                   struct switch_val *val)
1885 {
1886         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1887         priv->vlan_id[val->port_vlan] = val->value.i;
1888         return 0;
1889 }
1890
1891 static int
1892 ar8xxx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
1893                   struct switch_val *val)
1894 {
1895         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1896         val->value.i = priv->vlan_id[val->port_vlan];
1897         return 0;
1898 }
1899
1900 static int
1901 ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
1902                         struct switch_port_link *link)
1903 {
1904         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1905
1906         ar8216_read_port_link(priv, port, link);
1907         return 0;
1908 }
1909
1910 static int
1911 ar8xxx_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1912 {
1913         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1914         u8 ports = priv->vlan_table[val->port_vlan];
1915         int i;
1916
1917         val->len = 0;
1918         for (i = 0; i < dev->ports; i++) {
1919                 struct switch_port *p;
1920
1921                 if (!(ports & (1 << i)))
1922                         continue;
1923
1924                 p = &val->value.ports[val->len++];
1925                 p->id = i;
1926                 if (priv->vlan_tagged & (1 << i))
1927                         p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1928                 else
1929                         p->flags = 0;
1930         }
1931         return 0;
1932 }
1933
1934 static int
1935 ar8327_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1936 {
1937         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1938         u8 ports = priv->vlan_table[val->port_vlan];
1939         int i;
1940
1941         val->len = 0;
1942         for (i = 0; i < dev->ports; i++) {
1943                 struct switch_port *p;
1944
1945                 if (!(ports & (1 << i)))
1946                         continue;
1947
1948                 p = &val->value.ports[val->len++];
1949                 p->id = i;
1950                 if ((priv->vlan_tagged & (1 << i)) || (priv->pvid[i] != val->port_vlan))
1951                         p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1952                 else
1953                         p->flags = 0;
1954         }
1955         return 0;
1956 }
1957
1958 static int
1959 ar8xxx_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1960 {
1961         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1962         u8 *vt = &priv->vlan_table[val->port_vlan];
1963         int i, j;
1964
1965         *vt = 0;
1966         for (i = 0; i < val->len; i++) {
1967                 struct switch_port *p = &val->value.ports[i];
1968
1969                 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1970                         priv->vlan_tagged |= (1 << p->id);
1971                 } else {
1972                         priv->vlan_tagged &= ~(1 << p->id);
1973                         priv->pvid[p->id] = val->port_vlan;
1974
1975                         /* make sure that an untagged port does not
1976                          * appear in other vlans */
1977                         for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1978                                 if (j == val->port_vlan)
1979                                         continue;
1980                                 priv->vlan_table[j] &= ~(1 << p->id);
1981                         }
1982                 }
1983
1984                 *vt |= 1 << p->id;
1985         }
1986         return 0;
1987 }
1988
1989 static int
1990 ar8327_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1991 {
1992         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1993         u8 *vt = &priv->vlan_table[val->port_vlan];
1994         int i;
1995
1996         *vt = 0;
1997         for (i = 0; i < val->len; i++) {
1998                 struct switch_port *p = &val->value.ports[i];
1999
2000                 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
2001                         if (val->port_vlan == priv->pvid[p->id]) {
2002                                 priv->vlan_tagged |= (1 << p->id);
2003                         }
2004                 } else {
2005                         priv->vlan_tagged &= ~(1 << p->id);
2006                         priv->pvid[p->id] = val->port_vlan;
2007                 }
2008
2009                 *vt |= 1 << p->id;
2010         }
2011         return 0;
2012 }
2013
2014 static void
2015 ar8327_set_mirror_regs(struct ar8xxx_priv *priv)
2016 {
2017         int port;
2018
2019         /* reset all mirror registers */
2020         ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
2021                    AR8327_FWD_CTRL0_MIRROR_PORT,
2022                    (0xF << AR8327_FWD_CTRL0_MIRROR_PORT_S));
2023         for (port = 0; port < AR8327_NUM_PORTS; port++) {
2024                 ar8xxx_rmw(priv, AR8327_REG_PORT_LOOKUP(port),
2025                            AR8327_PORT_LOOKUP_ING_MIRROR_EN,
2026                            0);
2027
2028                 ar8xxx_rmw(priv, AR8327_REG_PORT_HOL_CTRL1(port),
2029                            AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN,
2030                            0);
2031         }
2032
2033         /* now enable mirroring if necessary */
2034         if (priv->source_port >= AR8327_NUM_PORTS ||
2035             priv->monitor_port >= AR8327_NUM_PORTS ||
2036             priv->source_port == priv->monitor_port) {
2037                 return;
2038         }
2039
2040         ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
2041                    AR8327_FWD_CTRL0_MIRROR_PORT,
2042                    (priv->monitor_port << AR8327_FWD_CTRL0_MIRROR_PORT_S));
2043
2044         if (priv->mirror_rx)
2045                 ar8xxx_rmw(priv, AR8327_REG_PORT_LOOKUP(priv->source_port),
2046                            AR8327_PORT_LOOKUP_ING_MIRROR_EN,
2047                            AR8327_PORT_LOOKUP_ING_MIRROR_EN);
2048
2049         if (priv->mirror_tx)
2050                 ar8xxx_rmw(priv, AR8327_REG_PORT_HOL_CTRL1(priv->source_port),
2051                            AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN,
2052                            AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN);
2053 }
2054
2055 static void
2056 ar8216_set_mirror_regs(struct ar8xxx_priv *priv)
2057 {
2058         int port;
2059
2060         /* reset all mirror registers */
2061         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
2062                    AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
2063                    (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
2064         for (port = 0; port < AR8216_NUM_PORTS; port++) {
2065                 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
2066                            AR8216_PORT_CTRL_MIRROR_RX,
2067                            0);
2068
2069                 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
2070                            AR8216_PORT_CTRL_MIRROR_TX,
2071                            0);
2072         }
2073
2074         /* now enable mirroring if necessary */
2075         if (priv->source_port >= AR8216_NUM_PORTS ||
2076             priv->monitor_port >= AR8216_NUM_PORTS ||
2077             priv->source_port == priv->monitor_port) {
2078                 return;
2079         }
2080
2081         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
2082                    AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
2083                    (priv->monitor_port << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
2084
2085         if (priv->mirror_rx)
2086                 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(priv->source_port),
2087                            AR8216_PORT_CTRL_MIRROR_RX,
2088                            AR8216_PORT_CTRL_MIRROR_RX);
2089
2090         if (priv->mirror_tx)
2091                 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(priv->source_port),
2092                            AR8216_PORT_CTRL_MIRROR_TX,
2093                            AR8216_PORT_CTRL_MIRROR_TX);
2094 }
2095
2096 static void
2097 ar8xxx_set_mirror_regs(struct ar8xxx_priv *priv)
2098 {
2099         if (chip_is_ar8327(priv) || chip_is_ar8337(priv)) {
2100                 ar8327_set_mirror_regs(priv);
2101         } else {
2102                 ar8216_set_mirror_regs(priv);
2103         }
2104 }
2105
2106 static int
2107 ar8xxx_sw_hw_apply(struct switch_dev *dev)
2108 {
2109         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2110         u8 portmask[AR8X16_MAX_PORTS];
2111         int i, j;
2112
2113         mutex_lock(&priv->reg_mutex);
2114         /* flush all vlan translation unit entries */
2115         priv->chip->vtu_flush(priv);
2116
2117         memset(portmask, 0, sizeof(portmask));
2118         if (!priv->init) {
2119                 /* calculate the port destination masks and load vlans
2120                  * into the vlan translation unit */
2121                 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
2122                         u8 vp = priv->vlan_table[j];
2123
2124                         if (!vp)
2125                                 continue;
2126
2127                         for (i = 0; i < dev->ports; i++) {
2128                                 u8 mask = (1 << i);
2129                                 if (vp & mask)
2130                                         portmask[i] |= vp & ~mask;
2131                         }
2132
2133                         priv->chip->vtu_load_vlan(priv, priv->vlan_id[j],
2134                                                  priv->vlan_table[j]);
2135                 }
2136         } else {
2137                 /* vlan disabled:
2138                  * isolate all ports, but connect them to the cpu port */
2139                 for (i = 0; i < dev->ports; i++) {
2140                         if (i == AR8216_PORT_CPU)
2141                                 continue;
2142
2143                         portmask[i] = 1 << AR8216_PORT_CPU;
2144                         portmask[AR8216_PORT_CPU] |= (1 << i);
2145                 }
2146         }
2147
2148         /* update the port destination mask registers and tag settings */
2149         for (i = 0; i < dev->ports; i++) {
2150                 priv->chip->setup_port(priv, i, portmask[i]);
2151         }
2152
2153         ar8xxx_set_mirror_regs(priv);
2154
2155         mutex_unlock(&priv->reg_mutex);
2156         return 0;
2157 }
2158
2159 static int
2160 ar8xxx_sw_reset_switch(struct switch_dev *dev)
2161 {
2162         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2163         int i;
2164
2165         mutex_lock(&priv->reg_mutex);
2166         memset(&priv->vlan, 0, sizeof(struct ar8xxx_priv) -
2167                 offsetof(struct ar8xxx_priv, vlan));
2168
2169         for (i = 0; i < AR8X16_MAX_VLANS; i++)
2170                 priv->vlan_id[i] = i;
2171
2172         /* Configure all ports */
2173         for (i = 0; i < dev->ports; i++)
2174                 priv->chip->init_port(priv, i);
2175
2176         priv->mirror_rx = false;
2177         priv->mirror_tx = false;
2178         priv->source_port = 0;
2179         priv->monitor_port = 0;
2180
2181         priv->chip->init_globals(priv);
2182
2183         mutex_unlock(&priv->reg_mutex);
2184
2185         return ar8xxx_sw_hw_apply(dev);
2186 }
2187
2188 static int
2189 ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
2190                          const struct switch_attr *attr,
2191                          struct switch_val *val)
2192 {
2193         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2194         unsigned int len;
2195         int ret;
2196
2197         if (!ar8xxx_has_mib_counters(priv))
2198                 return -EOPNOTSUPP;
2199
2200         mutex_lock(&priv->mib_lock);
2201
2202         len = priv->dev.ports * priv->chip->num_mibs *
2203               sizeof(*priv->mib_stats);
2204         memset(priv->mib_stats, '\0', len);
2205         ret = ar8xxx_mib_flush(priv);
2206         if (ret)
2207                 goto unlock;
2208
2209         ret = 0;
2210
2211 unlock:
2212         mutex_unlock(&priv->mib_lock);
2213         return ret;
2214 }
2215
2216 static int
2217 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
2218                                const struct switch_attr *attr,
2219                                struct switch_val *val)
2220 {
2221         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2222
2223         mutex_lock(&priv->reg_mutex);
2224         priv->mirror_rx = !!val->value.i;
2225         ar8xxx_set_mirror_regs(priv);
2226         mutex_unlock(&priv->reg_mutex);
2227
2228         return 0;
2229 }
2230
2231 static int
2232 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,
2233                                const struct switch_attr *attr,
2234                                struct switch_val *val)
2235 {
2236         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2237         val->value.i = priv->mirror_rx;
2238         return 0;
2239 }
2240
2241 static int
2242 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,
2243                                const struct switch_attr *attr,
2244                                struct switch_val *val)
2245 {
2246         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2247
2248         mutex_lock(&priv->reg_mutex);
2249         priv->mirror_tx = !!val->value.i;
2250         ar8xxx_set_mirror_regs(priv);
2251         mutex_unlock(&priv->reg_mutex);
2252
2253         return 0;
2254 }
2255
2256 static int
2257 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,
2258                                const struct switch_attr *attr,
2259                                struct switch_val *val)
2260 {
2261         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2262         val->value.i = priv->mirror_tx;
2263         return 0;
2264 }
2265
2266 static int
2267 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,
2268                                   const struct switch_attr *attr,
2269                                   struct switch_val *val)
2270 {
2271         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2272
2273         mutex_lock(&priv->reg_mutex);
2274         priv->monitor_port = val->value.i;
2275         ar8xxx_set_mirror_regs(priv);
2276         mutex_unlock(&priv->reg_mutex);
2277
2278         return 0;
2279 }
2280
2281 static int
2282 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,
2283                                   const struct switch_attr *attr,
2284                                   struct switch_val *val)
2285 {
2286         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2287         val->value.i = priv->monitor_port;
2288         return 0;
2289 }
2290
2291 static int
2292 ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,
2293                                  const struct switch_attr *attr,
2294                                  struct switch_val *val)
2295 {
2296         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2297
2298         mutex_lock(&priv->reg_mutex);
2299         priv->source_port = val->value.i;
2300         ar8xxx_set_mirror_regs(priv);
2301         mutex_unlock(&priv->reg_mutex);
2302
2303         return 0;
2304 }
2305
2306 static int
2307 ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,
2308                                  const struct switch_attr *attr,
2309                                  struct switch_val *val)
2310 {
2311         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2312         val->value.i = priv->source_port;
2313         return 0;
2314 }
2315
2316 static int
2317 ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
2318                              const struct switch_attr *attr,
2319                              struct switch_val *val)
2320 {
2321         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2322         int port;
2323         int ret;
2324
2325         if (!ar8xxx_has_mib_counters(priv))
2326                 return -EOPNOTSUPP;
2327
2328         port = val->port_vlan;
2329         if (port >= dev->ports)
2330                 return -EINVAL;
2331
2332         mutex_lock(&priv->mib_lock);
2333         ret = ar8xxx_mib_capture(priv);
2334         if (ret)
2335                 goto unlock;
2336
2337         ar8xxx_mib_fetch_port_stat(priv, port, true);
2338
2339         ret = 0;
2340
2341 unlock:
2342         mutex_unlock(&priv->mib_lock);
2343         return ret;
2344 }
2345
2346 static int
2347 ar8xxx_sw_get_port_mib(struct switch_dev *dev,
2348                        const struct switch_attr *attr,
2349                        struct switch_val *val)
2350 {
2351         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2352         const struct ar8xxx_chip *chip = priv->chip;
2353         u64 *mib_stats;
2354         int port;
2355         int ret;
2356         char *buf = priv->buf;
2357         int i, len = 0;
2358
2359         if (!ar8xxx_has_mib_counters(priv))
2360                 return -EOPNOTSUPP;
2361
2362         port = val->port_vlan;
2363         if (port >= dev->ports)
2364                 return -EINVAL;
2365
2366         mutex_lock(&priv->mib_lock);
2367         ret = ar8xxx_mib_capture(priv);
2368         if (ret)
2369                 goto unlock;
2370
2371         ar8xxx_mib_fetch_port_stat(priv, port, false);
2372
2373         len += snprintf(buf + len, sizeof(priv->buf) - len,
2374                         "Port %d MIB counters\n",
2375                         port);
2376
2377         mib_stats = &priv->mib_stats[port * chip->num_mibs];
2378         for (i = 0; i < chip->num_mibs; i++)
2379                 len += snprintf(buf + len, sizeof(priv->buf) - len,
2380                                 "%-12s: %llu\n",
2381                                 chip->mib_decs[i].name,
2382                                 mib_stats[i]);
2383
2384         val->value.s = buf;
2385         val->len = len;
2386
2387         ret = 0;
2388
2389 unlock:
2390         mutex_unlock(&priv->mib_lock);
2391         return ret;
2392 }
2393
2394 static struct switch_attr ar8xxx_sw_attr_globals[] = {
2395         {
2396                 .type = SWITCH_TYPE_INT,
2397                 .name = "enable_vlan",
2398                 .description = "Enable VLAN mode",
2399                 .set = ar8xxx_sw_set_vlan,
2400                 .get = ar8xxx_sw_get_vlan,
2401                 .max = 1
2402         },
2403         {
2404                 .type = SWITCH_TYPE_NOVAL,
2405                 .name = "reset_mibs",
2406                 .description = "Reset all MIB counters",
2407                 .set = ar8xxx_sw_set_reset_mibs,
2408         },
2409         {
2410                 .type = SWITCH_TYPE_INT,
2411                 .name = "enable_mirror_rx",
2412                 .description = "Enable mirroring of RX packets",
2413                 .set = ar8xxx_sw_set_mirror_rx_enable,
2414                 .get = ar8xxx_sw_get_mirror_rx_enable,
2415                 .max = 1
2416         },
2417         {
2418                 .type = SWITCH_TYPE_INT,
2419                 .name = "enable_mirror_tx",
2420                 .description = "Enable mirroring of TX packets",
2421                 .set = ar8xxx_sw_set_mirror_tx_enable,
2422                 .get = ar8xxx_sw_get_mirror_tx_enable,
2423                 .max = 1
2424         },
2425         {
2426                 .type = SWITCH_TYPE_INT,
2427                 .name = "mirror_monitor_port",
2428                 .description = "Mirror monitor port",
2429                 .set = ar8xxx_sw_set_mirror_monitor_port,
2430                 .get = ar8xxx_sw_get_mirror_monitor_port,
2431                 .max = AR8216_NUM_PORTS - 1
2432         },
2433         {
2434                 .type = SWITCH_TYPE_INT,
2435                 .name = "mirror_source_port",
2436                 .description = "Mirror source port",
2437                 .set = ar8xxx_sw_set_mirror_source_port,
2438                 .get = ar8xxx_sw_get_mirror_source_port,
2439                 .max = AR8216_NUM_PORTS - 1
2440         },
2441 };
2442
2443 static struct switch_attr ar8327_sw_attr_globals[] = {
2444         {
2445                 .type = SWITCH_TYPE_INT,
2446                 .name = "enable_vlan",
2447                 .description = "Enable VLAN mode",
2448                 .set = ar8xxx_sw_set_vlan,
2449                 .get = ar8xxx_sw_get_vlan,
2450                 .max = 1
2451         },
2452         {
2453                 .type = SWITCH_TYPE_NOVAL,
2454                 .name = "reset_mibs",
2455                 .description = "Reset all MIB counters",
2456                 .set = ar8xxx_sw_set_reset_mibs,
2457         },
2458         {
2459                 .type = SWITCH_TYPE_INT,
2460                 .name = "enable_mirror_rx",
2461                 .description = "Enable mirroring of RX packets",
2462                 .set = ar8xxx_sw_set_mirror_rx_enable,
2463                 .get = ar8xxx_sw_get_mirror_rx_enable,
2464                 .max = 1
2465         },
2466         {
2467                 .type = SWITCH_TYPE_INT,
2468                 .name = "enable_mirror_tx",
2469                 .description = "Enable mirroring of TX packets",
2470                 .set = ar8xxx_sw_set_mirror_tx_enable,
2471                 .get = ar8xxx_sw_get_mirror_tx_enable,
2472                 .max = 1
2473         },
2474         {
2475                 .type = SWITCH_TYPE_INT,
2476                 .name = "mirror_monitor_port",
2477                 .description = "Mirror monitor port",
2478                 .set = ar8xxx_sw_set_mirror_monitor_port,
2479                 .get = ar8xxx_sw_get_mirror_monitor_port,
2480                 .max = AR8327_NUM_PORTS - 1
2481         },
2482         {
2483                 .type = SWITCH_TYPE_INT,
2484                 .name = "mirror_source_port",
2485                 .description = "Mirror source port",
2486                 .set = ar8xxx_sw_set_mirror_source_port,
2487                 .get = ar8xxx_sw_get_mirror_source_port,
2488                 .max = AR8327_NUM_PORTS - 1
2489         },
2490 };
2491
2492 static struct switch_attr ar8xxx_sw_attr_port[] = {
2493         {
2494                 .type = SWITCH_TYPE_NOVAL,
2495                 .name = "reset_mib",
2496                 .description = "Reset single port MIB counters",
2497                 .set = ar8xxx_sw_set_port_reset_mib,
2498         },
2499         {
2500                 .type = SWITCH_TYPE_STRING,
2501                 .name = "mib",
2502                 .description = "Get port's MIB counters",
2503                 .set = NULL,
2504                 .get = ar8xxx_sw_get_port_mib,
2505         },
2506 };
2507
2508 static struct switch_attr ar8xxx_sw_attr_vlan[] = {
2509         {
2510                 .type = SWITCH_TYPE_INT,
2511                 .name = "vid",
2512                 .description = "VLAN ID (0-4094)",
2513                 .set = ar8xxx_sw_set_vid,
2514                 .get = ar8xxx_sw_get_vid,
2515                 .max = 4094,
2516         },
2517 };
2518
2519 static const struct switch_dev_ops ar8xxx_sw_ops = {
2520         .attr_global = {
2521                 .attr = ar8xxx_sw_attr_globals,
2522                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_globals),
2523         },
2524         .attr_port = {
2525                 .attr = ar8xxx_sw_attr_port,
2526                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
2527         },
2528         .attr_vlan = {
2529                 .attr = ar8xxx_sw_attr_vlan,
2530                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
2531         },
2532         .get_port_pvid = ar8xxx_sw_get_pvid,
2533         .set_port_pvid = ar8xxx_sw_set_pvid,
2534         .get_vlan_ports = ar8xxx_sw_get_ports,
2535         .set_vlan_ports = ar8xxx_sw_set_ports,
2536         .apply_config = ar8xxx_sw_hw_apply,
2537         .reset_switch = ar8xxx_sw_reset_switch,
2538         .get_port_link = ar8xxx_sw_get_port_link,
2539 };
2540
2541 static const struct switch_dev_ops ar8327_sw_ops = {
2542         .attr_global = {
2543                 .attr = ar8327_sw_attr_globals,
2544                 .n_attr = ARRAY_SIZE(ar8327_sw_attr_globals),
2545         },
2546         .attr_port = {
2547                 .attr = ar8xxx_sw_attr_port,
2548                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
2549         },
2550         .attr_vlan = {
2551                 .attr = ar8xxx_sw_attr_vlan,
2552                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
2553         },
2554         .get_port_pvid = ar8xxx_sw_get_pvid,
2555         .set_port_pvid = ar8xxx_sw_set_pvid,
2556         .get_vlan_ports = ar8327_sw_get_ports,
2557         .set_vlan_ports = ar8327_sw_set_ports,
2558         .apply_config = ar8xxx_sw_hw_apply,
2559         .reset_switch = ar8xxx_sw_reset_switch,
2560         .get_port_link = ar8xxx_sw_get_port_link,
2561 };
2562
2563 static int
2564 ar8xxx_id_chip(struct ar8xxx_priv *priv)
2565 {
2566         u32 val;
2567         u16 id;
2568         int i;
2569
2570         val = priv->read(priv, AR8216_REG_CTRL);
2571         if (val == ~0)
2572                 return -ENODEV;
2573
2574         id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2575         for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
2576                 u16 t;
2577
2578                 val = priv->read(priv, AR8216_REG_CTRL);
2579                 if (val == ~0)
2580                         return -ENODEV;
2581
2582                 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2583                 if (t != id)
2584                         return -ENODEV;
2585         }
2586
2587         priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
2588         priv->chip_rev = (id & AR8216_CTRL_REVISION);
2589
2590         switch (priv->chip_ver) {
2591         case AR8XXX_VER_AR8216:
2592                 priv->chip = &ar8216_chip;
2593                 break;
2594         case AR8XXX_VER_AR8236:
2595                 priv->chip = &ar8236_chip;
2596                 break;
2597         case AR8XXX_VER_AR8316:
2598                 priv->chip = &ar8316_chip;
2599                 break;
2600         case AR8XXX_VER_AR8327:
2601                 priv->mii_lo_first = true;
2602                 priv->chip = &ar8327_chip;
2603                 break;
2604         case AR8XXX_VER_AR8337:
2605                 priv->mii_lo_first = true;
2606                 priv->chip = &ar8327_chip;
2607                 break;
2608         default:
2609                 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
2610                        priv->chip_ver, priv->chip_rev);
2611
2612                 return -ENODEV;
2613         }
2614
2615         return 0;
2616 }
2617
2618 static void
2619 ar8xxx_mib_work_func(struct work_struct *work)
2620 {
2621         struct ar8xxx_priv *priv;
2622         int err;
2623
2624         priv = container_of(work, struct ar8xxx_priv, mib_work.work);
2625
2626         mutex_lock(&priv->mib_lock);
2627
2628         err = ar8xxx_mib_capture(priv);
2629         if (err)
2630                 goto next_port;
2631
2632         ar8xxx_mib_fetch_port_stat(priv, priv->mib_next_port, false);
2633
2634 next_port:
2635         priv->mib_next_port++;
2636         if (priv->mib_next_port >= priv->dev.ports)
2637                 priv->mib_next_port = 0;
2638
2639         mutex_unlock(&priv->mib_lock);
2640         schedule_delayed_work(&priv->mib_work,
2641                               msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
2642 }
2643
2644 static int
2645 ar8xxx_mib_init(struct ar8xxx_priv *priv)
2646 {
2647         unsigned int len;
2648
2649         if (!ar8xxx_has_mib_counters(priv))
2650                 return 0;
2651
2652         BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
2653
2654         len = priv->dev.ports * priv->chip->num_mibs *
2655               sizeof(*priv->mib_stats);
2656         priv->mib_stats = kzalloc(len, GFP_KERNEL);
2657
2658         if (!priv->mib_stats)
2659                 return -ENOMEM;
2660
2661         return 0;
2662 }
2663
2664 static void
2665 ar8xxx_mib_start(struct ar8xxx_priv *priv)
2666 {
2667         if (!ar8xxx_has_mib_counters(priv))
2668                 return;
2669
2670         schedule_delayed_work(&priv->mib_work,
2671                               msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
2672 }
2673
2674 static void
2675 ar8xxx_mib_stop(struct ar8xxx_priv *priv)
2676 {
2677         if (!ar8xxx_has_mib_counters(priv))
2678                 return;
2679
2680         cancel_delayed_work(&priv->mib_work);
2681 }
2682
2683 static struct ar8xxx_priv *
2684 ar8xxx_create(void)
2685 {
2686         struct ar8xxx_priv *priv;
2687
2688         priv = kzalloc(sizeof(struct ar8xxx_priv), GFP_KERNEL);
2689         if (priv == NULL)
2690                 return NULL;
2691
2692         mutex_init(&priv->reg_mutex);
2693         mutex_init(&priv->mib_lock);
2694         INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
2695
2696         return priv;
2697 }
2698
2699 static void
2700 ar8xxx_free(struct ar8xxx_priv *priv)
2701 {
2702         if (priv->chip && priv->chip->cleanup)
2703                 priv->chip->cleanup(priv);
2704
2705         kfree(priv->mib_stats);
2706         kfree(priv);
2707 }
2708
2709 static struct ar8xxx_priv *
2710 ar8xxx_create_mii(struct mii_bus *bus)
2711 {
2712         struct ar8xxx_priv *priv;
2713
2714         priv = ar8xxx_create();
2715         if (priv) {
2716                 priv->mii_bus = bus;
2717                 priv->read = ar8xxx_mii_read;
2718                 priv->write = ar8xxx_mii_write;
2719                 priv->rmw = ar8xxx_mii_rmw;
2720         }
2721
2722         return priv;
2723 }
2724
2725 static int
2726 ar8xxx_probe_switch(struct ar8xxx_priv *priv)
2727 {
2728         struct switch_dev *swdev;
2729         int ret;
2730
2731         ret = ar8xxx_id_chip(priv);
2732         if (ret)
2733                 return ret;
2734
2735         swdev = &priv->dev;
2736         swdev->cpu_port = AR8216_PORT_CPU;
2737         swdev->ops = &ar8xxx_sw_ops;
2738
2739         if (chip_is_ar8316(priv)) {
2740                 swdev->name = "Atheros AR8316";
2741                 swdev->vlans = AR8X16_MAX_VLANS;
2742                 swdev->ports = AR8216_NUM_PORTS;
2743         } else if (chip_is_ar8236(priv)) {
2744                 swdev->name = "Atheros AR8236";
2745                 swdev->vlans = AR8216_NUM_VLANS;
2746                 swdev->ports = AR8216_NUM_PORTS;
2747         } else if (chip_is_ar8327(priv)) {
2748                 swdev->name = "Atheros AR8327";
2749                 swdev->vlans = AR8X16_MAX_VLANS;
2750                 swdev->ports = AR8327_NUM_PORTS;
2751                 swdev->ops = &ar8327_sw_ops;
2752         } else if (chip_is_ar8337(priv)) {
2753                 swdev->name = "Atheros AR8337";
2754                 swdev->vlans = AR8X16_MAX_VLANS;
2755                 swdev->ports = AR8327_NUM_PORTS;
2756                 swdev->ops = &ar8327_sw_ops;
2757         } else {
2758                 swdev->name = "Atheros AR8216";
2759                 swdev->vlans = AR8216_NUM_VLANS;
2760                 swdev->ports = AR8216_NUM_PORTS;
2761         }
2762
2763         ret = ar8xxx_mib_init(priv);
2764         if (ret)
2765                 return ret;
2766
2767         return 0;
2768 }
2769
2770 static int
2771 ar8xxx_start(struct ar8xxx_priv *priv)
2772 {
2773         int ret;
2774
2775         priv->init = true;
2776
2777         ret = priv->chip->hw_init(priv);
2778         if (ret)
2779                 return ret;
2780
2781         ret = ar8xxx_sw_reset_switch(&priv->dev);
2782         if (ret)
2783                 return ret;
2784
2785         priv->init = false;
2786
2787         ar8xxx_mib_start(priv);
2788
2789         return 0;
2790 }
2791
2792 static int
2793 ar8xxx_phy_config_init(struct phy_device *phydev)
2794 {
2795         struct ar8xxx_priv *priv = phydev->priv;
2796         struct net_device *dev = phydev->attached_dev;
2797         int ret;
2798
2799         if (WARN_ON(!priv))
2800                 return -ENODEV;
2801
2802         if (priv->chip->config_at_probe)
2803                 return ar8xxx_phy_check_aneg(phydev);
2804
2805         priv->phy = phydev;
2806
2807         if (phydev->addr != 0) {
2808                 if (chip_is_ar8316(priv)) {
2809                         /* switch device has been initialized, reinit */
2810                         priv->dev.ports = (AR8216_NUM_PORTS - 1);
2811                         priv->initialized = false;
2812                         priv->port4_phy = true;
2813                         ar8316_hw_init(priv);
2814                         return 0;
2815                 }
2816
2817                 return 0;
2818         }
2819
2820         ret = ar8xxx_start(priv);
2821         if (ret)
2822                 return ret;
2823
2824         /* VID fixup only needed on ar8216 */
2825         if (chip_is_ar8216(priv)) {
2826                 dev->phy_ptr = priv;
2827                 dev->priv_flags |= IFF_NO_IP_ALIGN;
2828                 dev->eth_mangle_rx = ar8216_mangle_rx;
2829                 dev->eth_mangle_tx = ar8216_mangle_tx;
2830         }
2831
2832         return 0;
2833 }
2834
2835 static int
2836 ar8xxx_phy_read_status(struct phy_device *phydev)
2837 {
2838         struct ar8xxx_priv *priv = phydev->priv;
2839         struct switch_port_link link;
2840         int ret;
2841
2842         if (phydev->addr != 0)
2843                 return genphy_read_status(phydev);
2844
2845         ar8216_read_port_link(priv, phydev->addr, &link);
2846         phydev->link = !!link.link;
2847         if (!phydev->link)
2848                 return 0;
2849
2850         switch (link.speed) {
2851         case SWITCH_PORT_SPEED_10:
2852                 phydev->speed = SPEED_10;
2853                 break;
2854         case SWITCH_PORT_SPEED_100:
2855                 phydev->speed = SPEED_100;
2856                 break;
2857         case SWITCH_PORT_SPEED_1000:
2858                 phydev->speed = SPEED_1000;
2859                 break;
2860         default:
2861                 phydev->speed = 0;
2862         }
2863         phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
2864
2865         /* flush the address translation unit */
2866         mutex_lock(&priv->reg_mutex);
2867         ret = priv->chip->atu_flush(priv);
2868         mutex_unlock(&priv->reg_mutex);
2869
2870         phydev->state = PHY_RUNNING;
2871         netif_carrier_on(phydev->attached_dev);
2872         phydev->adjust_link(phydev->attached_dev);
2873
2874         return ret;
2875 }
2876
2877 static int
2878 ar8xxx_phy_config_aneg(struct phy_device *phydev)
2879 {
2880         if (phydev->addr == 0)
2881                 return 0;
2882
2883         return genphy_config_aneg(phydev);
2884 }
2885
2886 static const u32 ar8xxx_phy_ids[] = {
2887         0x004dd033,
2888         0x004dd034, /* AR8327 */
2889         0x004dd036, /* AR8337 */
2890         0x004dd041,
2891         0x004dd042,
2892         0x004dd043, /* AR8236 */
2893 };
2894
2895 static bool
2896 ar8xxx_phy_match(u32 phy_id)
2897 {
2898         int i;
2899
2900         for (i = 0; i < ARRAY_SIZE(ar8xxx_phy_ids); i++)
2901                 if (phy_id == ar8xxx_phy_ids[i])
2902                         return true;
2903
2904         return false;
2905 }
2906
2907 static bool
2908 ar8xxx_is_possible(struct mii_bus *bus)
2909 {
2910         unsigned i;
2911
2912         for (i = 0; i < 4; i++) {
2913                 u32 phy_id;
2914
2915                 phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
2916                 phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
2917                 if (!ar8xxx_phy_match(phy_id)) {
2918                         pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
2919                                  dev_name(&bus->dev), i, phy_id);
2920                         return false;
2921                 }
2922         }
2923
2924         return true;
2925 }
2926
2927 static int
2928 ar8xxx_phy_probe(struct phy_device *phydev)
2929 {
2930         struct ar8xxx_priv *priv;
2931         struct switch_dev *swdev;
2932         int ret;
2933
2934         /* skip PHYs at unused adresses */
2935         if (phydev->addr != 0 && phydev->addr != 4)
2936                 return -ENODEV;
2937
2938         if (!ar8xxx_is_possible(phydev->bus))
2939                 return -ENODEV;
2940
2941         mutex_lock(&ar8xxx_dev_list_lock);
2942         list_for_each_entry(priv, &ar8xxx_dev_list, list)
2943                 if (priv->mii_bus == phydev->bus)
2944                         goto found;
2945
2946         priv = ar8xxx_create_mii(phydev->bus);
2947         if (priv == NULL) {
2948                 ret = -ENOMEM;
2949                 goto unlock;
2950         }
2951
2952         ret = ar8xxx_probe_switch(priv);
2953         if (ret)
2954                 goto free_priv;
2955
2956         swdev = &priv->dev;
2957         swdev->alias = dev_name(&priv->mii_bus->dev);
2958         ret = register_switch(swdev, NULL);
2959         if (ret)
2960                 goto free_priv;
2961
2962         pr_info("%s: %s rev. %u switch registered on %s\n",
2963                 swdev->devname, swdev->name, priv->chip_rev,
2964                 dev_name(&priv->mii_bus->dev));
2965
2966 found:
2967         priv->use_count++;
2968
2969         if (phydev->addr == 0) {
2970                 if (ar8xxx_has_gige(priv)) {
2971                         phydev->supported = SUPPORTED_1000baseT_Full;
2972                         phydev->advertising = ADVERTISED_1000baseT_Full;
2973                 } else {
2974                         phydev->supported = SUPPORTED_100baseT_Full;
2975                         phydev->advertising = ADVERTISED_100baseT_Full;
2976                 }
2977
2978                 if (priv->chip->config_at_probe) {
2979                         priv->phy = phydev;
2980
2981                         ret = ar8xxx_start(priv);
2982                         if (ret)
2983                                 goto err_unregister_switch;
2984                 }
2985         } else {
2986                 if (ar8xxx_has_gige(priv)) {
2987                         phydev->supported |= SUPPORTED_1000baseT_Full;
2988                         phydev->advertising |= ADVERTISED_1000baseT_Full;
2989                 }
2990         }
2991
2992         phydev->priv = priv;
2993
2994         list_add(&priv->list, &ar8xxx_dev_list);
2995
2996         mutex_unlock(&ar8xxx_dev_list_lock);
2997
2998         return 0;
2999
3000 err_unregister_switch:
3001         if (--priv->use_count)
3002                 goto unlock;
3003
3004         unregister_switch(&priv->dev);
3005
3006 free_priv:
3007         ar8xxx_free(priv);
3008 unlock:
3009         mutex_unlock(&ar8xxx_dev_list_lock);
3010         return ret;
3011 }
3012
3013 static void
3014 ar8xxx_phy_detach(struct phy_device *phydev)
3015 {
3016         struct net_device *dev = phydev->attached_dev;
3017
3018         if (!dev)
3019                 return;
3020
3021         dev->phy_ptr = NULL;
3022         dev->priv_flags &= ~IFF_NO_IP_ALIGN;
3023         dev->eth_mangle_rx = NULL;
3024         dev->eth_mangle_tx = NULL;
3025 }
3026
3027 static void
3028 ar8xxx_phy_remove(struct phy_device *phydev)
3029 {
3030         struct ar8xxx_priv *priv = phydev->priv;
3031
3032         if (WARN_ON(!priv))
3033                 return;
3034
3035         phydev->priv = NULL;
3036         if (--priv->use_count > 0)
3037                 return;
3038
3039         mutex_lock(&ar8xxx_dev_list_lock);
3040         list_del(&priv->list);
3041         mutex_unlock(&ar8xxx_dev_list_lock);
3042
3043         unregister_switch(&priv->dev);
3044         ar8xxx_mib_stop(priv);
3045         ar8xxx_free(priv);
3046 }
3047
3048 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
3049 static int
3050 ar8xxx_phy_soft_reset(struct phy_device *phydev)
3051 {
3052         /* we don't need an extra reset */
3053         return 0;
3054 }
3055 #endif
3056
3057 static struct phy_driver ar8xxx_phy_driver = {
3058         .phy_id         = 0x004d0000,
3059         .name           = "Atheros AR8216/AR8236/AR8316",
3060         .phy_id_mask    = 0xffff0000,
3061         .features       = PHY_BASIC_FEATURES,
3062         .probe          = ar8xxx_phy_probe,
3063         .remove         = ar8xxx_phy_remove,
3064         .detach         = ar8xxx_phy_detach,
3065         .config_init    = ar8xxx_phy_config_init,
3066         .config_aneg    = ar8xxx_phy_config_aneg,
3067         .read_status    = ar8xxx_phy_read_status,
3068 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
3069         .soft_reset     = ar8xxx_phy_soft_reset,
3070 #endif
3071         .driver         = { .owner = THIS_MODULE },
3072 };
3073
3074 int __init
3075 ar8xxx_init(void)
3076 {
3077         return phy_driver_register(&ar8xxx_phy_driver);
3078 }
3079
3080 void __exit
3081 ar8xxx_exit(void)
3082 {
3083         phy_driver_unregister(&ar8xxx_phy_driver);
3084 }
3085
3086 module_init(ar8xxx_init);
3087 module_exit(ar8xxx_exit);
3088 MODULE_LICENSE("GPL");
3089