brcm63xx: add linux 4.4 support

[openwrt.git] / target / linux / brcm63xx / patches-4.4 / 336-MIPS-BCM63XX-dynamically-set-the-pcie-memory-windows.patch

diff --git a/target/linux/brcm63xx/patches-4.4/336-MIPS-BCM63XX-dynamically-set-the-pcie-memory-windows.patch b/target/linux/brcm63xx/patches-4.4/336-MIPS-BCM63XX-dynamically-set-the-pcie-memory-windows.patch
new file mode 100644 (file)
index 0000000..d6eb54d
--- /dev/null
+++ b/target/linux/brcm63xx/patches-4.4/336-MIPS-BCM63XX-dynamically-set-the-pcie-memory-windows.patch
@@ -0,0 +1,70 @@
+From aa05464973bc176478af462ca7c53a9239c651d4 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Sun, 8 Dec 2013 03:13:06 +0100
+Subject: [PATCH 46/53] MIPS: BCM63XX: dynamically set the pcie memory windows
+
+Different SoCs use different memory windows (and sizes), so don't
+hardcode it.
+---
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h |  8 ++++----
+ arch/mips/pci/pci-bcm63xx.c                     | 15 ++++++++++-----
+ 2 files changed, 14 insertions(+), 9 deletions(-)
+
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
+@@ -40,10 +40,10 @@
+ #define BCM_CB_MEM_END_PA             (BCM_CB_MEM_BASE_PA +           \
+                                       BCM_CB_MEM_SIZE - 1)
+ 
+-#define BCM_PCIE_MEM_BASE_PA          0x10f00000
+-#define BCM_PCIE_MEM_SIZE             (1 * 1024 * 1024)
+-#define BCM_PCIE_MEM_END_PA           (BCM_PCIE_MEM_BASE_PA +         \
+-                                      BCM_PCIE_MEM_SIZE - 1)
++#define BCM_PCIE_MEM_BASE_PA_6328     0x10f00000
++#define BCM_PCIE_MEM_SIZE_6328                (1 * 1024 * 1024)
++#define BCM_PCIE_MEM_END_PA_6328      (BCM_PCIE_MEM_BASE_PA_6328 +    \
++                                      BCM_PCIE_MEM_SIZE_6328 - 1)
+ 
+ /*
+  * Internal registers are accessed through KSEG3
+--- a/arch/mips/pci/pci-bcm63xx.c
++++ b/arch/mips/pci/pci-bcm63xx.c
+@@ -77,8 +77,8 @@ struct pci_controller bcm63xx_cb_control
+ 
+ static struct resource bcm_pcie_mem_resource = {
+       .name   = "bcm63xx PCIe memory space",
+-      .start  = BCM_PCIE_MEM_BASE_PA,
+-      .end    = BCM_PCIE_MEM_END_PA,
++      .start  = 0,
++      .end    = 0,
+       .flags  = IORESOURCE_MEM,
+ };
+ 
+@@ -195,12 +195,12 @@ static int __init bcm63xx_register_pcie(
+       bcm_pcie_writel(val, PCIE_CONFIG2_REG);
+ 
+       /* set bar0 to little endian */
+-      val = (BCM_PCIE_MEM_BASE_PA >> 20) << BASEMASK_BASE_SHIFT;
+-      val |= (BCM_PCIE_MEM_BASE_PA >> 20) << BASEMASK_MASK_SHIFT;
++      val = (bcm_pcie_mem_resource.start >> 20) << BASEMASK_BASE_SHIFT;
++      val |= (bcm_pcie_mem_resource.end >> 20) << BASEMASK_MASK_SHIFT;
+       val |= BASEMASK_REMAP_EN;
+       bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_BASEMASK_REG);
+ 
+-      val = (BCM_PCIE_MEM_BASE_PA >> 20) << REBASE_ADDR_BASE_SHIFT;
++      val = (bcm_pcie_mem_resource.start >> 20) << REBASE_ADDR_BASE_SHIFT;
+       bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_REBASE_ADDR_REG);
+ 
+       register_pci_controller(&bcm63xx_pcie_controller);
+@@ -334,6 +334,11 @@ static int __init bcm63xx_pci_init(void)
+       if (!bcm63xx_pci_enabled)
+               return -ENODEV;
+ 
++      if (BCMCPU_IS_6328() || BCMCPU_IS_6362()) {
++              bcm_pcie_mem_resource.start = BCM_PCIE_MEM_BASE_PA_6328;
++              bcm_pcie_mem_resource.end = BCM_PCIE_MEM_END_PA_6328;
++      }
++
+       switch (bcm63xx_get_cpu_id()) {
+       case BCM6328_CPU_ID:
+       case BCM6362_CPU_ID: