ar71xx: fix ethernet device registration for QCA9558

[openwrt.git] / target / linux / ar71xx / patches-3.6 / 601-MIPS-ath79-add-more-register-defines.patch

diff --git a/target/linux/ar71xx/patches-3.6/601-MIPS-ath79-add-more-register-defines.patch b/target/linux/ar71xx/patches-3.6/601-MIPS-ath79-add-more-register-defines.patch
index 0185248..407de36 100644 (file)
--- a/target/linux/ar71xx/patches-3.6/601-MIPS-ath79-add-more-register-defines.patch
+++ b/target/linux/ar71xx/patches-3.6/601-MIPS-ath79-add-more-register-defines.patch
@@ -93,7 +93,7 @@
  
  #define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT     0
  #define AR934X_PLL_CPU_CONFIG_NFRAC_MASK      0x3f
-@@ -252,6 +278,8 @@
+@@ -252,9 +278,13 @@
  #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL        BIT(21)
  #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL        BIT(24)
  
@@ -102,7 +102,12 @@
  #define QCA955X_PLL_CPU_CONFIG_REG            0x00
  #define QCA955X_PLL_DDR_CONFIG_REG            0x04
  #define QCA955X_PLL_CLK_CTRL_REG              0x08
-@@ -378,16 +406,50 @@
++#define QCA955X_PLL_ETH_XMII_CONTROL_REG      0x28
++#define QCA955X_PLL_ETH_SGMII_CONTROL_REG     0x48
+ 
+ #define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT    0
+ #define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK     0x3f
+@@ -378,16 +408,83 @@
  #define AR913X_RESET_USB_HOST         BIT(5)
  #define AR913X_RESET_USB_PHY          BIT(4)
  
@@ -147,13 +152,46 @@
 +#define AR934X_RESET_LUT              BIT(2)
 +#define AR934X_RESET_MBOX             BIT(1)
 +#define AR934X_RESET_I2S              BIT(0)
++
++#define QCA955X_RESET_HOST            BIT(31)
++#define QCA955X_RESET_SLIC            BIT(30)
++#define QCA955X_RESET_HDMA            BIT(29)
++#define QCA955X_RESET_EXTERNAL                BIT(28)
++#define QCA955X_RESET_RTC             BIT(27)
++#define QCA955X_RESET_PCIE_EP_INT     BIT(26)
++#define QCA955X_RESET_CHKSUM_ACC      BIT(25)
++#define QCA955X_RESET_FULL_CHIP               BIT(24)
++#define QCA955X_RESET_GE1_MDIO                BIT(23)
++#define QCA955X_RESET_GE0_MDIO                BIT(22)
++#define QCA955X_RESET_CPU_NMI         BIT(21)
++#define QCA955X_RESET_CPU_COLD                BIT(20)
++#define QCA955X_RESET_HOST_RESET_INT  BIT(19)
++#define QCA955X_RESET_PCIE_EP         BIT(18)
++#define QCA955X_RESET_UART1           BIT(17)
++#define QCA955X_RESET_DDR             BIT(16)
++#define QCA955X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
++#define QCA955X_RESET_NANDF           BIT(14)
++#define QCA955X_RESET_GE1_MAC         BIT(13)
++#define QCA955X_RESET_SGMII_ANALOG    BIT(12)
++#define QCA955X_RESET_USB_PHY_ANALOG  BIT(11)
++#define QCA955X_RESET_HOST_DMA_INT    BIT(10)
++#define QCA955X_RESET_GE0_MAC         BIT(9)
++#define QCA955X_RESET_SGMII           BIT(8)
++#define QCA955X_RESET_PCIE_PHY                BIT(7)
++#define QCA955X_RESET_PCIE            BIT(6)
++#define QCA955X_RESET_USB_HOST                BIT(5)
++#define QCA955X_RESET_USB_PHY         BIT(4)
++#define QCA955X_RESET_USBSUS_OVERRIDE BIT(3)
++#define QCA955X_RESET_LUT             BIT(2)
++#define QCA955X_RESET_MBOX            BIT(1)
++#define QCA955X_RESET_I2S             BIT(0)
  
 +#define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18)
 +#define AR933X_BOOTSTRAP_EEPBUSY      BIT(4)
  #define AR933X_BOOTSTRAP_REF_CLK_40   BIT(0)
  
  #define AR934X_BOOTSTRAP_SW_OPTION8   BIT(23)
-@@ -528,6 +590,12 @@
+@@ -528,6 +625,12 @@
  #define AR71XX_GPIO_REG_INT_ENABLE    0x24
  #define AR71XX_GPIO_REG_FUNC          0x28
  
@@ -166,7 +204,7 @@
  #define AR934X_GPIO_REG_FUNC          0x6c
  
  #define AR71XX_GPIO_COUNT             16
-@@ -559,4 +627,133 @@
+@@ -559,4 +662,133 @@
  #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT        13
  #define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7