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ar71xx: define NAND controller base address and register size for AR934X/QCA955x
[openwrt.git]
/
target
/
linux
/
ar71xx
/
patches-3.3
/
601-MIPS-ath79-add-more-register-defines.patch
2012-09-12
juhosg
ar71xx: define NAND controller base address and registe...
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commitdiff
2012-09-10
juhosg
ar71xx: fix QCA955X_EHCI_SIZE
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2012-09-09
juhosg
ar71xx: use dynamic clock dividers on the 2nd MDIO...
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2012-09-08
juhosg
ar71xx: fix CPU/DDR frequency calculation for SRIF...
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2012-07-05
juhosg
ar71xx: add initial support for the QCA955X SoCs
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2012-07-05
juhosg
ar71xx: refactor PCI code to allow registering multiple...
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2012-05-05
juhosg
ar71xx: update 3.3 patches
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2012-03-19
juhosg
ar71xx: add AR934x specific interface speed setup for ge0
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2012-02-10
juhosg
ar71xx: add preliminary support for 3.3
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