ar71xx: fix ar933x watchdog clock (#13866)
authornbd <nbd@3c298f89-4303-0410-b956-a3cf2f4a3e73>
Sat, 13 Jul 2013 22:29:53 +0000 (22:29 +0000)
committernbd <nbd@3c298f89-4303-0410-b956-a3cf2f4a3e73>
Sat, 13 Jul 2013 22:29:53 +0000 (22:29 +0000)
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@37273 3c298f89-4303-0410-b956-a3cf2f4a3e73

target/linux/ar71xx/patches-3.10/200-MIPS-ath79-fix-ar933x-watchdog-clock.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/200-MIPS-ath79-fix-ar933x-watchdog-clock.patch [new file with mode: 0644]

diff --git a/target/linux/ar71xx/patches-3.10/200-MIPS-ath79-fix-ar933x-watchdog-clock.patch b/target/linux/ar71xx/patches-3.10/200-MIPS-ath79-fix-ar933x-watchdog-clock.patch
new file mode 100644 (file)
index 0000000..b3a3cd3
--- /dev/null
@@ -0,0 +1,15 @@
+From: Felix Fietkau <nbd@openwrt.org>
+Subject: [PATCH] MIPS: ath79: fix ar933x watchdog clock
+
+Signed-off-by: Felix Fietkau <nbd@openwrt.org>
+--- a/arch/mips/ath79/clock.c
++++ b/arch/mips/ath79/clock.c
+@@ -164,7 +164,7 @@ static void __init ar933x_clocks_init(vo
+               ath79_ahb_clk.rate = freq / t;
+       }
+-      ath79_wdt_clk.rate = ath79_ref_clk.rate;
++      ath79_wdt_clk.rate = ath79_ahb_clk.rate;
+       ath79_uart_clk.rate = ath79_ref_clk.rate;
+ }
diff --git a/target/linux/ar71xx/patches-3.8/200-MIPS-ath79-fix-ar933x-watchdog-clock.patch b/target/linux/ar71xx/patches-3.8/200-MIPS-ath79-fix-ar933x-watchdog-clock.patch
new file mode 100644 (file)
index 0000000..b3a3cd3
--- /dev/null
@@ -0,0 +1,15 @@
+From: Felix Fietkau <nbd@openwrt.org>
+Subject: [PATCH] MIPS: ath79: fix ar933x watchdog clock
+
+Signed-off-by: Felix Fietkau <nbd@openwrt.org>
+--- a/arch/mips/ath79/clock.c
++++ b/arch/mips/ath79/clock.c
+@@ -164,7 +164,7 @@ static void __init ar933x_clocks_init(vo
+               ath79_ahb_clk.rate = freq / t;
+       }
+-      ath79_wdt_clk.rate = ath79_ref_clk.rate;
++      ath79_wdt_clk.rate = ath79_ahb_clk.rate;
+       ath79_uart_clk.rate = ath79_ref_clk.rate;
+ }