-+#define AR531X_RESETTMR (AR531X_APBBASE + 0x3000)
-+#define AR531X_TIMER (AR531X_RESETTMR + 0x0000) /* countdown timer */
-+#define AR531X_WD_CTRL (AR531X_RESETTMR + 0x0008) /* watchdog cntrl */
-+#define AR531X_WD_TIMER (AR531X_RESETTMR + 0x000c) /* watchdog timer */
-+#define AR531X_ISR (AR531X_RESETTMR + 0x0010) /* Intr Status Reg */
-+#define AR531X_IMR (AR531X_RESETTMR + 0x0014) /* Intr Mask Reg */
-+#define AR531X_RESET (AR531X_RESETTMR + 0x0020)
-+#define AR5312_CLOCKCTL1 (AR531X_RESETTMR + 0x0064)
-+#define AR5312_SCRATCH (AR531X_RESETTMR + 0x006c)
-+#define AR531X_PROCADDR (AR531X_RESETTMR + 0x0070)
-+#define AR531X_PROC1 (AR531X_RESETTMR + 0x0074)
-+#define AR531X_DMAADDR (AR531X_RESETTMR + 0x0078)
-+#define AR531X_DMA1 (AR531X_RESETTMR + 0x007c)
-+#define AR531X_ENABLE (AR531X_RESETTMR + 0x0080) /* interface enb */
-+#define AR531X_REV (AR531X_RESETTMR + 0x0090) /* revision */
-+
-+/* AR531X_WD_CTRL register bit field definitions */
-+#define AR531X_WD_CTRL_IGNORE_EXPIRATION 0x0000
-+#define AR531X_WD_CTRL_NMI 0x0001
-+#define AR531X_WD_CTRL_RESET 0x0002
-+
-+/* AR531X_ISR register bit field definitions */
-+#define AR531X_ISR_NONE 0x0000
-+#define AR531X_ISR_TIMER 0x0001
-+#define AR531X_ISR_AHBPROC 0x0002
-+#define AR531X_ISR_AHBDMA 0x0004
-+#define AR531X_ISR_GPIO 0x0008
-+#define AR531X_ISR_UART0 0x0010
-+#define AR531X_ISR_UART0DMA 0x0020
-+#define AR531X_ISR_WD 0x0040
-+#define AR531X_ISR_LOCAL 0x0080
-+
-+/* AR531X_RESET register bit field definitions */
-+#define AR531X_RESET_SYSTEM 0x00000001 /* cold reset full system */
-+#define AR531X_RESET_PROC 0x00000002 /* cold reset MIPS core */
-+#define AR531X_RESET_WLAN0 0x00000004 /* cold reset WLAN MAC and BB */
-+#define AR531X_RESET_EPHY0 0x00000008 /* cold reset ENET0 phy */
-+#define AR531X_RESET_EPHY1 0x00000010 /* cold reset ENET1 phy */
-+#define AR531X_RESET_ENET0 0x00000020 /* cold reset ENET0 mac */
-+#define AR531X_RESET_ENET1 0x00000040 /* cold reset ENET1 mac */
-+#define AR531X_RESET_UART0 0x00000100 /* cold reset UART0 (high speed) */
-+#define AR531X_RESET_WLAN1 0x00000200 /* cold reset WLAN MAC/BB */
-+#define AR531X_RESET_APB 0x00000400 /* cold reset APB (ar5312) */
-+#define AR531X_RESET_WARM_PROC 0x00001000 /* warm reset MIPS core */
-+#define AR531X_RESET_WARM_WLAN0_MAC 0x00002000 /* warm reset WLAN0 MAC */
-+#define AR531X_RESET_WARM_WLAN0_BB 0x00004000 /* warm reset WLAN0 BaseBand */
-+#define AR531X_RESET_NMI 0x00010000 /* send an NMI to the processor */
-+#define AR531X_RESET_WARM_WLAN1_MAC 0x00020000 /* warm reset WLAN1 mac */
-+#define AR531X_RESET_WARM_WLAN1_BB 0x00040000 /* warm reset WLAN1 baseband */
-+#define AR531X_RESET_LOCAL_BUS 0x00080000 /* reset local bus */
-+#define AR531X_RESET_WDOG 0x00100000 /* last reset was a watchdog */
-+
-+#define AR531X_RESET_WMAC0_BITS \
-+ (AR531X_RESET_WLAN0 |\
-+ AR531X_RESET_WARM_WLAN0_MAC |\
-+ AR531X_RESET_WARM_WLAN0_BB)
-+
-+#define AR531X_RESERT_WMAC1_BITS \
-+ (AR531X_RESET_WLAN1 |\
-+ AR531X_RESET_WARM_WLAN1_MAC |\
-+ AR531X_RESET_WARM_WLAN1_BB)
++#define AR5312_RESETTMR (AR5312_APBBASE + 0x3000)
++#define AR5312_TIMER (AR5312_RESETTMR + 0x0000) /* countdown timer */
++#define AR5312_WD_CTRL (AR5312_RESETTMR + 0x0008) /* watchdog cntrl */
++#define AR5312_WD_TIMER (AR5312_RESETTMR + 0x000c) /* watchdog timer */
++#define AR5312_ISR (AR5312_RESETTMR + 0x0010) /* Intr Status Reg */
++#define AR5312_IMR (AR5312_RESETTMR + 0x0014) /* Intr Mask Reg */
++#define AR5312_RESET (AR5312_RESETTMR + 0x0020)
++#define AR5312_CLOCKCTL1 (AR5312_RESETTMR + 0x0064)
++#define AR5312_SCRATCH (AR5312_RESETTMR + 0x006c)
++#define AR5312_PROCADDR (AR5312_RESETTMR + 0x0070)
++#define AR5312_PROC1 (AR5312_RESETTMR + 0x0074)
++#define AR5312_DMAADDR (AR5312_RESETTMR + 0x0078)
++#define AR5312_DMA1 (AR5312_RESETTMR + 0x007c)
++#define AR5312_ENABLE (AR5312_RESETTMR + 0x0080) /* interface enb */
++#define AR5312_REV (AR5312_RESETTMR + 0x0090) /* revision */
++
++/* AR5312_WD_CTRL register bit field definitions */
++#define AR5312_WD_CTRL_IGNORE_EXPIRATION 0x0000
++#define AR5312_WD_CTRL_NMI 0x0001
++#define AR5312_WD_CTRL_RESET 0x0002
++
++/* AR5312_ISR register bit field definitions */
++#define AR5312_ISR_NONE 0x0000
++#define AR5312_ISR_TIMER 0x0001
++#define AR5312_ISR_AHBPROC 0x0002
++#define AR5312_ISR_AHBDMA 0x0004
++#define AR5312_ISR_GPIO 0x0008
++#define AR5312_ISR_UART0 0x0010
++#define AR5312_ISR_UART0DMA 0x0020
++#define AR5312_ISR_WD 0x0040
++#define AR5312_ISR_LOCAL 0x0080
++
++/* AR5312_RESET register bit field definitions */
++#define AR5312_RESET_SYSTEM 0x00000001 /* cold reset full system */
++#define AR5312_RESET_PROC 0x00000002 /* cold reset MIPS core */
++#define AR5312_RESET_WLAN0 0x00000004 /* cold reset WLAN MAC and BB */
++#define AR5312_RESET_EPHY0 0x00000008 /* cold reset ENET0 phy */
++#define AR5312_RESET_EPHY1 0x00000010 /* cold reset ENET1 phy */
++#define AR5312_RESET_ENET0 0x00000020 /* cold reset ENET0 mac */
++#define AR5312_RESET_ENET1 0x00000040 /* cold reset ENET1 mac */
++#define AR5312_RESET_UART0 0x00000100 /* cold reset UART0 (high speed) */
++#define AR5312_RESET_WLAN1 0x00000200 /* cold reset WLAN MAC/BB */
++#define AR5312_RESET_APB 0x00000400 /* cold reset APB (ar5312) */
++#define AR5312_RESET_WARM_PROC 0x00001000 /* warm reset MIPS core */
++#define AR5312_RESET_WARM_WLAN0_MAC 0x00002000 /* warm reset WLAN0 MAC */
++#define AR5312_RESET_WARM_WLAN0_BB 0x00004000 /* warm reset WLAN0 BaseBand */
++#define AR5312_RESET_NMI 0x00010000 /* send an NMI to the processor */
++#define AR5312_RESET_WARM_WLAN1_MAC 0x00020000 /* warm reset WLAN1 mac */
++#define AR5312_RESET_WARM_WLAN1_BB 0x00040000 /* warm reset WLAN1 baseband */
++#define AR5312_RESET_LOCAL_BUS 0x00080000 /* reset local bus */
++#define AR5312_RESET_WDOG 0x00100000 /* last reset was a watchdog */
++
++#define AR5312_RESET_WMAC0_BITS \
++ (AR5312_RESET_WLAN0 |\
++ AR5312_RESET_WARM_WLAN0_MAC |\
++ AR5312_RESET_WARM_WLAN0_BB)
++
++#define AR5312_RESET_WMAC1_BITS \
++ (AR5312_RESET_WLAN1 |\
++ AR5312_RESET_WARM_WLAN1_MAC |\
++ AR5312_RESET_WARM_WLAN1_BB)