revert to vlynq bus clock divisor guessing
authorNicolas Thill <nico@openwrt.org>
Mon, 1 Oct 2007 10:16:14 +0000 (10:16 +0000)
committerNicolas Thill <nico@openwrt.org>
Mon, 1 Oct 2007 10:16:14 +0000 (10:16 +0000)
commit8465950fc2115474bea12a3e689a44dae6a59121
tree154c6fe3a753260bf748e91b9263591f12350388
parent9d3acc05d991ee22e1c455c28e1faee1349957c0
revert to vlynq bus clock divisor guessing

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@9086 3c298f89-4303-0410-b956-a3cf2f4a3e73
target/linux/ar7/files/arch/mips/ar7/vlynq-pci.c