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(parent: d8fd28f) | patch
ar71xx: use correct PLL configuration register bitmask for QCA956x SoC.
authornbd <nbd@3c298f89-4303-0410-b956-a3cf2f4a3e73>
Mon, 2 Nov 2015 18:20:51 +0000 (18:20 +0000)
committernbd <nbd@3c298f89-4303-0410-b956-a3cf2f4a3e73>
Mon, 2 Nov 2015 18:20:51 +0000 (18:20 +0000)
commit7f7bbb67ad2c7723dab1e373f3a603b9a8d46972
treeb2fb3f558930fc94dbe0c7b78bee2e58927e2cebtree | snapshot
parentd8fd28f02a77f8147a5a9b23745d4987068f4890commit | diff
ar71xx: use correct PLL configuration register bitmask for QCA956x SoC.

Incorrect value causes clock inaccuracy as huge as 1/60.

Signed-off-by: Dmitry Ivanov <dima@ubnt.com>
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@47363 3c298f89-4303-0410-b956-a3cf2f4a3e73
target/linux/ar71xx/patches-4.1/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch diff | blob | history
OpenWrt main development branch