#define RT305X_RESET_FE BIT(21)
#define RT305X_RESET_ESW BIT(23)
-#define SYSC_REG_RESET_CTRL 0x034
static const u32 rt5350_reg_table[FE_REG_COUNT] = {
[FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
[FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
[FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
[FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
+ [FE_REG_TX_DTX_IDX0] = RT5350_TX_DTX_IDX0,
[FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
[FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
[FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
+ [FE_REG_RX_DRX_IDX0] = RT5350_RX_DRX_IDX0,
[FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
[FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
[FE_REG_FE_RST_GL] = 0,
static void rt305x_fe_reset(void)
{
- rt_sysc_w32(RT305X_RESET_FE, SYSC_REG_RESET_CTRL);
- rt_sysc_w32(0, SYSC_REG_RESET_CTRL);
+ fe_reset(RT305X_RESET_FE);
}
static void rt5350_init_data(struct fe_soc_data *data,
return 0;
}
-static void rt5350_tx_dma(struct fe_priv *priv, int idx, struct sk_buff *skb)
+static void rt5350_tx_dma(struct fe_tx_dma *txd)
{
- priv->tx_dma[idx].txd4 = 0;
+ txd->txd4 = 0;
}
static void rt5350_fe_reset(void)
{
- rt_sysc_w32(RT305X_RESET_FE | RT305X_RESET_ESW, SYSC_REG_RESET_CTRL);
- rt_sysc_w32(0, SYSC_REG_RESET_CTRL);
+ fe_reset(RT305X_RESET_FE | RT305X_RESET_ESW);
}
static struct fe_soc_data rt3050_data = {
.pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS,
.checksum_bit = RX_DMA_L4VALID,
.tx_udf_bit = TX_DMA_UDF,
- .rx_dly_int = FE_RX_DLY_INT,
- .tx_dly_int = FE_TX_DLY_INT,
+ .rx_int = FE_RX_DONE_INT,
+ .tx_int = FE_TX_DONE_INT,
};
static struct fe_soc_data rt5350_data = {
.pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS,
.checksum_bit = RX_DMA_L4VALID,
.tx_udf_bit = TX_DMA_UDF,
- .rx_dly_int = RT5350_RX_DLY_INT,
- .tx_dly_int = RT5350_TX_DLY_INT,
+ .rx_int = RT5350_RX_DONE_INT,
+ .tx_int = RT5350_TX_DONE_INT,
};
const struct of_device_id of_fe_match[] = {