[ramips] uart_clk on Rt3352F is always 40MHz

[openwrt.git] / target / linux / ramips / files / arch / mips / ralink / rt305x / clock.c

diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c
index 4a99cf3..9585476 100644 (file)
--- a/target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c
+++ b/target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c
@@ -60,7 +60,7 @@ void __init rt305x_clocks_init(void)
                        break;
                }
                rt305x_sys_clk.rate = rt305x_cpu_clk.rate / 3;
-               rt305x_uart_clk.rate = rt305x_sys_clk.rate / 10;
+               rt305x_uart_clk.rate = 40000000;
                rt305x_wdt_clk.rate = rt305x_sys_clk.rate;
        } else {
                BUG();