ramips: enable CPS for mt7621

[openwrt.git] / target / linux / ramips / dts / mt7621.dtsi

diff --git a/target/linux/ramips/dts/mt7621.dtsi b/target/linux/ramips/dts/mt7621.dtsi
index e111c2b..a06aee7 100644 (file)
--- a/target/linux/ramips/dts/mt7621.dtsi
+++ b/target/linux/ramips/dts/mt7621.dtsi
@@ -1,3 +1,5 @@
+#include <dt-bindings/interrupt-controller/mips-gic.h>
+
 / {
        #address-cells = <1>;
        #size-cells = <1>;
@@ -72,12 +74,22 @@
                        reg = <0x300 0x100>;
                };
 
+               cpc@1fbf0000 {
+                            compatible = "mtk,mt7621-cpc";
+                            reg = <0x1fbf0000 0x8000>;
+               };
+
+               mc@1fbf8000 {
+                           compatible = "mtk,mt7621-mc";
+                           reg = <0x1fbf8000 0x8000>;
+               };
+
                uartlite@c00 {
                        compatible = "ns16550a";
                        reg = <0xc00 0x100>;
 
                        interrupt-parent = <&gic>;
-                       interrupts = <26>;
+                       interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
 
                        reg-shift = <2>;
                        reg-io-width = <4>;
@@ -94,7 +106,7 @@
                        reset-names = "spi";
 
                        #address-cells = <1>;
-                       #size-cells = <1>;
+                       #size-cells = <0>;
 
                        pinctrl-names = "default";
                        pinctrl-0 = <&spi_pins>;
@@ -134,35 +146,35 @@
                uart1_pins: uart1 {
                        uart1 {
                                ralink,group = "uart1";
-                               ralink,function = "uart";
+                               ralink,function = "uart1";
                        };
                };
 
                uart2_pins: uart2 {
                        uart2 {
                                ralink,group = "uart2";
-                               ralink,function = "uart";
+                               ralink,function = "uart2";
                        };
                };
 
                uart3_pins: uart3 {
                        uart3 {
                                ralink,group = "uart3";
-                               ralink,function = "uart";
+                               ralink,function = "uart3";
                        };
                };
 
                rgmii1_pins: rgmii1 {
                        rgmii1 {
                                ralink,group = "rgmii1";
-                               ralink,function = "rgmii";
+                               ralink,function = "rgmii1";
                        };
                };
 
                rgmii2_pins: rgmii2 {
                        rgmii2 {
                                ralink,group = "rgmii2";
-                               ralink,function = "rgmii";
+                               ralink,function = "rgmii2";
                        };
                };
 
@@ -183,12 +195,12 @@
                nand_pins: nand {
                        spi-nand {
                                ralink,group = "spi";
-                               ralink,function = "nand";
+                               ralink,function = "nand1";
                        };
 
                        sdhci-nand {
                                ralink,group = "sdhci";
-                               ralink,function = "nand";
+                               ralink,function = "nand2";
                        };
                };
 
@@ -210,28 +222,27 @@
                reg = <0x1E130000 4000>;
 
                interrupt-parent = <&gic>;
-               interrupts = <20>;
+               interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
        };
 
        xhci@1E1C0000 {
-               status = "disabled";
+               status = "okay";
 
                compatible = "xhci-platform";
                reg = <0x1E1C0000 4000>;
 
                interrupt-parent = <&gic>;
-               interrupts = <22>;
+               interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
        };
 
-       gic: gic@1fbc0000 {
-               #address-cells = <0>;
-               #interrupt-cells = <1>;
+       gic: interrupt-controller@1fbc0000 {
+               compatible = "mti,gic";
+               reg = <0x1fbc0000 0x2000>;
+
                interrupt-controller;
-               compatible = "ralink,mt7621-gic";
-               reg = < 0x1fbc0000 0x80 /* gic */
-                       0x1fbf0000 0x8000 /* cpc */
-                       0x1fbf8000 0x8000 /* gpmc */
-               >;
+               #interrupt-cells = <3>;
+
+               mti,reserved-cpu-vectors = <7>;
        };
 
        nand@1e003000 {
@@ -274,7 +285,7 @@
                reset-names = "fe", "eth";
 
                interrupt-parent = <&gic>;
-               interrupts = <3>;
+               interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
 
                mdio-bus {
                        #address-cells = <1>;
@@ -291,7 +302,7 @@
                compatible = "ralink,mt7620a-gsw";
                reg = <0x1e110000 8000>;
                interrupt-parent = <&gic>;
-               interrupts = <23>;
+               interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
        };
 
        pcie@1e140000 {
@@ -313,6 +324,11 @@
                        0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
                >;
 
+               interrupt-parent = <&gic>;
+               interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH
+                               GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH
+                               GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
+
                status = "okay";
 
                pcie0 {