+++ /dev/null
-From 60538f9841697cd4539d353afd8a7f51cd17e4af Mon Sep 17 00:00:00 2001
-From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Date: Fri, 5 Jul 2013 14:54:17 +0200
-Subject: [PATCH 066/203] PCI: mvebu: Adapt to the new device tree layout
-
-The new device tree layout encodes the window's target ID and attribute
-in the PCIe controller node's ranges property. This allows to parse
-such entries to obtain such information and use the recently introduced
-MBus API to create the windows, instead of using the current name based
-scheme.
-
-Acked-by: Bjorn Helgaas <bhelgaas@google.com>
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Tested-by: Andrew Lunn <andrew@lunn.ch>
-Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
----
- .../devicetree/bindings/pci/mvebu-pci.txt | 145 ++++++++++++++++-----
- 1 file changed, 109 insertions(+), 36 deletions(-)
-
---- a/Documentation/devicetree/bindings/pci/mvebu-pci.txt
-+++ b/Documentation/devicetree/bindings/pci/mvebu-pci.txt
-@@ -1,6 +1,7 @@
- * Marvell EBU PCIe interfaces
-
- Mandatory properties:
-+
- - compatible: one of the following values:
- marvell,armada-370-pcie
- marvell,armada-xp-pcie
-@@ -9,11 +10,49 @@ Mandatory properties:
- - #interrupt-cells, set to <1>
- - bus-range: PCI bus numbers covered
- - device_type, set to "pci"
--- ranges: ranges for the PCI memory and I/O regions, as well as the
-- MMIO registers to control the PCIe interfaces.
-+- ranges: ranges describing the MMIO registers to control the PCIe
-+ interfaces, and ranges describing the MBus windows needed to access
-+ the memory and I/O regions of each PCIe interface.
-+
-+The ranges describing the MMIO registers have the following layout:
-+
-+ 0x82000000 0 r MBUS_ID(0xf0, 0x01) r 0 s
-+
-+where:
-+
-+ * r is a 32-bits value that gives the offset of the MMIO
-+ registers of this PCIe interface, from the base of the internal
-+ registers.
-+
-+ * s is a 32-bits value that give the size of this MMIO
-+ registers area. This range entry translates the '0x82000000 0 r' PCI
-+ address into the 'MBUS_ID(0xf0, 0x01) r' CPU address, which is part
-+ of the internal register window (as identified by MBUS_ID(0xf0,
-+ 0x01)).
-+
-+The ranges describing the MBus windows have the following layout:
-+
-+ 0x8t000000 s 0 MBUS_ID(w, a) 0 1 0
-+
-+where:
-
--In addition, the Device Tree node must have sub-nodes describing each
-+ * t is the type of the MBus window (as defined by the standard PCI DT
-+ bindings), 1 for I/O and 2 for memory.
-+
-+ * s is the PCI slot that corresponds to this PCIe interface
-+
-+ * w is the 'target ID' value for the MBus window
-+
-+ * a the 'attribute' value for the MBus window.
-+
-+Since the location and size of the different MBus windows is not fixed in
-+hardware, and only determined in runtime, those ranges cover the full first
-+4 GB of the physical address space, and do not translate into a valid CPU
-+address.
-+
-+In addition, the device tree node must have sub-nodes describing each
- PCIe interface, having the following mandatory properties:
-+
- - reg: used only for interrupt mapping, so only the first four bytes
- are used to refer to the correct bus number and device number.
- - assigned-addresses: reference to the MMIO registers used to control
-@@ -25,7 +64,8 @@ PCIe interface, having the following man
- - #address-cells, set to <3>
- - #size-cells, set to <2>
- - #interrupt-cells, set to <1>
--- ranges, empty property.
-+- ranges, translating the MBus windows ranges of the parent node into
-+ standard PCI addresses.
- - interrupt-map-mask and interrupt-map, standard PCI properties to
- define the mapping of the PCIe interface to interrupt numbers.
-
-@@ -46,27 +86,50 @@ pcie-controller {
-
- bus-range = <0x00 0xff>;
-
-- ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000 /* Port 0.0 registers */
-- 0x82000000 0 0xd0042000 0xd0042000 0 0x00002000 /* Port 2.0 registers */
-- 0x82000000 0 0xd0044000 0xd0044000 0 0x00002000 /* Port 0.1 registers */
-- 0x82000000 0 0xd0048000 0xd0048000 0 0x00002000 /* Port 0.2 registers */
-- 0x82000000 0 0xd004c000 0xd004c000 0 0x00002000 /* Port 0.3 registers */
-- 0x82000000 0 0xd0080000 0xd0080000 0 0x00002000 /* Port 1.0 registers */
-- 0x82000000 0 0xd0082000 0xd0082000 0 0x00002000 /* Port 3.0 registers */
-- 0x82000000 0 0xd0084000 0xd0084000 0 0x00002000 /* Port 1.1 registers */
-- 0x82000000 0 0xd0088000 0xd0088000 0 0x00002000 /* Port 1.2 registers */
-- 0x82000000 0 0xd008c000 0xd008c000 0 0x00002000 /* Port 1.3 registers */
-- 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
-- 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
-+ ranges =
-+ <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
-+ 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
-+ 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
-+ 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
-+ 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
-+ 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
-+ 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
-+ 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
-+ 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
-+ 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
-+ 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
-+ 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
-+ 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
-+ 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
-+ 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
-+ 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
-+ 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
-+ 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
-+
-+ 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
-+ 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
-+ 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
-+ 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
-+ 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
-+ 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
-+ 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
-+ 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
-+
-+ 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
-+ 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */
-+
-+ 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
-+ 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;
-
- pcie@1,0 {
- device_type = "pci";
-- assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>;
-+ assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
- reg = <0x0800 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
-- ranges;
-+ ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
-+ 0x81000000 0 0 0x81000000 0x1 0 1 0>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 58>;
- marvell,pcie-port = <0>;
-@@ -77,12 +140,13 @@ pcie-controller {
-
- pcie@2,0 {
- device_type = "pci";
-- assigned-addresses = <0x82001000 0 0xd0044000 0 0x2000>;
-+ assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
- reg = <0x1000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
-- ranges;
-+ ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
-+ 0x81000000 0 0 0x81000000 0x2 0 1 0>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 59>;
- marvell,pcie-port = <0>;
-@@ -93,12 +157,13 @@ pcie-controller {
-
- pcie@3,0 {
- device_type = "pci";
-- assigned-addresses = <0x82001800 0 0xd0048000 0 0x2000>;
-+ assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
- reg = <0x1800 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
-- ranges;
-+ ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
-+ 0x81000000 0 0 0x81000000 0x3 0 1 0>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 60>;
- marvell,pcie-port = <0>;
-@@ -109,12 +174,13 @@ pcie-controller {
-
- pcie@4,0 {
- device_type = "pci";
-- assigned-addresses = <0x82002000 0 0xd004c000 0 0x2000>;
-+ assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
- reg = <0x2000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
-- ranges;
-+ ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
-+ 0x81000000 0 0 0x81000000 0x4 0 1 0>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 61>;
- marvell,pcie-port = <0>;
-@@ -125,12 +191,13 @@ pcie-controller {
-
- pcie@5,0 {
- device_type = "pci";
-- assigned-addresses = <0x82002800 0 0xd0080000 0 0x2000>;
-+ assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
- reg = <0x2800 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
-- ranges;
-+ ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
-+ 0x81000000 0 0 0x81000000 0x5 0 1 0>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 62>;
- marvell,pcie-port = <1>;
-@@ -141,12 +208,13 @@ pcie-controller {
-
- pcie@6,0 {
- device_type = "pci";
-- assigned-addresses = <0x82003000 0 0xd0084000 0 0x2000>;
-+ assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
- reg = <0x3000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
-- ranges;
-+ ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
-+ 0x81000000 0 0 0x81000000 0x6 0 1 0>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 63>;
- marvell,pcie-port = <1>;
-@@ -157,12 +225,13 @@ pcie-controller {
-
- pcie@7,0 {
- device_type = "pci";
-- assigned-addresses = <0x82003800 0 0xd0088000 0 0x2000>;
-+ assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
- reg = <0x3800 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
-- ranges;
-+ ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
-+ 0x81000000 0 0 0x81000000 0x7 0 1 0>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 64>;
- marvell,pcie-port = <1>;
-@@ -173,12 +242,13 @@ pcie-controller {
-
- pcie@8,0 {
- device_type = "pci";
-- assigned-addresses = <0x82004000 0 0xd008c000 0 0x2000>;
-+ assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
- reg = <0x4000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
-- ranges;
-+ ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
-+ 0x81000000 0 0 0x81000000 0x8 0 1 0>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 65>;
- marvell,pcie-port = <1>;
-@@ -186,14 +256,16 @@ pcie-controller {
- clocks = <&gateclk 12>;
- status = "disabled";
- };
-+
- pcie@9,0 {
- device_type = "pci";
-- assigned-addresses = <0x82004800 0 0xd0042000 0 0x2000>;
-+ assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
- reg = <0x4800 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
-- ranges;
-+ ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
-+ 0x81000000 0 0 0x81000000 0x9 0 1 0>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 99>;
- marvell,pcie-port = <2>;
-@@ -204,12 +276,13 @@ pcie-controller {
-
- pcie@10,0 {
- device_type = "pci";
-- assigned-addresses = <0x82005000 0 0xd0082000 0 0x2000>;
-+ assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
- reg = <0x5000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
-- ranges;
-+ ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
-+ 0x81000000 0 0 0x81000000 0xa 0 1 0>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &mpic 103>;
- marvell,pcie-port = <3>;
projects / openwrt.git / blobdiff