ipq806x: switch AP148 to using SMEM based MTD parser

[openwrt.git] / target / linux / ipq806x / patches-3.18 / 112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch

diff --git a/target/linux/ipq806x/patches-3.18/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch b/target/linux/ipq806x/patches-3.18/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch
index 3c1ae61..d15f0ac 100644 (file)
--- a/target/linux/ipq806x/patches-3.18/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch
+++ b/target/linux/ipq806x/patches-3.18/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch
@@ -15,22 +15,24 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
 
 --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
 +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
-@@ -30,6 +30,22 @@
+@@ -35,6 +35,24 @@
                                bias-disable;
                        };
  
-+                      pcie1_pins: pcie1_pinmux {
++                      pcie0_pins: pcie0_pinmux {
 +                              mux {
 +                                      pins = "gpio3";
-+                                      drive-strength = <2>;
++                                      function = "pcie1_rst";
++                                      drive-strength = <12>;
 +                                      bias-disable;
 +                              };
 +                      };
 +
-+                      pcie2_pins: pcie2_pinmux {
++                      pcie1_pins: pcie1_pinmux {
 +                              mux {
 +                                      pins = "gpio48";
-+                                      drive-strength = <2>;
++                                      function = "pcie2_rst";
++                                      drive-strength = <12>;
 +                                      bias-disable;
 +                              };
 +                      };
@@ -38,7 +40,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
                        spi_pins: spi_pins {
                                mux {
                                        pins = "gpio18", "gpio19", "gpio21";
-@@ -133,5 +149,19 @@
+@@ -115,5 +133,19 @@
                usb30@1 {
                        status = "ok";
                };
@@ -46,44 +48,47 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
 +              pcie0: pci@1b500000 {
 +                      status = "ok";
 +                      reset-gpio = <&qcom_pinmux 3 0>;
-+                      pinctrl-0 = <&pcie1_pins>;
++                      pinctrl-0 = <&pcie0_pins>;
 +                      pinctrl-names = "default";
 +              };
 +
 +              pcie1: pci@1b700000 {
 +                      status = "ok";
 +                      reset-gpio = <&qcom_pinmux 48 0>;
-+                      pinctrl-0 = <&pcie2_pins>;
++                      pinctrl-0 = <&pcie1_pins>;
 +                      pinctrl-names = "default";
 +              };
        };
  };
 --- a/arch/arm/boot/dts/qcom-ipq8064-db149.dts
 +++ b/arch/arm/boot/dts/qcom-ipq8064-db149.dts
-@@ -37,6 +37,30 @@
+@@ -30,6 +30,33 @@
                                bias-disable;
                        };
  
-+                      pcie1_pins: pcie1_pinmux {
++                      pcie0_pins: pcie0_pinmux {
 +                              mux {
 +                                      pins = "gpio3";
-+                                      drive-strength = <2>;
++                                      function = "pcie1_rst";
++                                      drive-strength = <12>;
 +                                      bias-disable;
 +                              };
 +                      };
 +
-+                      pcie2_pins: pcie2_pinmux {
++                      pcie1_pins: pcie1_pinmux {
 +                              mux {
 +                                      pins = "gpio48";
-+                                      drive-strength = <2>;
++                                      function = "pcie2_rst";
++                                      drive-strength = <12>;
 +                                      bias-disable;
 +                              };
 +                      };
 +
-+                      pcie3_pins: pcie3_pinmux {
++                      pcie2_pins: pcie2_pinmux {
 +                              mux {
 +                                      pins = "gpio63";
-+                                      drive-strength = <2>;
++                                      function = "pcie3_rst";
++                                      drive-strength = <12>;
 +                                      bias-disable;
 +                              };
 +                      };
@@ -91,46 +96,46 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
                        spi_pins: spi_pins {
                                mux {
                                        pins = "gpio18", "gpio19", "gpio21";
-@@ -153,6 +177,27 @@
+@@ -128,5 +155,26 @@
+               usb30@1 {
                        status = "ok";
                };
- 
++
 +              pcie0: pci@1b500000 {
 +                      status = "ok";
 +                      reset-gpio = <&qcom_pinmux 3 0>;
-+                      pinctrl-0 = <&pcie1_pins>;
++                      pinctrl-0 = <&pcie0_pins>;
 +                      pinctrl-names = "default";
 +              };
 +
 +              pcie1: pci@1b700000 {
 +                      status = "ok";
 +                      reset-gpio = <&qcom_pinmux 48 0>;
-+                      pinctrl-0 = <&pcie2_pins>;
++                      pinctrl-0 = <&pcie1_pins>;
 +                      pinctrl-names = "default";
 +              };
 +
 +              pcie2: pci@1b900000 {
 +                      status = "ok";
 +                      reset-gpio = <&qcom_pinmux 63 0>;
-+                      pinctrl-0 = <&pcie3_pins>;
++                      pinctrl-0 = <&pcie2_pins>;
 +                      pinctrl-names = "default";
 +              };
-+
-               mdio0: mdio {
-                       compatible = "virtual,mdio-gpio";
-                       #address-cells = <1>;
+       };
+ };
 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -3,6 +3,7 @@
+@@ -3,6 +3,8 @@
  #include "skeleton.dtsi"
  #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
  #include <dt-bindings/soc/qcom,gsbi.h>
 +#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
++#include <dt-bindings/interrupt-controller/arm-gic.h>
  
  / {
        model = "Qualcomm IPQ8064";
-@@ -306,6 +307,129 @@
-                       #reset-cells = <1>;
+@@ -311,6 +313,129 @@
+                       reg = <0x01200600 0x100>;
                };
  
 +              pcie0: pci@1b500000 {
@@ -259,10 +264,3 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
                hs_phy_1: phy@100f8800 {
                        compatible = "qcom,dwc3-hs-usb-phy";
                        reg = <0x100f8800 0x30>;
-@@ -389,6 +513,5 @@
-                               dr_mode = "host";
-                       };
-               };
--
-       };
- };