CC: upgrade kernel to 3.18.68

[15.05/openwrt.git] / target / linux / generic / patches-3.18 / 025-bcma_backport.patch

diff --git a/target/linux/generic/patches-3.18/025-bcma_backport.patch b/target/linux/generic/patches-3.18/025-bcma_backport.patch
index 48fd5bb..ec1cb00 100644 (file)
--- a/target/linux/generic/patches-3.18/025-bcma_backport.patch
+++ b/target/linux/generic/patches-3.18/025-bcma_backport.patch
@@ -1,6 +1,6 @@
 --- a/drivers/bcma/bcma_private.h
 +++ b/drivers/bcma/bcma_private.h
-@@ -24,6 +24,7 @@ struct bcma_bus;
+@@ -22,6 +22,7 @@ struct bcma_bus;
  /* main.c */
  bool bcma_wait_value(struct bcma_device *core, u16 reg, u32 mask, u32 value,
                     int timeout);
@@ -84,7 +84,7 @@
        pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
  
        readrq = pcie_get_readrq(dev);
-@@ -617,6 +617,6 @@ int bcma_core_pci_pcibios_map_irq(const 
+@@ -617,6 +617,6 @@ int bcma_core_pci_pcibios_map_irq(const
  
        pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host,
                               pci_ops);
@@ -223,7 +223,7 @@
                          core->core_index, bcma_device_name(&core->id),
 --- a/include/linux/bcma/bcma.h
 +++ b/include/linux/bcma/bcma.h
-@@ -447,4 +447,6 @@ extern u32 bcma_chipco_pll_read(struct b
+@@ -448,4 +448,6 @@ extern u32 bcma_chipco_pll_read(struct b
  #define  BCMA_DMA_TRANSLATION_DMA64_CMT       0x80000000 /* Client Mode Translation for 64-bit DMA */
  extern u32 bcma_core_dma_translation(struct bcma_device *core);
  
@@ -247,3 +247,40 @@
  {
        return 0;
  }
+--- a/Documentation/devicetree/bindings/bus/bcma.txt
++++ b/Documentation/devicetree/bindings/bus/bcma.txt
+@@ -8,6 +8,11 @@ Required properties:
+ 
+ The cores on the AXI bus are automatically detected by bcma with the
+ memory ranges they are using and they get registered afterwards.
++Automatic detection of the IRQ number is not working on
++BCM47xx/BCM53xx ARM SoCs. To assign IRQ numbers to the cores, provide
++them manually through device tree. Use an interrupt-map to specify the
++IRQ used by the devices on the bus. The first address is just an index,
++because we do not have any special register.
+ 
+ The top-level axi bus may contain children representing attached cores
+ (devices). This is needed since some hardware details can't be auto
+@@ -22,6 +27,22 @@ Example:
+               ranges = <0x00000000 0x18000000 0x00100000>;
+               #address-cells = <1>;
+               #size-cells = <1>;
++              #interrupt-cells = <1>;
++              interrupt-map-mask = <0x000fffff 0xffff>;
++              interrupt-map =
++                      /* Ethernet Controller 0 */
++                      <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
++
++                      /* Ethernet Controller 1 */
++                      <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
++
++                      /* PCIe Controller 0 */
++                      <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
++                      <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
++                      <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
++                      <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
++                      <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
++                      <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+ 
+               chipcommon {
+                       reg = <0x00000000 0x1000>;