AR8316_GCTRL_MTU, 9018 + 8 + 2);
/* enable cpu port to receive arp frames */
- ar8xxx_rmw(priv, AR8216_REG_ATU_CTRL,
- AR8236_ATU_CTRL_RES, AR8236_ATU_CTRL_RES);
+ ar8xxx_reg_set(priv, AR8216_REG_ATU_CTRL,
+ AR8236_ATU_CTRL_RES);
/* enable cpu port to receive multicast and broadcast frames */
- ar8xxx_rmw(priv, AR8216_REG_FLOOD_MASK,
- AR8236_FM_CPU_BROADCAST_EN | AR8236_FM_CPU_BCAST_FWD_EN,
+ ar8xxx_reg_set(priv, AR8216_REG_FLOOD_MASK,
AR8236_FM_CPU_BROADCAST_EN | AR8236_FM_CPU_BCAST_FWD_EN);
/* Enable MIB counters */
AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
(0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
for (port = 0; port < AR8216_NUM_PORTS; port++) {
- ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
- AR8216_PORT_CTRL_MIRROR_RX,
- 0);
+ ar8xxx_reg_clear(priv, AR8216_REG_PORT_CTRL(port),
+ AR8216_PORT_CTRL_MIRROR_RX);
- ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
- AR8216_PORT_CTRL_MIRROR_TX,
- 0);
+ ar8xxx_reg_clear(priv, AR8216_REG_PORT_CTRL(port),
+ AR8216_PORT_CTRL_MIRROR_TX);
}
/* now enable mirroring if necessary */
(priv->monitor_port << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
if (priv->mirror_rx)
- ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(priv->source_port),
- AR8216_PORT_CTRL_MIRROR_RX,
+ ar8xxx_reg_set(priv, AR8216_REG_PORT_CTRL(priv->source_port),
AR8216_PORT_CTRL_MIRROR_RX);
if (priv->mirror_tx)
- ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(priv->source_port),
- AR8216_PORT_CTRL_MIRROR_TX,
+ ar8xxx_reg_set(priv, AR8216_REG_PORT_CTRL(priv->source_port),
AR8216_PORT_CTRL_MIRROR_TX);
}
ar8xxx_sw_reset_switch(struct switch_dev *dev)
{
struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
+ const struct ar8xxx_chip *chip = priv->chip;
int i;
mutex_lock(&priv->reg_mutex);
/* Configure all ports */
for (i = 0; i < dev->ports; i++)
- priv->chip->init_port(priv, i);
+ chip->init_port(priv, i);
priv->mirror_rx = false;
priv->mirror_tx = false;
priv->source_port = 0;
priv->monitor_port = 0;
- priv->chip->init_globals(priv);
+ chip->init_globals(priv);
mutex_unlock(&priv->reg_mutex);
- return ar8xxx_sw_hw_apply(dev);
+ return chip->sw_hw_apply(dev);
}
int
return 0;
}
-static int
+int
ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
const struct switch_attr *attr,
struct switch_val *val)
return ret;
}
-static int
+int
ar8xxx_sw_get_port_mib(struct switch_dev *dev,
const struct switch_attr *attr,
struct switch_val *val)
.vtu_flush = ar8216_vtu_flush,
.vtu_load_vlan = ar8216_vtu_load_vlan,
.set_mirror_regs = ar8216_set_mirror_regs,
+ .sw_hw_apply = ar8xxx_sw_hw_apply,
.num_mibs = ARRAY_SIZE(ar8216_mibs),
.mib_decs = ar8216_mibs,
.vtu_flush = ar8216_vtu_flush,
.vtu_load_vlan = ar8216_vtu_load_vlan,
.set_mirror_regs = ar8216_set_mirror_regs,
+ .sw_hw_apply = ar8xxx_sw_hw_apply,
.num_mibs = ARRAY_SIZE(ar8236_mibs),
.mib_decs = ar8236_mibs,
.vtu_flush = ar8216_vtu_flush,
.vtu_load_vlan = ar8216_vtu_load_vlan,
.set_mirror_regs = ar8216_set_mirror_regs,
+ .sw_hw_apply = ar8xxx_sw_hw_apply,
.num_mibs = ARRAY_SIZE(ar8236_mibs),
.mib_decs = ar8236_mibs,