cns3xxx: update to linux 3.14

[15.05/openwrt.git] / target / linux / cns3xxx / patches-3.14 / 095-gpio_support.patch

diff --git a/target/linux/cns3xxx/patches-3.14/095-gpio_support.patch b/target/linux/cns3xxx/patches-3.14/095-gpio_support.patch
new file mode 100644 (file)
index 0000000..fead43a
--- /dev/null
+++ b/target/linux/cns3xxx/patches-3.14/095-gpio_support.patch
@@ -0,0 +1,82 @@
+--- a/arch/arm/mach-cns3xxx/cns3420vb.c
++++ b/arch/arm/mach-cns3xxx/cns3420vb.c
+@@ -245,6 +245,10 @@ static void __init cns3420_init(void)
+ 
+       cns3xxx_ahci_init();
+       cns3xxx_sdhci_init();
++      cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT, IRQ_CNS3XXX_GPIOA,
++              NR_IRQS_CNS3XXX);
++      cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, IRQ_CNS3XXX_GPIOB,
++              NR_IRQS_CNS3XXX + 32);
+ 
+       pm_power_off = cns3xxx_power_off;
+ }
+--- a/arch/arm/mach-cns3xxx/core.h
++++ b/arch/arm/mach-cns3xxx/core.h
+@@ -17,12 +17,6 @@ extern struct smp_operations cns3xxx_smp
+ extern void cns3xxx_timer_init(void);
+ extern void cns3xxx_pcie_iotable_init(void);
+ 
+-#ifdef CONFIG_CACHE_L2X0
+-void __init cns3xxx_l2x0_init(void);
+-#else
+-static inline void cns3xxx_l2x0_init(void) {}
+-#endif /* CONFIG_CACHE_L2X0 */
+-
+ void __init cns3xxx_map_io(void);
+ void __init cns3xxx_init_irq(void);
+ int  __init cns3xxx_pcie_init(void);
+--- a/arch/arm/mach-cns3xxx/Kconfig
++++ b/arch/arm/mach-cns3xxx/Kconfig
+@@ -2,6 +2,8 @@ config ARCH_CNS3XXX
+       bool "Cavium Networks CNS3XXX family" if ARCH_MULTI_V6
+       select ARM_GIC
+       select CPU_V6K
++      select ARCH_REQUIRE_GPIOLIB
++      select GENERIC_IRQ_CHIP
+       select GENERIC_CLOCKEVENTS
+       select MIGHT_HAVE_CACHE_L2X0
+       select MIGHT_HAVE_PCI
+--- a/arch/arm/mach-cns3xxx/Makefile
++++ b/arch/arm/mach-cns3xxx/Makefile
+@@ -1,7 +1,7 @@
+ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
+ 
+ obj-$(CONFIG_ARCH_CNS3XXX)            += cns3xxx.o
+-cns3xxx-y                             += core.o pm.o
++cns3xxx-y                             += core.o pm.o gpio.o
+ cns3xxx-$(CONFIG_ATAGS)                       += devices.o
+ cns3xxx-$(CONFIG_PCI)                 += pcie.o
+ cns3xxx-$(CONFIG_MACH_CNS3420VB)      += cns3420vb.o
+--- a/arch/arm/mach-cns3xxx/cns3xxx.h
++++ b/arch/arm/mach-cns3xxx/cns3xxx.h
+@@ -68,8 +68,10 @@
+ #define SMC_PCELL_ID_3_OFFSET                 0xFFC
+ 
+ #define CNS3XXX_GPIOA_BASE                    0x74000000      /* GPIO port A */
++#define CNS3XXX_GPIOA_BASE_VIRT                       0xFB006000
+ 
+ #define CNS3XXX_GPIOB_BASE                    0x74800000      /* GPIO port B */
++#define CNS3XXX_GPIOB_BASE_VIRT                       0xFB007000
+ 
+ #define CNS3XXX_RTC_BASE                      0x75000000      /* Real Time Clock */
+ 
+--- a/arch/arm/mach-cns3xxx/core.c
++++ b/arch/arm/mach-cns3xxx/core.c
+@@ -60,6 +60,16 @@ static struct map_desc cns3xxx_io_desc[]
+               .pfn            = __phys_to_pfn(CNS3XXX_PCIE1_IO_BASE),
+               .length         = SZ_16M,
+               .type           = MT_DEVICE,
++      }, {
++              .virtual        = CNS3XXX_GPIOA_BASE_VIRT,
++              .pfn            = __phys_to_pfn(CNS3XXX_GPIOA_BASE),
++              .length         = SZ_4K,
++              .type           = MT_DEVICE,
++      }, {
++              .virtual        = CNS3XXX_GPIOB_BASE_VIRT,
++              .pfn            = __phys_to_pfn(CNS3XXX_GPIOB_BASE),
++              .length         = SZ_4K,
++              .type           = MT_DEVICE,
+       },
+ };
+