ext_shift = 4;
break;
+ case BCM63268_CPU_ID:
-+ periph_bases[0] += PERF_IRQSTAT_63268_REG(0);
-+ periph_bases[1] += PERF_IRQSTAT_63268_REG(1);
++ periph_bases[0] += PERF_IRQMASK_63268_REG(0);
++ periph_bases[1] += PERF_IRQMASK_63268_REG(1);
+ periph_irq_count = 2;
+ periph_width = 4;
+
return -ENODEV;
ret = register_shared();
-@@ -295,8 +297,11 @@ bcm63xx_enetsw_register(const struct bcm
-
- if (BCMCPU_IS_6328())
+@@ -297,6 +299,8 @@ bcm63xx_enetsw_register(const struct bcm
enetsw_pd.num_ports = ENETSW_PORTS_6328;
-- else if (BCMCPU_IS_6362() || BCMCPU_IS_6368())
-+ else if (BCMCPU_IS_6362() || BCMCPU_IS_6368() ||
-+ BCMCPU_VARIANT_IS_63168() || BCMCPU_VARIANT_IS_63169())
+ else if (BCMCPU_IS_6362() || BCMCPU_IS_6368())
enetsw_pd.num_ports = ENETSW_PORTS_6368;
-+ else if (BCMCPU_VARIANT_IS_63268() || BCMCPU_VARIANT_IS_63269())
++ else if (BCMCPU_IS_63268())
+ enetsw_pd.num_ports = ENETSW_PORTS_63268;
enetsw_pd.dma_has_sram = true;