+
+/* Returns gpio for IRQ attached. Unchecked function */
+static inline int irq_to_gpio(unsigned irq) {
-+ return (irq - (AR531X_GPIO_IRQ(0)));
++ return irq - AR531X_GPIO_IRQ(0);
+}
+
+#include <asm-generic/gpio.h> /* cansleep wrappers */
+/*
+ * IRQs
+ */
-+#define AR2315_IRQ_MISC_INTRS MIPS_CPU_IRQ_BASE+2 /* C0_CAUSE: 0x0400 */
-+#define AR2315_IRQ_WLAN0_INTRS MIPS_CPU_IRQ_BASE+3 /* C0_CAUSE: 0x0800 */
-+#define AR2315_IRQ_ENET0_INTRS MIPS_CPU_IRQ_BASE+4 /* C0_CAUSE: 0x1000 */
-+#define AR2315_IRQ_LCBUS_PCI MIPS_CPU_IRQ_BASE+5 /* C0_CAUSE: 0x2000 */
-+#define AR2315_IRQ_WLAN0_POLL MIPS_CPU_IRQ_BASE+6 /* C0_CAUSE: 0x4000 */
++#define AR2315_IRQ_MISC_INTRS (MIPS_CPU_IRQ_BASE+2) /* C0_CAUSE: 0x0400 */
++#define AR2315_IRQ_WLAN0_INTRS (MIPS_CPU_IRQ_BASE+3) /* C0_CAUSE: 0x0800 */
++#define AR2315_IRQ_ENET0_INTRS (MIPS_CPU_IRQ_BASE+4) /* C0_CAUSE: 0x1000 */
++#define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
++#define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
+
+/*
+ * Address map
+ * IRQs
+ */
+
-+#define AR5312_IRQ_WLAN0_INTRS MIPS_CPU_IRQ_BASE+2 /* C0_CAUSE: 0x0400 */
-+#define AR5312_IRQ_ENET0_INTRS MIPS_CPU_IRQ_BASE+3 /* C0_CAUSE: 0x0800 */
-+#define AR5312_IRQ_ENET1_INTRS MIPS_CPU_IRQ_BASE+4 /* C0_CAUSE: 0x1000 */
-+#define AR5312_IRQ_WLAN1_INTRS MIPS_CPU_IRQ_BASE+5 /* C0_CAUSE: 0x2000 */
-+#define AR5312_IRQ_MISC_INTRS MIPS_CPU_IRQ_BASE+6 /* C0_CAUSE: 0x4000 */
++#define AR5312_IRQ_WLAN0_INTRS (MIPS_CPU_IRQ_BASE+2) /* C0_CAUSE: 0x0400 */
++#define AR5312_IRQ_ENET0_INTRS (MIPS_CPU_IRQ_BASE+3) /* C0_CAUSE: 0x0800 */
++#define AR5312_IRQ_ENET1_INTRS (MIPS_CPU_IRQ_BASE+4) /* C0_CAUSE: 0x1000 */
++#define AR5312_IRQ_WLAN1_INTRS (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
++#define AR5312_IRQ_MISC_INTRS (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
+
+
+/* Address Map */
+#define AR531X_RESET_WDOG 0x00100000 /* last reset was a watchdog */
+
+#define AR531X_RESET_WMAC0_BITS \
-+ AR531X_RESET_WLAN0 |\
-+ AR531X_RESET_WARM_WLAN0_MAC |\
-+ AR531X_RESET_WARM_WLAN0_BB
++ (AR531X_RESET_WLAN0 |\
++ AR531X_RESET_WARM_WLAN0_MAC |\
++ AR531X_RESET_WARM_WLAN0_BB)
+
+#define AR531X_RESERT_WMAC1_BITS \
-+ AR531X_RESET_WLAN1 |\
-+ AR531X_RESET_WARM_WLAN1_MAC |\
-+ AR531X_RESET_WARM_WLAN1_BB
++ (AR531X_RESET_WLAN1 |\
++ AR531X_RESET_WARM_WLAN1_MAC |\
++ AR531X_RESET_WARM_WLAN1_BB)
+
+/* AR5312_CLOCKCTL1 register bit field definitions */
+#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
+
--- /dev/null
+++ b/arch/mips/ar231x/ar5312.c
-@@ -0,0 +1,579 @@
+@@ -0,0 +1,580 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ .set = ar5312_gpio_set_value,
+ .get = ar5312_gpio_get_value,
+ .base = 0,
-+ .ngpio = AR531X_GPIO_IRQ_COUNT, // 22
++ .ngpio = AR531X_GPIO_IRQ_COUNT, /* 22 */
+ }
+};
+
-+// end of gpiolib
++/* end of gpiolib */
+
+static struct physmap_flash_data ar5312_flash_data = {
+ .width = 2,
+static int __init
+ar5312_cpu_frequency(void)
+{
-+ unsigned int result;
++ unsigned int scratch;
+ unsigned int predivide_mask, predivide_shift;
+ unsigned int multiplier_mask, multiplier_shift;
+ unsigned int clock_ctl1, predivide_select, predivisor, multiplier;
+ u16 devid;
+
+ /* Trust the bootrom's idea of cpu frequency. */
-+ if ((result = ar231x_read_reg(AR5312_SCRATCH)))
-+ return result;
++ scratch = ar231x_read_reg(AR5312_SCRATCH);
++ if (scratch)
++ return scratch;
+
+ devid = ar231x_read_reg(AR531X_REV);
+ devid &= AR531X_REV_MAJ;
+ u32 rett;
+ if (!(gpch->valid_mask & mask))
+ return 0;
-+ rett = ar2315_gpio_get(gpch->valid_mask); // legacy code
++ rett = ar2315_gpio_get(gpch->valid_mask); /* legacy code */
+ return !!(rett & mask);
+}
+
+ u32 mask = 1 << gpio;
+ if (!(gpch->valid_mask & mask))
+ return;
-+ ar2315_gpio_set(mask, (!!value) * mask); // legacy
++ ar2315_gpio_set(mask, (!!value) * mask); /* legacy */
+}
+
+static int
+ u32 mask = 1 << gpio;
+ if (!(gpch->valid_mask & mask))
+ return -ENXIO;
-+ ar2315_gpio_set_output(mask, 0); // legacy
++ ar2315_gpio_set_output(mask, 0); /* legacy */
+ return 0;
+}
+
+ u32 mask = 1 << gpio;
+ if (!(gpch->valid_mask & mask))
+ return -ENXIO;
-+ ar2315_gpio_set_output(mask, mask); // both legacy
++ ar2315_gpio_set_output(mask, mask); /* both legacy */
+ ar2315_gpio_set(mask, (!!value) * mask);
+ return 0;
+}
+ .set = ar2315_gpio_set_value,
+ .get = ar2315_gpio_get_value,
+ .base = 0,
-+ .ngpio = AR531X_GPIO_IRQ_COUNT, // 22
++ .ngpio = AR531X_GPIO_IRQ_COUNT, /* 22 */
+ }
+};
+
-+// end of gpiolib
++/* end of gpiolib */
+
+
+static struct ar231x_eth ar2315_eth_data = {
+#define AR531X_GPIO_IRQ_BASE 0x30
+
+/* Software's idea of interrupts handled by "CPU Interrupt Controller" */
-+#define AR531X_IRQ_NONE MIPS_CPU_IRQ_BASE+0
-+#define AR531X_IRQ_CPU_CLOCK MIPS_CPU_IRQ_BASE+7 /* C0_CAUSE: 0x8000 */
++#define AR531X_IRQ_NONE (MIPS_CPU_IRQ_BASE+0)
++#define AR531X_IRQ_CPU_CLOCK (MIPS_CPU_IRQ_BASE+7) /* C0_CAUSE: 0x8000 */
+
+/* Miscellaneous interrupts, which share IP6 */
-+#define AR531X_MISC_IRQ_NONE AR531X_MISC_IRQ_BASE+0
-+#define AR531X_MISC_IRQ_TIMER AR531X_MISC_IRQ_BASE+1
-+#define AR531X_MISC_IRQ_AHB_PROC AR531X_MISC_IRQ_BASE+2
-+#define AR531X_MISC_IRQ_AHB_DMA AR531X_MISC_IRQ_BASE+3
-+#define AR531X_MISC_IRQ_GPIO AR531X_MISC_IRQ_BASE+4
-+#define AR531X_MISC_IRQ_UART0 AR531X_MISC_IRQ_BASE+5
-+#define AR531X_MISC_IRQ_UART0_DMA AR531X_MISC_IRQ_BASE+6
-+#define AR531X_MISC_IRQ_WATCHDOG AR531X_MISC_IRQ_BASE+7
-+#define AR531X_MISC_IRQ_LOCAL AR531X_MISC_IRQ_BASE+8
-+#define AR531X_MISC_IRQ_SPI AR531X_MISC_IRQ_BASE+9
++#define AR531X_MISC_IRQ_NONE (AR531X_MISC_IRQ_BASE+0)
++#define AR531X_MISC_IRQ_TIMER (AR531X_MISC_IRQ_BASE+1)
++#define AR531X_MISC_IRQ_AHB_PROC (AR531X_MISC_IRQ_BASE+2)
++#define AR531X_MISC_IRQ_AHB_DMA (AR531X_MISC_IRQ_BASE+3)
++#define AR531X_MISC_IRQ_GPIO (AR531X_MISC_IRQ_BASE+4)
++#define AR531X_MISC_IRQ_UART0 (AR531X_MISC_IRQ_BASE+5)
++#define AR531X_MISC_IRQ_UART0_DMA (AR531X_MISC_IRQ_BASE+6)
++#define AR531X_MISC_IRQ_WATCHDOG (AR531X_MISC_IRQ_BASE+7)
++#define AR531X_MISC_IRQ_LOCAL (AR531X_MISC_IRQ_BASE+8)
++#define AR531X_MISC_IRQ_SPI (AR531X_MISC_IRQ_BASE+9)
+#define AR531X_MISC_IRQ_COUNT 10
+
+/* GPIO Interrupts [0..7], share AR531X_MISC_IRQ_GPIO */
-+#define AR531X_GPIO_IRQ_NONE AR531X_GPIO_IRQ_BASE+0
-+#define AR531X_GPIO_IRQ(n) AR531X_GPIO_IRQ_BASE+n
++#define AR531X_GPIO_IRQ_NONE (AR531X_GPIO_IRQ_BASE+0)
++#define AR531X_GPIO_IRQ(n) (AR531X_GPIO_IRQ_BASE+n)
+#define AR531X_GPIO_IRQ_COUNT 22
+
+static inline u32
projects / openwrt.git / blobdiff