--- /dev/null
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -96,6 +96,19 @@ config AR7
+ Support for the Texas Instruments AR7 System-on-a-Chip
+ family: TNETD7100, 7200 and 7300.
+
++config ATH25
++ bool "Atheros AR231x/AR531x SoC support"
++ select CEVT_R4K
++ select CSRC_R4K
++ select DMA_NONCOHERENT
++ select IRQ_CPU
++ select IRQ_DOMAIN
++ select SYS_HAS_CPU_MIPS32_R1
++ select SYS_SUPPORTS_BIG_ENDIAN
++ select SYS_SUPPORTS_32BIT_KERNEL
++ help
++ Support for Atheros AR231x and Atheros AR531x based boards
++
+ config ATH79
+ bool "Atheros AR71XX/AR724X/AR913X based boards"
+ select ARCH_REQUIRE_GPIOLIB
+@@ -835,6 +848,7 @@ config MIPS_PARAVIRT
+ endchoice
+
+ source "arch/mips/alchemy/Kconfig"
++source "arch/mips/ath25/Kconfig"
+ source "arch/mips/ath79/Kconfig"
+ source "arch/mips/bcm47xx/Kconfig"
+ source "arch/mips/bcm63xx/Kconfig"
+--- a/arch/mips/Kbuild.platforms
++++ b/arch/mips/Kbuild.platforms
+@@ -2,6 +2,7 @@
+
+ platforms += alchemy
+ platforms += ar7
++platforms += ath25
+ platforms += ath79
+ platforms += bcm47xx
+ platforms += bcm63xx
+--- /dev/null
++++ b/arch/mips/ath25/Platform
+@@ -0,0 +1,6 @@
++#
++# Atheros AR531X/AR231X WiSoC
++#
++platform-$(CONFIG_ATH25) += ath25/
++cflags-$(CONFIG_ATH25) += -I$(srctree)/arch/mips/include/asm/mach-ath25
++load-$(CONFIG_ATH25) += 0xffffffff80041000
+--- /dev/null
++++ b/arch/mips/ath25/Kconfig
+@@ -0,0 +1,9 @@
++config SOC_AR5312
++ bool "Atheros AR5312/AR2312+ SoC support"
++ depends on ATH25
++ default y
++
++config SOC_AR2315
++ bool "Atheros AR2315+ SoC support"
++ depends on ATH25
++ default y
+--- /dev/null
++++ b/arch/mips/ath25/Makefile
+@@ -0,0 +1,13 @@
++#
++# This file is subject to the terms and conditions of the GNU General Public
++# License. See the file "COPYING" in the main directory of this archive
++# for more details.
++#
++# Copyright (C) 2006 FON Technology, SL.
++# Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
++# Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
++#
++
++obj-y += board.o prom.o devices.o
++obj-$(CONFIG_SOC_AR5312) += ar5312.o
++obj-$(CONFIG_SOC_AR2315) += ar2315.o
+--- /dev/null
++++ b/arch/mips/ath25/board.c
+@@ -0,0 +1,234 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
++ * Copyright (C) 2006 FON Technology, SL.
++ * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
++ * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
++ */
++
++#include <linux/init.h>
++#include <linux/interrupt.h>
++#include <asm/irq_cpu.h>
++#include <asm/reboot.h>
++#include <asm/bootinfo.h>
++#include <asm/time.h>
++
++#include <ath25_platform.h>
++#include "devices.h"
++#include "ar5312.h"
++#include "ar2315.h"
++
++void (*ath25_irq_dispatch)(void);
++
++static inline bool check_radio_magic(const void __iomem *addr)
++{
++ addr += 0x7a; /* offset for flash magic */
++ return (__raw_readb(addr) == 0x5a) && (__raw_readb(addr + 1) == 0xa5);
++}
++
++static inline bool check_notempty(const void __iomem *addr)
++{
++ return __raw_readl(addr) != 0xffffffff;
++}
++
++static inline bool check_board_data(const void __iomem *addr, bool broken)
++{
++ /* config magic found */
++ if (__raw_readl(addr) == ATH25_BD_MAGIC)
++ return true;
++
++ if (!broken)
++ return false;
++
++ /* broken board data detected, use radio data to find the
++ * offset, user will fix this */
++
++ if (check_radio_magic(addr + 0x1000))
++ return true;
++ if (check_radio_magic(addr + 0xf8))
++ return true;
++
++ return false;
++}
++
++static const void __iomem * __init find_board_config(const void __iomem *limit,
++ const bool broken)
++{
++ const void __iomem *addr;
++ const void __iomem *begin = limit - 0x1000;
++ const void __iomem *end = limit - 0x30000;
++
++ for (addr = begin; addr >= end; addr -= 0x1000)
++ if (check_board_data(addr, broken))
++ return addr;
++
++ return NULL;
++}
++
++static const void __iomem * __init find_radio_config(const void __iomem *limit,
++ const void __iomem *bcfg)
++{
++ const void __iomem *rcfg, *begin, *end;
++
++ /*
++ * Now find the start of Radio Configuration data, using heuristics:
++ * Search forward from Board Configuration data by 0x1000 bytes
++ * at a time until we find non-0xffffffff.
++ */
++ begin = bcfg + 0x1000;
++ end = limit;
++ for (rcfg = begin; rcfg < end; rcfg += 0x1000)
++ if (check_notempty(rcfg) && check_radio_magic(rcfg))
++ return rcfg;
++
++ /* AR2316 relocates radio config to new location */
++ begin = bcfg + 0xf8;
++ end = limit - 0x1000 + 0xf8;
++ for (rcfg = begin; rcfg < end; rcfg += 0x1000)
++ if (check_notempty(rcfg) && check_radio_magic(rcfg))
++ return rcfg;
++
++ return NULL;
++}
++
++/*
++ * NB: Search region size could be larger than the actual flash size,
++ * but this shouldn't be a problem here, because the flash
++ * will simply be mapped multiple times.
++ */
++int __init ath25_find_config(phys_addr_t base, unsigned long size)
++{
++ const void __iomem *flash_base, *flash_limit;
++ struct ath25_boarddata *config;
++ unsigned int rcfg_size;
++ int broken_boarddata = 0;
++ const void __iomem *bcfg, *rcfg;
++ u8 *board_data;
++ u8 *radio_data;
++ u8 *mac_addr;
++ u32 offset;
++
++ flash_base = ioremap_nocache(base, size);
++ flash_limit = flash_base + size;
++
++ ath25_board.config = NULL;
++ ath25_board.radio = NULL;
++
++ /* Copy the board and radio data to RAM, because accessing the mapped
++ * memory of the flash directly after booting is not safe */
++
++ /* Try to find valid board and radio data */
++ bcfg = find_board_config(flash_limit, false);
++
++ /* If that fails, try to at least find valid radio data */
++ if (!bcfg) {
++ bcfg = find_board_config(flash_limit, true);
++ broken_boarddata = 1;
++ }
++
++ if (!bcfg) {
++ pr_warn("WARNING: No board configuration data found!\n");
++ goto error;
++ }
++
++ board_data = kzalloc(BOARD_CONFIG_BUFSZ, GFP_KERNEL);
++ ath25_board.config = (struct ath25_boarddata *)board_data;
++ memcpy_fromio(board_data, bcfg, 0x100);
++ if (broken_boarddata) {
++ pr_warn("WARNING: broken board data detected\n");
++ config = ath25_board.config;
++ if (is_zero_ether_addr(config->enet0_mac)) {
++ pr_info("Fixing up empty mac addresses\n");
++ config->reset_config_gpio = 0xffff;
++ config->sys_led_gpio = 0xffff;
++ random_ether_addr(config->wlan0_mac);
++ config->wlan0_mac[0] &= ~0x06;
++ random_ether_addr(config->enet0_mac);
++ random_ether_addr(config->enet1_mac);
++ }
++ }
++
++ /* Radio config starts 0x100 bytes after board config, regardless
++ * of what the physical layout on the flash chip looks like */
++
++ rcfg = find_radio_config(flash_limit, bcfg);
++ if (!rcfg) {
++ pr_warn("WARNING: Could not find Radio Configuration data\n");
++ goto error;
++ }
++
++ radio_data = board_data + 0x100 + ((rcfg - bcfg) & 0xfff);
++ ath25_board.radio = radio_data;
++ offset = radio_data - board_data;
++ pr_info("Radio config found at offset 0x%x (0x%x)\n", rcfg - bcfg,
++ offset);
++ rcfg_size = BOARD_CONFIG_BUFSZ - offset;
++ memcpy_fromio(radio_data, rcfg, rcfg_size);
++
++ mac_addr = &radio_data[0x1d * 2];
++ if (is_broadcast_ether_addr(mac_addr)) {
++ pr_info("Radio MAC is blank; using board-data\n");
++ ether_addr_copy(mac_addr, ath25_board.config->wlan0_mac);
++ }
++
++ iounmap(flash_base);
++
++ return 0;
++
++error:
++ iounmap(flash_base);
++ return -ENODEV;
++}
++
++static void ath25_halt(void)
++{
++ local_irq_disable();
++ unreachable();
++}
++
++void __init plat_mem_setup(void)
++{
++ _machine_halt = ath25_halt;
++ pm_power_off = ath25_halt;
++
++ if (is_ar5312())
++ ar5312_plat_mem_setup();
++ else
++ ar2315_plat_mem_setup();
++
++ /* Disable data watchpoints */
++ write_c0_watchlo0(0);
++}
++
++asmlinkage void plat_irq_dispatch(void)
++{
++ ath25_irq_dispatch();
++}
++
++void __init plat_time_init(void)
++{
++ if (is_ar5312())
++ ar5312_plat_time_init();
++ else
++ ar2315_plat_time_init();
++}
++
++unsigned int __cpuinit get_c0_compare_int(void)
++{
++ return CP0_LEGACY_COMPARE_IRQ;
++}
++
++void __init arch_init_irq(void)
++{
++ clear_c0_status(ST0_IM);
++ mips_cpu_irq_init();
++
++ /* Initialize interrupt controllers */
++ if (is_ar5312())
++ ar5312_arch_init_irq();
++ else
++ ar2315_arch_init_irq();
++}
+--- /dev/null
++++ b/arch/mips/ath25/prom.c
+@@ -0,0 +1,26 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright MontaVista Software Inc
++ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
++ * Copyright (C) 2006 FON Technology, SL.
++ * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
++ * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
++ */
++
++/*
++ * Prom setup file for AR5312/AR231x SoCs
++ */
++
++#include <linux/init.h>
++#include <asm/bootinfo.h>
++
++void __init prom_init(void)
++{
++}
++
++void __init prom_free_prom_memory(void)
++{
++}
+--- /dev/null
++++ b/arch/mips/include/asm/mach-ath25/ath25_platform.h
+@@ -0,0 +1,73 @@
++#ifndef __ASM_MACH_ATH25_PLATFORM_H
++#define __ASM_MACH_ATH25_PLATFORM_H
++
++#include <linux/etherdevice.h>
++
++/*
++ * This is board-specific data that is stored in a "fixed" location in flash.
++ * It is shared across operating systems, so it should not be changed lightly.
++ * The main reason we need it is in order to extract the ethernet MAC
++ * address(es).
++ */
++struct ath25_boarddata {
++ u32 magic; /* board data is valid */
++#define ATH25_BD_MAGIC 0x35333131 /* "5311", for all 531x/231x platforms */
++ u16 cksum; /* checksum (starting with BD_REV 2) */
++ u16 rev; /* revision of this struct */
++#define BD_REV 4
++ char board_name[64]; /* Name of board */
++ u16 major; /* Board major number */
++ u16 minor; /* Board minor number */
++ u32 flags; /* Board configuration */
++#define BD_ENET0 0x00000001 /* ENET0 is stuffed */
++#define BD_ENET1 0x00000002 /* ENET1 is stuffed */
++#define BD_UART1 0x00000004 /* UART1 is stuffed */
++#define BD_UART0 0x00000008 /* UART0 is stuffed (dma) */
++#define BD_RSTFACTORY 0x00000010 /* Reset factory defaults stuffed */
++#define BD_SYSLED 0x00000020 /* System LED stuffed */
++#define BD_EXTUARTCLK 0x00000040 /* External UART clock */
++#define BD_CPUFREQ 0x00000080 /* cpu freq is valid in nvram */
++#define BD_SYSFREQ 0x00000100 /* sys freq is set in nvram */
++#define BD_WLAN0 0x00000200 /* Enable WLAN0 */
++#define BD_MEMCAP 0x00000400 /* CAP SDRAM @ mem_cap for testing */
++#define BD_DISWATCHDOG 0x00000800 /* disable system watchdog */
++#define BD_WLAN1 0x00001000 /* Enable WLAN1 (ar5212) */
++#define BD_ISCASPER 0x00002000 /* FLAG for AR2312 */
++#define BD_WLAN0_2G_EN 0x00004000 /* FLAG for radio0_2G */
++#define BD_WLAN0_5G_EN 0x00008000 /* FLAG for radio0_2G */
++#define BD_WLAN1_2G_EN 0x00020000 /* FLAG for radio0_2G */
++#define BD_WLAN1_5G_EN 0x00040000 /* FLAG for radio0_2G */
++ u16 reset_config_gpio; /* Reset factory GPIO pin */
++ u16 sys_led_gpio; /* System LED GPIO pin */
++
++ u32 cpu_freq; /* CPU core frequency in Hz */
++ u32 sys_freq; /* System frequency in Hz */
++ u32 cnt_freq; /* Calculated C0_COUNT frequency */
++
++ u8 wlan0_mac[ETH_ALEN];
++ u8 enet0_mac[ETH_ALEN];
++ u8 enet1_mac[ETH_ALEN];
++
++ u16 pci_id; /* Pseudo PCIID for common code */
++ u16 mem_cap; /* cap bank1 in MB */
++
++ /* version 3 */
++ u8 wlan1_mac[ETH_ALEN]; /* (ar5212) */
++};
++
++#define BOARD_CONFIG_BUFSZ 0x1000
++
++/*
++ * Platform device information for the Wireless MAC
++ */
++struct ar231x_board_config {
++ u16 devid;
++
++ /* board config data */
++ struct ath25_boarddata *config;
++
++ /* radio calibration data */
++ const char *radio;
++};
++
++#endif /* __ASM_MACH_ATH25_PLATFORM_H */
+--- /dev/null
++++ b/arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h
+@@ -0,0 +1,64 @@
++/*
++ * Atheros AR231x/AR531x SoC specific CPU feature overrides
++ *
++ * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
++ *
++ * This file was derived from: include/asm-mips/cpu-features.h
++ * Copyright (C) 2003, 2004 Ralf Baechle
++ * Copyright (C) 2004 Maciej W. Rozycki
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ *
++ */
++#ifndef __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H
++#define __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H
++
++/*
++ * The Atheros AR531x/AR231x SoCs have MIPS 4Kc/4KEc core.
++ */
++#define cpu_has_tlb 1
++#define cpu_has_4kex 1
++#define cpu_has_3k_cache 0
++#define cpu_has_4k_cache 1
++#define cpu_has_tx39_cache 0
++#define cpu_has_sb1_cache 0
++#define cpu_has_fpu 0
++#define cpu_has_32fpr 0
++#define cpu_has_counter 1
++#define cpu_has_ejtag 1
++
++#if !defined(CONFIG_SOC_AR5312)
++# define cpu_has_llsc 1
++#else
++/*
++ * The MIPS 4Kc V0.9 core in the AR5312/AR2312 have problems with the
++ * ll/sc instructions.
++ */
++# define cpu_has_llsc 0
++#endif
++
++#define cpu_has_mips16 0
++#define cpu_has_mdmx 0
++#define cpu_has_mips3d 0
++#define cpu_has_smartmips 0
++
++#define cpu_has_mips32r1 1
++
++#if !defined(CONFIG_SOC_AR5312)
++# define cpu_has_mips32r2 1
++#endif
++
++#define cpu_has_mips64r1 0
++#define cpu_has_mips64r2 0
++
++#define cpu_has_dsp 0
++#define cpu_has_mipsmt 0
++
++#define cpu_has_64bits 0
++#define cpu_has_64bit_zero_reg 0
++#define cpu_has_64bit_gp_regs 0
++#define cpu_has_64bit_addresses 0
++
++#endif /* __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H */
+--- /dev/null
++++ b/arch/mips/include/asm/mach-ath25/dma-coherence.h
+@@ -0,0 +1,82 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
++ * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
++ *
++ */
++#ifndef __ASM_MACH_ATH25_DMA_COHERENCE_H
++#define __ASM_MACH_ATH25_DMA_COHERENCE_H
++
++#include <linux/device.h>
++
++/*
++ * We need some arbitrary non-zero value to be programmed to the BAR1 register
++ * of PCI host controller to enable DMA. The same value should be used as the
++ * offset to calculate the physical address of DMA buffer for PCI devices.
++ */
++#define AR2315_PCI_HOST_SDRAM_BASEADDR 0x20000000
++
++static inline dma_addr_t ath25_dev_offset(struct device *dev)
++{
++#ifdef CONFIG_PCI
++ extern struct bus_type pci_bus_type;
++
++ if (dev && dev->bus == &pci_bus_type)
++ return AR2315_PCI_HOST_SDRAM_BASEADDR;
++#endif
++ return 0;
++}
++
++static inline dma_addr_t
++plat_map_dma_mem(struct device *dev, void *addr, size_t size)
++{
++ return virt_to_phys(addr) + ath25_dev_offset(dev);
++}
++
++static inline dma_addr_t
++plat_map_dma_mem_page(struct device *dev, struct page *page)
++{
++ return page_to_phys(page) + ath25_dev_offset(dev);
++}
++
++static inline unsigned long
++plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr)
++{
++ return dma_addr - ath25_dev_offset(dev);
++}
++
++static inline void
++plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, size_t size,
++ enum dma_data_direction direction)
++{
++}
++
++static inline int plat_dma_supported(struct device *dev, u64 mask)
++{
++ return 1;
++}
++
++static inline void plat_extra_sync_for_device(struct device *dev)
++{
++}
++
++static inline int plat_dma_mapping_error(struct device *dev,
++ dma_addr_t dma_addr)
++{
++ return 0;
++}
++
++static inline int plat_device_is_coherent(struct device *dev)
++{
++#ifdef CONFIG_DMA_COHERENT
++ return 1;
++#endif
++#ifdef CONFIG_DMA_NONCOHERENT
++ return 0;
++#endif
++}
++
++#endif /* __ASM_MACH_ATH25_DMA_COHERENCE_H */
+--- /dev/null
++++ b/arch/mips/include/asm/mach-ath25/gpio.h
+@@ -0,0 +1,16 @@
++#ifndef __ASM_MACH_ATH25_GPIO_H
++#define __ASM_MACH_ATH25_GPIO_H
++
++#include <asm-generic/gpio.h>
++
++#define gpio_get_value __gpio_get_value
++#define gpio_set_value __gpio_set_value
++#define gpio_cansleep __gpio_cansleep
++#define gpio_to_irq __gpio_to_irq
++
++static inline int irq_to_gpio(unsigned irq)
++{
++ return -EINVAL;
++}
++
++#endif /* __ASM_MACH_ATH25_GPIO_H */
+--- /dev/null
++++ b/arch/mips/include/asm/mach-ath25/war.h
+@@ -0,0 +1,25 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2008 Felix Fietkau <nbd@openwrt.org>
++ */
++#ifndef __ASM_MACH_ATH25_WAR_H
++#define __ASM_MACH_ATH25_WAR_H
++
++#define R4600_V1_INDEX_ICACHEOP_WAR 0
++#define R4600_V1_HIT_CACHEOP_WAR 0
++#define R4600_V2_HIT_CACHEOP_WAR 0
++#define R5432_CP0_INTERRUPT_WAR 0
++#define BCM1250_M3_WAR 0
++#define SIBYTE_1956_WAR 0
++#define MIPS4K_ICACHE_REFILL_WAR 0
++#define MIPS_CACHE_SYNC_WAR 0
++#define TX49XX_ICACHE_INDEX_INV_WAR 0
++#define RM9000_CDEX_SMP_WAR 0
++#define ICACHE_REFILLS_WORKAROUND_WAR 0
++#define R10000_LLSC_WAR 0
++#define MIPS34K_MISSED_ITLB_WAR 0
++
++#endif /* __ASM_MACH_ATH25_WAR_H */
+--- /dev/null
++++ b/arch/mips/ath25/ar2315_regs.h
+@@ -0,0 +1,410 @@
++/*
++ * Register definitions for AR2315+
++ *
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
++ * Copyright (C) 2006 FON Technology, SL.
++ * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
++ * Copyright (C) 2006-2008 Felix Fietkau <nbd@openwrt.org>
++ */
++
++#ifndef __ASM_MACH_ATH25_AR2315_REGS_H
++#define __ASM_MACH_ATH25_AR2315_REGS_H
++
++/*
++ * IRQs
++ */
++#define AR2315_IRQ_MISC (MIPS_CPU_IRQ_BASE + 2) /* C0_CAUSE: 0x0400 */
++#define AR2315_IRQ_WLAN0 (MIPS_CPU_IRQ_BASE + 3) /* C0_CAUSE: 0x0800 */
++#define AR2315_IRQ_ENET0 (MIPS_CPU_IRQ_BASE + 4) /* C0_CAUSE: 0x1000 */
++#define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE + 5) /* C0_CAUSE: 0x2000 */
++#define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE + 6) /* C0_CAUSE: 0x4000 */
++
++/*
++ * Miscellaneous interrupts, which share IP2.
++ */
++#define AR2315_MISC_IRQ_UART0 0
++#define AR2315_MISC_IRQ_I2C_RSVD 1
++#define AR2315_MISC_IRQ_SPI 2
++#define AR2315_MISC_IRQ_AHB 3
++#define AR2315_MISC_IRQ_APB 4
++#define AR2315_MISC_IRQ_TIMER 5
++#define AR2315_MISC_IRQ_GPIO 6
++#define AR2315_MISC_IRQ_WATCHDOG 7
++#define AR2315_MISC_IRQ_IR_RSVD 8
++#define AR2315_MISC_IRQ_COUNT 9
++
++/*
++ * Address map
++ */
++#define AR2315_SPI_READ_BASE 0x08000000 /* SPI flash */
++#define AR2315_SPI_READ_SIZE 0x01000000
++#define AR2315_WLAN0_BASE 0x10000000 /* Wireless MMR */
++#define AR2315_PCI_BASE 0x10100000 /* PCI MMR */
++#define AR2315_PCI_SIZE 0x00001000
++#define AR2315_SDRAMCTL_BASE 0x10300000 /* SDRAM MMR */
++#define AR2315_SDRAMCTL_SIZE 0x00000020
++#define AR2315_LOCAL_BASE 0x10400000 /* Local bus MMR */
++#define AR2315_ENET0_BASE 0x10500000 /* Ethernet MMR */
++#define AR2315_RST_BASE 0x11000000 /* Reset control MMR */
++#define AR2315_RST_SIZE 0x00000100
++#define AR2315_UART0_BASE 0x11100000 /* UART MMR */
++#define AR2315_SPI_MMR_BASE 0x11300000 /* SPI flash MMR */
++#define AR2315_SPI_MMR_SIZE 0x00000010
++#define AR2315_PCI_EXT_BASE 0x80000000 /* PCI external */
++#define AR2315_PCI_EXT_SIZE 0x40000000
++
++/*
++ * Configuration registers
++ */
++
++/* Cold reset register */
++#define AR2315_COLD_RESET 0x0000
++
++#define AR2315_RESET_COLD_AHB 0x00000001
++#define AR2315_RESET_COLD_APB 0x00000002
++#define AR2315_RESET_COLD_CPU 0x00000004
++#define AR2315_RESET_COLD_CPUWARM 0x00000008
++#define AR2315_RESET_SYSTEM (RESET_COLD_CPU |\
++ RESET_COLD_APB |\
++ RESET_COLD_AHB) /* full system */
++#define AR2317_RESET_SYSTEM 0x00000010
++
++/* Reset register */
++#define AR2315_RESET 0x0004
++
++#define AR2315_RESET_WARM_WLAN0_MAC 0x00000001 /* warm reset WLAN0 MAC */
++#define AR2315_RESET_WARM_WLAN0_BB 0x00000002 /* warm reset WLAN0 BB */
++#define AR2315_RESET_MPEGTS_RSVD 0x00000004 /* warm reset MPEG-TS */
++#define AR2315_RESET_PCIDMA 0x00000008 /* warm reset PCI ahb/dma */
++#define AR2315_RESET_MEMCTL 0x00000010 /* warm reset mem control */
++#define AR2315_RESET_LOCAL 0x00000020 /* warm reset local bus */
++#define AR2315_RESET_I2C_RSVD 0x00000040 /* warm reset I2C bus */
++#define AR2315_RESET_SPI 0x00000080 /* warm reset SPI iface */
++#define AR2315_RESET_UART0 0x00000100 /* warm reset UART0 */
++#define AR2315_RESET_IR_RSVD 0x00000200 /* warm reset IR iface */
++#define AR2315_RESET_EPHY0 0x00000400 /* cold reset ENET0 phy */
++#define AR2315_RESET_ENET0 0x00000800 /* cold reset ENET0 MAC */
++
++/* AHB master arbitration control */
++#define AR2315_AHB_ARB_CTL 0x0008
++
++#define AR2315_ARB_CPU 0x00000001 /* CPU, default */
++#define AR2315_ARB_WLAN 0x00000002 /* WLAN */
++#define AR2315_ARB_MPEGTS_RSVD 0x00000004 /* MPEG-TS */
++#define AR2315_ARB_LOCAL 0x00000008 /* Local bus */
++#define AR2315_ARB_PCI 0x00000010 /* PCI bus */
++#define AR2315_ARB_ETHERNET 0x00000020 /* Ethernet */
++#define AR2315_ARB_RETRY 0x00000100 /* Retry policy (debug) */
++
++/* Config Register */
++#define AR2315_ENDIAN_CTL 0x000c
++
++#define AR2315_CONFIG_AHB 0x00000001 /* EC-AHB bridge endian */
++#define AR2315_CONFIG_WLAN 0x00000002 /* WLAN byteswap */
++#define AR2315_CONFIG_MPEGTS_RSVD 0x00000004 /* MPEG-TS byteswap */
++#define AR2315_CONFIG_PCI 0x00000008 /* PCI byteswap */
++#define AR2315_CONFIG_MEMCTL 0x00000010 /* Mem controller endian */
++#define AR2315_CONFIG_LOCAL 0x00000020 /* Local bus byteswap */
++#define AR2315_CONFIG_ETHERNET 0x00000040 /* Ethernet byteswap */
++#define AR2315_CONFIG_MERGE 0x00000200 /* CPU write buffer merge */
++#define AR2315_CONFIG_CPU 0x00000400 /* CPU big endian */
++#define AR2315_CONFIG_BIG 0x00000400
++#define AR2315_CONFIG_PCIAHB 0x00000800
++#define AR2315_CONFIG_PCIAHB_BRIDGE 0x00001000
++#define AR2315_CONFIG_SPI 0x00008000 /* SPI byteswap */
++#define AR2315_CONFIG_CPU_DRAM 0x00010000
++#define AR2315_CONFIG_CPU_PCI 0x00020000
++#define AR2315_CONFIG_CPU_MMR 0x00040000
++
++/* NMI control */
++#define AR2315_NMI_CTL 0x0010
++
++#define AR2315_NMI_EN 1
++
++/* Revision Register - Initial value is 0x3010 (WMAC 3.0, AR231X 1.0). */
++#define AR2315_SREV 0x0014
++
++#define AR2315_REV_MAJ 0x000000f0
++#define AR2315_REV_MAJ_S 4
++#define AR2315_REV_MIN 0x0000000f
++#define AR2315_REV_MIN_S 0
++#define AR2315_REV_CHIP (AR2315_REV_MAJ | AR2315_REV_MIN)
++
++/* Interface Enable */
++#define AR2315_IF_CTL 0x0018
++
++#define AR2315_IF_MASK 0x00000007
++#define AR2315_IF_DISABLED 0 /* Disable all */
++#define AR2315_IF_PCI 1 /* PCI */
++#define AR2315_IF_TS_LOCAL 2 /* Local bus */
++#define AR2315_IF_ALL 3 /* Emulation only */
++#define AR2315_IF_LOCAL_HOST 0x00000008
++#define AR2315_IF_PCI_HOST 0x00000010
++#define AR2315_IF_PCI_INTR 0x00000020
++#define AR2315_IF_PCI_CLK_MASK 0x00030000
++#define AR2315_IF_PCI_CLK_INPUT 0
++#define AR2315_IF_PCI_CLK_OUTPUT_LOW 1
++#define AR2315_IF_PCI_CLK_OUTPUT_CLK 2
++#define AR2315_IF_PCI_CLK_OUTPUT_HIGH 3
++#define AR2315_IF_PCI_CLK_SHIFT 16
++
++/* APB Interrupt control */
++#define AR2315_ISR 0x0020
++#define AR2315_IMR 0x0024
++#define AR2315_GISR 0x0028
++
++#define AR2315_ISR_UART0 0x00000001 /* high speed UART */
++#define AR2315_ISR_I2C_RSVD 0x00000002 /* I2C bus */
++#define AR2315_ISR_SPI 0x00000004 /* SPI bus */
++#define AR2315_ISR_AHB 0x00000008 /* AHB error */
++#define AR2315_ISR_APB 0x00000010 /* APB error */
++#define AR2315_ISR_TIMER 0x00000020 /* Timer */
++#define AR2315_ISR_GPIO 0x00000040 /* GPIO */
++#define AR2315_ISR_WD 0x00000080 /* Watchdog */
++#define AR2315_ISR_IR_RSVD 0x00000100 /* IR */
++
++#define AR2315_GISR_MISC 0x00000001 /* Misc */
++#define AR2315_GISR_WLAN0 0x00000002 /* WLAN0 */
++#define AR2315_GISR_MPEGTS_RSVD 0x00000004 /* MPEG-TS */
++#define AR2315_GISR_LOCALPCI 0x00000008 /* Local/PCI bus */
++#define AR2315_GISR_WMACPOLL 0x00000010
++#define AR2315_GISR_TIMER 0x00000020
++#define AR2315_GISR_ETHERNET 0x00000040 /* Ethernet */
++
++/* Generic timer */
++#define AR2315_TIMER 0x0030
++#define AR2315_RELOAD 0x0034
++
++/* Watchdog timer */
++#define AR2315_WDT_TIMER 0x0038
++#define AR2315_WDT_CTRL 0x003c
++
++#define AR2315_WDT_CTRL_IGNORE 0x00000000 /* ignore expiration */
++#define AR2315_WDT_CTRL_NMI 0x00000001 /* NMI on watchdog */
++#define AR2315_WDT_CTRL_RESET 0x00000002 /* reset on watchdog */
++
++/* CPU Performance Counters */
++#define AR2315_PERFCNT0 0x0048
++#define AR2315_PERFCNT1 0x004c
++
++#define AR2315_PERF0_DATAHIT 0x00000001 /* Count Data Cache Hits */
++#define AR2315_PERF0_DATAMISS 0x00000002 /* Count Data Cache Misses */
++#define AR2315_PERF0_INSTHIT 0x00000004 /* Count Instruction Cache Hits */
++#define AR2315_PERF0_INSTMISS 0x00000008 /* Count Instruction Cache Misses */
++#define AR2315_PERF0_ACTIVE 0x00000010 /* Count Active Processor Cycles */
++#define AR2315_PERF0_WBHIT 0x00000020 /* Count CPU Write Buffer Hits */
++#define AR2315_PERF0_WBMISS 0x00000040 /* Count CPU Write Buffer Misses */
++
++#define AR2315_PERF1_EB_ARDY 0x00000001 /* Count EB_ARdy signal */
++#define AR2315_PERF1_EB_AVALID 0x00000002 /* Count EB_AValid signal */
++#define AR2315_PERF1_EB_WDRDY 0x00000004 /* Count EB_WDRdy signal */
++#define AR2315_PERF1_EB_RDVAL 0x00000008 /* Count EB_RdVal signal */
++#define AR2315_PERF1_VRADDR 0x00000010 /* Count valid read address cycles*/
++#define AR2315_PERF1_VWADDR 0x00000020 /* Count valid write address cycl.*/
++#define AR2315_PERF1_VWDATA 0x00000040 /* Count valid write data cycles */
++
++/* AHB Error Reporting */
++#define AR2315_AHB_ERR0 0x0050 /* error */
++#define AR2315_AHB_ERR1 0x0054 /* haddr */
++#define AR2315_AHB_ERR2 0x0058 /* hwdata */
++#define AR2315_AHB_ERR3 0x005c /* hrdata */
++#define AR2315_AHB_ERR4 0x0060 /* status */
++
++#define AR2315_AHB_ERROR_DET 1 /* AHB Error has been detected, */
++ /* write 1 to clear all bits in ERR0 */
++#define AR2315_AHB_ERROR_OVR 2 /* AHB Error overflow has been detected */
++#define AR2315_AHB_ERROR_WDT 4 /* AHB Error due to wdt instead of hresp */
++
++#define AR2315_PROCERR_HMAST 0x0000000f
++#define AR2315_PROCERR_HMAST_DFLT 0
++#define AR2315_PROCERR_HMAST_WMAC 1
++#define AR2315_PROCERR_HMAST_ENET 2
++#define AR2315_PROCERR_HMAST_PCIENDPT 3
++#define AR2315_PROCERR_HMAST_LOCAL 4
++#define AR2315_PROCERR_HMAST_CPU 5
++#define AR2315_PROCERR_HMAST_PCITGT 6
++#define AR2315_PROCERR_HMAST_S 0
++#define AR2315_PROCERR_HWRITE 0x00000010
++#define AR2315_PROCERR_HSIZE 0x00000060
++#define AR2315_PROCERR_HSIZE_S 5
++#define AR2315_PROCERR_HTRANS 0x00000180
++#define AR2315_PROCERR_HTRANS_S 7
++#define AR2315_PROCERR_HBURST 0x00000e00
++#define AR2315_PROCERR_HBURST_S 9
++
++/* Clock Control */
++#define AR2315_PLLC_CTL 0x0064
++#define AR2315_PLLV_CTL 0x0068
++#define AR2315_CPUCLK 0x006c
++#define AR2315_AMBACLK 0x0070
++#define AR2315_SYNCCLK 0x0074
++#define AR2315_DSL_SLEEP_CTL 0x0080
++#define AR2315_DSL_SLEEP_DUR 0x0084
++
++/* PLLc Control fields */
++#define AR2315_PLLC_REF_DIV_M 0x00000003
++#define AR2315_PLLC_REF_DIV_S 0
++#define AR2315_PLLC_FDBACK_DIV_M 0x0000007c
++#define AR2315_PLLC_FDBACK_DIV_S 2
++#define AR2315_PLLC_ADD_FDBACK_DIV_M 0x00000080
++#define AR2315_PLLC_ADD_FDBACK_DIV_S 7
++#define AR2315_PLLC_CLKC_DIV_M 0x0001c000
++#define AR2315_PLLC_CLKC_DIV_S 14
++#define AR2315_PLLC_CLKM_DIV_M 0x00700000
++#define AR2315_PLLC_CLKM_DIV_S 20
++
++/* CPU CLK Control fields */
++#define AR2315_CPUCLK_CLK_SEL_M 0x00000003
++#define AR2315_CPUCLK_CLK_SEL_S 0
++#define AR2315_CPUCLK_CLK_DIV_M 0x0000000c
++#define AR2315_CPUCLK_CLK_DIV_S 2
++
++/* AMBA CLK Control fields */
++#define AR2315_AMBACLK_CLK_SEL_M 0x00000003
++#define AR2315_AMBACLK_CLK_SEL_S 0
++#define AR2315_AMBACLK_CLK_DIV_M 0x0000000c
++#define AR2315_AMBACLK_CLK_DIV_S 2
++
++/* PCI Clock Control */
++#define AR2315_PCICLK 0x00a4
++
++#define AR2315_PCICLK_INPUT_M 0x00000003
++#define AR2315_PCICLK_INPUT_S 0
++#define AR2315_PCICLK_PLLC_CLKM 0
++#define AR2315_PCICLK_PLLC_CLKM1 1
++#define AR2315_PCICLK_PLLC_CLKC 2
++#define AR2315_PCICLK_REF_CLK 3
++#define AR2315_PCICLK_DIV_M 0x0000000c
++#define AR2315_PCICLK_DIV_S 2
++#define AR2315_PCICLK_IN_FREQ 0
++#define AR2315_PCICLK_IN_FREQ_DIV_6 1
++#define AR2315_PCICLK_IN_FREQ_DIV_8 2
++#define AR2315_PCICLK_IN_FREQ_DIV_10 3
++
++/* Observation Control Register */
++#define AR2315_OCR 0x00b0
++
++#define AR2315_OCR_GPIO0_IRIN 0x00000040
++#define AR2315_OCR_GPIO1_IROUT 0x00000080
++#define AR2315_OCR_GPIO3_RXCLR 0x00000200
++
++/* General Clock Control */
++#define AR2315_MISCCLK 0x00b4
++
++#define AR2315_MISCCLK_PLLBYPASS_EN 0x00000001
++#define AR2315_MISCCLK_PROCREFCLK 0x00000002
++
++/*
++ * SDRAM Controller
++ * - No read or write buffers are included.
++ */
++#define AR2315_MEM_CFG 0x0000
++#define AR2315_MEM_CTRL 0x000c
++#define AR2315_MEM_REF 0x0010
++
++#define AR2315_MEM_CFG_DATA_WIDTH_M 0x00006000
++#define AR2315_MEM_CFG_DATA_WIDTH_S 13
++#define AR2315_MEM_CFG_COL_WIDTH_M 0x00001e00
++#define AR2315_MEM_CFG_COL_WIDTH_S 9
++#define AR2315_MEM_CFG_ROW_WIDTH_M 0x000001e0
++#define AR2315_MEM_CFG_ROW_WIDTH_S 5
++#define AR2315_MEM_CFG_BANKADDR_BITS_M 0x00000018
++#define AR2315_MEM_CFG_BANKADDR_BITS_S 3
++
++/*
++ * Local Bus Interface Registers
++ */
++#define AR2315_LB_CONFIG 0x0000
++
++#define AR2315_LBCONF_OE 0x00000001 /* =1 OE is low-true */
++#define AR2315_LBCONF_CS0 0x00000002 /* =1 first CS is low-true */
++#define AR2315_LBCONF_CS1 0x00000004 /* =1 2nd CS is low-true */
++#define AR2315_LBCONF_RDY 0x00000008 /* =1 RDY is low-true */
++#define AR2315_LBCONF_WE 0x00000010 /* =1 Write En is low-true */
++#define AR2315_LBCONF_WAIT 0x00000020 /* =1 WAIT is low-true */
++#define AR2315_LBCONF_ADS 0x00000040 /* =1 Adr Strobe is low-true */
++#define AR2315_LBCONF_MOT 0x00000080 /* =0 Intel, =1 Motorola */
++#define AR2315_LBCONF_8CS 0x00000100 /* =1 8 bits CS, 0= 16bits */
++#define AR2315_LBCONF_8DS 0x00000200 /* =1 8 bits Data S, 0=16bits */
++#define AR2315_LBCONF_ADS_EN 0x00000400 /* =1 Enable ADS */
++#define AR2315_LBCONF_ADR_OE 0x00000800 /* =1 Adr cap on OE, WE or DS */
++#define AR2315_LBCONF_ADDT_MUX 0x00001000 /* =1 Adr and Data share bus */
++#define AR2315_LBCONF_DATA_OE 0x00002000 /* =1 Data cap on OE, WE, DS */
++#define AR2315_LBCONF_16DATA 0x00004000 /* =1 Data is 16 bits wide */
++#define AR2315_LBCONF_SWAPDT 0x00008000 /* =1 Byte swap data */
++#define AR2315_LBCONF_SYNC 0x00010000 /* =1 Bus synchronous to clk */
++#define AR2315_LBCONF_INT 0x00020000 /* =1 Intr is low true */
++#define AR2315_LBCONF_INT_CTR0 0x00000000 /* GND high-Z, Vdd is high-Z */
++#define AR2315_LBCONF_INT_CTR1 0x00040000 /* GND drive, Vdd is high-Z */
++#define AR2315_LBCONF_INT_CTR2 0x00080000 /* GND high-Z, Vdd drive */
++#define AR2315_LBCONF_INT_CTR3 0x000c0000 /* GND drive, Vdd drive */
++#define AR2315_LBCONF_RDY_WAIT 0x00100000 /* =1 RDY is negative of WAIT */
++#define AR2315_LBCONF_INT_PULSE 0x00200000 /* =1 Interrupt is a pulse */
++#define AR2315_LBCONF_ENABLE 0x00400000 /* =1 Falcon respond to LB */
++
++#define AR2315_LB_CLKSEL 0x0004
++
++#define AR2315_LBCLK_EXT 0x00000001 /* use external clk for lb */
++
++#define AR2315_LB_1MS 0x0008
++
++#define AR2315_LB1MS_MASK 0x0003ffff /* # of AHB clk cycles in 1ms */
++
++#define AR2315_LB_MISCCFG 0x000c
++
++#define AR2315_LBM_TXD_EN 0x00000001 /* Enable TXD for fragments */
++#define AR2315_LBM_RX_INTEN 0x00000002 /* Enable LB ints on RX ready */
++#define AR2315_LBM_MBOXWR_INTEN 0x00000004 /* Enable LB ints on mbox wr */
++#define AR2315_LBM_MBOXRD_INTEN 0x00000008 /* Enable LB ints on mbox rd */
++#define AR2315_LMB_DESCSWAP_EN 0x00000010 /* Byte swap desc enable */
++#define AR2315_LBM_TIMEOUT_M 0x00ffff80
++#define AR2315_LBM_TIMEOUT_S 7
++#define AR2315_LBM_PORTMUX 0x07000000
++
++#define AR2315_LB_RXTSOFF 0x0010
++
++#define AR2315_LB_TX_CHAIN_EN 0x0100
++
++#define AR2315_LB_TXEN_0 0x00000001
++#define AR2315_LB_TXEN_1 0x00000002
++#define AR2315_LB_TXEN_2 0x00000004
++#define AR2315_LB_TXEN_3 0x00000008
++
++#define AR2315_LB_TX_CHAIN_DIS 0x0104
++#define AR2315_LB_TX_DESC_PTR 0x0200
++
++#define AR2315_LB_RX_CHAIN_EN 0x0400
++
++#define AR2315_LB_RXEN 0x00000001
++
++#define AR2315_LB_RX_CHAIN_DIS 0x0404
++#define AR2315_LB_RX_DESC_PTR 0x0408
++
++#define AR2315_LB_INT_STATUS 0x0500
++
++#define AR2315_LB_INT_TX_DESC 0x00000001
++#define AR2315_LB_INT_TX_OK 0x00000002
++#define AR2315_LB_INT_TX_ERR 0x00000004
++#define AR2315_LB_INT_TX_EOF 0x00000008
++#define AR2315_LB_INT_RX_DESC 0x00000010
++#define AR2315_LB_INT_RX_OK 0x00000020
++#define AR2315_LB_INT_RX_ERR 0x00000040
++#define AR2315_LB_INT_RX_EOF 0x00000080
++#define AR2315_LB_INT_TX_TRUNC 0x00000100
++#define AR2315_LB_INT_TX_STARVE 0x00000200
++#define AR2315_LB_INT_LB_TIMEOUT 0x00000400
++#define AR2315_LB_INT_LB_ERR 0x00000800
++#define AR2315_LB_INT_MBOX_WR 0x00001000
++#define AR2315_LB_INT_MBOX_RD 0x00002000
++
++/* Bit definitions for INT MASK are the same as INT_STATUS */
++#define AR2315_LB_INT_MASK 0x0504
++
++#define AR2315_LB_INT_EN 0x0508
++#define AR2315_LB_MBOX 0x0600
++
++#endif /* __ASM_MACH_ATH25_AR2315_REGS_H */
+--- /dev/null
++++ b/arch/mips/ath25/ar5312_regs.h
+@@ -0,0 +1,224 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
++ * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
++ * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
++ */
++
++#ifndef __ASM_MACH_ATH25_AR5312_REGS_H
++#define __ASM_MACH_ATH25_AR5312_REGS_H
++
++/*
++ * IRQs
++ */
++#define AR5312_IRQ_WLAN0 (MIPS_CPU_IRQ_BASE + 2) /* C0_CAUSE: 0x0400 */
++#define AR5312_IRQ_ENET0 (MIPS_CPU_IRQ_BASE + 3) /* C0_CAUSE: 0x0800 */
++#define AR5312_IRQ_ENET1 (MIPS_CPU_IRQ_BASE + 4) /* C0_CAUSE: 0x1000 */
++#define AR5312_IRQ_WLAN1 (MIPS_CPU_IRQ_BASE + 5) /* C0_CAUSE: 0x2000 */
++#define AR5312_IRQ_MISC (MIPS_CPU_IRQ_BASE + 6) /* C0_CAUSE: 0x4000 */
++
++/*
++ * Miscellaneous interrupts, which share IP6.
++ */
++#define AR5312_MISC_IRQ_TIMER 0
++#define AR5312_MISC_IRQ_AHB_PROC 1
++#define AR5312_MISC_IRQ_AHB_DMA 2
++#define AR5312_MISC_IRQ_GPIO 3
++#define AR5312_MISC_IRQ_UART0 4
++#define AR5312_MISC_IRQ_UART0_DMA 5
++#define AR5312_MISC_IRQ_WATCHDOG 6
++#define AR5312_MISC_IRQ_LOCAL 7
++#define AR5312_MISC_IRQ_SPI 8
++#define AR5312_MISC_IRQ_COUNT 9
++
++/*
++ * Address Map
++ *
++ * The AR5312 supports 2 enet MACS, even though many reference boards only
++ * actually use 1 of them (i.e. Only MAC 0 is actually connected to an enet
++ * PHY or PHY switch. The AR2312 supports 1 enet MAC.
++ */
++#define AR5312_WLAN0_BASE 0x18000000
++#define AR5312_ENET0_BASE 0x18100000
++#define AR5312_ENET1_BASE 0x18200000
++#define AR5312_SDRAMCTL_BASE 0x18300000
++#define AR5312_SDRAMCTL_SIZE 0x00000010
++#define AR5312_FLASHCTL_BASE 0x18400000
++#define AR5312_FLASHCTL_SIZE 0x00000010
++#define AR5312_WLAN1_BASE 0x18500000
++#define AR5312_UART0_BASE 0x1c000000 /* UART MMR */
++#define AR5312_GPIO_BASE 0x1c002000
++#define AR5312_GPIO_SIZE 0x00000010
++#define AR5312_RST_BASE 0x1c003000
++#define AR5312_RST_SIZE 0x00000100
++#define AR5312_FLASH_BASE 0x1e000000
++#define AR5312_FLASH_SIZE 0x00800000
++
++/*
++ * Need these defines to determine true number of ethernet MACs
++ */
++#define AR5312_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
++#define AR5312_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
++#define AR5312_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */
++
++/* Reset/Timer Block Address Map */
++#define AR5312_TIMER 0x0000 /* countdown timer */
++#define AR5312_RELOAD 0x0004 /* timer reload value */
++#define AR5312_WDT_CTRL 0x0008 /* watchdog cntrl */
++#define AR5312_WDT_TIMER 0x000c /* watchdog timer */
++#define AR5312_ISR 0x0010 /* Intr Status Reg */
++#define AR5312_IMR 0x0014 /* Intr Mask Reg */
++#define AR5312_RESET 0x0020
++#define AR5312_CLOCKCTL1 0x0064
++#define AR5312_SCRATCH 0x006c
++#define AR5312_PROCADDR 0x0070
++#define AR5312_PROC1 0x0074
++#define AR5312_DMAADDR 0x0078
++#define AR5312_DMA1 0x007c
++#define AR5312_ENABLE 0x0080 /* interface enb */
++#define AR5312_REV 0x0090 /* revision */
++
++/* AR5312_WDT_CTRL register bit field definitions */
++#define AR5312_WDT_CTRL_IGNORE 0x00000000 /* ignore expiration */
++#define AR5312_WDT_CTRL_NMI 0x00000001
++#define AR5312_WDT_CTRL_RESET 0x00000002
++
++/* AR5312_ISR register bit field definitions */
++#define AR5312_ISR_TIMER 0x00000001
++#define AR5312_ISR_AHBPROC 0x00000002
++#define AR5312_ISR_AHBDMA 0x00000004
++#define AR5312_ISR_GPIO 0x00000008
++#define AR5312_ISR_UART0 0x00000010
++#define AR5312_ISR_UART0DMA 0x00000020
++#define AR5312_ISR_WD 0x00000040
++#define AR5312_ISR_LOCAL 0x00000080
++
++/* AR5312_RESET register bit field definitions */
++#define AR5312_RESET_SYSTEM 0x00000001 /* cold reset full system */
++#define AR5312_RESET_PROC 0x00000002 /* cold reset MIPS core */
++#define AR5312_RESET_WLAN0 0x00000004 /* cold reset WLAN MAC/BB */
++#define AR5312_RESET_EPHY0 0x00000008 /* cold reset ENET0 phy */
++#define AR5312_RESET_EPHY1 0x00000010 /* cold reset ENET1 phy */
++#define AR5312_RESET_ENET0 0x00000020 /* cold reset ENET0 MAC */
++#define AR5312_RESET_ENET1 0x00000040 /* cold reset ENET1 MAC */
++#define AR5312_RESET_UART0 0x00000100 /* cold reset UART0 */
++#define AR5312_RESET_WLAN1 0x00000200 /* cold reset WLAN MAC/BB */
++#define AR5312_RESET_APB 0x00000400 /* cold reset APB ar5312 */
++#define AR5312_RESET_WARM_PROC 0x00001000 /* warm reset MIPS core */
++#define AR5312_RESET_WARM_WLAN0_MAC 0x00002000 /* warm reset WLAN0 MAC */
++#define AR5312_RESET_WARM_WLAN0_BB 0x00004000 /* warm reset WLAN0 BB */
++#define AR5312_RESET_NMI 0x00010000 /* send an NMI to the CPU */
++#define AR5312_RESET_WARM_WLAN1_MAC 0x00020000 /* warm reset WLAN1 MAC */
++#define AR5312_RESET_WARM_WLAN1_BB 0x00040000 /* warm reset WLAN1 BB */
++#define AR5312_RESET_LOCAL_BUS 0x00080000 /* reset local bus */
++#define AR5312_RESET_WDOG 0x00100000 /* last reset was a wdt */
++
++#define AR5312_RESET_WMAC0_BITS (AR5312_RESET_WLAN0 |\
++ AR5312_RESET_WARM_WLAN0_MAC |\
++ AR5312_RESET_WARM_WLAN0_BB)
++
++#define AR5312_RESET_WMAC1_BITS (AR5312_RESET_WLAN1 |\
++ AR5312_RESET_WARM_WLAN1_MAC |\
++ AR5312_RESET_WARM_WLAN1_BB)
++
++/* AR5312_CLOCKCTL1 register bit field definitions */
++#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
++#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
++#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
++#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
++#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
++
++/* Valid for AR5312 and AR2312 */
++#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
++#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
++#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
++#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
++#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
++
++/* Valid for AR2313 */
++#define AR2313_CLOCKCTL1_PREDIVIDE_MASK 0x00003000
++#define AR2313_CLOCKCTL1_PREDIVIDE_SHIFT 12
++#define AR2313_CLOCKCTL1_MULTIPLIER_MASK 0x001f0000
++#define AR2313_CLOCKCTL1_MULTIPLIER_SHIFT 16
++#define AR2313_CLOCKCTL1_DOUBLER_MASK 0x00000000
++
++/* AR5312_ENABLE register bit field definitions */
++#define AR5312_ENABLE_WLAN0 0x00000001
++#define AR5312_ENABLE_ENET0 0x00000002
++#define AR5312_ENABLE_ENET1 0x00000004
++#define AR5312_ENABLE_UART_AND_WLAN1_PIO 0x00000008/* UART & WLAN1 PIO */
++#define AR5312_ENABLE_WLAN1_DMA 0x00000010/* WLAN1 DMAs */
++#define AR5312_ENABLE_WLAN1 (AR5312_ENABLE_UART_AND_WLAN1_PIO |\
++ AR5312_ENABLE_WLAN1_DMA)
++
++/* AR5312_REV register bit field definitions */
++#define AR5312_REV_WMAC_MAJ 0x0000f000
++#define AR5312_REV_WMAC_MAJ_S 12
++#define AR5312_REV_WMAC_MIN 0x00000f00
++#define AR5312_REV_WMAC_MIN_S 8
++#define AR5312_REV_MAJ 0x000000f0
++#define AR5312_REV_MAJ_S 4
++#define AR5312_REV_MIN 0x0000000f
++#define AR5312_REV_MIN_S 0
++#define AR5312_REV_CHIP (AR5312_REV_MAJ|AR5312_REV_MIN)
++
++/* Major revision numbers, bits 7..4 of Revision ID register */
++#define AR5312_REV_MAJ_AR5312 0x4
++#define AR5312_REV_MAJ_AR2313 0x5
++
++/* Minor revision numbers, bits 3..0 of Revision ID register */
++#define AR5312_REV_MIN_DUAL 0x0 /* Dual WLAN version */
++#define AR5312_REV_MIN_SINGLE 0x1 /* Single WLAN version */
++
++/*
++ * ARM Flash Controller -- 3 flash banks with either x8 or x16 devices
++ */
++#define AR5312_FLASHCTL0 0x0000
++#define AR5312_FLASHCTL1 0x0004
++#define AR5312_FLASHCTL2 0x0008
++
++/* AR5312_FLASHCTL register bit field definitions */
++#define AR5312_FLASHCTL_IDCY 0x0000000f /* Idle cycle turnaround time */
++#define AR5312_FLASHCTL_IDCY_S 0
++#define AR5312_FLASHCTL_WST1 0x000003e0 /* Wait state 1 */
++#define AR5312_FLASHCTL_WST1_S 5
++#define AR5312_FLASHCTL_RBLE 0x00000400 /* Read byte lane enable */
++#define AR5312_FLASHCTL_WST2 0x0000f800 /* Wait state 2 */
++#define AR5312_FLASHCTL_WST2_S 11
++#define AR5312_FLASHCTL_AC 0x00070000 /* Flash addr check (added) */
++#define AR5312_FLASHCTL_AC_S 16
++#define AR5312_FLASHCTL_AC_128K 0x00000000
++#define AR5312_FLASHCTL_AC_256K 0x00010000
++#define AR5312_FLASHCTL_AC_512K 0x00020000
++#define AR5312_FLASHCTL_AC_1M 0x00030000
++#define AR5312_FLASHCTL_AC_2M 0x00040000
++#define AR5312_FLASHCTL_AC_4M 0x00050000
++#define AR5312_FLASHCTL_AC_8M 0x00060000
++#define AR5312_FLASHCTL_AC_RES 0x00070000 /* 16MB is not supported */
++#define AR5312_FLASHCTL_E 0x00080000 /* Flash bank enable (added) */
++#define AR5312_FLASHCTL_BUSERR 0x01000000 /* Bus transfer error flag */
++#define AR5312_FLASHCTL_WPERR 0x02000000 /* Write protect error flag */
++#define AR5312_FLASHCTL_WP 0x04000000 /* Write protect */
++#define AR5312_FLASHCTL_BM 0x08000000 /* Burst mode */
++#define AR5312_FLASHCTL_MW 0x30000000 /* Mem width */
++#define AR5312_FLASHCTL_MW8 0x00000000 /* Mem width x8 */
++#define AR5312_FLASHCTL_MW16 0x10000000 /* Mem width x16 */
++#define AR5312_FLASHCTL_MW32 0x20000000 /* Mem width x32 (not supp) */
++#define AR5312_FLASHCTL_ATNR 0x00000000 /* Access == no retry */
++#define AR5312_FLASHCTL_ATR 0x80000000 /* Access == retry every */
++#define AR5312_FLASHCTL_ATR4 0xc0000000 /* Access == retry every 4 */
++
++/*
++ * ARM SDRAM Controller -- just enough to determine memory size
++ */
++#define AR5312_MEM_CFG1 0x0004
++
++#define AR5312_MEM_CFG1_AC0_M 0x00000700 /* bank 0: SDRAM addr check */
++#define AR5312_MEM_CFG1_AC0_S 8
++#define AR5312_MEM_CFG1_AC1_M 0x00007000 /* bank 1: SDRAM addr check */
++#define AR5312_MEM_CFG1_AC1_S 12
++
++#endif /* __ASM_MACH_ATH25_AR5312_REGS_H */
+--- /dev/null
++++ b/arch/mips/ath25/ar5312.c
+@@ -0,0 +1,393 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
++ * Copyright (C) 2006 FON Technology, SL.
++ * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
++ * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
++ * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
++ */
++
++/*
++ * Platform devices for Atheros AR5312 SoCs
++ */
++
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/bitops.h>
++#include <linux/irqdomain.h>
++#include <linux/interrupt.h>
++#include <linux/platform_device.h>
++#include <linux/mtd/physmap.h>
++#include <linux/reboot.h>
++#include <asm/bootinfo.h>
++#include <asm/reboot.h>
++#include <asm/time.h>
++
++#include <ath25_platform.h>
++
++#include "devices.h"
++#include "ar5312.h"
++#include "ar5312_regs.h"
++
++static void __iomem *ar5312_rst_base;
++static struct irq_domain *ar5312_misc_irq_domain;
++
++static inline u32 ar5312_rst_reg_read(u32 reg)
++{
++ return __raw_readl(ar5312_rst_base + reg);
++}
++
++static inline void ar5312_rst_reg_write(u32 reg, u32 val)
++{
++ __raw_writel(val, ar5312_rst_base + reg);
++}
++
++static inline void ar5312_rst_reg_mask(u32 reg, u32 mask, u32 val)
++{
++ u32 ret = ar5312_rst_reg_read(reg);
++
++ ret &= ~mask;
++ ret |= val;
++ ar5312_rst_reg_write(reg, ret);
++}
++
++static irqreturn_t ar5312_ahb_err_handler(int cpl, void *dev_id)
++{
++ u32 proc1 = ar5312_rst_reg_read(AR5312_PROC1);
++ u32 proc_addr = ar5312_rst_reg_read(AR5312_PROCADDR); /* clears error */
++ u32 dma1 = ar5312_rst_reg_read(AR5312_DMA1);
++ u32 dma_addr = ar5312_rst_reg_read(AR5312_DMAADDR); /* clears error */
++
++ pr_emerg("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n",
++ proc_addr, proc1, dma_addr, dma1);
++
++ machine_restart("AHB error"); /* Catastrophic failure */
++ return IRQ_HANDLED;
++}
++
++static struct irqaction ar5312_ahb_err_interrupt = {
++ .handler = ar5312_ahb_err_handler,
++ .name = "ar5312-ahb-error",
++};
++
++static void ar5312_misc_irq_handler(unsigned irq, struct irq_desc *desc)
++{
++ u32 pending = ar5312_rst_reg_read(AR5312_ISR) &
++ ar5312_rst_reg_read(AR5312_IMR);
++ unsigned nr, misc_irq = 0;
++
++ if (pending) {
++ struct irq_domain *domain = irq_get_handler_data(irq);
++
++ nr = __ffs(pending);
++ misc_irq = irq_find_mapping(domain, nr);
++ }
++
++ if (misc_irq) {
++ generic_handle_irq(misc_irq);
++ if (nr == AR5312_MISC_IRQ_TIMER)
++ ar5312_rst_reg_read(AR5312_TIMER);
++ } else {
++ spurious_interrupt();
++ }
++}
++
++/* Enable the specified AR5312_MISC_IRQ interrupt */
++static void ar5312_misc_irq_unmask(struct irq_data *d)
++{
++ ar5312_rst_reg_mask(AR5312_IMR, 0, BIT(d->hwirq));
++}
++
++/* Disable the specified AR5312_MISC_IRQ interrupt */
++static void ar5312_misc_irq_mask(struct irq_data *d)
++{
++ ar5312_rst_reg_mask(AR5312_IMR, BIT(d->hwirq), 0);
++ ar5312_rst_reg_read(AR5312_IMR); /* flush write buffer */
++}
++
++static struct irq_chip ar5312_misc_irq_chip = {
++ .name = "ar5312-misc",
++ .irq_unmask = ar5312_misc_irq_unmask,
++ .irq_mask = ar5312_misc_irq_mask,
++};
++
++static int ar5312_misc_irq_map(struct irq_domain *d, unsigned irq,
++ irq_hw_number_t hw)
++{
++ irq_set_chip_and_handler(irq, &ar5312_misc_irq_chip, handle_level_irq);
++ return 0;
++}
++
++static struct irq_domain_ops ar5312_misc_irq_domain_ops = {
++ .map = ar5312_misc_irq_map,
++};
++
++static void ar5312_irq_dispatch(void)
++{
++ u32 pending = read_c0_status() & read_c0_cause();
++
++ if (pending & CAUSEF_IP2)
++ do_IRQ(AR5312_IRQ_WLAN0);
++ else if (pending & CAUSEF_IP5)
++ do_IRQ(AR5312_IRQ_WLAN1);
++ else if (pending & CAUSEF_IP6)
++ do_IRQ(AR5312_IRQ_MISC);
++ else if (pending & CAUSEF_IP7)
++ do_IRQ(ATH25_IRQ_CPU_CLOCK);
++ else
++ spurious_interrupt();
++}
++
++void __init ar5312_arch_init_irq(void)
++{
++ struct irq_domain *domain;
++ unsigned irq;
++
++ ath25_irq_dispatch = ar5312_irq_dispatch;
++
++ domain = irq_domain_add_linear(NULL, AR5312_MISC_IRQ_COUNT,
++ &ar5312_misc_irq_domain_ops, NULL);
++ if (!domain)
++ panic("Failed to add IRQ domain");
++
++ irq = irq_create_mapping(domain, AR5312_MISC_IRQ_AHB_PROC);
++ setup_irq(irq, &ar5312_ahb_err_interrupt);
++
++ irq_set_chained_handler(AR5312_IRQ_MISC, ar5312_misc_irq_handler);
++ irq_set_handler_data(AR5312_IRQ_MISC, domain);
++
++ ar5312_misc_irq_domain = domain;
++}
++
++static struct physmap_flash_data ar5312_flash_data = {
++ .width = 2,
++};
++
++static struct resource ar5312_flash_resource = {
++ .start = AR5312_FLASH_BASE,
++ .end = AR5312_FLASH_BASE + AR5312_FLASH_SIZE - 1,
++ .flags = IORESOURCE_MEM,
++};
++
++static struct platform_device ar5312_physmap_flash = {
++ .name = "physmap-flash",
++ .id = 0,
++ .dev.platform_data = &ar5312_flash_data,
++ .resource = &ar5312_flash_resource,
++ .num_resources = 1,
++};
++
++static void __init ar5312_flash_init(void)
++{
++ void __iomem *flashctl_base;
++ u32 ctl;
++
++ flashctl_base = ioremap_nocache(AR5312_FLASHCTL_BASE,
++ AR5312_FLASHCTL_SIZE);
++
++ ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL0);
++ ctl &= AR5312_FLASHCTL_MW;
++
++ /* fixup flash width */
++ switch (ctl) {
++ case AR5312_FLASHCTL_MW16:
++ ar5312_flash_data.width = 2;
++ break;
++ case AR5312_FLASHCTL_MW8:
++ default:
++ ar5312_flash_data.width = 1;
++ break;
++ }
++
++ /*
++ * Configure flash bank 0.
++ * Assume 8M window size. Flash will be aliased if it's smaller
++ */
++ ctl |= AR5312_FLASHCTL_E | AR5312_FLASHCTL_AC_8M | AR5312_FLASHCTL_RBLE;
++ ctl |= 0x01 << AR5312_FLASHCTL_IDCY_S;
++ ctl |= 0x07 << AR5312_FLASHCTL_WST1_S;
++ ctl |= 0x07 << AR5312_FLASHCTL_WST2_S;
++ __raw_writel(ctl, flashctl_base + AR5312_FLASHCTL0);
++
++ /* Disable other flash banks */
++ ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL1);
++ ctl &= ~(AR5312_FLASHCTL_E | AR5312_FLASHCTL_AC);
++ __raw_writel(ctl, flashctl_base + AR5312_FLASHCTL1);
++ ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL2);
++ ctl &= ~(AR5312_FLASHCTL_E | AR5312_FLASHCTL_AC);
++ __raw_writel(ctl, flashctl_base + AR5312_FLASHCTL2);
++
++ iounmap(flashctl_base);
++}
++
++void __init ar5312_init_devices(void)
++{
++ struct ath25_boarddata *config;
++
++ ar5312_flash_init();
++
++ /* Locate board/radio config data */
++ ath25_find_config(AR5312_FLASH_BASE, AR5312_FLASH_SIZE);
++ config = ath25_board.config;
++
++ /* AR2313 has CPU minor rev. 10 */
++ if ((current_cpu_data.processor_id & 0xff) == 0x0a)
++ ath25_soc = ATH25_SOC_AR2313;
++
++ /* AR2312 shares the same Silicon ID as AR5312 */
++ else if (config->flags & BD_ISCASPER)
++ ath25_soc = ATH25_SOC_AR2312;
++
++ /* Everything else is probably AR5312 or compatible */
++ else
++ ath25_soc = ATH25_SOC_AR5312;
++
++ platform_device_register(&ar5312_physmap_flash);
++
++ switch (ath25_soc) {
++ case ATH25_SOC_AR5312:
++ if (!ath25_board.radio)
++ return;
++
++ if (!(config->flags & BD_WLAN0))
++ break;
++
++ ath25_add_wmac(0, AR5312_WLAN0_BASE, AR5312_IRQ_WLAN0);
++ break;
++ case ATH25_SOC_AR2312:
++ case ATH25_SOC_AR2313:
++ if (!ath25_board.radio)
++ return;
++ break;
++ default:
++ break;
++ }
++
++ if (config->flags & BD_WLAN1)
++ ath25_add_wmac(1, AR5312_WLAN1_BASE, AR5312_IRQ_WLAN1);
++}
++
++static void ar5312_restart(char *command)
++{
++ /* reset the system */
++ local_irq_disable();
++ while (1)
++ ar5312_rst_reg_write(AR5312_RESET, AR5312_RESET_SYSTEM);
++}
++
++/*
++ * This table is indexed by bits 5..4 of the CLOCKCTL1 register
++ * to determine the predevisor value.
++ */
++static unsigned clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
++
++static unsigned __init ar5312_cpu_frequency(void)
++{
++ u32 scratch, devid, clock_ctl1;
++ u32 predivide_mask, multiplier_mask, doubler_mask;
++ unsigned predivide_shift, multiplier_shift;
++ unsigned predivide_select, predivisor, multiplier;
++
++ /* Trust the bootrom's idea of cpu frequency. */
++ scratch = ar5312_rst_reg_read(AR5312_SCRATCH);
++ if (scratch)
++ return scratch;
++
++ devid = ar5312_rst_reg_read(AR5312_REV);
++ devid = (devid & AR5312_REV_MAJ) >> AR5312_REV_MAJ_S;
++ if (devid == AR5312_REV_MAJ_AR2313) {
++ predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK;
++ predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT;
++ multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK;
++ multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT;
++ doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK;
++ } else { /* AR5312 and AR2312 */
++ predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK;
++ predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT;
++ multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK;
++ multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT;
++ doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK;
++ }
++
++ /*
++ * Clocking is derived from a fixed 40MHz input clock.
++ *
++ * cpu_freq = input_clock * MULT (where MULT is PLL multiplier)
++ * sys_freq = cpu_freq / 4 (used for APB clock, serial,
++ * flash, Timer, Watchdog Timer)
++ *
++ * cnt_freq = cpu_freq / 2 (use for CPU count/compare)
++ *
++ * So, for example, with a PLL multiplier of 5, we have
++ *
++ * cpu_freq = 200MHz
++ * sys_freq = 50MHz
++ * cnt_freq = 100MHz
++ *
++ * We compute the CPU frequency, based on PLL settings.
++ */
++
++ clock_ctl1 = ar5312_rst_reg_read(AR5312_CLOCKCTL1);
++ predivide_select = (clock_ctl1 & predivide_mask) >> predivide_shift;
++ predivisor = clockctl1_predivide_table[predivide_select];
++ multiplier = (clock_ctl1 & multiplier_mask) >> multiplier_shift;
++
++ if (clock_ctl1 & doubler_mask)
++ multiplier <<= 1;
++
++ return (40000000 / predivisor) * multiplier;
++}
++
++static inline unsigned ar5312_sys_frequency(void)
++{
++ return ar5312_cpu_frequency() / 4;
++}
++
++void __init ar5312_plat_time_init(void)
++{
++ mips_hpt_frequency = ar5312_cpu_frequency() / 2;
++}
++
++void __init ar5312_plat_mem_setup(void)
++{
++ void __iomem *sdram_base;
++ u32 memsize, memcfg, bank0_ac, bank1_ac;
++ u32 devid;
++
++ /* Detect memory size */
++ sdram_base = ioremap_nocache(AR5312_SDRAMCTL_BASE,
++ AR5312_SDRAMCTL_SIZE);
++ memcfg = __raw_readl(sdram_base + AR5312_MEM_CFG1);
++ bank0_ac = ATH25_REG_MS(memcfg, AR5312_MEM_CFG1_AC0);
++ bank1_ac = ATH25_REG_MS(memcfg, AR5312_MEM_CFG1_AC1);
++ memsize = (bank0_ac ? (1 << (bank0_ac + 1)) : 0) +
++ (bank1_ac ? (1 << (bank1_ac + 1)) : 0);
++ memsize <<= 20;
++ add_memory_region(0, memsize, BOOT_MEM_RAM);
++ iounmap(sdram_base);
++
++ ar5312_rst_base = ioremap_nocache(AR5312_RST_BASE, AR5312_RST_SIZE);
++
++ devid = ar5312_rst_reg_read(AR5312_REV);
++ devid >>= AR5312_REV_WMAC_MIN_S;
++ devid &= AR5312_REV_CHIP;
++ ath25_board.devid = (u16)devid;
++
++ /* Clear any lingering AHB errors */
++ ar5312_rst_reg_read(AR5312_PROCADDR);
++ ar5312_rst_reg_read(AR5312_DMAADDR);
++ ar5312_rst_reg_write(AR5312_WDT_CTRL, AR5312_WDT_CTRL_IGNORE);
++
++ _machine_restart = ar5312_restart;
++}
++
++void __init ar5312_arch_init(void)
++{
++ unsigned irq = irq_create_mapping(ar5312_misc_irq_domain,
++ AR5312_MISC_IRQ_UART0);
++
++ ath25_serial_setup(AR5312_UART0_BASE, irq, ar5312_sys_frequency());
++}
+--- /dev/null
++++ b/arch/mips/ath25/ar2315.c
+@@ -0,0 +1,308 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
++ * Copyright (C) 2006 FON Technology, SL.
++ * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
++ * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
++ * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
++ */
++
++/*
++ * Platform devices for Atheros AR2315 SoCs
++ */
++
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/bitops.h>
++#include <linux/irqdomain.h>
++#include <linux/interrupt.h>
++#include <linux/platform_device.h>
++#include <linux/reboot.h>
++#include <asm/bootinfo.h>
++#include <asm/reboot.h>
++#include <asm/time.h>
++
++#include <ath25_platform.h>
++
++#include "devices.h"
++#include "ar2315.h"
++#include "ar2315_regs.h"
++
++static void __iomem *ar2315_rst_base;
++static struct irq_domain *ar2315_misc_irq_domain;
++
++static inline u32 ar2315_rst_reg_read(u32 reg)
++{
++ return __raw_readl(ar2315_rst_base + reg);
++}
++
++static inline void ar2315_rst_reg_write(u32 reg, u32 val)
++{
++ __raw_writel(val, ar2315_rst_base + reg);
++}
++
++static inline void ar2315_rst_reg_mask(u32 reg, u32 mask, u32 val)
++{
++ u32 ret = ar2315_rst_reg_read(reg);
++
++ ret &= ~mask;
++ ret |= val;
++ ar2315_rst_reg_write(reg, ret);
++}
++
++static irqreturn_t ar2315_ahb_err_handler(int cpl, void *dev_id)
++{
++ ar2315_rst_reg_write(AR2315_AHB_ERR0, AR2315_AHB_ERROR_DET);
++ ar2315_rst_reg_read(AR2315_AHB_ERR1);
++
++ pr_emerg("AHB fatal error\n");
++ machine_restart("AHB error"); /* Catastrophic failure */
++
++ return IRQ_HANDLED;
++}
++
++static struct irqaction ar2315_ahb_err_interrupt = {
++ .handler = ar2315_ahb_err_handler,
++ .name = "ar2315-ahb-error",
++};
++
++static void ar2315_misc_irq_handler(unsigned irq, struct irq_desc *desc)
++{
++ u32 pending = ar2315_rst_reg_read(AR2315_ISR) &
++ ar2315_rst_reg_read(AR2315_IMR);
++ unsigned nr, misc_irq = 0;
++
++ if (pending) {
++ struct irq_domain *domain = irq_get_handler_data(irq);
++
++ nr = __ffs(pending);
++ misc_irq = irq_find_mapping(domain, nr);
++ }
++
++ if (misc_irq) {
++ if (nr == AR2315_MISC_IRQ_GPIO)
++ ar2315_rst_reg_write(AR2315_ISR, AR2315_ISR_GPIO);
++ else if (nr == AR2315_MISC_IRQ_WATCHDOG)
++ ar2315_rst_reg_write(AR2315_ISR, AR2315_ISR_WD);
++ generic_handle_irq(misc_irq);
++ } else {
++ spurious_interrupt();
++ }
++}
++
++static void ar2315_misc_irq_unmask(struct irq_data *d)
++{
++ ar2315_rst_reg_mask(AR2315_IMR, 0, BIT(d->hwirq));
++}
++
++static void ar2315_misc_irq_mask(struct irq_data *d)
++{
++ ar2315_rst_reg_mask(AR2315_IMR, BIT(d->hwirq), 0);
++}
++
++static struct irq_chip ar2315_misc_irq_chip = {
++ .name = "ar2315-misc",
++ .irq_unmask = ar2315_misc_irq_unmask,
++ .irq_mask = ar2315_misc_irq_mask,
++};
++
++static int ar2315_misc_irq_map(struct irq_domain *d, unsigned irq,
++ irq_hw_number_t hw)
++{
++ irq_set_chip_and_handler(irq, &ar2315_misc_irq_chip, handle_level_irq);
++ return 0;
++}
++
++static struct irq_domain_ops ar2315_misc_irq_domain_ops = {
++ .map = ar2315_misc_irq_map,
++};
++
++/*
++ * Called when an interrupt is received, this function
++ * determines exactly which interrupt it was, and it
++ * invokes the appropriate handler.
++ *
++ * Implicitly, we also define interrupt priority by
++ * choosing which to dispatch first.
++ */
++static void ar2315_irq_dispatch(void)
++{
++ u32 pending = read_c0_status() & read_c0_cause();
++
++ if (pending & CAUSEF_IP3)
++ do_IRQ(AR2315_IRQ_WLAN0);
++ else if (pending & CAUSEF_IP2)
++ do_IRQ(AR2315_IRQ_MISC);
++ else if (pending & CAUSEF_IP7)
++ do_IRQ(ATH25_IRQ_CPU_CLOCK);
++ else
++ spurious_interrupt();
++}
++
++void __init ar2315_arch_init_irq(void)
++{
++ struct irq_domain *domain;
++ unsigned irq;
++
++ ath25_irq_dispatch = ar2315_irq_dispatch;
++
++ domain = irq_domain_add_linear(NULL, AR2315_MISC_IRQ_COUNT,
++ &ar2315_misc_irq_domain_ops, NULL);
++ if (!domain)
++ panic("Failed to add IRQ domain");
++
++ irq = irq_create_mapping(domain, AR2315_MISC_IRQ_AHB);
++ setup_irq(irq, &ar2315_ahb_err_interrupt);
++
++ irq_set_chained_handler(AR2315_IRQ_MISC, ar2315_misc_irq_handler);
++ irq_set_handler_data(AR2315_IRQ_MISC, domain);
++
++ ar2315_misc_irq_domain = domain;
++}
++
++void __init ar2315_init_devices(void)
++{
++ /* Find board configuration */
++ ath25_find_config(AR2315_SPI_READ_BASE, AR2315_SPI_READ_SIZE);
++
++ ath25_add_wmac(0, AR2315_WLAN0_BASE, AR2315_IRQ_WLAN0);
++}
++
++static void ar2315_restart(char *command)
++{
++ void (*mips_reset_vec)(void) = (void *)0xbfc00000;
++
++ local_irq_disable();
++
++ /* try reset the system via reset control */
++ ar2315_rst_reg_write(AR2315_COLD_RESET, AR2317_RESET_SYSTEM);
++
++ /* Cold reset does not work on the AR2315/6, use the GPIO reset bits
++ * a workaround. Give it some time to attempt a gpio based hardware
++ * reset (atheros reference design workaround) */
++
++ /* TODO: implement the GPIO reset workaround */
++
++ /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic
++ * workaround. Attempt to jump to the mips reset location -
++ * the boot loader itself might be able to recover the system */
++ mips_reset_vec();
++}
++
++/*
++ * This table is indexed by bits 5..4 of the CLOCKCTL1 register
++ * to determine the predevisor value.
++ */
++static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
++static int pllc_divide_table[5] __initdata = { 2, 3, 4, 6, 3 };
++
++static unsigned __init ar2315_sys_clk(u32 clock_ctl)
++{
++ unsigned int pllc_ctrl, cpu_div;
++ unsigned int pllc_out, refdiv, fdiv, divby2;
++ unsigned int clk_div;
++
++ pllc_ctrl = ar2315_rst_reg_read(AR2315_PLLC_CTL);
++ refdiv = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_REF_DIV);
++ refdiv = clockctl1_predivide_table[refdiv];
++ fdiv = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_FDBACK_DIV);
++ divby2 = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_ADD_FDBACK_DIV) + 1;
++ pllc_out = (40000000 / refdiv) * (2 * divby2) * fdiv;
++
++ /* clkm input selected */
++ switch (clock_ctl & AR2315_CPUCLK_CLK_SEL_M) {
++ case 0:
++ case 1:
++ clk_div = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_CLKM_DIV);
++ clk_div = pllc_divide_table[clk_div];
++ break;
++ case 2:
++ clk_div = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_CLKC_DIV);
++ clk_div = pllc_divide_table[clk_div];
++ break;
++ default:
++ pllc_out = 40000000;
++ clk_div = 1;
++ break;
++ }
++
++ cpu_div = ATH25_REG_MS(clock_ctl, AR2315_CPUCLK_CLK_DIV);
++ cpu_div = cpu_div * 2 ?: 1;
++
++ return pllc_out / (clk_div * cpu_div);
++}
++
++static inline unsigned ar2315_cpu_frequency(void)
++{
++ return ar2315_sys_clk(ar2315_rst_reg_read(AR2315_CPUCLK));
++}
++
++static inline unsigned ar2315_apb_frequency(void)
++{
++ return ar2315_sys_clk(ar2315_rst_reg_read(AR2315_AMBACLK));
++}
++
++void __init ar2315_plat_time_init(void)
++{
++ mips_hpt_frequency = ar2315_cpu_frequency() / 2;
++}
++
++void __init ar2315_plat_mem_setup(void)
++{
++ void __iomem *sdram_base;
++ u32 memsize, memcfg;
++ u32 devid;
++ u32 config;
++
++ /* Detect memory size */
++ sdram_base = ioremap_nocache(AR2315_SDRAMCTL_BASE,
++ AR2315_SDRAMCTL_SIZE);
++ memcfg = __raw_readl(sdram_base + AR2315_MEM_CFG);
++ memsize = 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_DATA_WIDTH);
++ memsize <<= 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_COL_WIDTH);
++ memsize <<= 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_ROW_WIDTH);
++ memsize <<= 3;
++ add_memory_region(0, memsize, BOOT_MEM_RAM);
++ iounmap(sdram_base);
++
++ ar2315_rst_base = ioremap_nocache(AR2315_RST_BASE, AR2315_RST_SIZE);
++
++ /* Detect the hardware based on the device ID */
++ devid = ar2315_rst_reg_read(AR2315_SREV) & AR2315_REV_CHIP;
++ switch (devid) {
++ case 0x91: /* Need to check */
++ ath25_soc = ATH25_SOC_AR2318;
++ break;
++ case 0x90:
++ ath25_soc = ATH25_SOC_AR2317;
++ break;
++ case 0x87:
++ ath25_soc = ATH25_SOC_AR2316;
++ break;
++ case 0x86:
++ default:
++ ath25_soc = ATH25_SOC_AR2315;
++ break;
++ }
++ ath25_board.devid = devid;
++
++ /* Clear any lingering AHB errors */
++ config = read_c0_config();
++ write_c0_config(config & ~0x3);
++ ar2315_rst_reg_write(AR2315_AHB_ERR0, AR2315_AHB_ERROR_DET);
++ ar2315_rst_reg_read(AR2315_AHB_ERR1);
++ ar2315_rst_reg_write(AR2315_WDT_CTRL, AR2315_WDT_CTRL_IGNORE);
++
++ _machine_restart = ar2315_restart;
++}
++
++void __init ar2315_arch_init(void)
++{
++ unsigned irq = irq_create_mapping(ar2315_misc_irq_domain,
++ AR2315_MISC_IRQ_UART0);
++
++ ath25_serial_setup(AR2315_UART0_BASE, irq, ar2315_apb_frequency());
++}
+--- /dev/null
++++ b/arch/mips/ath25/ar2315.h
+@@ -0,0 +1,22 @@
++#ifndef __AR2315_H
++#define __AR2315_H
++
++#ifdef CONFIG_SOC_AR2315
++
++void ar2315_arch_init_irq(void);
++void ar2315_init_devices(void);
++void ar2315_plat_time_init(void);
++void ar2315_plat_mem_setup(void);
++void ar2315_arch_init(void);
++
++#else
++
++static inline void ar2315_arch_init_irq(void) {}
++static inline void ar2315_init_devices(void) {}
++static inline void ar2315_plat_time_init(void) {}
++static inline void ar2315_plat_mem_setup(void) {}
++static inline void ar2315_arch_init(void) {}
++
++#endif
++
++#endif /* __AR2315_H */
+--- /dev/null
++++ b/arch/mips/ath25/ar5312.h
+@@ -0,0 +1,22 @@
++#ifndef __AR5312_H
++#define __AR5312_H
++
++#ifdef CONFIG_SOC_AR5312
++
++void ar5312_arch_init_irq(void);
++void ar5312_init_devices(void);
++void ar5312_plat_time_init(void);
++void ar5312_plat_mem_setup(void);
++void ar5312_arch_init(void);
++
++#else
++
++static inline void ar5312_arch_init_irq(void) {}
++static inline void ar5312_init_devices(void) {}
++static inline void ar5312_plat_time_init(void) {}
++static inline void ar5312_plat_mem_setup(void) {}
++static inline void ar5312_arch_init(void) {}
++
++#endif
++
++#endif /* __AR5312_H */
+--- /dev/null
++++ b/arch/mips/ath25/devices.h
+@@ -0,0 +1,43 @@
++#ifndef __ATH25_DEVICES_H
++#define __ATH25_DEVICES_H
++
++#include <linux/cpu.h>
++
++#define ATH25_REG_MS(_val, _field) (((_val) & _field##_M) >> _field##_S)
++
++#define ATH25_IRQ_CPU_CLOCK (MIPS_CPU_IRQ_BASE + 7) /* C0_CAUSE: 0x8000 */
++
++enum ath25_soc_type {
++ /* handled by ar5312.c */
++ ATH25_SOC_AR2312,
++ ATH25_SOC_AR2313,
++ ATH25_SOC_AR5312,
++
++ /* handled by ar2315.c */
++ ATH25_SOC_AR2315,
++ ATH25_SOC_AR2316,
++ ATH25_SOC_AR2317,
++ ATH25_SOC_AR2318,
++
++ ATH25_SOC_UNKNOWN
++};
++
++extern enum ath25_soc_type ath25_soc;
++extern struct ar231x_board_config ath25_board;
++extern void (*ath25_irq_dispatch)(void);
++
++int ath25_find_config(phys_addr_t offset, unsigned long size);
++void ath25_serial_setup(u32 mapbase, int irq, unsigned int uartclk);
++int ath25_add_wmac(int nr, u32 base, int irq);
++
++static inline bool is_ar2315(void)
++{
++ return (current_cpu_data.cputype == CPU_4KEC);
++}
++
++static inline bool is_ar5312(void)
++{
++ return !is_ar2315();
++}
++
++#endif
+--- /dev/null
++++ b/arch/mips/ath25/devices.c
+@@ -0,0 +1,125 @@
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/serial_8250.h>
++#include <linux/platform_device.h>
++#include <asm/bootinfo.h>
++
++#include <ath25_platform.h>
++#include "devices.h"
++#include "ar5312.h"
++#include "ar2315.h"
++
++struct ar231x_board_config ath25_board;
++enum ath25_soc_type ath25_soc = ATH25_SOC_UNKNOWN;
++
++static struct resource ath25_wmac0_res[] = {
++ {
++ .name = "wmac0_membase",
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .name = "wmac0_irq",
++ .flags = IORESOURCE_IRQ,
++ }
++};
++
++static struct resource ath25_wmac1_res[] = {
++ {
++ .name = "wmac1_membase",
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .name = "wmac1_irq",
++ .flags = IORESOURCE_IRQ,
++ }
++};
++
++static struct platform_device ath25_wmac[] = {
++ {
++ .id = 0,
++ .name = "ar231x-wmac",
++ .resource = ath25_wmac0_res,
++ .num_resources = ARRAY_SIZE(ath25_wmac0_res),
++ .dev.platform_data = &ath25_board,
++ },
++ {
++ .id = 1,
++ .name = "ar231x-wmac",
++ .resource = ath25_wmac1_res,
++ .num_resources = ARRAY_SIZE(ath25_wmac1_res),
++ .dev.platform_data = &ath25_board,
++ },
++};
++
++static const char * const soc_type_strings[] = {
++ [ATH25_SOC_AR5312] = "Atheros AR5312",
++ [ATH25_SOC_AR2312] = "Atheros AR2312",
++ [ATH25_SOC_AR2313] = "Atheros AR2313",
++ [ATH25_SOC_AR2315] = "Atheros AR2315",
++ [ATH25_SOC_AR2316] = "Atheros AR2316",
++ [ATH25_SOC_AR2317] = "Atheros AR2317",
++ [ATH25_SOC_AR2318] = "Atheros AR2318",
++ [ATH25_SOC_UNKNOWN] = "Atheros (unknown)",
++};
++
++const char *get_system_type(void)
++{
++ if ((ath25_soc >= ARRAY_SIZE(soc_type_strings)) ||
++ !soc_type_strings[ath25_soc])
++ return soc_type_strings[ATH25_SOC_UNKNOWN];
++ return soc_type_strings[ath25_soc];
++}
++
++void __init ath25_serial_setup(u32 mapbase, int irq, unsigned int uartclk)
++{
++ struct uart_port s;
++
++ memset(&s, 0, sizeof(s));
++
++ s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP;
++ s.iotype = UPIO_MEM32;
++ s.irq = irq;
++ s.regshift = 2;
++ s.mapbase = mapbase;
++ s.uartclk = uartclk;
++
++ early_serial_setup(&s);
++}
++
++int __init ath25_add_wmac(int nr, u32 base, int irq)
++{
++ struct resource *res;
++
++ ath25_wmac[nr].dev.platform_data = &ath25_board;
++ res = &ath25_wmac[nr].resource[0];
++ res->start = base;
++ res->end = base + 0x10000 - 1;
++ res++;
++ res->start = irq;
++ res->end = irq;
++ return platform_device_register(&ath25_wmac[nr]);
++}
++
++static int __init ath25_register_devices(void)
++{
++ if (is_ar5312())
++ ar5312_init_devices();
++ else
++ ar2315_init_devices();
++
++ return 0;
++}
++
++device_initcall(ath25_register_devices);
++
++static int __init ath25_arch_init(void)
++{
++ if (is_ar5312())
++ ar5312_arch_init();
++ else
++ ar2315_arch_init();
++
++ return 0;
++}
++
++arch_initcall(ath25_arch_init);
projects / openwrt.git / blobdiff