ar71xx: remove useless irq_desc.status initializations

[openwrt.git] / target / linux / ar71xx / files / arch / mips / ar71xx / gpio.c

diff --git a/target/linux/ar71xx/files/arch/mips/ar71xx/gpio.c b/target/linux/ar71xx/files/arch/mips/ar71xx/gpio.c
index 03bf38b..10d8081 100644 (file)
--- a/target/linux/ar71xx/files/arch/mips/ar71xx/gpio.c
+++ b/target/linux/ar71xx/files/arch/mips/ar71xx/gpio.c
@@ -1,7 +1,7 @@
 /*
- *  Atheros AR71xx SoC GPIO API support
+ *  Atheros AR7XXX/AR9XXX SoC GPIO API support
  *
- *  Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  *
  *  This program is free software; you can redistribute it and/or modify it
@@ -22,24 +22,23 @@
 
 static DEFINE_SPINLOCK(ar71xx_gpio_lock);
 
+unsigned long ar71xx_gpio_count;
+EXPORT_SYMBOL(ar71xx_gpio_count);
+
 void __ar71xx_gpio_set_value(unsigned gpio, int value)
 {
-       unsigned long flags;
-
-       spin_lock_irqsave(&ar71xx_gpio_lock, flags);
+       void __iomem *base = ar71xx_gpio_base;
 
        if (value)
-               ar71xx_gpio_wr(GPIO_REG_SET, (1 << gpio));
+               __raw_writel(1 << gpio, base + GPIO_REG_SET);
        else
-               ar71xx_gpio_wr(GPIO_REG_CLEAR, (1 << gpio));
-
-       spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
+               __raw_writel(1 << gpio, base + GPIO_REG_CLEAR);
 }
 EXPORT_SYMBOL(__ar71xx_gpio_set_value);
 
 int __ar71xx_gpio_get_value(unsigned gpio)
 {
-       return (ar71xx_gpio_rr(GPIO_REG_IN) & (1 << gpio)) ? 1 : 0;
+       return (__raw_readl(ar71xx_gpio_base + GPIO_REG_IN) >> gpio) & 1;
 }
 EXPORT_SYMBOL(__ar71xx_gpio_get_value);
 
@@ -57,12 +56,13 @@ static void ar71xx_gpio_set_value(struct gpio_chip *chip,
 static int ar71xx_gpio_direction_input(struct gpio_chip *chip,
                                       unsigned offset)
 {
+       void __iomem *base = ar71xx_gpio_base;
        unsigned long flags;
 
        spin_lock_irqsave(&ar71xx_gpio_lock, flags);
 
-       ar71xx_gpio_wr(GPIO_REG_OE,
-                       ar71xx_gpio_rr(GPIO_REG_OE) & ~(1 << offset));
+       __raw_writel(__raw_readl(base + GPIO_REG_OE) & ~(1 << offset),
+                    base + GPIO_REG_OE);
 
        spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
 
@@ -72,17 +72,18 @@ static int ar71xx_gpio_direction_input(struct gpio_chip *chip,
 static int ar71xx_gpio_direction_output(struct gpio_chip *chip,
                                        unsigned offset, int value)
 {
+       void __iomem *base = ar71xx_gpio_base;
        unsigned long flags;
 
        spin_lock_irqsave(&ar71xx_gpio_lock, flags);
 
        if (value)
-               ar71xx_gpio_wr(GPIO_REG_SET, (1 << offset));
+               __raw_writel(1 << offset, base + GPIO_REG_SET);
        else
-               ar71xx_gpio_wr(GPIO_REG_CLEAR, (1 << offset));
+               __raw_writel(1 << offset, base + GPIO_REG_CLEAR);
 
-       ar71xx_gpio_wr(GPIO_REG_OE,
-                       ar71xx_gpio_rr(GPIO_REG_OE) | (1 << offset));
+       __raw_writel(__raw_readl(base + GPIO_REG_OE) | (1 << offset),
+                    base + GPIO_REG_OE);
 
        spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
 
@@ -101,25 +102,49 @@ static struct gpio_chip ar71xx_gpio_chip = {
 
 void ar71xx_gpio_function_enable(u32 mask)
 {
+       void __iomem *base = ar71xx_gpio_base;
        unsigned long flags;
 
        spin_lock_irqsave(&ar71xx_gpio_lock, flags);
 
-       ar71xx_gpio_wr(GPIO_REG_FUNC, ar71xx_gpio_rr(GPIO_REG_FUNC) | mask);
+       __raw_writel(__raw_readl(base + GPIO_REG_FUNC) | mask,
+                    base + GPIO_REG_FUNC);
+       /* flush write */
+       (void) __raw_readl(base + GPIO_REG_FUNC);
 
        spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
 }
 
 void ar71xx_gpio_function_disable(u32 mask)
 {
+       void __iomem *base = ar71xx_gpio_base;
+       unsigned long flags;
+
+       spin_lock_irqsave(&ar71xx_gpio_lock, flags);
+
+       __raw_writel(__raw_readl(base + GPIO_REG_FUNC) & ~mask,
+                    base + GPIO_REG_FUNC);
+       /* flush write */
+       (void) __raw_readl(base + GPIO_REG_FUNC);
+
+       spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
+}
+
+void ar71xx_gpio_function_setup(u32 set, u32 clear)
+{
+       void __iomem *base = ar71xx_gpio_base;
        unsigned long flags;
 
        spin_lock_irqsave(&ar71xx_gpio_lock, flags);
 
-       ar71xx_gpio_wr(GPIO_REG_FUNC, ar71xx_gpio_rr(GPIO_REG_FUNC) & ~mask);
+       __raw_writel((__raw_readl(base + GPIO_REG_FUNC) & ~clear) | set,
+                    base + GPIO_REG_FUNC);
+       /* flush write */
+       (void) __raw_readl(base + GPIO_REG_FUNC);
 
        spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
 }
+EXPORT_SYMBOL(ar71xx_gpio_function_setup);
 
 void __init ar71xx_gpio_init(void)
 {
@@ -129,6 +154,39 @@ void __init ar71xx_gpio_init(void)
                                "AR71xx GPIO controller"))
                panic("cannot allocate AR71xx GPIO registers page");
 
+       switch (ar71xx_soc) {
+       case AR71XX_SOC_AR7130:
+       case AR71XX_SOC_AR7141:
+       case AR71XX_SOC_AR7161:
+               ar71xx_gpio_chip.ngpio = AR71XX_GPIO_COUNT;
+               break;
+
+       case AR71XX_SOC_AR7240:
+       case AR71XX_SOC_AR7241:
+       case AR71XX_SOC_AR7242:
+               ar71xx_gpio_chip.ngpio = AR724X_GPIO_COUNT;
+               break;
+
+       case AR71XX_SOC_AR9130:
+       case AR71XX_SOC_AR9132:
+               ar71xx_gpio_chip.ngpio = AR91XX_GPIO_COUNT;
+               break;
+
+       case AR71XX_SOC_AR9330:
+       case AR71XX_SOC_AR9331:
+               ar71xx_gpio_chip.ngpio = AR933X_GPIO_COUNT;
+               break;
+
+       case AR71XX_SOC_AR9341:
+       case AR71XX_SOC_AR9342:
+       case AR71XX_SOC_AR9344:
+               ar71xx_gpio_chip.ngpio = AR934X_GPIO_COUNT;
+               break;
+
+       default:
+               BUG();
+       }
+
        err = gpiochip_add(&ar71xx_gpio_chip);
        if (err)
                panic("cannot add AR71xx GPIO chip, error=%d", err);