[adm5120] add support for GPIO IRQs

[openwrt.git] / target / linux / adm5120 / files / include / asm-mips / mach-adm5120 / adm5120_switch.h

diff --git a/target/linux/adm5120/files/include/asm-mips/mach-adm5120/adm5120_switch.h b/target/linux/adm5120/files/include/asm-mips/mach-adm5120/adm5120_switch.h
index f3c05f6..f96c7d5 100644 (file)
--- a/target/linux/adm5120/files/include/asm-mips/mach-adm5120/adm5120_switch.h
+++ b/target/linux/adm5120/files/include/asm-mips/mach-adm5120/adm5120_switch.h
@@ -141,6 +141,9 @@
 #define CPUP_CONF_DCPUP                BIT(0)  /* Disable CPU port */
 #define CPUP_CONF_CRCP         BIT(1)  /* CRC padding from CPU */
 #define CPUP_CONF_BTM          BIT(2)  /* Bridge Testing Mode */
+#define CPUP_CONF_DUNP_SHIFT   9       /* Disable Unknown Packets for portX */
+#define CPUP_CONF_DMCP_SHIFT   16      /* Disable Mcast Packets form portX */
+#define CPUP_CONF_DBCP_SHIFT   24      /* Disable Bcast Packets form portX */
 
 /* PORT_CONF0 register bits */
 #define PORT_CONF0_DP_SHIFT    0       /* Disable Port */
@@ -156,6 +159,26 @@
 #define SEND_TRIG_STL          BIT(0)  /* Send Trigger Low */
 #define SEND_TRIG_STH          BIT(1)  /* Send Trigger High */
 
+/* MAC_WT0 register bits */
+#define MAC_WT0_MAWC           BIT(0)  /* MAC address write command */
+#define MAC_WT0_MWD_SHIFT      1
+#define MAC_WT0_MWD            BIT(1)  /* MAC write done */
+#define MAC_WT0_WFB            BIT(2)  /* Write Filter Bit */
+#define MAC_WT0_WVN_SHIFT      3       /* Write Vlan Number shift */
+#define MAC_WT0_WVE            BIT(6)  /* Write VLAN enable */
+#define MAC_WT0_WPMN_SHIFT     7
+#define MAC_WT0_WAF_SHIFT      13      /* Write Age Field shift */
+#define MAC_WT0_WAF_EMPTY      0
+#define MAC_WT0_WAF_STATIC     7       /* age: static */
+#define MAC_WT0_MAC0_SHIFT     16
+#define MAC_WT0_MAC1_SHIFT     24
+
+/* MAC_WT1 register bits */
+#define MAC_WT1_MAC2_SHIFT     0
+#define MAC_WT1_MAC3_SHIFT     8
+#define MAC_WT1_MAC4_SHIFT     16
+#define MAC_WT1_MAC5_SHIFT     24
+
 /* BW_CNTL0/BW_CNTL1 register bits */
 #define BW_CNTL_DISABLE                0x00
 #define BW_CNTL_64K            0x01
@@ -171,6 +194,8 @@
 #define P5TBC_SHIFT            8
 #define P5RBC_SHIFT            12
 
+#define BW_CNTL1_NAND_ENABLE   0x100
+
 /* PHY_CNTL0 register bits */
 #define PHY_CNTL0_PHYA_MASK    BITMASK(5)
 #define PHY_CNTL0_PHYR_MASK    BITMASK(5)
@@ -196,6 +221,9 @@
 /* PHY_CNTL2_RMAE is bad in datasheet */
 #define PHY_CNTL2_RMAE         BIT(31) /* Recommended MCC Average enable */
 
+/* PHY_CNTL3 register bits */
+#define PHY_CNTL3_RNT          BIT(10) /* Recommend Normal Threshold */
+
 /* PORT_TH register bits */
 #define PORT_TH_PPT_MASK       BITMASK(8)      /* Per Port Threshold */
 #define PORT_TH_CPUT_SHIFT     8               /* CPU Port Buffer Threshold */
@@ -219,6 +247,11 @@
 #define GPIO_CONF0_OE_MASK     (0xFF << GPIO_CONF0_OE_SHIFT)
 #define GPIO_CONF0_OV_MASK     (0xFF << GPIO_CONF0_OV_SHIFT)
 
+/* GPIO_CONF2 register bits */
+#define GPIO_CONF2_CSX0                BIT(4)  /* enable CSX0:INTX0 on GPIO 1:2 */
+#define GPIO_CONF2_CSX1                BIT(5)  /* enable CSX1:INTX1 on GPIO 3:4 */
+#define GPIO_CONF2_EW          BIT(6)  /* enable wait state pin for CSX0/1 */
+
 /* INT_STATUS/INT_MASK register bits */
 #define SWITCH_INT_SHD         BIT(0)  /* Send High Done */
 #define SWITCH_INT_SLD         BIT(1)  /* Send Low Done */