package: uboot-sunxi: various changes

[openwrt.git] / package / boot / uboot-sunxi / patches / 015-fix-2nd-usb-ctrler-on-sun47i.patch

diff --git a/package/boot/uboot-sunxi/patches/015-fix-2nd-usb-ctrler-on-sun47i.patch b/package/boot/uboot-sunxi/patches/015-fix-2nd-usb-ctrler-on-sun47i.patch
new file mode 100644 (file)
index 0000000..2d49194
--- /dev/null
+++ b/package/boot/uboot-sunxi/patches/015-fix-2nd-usb-ctrler-on-sun47i.patch
@@ -0,0 +1,82 @@
+From 948603d4d637a0e04a3214253b911cfc4ed11220 Mon Sep 17 00:00:00 2001
+From: Hans de Goede <hdegoede@redhat.com>
+Date: Mon, 21 Mar 2016 14:44:35 +0100
+Subject: [PATCH] sunxi: Fix 2nd usb controller on sun4i/sun7i no longer
+ working
+
+The 2nd usb controller on sun4i/sun7i has its base address 0x8000
+bytes from the 1st one, rather then 0x1000. Also the ahb clk gates
+are interleaved with the ohci clk-gates introducing a hole between
+the clks for usb1 and usb2.
+
+Signed-off-by: Hans de Goede <hdegoede@redhat.com>
+Acked-by: Ian Campbell <ijc@hellion.org.uk>
+---
+ drivers/usb/host/ehci-sunxi.c | 13 +++++++++++--
+ drivers/usb/host/ohci-sunxi.c | 15 ++++++++++++---
+ 2 files changed, 23 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/usb/host/ehci-sunxi.c b/drivers/usb/host/ehci-sunxi.c
+index cf3dcc4..677a5d3 100644
+--- a/drivers/usb/host/ehci-sunxi.c
++++ b/drivers/usb/host/ehci-sunxi.c
+@@ -17,6 +17,14 @@
+ #include <dm.h>
+ #include "ehci.h"
+ 
++#ifdef CONFIG_SUNXI_GEN_SUN4I
++#define BASE_DIST             0x8000
++#define AHB_CLK_DIST          2
++#else
++#define BASE_DIST             0x1000
++#define AHB_CLK_DIST          1
++#endif
++
+ struct ehci_sunxi_priv {
+       struct ehci_ctrl ehci;
+       int ahb_gate_mask; /* Mask of ahb_gate0 clk gate bits for this hcd */
+@@ -39,8 +47,9 @@ static int ehci_usb_probe(struct udevice *dev)
+ #ifdef CONFIG_MACH_SUN8I_H3
+       priv->ahb_gate_mask |= 1 << AHB_GATE_OFFSET_USB_OHCI0;
+ #endif
+-      priv->phy_index = ((u32)hccr - SUNXI_USB1_BASE) / 0x1000 + 1;
+-      priv->ahb_gate_mask <<= priv->phy_index - 1;
++      priv->phy_index = ((u32)hccr - SUNXI_USB1_BASE) / BASE_DIST;
++      priv->ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST;
++      priv->phy_index++; /* Non otg phys start at 1 */
+ 
+       setbits_le32(&ccm->ahb_gate0, priv->ahb_gate_mask);
+ #ifdef CONFIG_SUNXI_GEN_SUN6I
+diff --git a/drivers/usb/host/ohci-sunxi.c b/drivers/usb/host/ohci-sunxi.c
+index 1b1f651..d4fb95a 100644
+--- a/drivers/usb/host/ohci-sunxi.c
++++ b/drivers/usb/host/ohci-sunxi.c
+@@ -17,6 +17,14 @@
+ #include <usb.h>
+ #include "ohci.h"
+ 
++#ifdef CONFIG_SUNXI_GEN_SUN4I
++#define BASE_DIST             0x8000
++#define AHB_CLK_DIST          2
++#else
++#define BASE_DIST             0x1000
++#define AHB_CLK_DIST          1
++#endif
++
+ struct ohci_sunxi_priv {
+       ohci_t ohci;
+       int ahb_gate_mask; /* Mask of ahb_gate0 clk gate bits for this hcd */
+@@ -42,9 +50,10 @@ static int ohci_usb_probe(struct udevice *dev)
+       priv->ahb_gate_mask |= 1 << AHB_GATE_OFFSET_USB_EHCI0;
+ #endif
+       priv->usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK;
+-      priv->phy_index = ((u32)regs - (SUNXI_USB1_BASE + 0x400)) / 0x1000 + 1;
+-      priv->ahb_gate_mask <<= priv->phy_index - 1;
+-      priv->usb_gate_mask <<= priv->phy_index - 1;
++      priv->phy_index = ((u32)regs - (SUNXI_USB1_BASE + 0x400)) / BASE_DIST;
++      priv->ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST;
++      priv->usb_gate_mask <<= priv->phy_index;
++      priv->phy_index++; /* Non otg phys start at 1 */
+ 
+       setbits_le32(&ccm->ahb_gate0, priv->ahb_gate_mask);
+       setbits_le32(&ccm->usb_clk_cfg, priv->usb_gate_mask);