- u32 t, m;
-
- m = QCA955X_ETH_CFG_RGMII_EN |
- QCA955X_ETH_CFG_MII_GE0 |
- QCA955X_ETH_CFG_GMII_GE0 |
- QCA955X_ETH_CFG_MII_GE0_MASTER |
- QCA955X_ETH_CFG_MII_GE0_SLAVE |
- QCA955X_ETH_CFG_GE0_ERR_EN |
- QCA955X_ETH_CFG_GE0_SGMII |
- QCA955X_ETH_CFG_RMII_GE0 |
- QCA955X_ETH_CFG_MII_CNTL_SPEED |
- QCA955X_ETH_CFG_RMII_GE0_MASTER;
- m |= QCA955X_ETH_CFG_RXD_DELAY_MASK << QCA955X_ETH_CFG_RXD_DELAY_SHIFT;
- m |= QCA955X_ETH_CFG_RDV_DELAY_MASK << QCA955X_ETH_CFG_RDV_DELAY_SHIFT;
- m |= QCA955X_ETH_CFG_TXD_DELAY_MASK << QCA955X_ETH_CFG_TXD_DELAY_SHIFT;
- m |= QCA955X_ETH_CFG_TXE_DELAY_MASK << QCA955X_ETH_CFG_TXE_DELAY_SHIFT;