+ }
+ }
+--- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
++++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
+@@ -131,8 +131,9 @@ static const struct ar9300_eeprom ar9300
+ .thresh62 = 28,
+ .papdRateMaskHt20 = LE32(0x0cf0e0e0),
+ .papdRateMaskHt40 = LE32(0x6cf0e0e0),
++ .xlna_bias_strength = 0,
+ .futureModal = {
+- 0, 0, 0, 0, 0, 0, 0, 0,
++ 0, 0, 0, 0, 0, 0, 0,
+ },
+ },
+ .base_ext1 = {
+@@ -331,8 +332,9 @@ static const struct ar9300_eeprom ar9300
+ .thresh62 = 28,
+ .papdRateMaskHt20 = LE32(0x0c80c080),
+ .papdRateMaskHt40 = LE32(0x0080c080),
++ .xlna_bias_strength = 0,
+ .futureModal = {
+- 0, 0, 0, 0, 0, 0, 0, 0,
++ 0, 0, 0, 0, 0, 0, 0,
+ },
+ },
+ .base_ext2 = {
+@@ -704,8 +706,9 @@ static const struct ar9300_eeprom ar9300
+ .thresh62 = 28,
+ .papdRateMaskHt20 = LE32(0x0c80c080),
+ .papdRateMaskHt40 = LE32(0x0080c080),
++ .xlna_bias_strength = 0,
+ .futureModal = {
+- 0, 0, 0, 0, 0, 0, 0, 0,
++ 0, 0, 0, 0, 0, 0, 0,
+ },
+ },
+ .base_ext1 = {
+@@ -904,8 +907,9 @@ static const struct ar9300_eeprom ar9300
+ .thresh62 = 28,
+ .papdRateMaskHt20 = LE32(0x0cf0e0e0),
+ .papdRateMaskHt40 = LE32(0x6cf0e0e0),
++ .xlna_bias_strength = 0,
+ .futureModal = {
+- 0, 0, 0, 0, 0, 0, 0, 0,
++ 0, 0, 0, 0, 0, 0, 0,
+ },
+ },
+ .base_ext2 = {
+@@ -1278,8 +1282,9 @@ static const struct ar9300_eeprom ar9300
+ .thresh62 = 28,
+ .papdRateMaskHt20 = LE32(0x0c80c080),
+ .papdRateMaskHt40 = LE32(0x0080c080),
++ .xlna_bias_strength = 0,
+ .futureModal = {
+- 0, 0, 0, 0, 0, 0, 0, 0,
++ 0, 0, 0, 0, 0, 0, 0,
+ },
+ },
+ .base_ext1 = {
+@@ -1478,8 +1483,9 @@ static const struct ar9300_eeprom ar9300
+ .thresh62 = 28,
+ .papdRateMaskHt20 = LE32(0x0cf0e0e0),
+ .papdRateMaskHt40 = LE32(0x6cf0e0e0),
++ .xlna_bias_strength = 0,
+ .futureModal = {
+- 0, 0, 0, 0, 0, 0, 0, 0,
++ 0, 0, 0, 0, 0, 0, 0,
+ },
+ },
+ .base_ext2 = {
+@@ -1852,8 +1858,9 @@ static const struct ar9300_eeprom ar9300
+ .thresh62 = 28,
+ .papdRateMaskHt20 = LE32(0x0c80c080),
+ .papdRateMaskHt40 = LE32(0x0080c080),
++ .xlna_bias_strength = 0,
+ .futureModal = {
+- 0, 0, 0, 0, 0, 0, 0, 0,
++ 0, 0, 0, 0, 0, 0, 0,
+ },
+ },
+ .base_ext1 = {
+@@ -2052,8 +2059,9 @@ static const struct ar9300_eeprom ar9300
+ .thresh62 = 28,
+ .papdRateMaskHt20 = LE32(0x0cf0e0e0),
+ .papdRateMaskHt40 = LE32(0x6cf0e0e0),
++ .xlna_bias_strength = 0,
+ .futureModal = {
+- 0, 0, 0, 0, 0, 0, 0, 0,
++ 0, 0, 0, 0, 0, 0, 0,
+ },
+ },
+ .base_ext2 = {
+@@ -2425,8 +2433,9 @@ static const struct ar9300_eeprom ar9300
+ .thresh62 = 28,
+ .papdRateMaskHt20 = LE32(0x0c80C080),
+ .papdRateMaskHt40 = LE32(0x0080C080),
++ .xlna_bias_strength = 0,
+ .futureModal = {
+- 0, 0, 0, 0, 0, 0, 0, 0,
++ 0, 0, 0, 0, 0, 0, 0,
+ },
+ },
+ .base_ext1 = {
+@@ -2625,8 +2634,9 @@ static const struct ar9300_eeprom ar9300
+ .thresh62 = 28,
+ .papdRateMaskHt20 = LE32(0x0cf0e0e0),
+ .papdRateMaskHt40 = LE32(0x6cf0e0e0),
++ .xlna_bias_strength = 0,
+ .futureModal = {
+- 0, 0, 0, 0, 0, 0, 0, 0,
++ 0, 0, 0, 0, 0, 0, 0,
+ },
+ },
+ .base_ext2 = {
+@@ -2971,14 +2981,6 @@ static u32 ath9k_hw_ar9300_get_eeprom(st
+ return (pBase->txrxMask >> 4) & 0xf;
+ case EEP_RX_MASK:
+ return pBase->txrxMask & 0xf;
+- case EEP_DRIVE_STRENGTH:
+-#define AR9300_EEP_BASE_DRIV_STRENGTH 0x1
+- return pBase->miscConfiguration & AR9300_EEP_BASE_DRIV_STRENGTH;
+- case EEP_INTERNAL_REGULATOR:
+- /* Bit 4 is internal regulator flag */
+- return (pBase->featureEnable & 0x10) >> 4;
+- case EEP_SWREG:
+- return le32_to_cpu(pBase->swreg);
+ case EEP_PAPRD:
+ return !!(pBase->featureEnable & BIT(5));
+ case EEP_CHAIN_MASK_REDUCE:
+@@ -2989,8 +2991,6 @@ static u32 ath9k_hw_ar9300_get_eeprom(st
+ return eep->modalHeader5G.antennaGain;
+ case EEP_ANTENNA_GAIN_2G:
+ return eep->modalHeader2G.antennaGain;
+- case EEP_QUICK_DROP:
+- return pBase->miscConfiguration & BIT(1);
+ default:
+ return 0;
+ }
+@@ -3260,10 +3260,20 @@ static int ar9300_eeprom_restore_interna
+ int it;
+ u16 checksum, mchecksum;
+ struct ath_common *common = ath9k_hw_common(ah);
++ struct ar9300_eeprom *eep;
+ eeprom_read_op read;
+
+- if (ath9k_hw_use_flash(ah))
+- return ar9300_eeprom_restore_flash(ah, mptr, mdata_size);
++ if (ath9k_hw_use_flash(ah)) {
++ u8 txrx;
++
++ ar9300_eeprom_restore_flash(ah, mptr, mdata_size);
++
++ /* check if eeprom contains valid data */
++ eep = (struct ar9300_eeprom *) mptr;
++ txrx = eep->baseEepHeader.txrxMask;
++ if (txrx != 0 && txrx != 0xff)
++ return 0;
++ }
+
+ word = kzalloc(2048, GFP_KERNEL);
+ if (!word)
+@@ -3493,19 +3503,20 @@ static int ath9k_hw_ar9300_get_eeprom_re
+ return 0;
+ }
+
+-static s32 ar9003_hw_xpa_bias_level_get(struct ath_hw *ah, bool is2ghz)
++static struct ar9300_modal_eep_header *ar9003_modal_header(struct ath_hw *ah,
++ bool is2ghz)
+ {
+ struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
+
+ if (is2ghz)
+- return eep->modalHeader2G.xpaBiasLvl;
++ return &eep->modalHeader2G;
+ else
+- return eep->modalHeader5G.xpaBiasLvl;
++ return &eep->modalHeader5G;
+ }
+
+ static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz)
+ {
+- int bias = ar9003_hw_xpa_bias_level_get(ah, is2ghz);
++ int bias = ar9003_modal_header(ah, is2ghz)->xpaBiasLvl;
+
+ if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
+ REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias);
+@@ -3521,57 +3532,26 @@ static void ar9003_hw_xpa_bias_level_app
+ }
+ }
+
+-static u16 ar9003_switch_com_spdt_get(struct ath_hw *ah, bool is_2ghz)
++static u16 ar9003_switch_com_spdt_get(struct ath_hw *ah, bool is2ghz)
+ {
+- struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
+- __le16 val;
+-
+- if (is_2ghz)
+- val = eep->modalHeader2G.switchcomspdt;
+- else
+- val = eep->modalHeader5G.switchcomspdt;
+- return le16_to_cpu(val);
++ return le16_to_cpu(ar9003_modal_header(ah, is2ghz)->switchcomspdt);
+ }
+
+
+ static u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz)
+ {
+- struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
+- __le32 val;
+-
+- if (is2ghz)
+- val = eep->modalHeader2G.antCtrlCommon;
+- else
+- val = eep->modalHeader5G.antCtrlCommon;
+- return le32_to_cpu(val);
++ return le32_to_cpu(ar9003_modal_header(ah, is2ghz)->antCtrlCommon);
+ }
+
+ static u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, bool is2ghz)
+ {
+- struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
+- __le32 val;
+-
+- if (is2ghz)
+- val = eep->modalHeader2G.antCtrlCommon2;
+- else
+- val = eep->modalHeader5G.antCtrlCommon2;
+- return le32_to_cpu(val);
++ return le32_to_cpu(ar9003_modal_header(ah, is2ghz)->antCtrlCommon2);
+ }
+
+-static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah,
+- int chain,
++static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah, int chain,
+ bool is2ghz)
+ {
+- struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
+- __le16 val = 0;
+-
+- if (chain >= 0 && chain < AR9300_MAX_CHAINS) {
+- if (is2ghz)
+- val = eep->modalHeader2G.antCtrlChain[chain];
+- else
+- val = eep->modalHeader5G.antCtrlChain[chain];
+- }
+-
++ __le16 val = ar9003_modal_header(ah, is2ghz)->antCtrlChain[chain];
+ return le16_to_cpu(val);
+ }
+
+@@ -3681,11 +3661,12 @@ static void ar9003_hw_ant_ctrl_apply(str
+
+ static void ar9003_hw_drive_strength_apply(struct ath_hw *ah)
+ {
++ struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
++ struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
+ int drive_strength;
+ unsigned long reg;
+
+- drive_strength = ath9k_hw_ar9300_get_eeprom(ah, EEP_DRIVE_STRENGTH);
+-
++ drive_strength = pBase->miscConfiguration & BIT(0);
+ if (!drive_strength)
+ return;
+
+@@ -3815,11 +3796,11 @@ static bool is_pmu_set(struct ath_hw *ah
+
+ void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
+ {
+- int internal_regulator =
+- ath9k_hw_ar9300_get_eeprom(ah, EEP_INTERNAL_REGULATOR);
++ struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
++ struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
+ u32 reg_val;
+
+- if (internal_regulator) {
++ if (pBase->featureEnable & BIT(4)) {
+ if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
+ int reg_pmu_set;
+
+@@ -3863,11 +3844,11 @@ void ar9003_hw_internal_regulator_apply(
+ if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
+ return;
+ } else if (AR_SREV_9462(ah)) {
+- reg_val = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG);
++ reg_val = le32_to_cpu(pBase->swreg);
+ REG_WRITE(ah, AR_PHY_PMU1, reg_val);
+ } else {
+ /* Internal regulator is ON. Write swreg register. */
+- reg_val = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG);
++ reg_val = le32_to_cpu(pBase->swreg);
+ REG_WRITE(ah, AR_RTC_REG_CONTROL1,
+ REG_READ(ah, AR_RTC_REG_CONTROL1) &
+ (~AR_RTC_REG_CONTROL1_SWREG_PROGRAM));
+@@ -3909,6 +3890,9 @@ static void ar9003_hw_apply_tuning_caps(
+ struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
+ u8 tuning_caps_param = eep->baseEepHeader.params_for_tuning_caps[0];
+
++ if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
++ return;
++
+ if (eep->baseEepHeader.featureEnable & 0x40) {
+ tuning_caps_param &= 0x7f;
+ REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPINDAC,
+@@ -3921,10 +3905,11 @@ static void ar9003_hw_apply_tuning_caps(
+ static void ar9003_hw_quick_drop_apply(struct ath_hw *ah, u16 freq)
+ {
+ struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
+- int quick_drop = ath9k_hw_ar9300_get_eeprom(ah, EEP_QUICK_DROP);
++ struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
++ int quick_drop;
+ s32 t[3], f[3] = {5180, 5500, 5785};
+
+- if (!quick_drop)
++ if (!(pBase->miscConfiguration & BIT(1)))
+ return;
+
+ if (freq < 4000)
+@@ -3938,13 +3923,11 @@ static void ar9003_hw_quick_drop_apply(s
+ REG_RMW_FIELD(ah, AR_PHY_AGC, AR_PHY_AGC_QUICK_DROP, quick_drop);
+ }
+
+-static void ar9003_hw_txend_to_xpa_off_apply(struct ath_hw *ah, u16 freq)
++static void ar9003_hw_txend_to_xpa_off_apply(struct ath_hw *ah, bool is2ghz)
+ {
+- struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
+ u32 value;
+
+- value = (freq < 4000) ? eep->modalHeader2G.txEndToXpaOff :
+- eep->modalHeader5G.txEndToXpaOff;
++ value = ar9003_modal_header(ah, is2ghz)->txEndToXpaOff;
+
+ REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL,
+ AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF, value);
+@@ -3952,19 +3935,63 @@ static void ar9003_hw_txend_to_xpa_off_a
+ AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF, value);
+ }
+
++static void ar9003_hw_xpa_timing_control_apply(struct ath_hw *ah, bool is2ghz)
++{
++ struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
++ u8 xpa_ctl;
++
++ if (!(eep->baseEepHeader.featureEnable & 0x80))
++ return;
++
++ if (!AR_SREV_9300(ah) && !AR_SREV_9340(ah) && !AR_SREV_9580(ah))
++ return;
++
++ xpa_ctl = ar9003_modal_header(ah, is2ghz)->txFrameToXpaOn;
++ if (is2ghz)
++ REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL,
++ AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON, xpa_ctl);
++ else
++ REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL,
++ AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON, xpa_ctl);
++}
++
++static void ar9003_hw_xlna_bias_strength_apply(struct ath_hw *ah, bool is2ghz)
++{
++ struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
++ u8 bias;
++
++ if (!(eep->baseEepHeader.featureEnable & 0x40))
++ return;
++
++ if (!AR_SREV_9300(ah))
++ return;
++
++ bias = ar9003_modal_header(ah, is2ghz)->xlna_bias_strength;
++ REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX4, AR_PHY_65NM_RXTX4_XLNA_BIAS,
++ bias & 0x3);
++ bias >>= 2;
++ REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX4, AR_PHY_65NM_RXTX4_XLNA_BIAS,
++ bias & 0x3);
++ bias >>= 2;
++ REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX4, AR_PHY_65NM_RXTX4_XLNA_BIAS,
++ bias & 0x3);
++}
++
+ static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
+ struct ath9k_channel *chan)
+ {
+- ar9003_hw_xpa_bias_level_apply(ah, IS_CHAN_2GHZ(chan));
+- ar9003_hw_ant_ctrl_apply(ah, IS_CHAN_2GHZ(chan));
++ bool is2ghz = IS_CHAN_2GHZ(chan);
++ ar9003_hw_xpa_timing_control_apply(ah, is2ghz);
++ ar9003_hw_xpa_bias_level_apply(ah, is2ghz);
++ ar9003_hw_ant_ctrl_apply(ah, is2ghz);
+ ar9003_hw_drive_strength_apply(ah);
++ ar9003_hw_xlna_bias_strength_apply(ah, is2ghz);
+ ar9003_hw_atten_apply(ah, chan);
+ ar9003_hw_quick_drop_apply(ah, chan->channel);
+ if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah) && !AR_SREV_9550(ah))
+ ar9003_hw_internal_regulator_apply(ah);
+- if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
+- ar9003_hw_apply_tuning_caps(ah);
+- ar9003_hw_txend_to_xpa_off_apply(ah, chan->channel);
++ ar9003_hw_apply_tuning_caps(ah);
++ ar9003_hw_txend_to_xpa_off_apply(ah, is2ghz);
+ }
+
+ static void ath9k_hw_ar9300_set_addac(struct ath_hw *ah,
+@@ -5100,14 +5127,9 @@ s32 ar9003_hw_get_rx_gain_idx(struct ath
+ return (eep->baseEepHeader.txrxgain) & 0xf; /* bits 3:0 */
+ }
+
+-u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is_2ghz)
++u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is2ghz)
+ {
+- struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
+-
+- if (is_2ghz)
+- return eep->modalHeader2G.spurChans;
+- else
+- return eep->modalHeader5G.spurChans;
++ return ar9003_modal_header(ah, is2ghz)->spurChans;
+ }
+
+ unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah,
+--- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
++++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
+@@ -231,7 +231,8 @@ struct ar9300_modal_eep_header {
+ __le32 papdRateMaskHt20;
+ __le32 papdRateMaskHt40;
+ __le16 switchcomspdt;
+- u8 futureModal[8];
++ u8 xlna_bias_strength;
++ u8 futureModal[7];
+ } __packed;
+
+ struct ar9300_cal_data_per_freq_op_loop {
+--- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c
++++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
+@@ -44,462 +44,310 @@ static void ar9003_hw_init_mode_regs(str
+ ar9462_2p0_baseband_core_txfir_coeff_japan_2484
+ if (AR_SREV_9330_11(ah)) {
+ /* mac */
+- INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
+ INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
+- ar9331_1p1_mac_core,
+- ARRAY_SIZE(ar9331_1p1_mac_core), 2);
++ ar9331_1p1_mac_core);
+ INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
+- ar9331_1p1_mac_postamble,
+- ARRAY_SIZE(ar9331_1p1_mac_postamble), 5);
++ ar9331_1p1_mac_postamble);
+
+ /* bb */
+- INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
+ INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
+- ar9331_1p1_baseband_core,
+- ARRAY_SIZE(ar9331_1p1_baseband_core), 2);
++ ar9331_1p1_baseband_core);
+ INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
+- ar9331_1p1_baseband_postamble,
+- ARRAY_SIZE(ar9331_1p1_baseband_postamble), 5);
++ ar9331_1p1_baseband_postamble);
+
+ /* radio */
+- INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
+ INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
+- ar9331_1p1_radio_core,
+- ARRAY_SIZE(ar9331_1p1_radio_core), 2);
+- INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], NULL, 0, 0);
++ ar9331_1p1_radio_core);
+
+ /* soc */
+ INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
+- ar9331_1p1_soc_preamble,
+- ARRAY_SIZE(ar9331_1p1_soc_preamble), 2);
+- INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
++ ar9331_1p1_soc_preamble);
+ INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
+- ar9331_1p1_soc_postamble,
+- ARRAY_SIZE(ar9331_1p1_soc_postamble), 2);
++ ar9331_1p1_soc_postamble);
+
+ /* rx/tx gain */
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar9331_common_rx_gain_1p1,
+- ARRAY_SIZE(ar9331_common_rx_gain_1p1), 2);
++ ar9331_common_rx_gain_1p1);
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9331_modes_lowest_ob_db_tx_gain_1p1,
+- ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p1),
+- 5);
++ ar9331_modes_lowest_ob_db_tx_gain_1p1);
+
+ /* additional clock settings */
+ if (ah->is_clk_25mhz)
+ INIT_INI_ARRAY(&ah->iniAdditional,
+- ar9331_1p1_xtal_25M,
+- ARRAY_SIZE(ar9331_1p1_xtal_25M), 2);
++ ar9331_1p1_xtal_25M);
+ else
+ INIT_INI_ARRAY(&ah->iniAdditional,
+- ar9331_1p1_xtal_40M,
+- ARRAY_SIZE(ar9331_1p1_xtal_40M), 2);
++ ar9331_1p1_xtal_40M);
+ } else if (AR_SREV_9330_12(ah)) {
+ /* mac */
+- INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
+ INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
+- ar9331_1p2_mac_core,
+- ARRAY_SIZE(ar9331_1p2_mac_core), 2);
++ ar9331_1p2_mac_core);
+ INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
+- ar9331_1p2_mac_postamble,
+- ARRAY_SIZE(ar9331_1p2_mac_postamble), 5);
++ ar9331_1p2_mac_postamble);
+
+ /* bb */
+- INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
+ INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
+- ar9331_1p2_baseband_core,
+- ARRAY_SIZE(ar9331_1p2_baseband_core), 2);
++ ar9331_1p2_baseband_core);
+ INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
+- ar9331_1p2_baseband_postamble,
+- ARRAY_SIZE(ar9331_1p2_baseband_postamble), 5);
++ ar9331_1p2_baseband_postamble);
+
+ /* radio */
+- INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
+ INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
+- ar9331_1p2_radio_core,
+- ARRAY_SIZE(ar9331_1p2_radio_core), 2);
+- INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], NULL, 0, 0);
++ ar9331_1p2_radio_core);
+
+ /* soc */
+ INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
+- ar9331_1p2_soc_preamble,
+- ARRAY_SIZE(ar9331_1p2_soc_preamble), 2);
+- INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
++ ar9331_1p2_soc_preamble);
+ INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
+- ar9331_1p2_soc_postamble,
+- ARRAY_SIZE(ar9331_1p2_soc_postamble), 2);
++ ar9331_1p2_soc_postamble);
+
+ /* rx/tx gain */
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar9331_common_rx_gain_1p2,
+- ARRAY_SIZE(ar9331_common_rx_gain_1p2), 2);
++ ar9331_common_rx_gain_1p2);
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9331_modes_lowest_ob_db_tx_gain_1p2,
+- ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p2),
+- 5);
++ ar9331_modes_lowest_ob_db_tx_gain_1p2);
+
+ /* additional clock settings */
+ if (ah->is_clk_25mhz)
+ INIT_INI_ARRAY(&ah->iniAdditional,
+- ar9331_1p2_xtal_25M,
+- ARRAY_SIZE(ar9331_1p2_xtal_25M), 2);
++ ar9331_1p2_xtal_25M);
+ else
+ INIT_INI_ARRAY(&ah->iniAdditional,
+- ar9331_1p2_xtal_40M,
+- ARRAY_SIZE(ar9331_1p2_xtal_40M), 2);
++ ar9331_1p2_xtal_40M);
+ } else if (AR_SREV_9340(ah)) {
+ /* mac */
+- INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
+ INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
+- ar9340_1p0_mac_core,
+- ARRAY_SIZE(ar9340_1p0_mac_core), 2);
++ ar9340_1p0_mac_core);
+ INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
+- ar9340_1p0_mac_postamble,
+- ARRAY_SIZE(ar9340_1p0_mac_postamble), 5);
++ ar9340_1p0_mac_postamble);
+
+ /* bb */
+- INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
+ INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
+- ar9340_1p0_baseband_core,
+- ARRAY_SIZE(ar9340_1p0_baseband_core), 2);
++ ar9340_1p0_baseband_core);
+ INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
+- ar9340_1p0_baseband_postamble,
+- ARRAY_SIZE(ar9340_1p0_baseband_postamble), 5);
++ ar9340_1p0_baseband_postamble);
+
+ /* radio */
+- INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
+ INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
+- ar9340_1p0_radio_core,
+- ARRAY_SIZE(ar9340_1p0_radio_core), 2);
++ ar9340_1p0_radio_core);
+ INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
+- ar9340_1p0_radio_postamble,
+- ARRAY_SIZE(ar9340_1p0_radio_postamble), 5);
++ ar9340_1p0_radio_postamble);
+
+ /* soc */
+ INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
+- ar9340_1p0_soc_preamble,
+- ARRAY_SIZE(ar9340_1p0_soc_preamble), 2);
+- INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
++ ar9340_1p0_soc_preamble);
+ INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
+- ar9340_1p0_soc_postamble,
+- ARRAY_SIZE(ar9340_1p0_soc_postamble), 5);
++ ar9340_1p0_soc_postamble);
+
+ /* rx/tx gain */
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar9340Common_wo_xlna_rx_gain_table_1p0,
+- ARRAY_SIZE(ar9340Common_wo_xlna_rx_gain_table_1p0),
+- 5);
+- INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9340Modes_high_ob_db_tx_gain_table_1p0,
+- ARRAY_SIZE(ar9340Modes_high_ob_db_tx_gain_table_1p0),
+- 5);
++ ar9340Common_wo_xlna_rx_gain_table_1p0);
++ INIT_INI_ARRAY(&ah->iniModesTxGain,
++ ar9340Modes_high_ob_db_tx_gain_table_1p0);
+
+ INIT_INI_ARRAY(&ah->iniModesFastClock,
+- ar9340Modes_fast_clock_1p0,
+- ARRAY_SIZE(ar9340Modes_fast_clock_1p0),
+- 3);
++ ar9340Modes_fast_clock_1p0);
+
+ if (!ah->is_clk_25mhz)
+ INIT_INI_ARRAY(&ah->iniAdditional,
+- ar9340_1p0_radio_core_40M,
+- ARRAY_SIZE(ar9340_1p0_radio_core_40M),
+- 2);
++ ar9340_1p0_radio_core_40M);
+ } else if (AR_SREV_9485_11(ah)) {
+ /* mac */
+- INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
+ INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
+- ar9485_1_1_mac_core,
+- ARRAY_SIZE(ar9485_1_1_mac_core), 2);
++ ar9485_1_1_mac_core);
+ INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
+- ar9485_1_1_mac_postamble,
+- ARRAY_SIZE(ar9485_1_1_mac_postamble), 5);
++ ar9485_1_1_mac_postamble);
+
+ /* bb */
+- INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_1,
+- ARRAY_SIZE(ar9485_1_1), 2);
++ INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_1);
+ INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
+- ar9485_1_1_baseband_core,
+- ARRAY_SIZE(ar9485_1_1_baseband_core), 2);
++ ar9485_1_1_baseband_core);
+ INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
+- ar9485_1_1_baseband_postamble,
+- ARRAY_SIZE(ar9485_1_1_baseband_postamble), 5);
++ ar9485_1_1_baseband_postamble);
+
+ /* radio */
+- INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
+ INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
+- ar9485_1_1_radio_core,
+- ARRAY_SIZE(ar9485_1_1_radio_core), 2);
++ ar9485_1_1_radio_core);
+ INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
+- ar9485_1_1_radio_postamble,
+- ARRAY_SIZE(ar9485_1_1_radio_postamble), 2);
++ ar9485_1_1_radio_postamble);
+
+ /* soc */
+ INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
+- ar9485_1_1_soc_preamble,
+- ARRAY_SIZE(ar9485_1_1_soc_preamble), 2);
+- INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
+- INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], NULL, 0, 0);
++ ar9485_1_1_soc_preamble);
+
+ /* rx/tx gain */
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar9485Common_wo_xlna_rx_gain_1_1,
+- ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1), 2);
++ ar9485Common_wo_xlna_rx_gain_1_1);
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9485_modes_lowest_ob_db_tx_gain_1_1,
+- ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1),
+- 5);
++ ar9485_modes_lowest_ob_db_tx_gain_1_1);
+
+ /* Load PCIE SERDES settings from INI */
+
+ /* Awake Setting */
+
+ INIT_INI_ARRAY(&ah->iniPcieSerdes,
+- ar9485_1_1_pcie_phy_clkreq_disable_L1,
+- ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1),
+- 2);
++ ar9485_1_1_pcie_phy_clkreq_disable_L1);
+
+ /* Sleep Setting */
+
+ INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
+- ar9485_1_1_pcie_phy_clkreq_disable_L1,
+- ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1),
+- 2);
++ ar9485_1_1_pcie_phy_clkreq_disable_L1);
+ } else if (AR_SREV_9462_20(ah)) {
+
+- INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
+- INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core,
+- ARRAY_SIZE(ar9462_2p0_mac_core), 2);
++ INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core);
+ INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
+- ar9462_2p0_mac_postamble,
+- ARRAY_SIZE(ar9462_2p0_mac_postamble), 5);
++ ar9462_2p0_mac_postamble);
+
+- INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
+ INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
+- ar9462_2p0_baseband_core,
+- ARRAY_SIZE(ar9462_2p0_baseband_core), 2);
++ ar9462_2p0_baseband_core);
+ INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
+- ar9462_2p0_baseband_postamble,
+- ARRAY_SIZE(ar9462_2p0_baseband_postamble), 5);
++ ar9462_2p0_baseband_postamble);
+
+- INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
+ INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
+- ar9462_2p0_radio_core,
+- ARRAY_SIZE(ar9462_2p0_radio_core), 2);
++ ar9462_2p0_radio_core);
+ INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
+- ar9462_2p0_radio_postamble,
+- ARRAY_SIZE(ar9462_2p0_radio_postamble), 5);
++ ar9462_2p0_radio_postamble);
+ INIT_INI_ARRAY(&ah->ini_radio_post_sys2ant,
+- ar9462_2p0_radio_postamble_sys2ant,
+- ARRAY_SIZE(ar9462_2p0_radio_postamble_sys2ant),
+- 5);
++ ar9462_2p0_radio_postamble_sys2ant);
+
+ INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
+- ar9462_2p0_soc_preamble,
+- ARRAY_SIZE(ar9462_2p0_soc_preamble), 2);
+- INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
++ ar9462_2p0_soc_preamble);
+ INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
+- ar9462_2p0_soc_postamble,
+- ARRAY_SIZE(ar9462_2p0_soc_postamble), 5);
++ ar9462_2p0_soc_postamble);
+
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar9462_common_rx_gain_table_2p0,
+- ARRAY_SIZE(ar9462_common_rx_gain_table_2p0), 2);
++ ar9462_common_rx_gain_table_2p0);
+
+ /* Awake -> Sleep Setting */
+ INIT_INI_ARRAY(&ah->iniPcieSerdes,
+- PCIE_PLL_ON_CREQ_DIS_L1_2P0,
+- ARRAY_SIZE(PCIE_PLL_ON_CREQ_DIS_L1_2P0),
+- 2);
++ PCIE_PLL_ON_CREQ_DIS_L1_2P0);
+ /* Sleep -> Awake Setting */
+ INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
+- PCIE_PLL_ON_CREQ_DIS_L1_2P0,
+- ARRAY_SIZE(PCIE_PLL_ON_CREQ_DIS_L1_2P0),
+- 2);
++ PCIE_PLL_ON_CREQ_DIS_L1_2P0);
+
+ /* Fast clock modal settings */
+ INIT_INI_ARRAY(&ah->iniModesFastClock,
+- ar9462_modes_fast_clock_2p0,
+- ARRAY_SIZE(ar9462_modes_fast_clock_2p0), 3);
++ ar9462_modes_fast_clock_2p0);
+
+ INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
+- AR9462_BB_CTX_COEFJ(2p0),
+- ARRAY_SIZE(AR9462_BB_CTX_COEFJ(2p0)), 2);
++ AR9462_BB_CTX_COEFJ(2p0));
+
+- INIT_INI_ARRAY(&ah->ini_japan2484, AR9462_BBC_TXIFR_COEFFJ,
+- ARRAY_SIZE(AR9462_BBC_TXIFR_COEFFJ), 2);
++ INIT_INI_ARRAY(&ah->ini_japan2484, AR9462_BBC_TXIFR_COEFFJ);
+ } else if (AR_SREV_9550(ah)) {
+ /* mac */
+- INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
+ INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
+- ar955x_1p0_mac_core,
+- ARRAY_SIZE(ar955x_1p0_mac_core), 2);
++ ar955x_1p0_mac_core);
+ INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
+- ar955x_1p0_mac_postamble,
+- ARRAY_SIZE(ar955x_1p0_mac_postamble), 5);
++ ar955x_1p0_mac_postamble);
+
+ /* bb */
+- INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
+ INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
+- ar955x_1p0_baseband_core,
+- ARRAY_SIZE(ar955x_1p0_baseband_core), 2);
++ ar955x_1p0_baseband_core);
+ INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
+- ar955x_1p0_baseband_postamble,
+- ARRAY_SIZE(ar955x_1p0_baseband_postamble), 5);
++ ar955x_1p0_baseband_postamble);
+
+ /* radio */
+- INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
+ INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
+- ar955x_1p0_radio_core,
+- ARRAY_SIZE(ar955x_1p0_radio_core), 2);
++ ar955x_1p0_radio_core);
+ INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
+- ar955x_1p0_radio_postamble,
+- ARRAY_SIZE(ar955x_1p0_radio_postamble), 5);
++ ar955x_1p0_radio_postamble);
+
+ /* soc */
+ INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
+- ar955x_1p0_soc_preamble,
+- ARRAY_SIZE(ar955x_1p0_soc_preamble), 2);
+- INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
++ ar955x_1p0_soc_preamble);
+ INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
+- ar955x_1p0_soc_postamble,
+- ARRAY_SIZE(ar955x_1p0_soc_postamble), 5);
++ ar955x_1p0_soc_postamble);
+
+ /* rx/tx gain */
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar955x_1p0_common_wo_xlna_rx_gain_table,
+- ARRAY_SIZE(ar955x_1p0_common_wo_xlna_rx_gain_table),
+- 2);
++ ar955x_1p0_common_wo_xlna_rx_gain_table);
+ INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
+- ar955x_1p0_common_wo_xlna_rx_gain_bounds,
+- ARRAY_SIZE(ar955x_1p0_common_wo_xlna_rx_gain_bounds),
+- 5);
+- INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar955x_1p0_modes_xpa_tx_gain_table,
+- ARRAY_SIZE(ar955x_1p0_modes_xpa_tx_gain_table),
+- 9);
++ ar955x_1p0_common_wo_xlna_rx_gain_bounds);
++ INIT_INI_ARRAY(&ah->iniModesTxGain,
++ ar955x_1p0_modes_xpa_tx_gain_table);
+
+ /* Fast clock modal settings */
+ INIT_INI_ARRAY(&ah->iniModesFastClock,
+- ar955x_1p0_modes_fast_clock,
+- ARRAY_SIZE(ar955x_1p0_modes_fast_clock), 3);
++ ar955x_1p0_modes_fast_clock);
+ } else if (AR_SREV_9580(ah)) {
+ /* mac */
+- INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
+ INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
+- ar9580_1p0_mac_core,
+- ARRAY_SIZE(ar9580_1p0_mac_core), 2);
++ ar9580_1p0_mac_core);
+ INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
+- ar9580_1p0_mac_postamble,
+- ARRAY_SIZE(ar9580_1p0_mac_postamble), 5);
++ ar9580_1p0_mac_postamble);
+
+ /* bb */
+- INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
+ INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
+- ar9580_1p0_baseband_core,
+- ARRAY_SIZE(ar9580_1p0_baseband_core), 2);
++ ar9580_1p0_baseband_core);
+ INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
+- ar9580_1p0_baseband_postamble,
+- ARRAY_SIZE(ar9580_1p0_baseband_postamble), 5);
++ ar9580_1p0_baseband_postamble);
+
+ /* radio */
+- INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
+ INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
+- ar9580_1p0_radio_core,
+- ARRAY_SIZE(ar9580_1p0_radio_core), 2);
++ ar9580_1p0_radio_core);
+ INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
+- ar9580_1p0_radio_postamble,
+- ARRAY_SIZE(ar9580_1p0_radio_postamble), 5);
++ ar9580_1p0_radio_postamble);
+
+ /* soc */
+ INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
+- ar9580_1p0_soc_preamble,
+- ARRAY_SIZE(ar9580_1p0_soc_preamble), 2);
+- INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
++ ar9580_1p0_soc_preamble);
+ INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
+- ar9580_1p0_soc_postamble,
+- ARRAY_SIZE(ar9580_1p0_soc_postamble), 5);
++ ar9580_1p0_soc_postamble);
+
+ /* rx/tx gain */
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar9580_1p0_rx_gain_table,
+- ARRAY_SIZE(ar9580_1p0_rx_gain_table), 2);
++ ar9580_1p0_rx_gain_table);
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9580_1p0_low_ob_db_tx_gain_table,
+- ARRAY_SIZE(ar9580_1p0_low_ob_db_tx_gain_table),
+- 5);
++ ar9580_1p0_low_ob_db_tx_gain_table);
+
+ INIT_INI_ARRAY(&ah->iniModesFastClock,
+- ar9580_1p0_modes_fast_clock,
+- ARRAY_SIZE(ar9580_1p0_modes_fast_clock),
+- 3);
++ ar9580_1p0_modes_fast_clock);
+ } else {
+ /* mac */
+- INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
+ INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
+- ar9300_2p2_mac_core,
+- ARRAY_SIZE(ar9300_2p2_mac_core), 2);
++ ar9300_2p2_mac_core);
+ INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
+- ar9300_2p2_mac_postamble,
+- ARRAY_SIZE(ar9300_2p2_mac_postamble), 5);
++ ar9300_2p2_mac_postamble);
+
+ /* bb */
+- INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
+ INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
+- ar9300_2p2_baseband_core,
+- ARRAY_SIZE(ar9300_2p2_baseband_core), 2);
++ ar9300_2p2_baseband_core);
+ INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
+- ar9300_2p2_baseband_postamble,
+- ARRAY_SIZE(ar9300_2p2_baseband_postamble), 5);
++ ar9300_2p2_baseband_postamble);
+
+ /* radio */
+- INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
+ INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
+- ar9300_2p2_radio_core,
+- ARRAY_SIZE(ar9300_2p2_radio_core), 2);
++ ar9300_2p2_radio_core);
+ INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
+- ar9300_2p2_radio_postamble,
+- ARRAY_SIZE(ar9300_2p2_radio_postamble), 5);
++ ar9300_2p2_radio_postamble);
+
+ /* soc */
+ INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
+- ar9300_2p2_soc_preamble,
+- ARRAY_SIZE(ar9300_2p2_soc_preamble), 2);
+- INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
++ ar9300_2p2_soc_preamble);
+ INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
+- ar9300_2p2_soc_postamble,
+- ARRAY_SIZE(ar9300_2p2_soc_postamble), 5);
++ ar9300_2p2_soc_postamble);
+
+ /* rx/tx gain */
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar9300Common_rx_gain_table_2p2,
+- ARRAY_SIZE(ar9300Common_rx_gain_table_2p2), 2);
++ ar9300Common_rx_gain_table_2p2);
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
+- ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
+- 5);
++ ar9300Modes_lowest_ob_db_tx_gain_table_2p2);
+
+ /* Load PCIE SERDES settings from INI */
+
+ /* Awake Setting */
+
+ INIT_INI_ARRAY(&ah->iniPcieSerdes,
+- ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,
+- ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
+- 2);
++ ar9300PciePhy_pll_on_clkreq_disable_L1_2p2);
+
+ /* Sleep Setting */
+
+ INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
+- ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,
+- ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
+- 2);
++ ar9300PciePhy_pll_on_clkreq_disable_L1_2p2);
+
+ /* Fast clock modal settings */
+ INIT_INI_ARRAY(&ah->iniModesFastClock,
+- ar9300Modes_fast_clock_2p2,
+- ARRAY_SIZE(ar9300Modes_fast_clock_2p2),
+- 3);
++ ar9300Modes_fast_clock_2p2);
+ }
+ }
+
+@@ -507,156 +355,110 @@ static void ar9003_tx_gain_table_mode0(s
+ {
+ if (AR_SREV_9330_12(ah))
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9331_modes_lowest_ob_db_tx_gain_1p2,
+- ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p2),
+- 5);
++ ar9331_modes_lowest_ob_db_tx_gain_1p2);
+ else if (AR_SREV_9330_11(ah))
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9331_modes_lowest_ob_db_tx_gain_1p1,
+- ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p1),
+- 5);
++ ar9331_modes_lowest_ob_db_tx_gain_1p1);
+ else if (AR_SREV_9340(ah))
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
+- ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
+- 5);
++ ar9340Modes_lowest_ob_db_tx_gain_table_1p0);
+ else if (AR_SREV_9485_11(ah))
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9485_modes_lowest_ob_db_tx_gain_1_1,
+- ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1),
+- 5);
++ ar9485_modes_lowest_ob_db_tx_gain_1_1);
+ else if (AR_SREV_9550(ah))
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar955x_1p0_modes_xpa_tx_gain_table,
+- ARRAY_SIZE(ar955x_1p0_modes_xpa_tx_gain_table),
+- 9);
++ ar955x_1p0_modes_xpa_tx_gain_table);
+ else if (AR_SREV_9580(ah))
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9580_1p0_lowest_ob_db_tx_gain_table,
+- ARRAY_SIZE(ar9580_1p0_lowest_ob_db_tx_gain_table),
+- 5);
++ ar9580_1p0_lowest_ob_db_tx_gain_table);
+ else if (AR_SREV_9462_20(ah))
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9462_modes_low_ob_db_tx_gain_table_2p0,
+- ARRAY_SIZE(ar9462_modes_low_ob_db_tx_gain_table_2p0),
+- 5);
++ ar9462_modes_low_ob_db_tx_gain_table_2p0);
+ else
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
+- ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
+- 5);
++ ar9300Modes_lowest_ob_db_tx_gain_table_2p2);
+ }
+
+ static void ar9003_tx_gain_table_mode1(struct ath_hw *ah)
+ {
+ if (AR_SREV_9330_12(ah))
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9331_modes_high_ob_db_tx_gain_1p2,
+- ARRAY_SIZE(ar9331_modes_high_ob_db_tx_gain_1p2),
+- 5);
++ ar9331_modes_high_ob_db_tx_gain_1p2);
+ else if (AR_SREV_9330_11(ah))
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9331_modes_high_ob_db_tx_gain_1p1,
+- ARRAY_SIZE(ar9331_modes_high_ob_db_tx_gain_1p1),
+- 5);
++ ar9331_modes_high_ob_db_tx_gain_1p1);
+ else if (AR_SREV_9340(ah))
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
+- ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
+- 5);
++ ar9340Modes_high_ob_db_tx_gain_table_1p0);
+ else if (AR_SREV_9485_11(ah))
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9485Modes_high_ob_db_tx_gain_1_1,
+- ARRAY_SIZE(ar9485Modes_high_ob_db_tx_gain_1_1),
+- 5);
++ ar9485Modes_high_ob_db_tx_gain_1_1);
+ else if (AR_SREV_9580(ah))
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9580_1p0_high_ob_db_tx_gain_table,
+- ARRAY_SIZE(ar9580_1p0_high_ob_db_tx_gain_table),
+- 5);
++ ar9580_1p0_high_ob_db_tx_gain_table);
+ else if (AR_SREV_9550(ah))
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar955x_1p0_modes_no_xpa_tx_gain_table,
+- ARRAY_SIZE(ar955x_1p0_modes_no_xpa_tx_gain_table),
+- 9);
++ ar955x_1p0_modes_no_xpa_tx_gain_table);
+ else if (AR_SREV_9462_20(ah))
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9462_modes_high_ob_db_tx_gain_table_2p0,
+- ARRAY_SIZE(ar9462_modes_high_ob_db_tx_gain_table_2p0),
+- 5);
++ ar9462_modes_high_ob_db_tx_gain_table_2p0);
+ else
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9300Modes_high_ob_db_tx_gain_table_2p2,
+- ARRAY_SIZE(ar9300Modes_high_ob_db_tx_gain_table_2p2),
+- 5);
++ ar9300Modes_high_ob_db_tx_gain_table_2p2);
+ }
+
+ static void ar9003_tx_gain_table_mode2(struct ath_hw *ah)
+ {
+ if (AR_SREV_9330_12(ah))
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9331_modes_low_ob_db_tx_gain_1p2,
+- ARRAY_SIZE(ar9331_modes_low_ob_db_tx_gain_1p2),
+- 5);
++ ar9331_modes_low_ob_db_tx_gain_1p2);
+ else if (AR_SREV_9330_11(ah))
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9331_modes_low_ob_db_tx_gain_1p1,
+- ARRAY_SIZE(ar9331_modes_low_ob_db_tx_gain_1p1),
+- 5);
++ ar9331_modes_low_ob_db_tx_gain_1p1);
+ else if (AR_SREV_9340(ah))
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
+- ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
+- 5);
++ ar9340Modes_low_ob_db_tx_gain_table_1p0);
+ else if (AR_SREV_9485_11(ah))
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9485Modes_low_ob_db_tx_gain_1_1,
+- ARRAY_SIZE(ar9485Modes_low_ob_db_tx_gain_1_1),
+- 5);
++ ar9485Modes_low_ob_db_tx_gain_1_1);
+ else if (AR_SREV_9580(ah))
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9580_1p0_low_ob_db_tx_gain_table,
+- ARRAY_SIZE(ar9580_1p0_low_ob_db_tx_gain_table),
+- 5);
++ ar9580_1p0_low_ob_db_tx_gain_table);
+ else
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9300Modes_low_ob_db_tx_gain_table_2p2,
+- ARRAY_SIZE(ar9300Modes_low_ob_db_tx_gain_table_2p2),
+- 5);
++ ar9300Modes_low_ob_db_tx_gain_table_2p2);
+ }
+
+ static void ar9003_tx_gain_table_mode3(struct ath_hw *ah)
+ {
+ if (AR_SREV_9330_12(ah))
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9331_modes_high_power_tx_gain_1p2,
+- ARRAY_SIZE(ar9331_modes_high_power_tx_gain_1p2),
+- 5);
++ ar9331_modes_high_power_tx_gain_1p2);
+ else if (AR_SREV_9330_11(ah))
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9331_modes_high_power_tx_gain_1p1,
+- ARRAY_SIZE(ar9331_modes_high_power_tx_gain_1p1),
+- 5);
++ ar9331_modes_high_power_tx_gain_1p1);
+ else if (AR_SREV_9340(ah))
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
+- ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
+- 5);
++ ar9340Modes_high_power_tx_gain_table_1p0);
+ else if (AR_SREV_9485_11(ah))
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9485Modes_high_power_tx_gain_1_1,
+- ARRAY_SIZE(ar9485Modes_high_power_tx_gain_1_1),
+- 5);
++ ar9485Modes_high_power_tx_gain_1_1);
+ else if (AR_SREV_9580(ah))
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9580_1p0_high_power_tx_gain_table,
+- ARRAY_SIZE(ar9580_1p0_high_power_tx_gain_table),
+- 5);
++ ar9580_1p0_high_power_tx_gain_table);
+ else
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9300Modes_high_power_tx_gain_table_2p2,
+- ARRAY_SIZE(ar9300Modes_high_power_tx_gain_table_2p2),
+- 5);
++ ar9300Modes_high_power_tx_gain_table_2p2);
++}
++
++static void ar9003_tx_gain_table_mode4(struct ath_hw *ah)
++{
++ if (AR_SREV_9340(ah))
++ INIT_INI_ARRAY(&ah->iniModesTxGain,
++ ar9340Modes_mixed_ob_db_tx_gain_table_1p0);
++ else if (AR_SREV_9580(ah))
++ INIT_INI_ARRAY(&ah->iniModesTxGain,
++ ar9580_1p0_mixed_ob_db_tx_gain_table);
+ }
+
+ static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
+@@ -675,6 +477,9 @@ static void ar9003_tx_gain_table_apply(s
+ case 3:
+ ar9003_tx_gain_table_mode3(ah);
+ break;
++ case 4:
++ ar9003_tx_gain_table_mode4(ah);
++ break;
+ }
+ }
+
+@@ -682,104 +487,67 @@ static void ar9003_rx_gain_table_mode0(s
+ {
+ if (AR_SREV_9330_12(ah))
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar9331_common_rx_gain_1p2,
+- ARRAY_SIZE(ar9331_common_rx_gain_1p2),
+- 2);
++ ar9331_common_rx_gain_1p2);
+ else if (AR_SREV_9330_11(ah))
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar9331_common_rx_gain_1p1,
+- ARRAY_SIZE(ar9331_common_rx_gain_1p1),
+- 2);
++ ar9331_common_rx_gain_1p1);
+ else if (AR_SREV_9340(ah))
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar9340Common_rx_gain_table_1p0,
+- ARRAY_SIZE(ar9340Common_rx_gain_table_1p0),
+- 2);
++ ar9340Common_rx_gain_table_1p0);
+ else if (AR_SREV_9485_11(ah))
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar9485Common_wo_xlna_rx_gain_1_1,
+- ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
+- 2);
++ ar9485Common_wo_xlna_rx_gain_1_1);
+ else if (AR_SREV_9550(ah)) {
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar955x_1p0_common_rx_gain_table,
+- ARRAY_SIZE(ar955x_1p0_common_rx_gain_table),
+- 2);
++ ar955x_1p0_common_rx_gain_table);
+ INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
+- ar955x_1p0_common_rx_gain_bounds,
+- ARRAY_SIZE(ar955x_1p0_common_rx_gain_bounds),
+- 5);
++ ar955x_1p0_common_rx_gain_bounds);
+ } else if (AR_SREV_9580(ah))
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar9580_1p0_rx_gain_table,
+- ARRAY_SIZE(ar9580_1p0_rx_gain_table),
+- 2);
++ ar9580_1p0_rx_gain_table);
+ else if (AR_SREV_9462_20(ah))
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar9462_common_rx_gain_table_2p0,
+- ARRAY_SIZE(ar9462_common_rx_gain_table_2p0),
+- 2);
++ ar9462_common_rx_gain_table_2p0);
+ else
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar9300Common_rx_gain_table_2p2,
+- ARRAY_SIZE(ar9300Common_rx_gain_table_2p2),
+- 2);
++ ar9300Common_rx_gain_table_2p2);
+ }
+
+ static void ar9003_rx_gain_table_mode1(struct ath_hw *ah)
+ {
+ if (AR_SREV_9330_12(ah))
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar9331_common_wo_xlna_rx_gain_1p2,
+- ARRAY_SIZE(ar9331_common_wo_xlna_rx_gain_1p2),
+- 2);
++ ar9331_common_wo_xlna_rx_gain_1p2);
+ else if (AR_SREV_9330_11(ah))
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar9331_common_wo_xlna_rx_gain_1p1,
+- ARRAY_SIZE(ar9331_common_wo_xlna_rx_gain_1p1),
+- 2);
++ ar9331_common_wo_xlna_rx_gain_1p1);
+ else if (AR_SREV_9340(ah))
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar9340Common_wo_xlna_rx_gain_table_1p0,
+- ARRAY_SIZE(ar9340Common_wo_xlna_rx_gain_table_1p0),
+- 2);
++ ar9340Common_wo_xlna_rx_gain_table_1p0);
+ else if (AR_SREV_9485_11(ah))
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar9485Common_wo_xlna_rx_gain_1_1,
+- ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
+- 2);
++ ar9485Common_wo_xlna_rx_gain_1_1);
+ else if (AR_SREV_9462_20(ah))
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar9462_common_wo_xlna_rx_gain_table_2p0,
+- ARRAY_SIZE(ar9462_common_wo_xlna_rx_gain_table_2p0),
+- 2);
++ ar9462_common_wo_xlna_rx_gain_table_2p0);
+ else if (AR_SREV_9550(ah)) {
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar955x_1p0_common_wo_xlna_rx_gain_table,
+- ARRAY_SIZE(ar955x_1p0_common_wo_xlna_rx_gain_table),
+- 2);
++ ar955x_1p0_common_wo_xlna_rx_gain_table);
+ INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
+- ar955x_1p0_common_wo_xlna_rx_gain_bounds,
+- ARRAY_SIZE(ar955x_1p0_common_wo_xlna_rx_gain_bounds),
+- 5);
++ ar955x_1p0_common_wo_xlna_rx_gain_bounds);
+ } else if (AR_SREV_9580(ah))
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar9580_1p0_wo_xlna_rx_gain_table,
+- ARRAY_SIZE(ar9580_1p0_wo_xlna_rx_gain_table),
+- 2);
++ ar9580_1p0_wo_xlna_rx_gain_table);
+ else
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar9300Common_wo_xlna_rx_gain_table_2p2,
+- ARRAY_SIZE(ar9300Common_wo_xlna_rx_gain_table_2p2),
+- 2);
++ ar9300Common_wo_xlna_rx_gain_table_2p2);
+ }
+
+ static void ar9003_rx_gain_table_mode2(struct ath_hw *ah)
+ {
+ if (AR_SREV_9462_20(ah))
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar9462_common_mixed_rx_gain_table_2p0,
+- ARRAY_SIZE(ar9462_common_mixed_rx_gain_table_2p0), 2);
++ ar9462_common_mixed_rx_gain_table_2p0);
+ }
+
+ static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
+--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
++++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
+@@ -117,8 +117,8 @@ static int ar9003_hw_set_channel(struct
+ ah->is_clk_25mhz) {
+ u32 chan_frac;
+
+- channelSel = (freq * 2) / 75;
+- chan_frac = (((freq * 2) % 75) * 0x20000) / 75;
++ channelSel = freq / 75;
++ chan_frac = ((freq % 75) * 0x20000) / 75;
+ channelSel = (channelSel << 17) | chan_frac;
+ } else {
+ channelSel = CHANSEL_5G(freq);
+--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.h
++++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
+@@ -633,6 +633,8 @@
+ #define AR_PHY_65NM_CH0_BIAS2 0x160c4
+ #define AR_PHY_65NM_CH0_BIAS4 0x160cc
+ #define AR_PHY_65NM_CH0_RXTX4 0x1610c
++#define AR_PHY_65NM_CH1_RXTX4 0x1650c
++#define AR_PHY_65NM_CH2_RXTX4 0x1690c
+
+ #define AR_CH0_TOP (AR_SREV_9300(ah) ? 0x16288 : \
+ ((AR_SREV_9462(ah) ? 0x1628c : 0x16280)))
+@@ -876,6 +878,9 @@
+ #define AR_PHY_65NM_CH0_RXTX4_THERM_ON 0x10000000
+ #define AR_PHY_65NM_CH0_RXTX4_THERM_ON_S 28
+
++#define AR_PHY_65NM_RXTX4_XLNA_BIAS 0xC0000000
++#define AR_PHY_65NM_RXTX4_XLNA_BIAS_S 30
++
+ /*
+ * Channel 1 Register Map
+ */
+--- a/drivers/net/wireless/ath/ath9k/ath9k.h
++++ b/drivers/net/wireless/ath/ath9k/ath9k.h
+@@ -297,6 +297,8 @@ struct ath_tx {
+ struct ath_txq txq[ATH9K_NUM_TX_QUEUES];
+ struct ath_descdma txdma;
+ struct ath_txq *txq_map[WME_NUM_AC];
++ u32 txq_max_pending[WME_NUM_AC];
++ u16 max_aggr_framelen[WME_NUM_AC][4][32];
+ };
+
+ struct ath_rx_edma {
+@@ -341,6 +343,7 @@ int ath_tx_init(struct ath_softc *sc, in
+ void ath_tx_cleanup(struct ath_softc *sc);
+ int ath_txq_update(struct ath_softc *sc, int qnum,
+ struct ath9k_tx_queue_info *q);
++void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop);
+ int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
+ struct ath_tx_control *txctl);
+ void ath_tx_tasklet(struct ath_softc *sc);
+@@ -360,7 +363,7 @@ void ath_tx_aggr_sleep(struct ieee80211_
+
+ struct ath_vif {
+ int av_bslot;
+- bool is_bslot_active, primary_sta_vif;
++ bool primary_sta_vif;
+ __le64 tsf_adjust; /* TSF adjustment for staggered beacons */
+ struct ath_buf *av_bcbuf;
+ };
+@@ -386,6 +389,7 @@ struct ath_beacon_config {
+ u16 dtim_period;
+ u16 bmiss_timeout;
+ u8 dtim_count;
++ bool enable_beacon;
+ };
+
+ struct ath_beacon {
+@@ -397,7 +401,6 @@ struct ath_beacon {
+
+ u32 beaconq;
+ u32 bmisscnt;
+- u32 ast_be_xmit;
+ u32 bc_tstamp;
+ struct ieee80211_vif *bslot[ATH_BCBUF];
+ int slottime;
+@@ -411,12 +414,14 @@ struct ath_beacon {
+ bool tx_last;
+ };
+
+-void ath_beacon_tasklet(unsigned long data);
+-void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif);
+-int ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_vif *vif);
+-void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp);
+-int ath_beaconq_config(struct ath_softc *sc);
+-void ath_set_beacon(struct ath_softc *sc);
++void ath9k_beacon_tasklet(unsigned long data);
++bool ath9k_allow_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif);
++void ath9k_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif,
++ u32 changed);
++void ath9k_beacon_assign_slot(struct ath_softc *sc, struct ieee80211_vif *vif);
++void ath9k_beacon_remove_slot(struct ath_softc *sc, struct ieee80211_vif *vif);
++void ath9k_set_tsfadjust(struct ath_softc *sc, struct ieee80211_vif *vif);
++void ath9k_set_beacon(struct ath_softc *sc);
+ void ath9k_set_beaconing_status(struct ath_softc *sc, bool status);
+
+ /*******************/
+@@ -442,9 +447,12 @@ void ath_rx_poll(unsigned long data);
+ void ath_start_rx_poll(struct ath_softc *sc, u8 nbeacon);
+ void ath_paprd_calibrate(struct work_struct *work);
+ void ath_ani_calibrate(unsigned long data);
+-void ath_start_ani(struct ath_common *common);
++void ath_start_ani(struct ath_softc *sc);
++void ath_stop_ani(struct ath_softc *sc);
++void ath_check_ani(struct ath_softc *sc);
+ int ath_update_survey_stats(struct ath_softc *sc);
+ void ath_update_survey_nf(struct ath_softc *sc, int channel);
++void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type);
+
+ /**********/
+ /* BTCOEX */
+@@ -619,7 +627,6 @@ enum sc_op_flags {
+ SC_OP_INVALID,
+ SC_OP_BEACONS,
+ SC_OP_RXFLUSH,
+- SC_OP_TSF_RESET,
+ SC_OP_ANI_RUN,
+ SC_OP_PRIM_STA_VIF,
+ SC_OP_HW_RESET,
+--- a/drivers/net/wireless/ath/ath9k/beacon.c
++++ b/drivers/net/wireless/ath/ath9k/beacon.c
+@@ -30,7 +30,7 @@ static void ath9k_reset_beacon_status(st
+ * the operating mode of the station (AP or AdHoc). Parameters are AIFS
+ * settings and channel width min/max
+ */
+-int ath_beaconq_config(struct ath_softc *sc)
++static void ath9k_beaconq_config(struct ath_softc *sc)
+ {
+ struct ath_hw *ah = sc->sc_ah;
+ struct ath_common *common = ath9k_hw_common(ah);
+@@ -38,6 +38,7 @@ int ath_beaconq_config(struct ath_softc
+ struct ath_txq *txq;
+
+ ath9k_hw_get_txq_props(ah, sc->beacon.beaconq, &qi);
++
+ if (sc->sc_ah->opmode == NL80211_IFTYPE_AP) {
+ /* Always burst out beacon and CAB traffic. */
+ qi.tqi_aifs = 1;
+@@ -56,12 +57,9 @@ int ath_beaconq_config(struct ath_softc
+ }
+
+ if (!ath9k_hw_set_txq_props(ah, sc->beacon.beaconq, &qi)) {
+- ath_err(common,
+- "Unable to update h/w beacon queue parameters\n");
+- return 0;
++ ath_err(common, "Unable to update h/w beacon queue parameters\n");
+ } else {
+ ath9k_hw_resettxqueue(ah, sc->beacon.beaconq);
+- return 1;
+ }
+ }
+
+@@ -70,7 +68,7 @@ int ath_beaconq_config(struct ath_softc
+ * up rate codes, and channel flags. Beacons are always sent out at the
+ * lowest rate, and are not retried.
+ */
+-static void ath_beacon_setup(struct ath_softc *sc, struct ieee80211_vif *vif,
++static void ath9k_beacon_setup(struct ath_softc *sc, struct ieee80211_vif *vif,
+ struct ath_buf *bf, int rateidx)
+ {
+ struct sk_buff *skb = bf->bf_mpdu;
+@@ -81,8 +79,6 @@ static void ath_beacon_setup(struct ath_
+ u8 chainmask = ah->txchainmask;
+ u8 rate = 0;
+
+- ath9k_reset_beacon_status(sc);