f2a70ca862d8376658eecad80019f4530e238944
[openwrt.git] / toolchain / binutils / patches / 2.19.1 / 600-ubicom32_binutils_20090818.patch
1 --- a/bfd/archures.c
2 +++ b/bfd/archures.c
3 @@ -375,6 +375,11 @@ DESCRIPTION
4  .  bfd_arch_score,     {* Sunplus score *} 
5  .  bfd_arch_openrisc,  {* OpenRISC *}
6  .  bfd_arch_mmix,      {* Donald Knuth's educational processor.  *}
7 +.  bfd_arch_ubicom32,
8 +.#define bfd_mach_ubicom32         0
9 +.#define bfd_mach_ubicom32dsp      1
10 +.#define bfd_mach_ubicom32ver4      2
11 +.#define bfd_mach_ubicom32posix     3
12  .  bfd_arch_xstormy16,
13  .#define bfd_mach_xstormy16    1
14  .  bfd_arch_msp430,    {* Texas Instruments MSP430 architecture.  *}
15 @@ -501,6 +506,7 @@ extern const bfd_arch_info_type bfd_tic3
16  extern const bfd_arch_info_type bfd_tic4x_arch;
17  extern const bfd_arch_info_type bfd_tic54x_arch;
18  extern const bfd_arch_info_type bfd_tic80_arch;
19 +extern const bfd_arch_info_type bfd_ubicom32_arch;
20  extern const bfd_arch_info_type bfd_v850_arch;
21  extern const bfd_arch_info_type bfd_vax_arch;
22  extern const bfd_arch_info_type bfd_we32k_arch;
23 @@ -570,6 +576,7 @@ static const bfd_arch_info_type * const 
24      &bfd_tic4x_arch,
25      &bfd_tic54x_arch,
26      &bfd_tic80_arch,
27 +    &bfd_ubicom32_arch,
28      &bfd_v850_arch,
29      &bfd_vax_arch,
30      &bfd_w65_arch,
31 --- a/bfd/bfd-in2.h
32 +++ b/bfd/bfd-in2.h
33 @@ -1997,6 +1997,11 @@ enum bfd_architecture
34    bfd_arch_score,     /* Sunplus score */ 
35    bfd_arch_openrisc,  /* OpenRISC */
36    bfd_arch_mmix,      /* Donald Knuth's educational processor.  */
37 +  bfd_arch_ubicom32,
38 +#define bfd_mach_ubicom32          0
39 +#define bfd_mach_ubicom32dsp       1
40 +#define bfd_mach_ubicom32ver4      2
41 +#define bfd_mach_ubicom32posix     3
42    bfd_arch_xstormy16,
43  #define bfd_mach_xstormy16     1
44    bfd_arch_msp430,    /* Texas Instruments MSP430 architecture.  */
45 @@ -3908,6 +3913,41 @@ instructions  */
46    BFD_RELOC_VPE4KMATH_DATA,
47    BFD_RELOC_VPE4KMATH_INSN,
48  
49 +/* Ubicom UBICOM32 Relocations.  */
50 +  BFD_RELOC_UBICOM32_21_PCREL,
51 +  BFD_RELOC_UBICOM32_24_PCREL,
52 +  BFD_RELOC_UBICOM32_HI24,
53 +  BFD_RELOC_UBICOM32_LO7_S,
54 +  BFD_RELOC_UBICOM32_LO7_2_S,
55 +  BFD_RELOC_UBICOM32_LO7_4_S,
56 +  BFD_RELOC_UBICOM32_LO7_D,
57 +  BFD_RELOC_UBICOM32_LO7_2_D,
58 +  BFD_RELOC_UBICOM32_LO7_4_D,
59 +  BFD_RELOC_UBICOM32_LO7_CALLI,
60 +  BFD_RELOC_UBICOM32_LO16_CALLI,
61 +  BFD_RELOC_UBICOM32_GOT_HI24,
62 +  BFD_RELOC_UBICOM32_GOT_LO7_S,
63 +  BFD_RELOC_UBICOM32_GOT_LO7_2_S,
64 +  BFD_RELOC_UBICOM32_GOT_LO7_4_S,
65 +  BFD_RELOC_UBICOM32_GOT_LO7_D,
66 +  BFD_RELOC_UBICOM32_GOT_LO7_2_D,
67 +  BFD_RELOC_UBICOM32_GOT_LO7_4_D,
68 +  BFD_RELOC_UBICOM32_FUNCDESC_GOT_HI24,
69 +  BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_S,
70 +  BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_2_S,
71 +  BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_4_S,
72 +  BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_D,
73 +  BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_2_D,
74 +  BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_4_D,
75 +  BFD_RELOC_UBICOM32_GOT_LO7_CALLI,
76 +  BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_CALLI,
77 +  BFD_RELOC_UBICOM32_FUNCDESC_VALUE,
78 +  BFD_RELOC_UBICOM32_FUNCDESC,
79 +  BFD_RELOC_UBICOM32_GOTOFFSET_LO,
80 +  BFD_RELOC_UBICOM32_GOTOFFSET_HI,
81 +  BFD_RELOC_UBICOM32_FUNCDESC_GOTOFFSET_LO,
82 +  BFD_RELOC_UBICOM32_FUNCDESC_GOTOFFSET_HI,
83 +
84  /* These two relocations are used by the linker to determine which of
85  the entries in a C++ virtual function table are actually used.  When
86  the --gc-sections option is given, the linker will zero out the entries
87 --- a/bfd/config.bfd
88 +++ b/bfd/config.bfd
89 @@ -1432,6 +1432,11 @@ case "${targ}" in
90      targ_underscore=yes
91      ;;
92  
93 +  ubicom32-*-*)
94 +    targ_defvec=bfd_elf32_ubicom32_vec
95 +    targ_selvecs=bfd_elf32_ubicom32fdpic_vec
96 +    ;;
97 +
98    v850-*-*)
99      targ_defvec=bfd_elf32_v850_vec
100      ;;
101 --- a/bfd/configure
102 +++ b/bfd/configure
103 @@ -19743,6 +19743,8 @@ do
104      bfd_elf32_tradbigmips_vec)  tb="$tb elf32-mips.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo" ;;
105      bfd_elf32_tradlittlemips_vec) tb="$tb elf32-mips.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo" ;;
106      bfd_elf32_us_cris_vec)     tb="$tb elf32-cris.lo elf32.lo $elf" ;;
107 +    bfd_elf32_ubicom32_vec)    tb="$tb elf32-ubicom32.lo elf32.lo $elf" ;;
108 +    bfd_elf32_ubicom32fdpic_vec)       tb="$tb elf32-ubicom32.lo elf32.lo $elf" ;;
109      bfd_elf32_v850_vec)                tb="$tb elf32-v850.lo elf32.lo $elf" ;;
110      bfd_elf32_vax_vec)         tb="$tb elf32-vax.lo elf32.lo $elf" ;;
111      bfd_elf32_xstormy16_vec)   tb="$tb elf32-xstormy16.lo elf32.lo $elf" ;;
112 --- a/bfd/configure.in
113 +++ b/bfd/configure.in
114 @@ -736,6 +736,8 @@ do
115      bfd_elf32_tradbigmips_vec)  tb="$tb elf32-mips.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo" ;;
116      bfd_elf32_tradlittlemips_vec) tb="$tb elf32-mips.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo" ;;
117      bfd_elf32_us_cris_vec)     tb="$tb elf32-cris.lo elf32.lo $elf" ;;
118 +    bfd_elf32_ubicom32_vec)    tb="$tb elf32-ubicom32.lo elf32.lo $elf" ;;
119 +    bfd_elf32_ubicom32fdpic_vec) tb="$tb elf32-ubicom32.lo elf32.lo $elf" ;;
120      bfd_elf32_v850_vec)                tb="$tb elf32-v850.lo elf32.lo $elf" ;;
121      bfd_elf32_vax_vec)         tb="$tb elf32-vax.lo elf32.lo $elf" ;;
122      bfd_elf32_xstormy16_vec)   tb="$tb elf32-xstormy16.lo elf32.lo $elf" ;;
123 --- /dev/null
124 +++ b/bfd/cpu-ubicom32.c
125 @@ -0,0 +1,126 @@
126 +/* BFD support for the Ubicom32 processor.
127 +   Copyright (C) 2000 Free Software Foundation, Inc.
128 +
129 +This file is part of BFD, the Binary File Descriptor library.
130 +
131 +This program is free software; you can redistribute it and/or modify
132 +it under the terms of the GNU General Public License as published by
133 +the Free Software Foundation; either version 2 of the License, or
134 +(at your option) any later version.
135 +
136 +This program is distributed in the hope that it will be useful,
137 +but WITHOUT ANY WARRANTY; without even the implied warranty of
138 +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
139 +GNU General Public License for more details.
140 +
141 +You should have received a copy of the GNU General Public License
142 +along with this program; if not, write to the Free Software
143 +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
144 +
145 +#include "bfd.h"
146 +#include "sysdep.h"
147 +#include "libbfd.h"
148 +
149 +static const bfd_arch_info_type *
150 +ubicom32_arch_compatible (const bfd_arch_info_type *a,
151 +                       const bfd_arch_info_type *b)
152 +{
153 +  if (a->arch != b->arch)
154 +    return NULL;
155 +
156 +  if (a->bits_per_word != b->bits_per_word)
157 +    return NULL;
158 +
159 +  if (a->mach > b->mach)
160 +    return a;
161 +
162 +  if (b->mach > a->mach)
163 +    return b;
164 +
165 +  if (b->mach == bfd_mach_ubicom32ver4  && 
166 +      strcmp("ubicom32uclinux", b->printable_name) == 0) {
167 +         return b;
168 +  }
169 +  
170 +  return a;
171 +}
172 +
173 +const bfd_arch_info_type bfd_ubicom32_uclinux_arch =
174 +{
175 +  32,                          /* bits per word */
176 +  32,                          /* bits per address */
177 +  8,                           /* bits per byte */
178 +  bfd_arch_ubicom32,           /* architecture */
179 +  bfd_mach_ubicom32ver4,       /* machine */
180 +  "ubicom32",                  /* architecture name */
181 +  "ubicom32uclinux",           /* printable name */
182 +  3,                           /* section align power */
183 +  FALSE,                       /* the default ? */
184 +  ubicom32_arch_compatible,    /* architecture comparison fn */
185 +  bfd_default_scan,            /* string to architecture convert fn */
186 +  NULL                         /* next in list */
187 +};
188 +
189 +const bfd_arch_info_type bfd_ubicom32_posix_arch =
190 +{
191 +  32,                          /* bits per word */
192 +  32,                          /* bits per address */
193 +  8,                           /* bits per byte */
194 +  bfd_arch_ubicom32,           /* architecture */
195 +  bfd_mach_ubicom32ver4,       /* machine */
196 +  "ubicom32",                  /* architecture name */
197 +  "ubicom32posix",             /* printable name */
198 +  3,                           /* section align power */
199 +  FALSE,                       /* the default ? */
200 +  bfd_default_compatible,      /* architecture comparison fn */
201 +  bfd_default_scan,            /* string to architecture convert fn */
202 +  &bfd_ubicom32_uclinux_arch,  /* next in list */
203 +};
204 +
205 +const bfd_arch_info_type bfd_ubicom32_ver4_arch =
206 +{
207 +  32,                          /* bits per word */
208 +  32,                          /* bits per address */
209 +  8,                           /* bits per byte */
210 +  bfd_arch_ubicom32,           /* architecture */
211 +  bfd_mach_ubicom32ver4,       /* machine */
212 +  "ubicom32",                  /* architecture name */
213 +  "ubicom32ver4",              /* printable name */
214 +  3,                           /* section align power */
215 +  FALSE,                       /* the default ? */
216 +  ubicom32_arch_compatible,    /* architecture comparison fn */
217 +  bfd_default_scan,            /* string to architecture convert fn */
218 +  &bfd_ubicom32_posix_arch     /* next in list */
219 +};
220 +
221 +const bfd_arch_info_type bfd_ubicom32_nonext_arch =
222 +{
223 +  32,                          /* bits per word */
224 +  32,                          /* bits per address */
225 +  8,                           /* bits per byte */
226 +  bfd_arch_ubicom32,           /* architecture */
227 +  bfd_mach_ubicom32dsp,                /* machine */
228 +  "ubicom32",                  /* architecture name */
229 +  "ubicom32dsp",               /* printable name */
230 +  3,                           /* section align power */
231 +  FALSE,                       /* the default ? */
232 +  bfd_default_compatible,      /* architecture comparison fn */
233 +  bfd_default_scan,            /* string to architecture convert fn */
234 +  & bfd_ubicom32_ver4_arch     /* next in list */
235 +};
236 +
237 +const bfd_arch_info_type bfd_ubicom32_arch =
238 +{
239 +  32,                          /* bits per word */
240 +  32,                          /* bits per address */
241 +  8,                           /* bits per byte */
242 +  bfd_arch_ubicom32,           /* architecture */
243 +  bfd_mach_ubicom32,           /* machine */
244 +  "ubicom32",                  /* architecture name */
245 +  "ubicom32",                  /* printable name */
246 +  3,                           /* section align power */
247 +  TRUE,                                /* the default ? */
248 +  bfd_default_compatible,      /* architecture comparison fn */
249 +  bfd_default_scan,            /* string to architecture convert fn */
250 +  & bfd_ubicom32_nonext_arch   /* next in list */
251 +};
252 --- a/bfd/doc/archures.texi
253 +++ b/bfd/doc/archures.texi
254 @@ -303,6 +303,11 @@ enum bfd_architecture
255    bfd_arch_ip2k,      /* Ubicom IP2K microcontrollers. */
256  #define bfd_mach_ip2022        1
257  #define bfd_mach_ip2022ext     2
258 +  bfd_arch_ubicom32,
259 +#define bfd_mach_ubicom32          0
260 +#define bfd_mach_ubicom32dsp       1
261 +#define bfd_mach_ubicom32ver4      2
262 +#define bfd_mach_ubicom32posix     3
263   bfd_arch_iq2000,     /* Vitesse IQ2000.  */
264  #define bfd_mach_iq2000        1
265  #define bfd_mach_iq10          2
266 --- /dev/null
267 +++ b/bfd/elf32-ubicom32.c
268 @@ -0,0 +1,5008 @@
269 +/* Ubicom32 specific support for 32-bit ELF
270 +   Copyright 2000 Free Software Foundation, Inc.
271 +
272 +This file is part of BFD, the Binary File Descriptor library.
273 +
274 +This program is free software; you can redistribute it and/or modify
275 +it under the terms of the GNU General Public License as published by
276 +the Free Software Foundation; either version 2 of the License, or
277 +(at your option) any later version.
278 +
279 +This program is distributed in the hope that it will be useful,
280 +but WITHOUT ANY WARRANTY; without even the implied warranty of
281 +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
282 +GNU General Public License for more details.
283 +
284 +You should have received a copy of the GNU General Public License
285 +along with this program; if not, write to the Free Software
286 +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
287 +
288 +#include <string.h>
289 +#include "bfd.h"
290 +#include "sysdep.h"
291 +#include "libbfd.h"
292 +#include "elf-bfd.h"
293 +#include "elf/ubicom32.h"
294 +#include "elf/dwarf2.h"
295 +
296 +/* Call offset = signed 24bit word offset
297 +   => 26bit signed byte offset.  */
298 +#define UBICOM32_CALL_MAX_POS_OFFS ((1 << 25) - 1)
299 +#define UBICOM32_CALL_MAX_NEG_OFFS (-(1 << 25))
300 +
301 +#define UNDEFINED_SYMBOL (~(bfd_vma)0)
302 +#define BASEADDR(SEC) ((SEC)->output_section->vma + (SEC)->output_offset)
303 +
304 +#if 0
305 +#define DPRINTF(fmt, ...) { printf("DBG %4d:"  fmt, __LINE__, __VA_ARGS__); fflush(stdout); }
306 +#else
307 +#define DPRINTF(fmt, ...) {}
308 +#endif
309 +struct debugLineInfo {
310 +  unsigned int startOffset;
311 +  unsigned int length;
312 +  char *sectionName;
313 +  unsigned int startRelocIndex;
314 +  unsigned int endRelocIndex;
315 +  unsigned int discard;
316 +};
317 +
318 +struct debugLineInfoHeader {
319 +  unsigned int numEntries;
320 +  struct debugLineInfo linfo[1];
321 +};
322 +
323 +/* we want RELA relocations, not REL */
324 +#undef USE_REL
325 +#define USE_RELA
326 +
327 +static bfd_reloc_status_type ubicom32_elf_generic_reloc
328 +  PARAMS ((bfd *abfd, arelent *reloc_entry, asymbol *symbol, PTR data,
329 +          asection *input_section, bfd *output_bfd, char **error_message));
330 +static bfd_reloc_status_type ubicom32_elf_relocate_hi16
331 +  PARAMS ((bfd *,  Elf_Internal_Rela *, bfd_byte *, bfd_vma));
332 +static bfd_reloc_status_type ubicom32_elf_relocate_lo16
333 +  PARAMS ((bfd *,  Elf_Internal_Rela *, bfd_byte *, bfd_vma));
334 +static bfd_reloc_status_type ubicom32_elf_relocate_hi24
335 +  PARAMS ((bfd *,  Elf_Internal_Rela *,   bfd_byte *, bfd_vma));
336 +static bfd_reloc_status_type ubicom32_elf_relocate_lo7_s
337 +  PARAMS ((bfd *,  Elf_Internal_Rela *,   bfd_byte *, bfd_vma));
338 +static bfd_reloc_status_type ubicom32_elf_relocate_lo7_2_s
339 +  PARAMS ((bfd *,  Elf_Internal_Rela *,   bfd_byte *, bfd_vma));
340 +static bfd_reloc_status_type ubicom32_elf_relocate_lo7_4_s
341 +  PARAMS ((bfd *,  Elf_Internal_Rela *,   bfd_byte *, bfd_vma));
342 +static bfd_reloc_status_type ubicom32_elf_relocate_lo7_d
343 +  PARAMS ((bfd *,  Elf_Internal_Rela *,   bfd_byte *, bfd_vma));
344 +static bfd_reloc_status_type ubicom32_elf_relocate_lo7_2_d
345 +  PARAMS ((bfd *,  Elf_Internal_Rela *,   bfd_byte *, bfd_vma));
346 +static bfd_reloc_status_type ubicom32_elf_relocate_lo7_4_d
347 +  PARAMS ((bfd *,  Elf_Internal_Rela *,   bfd_byte *, bfd_vma));
348 +static bfd_reloc_status_type ubicom32_elf_relocate_pcrel24
349 +  PARAMS ((bfd *, asection *, Elf_Internal_Rela *, bfd_byte *, bfd_vma));
350 +static bfd_reloc_status_type ubicom32_elf_relocate_lo_calli
351 +  PARAMS ((bfd *,  Elf_Internal_Rela *,   bfd_byte *, bfd_vma, int));
352 +
353 +static void ubicom32_info_to_howto_rela
354 +  PARAMS ((bfd *, arelent *, Elf_Internal_Rela *));
355 +
356 +static reloc_howto_type * ubicom32_reloc_type_lookup
357 +  PARAMS ((bfd *abfd, bfd_reloc_code_real_type code));
358 +
359 +static bfd_vma symbol_value
360 +  PARAMS ((bfd *, Elf_Internal_Rela *));
361 +static Elf_Internal_Shdr *file_symtab_hdr
362 +  PARAMS ((bfd *));
363 +static Elf_Internal_Sym *file_isymbuf
364 +  PARAMS ((bfd *));
365 +static Elf_Internal_Rela *section_relocs
366 +  PARAMS ((bfd *, asection *));
367 +static bfd_byte *section_contents
368 +  PARAMS ((bfd *, asection *));
369 +static bfd_boolean ubicom32_elf_relax_section
370 +  PARAMS ((bfd *, asection *, struct bfd_link_info *, bfd_boolean *));
371 +static bfd_boolean ubicom32_elf_relax_calli
372 +  PARAMS ((bfd *, asection *, bfd_boolean *));
373 +static bfd_boolean ubicom32_elf_relax_delete_bytes
374 +  PARAMS ((bfd *, asection *, bfd_vma, int));
375 +static void adjust_sec_relocations
376 +  PARAMS ((bfd *, asection *, asection *, bfd_vma, int));
377 +static void adjust_all_relocations
378 +  PARAMS ((bfd *, asection *, bfd_vma, int));
379 +
380 +static bfd_reloc_status_type ubicom32_final_link_relocate
381 +  PARAMS ((reloc_howto_type *, bfd *, asection *, bfd_byte *,
382 +          Elf_Internal_Rela *, bfd_vma));
383 +static bfd_boolean ubicom32_elf_relocate_section
384 +  PARAMS ((bfd *, struct bfd_link_info *, bfd *, asection *,
385 +          bfd_byte *, Elf_Internal_Rela *, Elf_Internal_Sym *,
386 +          asection **));
387 +
388 +static bfd_boolean ubicom32_elf_gc_sweep_hook
389 +  PARAMS ((bfd *, struct bfd_link_info *, asection *, const
390 +          Elf_Internal_Rela *));
391 +static asection * ubicom32_elf_gc_mark_hook
392 +  PARAMS ((asection *, struct bfd_link_info *, Elf_Internal_Rela *, struct
393 +          elf_link_hash_entry *, Elf_Internal_Sym *));
394 +static bfd_boolean ubicom32_elf_check_relocs
395 +  PARAMS ((bfd *, struct bfd_link_info *, asection *,
396 +          const Elf_Internal_Rela *));
397 +extern bfd_boolean ubicom32_elf_discard_info
398 +  PARAMS ((bfd *, struct elf_reloc_cookie *, struct bfd_link_info *));
399 +
400 +static bfd_boolean ubicom32_elf_object_p PARAMS ((bfd *));
401 +static bfd_boolean ubicom32_elf_set_private_flags PARAMS ((bfd *, flagword));
402 +static bfd_boolean ubicom32_elf_copy_private_bfd_data PARAMS ((bfd *, bfd *));
403 +static bfd_boolean ubicom32_elf_merge_private_bfd_data PARAMS ((bfd *, bfd *));
404 +static bfd_boolean ubicom32_elf_print_private_bfd_data PARAMS ((bfd *, PTR));
405 +
406 +//static unsigned long read_unsigned_leb128 (bfd *, char *, unsigned int *);
407 +
408 +//static long read_signed_leb128 (bfd *, char *, unsigned int *);
409 +
410 +/* read dwarf information from a buffer */
411 +
412 +#define UBICOM32_HOWTO(t,rs,s,bs,pr,bp,name,sm,dm) \
413 +    HOWTO(t,                   /* type */ \
414 +         rs,                   /* rightshift */ \
415 +         s,                    /* size (0 = byte, 1 = short, 2 = long) */ \
416 +         bs,                   /* bitsize */ \
417 +         pr,                   /* pc_relative */ \
418 +         bp,                   /* bitpos */ \
419 +         complain_overflow_bitfield,   /* complain_on_overflow */ \
420 +         ubicom32_elf_generic_reloc,   /* special_function */ \
421 +         name,                 /* name */ \
422 +         FALSE,                /* partial_inplace */ \
423 +         sm,                   /* src_mask */ \
424 +         dm,                   /* dst_mask */ \
425 +         pr)                   /* pcrel_offset */
426 +
427 +/* Special Note:  For addresses, we must always zero out the top byte of a
428 +                 address because the harvard address space is represented as
429 +                 a single virtual address space that uses the top byte to denote
430 +                 whether the address belongs in the data or program space.  This is
431 +                 done to accomodate GDB which cannot handle program and data addresses
432 +                 overlapping.                                                       */
433 +
434 +static reloc_howto_type ubicom32_elf_howto_table [] =
435 +{
436 +  /* This reloc does nothing.  */
437 +  UBICOM32_HOWTO (R_UBICOM32_NONE, 0,  2, 32, FALSE, 0, "R_UBICOM32_NONE", 0, 0),
438 +
439 +  /* A 16 bit absolute relocation.  */
440 +  UBICOM32_HOWTO (R_UBICOM32_16, 0, 1, 16, FALSE, 0,   "R_UBICOM32_16", 0, 0xffff),
441 +
442 +  /* A 32 bit absolute relocation.  Must zero top byte of virtual address. */
443 +  UBICOM32_HOWTO (R_UBICOM32_32, 0, 2, 32, FALSE, 0, "R_UBICOM32_32", 0, 0xffffffff),
444 +
445 +  /* A 16 bit indirect relocation, low 16 bits of 32 */
446 +  UBICOM32_HOWTO (R_UBICOM32_LO16, 0, 2, 16, FALSE, 0, "R_UBICOM32_LO16", 0x0, 0x0000ffff),
447 +
448 +  /* A 16 bit indirect relocation, high 16 bits of 32 - must zero top byte of virtual address */
449 +  UBICOM32_HOWTO (R_UBICOM32_HI16, 0, 2, 16, FALSE, 0, "R_UBICOM32_HI16", 0x0, 0x0000ffff),
450 +
451 +  /* A 21 bit relative relocation.  */
452 +  UBICOM32_HOWTO (R_UBICOM32_21_PCREL, 2, 2, 21, TRUE, 0, "R_UBICOM32_21_PCREL", 0x0, 0x001fffff),
453 +
454 +  /* A 24 bit relative relocation.  */
455 +  UBICOM32_HOWTO (R_UBICOM32_24_PCREL, 2, 2, 24, TRUE, 0, "R_UBICOM32_24_PCREL", 0x0, 0x071fffff),
456 +
457 +  /* A 24 bit indirect relocation, bits 31:7 - assume top byte zero. */
458 +  UBICOM32_HOWTO (R_UBICOM32_HI24, 7, 2, 24, FALSE, 0, "R_UBICOM32_HI24", 0x0, 0x0001ffff),
459 +
460 +  /* A source operand low 7 bit indirect relocation. */
461 +  UBICOM32_HOWTO (R_UBICOM32_LO7_S, 0, 2, 7, FALSE, 0, "R_UBICOM32_LO7_S", 0x0, 0x0000031f),
462 +
463 +  /* A source operand low 7 bit .2 insn indirect relocation. */
464 +  UBICOM32_HOWTO (R_UBICOM32_LO7_2_S, 1, 2, 7, FALSE, 0, "R_UBICOM32_LO7_2_S", 0x0, 0x0000031f),
465 +
466 +  /* A source operand low 7 bit .4 insn indirect relocation. */
467 +  UBICOM32_HOWTO (R_UBICOM32_LO7_4_S, 2, 2, 7, FALSE, 0, "R_UBICOM32_LO7_4_S", 0x0, 0x0000031f),
468 +
469 +  /* A destination operand low 7 bit indirect relocation. */
470 +  UBICOM32_HOWTO (R_UBICOM32_LO7_D, 0, 2, 7, FALSE, 0, "R_UBICOM32_LO7_D", 0x0, 0x031f0000),
471 +
472 +  /* A destination operand low 7 bit .2 insn indirect relocation. */
473 +  UBICOM32_HOWTO (R_UBICOM32_LO7_2_D, 1, 2, 7, FALSE, 0, "R_UBICOM32_LO7_2_D", 0x0, 0x031f0000),
474 +
475 +  /* A destination operand low 7 bit .2 insn indirect relocation. */
476 +  UBICOM32_HOWTO (R_UBICOM32_LO7_4_D, 2, 2, 7, FALSE, 0, "R_UBICOM32_LO7_4_D", 0x0, 0x031f0000),
477 +
478 +  /* A 32 bit absolute relocation in debug section.  Must retain top byte of virtual address. */
479 +  UBICOM32_HOWTO (R_UBICOM32_32_HARVARD, 0, 2, 32, FALSE, 0, "R_UBICOM32_32_HARVARD", 0, 0xffffffff),
480 +
481 +  /* A calli offset operand low 7 bit .4 insn indirect relocation. */
482 +  UBICOM32_HOWTO (R_UBICOM32_LO7_CALLI, 2, 2, 7, FALSE, 0, "R_UBICOM32_LO7_CALLI", 0x0, 0x071f071f),
483 +
484 +  /* A calli offset operand low 18 bit .4 insn indirect relocation. */
485 +  UBICOM32_HOWTO (R_UBICOM32_LO16_CALLI, 2, 2, 16, FALSE, 0, "R_UBICOM32_LO16_CALLI", 0x0, 0x071f071f),
486 +
487 +  /* A 24 bit indirect relocation, bits 31:7 - assume top byte zero. */
488 +  UBICOM32_HOWTO (R_UBICOM32_GOT_HI24, 7, 2, 24, FALSE, 0, "R_UBICOM32_GOT_HI24", 0x0, 0x0001ffff),
489 +
490 +  /* A source operand low 7 bit indirect relocation. */
491 +  UBICOM32_HOWTO (R_UBICOM32_GOT_LO7_S, 0, 2, 7, FALSE, 0, "R_UBICOM32_GOT_LO7_S", 0x0, 0x0000031f),
492 +
493 +  /* A source operand low 7 bit .2 insn indirect relocation. */
494 +  UBICOM32_HOWTO (R_UBICOM32_GOT_LO7_2_S, 1, 2, 7, FALSE, 0, "R_UBICOM32_GOT_LO7_2_S", 0x0, 0x0000031f),
495 +
496 +  /* A source operand low 7 bit .4 insn indirect relocation. */
497 +  UBICOM32_HOWTO (R_UBICOM32_GOT_LO7_4_S, 2, 2, 7, FALSE, 0, "R_UBICOM32_GOT_LO7_4_S", 0x0, 0x0000031f),
498 +
499 +  /* A destination operand low 7 bit indirect relocation. */
500 +  UBICOM32_HOWTO (R_UBICOM32_GOT_LO7_D, 0, 2, 7, FALSE, 0, "R_UBICOM32_GOT_LO7_D", 0x0, 0x031f0000),
501 +
502 +  /* A destination operand low 7 bit .2 insn indirect relocation. */
503 +  UBICOM32_HOWTO (R_UBICOM32_GOT_LO7_2_D, 1, 2, 7, FALSE, 0, "R_UBICOM32_GOT_LO7_2_D", 0x0, 0x031f0000),
504 +
505 +  /* A destination operand low 7 bit .2 insn indirect relocation. */
506 +  UBICOM32_HOWTO (R_UBICOM32_GOT_LO7_4_D, 2, 2, 7, FALSE, 0, "R_UBICOM32_GOT_LO7_4_D", 0x0, 0x031f0000),
507 +
508 +  /* A 24 bit indirect relocation, bits 31:7 - assume top byte zero. */
509 +  UBICOM32_HOWTO (R_UBICOM32_FUNCDESC_GOT_HI24, 7, 2, 24, FALSE, 0, "R_UBICOM32_FUNCDESC_GOT_HI24", 0x0, 0x0001ffff),
510 +
511 +  /* A source operand low 7 bit indirect relocation. */
512 +  UBICOM32_HOWTO (R_UBICOM32_FUNCDESC_GOT_LO7_S, 0, 2, 7, FALSE, 0, "R_UBICOM32_FUNCDESC_GOT_LO7_S", 0x0, 0x0000031f),
513 +
514 +  /* A source operand low 7 bit .2 insn indirect relocation. */
515 +  UBICOM32_HOWTO (R_UBICOM32_FUNCDESC_GOT_LO7_2_S, 1, 2, 7, FALSE, 0, "R_UBICOM32_FUNCDESC_GOT_LO7_2_S", 0x0, 0x0000031f),
516 +
517 +  /* A source operand low 7 bit .4 insn indirect relocation. */
518 +  UBICOM32_HOWTO (R_UBICOM32_FUNCDESC_GOT_LO7_4_S, 2, 2, 7, FALSE, 0, "R_UBICOM32_FUNCDESC_GOT_LO7_4_S", 0x0, 0x0000031f),
519 +
520 +  /* A destination operand low 7 bit indirect relocation. */
521 +  UBICOM32_HOWTO (R_UBICOM32_FUNCDESC_GOT_LO7_D, 0, 2, 7, FALSE, 0, "R_UBICOM32_FUNCDESC_GOT_LO7_D", 0x0, 0x031f0000),
522 +
523 +  /* A destination operand low 7 bit .2 insn indirect relocation. */
524 +  UBICOM32_HOWTO (R_UBICOM32_FUNCDESC_GOT_LO7_2_D, 1, 2, 7, FALSE, 0, "R_UBICOM32_FUNCDESC_GOT_LO7_2_D", 0x0, 0x031f0000),
525 +
526 +  /* A destination operand low 7 bit .2 insn indirect relocation. */
527 +  UBICOM32_HOWTO (R_UBICOM32_FUNCDESC_GOT_LO7_4_D, 2, 2, 7, FALSE, 0, "R_UBICOM32_FUNCDESC_GOT_LO7_4_D", 0x0, 0x031f0000),
528 +
529 +  /* A calli offset operand low 7 bit .4 insn indirect relocation. */
530 +  UBICOM32_HOWTO (R_UBICOM32_GOT_LO7_CALLI, 2, 2, 7, FALSE, 0, "R_UBICOM32_GOT_LO7_CALLI", 0x0, 0x071f071f),
531 +
532 +  /* A calli offset operand low 7 bit .4 insn indirect relocation. */
533 +  UBICOM32_HOWTO (R_UBICOM32_FUNCDESC_GOT_LO7_CALLI, 2, 2, 7, FALSE, 0, "R_UBICOM32_FUNCDESC_GOT_LO7_CALLI", 0x0, 0x071f071f),
534 +
535 +  /* A 32 bit absolute relocation.  Must zero top byte of virtual address. */
536 +  UBICOM32_HOWTO (R_UBICOM32_FUNCDESC_VALUE, 0, 2, 32, FALSE, 0, "R_UBICOM32_FUNCDESC_VALUE", 0, 0xffffffff),
537 +
538 +  /* A 32 bit absolute relocation.  Must zero top byte of virtual address. */
539 +  UBICOM32_HOWTO (R_UBICOM32_FUNCDESC, 0, 2, 32, FALSE, 0, "R_UBICOM32_FUNCDESC", 0, 0xffffffff),
540 +
541 +  /* A 16 bit absolute relocation.  */
542 +  UBICOM32_HOWTO (R_UBICOM32_GOTOFFSET_LO, 0, 1, 16, FALSE, 0, "R_UBICOM32_GOTOFFSET_LO", 0, 0xffff),
543 +
544 +  /* A 16 bit absolute relocation.  */
545 +  UBICOM32_HOWTO (R_UBICOM32_GOTOFFSET_HI, 0, 1, 16, FALSE, 0, "R_UBICOM32_GOTOFFSET_HI", 0, 0xffff),
546 +
547 +  /* A 16 bit absolute relocation.  */
548 +  UBICOM32_HOWTO (R_UBICOM32_FUNCDESC_GOTOFFSET_LO, 0, 1, 16, FALSE, 0,        "R_UBICOM32_FUNCDESC_GOTOFFSET_LO", 0, 0xffff),
549 +
550 +  /* A 16 bit absolute relocation.  */
551 +  UBICOM32_HOWTO (R_UBICOM32_FUNCDESC_GOTOFFSET_HI, 0, 1, 16, FALSE, 0,        "R_UBICOM32_FUNCDESC_GOTOFFSET_HI", 0, 0xffff),
552 +};
553 +
554 +/* GNU extension to record C++ vtable hierarchy */
555 +static reloc_howto_type ubicom32_elf_vtinherit_howto =
556 +  HOWTO (R_UBICOM32_GNU_VTINHERIT,   /* type */
557 +        0,                     /* rightshift */
558 +        2,                     /* size (0 = byte, 1 = short, 2 = long) */
559 +        0,                     /* bitsize */
560 +        FALSE,                 /* pc_relative */
561 +        0,                     /* bitpos */
562 +        complain_overflow_dont, /* complain_on_overflow */
563 +        NULL,                  /* special_function */
564 +        "R_UBICOM32_GNU_VTINHERIT", /* name */
565 +        FALSE,                 /* partial_inplace */
566 +        0,                     /* src_mask */
567 +        0,                     /* dst_mask */
568 +        FALSE);                /* pcrel_offset */
569 +
570 +  /* GNU extension to record C++ vtable member usage */
571 +static reloc_howto_type ubicom32_elf_vtentry_howto =
572 +  HOWTO (R_UBICOM32_GNU_VTENTRY,     /* type */
573 +        0,                     /* rightshift */
574 +        2,                     /* size (0 = byte, 1 = short, 2 = long) */
575 +        0,                     /* bitsize */
576 +        FALSE,                 /* pc_relative */
577 +        0,                     /* bitpos */
578 +        complain_overflow_dont, /* complain_on_overflow */
579 +        _bfd_elf_rel_vtable_reloc_fn,  /* special_function */
580 +        "R_UBICOM32_GNU_VTENTRY",   /* name */
581 +        FALSE,                 /* partial_inplace */
582 +        0,                     /* src_mask */
583 +        0,                     /* dst_mask */
584 +        FALSE);                /* pcrel_offset */
585 +
586 +extern const bfd_target bfd_elf32_ubicom32fdpic_vec;
587 +#define IS_FDPIC(bfd) ((bfd)->xvec == &bfd_elf32_ubicom32fdpic_vec)
588 +\f
589 +/* Relocation helpers */
590 +bfd_reloc_status_type
591 +ubicom32_elf_generic_reloc (abfd,
592 +                           reloc_entry,
593 +                           symbol,
594 +                           data,
595 +                           input_section,
596 +                           output_bfd,
597 +                           error_message)
598 +     bfd *abfd ATTRIBUTE_UNUSED;
599 +     arelent *reloc_entry;
600 +     asymbol *symbol;
601 +     PTR data ATTRIBUTE_UNUSED;
602 +     asection *input_section;
603 +     bfd *output_bfd;
604 +     char **error_message ATTRIBUTE_UNUSED;
605 +{
606 +  if (output_bfd != (bfd *) NULL
607 +      && (symbol->flags & BSF_SECTION_SYM) == 0
608 +      && (! reloc_entry->howto->partial_inplace
609 +         || reloc_entry->addend == 0))
610 +    {
611 +      reloc_entry->address += input_section->output_offset;
612 +      symbol = *reloc_entry->sym_ptr_ptr;
613 +
614 +      if((symbol->flags & BSF_OBJECT) == 0)
615 +       {
616 +         reloc_entry->addend -= symbol->value;
617 +       }
618 +      return bfd_reloc_ok;
619 +    }
620 +
621 +  return bfd_reloc_continue;
622 +}
623 +
624 +bfd_reloc_status_type
625 +ubicom32_elf_relocate_hi16 (input_bfd, relhi, contents, value)
626 +     bfd *input_bfd;
627 +     Elf_Internal_Rela *relhi;
628 +     bfd_byte *contents;
629 +     bfd_vma value;
630 +{
631 +  bfd_vma insn;
632 +
633 +  insn = bfd_get_32 (input_bfd, contents + relhi->r_offset);
634 +
635 +  value += relhi->r_addend;
636 +  value >>= 16;
637 +  value &= 0xffff;  /* take off top byte of virtual address */
638 +  insn = ((insn & ~0xFFFF) | value);
639 +
640 +  bfd_put_32 (input_bfd, insn, contents + relhi->r_offset);
641 +  return bfd_reloc_ok;
642 +}
643 +
644 +bfd_reloc_status_type
645 +ubicom32_elf_relocate_lo16 (input_bfd, relhi, contents, value)
646 +     bfd *input_bfd;
647 +     Elf_Internal_Rela *relhi;
648 +     bfd_byte *contents;
649 +     bfd_vma value;
650 +{
651 +  bfd_vma insn;
652 +
653 +  insn = bfd_get_32 (input_bfd, contents + relhi->r_offset);
654 +
655 +  value += relhi->r_addend;
656 +  value &= 0xFFFF;
657 +  insn = ((insn & ~0xFFFF) | value);
658 +
659 +  bfd_put_32 (input_bfd, insn, contents + relhi->r_offset);
660 +  return bfd_reloc_ok;
661 +}
662 +
663 +bfd_reloc_status_type
664 +ubicom32_elf_relocate_hi24 (input_bfd, relhi, contents, value)
665 +     bfd *input_bfd;
666 +     Elf_Internal_Rela *relhi;
667 +     bfd_byte *contents;
668 +     bfd_vma value;
669 +{
670 +  bfd_vma insn;
671 +
672 +  insn = bfd_get_32 (input_bfd, contents + relhi->r_offset);
673 +
674 +  value += relhi->r_addend;
675 +  if (value & 0x80000000) {
676 +    fprintf (stderr,"@@@: You are trying load the address of something at %08lx\n  This is >= 0x80000000 and the moveai instruction does not support it!\n",value);
677 +  }
678 +  value &= 0x7fffffff; /* zero off top bit of virtual address */
679 +  value >>= 7;
680 +  insn = (insn & ~0x071FFFFF);
681 +
682 +  insn |= (value & 0x1FFFFF);
683 +  insn |= (value & 0xe00000) << 3;
684 +
685 +  bfd_put_32 (input_bfd, insn, contents + relhi->r_offset);
686 +  return bfd_reloc_ok;
687 +}
688 +
689 +bfd_reloc_status_type
690 +ubicom32_elf_relocate_lo7_s (input_bfd, relhi, contents, value)
691 +     bfd *input_bfd;
692 +     Elf_Internal_Rela *relhi;
693 +     bfd_byte *contents;
694 +     bfd_vma value;
695 +{
696 +  bfd_vma insn;
697 +  bfd_vma top;
698 +  bfd_vma bottom;
699 +
700 +  insn = bfd_get_32 (input_bfd, contents + relhi->r_offset);
701 +
702 +  value += relhi->r_addend;
703 +  value &= 0x7f;
704 +
705 +  /* must split up value into top 2 bits and bottom 5 bits */
706 +  top = value >> 5;
707 +  bottom = value & 0x1f;
708 +  insn = ((insn & ~0x31f) | (top << 8) | bottom);
709 +
710 +  bfd_put_32 (input_bfd, insn, contents + relhi->r_offset);
711 +  return bfd_reloc_ok;
712 +}
713 +
714 +bfd_reloc_status_type
715 +ubicom32_elf_relocate_lo7_2_s (input_bfd, relhi, contents, value)
716 +     bfd *input_bfd;
717 +     Elf_Internal_Rela *relhi;
718 +     bfd_byte *contents;
719 +     bfd_vma value;
720 +{
721 +  bfd_vma insn;
722 +  bfd_vma top;
723 +  bfd_vma bottom;
724 +
725 +  insn = bfd_get_32 (input_bfd, contents + relhi->r_offset);
726 +
727 +  value += relhi->r_addend;
728 +  value &= 0x7f;
729 +  value >>= 1;  /* must shift by 1 because this is .2 insn */
730 +
731 +  /* must split up value into top 2 bits and bottom 5 bits */
732 +  top = value >> 5;
733 +  bottom = value & 0x1f;
734 +  insn = ((insn & ~0x31f) | (top << 8) | bottom);
735 +
736 +  bfd_put_32 (input_bfd, insn, contents + relhi->r_offset);
737 +  return bfd_reloc_ok;
738 +}
739 +
740 +bfd_reloc_status_type
741 +ubicom32_elf_relocate_lo7_4_s (input_bfd, relhi, contents, value)
742 +     bfd *input_bfd;
743 +     Elf_Internal_Rela *relhi;
744 +     bfd_byte *contents;
745 +     bfd_vma value;
746 +{
747 +  bfd_vma insn;
748 +  bfd_vma top;
749 +  bfd_vma bottom;
750 +
751 +  insn = bfd_get_32 (input_bfd, contents + relhi->r_offset);
752 +
753 +  value += relhi->r_addend;
754 +  value &= 0x7f;
755 +  value >>= 2;  /* must shift by 1 because this is .4 insn */
756 +
757 +  /* must split up value into top 2 bits and bottom 5 bits */
758 +  top = value >> 5;
759 +  bottom = value & 0x1f;
760 +  insn = ((insn & ~0x31f) | (top << 8) | bottom);
761 +
762 +  bfd_put_32 (input_bfd, insn, contents + relhi->r_offset);
763 +  return bfd_reloc_ok;
764 +}
765 +
766 +bfd_reloc_status_type
767 +ubicom32_elf_relocate_lo7_d (input_bfd, relhi, contents, value)
768 +     bfd *input_bfd;
769 +     Elf_Internal_Rela *relhi;
770 +     bfd_byte *contents;
771 +     bfd_vma value;
772 +{
773 +  bfd_vma insn;
774 +  bfd_vma top;
775 +  bfd_vma bottom;
776 +
777 +  insn = bfd_get_32 (input_bfd, contents + relhi->r_offset);
778 +
779 +  value += relhi->r_addend;
780 +  value &= 0x7f;
781 +
782 +  /* must split up value into top 2 bits and bottom 5 bits */
783 +  top = value >> 5;
784 +  bottom = value & 0x1f;
785 +  insn = ((insn & ~0x031f0000) | (top << 24) | (bottom << 16));
786 +
787 +  bfd_put_32 (input_bfd, insn, contents + relhi->r_offset);
788 +  return bfd_reloc_ok;
789 +}
790 +
791 +bfd_reloc_status_type
792 +ubicom32_elf_relocate_lo7_2_d (input_bfd, relhi, contents, value)
793 +     bfd *input_bfd;
794 +     Elf_Internal_Rela *relhi;
795 +     bfd_byte *contents;
796 +     bfd_vma value;
797 +{
798 +  bfd_vma insn;
799 +  bfd_vma top;
800 +  bfd_vma bottom;
801 +
802 +  insn = bfd_get_32 (input_bfd, contents + relhi->r_offset);
803 +
804 +  value += relhi->r_addend;
805 +  value &= 0x7f;
806 +  value >>= 1; /* must shift by 1 because this is for a .2 insn */
807 +
808 +  /* must split up value into top 2 bits and bottom 5 bits */
809 +  top = value >> 5;
810 +  bottom = value & 0x1f;
811 +  insn = ((insn & ~0x031f0000) | (top << 24) | (bottom << 16));
812 +
813 +  bfd_put_32 (input_bfd, insn, contents + relhi->r_offset);
814 +  return bfd_reloc_ok;
815 +}
816 +
817 +bfd_reloc_status_type
818 +ubicom32_elf_relocate_lo7_4_d (input_bfd, relhi, contents, value)
819 +     bfd *input_bfd;
820 +     Elf_Internal_Rela *relhi;
821 +     bfd_byte *contents;
822 +     bfd_vma value;
823 +{
824 +  bfd_vma insn;
825 +  bfd_vma top;
826 +  bfd_vma bottom;
827 +
828 +  insn = bfd_get_32 (input_bfd, contents + relhi->r_offset);
829 +
830 +  value += relhi->r_addend;
831 +  value &= 0x7f;
832 +  value >>= 2; /* must shift by 2 because this is for a .4 insn */
833 +
834 +  /* must split up value into top 2 bits and bottom 5 bits */
835 +  top = value >> 5;
836 +  bottom = value & 0x1f;
837 +  insn = ((insn & ~0x031f0000) | (top << 24) | (bottom << 16));
838 +
839 +  bfd_put_32 (input_bfd, insn, contents + relhi->r_offset);
840 +  return bfd_reloc_ok;
841 +}
842 +
843 +/* Perform the relocation for call instructions */
844 +static bfd_reloc_status_type
845 +ubicom32_elf_relocate_pcrel24 (input_bfd, input_section, rello, contents, value)
846 +     bfd *input_bfd;
847 +     asection *input_section;
848 +     Elf_Internal_Rela *rello;
849 +     bfd_byte *contents;
850 +     bfd_vma value;
851 +{
852 +  bfd_vma insn;
853 +  bfd_vma value_top;
854 +  bfd_vma value_bottom;
855 +
856 +  /* Grab the instruction */
857 +  insn = bfd_get_32 (input_bfd, contents + rello->r_offset);
858 +
859 +  value -= input_section->output_section->vma + input_section->output_offset;
860 +  value -= rello->r_offset;
861 +  value += rello->r_addend;
862 +
863 +  /* insn uses bottom 24 bits of relocation value times 4 */
864 +  if (value & 0x03)
865 +    return bfd_reloc_dangerous;
866 +
867 +  value = (value & 0x3ffffff) >> 2;
868 +
869 +  if ((long) value > 0xffffff)
870 +    return bfd_reloc_overflow;
871 +
872 +  value_top = (value >> 21) << 24;
873 +  value_bottom = value & 0x1fffff;
874 +
875 +  insn = insn & 0xf8e00000;
876 +  insn = insn | value_top | value_bottom;
877 +
878 +  bfd_put_32 (input_bfd, insn, contents + rello->r_offset);
879 +
880 +  return bfd_reloc_ok;
881 +}
882 +
883 +static bfd_reloc_status_type
884 +ubicom32_elf_relocate_gotoffset_lo (input_bfd, input_section, rello, contents, value)
885 +     bfd *input_bfd;
886 +     asection *input_section;
887 +     Elf_Internal_Rela *rello;
888 +     bfd_byte *contents;
889 +     bfd_vma value;
890 +{
891 +  bfd_vma insn;
892 +
893 +  /* Grab the instruction */
894 +  insn = bfd_get_32 (input_bfd, contents + rello->r_offset);
895 +
896 +  /* Truncte to 16 and store. */
897 +  value &= 0xffff;
898 +
899 +  insn = (insn & 0xffff0000) | value;
900 +
901 +  /* output it. */
902 +  bfd_put_32 (input_bfd, insn, contents + rello->r_offset);
903 +}
904 +
905 +static bfd_reloc_status_type
906 +ubicom32_elf_relocate_funcdesc_gotoffset_lo (input_bfd, input_section, rello, contents, value)
907 +     bfd *input_bfd;
908 +     asection *input_section;
909 +     Elf_Internal_Rela *rello;
910 +     bfd_byte *contents;
911 +     bfd_vma value;
912 +{
913 +  bfd_vma insn;
914 +
915 +  /* Grab the instruction */
916 +  insn = bfd_get_32 (input_bfd, contents + rello->r_offset);
917 +
918 +  /* Truncte to 16 and store. */
919 +  value &= 0xffff;
920 +
921 +  insn = (insn & 0xffff0000) | value;
922 +
923 +  /* output it. */
924 +  bfd_put_32 (input_bfd, insn, contents + rello->r_offset);
925 +}
926 +
927 +static bfd_reloc_status_type
928 +ubicom32_elf_relocate_funcdesc (input_bfd, input_section, rello, contents, value)
929 +     bfd *input_bfd;
930 +     asection *input_section;
931 +     Elf_Internal_Rela *rello;
932 +     bfd_byte *contents;
933 +     bfd_vma value;
934 +{
935 +  bfd_vma insn;
936 +
937 +  /* Grab the instruction */
938 +  insn = bfd_get_32 (input_bfd, contents + rello->r_offset);
939 +
940 +  /* Truncte to 16 and store. */
941 +  value &= 0xffff;
942 +
943 +  insn = (insn & 0xffff0000) | value;
944 +
945 +  /* output it. */
946 +  bfd_put_32 (input_bfd, insn, contents + rello->r_offset);
947 +}
948 +
949 +bfd_reloc_status_type
950 +ubicom32_elf_relocate_lo_calli (input_bfd, relhi, contents, value, bits)
951 +     bfd *input_bfd;
952 +     Elf_Internal_Rela *relhi;
953 +     bfd_byte *contents;
954 +     bfd_vma value;
955 +     int bits;
956 +{
957 +  bfd_vma insn;
958 +
959 +  insn = bfd_get_32 (input_bfd, contents + relhi->r_offset);
960 +
961 +  value += relhi->r_addend;
962 +  value &= (1 << bits) - 1;
963 +  value >>= 2;  /* must shift by 2 because this is .4 insn */
964 +
965 +  /* must split up value into top 2 bits and bottom 5 bits */
966 +  insn &= ~0x071f071f;
967 +  insn |= (value & 0x1f) << 0;
968 +  value >>= 5;
969 +  insn |= (value & 0x07) << 8;
970 +  value >>= 3;
971 +  insn |= (value & 0x1f) << 16;
972 +  value >>= 5;
973 +  insn |= (value & 0x07) << 24;
974 +
975 +  bfd_put_32 (input_bfd, insn, contents + relhi->r_offset);
976 +  return bfd_reloc_ok;
977 +}
978 +
979 +\f
980 +/* Set the howto pointer for a UBICOM32 ELF reloc.  */
981 +
982 +static void
983 +ubicom32_info_to_howto_rela (abfd, cache_ptr, dst)
984 +     bfd * abfd ATTRIBUTE_UNUSED;
985 +     arelent * cache_ptr;
986 +     Elf_Internal_Rela * dst;
987 +{
988 +  unsigned int r_type;
989 +
990 +  r_type = ELF32_R_TYPE (dst->r_info);
991 +  switch (r_type)
992 +    {
993 +    case R_UBICOM32_GNU_VTINHERIT:
994 +      cache_ptr->howto = &ubicom32_elf_vtinherit_howto;
995 +      break;
996 +
997 +    case R_UBICOM32_GNU_VTENTRY:
998 +      cache_ptr->howto = &ubicom32_elf_vtentry_howto;
999 +      break;
1000 +
1001 +    default:
1002 +      cache_ptr->howto = &ubicom32_elf_howto_table[r_type];
1003 +      break;
1004 +    }
1005 +}
1006 +
1007 +\f
1008 +static reloc_howto_type *
1009 +ubicom32_reloc_type_lookup (abfd, code)
1010 +     bfd * abfd ATTRIBUTE_UNUSED;
1011 +     bfd_reloc_code_real_type code;
1012 +{
1013 +  switch (code)
1014 +    {
1015 +    case BFD_RELOC_NONE:
1016 +      return &ubicom32_elf_howto_table[(int)R_UBICOM32_NONE];
1017 +
1018 +    case BFD_RELOC_16:
1019 +      return &ubicom32_elf_howto_table[(int)R_UBICOM32_16];
1020 +
1021 +    case BFD_RELOC_32:
1022 +      return &ubicom32_elf_howto_table[(int)R_UBICOM32_32];
1023 +
1024 +    case BFD_RELOC_LO16:
1025 +      return &ubicom32_elf_howto_table[(int)R_UBICOM32_LO16];
1026 +
1027 +    case BFD_RELOC_HI16:
1028 +      return &ubicom32_elf_howto_table[(int)R_UBICOM32_HI16];
1029 +
1030 +    case BFD_RELOC_UBICOM32_HI24:
1031 +      return &ubicom32_elf_howto_table[(int)R_UBICOM32_HI24];
1032 +
1033 +    case BFD_RELOC_UBICOM32_LO7_S:
1034 +      return &ubicom32_elf_howto_table[(int)R_UBICOM32_LO7_S];
1035 +
1036 +    case BFD_RELOC_UBICOM32_LO7_2_S:
1037 +      return &ubicom32_elf_howto_table[(int)R_UBICOM32_LO7_2_S];
1038 +
1039 +    case BFD_RELOC_UBICOM32_LO7_4_S:
1040 +      return &ubicom32_elf_howto_table[(int)R_UBICOM32_LO7_4_S];
1041 +
1042 +    case BFD_RELOC_UBICOM32_LO7_D:
1043 +      return &ubicom32_elf_howto_table[(int)R_UBICOM32_LO7_D];
1044 +
1045 +    case BFD_RELOC_UBICOM32_LO7_2_D:
1046 +      return &ubicom32_elf_howto_table[(int)R_UBICOM32_LO7_2_D];
1047 +
1048 +    case BFD_RELOC_UBICOM32_LO7_4_D:
1049 +      return &ubicom32_elf_howto_table[(int)R_UBICOM32_LO7_4_D];
1050 +
1051 +    case BFD_RELOC_UBICOM32_21_PCREL:
1052 +      return &ubicom32_elf_howto_table[(int)R_UBICOM32_21_PCREL];
1053 +
1054 +    case BFD_RELOC_UBICOM32_24_PCREL:
1055 +      return &ubicom32_elf_howto_table[(int)R_UBICOM32_24_PCREL];
1056 +
1057 +    case BFD_RELOC_UBICOM32_GOT_HI24:
1058 +      return &ubicom32_elf_howto_table[(int)R_UBICOM32_GOT_HI24];
1059 +
1060 +    case BFD_RELOC_UBICOM32_GOT_LO7_S:
1061 +      return &ubicom32_elf_howto_table[(int)R_UBICOM32_GOT_LO7_S];
1062 +
1063 +    case BFD_RELOC_UBICOM32_GOT_LO7_2_S:
1064 +      return &ubicom32_elf_howto_table[(int)R_UBICOM32_GOT_LO7_2_S];
1065 +
1066 +    case BFD_RELOC_UBICOM32_GOT_LO7_4_S:
1067 +      return &ubicom32_elf_howto_table[(int)R_UBICOM32_GOT_LO7_4_S];
1068 +
1069 +    case BFD_RELOC_UBICOM32_GOT_LO7_D:
1070 +      return &ubicom32_elf_howto_table[(int)R_UBICOM32_GOT_LO7_D];
1071 +
1072 +    case BFD_RELOC_UBICOM32_GOT_LO7_2_D:
1073 +      return &ubicom32_elf_howto_table[(int)R_UBICOM32_GOT_LO7_2_D];
1074 +
1075 +    case BFD_RELOC_UBICOM32_GOT_LO7_4_D:
1076 +      return &ubicom32_elf_howto_table[(int)R_UBICOM32_GOT_LO7_4_D];
1077 +
1078 +    case BFD_RELOC_UBICOM32_FUNCDESC_GOT_HI24:
1079 +      return &ubicom32_elf_howto_table[(int)R_UBICOM32_FUNCDESC_GOT_HI24];
1080 +
1081 +    case BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_S:
1082 +      return &ubicom32_elf_howto_table[(int)R_UBICOM32_FUNCDESC_GOT_LO7_S];
1083 +
1084 +    case BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_2_S:
1085 +      return &ubicom32_elf_howto_table[(int)R_UBICOM32_FUNCDESC_GOT_LO7_2_S];
1086 +
1087 +    case BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_4_S:
1088 +      return &ubicom32_elf_howto_table[(int)R_UBICOM32_FUNCDESC_GOT_LO7_4_S];
1089 +
1090 +    case BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_D:
1091 +      return &ubicom32_elf_howto_table[(int)R_UBICOM32_FUNCDESC_GOT_LO7_D];
1092 +
1093 +    case BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_2_D:
1094 +      return &ubicom32_elf_howto_table[(int)R_UBICOM32_FUNCDESC_GOT_LO7_2_D];
1095 +
1096 +    case BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_4_D:
1097 +      return &ubicom32_elf_howto_table[(int)R_UBICOM32_FUNCDESC_GOT_LO7_4_D];
1098 +
1099 +    case BFD_RELOC_UBICOM32_LO7_CALLI:
1100 +      return &ubicom32_elf_howto_table[(int)R_UBICOM32_LO7_CALLI];
1101 +
1102 +    case BFD_RELOC_UBICOM32_GOT_LO7_CALLI:
1103 +      return &ubicom32_elf_howto_table[(int)R_UBICOM32_GOT_LO7_CALLI];
1104 +
1105 +    case BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_CALLI:
1106 +      return &ubicom32_elf_howto_table[(int)R_UBICOM32_FUNCDESC_GOT_LO7_CALLI];
1107 +
1108 +    case BFD_RELOC_UBICOM32_LO16_CALLI:
1109 +      return &ubicom32_elf_howto_table[(int)R_UBICOM32_LO16_CALLI];
1110 +
1111 +    case BFD_RELOC_UBICOM32_FUNCDESC_VALUE:
1112 +      return &ubicom32_elf_howto_table[(int)R_UBICOM32_FUNCDESC_VALUE];
1113 +
1114 +    case BFD_RELOC_UBICOM32_FUNCDESC:
1115 +      return &ubicom32_elf_howto_table[(int)R_UBICOM32_FUNCDESC];
1116 +
1117 +    case BFD_RELOC_UBICOM32_GOTOFFSET_LO:
1118 +      return &ubicom32_elf_howto_table[(int)R_UBICOM32_GOTOFFSET_LO];
1119 +
1120 +    case BFD_RELOC_UBICOM32_GOTOFFSET_HI:
1121 +      return &ubicom32_elf_howto_table[(int)R_UBICOM32_GOTOFFSET_HI];
1122 +
1123 +    case BFD_RELOC_UBICOM32_FUNCDESC_GOTOFFSET_LO:
1124 +      return &ubicom32_elf_howto_table[(int)R_UBICOM32_FUNCDESC_GOTOFFSET_LO];
1125 +
1126 +    case BFD_RELOC_UBICOM32_FUNCDESC_GOTOFFSET_HI:
1127 +      return &ubicom32_elf_howto_table[(int)R_UBICOM32_FUNCDESC_GOTOFFSET_HI];
1128 +
1129 +    case BFD_RELOC_VTABLE_INHERIT:
1130 +      return &ubicom32_elf_vtinherit_howto;
1131 +
1132 +    case BFD_RELOC_VTABLE_ENTRY:
1133 +      return &ubicom32_elf_vtentry_howto;
1134 +
1135 +    default:
1136 +      /* Pacify gcc -Wall. */
1137 +      return NULL;
1138 +    }
1139 +
1140 +  return NULL;
1141 +}
1142 +
1143 +static reloc_howto_type *
1144 +ubicom32_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
1145 +                           const char *r_name)
1146 +{
1147 +  unsigned int i;
1148 +
1149 +  for (i = 0;
1150 +       i < (sizeof (ubicom32_elf_howto_table)
1151 +           / sizeof (ubicom32_elf_howto_table[0]));
1152 +       i++)
1153 +    if (ubicom32_elf_howto_table[i].name != NULL
1154 +       && strcasecmp (ubicom32_elf_howto_table[i].name, r_name) == 0)
1155 +      return &ubicom32_elf_howto_table[i];
1156 +
1157 +  return NULL;
1158 +}
1159 +
1160 +/* Return the value of the symbol associated with the relocation IREL.  */
1161 +
1162 +static bfd_vma
1163 +symbol_value (abfd, irel)
1164 +     bfd *abfd;
1165 +     Elf_Internal_Rela *irel;
1166 +{
1167 +  Elf_Internal_Shdr *symtab_hdr = file_symtab_hdr (abfd);
1168 +  Elf_Internal_Sym *isymbuf = file_isymbuf (abfd);
1169 +
1170 +  if (ELF32_R_SYM (irel->r_info) < symtab_hdr->sh_info)
1171 +    {
1172 +      Elf_Internal_Sym *isym;
1173 +      asection *sym_sec;
1174 +
1175 +      isym = isymbuf + ELF32_R_SYM (irel->r_info);
1176 +      if (isym->st_shndx == SHN_UNDEF)
1177 +       sym_sec = bfd_und_section_ptr;
1178 +      else if (isym->st_shndx == SHN_ABS)
1179 +       sym_sec = bfd_abs_section_ptr;
1180 +      else if (isym->st_shndx == SHN_COMMON)
1181 +       sym_sec = bfd_com_section_ptr;
1182 +      else
1183 +       sym_sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
1184 +
1185 +      return isym->st_value + BASEADDR (sym_sec);
1186 +    }
1187 +  else
1188 +    {
1189 +      unsigned long indx;
1190 +      struct elf_link_hash_entry *h;
1191 +
1192 +      indx = ELF32_R_SYM (irel->r_info) - symtab_hdr->sh_info;
1193 +      h = elf_sym_hashes (abfd)[indx];
1194 +      BFD_ASSERT (h != NULL);
1195 +
1196 +      if (h->root.type != bfd_link_hash_defined
1197 +         && h->root.type != bfd_link_hash_defweak)
1198 +       return UNDEFINED_SYMBOL;
1199 +
1200 +      return (h->root.u.def.value + BASEADDR (h->root.u.def.section));
1201 +    }
1202 +}
1203 +
1204 +
1205 +static Elf_Internal_Shdr *
1206 +file_symtab_hdr (abfd)
1207 +     bfd *abfd;
1208 +{
1209 +  return &elf_tdata (abfd)->symtab_hdr;
1210 +}
1211 +
1212 +static Elf_Internal_Sym *
1213 +file_isymbuf (abfd)
1214 +     bfd *abfd;
1215 +{
1216 +  Elf_Internal_Shdr *symtab_hdr;
1217 +
1218 +  symtab_hdr = file_symtab_hdr (abfd);
1219 +  if (symtab_hdr->sh_info == 0)
1220 +    return NULL;
1221 +
1222 +  if (symtab_hdr->contents == NULL)
1223 +    {
1224 +      Elf_Internal_Sym * contents = bfd_elf_get_elf_syms (abfd, symtab_hdr, symtab_hdr->sh_info, 0,
1225 +                                                         NULL, NULL, NULL);
1226 +      symtab_hdr->contents = (unsigned char *) contents;
1227 +    }
1228 +
1229 +  return (Elf_Internal_Sym *) symtab_hdr->contents;
1230 +}
1231 +
1232 +static Elf_Internal_Rela *
1233 +section_relocs (abfd, sec)
1234 +     bfd *abfd;
1235 +     asection *sec;
1236 +{
1237 +  if ((sec->flags & SEC_RELOC) == 0)
1238 +    return NULL;
1239 +
1240 +  if (sec->reloc_count == 0)
1241 +    return NULL;
1242 +
1243 +  if (elf_section_data (sec)->relocs == NULL)
1244 +    elf_section_data (sec)->relocs =
1245 +      _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, 1);
1246 +
1247 +  return elf_section_data (sec)->relocs;
1248 +}
1249 +
1250 +static bfd_byte *
1251 +section_contents (abfd, sec)
1252 +     bfd *abfd;
1253 +     asection *sec;
1254 +{
1255 +  bfd_byte *contents;
1256 +
1257 +  sec->rawsize = sec->rawsize ? sec->rawsize: sec->size;
1258 +
1259 +  if (elf_section_data (sec)->this_hdr.contents)
1260 +    return elf_section_data (sec)->this_hdr.contents;
1261 +
1262 +  contents = (bfd_byte *) bfd_malloc (sec->rawsize);
1263 +  if (contents == NULL)
1264 +    return NULL;
1265 +
1266 +  if (! bfd_get_section_contents (abfd, sec, contents,
1267 +                                 (file_ptr) 0, sec->rawsize))
1268 +    {
1269 +      free (contents);
1270 +      return NULL;
1271 +    }
1272 +
1273 +  elf_section_data (sec)->this_hdr.contents = contents;
1274 +  return contents;
1275 +}
1276 +
1277 +/* This function handles relaxing for the ubicom32.
1278 +
1279 +   Principle: Start with the first page and remove page instructions that
1280 +   are not require on this first page. By removing page instructions more
1281 +   code will fit into this page - repeat until nothing more can be achieved
1282 +   for this page. Move on to the next page.
1283 +
1284 +   Processing the pages one at a time from the lowest page allows a removal
1285 +   only policy to be used - pages can be removed but are never reinserted.  */
1286 +
1287 +static bfd_boolean
1288 +ubicom32_elf_relax_section (abfd, sec, link_info, again)
1289 +     bfd *abfd;
1290 +     asection *sec;
1291 +     struct bfd_link_info *link_info;
1292 +     bfd_boolean *again;
1293 +{
1294 +  /* Assume nothing changes.  */
1295 +  *again = FALSE;
1296 +
1297 +  /* We don't have to do anything for a relocatable link,
1298 +     if this section does not have relocs, or if this is
1299 +     not a code section.  */
1300 +  if (link_info->relocatable
1301 +      || (sec->flags & SEC_RELOC) == 0
1302 +      || sec->reloc_count == 0
1303 +      || (sec->flags & SEC_CODE) == 0)
1304 +    return TRUE;
1305 +
1306 +  /* If this is the first time we have been called
1307 +      for this section, initialise the cooked size.
1308 +  if (sec->_cooked_size == 0)
1309 +    sec->_cooked_size = sec->rawsize;
1310 +  */
1311 +
1312 +  /* This is where all the relaxation actually get done.  */
1313 +  if (!ubicom32_elf_relax_calli (abfd, sec, again))
1314 +    return FALSE;
1315 +
1316 +  if (sec->rawsize != sec->size)
1317 +    sec->size = sec->rawsize;
1318 +
1319 +  /* Success!  */
1320 +  return TRUE;
1321 +}
1322 +
1323 +static bfd_boolean
1324 +ubicom32_elf_relax_calli (abfd, sec, again)
1325 +     bfd *abfd;
1326 +     asection *sec;
1327 +     bfd_boolean *again;
1328 +{
1329 +  bfd_byte *contents = section_contents (abfd, sec);
1330 +  Elf_Internal_Rela *irelbase = section_relocs (abfd, sec);
1331 +  Elf_Internal_Rela *irelend = irelbase + sec->reloc_count;
1332 +  Elf_Internal_Rela *irel_moveai = NULL;
1333 +  Elf_Internal_Rela *irel;
1334 +  unsigned long insn;
1335 +  bfd_vma symval;
1336 +  bfd_vma pc;
1337 +  bfd_vma dest;
1338 +  signed long offs;
1339 +
1340 +  /* Walk thru the section looking for relaxation opertunities.  */
1341 +  for (irel = irelbase; irel < irelend; irel++)
1342 +    {
1343 +      /* Remember last moveai instruction */
1344 +      if (ELF32_R_TYPE (irel->r_info) == (int) R_UBICOM32_HI24)
1345 +       {
1346 +         irel_moveai = irel;
1347 +         continue;
1348 +       }
1349 +
1350 +      /* Ignore non calli instructions */
1351 +      if (ELF32_R_TYPE (irel->r_info) != (int) R_UBICOM32_LO7_CALLI)
1352 +       continue;
1353 +
1354 +      /* calli instruction => verify it is a calli instruction
1355 +        using a5 with a 5 bit positive offset */
1356 +      insn = bfd_get_32 (abfd, (bfd_byte *)(contents + irel->r_offset));
1357 +      if ((insn & 0xffffffe0) != 0xf0a000a0)
1358 +       continue;
1359 +      symval = symbol_value (abfd, irel);
1360 +      if (symval == UNDEFINED_SYMBOL)
1361 +       continue;
1362 +      dest = symval + irel->r_addend;
1363 +
1364 +      /* Check proceeding instruction for a valid moveai */
1365 +      if (!irel_moveai)
1366 +       continue;
1367 +      if (irel_moveai->r_offset != (irel->r_offset - 4))
1368 +       continue;
1369 +      insn = bfd_get_32 (abfd, (bfd_byte *)(contents + irel_moveai->r_offset));
1370 +      if ((insn & 0xf8e00000) !=  0xe0a00000)
1371 +       continue;
1372 +      symval = symbol_value (abfd, irel_moveai);
1373 +      if (symval == UNDEFINED_SYMBOL)
1374 +       continue;
1375 +      symval += irel_moveai->r_addend;
1376 +      if (symval != dest)
1377 +       continue;
1378 +
1379 +      /* Check offset required */
1380 +      pc = BASEADDR (sec) + irel_moveai->r_offset;
1381 +      offs = dest - pc;
1382 +      if (offs > (UBICOM32_CALL_MAX_POS_OFFS + 4))
1383 +       continue;
1384 +      if (offs < UBICOM32_CALL_MAX_NEG_OFFS)
1385 +       continue;
1386 +
1387 +      /* Replace calli with a call instruction */
1388 +      irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info), R_UBICOM32_24_PCREL);
1389 +      bfd_put_32 (abfd, 0xd8a00000, contents + irel->r_offset);
1390 +
1391 +      /* Delete moveai instruction */
1392 +      irel_moveai->r_info = ELF32_R_INFO (ELF32_R_SYM (irel_moveai->r_info), R_UBICOM32_NONE);
1393 +      if (!ubicom32_elf_relax_delete_bytes (abfd, sec, irel_moveai->r_offset, 4))
1394 +       return FALSE;
1395 +
1396 +      /* Modified => will need to iterate relaxation again.  */
1397 +      *again = TRUE;
1398 +    }
1399 +
1400 +  return TRUE;
1401 +}
1402 +
1403 +/* Delete some bytes from a section while relaxing.  */
1404 +
1405 +static bfd_boolean
1406 +ubicom32_elf_relax_delete_bytes (abfd, sec, addr, count)
1407 +     bfd *abfd;
1408 +     asection *sec;
1409 +     bfd_vma addr;
1410 +     int count;
1411 +{
1412 +  bfd_byte *contents = elf_section_data (sec)->this_hdr.contents;
1413 +  bfd_vma endaddr = sec->rawsize;
1414 +
1415 +  /* Actually delete the bytes.  */
1416 +  memmove (contents + addr, contents + addr + count,
1417 +          endaddr - addr - count);
1418 +
1419 +  sec->rawsize -= count;
1420 +
1421 +  adjust_all_relocations (abfd, sec, addr + count, -count);
1422 +  return TRUE;
1423 +}
1424 +
1425 +/* Adjust all the relocations entries after adding or inserting instructions.  */
1426 +
1427 +static void
1428 +adjust_sec_relocations (abfd, sec_to_process, addr_sec, addr, count)
1429 +     bfd *abfd;
1430 +     asection *sec_to_process;
1431 +     asection *addr_sec;
1432 +     bfd_vma addr;
1433 +     int count;
1434 +{
1435 +  Elf_Internal_Shdr *symtab_hdr;
1436 +  Elf_Internal_Sym *isymbuf, *isym;
1437 +  Elf_Internal_Rela *irel, *irelend, *irelbase;
1438 +  unsigned int addr_shndx;
1439 +
1440 +  irelbase = section_relocs (abfd, sec_to_process);
1441 +  if (irelbase == NULL)
1442 +    return;
1443 +  irelend = irelbase + sec_to_process->reloc_count;
1444 +
1445 +  symtab_hdr = file_symtab_hdr (abfd);
1446 +  isymbuf = file_isymbuf (abfd);
1447 +
1448 +  addr_shndx = _bfd_elf_section_from_bfd_section (abfd, addr_sec);
1449 +
1450 +  for (irel = irelbase; irel < irelend; irel++)
1451 +    {
1452 +      if (ELF32_R_TYPE (irel->r_info) != R_UBICOM32_NONE)
1453 +       {
1454 +         /* Get the value of the symbol referred to by the reloc.  */
1455 +         if (ELF32_R_SYM (irel->r_info) < symtab_hdr->sh_info)
1456 +           {
1457 +             asection *sym_sec;
1458 +             bfd_vma xaddr, symval, relval;
1459 +
1460 +             /* A local symbol.  */
1461 +             isym = isymbuf + ELF32_R_SYM (irel->r_info);
1462 +             sym_sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
1463 +             xaddr = BASEADDR (addr_sec) + addr;
1464 +             symval = BASEADDR (sym_sec) + isym->st_value;
1465 +             relval = symval + irel->r_addend;
1466 +
1467 +             if ((isym->st_shndx == addr_shndx)
1468 +                 && (xaddr > symval)
1469 +                 && (xaddr <= relval))
1470 +               irel->r_addend += count;
1471 +           }
1472 +       }
1473 +
1474 +      /* Adjust irel base address for PC space relocations after a deleted instruction.  */
1475 +      if (sec_to_process == addr_sec)
1476 +       {
1477 +         if (addr <= irel->r_offset)
1478 +           irel->r_offset += count;
1479 +       }
1480 +    }
1481 +}
1482 +
1483 +static void
1484 +adjust_all_relocations (abfd, sec, addr, count)
1485 +     bfd *abfd;
1486 +     asection *sec;
1487 +     bfd_vma addr;
1488 +     int count;
1489 +{
1490 +  Elf_Internal_Shdr *symtab_hdr;
1491 +  Elf_Internal_Sym *isymbuf, *isym, *isymend;
1492 +  struct elf_link_hash_entry **sym_hashes;
1493 +  struct elf_link_hash_entry **end_hashes;
1494 +  unsigned int symcount;
1495 +  asection *section;
1496 +  unsigned int shndx;
1497 +
1498 +  symtab_hdr = file_symtab_hdr (abfd);
1499 +  isymbuf = file_isymbuf (abfd);
1500 +
1501 +  shndx = _bfd_elf_section_from_bfd_section (abfd, sec);
1502 +
1503 +  /* Adjust all relocations that are affected.  */
1504 +  for (section = abfd->sections; section != NULL; section = section->next)
1505 +    adjust_sec_relocations (abfd, section, sec, addr, count);
1506 +
1507 +  /* Adjust the local symbols defined in this section.  */
1508 +  isymend = isymbuf + symtab_hdr->sh_info;
1509 +  for (isym = isymbuf; isym < isymend; isym++)
1510 +    {
1511 +      if (isym->st_shndx == shndx
1512 +         && addr <= isym->st_value)
1513 +       isym->st_value += count;
1514 +    }
1515 +
1516 +  /* Now adjust the global symbols defined in this section.  */
1517 +  symcount = (symtab_hdr->sh_size / sizeof (Elf32_External_Sym)
1518 +             - symtab_hdr->sh_info);
1519 +  sym_hashes = elf_sym_hashes (abfd);
1520 +  end_hashes = sym_hashes + symcount;
1521 +  for (; sym_hashes < end_hashes; sym_hashes++)
1522 +    {
1523 +      struct elf_link_hash_entry *sym_hash = *sym_hashes;
1524 +
1525 +      if ((sym_hash->root.type == bfd_link_hash_defined
1526 +          || sym_hash->root.type == bfd_link_hash_defweak)
1527 +         && sym_hash->root.u.def.section == sec)
1528 +       {
1529 +         if (addr <= sym_hash->root.u.def.value)
1530 +           sym_hash->root.u.def.value += count;
1531 +       }
1532 +    }
1533 +}
1534 +
1535 +/* Perform a single relocation.  By default we use the standard BFD
1536 +   routines. */
1537 +
1538 +static bfd_reloc_status_type
1539 +ubicom32_final_link_relocate (howto, input_bfd, input_section, contents, rel, relocation)
1540 +     reloc_howto_type *  howto;
1541 +     bfd *               input_bfd;
1542 +     asection *          input_section;
1543 +     bfd_byte *          contents;
1544 +     Elf_Internal_Rela * rel;
1545 +     bfd_vma             relocation;
1546 +{
1547 +  bfd_reloc_status_type r = bfd_reloc_ok;
1548 +
1549 +  switch (howto->type)
1550 +    {
1551 +    default:
1552 +      r = _bfd_final_link_relocate (howto, input_bfd, input_section,
1553 +                                   contents, rel->r_offset,
1554 +                                   relocation, rel->r_addend);
1555 +    }
1556 +
1557 +  return r;
1558 +}
1559 +
1560 +/* Relocate a UBICOM32 ELF section.
1561 +   There is some attempt to make this function usable for many architectures,
1562 +   both USE_REL and USE_RELA ['twould be nice if such a critter existed],
1563 +   if only to serve as a learning tool.
1564 +
1565 +   The RELOCATE_SECTION function is called by the new ELF backend linker
1566 +   to handle the relocations for a section.
1567 +
1568 +   The relocs are always passed as Rela structures; if the section
1569 +   actually uses Rel structures, the r_addend field will always be
1570 +   zero.
1571 +
1572 +   This function is responsible for adjusting the section contents as
1573 +   necessary, and (if using Rela relocs and generating a relocatable
1574 +   output file) adjusting the reloc addend as necessary.
1575 +
1576 +   This function does not have to worry about setting the reloc
1577 +   address or the reloc symbol index.
1578 +
1579 +   LOCAL_SYMS is a pointer to the swapped in local symbols.
1580 +
1581 +   LOCAL_SECTIONS is an array giving the section in the input file
1582 +   corresponding to the st_shndx field of each local symbol.
1583 +
1584 +   The global hash table entry for the global symbols can be found
1585 +   via elf_sym_hashes (input_bfd).
1586 +
1587 +   When generating relocatable output, this function must handle
1588 +   STB_LOCAL/STT_SECTION symbols specially.  The output symbol is
1589 +   going to be the section symbol corresponding to the output
1590 +   section, which means that the addend must be adjusted
1591 +   accordingly.  */
1592 +
1593 +static bfd_boolean
1594 +ubicom32_elf_relocate_section (output_bfd, info, input_bfd, input_section,
1595 +                              contents, relocs, local_syms, local_sections)
1596 +     bfd *                   output_bfd ATTRIBUTE_UNUSED;
1597 +     struct bfd_link_info *  info;
1598 +     bfd *                   input_bfd;
1599 +     asection *              input_section;
1600 +     bfd_byte *              contents;
1601 +     Elf_Internal_Rela *     relocs;
1602 +     Elf_Internal_Sym *      local_syms;
1603 +     asection **             local_sections;
1604 +{
1605 +  Elf_Internal_Shdr *           symtab_hdr;
1606 +  struct elf_link_hash_entry ** sym_hashes;
1607 +  Elf_Internal_Rela *           rel;
1608 +  Elf_Internal_Rela *           relend;
1609 +  struct debugLineInfoHeader *lh = NULL;
1610 +  int cooked_size, discard_size;
1611 +  bfd_byte *src, *dest, *content_end;
1612 +  unsigned int i;
1613 +
1614 +  symtab_hdr = & elf_tdata (input_bfd)->symtab_hdr;
1615 +  sym_hashes = elf_sym_hashes (input_bfd);
1616 +  relend     = relocs + input_section->reloc_count;
1617 +
1618 +  for (rel = relocs; rel < relend; rel ++)
1619 +    {
1620 +      reloc_howto_type *           howto;
1621 +      unsigned long                r_symndx;
1622 +      Elf_Internal_Sym *           sym;
1623 +      asection *                   sec;
1624 +      struct elf_link_hash_entry * h;
1625 +      bfd_vma                      relocation;
1626 +      bfd_reloc_status_type        r;
1627 +      const char *                 name = NULL;
1628 +      int                          r_type;
1629 +
1630 +      r_type = ELF32_R_TYPE (rel->r_info);
1631 +
1632 +      if ( r_type == R_UBICOM32_GNU_VTINHERIT
1633 +          || r_type == R_UBICOM32_GNU_VTENTRY)
1634 +       continue;
1635 +
1636 +      r_symndx = ELF32_R_SYM (rel->r_info);
1637 +
1638 +      if (info->relocatable)
1639 +       {
1640 +         /* This is a relocatable link.  We don't have to change
1641 +            anything, unless the reloc is against a section symbol,
1642 +            in which case we have to adjust according to where the
1643 +            section symbol winds up in the output section.  */
1644 +         if (r_symndx < symtab_hdr->sh_info)
1645 +           {
1646 +             sym = local_syms + r_symndx;
1647 +
1648 +             if (ELF_ST_TYPE (sym->st_info) == STT_SECTION)
1649 +               {
1650 +                 sec = local_sections [r_symndx];
1651 +                 rel->r_addend += sec->output_offset + sym->st_value;
1652 +               }
1653 +           }
1654 +
1655 +         continue;
1656 +       }
1657 +
1658 +      /* This is a final link.  */
1659 +      howto  = ubicom32_elf_howto_table + ELF32_R_TYPE (rel->r_info);
1660 +      h      = NULL;
1661 +      sym    = NULL;
1662 +      sec    = NULL;
1663 +
1664 +      if (r_symndx < symtab_hdr->sh_info)
1665 +       {
1666 +         sym = local_syms + r_symndx;
1667 +         sec = local_sections [r_symndx];
1668 +         relocation = (sec->output_section->vma
1669 +                       + sec->output_offset
1670 +                       + sym->st_value);
1671 +
1672 +         name = bfd_elf_string_from_elf_section
1673 +           (input_bfd, symtab_hdr->sh_link, sym->st_name);
1674 +         name = (name == NULL) ? bfd_section_name (input_bfd, sec) : name;
1675 +       }
1676 +      else
1677 +       {
1678 +         h = sym_hashes [r_symndx - symtab_hdr->sh_info];
1679 +
1680 +         while (h->root.type == bfd_link_hash_indirect
1681 +                || h->root.type == bfd_link_hash_warning)
1682 +           h = (struct elf_link_hash_entry *) h->root.u.i.link;
1683 +
1684 +         name = h->root.root.string;
1685 +
1686 +         if (h->root.type == bfd_link_hash_defined
1687 +             || h->root.type == bfd_link_hash_defweak)
1688 +           {
1689 +             sec = h->root.u.def.section;
1690 +             relocation = (h->root.u.def.value
1691 +                           + sec->output_section->vma
1692 +                           + sec->output_offset);
1693 +           }
1694 +         else if (h->root.type == bfd_link_hash_undefweak)
1695 +           {
1696 +             relocation = 0;
1697 +           }
1698 +         else
1699 +           {
1700 +             if (! ((*info->callbacks->undefined_symbol)
1701 +                    (info, h->root.root.string, input_bfd,
1702 +                     input_section, rel->r_offset,
1703 +                     (!info->shared ))))
1704 +               return FALSE;
1705 +             relocation = 0;
1706 +           }
1707 +       }
1708 +
1709 +      switch (r_type)
1710 +       {
1711 +       case R_UBICOM32_LO16:
1712 +         r = ubicom32_elf_relocate_lo16 (input_bfd, rel, contents, relocation);
1713 +         break;
1714 +
1715 +       case R_UBICOM32_HI16:
1716 +         r = ubicom32_elf_relocate_hi16 (input_bfd, rel, contents, relocation);
1717 +         break;
1718 +
1719 +       case R_UBICOM32_HI24:
1720 +         r = ubicom32_elf_relocate_hi24 (input_bfd, rel, contents, relocation);
1721 +         break;
1722 +
1723 +       case R_UBICOM32_LO7_S:
1724 +         r = ubicom32_elf_relocate_lo7_s (input_bfd, rel, contents, relocation);
1725 +         break;
1726 +
1727 +       case R_UBICOM32_LO7_2_S:
1728 +         r = ubicom32_elf_relocate_lo7_2_s (input_bfd, rel, contents, relocation);
1729 +         break;
1730 +
1731 +       case R_UBICOM32_LO7_4_S:
1732 +         r = ubicom32_elf_relocate_lo7_4_s (input_bfd, rel, contents, relocation);
1733 +         break;
1734 +
1735 +       case R_UBICOM32_LO7_D:
1736 +         r = ubicom32_elf_relocate_lo7_d (input_bfd, rel, contents, relocation);
1737 +         break;
1738 +
1739 +       case R_UBICOM32_LO7_2_D:
1740 +         r = ubicom32_elf_relocate_lo7_2_d (input_bfd, rel, contents, relocation);
1741 +         break;
1742 +
1743 +       case R_UBICOM32_LO7_4_D:
1744 +         r = ubicom32_elf_relocate_lo7_4_d (input_bfd, rel, contents, relocation);
1745 +         break;
1746 +
1747 +       case R_UBICOM32_24_PCREL:
1748 +         r = ubicom32_elf_relocate_pcrel24 (input_bfd, input_section, rel, contents, relocation);
1749 +         break;
1750 +
1751 +       case R_UBICOM32_LO7_CALLI:
1752 +         r = ubicom32_elf_relocate_lo_calli (input_bfd, rel, contents, relocation, 7);
1753 +         break;
1754 +
1755 +       case R_UBICOM32_LO16_CALLI:
1756 +         r = ubicom32_elf_relocate_lo_calli (input_bfd, rel, contents, relocation, 18);
1757 +         break;
1758 +
1759 +       case R_UBICOM32_32:
1760 +         /* relocation &= ~(0xff << 24); */
1761 +         /* FALLTHROUGH */
1762 +
1763 +       default:
1764 +         r = ubicom32_final_link_relocate (howto, input_bfd, input_section,
1765 +                                           contents, rel, relocation);
1766 +         break;
1767 +       }
1768 +
1769 +      if (r != bfd_reloc_ok)
1770 +       {
1771 +         const char * msg = (const char *) NULL;
1772 +
1773 +         switch (r)
1774 +           {
1775 +           case bfd_reloc_overflow:
1776 +             r = info->callbacks->reloc_overflow
1777 +               (info, NULL, name, howto->name, (bfd_vma) 0,
1778 +                input_bfd, input_section, rel->r_offset);
1779 +             break;
1780 +
1781 +           case bfd_reloc_undefined:
1782 +             r = info->callbacks->undefined_symbol
1783 +               (info, name, input_bfd, input_section, rel->r_offset, TRUE);
1784 +             break;
1785 +
1786 +           case bfd_reloc_outofrange:
1787 +             msg = _("internal error: out of range error");
1788 +             break;
1789 +
1790 +           case bfd_reloc_notsupported:
1791 +             msg = _("internal error: unsupported relocation error");
1792 +             break;
1793 +
1794 +           case bfd_reloc_dangerous:
1795 +             msg = _("internal error: dangerous relocation");
1796 +             break;
1797 +
1798 +           default:
1799 +             msg = _("internal error: unknown error");
1800 +             break;
1801 +           }
1802 +
1803 +         if (msg)
1804 +           r = info->callbacks->warning
1805 +             (info, msg, name, input_bfd, input_section, rel->r_offset);
1806 +
1807 +         if (! r)
1808 +           return FALSE;
1809 +       }
1810 +    }
1811 +
1812 +  /*
1813 +   * now we have to collapse the .debug_line section if it has a
1814 +   * sec_info section
1815 +   */
1816 +
1817 +  if(strcmp(input_section->name, ".debug_line"))
1818 +    return TRUE;
1819 +
1820 +  /* this is a .debug_line section. See it has a sec_info entry */
1821 +  if(elf_section_data(input_section)->sec_info == NULL)
1822 +    return TRUE;
1823 +
1824 +  lh = (struct debugLineInfoHeader *) elf_section_data(input_section)->sec_info;
1825 +
1826 +  if(lh->numEntries == 0)
1827 +    return TRUE;
1828 +
1829 +  dest = contents + lh->linfo[0].startOffset;
1830 +
1831 +  cooked_size = input_section->rawsize;
1832 +  content_end = contents + cooked_size;
1833 +  discard_size = 0;
1834 +
1835 +  for(i=0; i< lh->numEntries; i++)
1836 +    {
1837 +      if(lh->linfo[i].discard)
1838 +       discard_size += lh->linfo[i].length;
1839 +      else
1840 +       {
1841 +         src = contents + lh->linfo[i].startOffset;
1842 +         (void) memcpy(dest, src, lh->linfo[i].length);
1843 +         dest += lh->linfo[i].length;
1844 +       }
1845 +    }
1846 +
1847 +  src = contents + lh->linfo[lh->numEntries-1].startOffset + lh->linfo[lh->numEntries-1].length;
1848 +  if(src < content_end)
1849 +    (void) memcpy(dest, src, content_end - src);
1850 +
1851 +  i = bfd_get_32(input_bfd, contents);
1852 +  i -= discard_size;
1853 +  bfd_put_32(input_bfd, i, contents);
1854 +  //input_section->rawsize -= discard_size;
1855 +  return TRUE;
1856 +}
1857 +
1858 +\f
1859 +/* Update the got entry reference counts for the section being
1860 +   removed.  */
1861 +
1862 +static bfd_boolean
1863 +ubicom32_elf_gc_sweep_hook (abfd, info, sec, relocs)
1864 +     bfd *                     abfd ATTRIBUTE_UNUSED;
1865 +     struct bfd_link_info *    info ATTRIBUTE_UNUSED;
1866 +     asection *                sec ATTRIBUTE_UNUSED;
1867 +     const Elf_Internal_Rela * relocs ATTRIBUTE_UNUSED;
1868 +{
1869 +  return TRUE;
1870 +}
1871 +
1872 +/* Return the section that should be marked against GC for a given
1873 +   relocation.  */
1874 +
1875 +static asection *
1876 +ubicom32_elf_gc_mark_hook (sec, info, rel, h, sym)
1877 +     asection *                   sec;
1878 +     struct bfd_link_info *       info ATTRIBUTE_UNUSED;
1879 +     Elf_Internal_Rela *          rel;
1880 +     struct elf_link_hash_entry * h;
1881 +     Elf_Internal_Sym *           sym;
1882 +{
1883 +  if (h != NULL)
1884 +    {
1885 +      switch (ELF32_R_TYPE (rel->r_info))
1886 +       {
1887 +       case R_UBICOM32_GNU_VTINHERIT:
1888 +       case R_UBICOM32_GNU_VTENTRY:
1889 +         break;
1890 +
1891 +       default:
1892 +         switch (h->root.type)
1893 +           {
1894 +           case bfd_link_hash_defined:
1895 +           case bfd_link_hash_defweak:
1896 +             return h->root.u.def.section;
1897 +
1898 +           case bfd_link_hash_common:
1899 +             return h->root.u.c.p->section;
1900 +
1901 +           default:
1902 +             break;
1903 +           }
1904 +       }
1905 +    }
1906 +  else
1907 +    {
1908 +      if (!(elf_bad_symtab (sec->owner)
1909 +           && ELF_ST_BIND (sym->st_info) != STB_LOCAL)
1910 +         && ! ((sym->st_shndx <= 0 || sym->st_shndx >= SHN_LORESERVE)
1911 +               && sym->st_shndx != SHN_COMMON))
1912 +       {
1913 +         return bfd_section_from_elf_index (sec->owner, sym->st_shndx);
1914 +       }
1915 +    }
1916 +
1917 +  return NULL;
1918 +}
1919 +
1920 +/* Look through the relocs for a section during the first phase.
1921 +   Since we don't do .gots or .plts, we just need to consider the
1922 +   virtual table relocs for gc.  */
1923 +
1924 +static bfd_boolean
1925 +ubicom32_elf_check_relocs (abfd, info, sec, relocs)
1926 +     bfd *abfd;
1927 +     struct bfd_link_info *info;
1928 +     asection *sec;
1929 +     const Elf_Internal_Rela *relocs;
1930 +{
1931 +  Elf_Internal_Shdr *symtab_hdr;
1932 +  struct elf_link_hash_entry **sym_hashes, **sym_hashes_end;
1933 +  Elf_Internal_Rela *rel;
1934 +  Elf_Internal_Rela *rel_end;
1935 +  Elf_Internal_Rela *my_rel = ( Elf_Internal_Rela*)relocs;
1936 +  if (info->relocatable)
1937 +    return TRUE;
1938 +
1939 +  symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
1940 +  sym_hashes = elf_sym_hashes (abfd);
1941 +  sym_hashes_end = sym_hashes + symtab_hdr->sh_size/sizeof(Elf32_External_Sym);
1942 +  if (!elf_bad_symtab (abfd))
1943 +    sym_hashes_end -= symtab_hdr->sh_info;
1944 +
1945 +  rel_end = my_rel + sec->reloc_count;
1946 +  for (rel = my_rel; rel < rel_end; rel++)
1947 +    {
1948 +      struct elf_link_hash_entry *h;
1949 +      unsigned long r_symndx;
1950 +
1951 +      r_symndx = ELF32_R_SYM (rel->r_info);
1952 +      if (r_symndx < symtab_hdr->sh_info)
1953 +       h = NULL;
1954 +      else
1955 +       h = sym_hashes [r_symndx - symtab_hdr->sh_info];
1956 +
1957 +      switch (ELF32_R_TYPE (rel->r_info))
1958 +       {
1959 +         /* This relocation describes the C++ object vtable hierarchy.
1960 +            Reconstruct it for later use during GC.  */
1961 +       case R_UBICOM32_GNU_VTINHERIT:
1962 +         if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset))
1963 +           return FALSE;
1964 +         break;
1965 +
1966 +         /* This relocation describes which C++ vtable entries are actually
1967 +            used.  Record for later use during GC.  */
1968 +       case R_UBICOM32_GNU_VTENTRY:
1969 +         if (!bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_addend))
1970 +           return FALSE;
1971 +         break;
1972 +
1973 +       case R_UBICOM32_32:
1974 +         /* For debug section, change to harvard relocations */
1975 +         if (memcmp (sec->name, ".debug", 6) == 0
1976 +             || memcmp (sec->name, ".stab", 5) == 0)
1977 +           rel->r_info = ELF32_R_INFO (ELF32_R_SYM (rel->r_info), R_UBICOM32_32_HARVARD);
1978 +         break;
1979 +       }
1980 +    }
1981 +  return TRUE;
1982 +}
1983 +
1984 +static bfd_boolean
1985 +ubicom32_elf_object_p (abfd)
1986 +     bfd *abfd;
1987 +{
1988 +  flagword  mach = elf_elfheader (abfd)->e_flags & 0xffff;
1989 +  bfd_default_set_arch_mach (abfd, bfd_arch_ubicom32, mach);
1990 +  return (((elf_elfheader (abfd)->e_flags & EF_UBICOM32_FDPIC) != 0)
1991 +         == (IS_FDPIC (abfd)));
1992 +}
1993 +
1994 +\f
1995 +/* Function to set the ELF flag bits */
1996 +
1997 +static bfd_boolean
1998 +ubicom32_elf_set_private_flags (abfd, flags)
1999 +     bfd *abfd;
2000 +     flagword flags;
2001 +{
2002 +  elf_elfheader (abfd)->e_flags = flags;
2003 +  elf_flags_init (abfd) = TRUE;
2004 +  return TRUE;
2005 +}
2006 +
2007 +static bfd_boolean
2008 +ubicom32_elf_copy_private_bfd_data (ibfd, obfd)
2009 +     bfd *ibfd;
2010 +     bfd *obfd;
2011 +{
2012 +  if (bfd_get_flavour (ibfd) != bfd_target_elf_flavour
2013 +      || bfd_get_flavour (obfd) != bfd_target_elf_flavour)
2014 +    return TRUE;
2015 +
2016 +  BFD_ASSERT (!elf_flags_init (obfd)
2017 +             || elf_elfheader (obfd)->e_flags == elf_elfheader (ibfd)->e_flags);
2018 +
2019 +  elf_elfheader (obfd)->e_flags = elf_elfheader (ibfd)->e_flags;
2020 +  elf_flags_init (obfd) = TRUE;
2021 +  return TRUE;
2022 +}
2023 +
2024 +/* Merge backend specific data from an object file to the output
2025 +   object file when linking. */
2026 +static bfd_boolean
2027 +ubicom32_elf_merge_private_bfd_data (ibfd, obfd)
2028 +     bfd *ibfd;
2029 +     bfd *obfd;
2030 +{
2031 +  flagword old_flags, new_flags;
2032 +  bfd_boolean error = FALSE;
2033 +
2034 +  new_flags = elf_elfheader (ibfd)->e_flags;
2035 +  old_flags = elf_elfheader (obfd)->e_flags;
2036 +
2037 +#ifdef DEBUG
2038 +  (*_bfd_error_handler) ("old_flags = 0x%.8lx, new_flags = 0x%.8lx, init = %s, filename = %s",
2039 +                        old_flags, new_flags, elf_flags_init (obfd) ? "yes" : "no",
2040 +                        bfd_get_filename (ibfd));
2041 +#endif
2042 +
2043 +  if (!elf_flags_init (obfd))                  /* First call, no flags set */
2044 +    {
2045 +      elf_flags_init (obfd) = TRUE;
2046 +      elf_elfheader (obfd)->e_flags = new_flags;
2047 +    }
2048 +  else
2049 +    {
2050 +      if (new_flags != old_flags)
2051 +       {
2052 +         /* Mismatched flags. */
2053 +         char *output_cpu_version = ((old_flags &0xffff) == 1) ? "V3" : (((old_flags &0xffff) == 2) ? "V4" : "unknown");
2054 +         char *input_cpu_version = ((new_flags &0xffff) == 1) ? "V3" : (((new_flags &0xffff) == 2) ? "V4" : "unknown");
2055 +         char *output_filename = bfd_get_filename (obfd);
2056 +         char *input_filename = bfd_get_filename (ibfd);
2057 +         char *output_pic = (old_flags & EF_UBICOM32_PIC_FLAGS) ? ((old_flags & EF_UBICOM32_PIC) ? "FPIC" : "FDPIC") : NULL;
2058 +         char *input_pic = (new_flags & EF_UBICOM32_PIC_FLAGS) ? ((new_flags & EF_UBICOM32_PIC) ? "FPIC" : "FDPIC") : NULL;
2059 +
2060 +         (*_bfd_error_handler) ("Linking mismatched file types. Output file = %s file type 0x%.8lx, input file = %s file type 0x%.8lx",
2061 +                                output_filename, old_flags, input_filename, new_flags);
2062 +
2063 +         if (output_pic)
2064 +           {
2065 +             (*_bfd_error_handler)("Output file %s %s for cpu version %s", output_filename, output_pic, output_cpu_version);
2066 +           }
2067 +         else
2068 +           {
2069 +             (*_bfd_error_handler)("Output file %s for cpu version %s", output_filename, output_cpu_version);
2070 +           }
2071 +
2072 +         if (input_pic)
2073 +           {
2074 +             (*_bfd_error_handler)("Input file %s %s for cpu version %s", input_filename, input_pic, input_cpu_version);
2075 +           }
2076 +         else
2077 +           {
2078 +             (*_bfd_error_handler)("Input file %s for cpu version %s", input_filename, input_cpu_version);
2079 +           }
2080 +         
2081 +         (*_bfd_error_handler) ("Link ABORTED.");
2082 +         _exit(EXIT_FAILURE);
2083 +       }
2084 +    }
2085 +  if (error)
2086 +    bfd_set_error (bfd_error_bad_value);
2087 +
2088 +  return !error;
2089 +}
2090 +
2091 +static bfd_boolean
2092 +ubicom32_elf_print_private_bfd_data (abfd, ptr)
2093 +     bfd *abfd;
2094 +     PTR ptr;
2095 +{
2096 +  FILE *file = (FILE *) ptr;
2097 +  flagword flags;
2098 +
2099 +  BFD_ASSERT (abfd != NULL && ptr != NULL);
2100 +
2101 +  /* Print normal ELF private data.  */
2102 +  _bfd_elf_print_private_bfd_data (abfd, ptr);
2103 +
2104 +  flags = elf_elfheader (abfd)->e_flags;
2105 +  fprintf (file, _("private flags = 0x%lx:"), (long)flags);
2106 +
2107 +  fputc ('\n', file);
2108 +
2109 +  return TRUE;
2110 +}
2111 +
2112 +bfd_boolean
2113 +ubicom32_elf_discard_info(abfd, cookie, info)
2114 +     bfd *abfd;
2115 +     struct elf_reloc_cookie *cookie ATTRIBUTE_UNUSED;
2116 +     struct bfd_link_info *info;
2117 +
2118 +{
2119 +  unsigned int hasDebugLine=0;
2120 +  unsigned needExclude = 0;
2121 +  asection *o;
2122 +  asection *sec= NULL;
2123 +  bfd_byte *contents = NULL;
2124 +  bfd_byte *contentsEnd;
2125 +  Elf_Internal_Rela *irel, *irelend, *irelbase;
2126 +  Elf_Internal_Shdr *symtab_hdr;
2127 +  Elf_Internal_Sym *isym;
2128 +  Elf_Internal_Sym *isymbuf = NULL;
2129 +  struct debugLineInfoHeader *lh = NULL;
2130 +  unsigned int maxLineInfoEntries = 10;
2131 +  unsigned int offset, contentLength;
2132 +  unsigned char *ptr, *sequence_start;
2133 +  unsigned int setupEntry=1;
2134 +  unsigned int opcode_base, op_code;
2135 +  unsigned int bytes_read;
2136 +
2137 +  for (o = abfd->sections; o != NULL; o = o->next)
2138 +    {
2139 +      if(!hasDebugLine)
2140 +       if(!strcmp(o->name, ".debug_line"))
2141 +         {
2142 +           hasDebugLine =1;
2143 +           sec = o;
2144 +         }
2145 +
2146 +      /* Keep special sections.  Keep .debug sections.  */
2147 +      if (o->flags & SEC_EXCLUDE)
2148 +       {
2149 +         needExclude = 1;
2150 +       }
2151 +    }
2152 +
2153 +  if(needExclude == 0 || hasDebugLine ==0)
2154 +    return FALSE;
2155 +
2156 +  /*
2157 +   * you can be here only if we have .debug_line section and some
2158 +   * section is being excudled
2159 +   */
2160 +
2161 +  /*
2162 +   * We need to extract .debug_line section contents and its
2163 +   * relocation contents.
2164 +   */
2165 +
2166 +  /* We don't have to do anything for a relocatable link,
2167 +     if this section does not have relocs */
2168 +  if (info->relocatable
2169 +      || (sec->flags & SEC_RELOC) == 0
2170 +      || sec->reloc_count == 0)
2171 +    return FALSE;
2172 +
2173 +  /* If this is the first time we have been called
2174 +     for this section, initialise the cooked size.
2175 +     if (sec->_cooked_size == 0)
2176 +     sec->_cooked_size = sec->rawsize;
2177 +  */
2178 +
2179 +  symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
2180 +
2181 +  irelbase = _bfd_elf_link_read_relocs (abfd, sec, NULL,
2182 +                                       (Elf_Internal_Rela *)NULL,
2183 +                                       info->keep_memory);
2184 +
2185 +  if(irelbase == NULL)
2186 +    return FALSE;
2187 +
2188 +  irelend = irelbase +sec->reloc_count;
2189 +
2190 +  /* Get section contents cached copy if it exists.  */
2191 +  if (contents == NULL)
2192 +    {
2193 +      contents = section_contents(abfd, sec);
2194 +    }
2195 +
2196 +  if (isymbuf == NULL && symtab_hdr->sh_info != 0)
2197 +    {
2198 +      isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents;
2199 +      if (isymbuf == NULL)
2200 +       isymbuf = bfd_elf_get_elf_syms (abfd, symtab_hdr,
2201 +                                       symtab_hdr->sh_info, 0,
2202 +                                       NULL, NULL, NULL);
2203 +      if (isymbuf == NULL)
2204 +       return FALSE;
2205 +    }
2206 +
2207 +  /* allocate the line header and initialize it */
2208 +  lh = (struct debugLineInfoHeader *)
2209 +    realloc( (void *)lh, sizeof (struct debugLineInfo)*maxLineInfoEntries +
2210 +            sizeof(unsigned int));
2211 +
2212 +  lh->numEntries = 0;
2213 +
2214 +  /* the first 4 bytes contains the length */
2215 +  contentLength = bfd_get_32 (abfd, (bfd_byte *)contents);
2216 +  contentsEnd = contents + contentLength + 4;
2217 +
2218 +  ptr = (unsigned char *)contents;
2219 +  ptr +=6;
2220 +  /* read the header length */
2221 +  offset = bfd_get_32(abfd, (bfd_byte *)ptr);
2222 +  ptr += 4;
2223 +  ptr += offset;
2224 +
2225 +  /* extract the base opcode */
2226 +  opcode_base = (unsigned char)contents[14];
2227 +  sequence_start = NULL;
2228 +  while(ptr < (unsigned char *) contentsEnd)
2229 +    {
2230 +      if(setupEntry)
2231 +       {
2232 +         if(lh->numEntries == maxLineInfoEntries)
2233 +           {
2234 +             /* need to do some reallocing. Bump up the entries by 10 */
2235 +             maxLineInfoEntries += 10;
2236 +             lh = (struct debugLineInfoHeader *)
2237 +               realloc( (void *)lh,
2238 +                        sizeof (struct debugLineInfo)*maxLineInfoEntries +
2239 +                        sizeof(unsigned int));
2240 +           }
2241 +
2242 +         /* zero out the entry */
2243 +         memset((void *) &lh->linfo[lh->numEntries],
2244 +                0,
2245 +                sizeof(struct debugLineInfo));
2246 +         lh->linfo[lh->numEntries].startOffset = (bfd_byte *)ptr - contents;
2247 +         setupEntry = 0;
2248 +         sequence_start = ptr;
2249 +       }
2250 +
2251 +      /* We need to run the state machine */
2252 +      op_code = bfd_get_8 (abfd, (bfd_byte *)ptr);
2253 +      ptr += 1;
2254 +
2255 +      if(op_code >= opcode_base)
2256 +       continue;
2257 +
2258 +      switch(op_code)
2259 +       {
2260 +       case DW_LNS_extended_op:
2261 +         ptr += 1;     /* ignore length */
2262 +         op_code = bfd_get_8 (abfd, (bfd_byte *)ptr);
2263 +         ptr += 1;
2264 +         switch (op_code)
2265 +           {
2266 +           case DW_LNE_end_sequence:
2267 +             /* end of sequence. Time to record stuff */
2268 +             lh->linfo[lh->numEntries++].length =
2269 +               (bfd_byte *)ptr - sequence_start;
2270 +             setupEntry = 1;
2271 +             break;
2272 +           case DW_LNE_set_address:
2273 +             ptr += 4;
2274 +             break;
2275 +           case DW_LNE_define_file:
2276 +             {
2277 +               ptr += (strlen((char *)ptr) + 1);
2278 +               (void) read_unsigned_leb128(abfd, ptr, &bytes_read);
2279 +               ptr += bytes_read;
2280 +               (void) read_unsigned_leb128(abfd, ptr, &bytes_read);
2281 +               ptr += bytes_read;
2282 +               (void) read_unsigned_leb128(abfd, ptr, &bytes_read);
2283 +               ptr += bytes_read;
2284 +               break;
2285 +             }
2286 +           }
2287 +       case DW_LNS_negate_stmt:
2288 +       case DW_LNS_set_basic_block:
2289 +       case DW_LNS_const_add_pc:
2290 +       case DW_LNS_copy:
2291 +         break;
2292 +       case DW_LNS_advance_pc:
2293 +       case DW_LNS_set_file:
2294 +       case DW_LNS_set_column:
2295 +         (void) read_unsigned_leb128 (abfd, ptr, &bytes_read);
2296 +         ptr += bytes_read;
2297 +         break;
2298 +       case DW_LNS_advance_line:
2299 +         (void) read_signed_leb128 (abfd, ptr, &bytes_read);
2300 +         ptr += bytes_read;
2301 +         break;
2302 +       case DW_LNS_fixed_advance_pc:
2303 +         ptr += 2;
2304 +         break;
2305 +       }
2306 +    }
2307 +
2308 +  /*
2309 +   * now scan through the relocations and match the
2310 +   * lineinfo to a section name
2311 +   */
2312 +  for(irel = irelbase; irel< irelend; irel++)
2313 +    {
2314 +      bfd_vma offset;
2315 +      asection *sym_sec;
2316 +      int i;
2317 +
2318 +      offset = irel->r_offset;
2319 +      isym = isymbuf + ELF32_R_SYM (irel->r_info);
2320 +
2321 +      sym_sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
2322 +
2323 +      /* find which line section this rel entry belongs to */
2324 +      for(i=0; i< (int) lh->numEntries; i++)
2325 +       {
2326 +         if(lh->linfo[i].startOffset <= offset &&
2327 +            offset < lh->linfo[i].startOffset + lh->linfo[i].length)
2328 +           break;
2329 +       }
2330 +
2331 +      if(lh->linfo[i].sectionName == NULL)
2332 +       lh->linfo[i].sectionName = strdup(sym_sec->name);
2333 +    }
2334 +
2335 +  /* now scan through and find the exclude sections */
2336 +  for (o = abfd->sections; o != NULL; o = o->next)
2337 +    {
2338 +      if (o->flags & SEC_EXCLUDE)
2339 +       {
2340 +         /* go through the lh entries and mark as discard */
2341 +         int i;
2342 +         for(i=0; i< (int) lh->numEntries; i++)
2343 +           {
2344 +             if(!strcmp(o->name, lh->linfo[i].sectionName))
2345 +               lh->linfo[i].discard = 1;
2346 +           }
2347 +       }
2348 +    }
2349 +
2350 +  elf_section_data(sec)->sec_info = (PTR)(lh);
2351 +
2352 +  return TRUE;
2353 +}
2354 +
2355 +\f
2356 +/* An extension of the elf hash table data structure, containing some
2357 +   additional Blackfin-specific data.  */
2358 +struct ubicom32fdpic_elf_link_hash_table
2359 +{
2360 +  struct elf_link_hash_table elf;
2361 +
2362 +  /* A pointer to the .got section.  */
2363 +  asection *sgot;
2364 +  /* A pointer to the .rel.got section.  */
2365 +  asection *sgotrel;
2366 +  /* A pointer to the .rofixup section.  */
2367 +  asection *sgotfixup;
2368 +  /* A pointer to the .plt section.  */
2369 +  asection *splt;
2370 +  /* A pointer to the .rel.plt section.  */
2371 +  asection *spltrel;
2372 +  /* GOT base offset.  */
2373 +  bfd_vma got0;
2374 +  /* Location of the first non-lazy PLT entry, i.e., the number of
2375 +     bytes taken by lazy PLT entries.  */
2376 +  bfd_vma plt0;
2377 +  /* A hash table holding information about which symbols were
2378 +     referenced with which PIC-related relocations.  */
2379 +  struct htab *relocs_info;
2380 +};
2381 +
2382 +/* Get the Ubicom32 ELF linker hash table from a link_info structure.  */
2383 +
2384 +#define ubicom32fdpic_hash_table(info) \
2385 +  ((struct ubicom32fdpic_elf_link_hash_table *) ((info)->hash))
2386 +
2387 +#define ubicom32fdpic_got_section(info) \
2388 +  (ubicom32fdpic_hash_table (info)->sgot)
2389 +#define ubicom32fdpic_gotrel_section(info) \
2390 +  (ubicom32fdpic_hash_table (info)->sgotrel)
2391 +#define ubicom32fdpic_gotfixup_section(info) \
2392 +  (ubicom32fdpic_hash_table (info)->sgotfixup)
2393 +#define ubicom32fdpic_plt_section(info) \
2394 +  (ubicom32fdpic_hash_table (info)->splt)
2395 +#define ubicom32fdpic_pltrel_section(info) \
2396 +  (ubicom32fdpic_hash_table (info)->spltrel)
2397 +#define ubicom32fdpic_relocs_info(info) \
2398 +  (ubicom32fdpic_hash_table (info)->relocs_info)
2399 +#define ubicom32fdpic_got_initial_offset(info) \
2400 +  (ubicom32fdpic_hash_table (info)->got0)
2401 +#define ubicom32fdpic_plt_initial_offset(info) \
2402 +  (ubicom32fdpic_hash_table (info)->plt0)
2403 +
2404 +/* The name of the dynamic interpreter.  This is put in the .interp
2405 +   section.  */
2406 +
2407 +#define ELF_DYNAMIC_INTERPRETER "/lib/ld.so.1"
2408 +
2409 +#define DEFAULT_STACK_SIZE 0x20000
2410 +
2411 +/* This structure is used to collect the number of entries present in
2412 +   each addressable range of the got.  */
2413 +struct _ubicom32fdpic_dynamic_got_info
2414 +{
2415 +  /* Several bits of information about the current link.  */
2416 +  struct bfd_link_info *info;
2417 +  /* Total size needed for GOT entries. */
2418 +  bfd_vma gotoffset_lo, gotoffset_hi;
2419 +  /* Total size needed for function descriptor entries. */
2420 +  bfd_vma fd_gotoffset_lo, fd_gotoffset_hi;
2421 +  /* Total size needed function descriptor entries referenced in PLT
2422 +     entries, that would be profitable to place in offsets close to
2423 +     the PIC register.  */
2424 +  bfd_vma fdplt, privfdplt;
2425 +  /* Total size needed by lazy PLT entries.  */
2426 +  bfd_vma lzplt;
2427 +  bfd_vma num_plts;
2428 +
2429 +  /* Number of relocations carried over from input object files.  */
2430 +  unsigned long relocs;
2431 +  /* Number of fixups introduced by relocations in input object files.  */
2432 +  unsigned long fixups;
2433 +};
2434 +
2435 +/* This structure is used to assign offsets to got entries, function
2436 +   descriptors, plt entries and lazy plt entries.  */
2437 +struct ubicom32fdpic_dynamic_got_plt_info
2438 +{
2439 +  /* Summary information collected with _bfinfdpic_count_got_plt_entries.  */
2440 +  struct _ubicom32fdpic_dynamic_got_info g;
2441 +
2442 +  bfd_signed_vma current_got;  /* This will be used during got entry allocation */
2443 +  bfd_signed_vma current_fd;   /* This will be used for function descriptro allocation. The numbers will go negative */
2444 +  bfd_signed_vma current_privfd;       /* This will be used for function descriptro allocation. The numbers will go negative */
2445 +  bfd_vma current_plt;         /* This is the offset to the PLT entry. We will need this to resolve the call entries. */
2446 +  bfd_vma current_plt_trampoline; /* This is the offset to the PLT trampoline entry. */
2447 +  bfd_vma total_fdplt;         /* Total size of function descriptors. This is the memory above GOT pointer. */
2448 +  bfd_vma total_got;           /* This is the total of got entries for got_lo and got_funcdesc_lo references. */
2449 +  bfd_vma total_lzplt;         /* This is the total area for the PLT entries. This does not have the trampoline entry. */
2450 +  bfd_vma total_trampoline;    /* This is the total area for the PLT trampoline entries. */
2451 +};
2452 +
2453 +/* Decide whether a reference to a symbol can be resolved locally or
2454 +   not.  If the symbol is protected, we want the local address, but
2455 +   its function descriptor must be assigned by the dynamic linker.  */
2456 +#define UBICOM32FDPIC_SYM_LOCAL(INFO, H) \
2457 +  (_bfd_elf_symbol_refs_local_p ((H), (INFO), 1) \
2458 +   || ! elf_hash_table (INFO)->dynamic_sections_created)
2459 +#define UBICOM32FDPIC_FUNCDESC_LOCAL(INFO, H) \
2460 +  ((H)->dynindx == -1 || ! elf_hash_table (INFO)->dynamic_sections_created)
2461 +
2462 +/* This structure collects information on what kind of GOT, PLT or
2463 +   function descriptors are required by relocations that reference a
2464 +   certain symbol.  */
2465 +struct ubicom32fdpic_relocs_info
2466 +{
2467 +  /* The index of the symbol, as stored in the relocation r_info, if
2468 +     we have a local symbol; -1 otherwise.  */
2469 +  long symndx;
2470 +  union
2471 +  {
2472 +    /* The input bfd in which the symbol is defined, if it's a local
2473 +       symbol.  */
2474 +    bfd *abfd;
2475 +    /* If symndx == -1, the hash table entry corresponding to a global
2476 +       symbol (even if it turns out to bind locally, in which case it
2477 +       should ideally be replaced with section's symndx + addend).  */
2478 +    struct elf_link_hash_entry *h;
2479 +  } d;
2480 +  /* The addend of the relocation that references the symbol.  */
2481 +  bfd_vma addend;
2482 +
2483 +  /* The fields above are used to identify an entry.  The fields below
2484 +     contain information on how an entry is used and, later on, which
2485 +     locations it was assigned.  */
2486 +  /* The following 2 fields record whether the symbol+addend above was
2487 +     ever referenced with a GOT relocation.  The 17M4 suffix indicates a
2488 +     GOT17M4 relocation; hilo is used for GOTLO/GOTHI pairs.  */
2489 +  unsigned gotoffset_lo;
2490 +  unsigned gotoffset_hi;
2491 +  /* Whether a FUNCDESC relocation references symbol+addend.  */
2492 +  unsigned fd;
2493 +  /* Whether a FUNCDESC_GOT relocation references symbol+addend.  */
2494 +  unsigned fd_gotoffset_lo;
2495 +  unsigned fd_gotoffset_hi;
2496 +  /* Whether symbol+addend is referenced with GOTOFF17M4, GOTOFFLO or
2497 +     GOTOFFHI relocations.  The addend doesn't really matter, since we
2498 +     envision that this will only be used to check whether the symbol
2499 +     is mapped to the same segment as the got.  */
2500 +  unsigned gotoff;
2501 +  /* Whether symbol+addend is referenced by a LABEL24 relocation.  */
2502 +  unsigned call;
2503 +  /* Whether symbol+addend is referenced by a 32 or FUNCDESC_VALUE
2504 +     relocation.  */
2505 +  unsigned sym;
2506 +  /* Whether we need a PLT entry for a symbol.  Should be implied by
2507 +     something like:
2508 +     (call && symndx == -1 && ! BFINFDPIC_SYM_LOCAL (info, d.h))  */
2509 +  unsigned plt:1;
2510 +  /* Whether a function descriptor should be created in this link unit
2511 +     for symbol+addend.  Should be implied by something like:
2512 +     (plt || fd_gotoffset_lo || fd_gotoffset_hi
2513 +     || ((fd || fdgot17m4 || fdgothilo)
2514 +     && (symndx != -1 || BFINFDPIC_FUNCDESC_LOCAL (info, d.h))))  */
2515 +  unsigned privfd:1;
2516 +  /* Whether a lazy PLT entry is needed for this symbol+addend.
2517 +     Should be implied by something like:
2518 +     (privfd && symndx == -1 && ! BFINFDPIC_SYM_LOCAL (info, d.h)
2519 +     && ! (info->flags & DF_BIND_NOW))  */
2520 +  unsigned lazyplt:1;
2521 +  /* Whether we've already emitted GOT relocations and PLT entries as
2522 +     needed for this symbol.  */
2523 +  unsigned done:1;
2524 +
2525 +  /* The number of R_byte4_data, R_BFIN_FUNCDESC and R_BFIN_FUNCDESC_VALUE
2526 +     relocations referencing the symbol.  */
2527 +  unsigned relocs32, relocsfd, relocsfdv;
2528 +
2529 +  /* The number of .rofixups entries and dynamic relocations allocated
2530 +     for this symbol, minus any that might have already been used.  */
2531 +  unsigned fixups, dynrelocs;
2532 +
2533 +  /* The offsets of the GOT entries assigned to symbol+addend, to the
2534 +     function descriptor's address, and to a function descriptor,
2535 +     respectively.  Should be zero if unassigned.  The offsets are
2536 +     counted from the value that will be assigned to the PIC register,
2537 +     not from the beginning of the .got section.  */
2538 +  bfd_signed_vma got_entry, fdgot_entry, fd_entry;
2539 +  /* The offsets of the PLT entries assigned to symbol+addend,
2540 +     non-lazy and lazy, respectively.  If unassigned, should be
2541 +     (bfd_vma)-1.  */
2542 +  bfd_vma plt_entry;
2543 +  bfd_vma plt_trampoline_entry;
2544 +
2545 +  /* plt_type is 1 for Sequence type 2 (0 - 255) it is 2 for > 255 */
2546 +  bfd_vma plt_type;
2547 +
2548 +  /* rel_offset. Plt relocation offset need to be encoded into the plt entry. */
2549 +  bfd_vma rel_offset;
2550 +
2551 +  /* bfd_vma lzplt_entry; not used in ubicom32 */
2552 +};
2553 +
2554 +/* Compute the total GOT size required by each symbol in each range.
2555 +   Symbols may require up to 4 words in the GOT: an entry pointing to
2556 +   the symbol, an entry pointing to its function descriptor, and a
2557 +   private function descriptors taking two words.  */
2558 +
2559 +#if 0
2560 +static bfd_vma plt_code[] = {
2561 +  0xc90f0000,  //movei d15,#0
2562 +  0x0123e30f,  //lea.4 a3,(a0,d15)
2563 +  0x0124630f,  //move.4 a4,(a0,d15)
2564 +  0x01206461,  //move.4 a0,4(a3)
2565 +  0xf0800080,  //calli a4,0(a4)
2566 +};
2567 +#endif
2568 +
2569 +static bfd_vma plt_trampoline[] = {
2570 +  0xc9280000,   //     movei mac_hi,#0
2571 +  0x00002400,   //     ret (a0)
2572 +};
2573 +
2574 +static bfd_vma plt_code_seq1[] = {
2575 +  0xc90fffe8,  //movei d15,#-24
2576 +  0x0123e30f,  //lea.4 a3,(a0,d15)
2577 +  0x01206461,  //move.4 a0,4(a3)
2578 +  0x00002460,  //ret (a3)
2579 +};
2580 +
2581 +static bfd_vma plt_code_seq2[] = {
2582 +  0x0123f71f,   //     pdec a3,4(a0)
2583 +  0x01206461,   //     move.4 a0,4(a3)
2584 +  0x00002460,   //     ret (a3)
2585 +};
2586 +
2587 +#define NUM_PLT_CODE_WORDS (sizeof (plt_code) / sizeof (bfd_vma))
2588 +#define LZPLT_NORMAL_SIZE (sizeof(plt_code))
2589 +
2590 +#define NUM_PLT_CODE_WORDS_SEQ1 (sizeof (plt_code_seq1) / sizeof (bfd_vma))
2591 +#define LZPLT_SIZE_SEQ1 (sizeof(plt_code_seq1))
2592 +
2593 +#define NUM_PLT_CODE_WORDS_SEQ2 (sizeof (plt_code_seq2) / sizeof (bfd_vma))
2594 +#define LZPLT_SIZE_SEQ2 (sizeof(plt_code_seq2))
2595 +
2596 +#define NUM_PLT_TRAMPOLINE_WORDS (sizeof (plt_trampoline) / sizeof (bfd_vma))
2597 +#define PLT_TRAMPOLINE_SIZE (sizeof(plt_trampoline))
2598 +
2599 +//#define FUNCTION_DESCRIPTOR_SIZE 12
2600 +#define FUNCTION_DESCRIPTOR_SIZE 8
2601 +/* Decide whether a reference to a symbol can be resolved locally or
2602 +   not.  If the symbol is protected, we want the local address, but
2603 +   its function descriptor must be assigned by the dynamic linker.  */
2604 +#define UBICOM32FPIC_SYM_LOCAL(INFO, H) \
2605 +  (_bfd_elf_symbol_refs_local_p ((H), (INFO), 1) \
2606 +   || ! elf_hash_table (INFO)->dynamic_sections_created)
2607 +#define UBICOM32FPIC_FUNCDESC_LOCAL(INFO, H) \
2608 +  ((H)->dynindx == -1 || ! elf_hash_table (INFO)->dynamic_sections_created)
2609 +
2610 +
2611 +static int
2612 +ubicom32fdpic_count_got_plt_entries (void **entryp, void *dinfo_)
2613 +{
2614 +  struct ubicom32fdpic_relocs_info *entry = *entryp;
2615 +  struct _ubicom32fdpic_dynamic_got_info *dinfo = dinfo_;
2616 +  unsigned relocs = 0, fixups = 0;
2617 +
2618 +  /* Allocate space for a GOT entry pointing to the symbol.  */
2619 +  if (entry->gotoffset_lo)
2620 +    {
2621 +      dinfo->gotoffset_lo += 4;
2622 +      entry->relocs32++;
2623 +    }
2624 +
2625 +  /* Allocate space for a GOT entry pointing to the function
2626 +     descriptor.  */
2627 +  if (entry->fd_gotoffset_lo)
2628 +    {
2629 +      dinfo->gotoffset_lo += 4;
2630 +      entry->relocsfd++;
2631 +    }
2632 +  else if (entry->fd_gotoffset_hi)
2633 +    {
2634 +      dinfo->gotoffset_lo += 4;
2635 +      entry->relocsfd++;
2636 +    }
2637 +
2638 +  /* Decide whether we need a PLT entry, a function descriptor in the
2639 +     GOT, and a lazy PLT entry for this symbol.  */
2640 +  entry->plt = entry->call
2641 +    && entry->symndx == -1 && ! UBICOM32FPIC_SYM_LOCAL (dinfo->info, entry->d.h)
2642 +    && elf_hash_table (dinfo->info)->dynamic_sections_created;
2643 +  entry->privfd = entry->plt
2644 +    || ((entry->fd_gotoffset_lo || entry->fd_gotoffset_hi || entry->fd)
2645 +       && (entry->symndx != -1
2646 +           || UBICOM32FPIC_FUNCDESC_LOCAL (dinfo->info, entry->d.h)));
2647 +  entry->lazyplt = entry->privfd
2648 +    && entry->symndx == -1 && ! UBICOM32FPIC_SYM_LOCAL (dinfo->info, entry->d.h)
2649 +    && ! (dinfo->info->flags & DF_BIND_NOW)
2650 +    && elf_hash_table (dinfo->info)->dynamic_sections_created;
2651 +
2652 +  /* Allocate space for a function descriptor.  */
2653 +  if (entry->privfd && entry->plt)
2654 +    {
2655 +      dinfo->fdplt += FUNCTION_DESCRIPTOR_SIZE;
2656 +      entry->relocsfdv++;
2657 +    }
2658 +  else if (entry->privfd)
2659 +    {
2660 +      /* privfd with plt = 0 */
2661 +      //printf("Privfd set with plt 0 gotoff_lo = %d fd_gotoffset_lo = %d entry = 0x%x\n", entry->gotoffset_lo, entry->fd_gotoffset_lo, entry);
2662 +      //printf("symnxd = 0x%x sym_local = %d funcdesc_local = %d\n", entry->symndx,
2663 +      //     UBICOM32FPIC_SYM_LOCAL (dinfo->info, entry->d.h),
2664 +      //     UBICOM32FPIC_FUNCDESC_LOCAL (dinfo->info, entry->d.h));
2665 +      //printf("Name = %s\n\n", entry->d.h->root.root.string);
2666 +      dinfo->privfdplt += FUNCTION_DESCRIPTOR_SIZE;
2667 +      entry->relocsfdv++;
2668 +    }
2669 +
2670 +
2671 +  if (entry->lazyplt)
2672 +    {
2673 +      //dinfo->lzplt += LZPLT_NORMAL_SIZE;
2674 +      dinfo->num_plts++;
2675 +
2676 +#if 0
2677 +      if (dinfo->num_plts > 256)
2678 +       dinfo->lzplt += LZPLT_SIZE_SEQ1;
2679 +      else
2680 +       dinfo->lzplt += LZPLT_SIZE_SEQ2;
2681 +
2682 +      DPRINTF("lzplt %d num_plt %d\n",  dinfo->lzplt, dinfo->num_plts);
2683 +#endif
2684 +    }
2685 +
2686 +  if (!dinfo->info->executable || dinfo->info->pie)
2687 +    relocs = entry->relocs32 + entry->relocsfd + entry->relocsfdv;
2688 +  else
2689 +    {
2690 +      if (entry->symndx != -1 || UBICOM32FPIC_SYM_LOCAL (dinfo->info, entry->d.h))
2691 +       {
2692 +         if (entry->symndx != -1
2693 +             || entry->d.h->root.type != bfd_link_hash_undefweak)
2694 +           fixups += entry->relocs32 + 2 * entry->relocsfdv;
2695 +       }
2696 +      else
2697 +       relocs += entry->relocs32 + entry->relocsfdv;
2698 +
2699 +      if (entry->symndx != -1
2700 +         || UBICOM32FPIC_FUNCDESC_LOCAL (dinfo->info, entry->d.h))
2701 +       {
2702 +         if (entry->symndx != -1
2703 +             || entry->d.h->root.type != bfd_link_hash_undefweak)
2704 +           fixups += entry->relocsfd;
2705 +       }
2706 +      else
2707 +       relocs += entry->relocsfd;
2708 +    }
2709 +
2710 +  entry->dynrelocs += relocs;
2711 +  entry->fixups += fixups;
2712 +  dinfo->relocs += relocs;
2713 +  dinfo->fixups += fixups;
2714 +
2715 +  return 1;
2716 +}
2717 +
2718 +/* Create a Ubicom32 ELF linker hash table.  */
2719 +static struct bfd_link_hash_table *
2720 +ubicom32fdpic_elf_link_hash_table_create (bfd *abfd)
2721 +{
2722 +  struct ubicom32fdpic_elf_link_hash_table *ret;
2723 +  bfd_size_type amt = sizeof (struct ubicom32fdpic_elf_link_hash_table);
2724 +
2725 +  ret = bfd_zalloc (abfd, amt);
2726 +  if (ret == NULL)
2727 +    return NULL;
2728 +
2729 +  if (!_bfd_elf_link_hash_table_init (&ret->elf, abfd,
2730 +                                     _bfd_elf_link_hash_newfunc,
2731 +                                     sizeof (struct elf_link_hash_entry)))
2732 +    {
2733 +      free (ret);
2734 +      return NULL;
2735 +    }
2736 +
2737 +  return &ret->elf.root;
2738 +}
2739 +
2740 +/* Compute a hash with the key fields of an ubicom32fdpic_relocs_info entry.  */
2741 +static hashval_t
2742 +ubicom32fdpic_relocs_info_hash (const void *entry_)
2743 +{
2744 +  const struct ubicom32fdpic_relocs_info *entry = entry_;
2745 +
2746 +  return (entry->symndx == -1
2747 +         ? (long) entry->d.h->root.root.hash
2748 +         : entry->symndx + (long) entry->d.abfd->id * 257) + entry->addend;
2749 +}
2750 +
2751 +/* Test whether the key fields of two ubicom32fdpic_relocs_info entries are
2752 +   identical.  */
2753 +static int
2754 +ubicom32fdpic_relocs_info_eq (const void *entry1, const void *entry2)
2755 +{
2756 +  const struct ubicom32fdpic_relocs_info *e1 = entry1;
2757 +  const struct ubicom32fdpic_relocs_info *e2 = entry2;
2758 +
2759 +  return e1->symndx == e2->symndx && e1->addend == e2->addend
2760 +    && (e1->symndx == -1 ? e1->d.h == e2->d.h : e1->d.abfd == e2->d.abfd);
2761 +}
2762 +
2763 +/* Find or create an entry in a hash table HT that matches the key
2764 +   fields of the given ENTRY.  If it's not found, memory for a new
2765 +   entry is allocated in ABFD's obstack.  */
2766 +static struct ubicom32fdpic_relocs_info *
2767 +ubicom32fdpic_relocs_info_find (struct htab *ht,
2768 +                               bfd *abfd,
2769 +                               const struct ubicom32fdpic_relocs_info *entry,
2770 +                               enum insert_option insert)
2771 +{
2772 +  struct ubicom32fdpic_relocs_info **loc =
2773 +    (struct ubicom32fdpic_relocs_info **) htab_find_slot (ht, entry, insert);
2774 +
2775 +  if (! loc)
2776 +    return NULL;
2777 +
2778 +  if (*loc)
2779 +    return *loc;
2780 +
2781 +  *loc = bfd_zalloc (abfd, sizeof (**loc));
2782 +
2783 +  if (! *loc)
2784 +    return *loc;
2785 +
2786 +  (*loc)->symndx = entry->symndx;
2787 +  (*loc)->d = entry->d;
2788 +  (*loc)->addend = entry->addend;
2789 +  (*loc)->plt_entry = (bfd_vma)-1;
2790 +  /* (*loc)->lzplt_entry = (bfd_vma)-1; */
2791 +
2792 +  return *loc;
2793 +}
2794 +
2795 +/* Obtain the address of the entry in HT associated with H's symbol +
2796 +   addend, creating a new entry if none existed.  ABFD is only used
2797 +   for memory allocation purposes.  */
2798 +inline static struct ubicom32fdpic_relocs_info *
2799 +ubicom32fdpic_relocs_info_for_global (struct htab *ht,
2800 +                                     bfd *abfd,
2801 +                                     struct elf_link_hash_entry *h,
2802 +                                     bfd_vma addend,
2803 +                                     enum insert_option insert)
2804 +{
2805 +  struct ubicom32fdpic_relocs_info entry;
2806 +
2807 +  entry.symndx = -1;
2808 +  entry.d.h = h;
2809 +  entry.addend = addend;
2810 +
2811 +  return ubicom32fdpic_relocs_info_find (ht, abfd, &entry, insert);
2812 +}
2813 +
2814 +/* Obtain the address of the entry in HT associated with the SYMNDXth
2815 +   local symbol of the input bfd ABFD, plus the addend, creating a new
2816 +   entry if none existed.  */
2817 +inline static struct ubicom32fdpic_relocs_info *
2818 +ubicom32fdpic_relocs_info_for_local (struct htab *ht,
2819 +                                    bfd *abfd,
2820 +                                    long symndx,
2821 +                                    bfd_vma addend,
2822 +                                    enum insert_option insert)
2823 +{
2824 +  struct ubicom32fdpic_relocs_info entry;
2825 +
2826 +  entry.symndx = symndx;
2827 +  entry.d.abfd = abfd;
2828 +  entry.addend = addend;
2829 +
2830 +  return ubicom32fdpic_relocs_info_find (ht, abfd, &entry, insert);
2831 +}
2832 +
2833 +/* Merge fields set by check_relocs() of two entries that end up being
2834 +   mapped to the same (presumably global) symbol.  */
2835 +
2836 +inline static void
2837 +ubicom32fdpic_pic_merge_early_relocs_info (struct ubicom32fdpic_relocs_info *e2,
2838 +                                          struct ubicom32fdpic_relocs_info const *e1)
2839 +{
2840 +  e2->gotoffset_lo |= e1->gotoffset_lo;
2841 +  e2->gotoffset_hi |= e1->gotoffset_hi;
2842 +  e2->fd_gotoffset_lo |= e1->fd_gotoffset_lo;
2843 +  e2->fd_gotoffset_hi |= e1->fd_gotoffset_hi;
2844 +  e2->fd |= e1->fd;
2845 +  e2->gotoff |= e1->gotoff;
2846 +  e2->call |= e1->call;
2847 +  e2->sym |= e1->sym;
2848 +}
2849 +
2850 +/* Add a dynamic relocation to the SRELOC section.  */
2851 +
2852 +inline static bfd_vma
2853 +ubicom32fdpic_add_dyn_reloc (bfd *output_bfd, asection *sreloc, bfd_vma offset,
2854 +                            int reloc_type, long dynindx, bfd_vma addend,
2855 +                            struct ubicom32fdpic_relocs_info *entry)
2856 +{
2857 +  Elf_Internal_Rela outrel;
2858 +  bfd_vma reloc_offset;
2859 +
2860 +  outrel.r_offset = offset;
2861 +  outrel.r_info = ELF32_R_INFO (dynindx, reloc_type);
2862 +  outrel.r_addend = addend;
2863 +
2864 +  reloc_offset = sreloc->reloc_count * sizeof (Elf32_External_Rel);
2865 +  BFD_ASSERT (reloc_offset < sreloc->size);
2866 +  bfd_elf32_swap_reloc_out (output_bfd, &outrel,
2867 +                           sreloc->contents + reloc_offset);
2868 +  sreloc->reloc_count++;
2869 +
2870 +  /* If the entry's index is zero, this relocation was probably to a
2871 +     linkonce section that got discarded.  We reserved a dynamic
2872 +     relocation, but it was for another entry than the one we got at
2873 +     the time of emitting the relocation.  Unfortunately there's no
2874 +     simple way for us to catch this situation, since the relocation
2875 +     is cleared right before calling relocate_section, at which point
2876 +     we no longer know what the relocation used to point to.  */
2877 +  if (entry->symndx)
2878 +    {
2879 +      BFD_ASSERT (entry->dynrelocs > 0);
2880 +      entry->dynrelocs--;
2881 +    }
2882 +
2883 +  return reloc_offset;
2884 +}
2885 +
2886 +/* Add a fixup to the ROFIXUP section.  */
2887 +
2888 +static bfd_vma
2889 +ubicom32fdpic_add_rofixup (bfd *output_bfd, asection *rofixup, bfd_vma offset,
2890 +                          struct ubicom32fdpic_relocs_info *entry)
2891 +{
2892 +  bfd_vma fixup_offset;
2893 +
2894 +  if (rofixup->flags & SEC_EXCLUDE)
2895 +    return -1;
2896 +
2897 +  fixup_offset = rofixup->reloc_count * 4;
2898 +  if (rofixup->contents)
2899 +    {
2900 +      BFD_ASSERT (fixup_offset < rofixup->size);
2901 +      bfd_put_32 (output_bfd, offset, rofixup->contents + fixup_offset);
2902 +    }
2903 +  rofixup->reloc_count++;
2904 +
2905 +  if (entry && entry->symndx)
2906 +    {
2907 +      /* See discussion about symndx == 0 in _ubicom32fdpic_add_dyn_reloc
2908 +        above.  */
2909 +      BFD_ASSERT (entry->fixups > 0);
2910 +      entry->fixups--;
2911 +    }
2912 +
2913 +  return fixup_offset;
2914 +}
2915 +
2916 +/* Find the segment number in which OSEC, and output section, is
2917 +   located.  */
2918 +
2919 +static unsigned
2920 +ubicom32fdpic_osec_to_segment (bfd *output_bfd, asection *osec)
2921 +{
2922 +  Elf_Internal_Phdr *p = _bfd_elf_find_segment_containing_section (output_bfd, osec);
2923 +
2924 +  return (p != NULL) ? p - elf_tdata (output_bfd)->phdr : -1;
2925 +}
2926 +
2927 +inline static bfd_boolean
2928 +ubicom32fdpic_osec_readonly_p (bfd *output_bfd, asection *osec)
2929 +{
2930 +  unsigned seg = ubicom32fdpic_osec_to_segment (output_bfd, osec);
2931 +
2932 +  return ! (elf_tdata (output_bfd)->phdr[seg].p_flags & PF_W);
2933 +}
2934 +
2935 +#if 0
2936 +static bfd_vma plt_trampoline[] = {
2937 +  0x00002400,  //ret (a0)
2938 +};
2939 +#endif
2940 +
2941 +/* Generate relocations for GOT entries, function descriptors, and
2942 +   code for PLT and lazy PLT entries.  */
2943 +
2944 +static bfd_boolean
2945 +ubicom32fdpic_emit_got_relocs_plt_entries (struct ubicom32fdpic_relocs_info *entry,
2946 +                                          bfd *output_bfd,
2947 +                                          struct bfd_link_info *info,
2948 +                                          asection *sec,
2949 +                                          Elf_Internal_Sym *sym,
2950 +                                          bfd_vma addend)
2951 +
2952 +{
2953 +  bfd_vma fd_lazy_rel_offset = (bfd_vma)-1;
2954 +  int dynindx = -1;
2955 +
2956 +  if (entry->done)
2957 +    return TRUE;
2958 +  entry->done = 1;
2959 +
2960 +  if (entry->got_entry || entry->fdgot_entry || entry->fd_entry)
2961 +    {
2962 +      DPRINTF(" emit %p got %d fdgot %d fd %d addend %d\n", entry, entry->got_entry, entry->fdgot_entry, entry->fd_entry, addend);
2963 +      /* If the symbol is dynamic, consider it for dynamic
2964 +        relocations, otherwise decay to section + offset.  */
2965 +      if (entry->symndx == -1 && entry->d.h->dynindx != -1)
2966 +       dynindx = entry->d.h->dynindx;
2967 +      else
2968 +       {
2969 +         if (sec->output_section
2970 +             && ! bfd_is_abs_section (sec->output_section)
2971 +             && ! bfd_is_und_section (sec->output_section))
2972 +           dynindx = elf_section_data (sec->output_section)->dynindx;
2973 +         else
2974 +           dynindx = 0;
2975 +       }
2976 +    }
2977 +
2978 +  /* Generate relocation for GOT entry pointing to the symbol.  */
2979 +  if (entry->got_entry)
2980 +    {
2981 +      DPRINTF(" emit got entry %d:%p\n", entry->got_entry, entry);
2982 +
2983 +      int idx = dynindx;
2984 +      bfd_vma ad = addend;
2985 +
2986 +      /* If the symbol is dynamic but binds locally, use
2987 +        section+offset.  */
2988 +      if (sec && (entry->symndx != -1
2989 +                 || UBICOM32FDPIC_SYM_LOCAL (info, entry->d.h)))
2990 +       {
2991 +         if (entry->symndx == -1)
2992 +           ad += entry->d.h->root.u.def.value;
2993 +         else
2994 +           ad += sym->st_value;
2995 +         ad += sec->output_offset;
2996 +         if (sec->output_section && elf_section_data (sec->output_section))
2997 +           idx = elf_section_data (sec->output_section)->dynindx;
2998 +         else
2999 +           idx = 0;
3000 +       }
3001 +
3002 +      /* If we're linking an executable at a fixed address, we can
3003 +        omit the dynamic relocation as long as the symbol is local to
3004 +        this module.  */
3005 +      if (info->executable && !info->pie
3006 +         && (entry->symndx != -1
3007 +             || UBICOM32FDPIC_SYM_LOCAL (info, entry->d.h)))
3008 +       {
3009 +         if (sec)
3010 +           ad += sec->output_section->vma;
3011 +         if (entry->symndx != -1
3012 +             || entry->d.h->root.type != bfd_link_hash_undefweak)
3013 +           ubicom32fdpic_add_rofixup (output_bfd,
3014 +                                      ubicom32fdpic_gotfixup_section (info),
3015 +                                      ubicom32fdpic_got_section (info)->output_section->vma
3016 +                                      + ubicom32fdpic_got_section (info)->output_offset
3017 +                                      + ubicom32fdpic_got_initial_offset (info)
3018 +                                      + entry->got_entry, entry);
3019 +       }
3020 +      else
3021 +       ubicom32fdpic_add_dyn_reloc (output_bfd, ubicom32fdpic_gotrel_section (info),
3022 +                                    _bfd_elf_section_offset
3023 +                                    (output_bfd, info,
3024 +                                     ubicom32fdpic_got_section (info),
3025 +                                     ubicom32fdpic_got_initial_offset (info)
3026 +                                     + entry->got_entry)
3027 +                                    + ubicom32fdpic_got_section (info)
3028 +                                    ->output_section->vma
3029 +                                    + ubicom32fdpic_got_section (info)->output_offset,
3030 +                                    R_UBICOM32_32, idx, ad, entry);
3031 +
3032 +      bfd_put_32 (output_bfd, ad,
3033 +                 ubicom32fdpic_got_section (info)->contents
3034 +                 + ubicom32fdpic_got_initial_offset (info)
3035 +                 + entry->got_entry);
3036 +    }
3037 +
3038 +  /* Generate relocation for GOT entry pointing to a canonical
3039 +     function descriptor.  */
3040 +  if (entry->fdgot_entry)
3041 +    {
3042 +      DPRINTF(" emit got fdgot entry %d:%p\n", entry->fdgot_entry, entry);
3043 +
3044 +      int reloc, idx;
3045 +      bfd_vma ad = 0;
3046 +
3047 +      if (! (entry->symndx == -1
3048 +            && entry->d.h->root.type == bfd_link_hash_undefweak
3049 +            && UBICOM32FDPIC_SYM_LOCAL (info, entry->d.h)))
3050 +       {
3051 +         /* If the symbol is dynamic and there may be dynamic symbol
3052 +            resolution because we are, or are linked with, a shared
3053 +            library, emit a FUNCDESC relocation such that the dynamic
3054 +            linker will allocate the function descriptor.  If the
3055 +            symbol needs a non-local function descriptor but binds
3056 +            locally (e.g., its visibility is protected, emit a
3057 +            dynamic relocation decayed to section+offset.  */
3058 +         if (entry->symndx == -1
3059 +             && ! UBICOM32FDPIC_FUNCDESC_LOCAL (info, entry->d.h)
3060 +             && UBICOM32FDPIC_SYM_LOCAL (info, entry->d.h)
3061 +             && !(info->executable && !info->pie))
3062 +           {
3063 +             reloc = R_UBICOM32_FUNCDESC;
3064 +             idx = elf_section_data (entry->d.h->root.u.def.section
3065 +                                     ->output_section)->dynindx;
3066 +             ad = entry->d.h->root.u.def.section->output_offset
3067 +               + entry->d.h->root.u.def.value;
3068 +           }
3069 +         else if (entry->symndx == -1
3070 +                  && ! UBICOM32FDPIC_FUNCDESC_LOCAL (info, entry->d.h))
3071 +           {
3072 +             reloc = R_UBICOM32_FUNCDESC;
3073 +             idx = dynindx;
3074 +             ad = addend;
3075 +             if (ad)
3076 +               return FALSE;
3077 +           }
3078 +         else
3079 +           {
3080 +             /* Otherwise, we know we have a private function descriptor,
3081 +                so reference it directly.  */
3082 +             if (elf_hash_table (info)->dynamic_sections_created)
3083 +               BFD_ASSERT (entry->privfd);
3084 +             reloc = R_UBICOM32_32;
3085 +             idx = elf_section_data (ubicom32fdpic_got_section (info)
3086 +                                     ->output_section)->dynindx;
3087 +             ad = ubicom32fdpic_got_section (info)->output_offset
3088 +               + ubicom32fdpic_got_initial_offset (info) + entry->fd_entry;
3089 +           }
3090 +
3091 +         /* If there is room for dynamic symbol resolution, emit the
3092 +            dynamic relocation.  However, if we're linking an
3093 +            executable at a fixed location, we won't have emitted a
3094 +            dynamic symbol entry for the got section, so idx will be
3095 +            zero, which means we can and should compute the address
3096 +            of the private descriptor ourselves.  */
3097 +         if (info->executable && !info->pie
3098 +             && (entry->symndx != -1
3099 +                 || UBICOM32FDPIC_FUNCDESC_LOCAL (info, entry->d.h)))
3100 +           {
3101 +             ad += ubicom32fdpic_got_section (info)->output_section->vma;
3102 +             ubicom32fdpic_add_rofixup (output_bfd,
3103 +                                        ubicom32fdpic_gotfixup_section (info),
3104 +                                        ubicom32fdpic_got_section (info)
3105 +                                        ->output_section->vma
3106 +                                        + ubicom32fdpic_got_section (info)
3107 +                                        ->output_offset
3108 +                                        + ubicom32fdpic_got_initial_offset (info)
3109 +                                        + entry->fdgot_entry, entry);
3110 +           }
3111 +         else
3112 +           ubicom32fdpic_add_dyn_reloc (output_bfd,
3113 +                                        ubicom32fdpic_gotrel_section (info),
3114 +                                        _bfd_elf_section_offset
3115 +                                        (output_bfd, info,
3116 +                                         ubicom32fdpic_got_section (info),
3117 +                                         ubicom32fdpic_got_initial_offset (info)
3118 +                                         + entry->fdgot_entry)
3119 +                                        + ubicom32fdpic_got_section (info)
3120 +                                        ->output_section->vma
3121 +                                        + ubicom32fdpic_got_section (info)
3122 +                                        ->output_offset,
3123 +                                        reloc, idx, ad, entry);
3124 +       }
3125 +
3126 +      bfd_put_32 (output_bfd, ad,
3127 +                 ubicom32fdpic_got_section (info)->contents
3128 +                 + ubicom32fdpic_got_initial_offset (info)
3129 +                 + entry->fdgot_entry);
3130 +    }
3131 +
3132 +  /* Generate relocation to fill in a private function descriptor in
3133 +     the GOT.  */
3134 +  if (entry->fd_entry)
3135 +    {
3136 +
3137 +      int idx = dynindx;
3138 +      bfd_vma ad = addend;
3139 +      bfd_vma ofst;
3140 +      long lowword, highword;
3141 +
3142 +      /* If the symbol is dynamic but binds locally, use
3143 +        section+offset.  */
3144 +      if (sec && (entry->symndx != -1
3145 +                 || UBICOM32FDPIC_SYM_LOCAL (info, entry->d.h)))
3146 +       {
3147 +         if (entry->symndx == -1)
3148 +           ad += entry->d.h->root.u.def.value;
3149 +         else
3150 +           ad += sym->st_value;
3151 +         ad += sec->output_offset;
3152 +         if (sec->output_section && elf_section_data (sec->output_section))
3153 +           idx = elf_section_data (sec->output_section)->dynindx;
3154 +         else
3155 +           idx = 0;
3156 +       }
3157 +
3158 +      /* If we're linking an executable at a fixed address, we can
3159 +        omit the dynamic relocation as long as the symbol is local to
3160 +        this module.  */
3161 +      if (info->executable && !info->pie
3162 +         && (entry->symndx != -1 || UBICOM32FDPIC_SYM_LOCAL (info, entry->d.h)))
3163 +       {
3164 +         if (sec)
3165 +           ad += sec->output_section->vma;
3166 +         ofst = 0;
3167 +         if (entry->symndx != -1
3168 +             || entry->d.h->root.type != bfd_link_hash_undefweak)
3169 +           {
3170 +             ubicom32fdpic_add_rofixup (output_bfd,
3171 +                                        ubicom32fdpic_gotfixup_section (info),
3172 +                                        ubicom32fdpic_got_section (info)
3173 +                                        ->output_section->vma
3174 +                                        + ubicom32fdpic_got_section (info)
3175 +                                        ->output_offset
3176 +                                        + ubicom32fdpic_got_initial_offset (info)
3177 +                                        + entry->fd_entry, entry);
3178 +             ubicom32fdpic_add_rofixup (output_bfd,
3179 +                                        ubicom32fdpic_gotfixup_section (info),
3180 +                                        ubicom32fdpic_got_section (info)
3181 +                                        ->output_section->vma
3182 +                                        + ubicom32fdpic_got_section (info)
3183 +                                        ->output_offset
3184 +                                        + ubicom32fdpic_got_initial_offset (info)
3185 +                                        + entry->fd_entry + 4, entry);
3186 +           }
3187 +       }
3188 +      else
3189 +       {
3190 +         ofst
3191 +           = ubicom32fdpic_add_dyn_reloc (output_bfd,
3192 +                                          entry->lazyplt
3193 +                                          ? ubicom32fdpic_pltrel_section (info)
3194 +                                          : ubicom32fdpic_gotrel_section (info),
3195 +                                          _bfd_elf_section_offset
3196 +                                          (output_bfd, info,
3197 +                                           ubicom32fdpic_got_section (info),
3198 +                                           ubicom32fdpic_got_initial_offset (info)
3199 +                                           + entry->fd_entry)
3200 +                                          + ubicom32fdpic_got_section (info)
3201 +                                          ->output_section->vma
3202 +                                          + ubicom32fdpic_got_section (info)
3203 +                                          ->output_offset,
3204 +                                          R_UBICOM32_FUNCDESC_VALUE, idx, ad, entry);
3205 +       }
3206 +
3207 +      /* If we've omitted the dynamic relocation, just emit the fixed
3208 +        addresses of the symbol and of the local GOT base offset.  */
3209 +      if (info->executable && !info->pie && sec && sec->output_section)
3210 +       {
3211 +         lowword = ad;
3212 +         highword = ubicom32fdpic_got_section (info)->output_section->vma
3213 +           + ubicom32fdpic_got_section (info)->output_offset
3214 +           + ubicom32fdpic_got_initial_offset (info);
3215 +       }
3216 +      else if (entry->lazyplt)
3217 +       {
3218 +         if (ad)
3219 +           return FALSE;
3220 +
3221 +         fd_lazy_rel_offset = ofst;
3222 +
3223 +         /* A function descriptor used for lazy or local resolving is
3224 +            initialized such that its high word contains the output
3225 +            section index in which the PLT entries are located, and
3226 +            the low word contains the address to the base of the PLT.
3227 +            That location contains the PLT trampoline instruction ret 0(a0).
3228 +            assigned to that section.  */
3229 +         lowword =  ubicom32fdpic_plt_section (info)->output_offset
3230 +           + ubicom32fdpic_plt_section (info)->output_section->vma + entry->plt_trampoline_entry;
3231 +         highword = ubicom32fdpic_osec_to_segment
3232 +           (output_bfd, ubicom32fdpic_plt_section (info)->output_section);
3233 +       }
3234 +      else
3235 +       {
3236 +         /* A function descriptor for a local function gets the index
3237 +            of the section.  For a non-local function, it's
3238 +            disregarded.  */
3239 +         lowword = ad;
3240 +         if (entry->symndx == -1 && entry->d.h->dynindx != -1
3241 +             && entry->d.h->dynindx == idx)
3242 +           highword = 0;
3243 +         else
3244 +           highword = ubicom32fdpic_osec_to_segment
3245 +             (output_bfd, sec->output_section);
3246 +       }
3247 +
3248 +      DPRINTF(" emit got fd_entry %d:%p lw 0x%x hw 0x%x fd_l_r_off 0x%x\n", entry->fd_entry, entry, lowword, highword, fd_lazy_rel_offset);
3249 +
3250 +
3251 +      bfd_put_32 (output_bfd, lowword,
3252 +                 ubicom32fdpic_got_section (info)->contents
3253 +                 + ubicom32fdpic_got_initial_offset (info)
3254 +                 + entry->fd_entry);
3255 +      bfd_put_32 (output_bfd, highword,
3256 +                 ubicom32fdpic_got_section (info)->contents
3257 +                 + ubicom32fdpic_got_initial_offset (info)
3258 +                 + entry->fd_entry + 4);
3259 +
3260 +#if 0
3261 +      /* Load the fixup offset here. */
3262 +      bfd_put_32 (output_bfd, fd_lazy_rel_offset,
3263 +                 ubicom32fdpic_got_section (info)->contents
3264 +                 + ubicom32fdpic_got_initial_offset (info)
3265 +                 + entry->fd_entry + 8);
3266 +#endif
3267 +
3268 +      entry->rel_offset = fd_lazy_rel_offset;
3269 +    }
3270 +
3271 +  /* Generate code for the PLT entry.  */
3272 +  if (entry->plt_entry != (bfd_vma) -1)
3273 +    {
3274 +      static output_trampoline_code = 1;
3275 +      bfd_byte *plt_output_code = ubicom32fdpic_plt_section (info)->contents;
3276 +      int i;
3277 +      bfd_vma *plt_code;
3278 +
3279 +      DPRINTF(" emit fd entry %x:%p plt=%2x code=%p\n", entry->fd_entry, entry, entry->plt_entry, plt_output_code);
3280 +
3281 +#if 0
3282 +      if (output_trampoline_code)
3283 +       {
3284 +         /* output the trampoline code.*/
3285 +         bfd_put_32 (output_bfd, plt_trampoline[0], plt_output_code);
3286 +       }
3287 +#endif
3288 +
3289 +      /* output the trampoline entry. */
3290 +
3291 +      plt_output_code += entry->plt_trampoline_entry;
3292 +      plt_code = plt_trampoline;
3293 +      plt_code[0] = (plt_code[0] & 0xFFFF0000) | (entry->rel_offset &0xffff);
3294 +      bfd_put_32 (output_bfd, plt_code[0], plt_output_code);
3295 +      bfd_put_32 (output_bfd, plt_code[1], plt_output_code + 4);
3296 +
3297 +
3298 +      /* output the plt itself. */
3299 +      plt_output_code = ubicom32fdpic_plt_section (info)->contents;
3300 +      plt_output_code += entry->plt_entry;
3301 +      BFD_ASSERT (entry->fd_entry);
3302 +
3303 +      if (entry->plt_type == 2)
3304 +       {
3305 +         bfd_vma data_lo = (entry->fd_entry >> 2) & 0xff;
3306 +
3307 +         /* Output seqence 2. */
3308 +         plt_code = plt_code_seq2;
3309 +
3310 +         /* Code the entry into the PDEC instruction. */
3311 +         plt_code[0] &= 0xFFFFF8E0;
3312 +         plt_code[0] |= (data_lo & 0x1F);
3313 +         plt_code[0] |= (data_lo & 0xE0) << 3;
3314 +
3315 +         /* Write out the sequence. */
3316 +         for (i = 0; i < NUM_PLT_CODE_WORDS_SEQ2; i++)
3317 +           {
3318 +             bfd_put_32 (output_bfd, plt_code[i], plt_output_code);
3319 +             plt_output_code += 4;
3320 +           }
3321 +       }
3322 +      else if (entry->plt_type == 1)
3323 +       {
3324 +         /* Outupt sequence 1 */
3325 +         plt_code = plt_code_seq1;
3326 +
3327 +         /* Code the entry into the movei instruction. */
3328 +         plt_code[0] = (plt_code[0] & 0xFFFF0000) | ((entry->fd_entry >> 2) & 0xFFFF);
3329 +
3330 +         /* Write out the sequence. */
3331 +         for (i = 0; i < NUM_PLT_CODE_WORDS_SEQ1; i++)
3332 +           {
3333 +             bfd_put_32 (output_bfd, plt_code[i], plt_output_code);
3334 +             plt_output_code += 4;
3335 +           }
3336 +       }
3337 +      else
3338 +       BFD_ASSERT(0);
3339 +
3340 +#if 0
3341 +      /* We have to output 5 words. The very first movei has to be modified with whatever is in fd_entry. */
3342 +      plt_code[0] = (plt_code[0] & 0xFFFF0000) | ((entry->fd_entry >> 2) & 0xFFFF);
3343 +
3344 +      for (i = 0; i < NUM_PLT_CODE_WORDS; i++)
3345 +       {
3346 +         bfd_put_32 (output_bfd, plt_code[i], plt_output_code);
3347 +         plt_output_code += 4;
3348 +       }
3349 +#endif
3350 +    }
3351 +
3352 +  return TRUE;
3353 +}
3354 +
3355 +\f
3356 +/* Create  a .got section, as well as its additional info field.  This
3357 +   is almost entirely copied from
3358 +   elflink.c:_bfd_elf_create_got_section().  */
3359 +
3360 +static bfd_boolean
3361 +ubicom32fdpic_elf_create_got_section (bfd *abfd, struct bfd_link_info *info)
3362 +{
3363 +  flagword flags, pltflags;
3364 +  asection *s;
3365 +  struct elf_link_hash_entry *h;
3366 +  const struct elf_backend_data *bed = get_elf_backend_data (abfd);
3367 +  int ptralign;
3368 +  int offset;
3369 +
3370 +  /* This function may be called more than once.  */
3371 +  s = bfd_get_section_by_name (abfd, ".got");
3372 +  if (s != NULL && (s->flags & SEC_LINKER_CREATED) != 0)
3373 +    return TRUE;
3374 +
3375 +  /* Machine specific: although pointers are 32-bits wide, we want the
3376 +     GOT to be aligned to a 64-bit boundary, such that function
3377 +     descriptors in it can be accessed with 64-bit loads and
3378 +     stores.  */
3379 +  ptralign = 3;
3380 +
3381 +  flags = (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY
3382 +          | SEC_LINKER_CREATED);
3383 +  pltflags = flags;
3384 +
3385 +  s = bfd_make_section_with_flags (abfd, ".got", flags);
3386 +  if (s == NULL
3387 +      || !bfd_set_section_alignment (abfd, s, ptralign))
3388 +    return FALSE;
3389 +
3390 +  if (bed->want_got_plt)
3391 +    {
3392 +      s = bfd_make_section_with_flags (abfd, ".got.plt", flags);
3393 +      if (s == NULL
3394 +         || !bfd_set_section_alignment (abfd, s, ptralign))
3395 +       return FALSE;
3396 +    }
3397 +
3398 +  if (bed->want_got_sym)
3399 +    {
3400 +      /* Define the symbol _GLOBAL_OFFSET_TABLE_ at the start of the .got
3401 +        (or .got.plt) section.  We don't do this in the linker script
3402 +        because we don't want to define the symbol if we are not creating
3403 +        a global offset table.  */
3404 +      h = _bfd_elf_define_linkage_sym (abfd, info, s, "_GLOBAL_OFFSET_TABLE_");
3405 +      elf_hash_table (info)->hgot = h;
3406 +      if (h == NULL)
3407 +       return FALSE;
3408 +
3409 +      /* Machine-specific: we want the symbol for executables as
3410 +        well.  */
3411 +      if (! bfd_elf_link_record_dynamic_symbol (info, h))
3412 +       return FALSE;
3413 +    }
3414 +
3415 +  /* The first bit of the global offset table is the header.  */
3416 +  s->size += bed->got_header_size;
3417 +
3418 +  /* This is the machine-specific part.  Create and initialize section
3419 +     data for the got.  */
3420 +  if (IS_FDPIC (abfd))
3421 +    {
3422 +      ubicom32fdpic_got_section (info) = s;
3423 +      ubicom32fdpic_relocs_info (info) = htab_try_create (1,
3424 +                                                         ubicom32fdpic_relocs_info_hash,
3425 +                                                         ubicom32fdpic_relocs_info_eq,
3426 +                                                         (htab_del) NULL);
3427 +      if (! ubicom32fdpic_relocs_info (info))
3428 +       return FALSE;
3429 +
3430 +      s = bfd_make_section_with_flags (abfd, ".rel.got",
3431 +                                      (flags | SEC_READONLY));
3432 +      if (s == NULL
3433 +         || ! bfd_set_section_alignment (abfd, s, 2))
3434 +       return FALSE;
3435 +
3436 +      ubicom32fdpic_gotrel_section (info) = s;
3437 +
3438 +      /* Machine-specific.  */
3439 +      s = bfd_make_section_with_flags (abfd, ".rofixup",
3440 +                                      (flags | SEC_READONLY));
3441 +      if (s == NULL
3442 +         || ! bfd_set_section_alignment (abfd, s, 2))
3443 +       return FALSE;
3444 +
3445 +      ubicom32fdpic_gotfixup_section (info) = s;
3446 +      offset = -2048;
3447 +      flags = BSF_GLOBAL;
3448 +    }
3449 +  else
3450 +    {
3451 +      offset = 2048;
3452 +      flags = BSF_GLOBAL | BSF_WEAK;
3453 +    }
3454 +
3455 +  return TRUE;
3456 +}
3457 +
3458 +/* Make sure the got and plt sections exist, and that our pointers in
3459 +   the link hash table point to them.  */
3460 +
3461 +static bfd_boolean
3462 +ubicom32fdpic_elf_create_dynamic_sections (bfd *abfd, struct bfd_link_info *info)
3463 +{  flagword flags, pltflags;
3464 +  asection *s;
3465 +  const struct elf_backend_data *bed = get_elf_backend_data (abfd);
3466 +
3467 +  /* We need to create .plt, .rel[a].plt, .got, .got.plt, .dynbss, and
3468 +     .rel[a].bss sections.  */
3469 +  DPRINTF(" ubicom32fdpic_elf_create_dynamic_sections %p %p\n", abfd, info);
3470 +
3471 +  flags = (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY
3472 +          | SEC_LINKER_CREATED);
3473 +
3474 +  pltflags = flags;
3475 +  pltflags |= SEC_CODE;
3476 +  if (bed->plt_not_loaded)
3477 +    pltflags &= ~ (SEC_CODE | SEC_LOAD | SEC_HAS_CONTENTS);
3478 +  if (bed->plt_readonly)
3479 +    pltflags |= SEC_READONLY;
3480 +
3481 +  s = bfd_make_section_with_flags (abfd, ".plt", pltflags);
3482 +  if (s == NULL
3483 +      || ! bfd_set_section_alignment (abfd, s, bed->plt_alignment))
3484 +    return FALSE;
3485 +  /* Blackfin-specific: remember it.  */
3486 +  ubicom32fdpic_plt_section (info) = s;
3487 +
3488 +  if (bed->want_plt_sym)
3489 +    {
3490 +      /* Define the symbol _PROCEDURE_LINKAGE_TABLE_ at the start of the
3491 +        .plt section.  */
3492 +      struct elf_link_hash_entry *h;
3493 +      struct bfd_link_hash_entry *bh = NULL;
3494 +
3495 +      if (! (_bfd_generic_link_add_one_symbol
3496 +            (info, abfd, "_PROCEDURE_LINKAGE_TABLE_", BSF_GLOBAL, s, 0, NULL,
3497 +             FALSE, get_elf_backend_data (abfd)->collect, &bh)))
3498 +       return FALSE;
3499 +      h = (struct elf_link_hash_entry *) bh;
3500 +      h->def_regular = 1;
3501 +      h->type = STT_OBJECT;
3502 +
3503 +      if (! info->executable
3504 +         && ! bfd_elf_link_record_dynamic_symbol (info, h))
3505 +       return FALSE;
3506 +    }
3507 +
3508 +  /* Blackfin-specific: we want rel relocations for the plt.  */
3509 +  s = bfd_make_section_with_flags (abfd, ".rel.plt", flags | SEC_READONLY);
3510 +  if (s == NULL
3511 +      || ! bfd_set_section_alignment (abfd, s, bed->s->log_file_align))
3512 +    return FALSE;
3513 +  /* Blackfin-specific: remember it.  */
3514 +  ubicom32fdpic_pltrel_section (info) = s;
3515 +
3516 +  /* Blackfin-specific: we want to create the GOT in the Blackfin way.  */
3517 +  if (! ubicom32fdpic_elf_create_got_section (abfd, info))
3518 +    return FALSE;
3519 +
3520 +  /* Blackfin-specific: make sure we created everything we wanted.  */
3521 +  BFD_ASSERT (ubicom32fdpic_got_section (info) && ubicom32fdpic_gotrel_section (info)
3522 +             /* && ubicom32fdpic_gotfixup_section (info) */
3523 +             && ubicom32fdpic_plt_section (info)
3524 +             && ubicom32fdpic_pltrel_section (info));
3525 +
3526 +  if (bed->want_dynbss)
3527 +    {
3528 +      /* The .dynbss section is a place to put symbols which are defined
3529 +        by dynamic objects, are referenced by regular objects, and are
3530 +        not functions.  We must allocate space for them in the process
3531 +        image and use a R_*_COPY reloc to tell the dynamic linker to
3532 +        initialize them at run time.  The linker script puts the .dynbss
3533 +        section into the .bss section of the final image.  */
3534 +      s = bfd_make_section_with_flags (abfd, ".dynbss",
3535 +                                      SEC_ALLOC | SEC_LINKER_CREATED);
3536 +      if (s == NULL)
3537 +       return FALSE;
3538 +
3539 +      /* The .rel[a].bss section holds copy relocs.  This section is not
3540 +     normally needed.  We need to create it here, though, so that the
3541 +     linker will map it to an output section.  We can't just create it
3542 +     only if we need it, because we will not know whether we need it
3543 +     until we have seen all the input files, and the first time the
3544 +     main linker code calls BFD after examining all the input files
3545 +     (size_dynamic_sections) the input sections have already been
3546 +     mapped to the output sections.  If the section turns out not to
3547 +     be needed, we can discard it later.  We will never need this
3548 +     section when generating a shared object, since they do not use
3549 +     copy relocs.  */
3550 +      if (! info->shared)
3551 +       {
3552 +         s = bfd_make_section_with_flags (abfd,
3553 +                                          (bed->default_use_rela_p
3554 +                                           ? ".rela.bss" : ".rel.bss"),
3555 +                                          flags | SEC_READONLY);
3556 +         if (s == NULL
3557 +             || ! bfd_set_section_alignment (abfd, s, bed->s->log_file_align))
3558 +           return FALSE;
3559 +       }
3560 +    }
3561 +
3562 +  return TRUE;
3563 +}
3564 +
3565 +/* We need dynamic symbols for every section, since segments can
3566 +   relocate independently.  */
3567 +static bfd_boolean
3568 +ubicom32fdpic_elf_link_omit_section_dynsym (bfd *output_bfd ATTRIBUTE_UNUSED,
3569 +                                           struct bfd_link_info *info
3570 +                                           ATTRIBUTE_UNUSED,
3571 +                                           asection *p ATTRIBUTE_UNUSED)
3572 +{
3573 +  switch (elf_section_data (p)->this_hdr.sh_type)
3574 +    {
3575 +    case SHT_PROGBITS:
3576 +    case SHT_NOBITS:
3577 +      /* If sh_type is yet undecided, assume it could be
3578 +        SHT_PROGBITS/SHT_NOBITS.  */
3579 +    case SHT_NULL:
3580 +      return FALSE;
3581 +
3582 +      /* There shouldn't be section relative relocations
3583 +        against any other section.  */
3584 +    default:
3585 +      return TRUE;
3586 +    }
3587 +}
3588 +
3589 +/* Look through the relocs for a section during the first phase.
3590 +
3591 +   Besides handling virtual table relocs for gc, we have to deal with
3592 +   all sorts of PIC-related relocations.  We describe below the
3593 +   general plan on how to handle such relocations, even though we only
3594 +   collect information at this point, storing them in hash tables for
3595 +   perusal of later passes.
3596 +
3597 +*/
3598 +static bfd_boolean
3599 +ubicom32fdpic_elf_check_relocs (bfd *abfd, struct bfd_link_info *info,
3600 +                               asection *sec, const Elf_Internal_Rela *relocs)
3601 +{
3602 +  Elf_Internal_Shdr *symtab_hdr;
3603 +  struct elf_link_hash_entry **sym_hashes, **sym_hashes_end;
3604 +  const Elf_Internal_Rela *rel;
3605 +  const Elf_Internal_Rela *rel_end;
3606 +  bfd *dynobj;
3607 +  struct ubicom32fdpic_relocs_info *picrel;
3608 +
3609 +  if (info->relocatable)
3610 +    return TRUE;
3611 +
3612 +  symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
3613 +  sym_hashes = elf_sym_hashes (abfd);
3614 +  sym_hashes_end = sym_hashes + symtab_hdr->sh_size/sizeof(Elf32_External_Sym);
3615 +  if (!elf_bad_symtab (abfd))
3616 +    sym_hashes_end -= symtab_hdr->sh_info;
3617 +
3618 +  dynobj = elf_hash_table (info)->dynobj;
3619 +  rel_end = relocs + sec->reloc_count;
3620 +  for (rel = relocs; rel < rel_end; rel++)
3621 +    {
3622 +      struct elf_link_hash_entry *h;
3623 +      unsigned long r_symndx;
3624 +
3625 +      r_symndx = ELF32_R_SYM (rel->r_info);
3626 +      if (r_symndx < symtab_hdr->sh_info)
3627 +       h = NULL;
3628 +      else
3629 +       h = sym_hashes[r_symndx - symtab_hdr->sh_info];
3630 +
3631 +      switch (ELF32_R_TYPE (rel->r_info))
3632 +       {
3633 +       case R_UBICOM32_GOTOFFSET_HI:
3634 +       case R_UBICOM32_GOTOFFSET_LO:
3635 +       case R_UBICOM32_FUNCDESC_GOTOFFSET_HI:
3636 +       case R_UBICOM32_FUNCDESC_GOTOFFSET_LO:
3637 +       case R_UBICOM32_FUNCDESC:
3638 +       case R_UBICOM32_FUNCDESC_VALUE:
3639 +         if (! IS_FDPIC (abfd))
3640 +           goto bad_reloc;
3641 +         /* Fall through.  */
3642 +       case R_UBICOM32_24_PCREL:
3643 +       case R_UBICOM32_32:
3644 +         if (IS_FDPIC (abfd) && ! dynobj)
3645 +           {
3646 +             elf_hash_table (info)->dynobj = dynobj = abfd;
3647 +             if (! ubicom32fdpic_elf_create_got_section (abfd, info))
3648 +               return FALSE;
3649 +           }
3650 +         if (! IS_FDPIC (abfd))
3651 +           {
3652 +             picrel = NULL;
3653 +             break;
3654 +           }
3655 +         if (h != NULL)
3656 +           {
3657 +             if (h->dynindx == -1)
3658 +               switch (ELF_ST_VISIBILITY (h->other))
3659 +                 {
3660 +                 case STV_INTERNAL:
3661 +                 case STV_HIDDEN:
3662 +                   break;
3663 +                 default:
3664 +                   bfd_elf_link_record_dynamic_symbol (info, h);
3665 +                   break;
3666 +                 }
3667 +             picrel
3668 +               = ubicom32fdpic_relocs_info_for_global (ubicom32fdpic_relocs_info (info),
3669 +                                                       abfd, h,
3670 +                                                       rel->r_addend, INSERT);
3671 +           }
3672 +         else
3673 +           picrel = ubicom32fdpic_relocs_info_for_local (ubicom32fdpic_relocs_info (info),
3674 +                                                         abfd, r_symndx,
3675 +                                                         rel->r_addend, INSERT);
3676 +         if (! picrel)
3677 +           return FALSE;
3678 +         break;
3679 +
3680 +       default:
3681 +         picrel = NULL;
3682 +         break;
3683 +       }
3684 +
3685 +      switch (ELF32_R_TYPE (rel->r_info))
3686 +       {
3687 +       case R_UBICOM32_24_PCREL:
3688 +         if (IS_FDPIC (abfd))
3689 +           picrel->call++;
3690 +         break;
3691 +
3692 +       case R_UBICOM32_FUNCDESC_VALUE:
3693 +         picrel->relocsfdv++;
3694 +         picrel->sym++;
3695 +         break;
3696 +
3697 +       case R_UBICOM32_32:
3698 +         if (! IS_FDPIC (abfd))
3699 +           break;
3700 +
3701 +         picrel->sym++;
3702 +         if (bfd_get_section_flags (abfd, sec) & SEC_ALLOC)
3703 +           picrel->relocs32++;
3704 +         break;
3705 +
3706 +       case R_UBICOM32_GOTOFFSET_HI:
3707 +         picrel->gotoffset_hi++;
3708 +         break;
3709 +
3710 +       case R_UBICOM32_GOTOFFSET_LO:
3711 +         picrel->gotoffset_lo++;
3712 +         break;
3713 +
3714 +       case R_UBICOM32_FUNCDESC_GOTOFFSET_HI:
3715 +         picrel->fd_gotoffset_hi++;
3716 +         break;
3717 +
3718 +       case R_UBICOM32_FUNCDESC_GOTOFFSET_LO:
3719 +         picrel->fd_gotoffset_lo++;
3720 +         break;
3721 +
3722 +       case R_UBICOM32_FUNCDESC:
3723 +         picrel->fd++;
3724 +         picrel->relocsfd++;
3725 +         break;
3726 +
3727 +         /* This relocation describes the C++ object vtable hierarchy.
3728 +            Reconstruct it for later use during GC.  */
3729 +       case R_UBICOM32_GNU_VTINHERIT:
3730 +         if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset))
3731 +           return FALSE;
3732 +         break;
3733 +
3734 +         /* This relocation describes which C++ vtable entries are actually
3735 +            used.  Record for later use during GC.  */
3736 +       case R_UBICOM32_GNU_VTENTRY:
3737 +         if (!bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_addend))
3738 +           return FALSE;
3739 +         break;
3740 +
3741 +       case R_UBICOM32_21_PCREL:
3742 +       case R_UBICOM32_HI24:
3743 +       case R_UBICOM32_LO7_S:
3744 +         break;
3745 +
3746 +       default:
3747 +       bad_reloc:
3748 +         (*_bfd_error_handler)
3749 +           (_("%B: unsupported (ubicom32) relocation type %i"),
3750 +            abfd, ELF32_R_TYPE (rel->r_info));
3751 +         return FALSE;
3752 +       }
3753 +    }
3754 +
3755 +  return TRUE;
3756 +}
3757 +
3758 +/* Follow indirect and warning hash entries so that each got entry
3759 +   points to the final symbol definition.  P must point to a pointer
3760 +   to the hash table we're traversing.  Since this traversal may
3761 +   modify the hash table, we set this pointer to NULL to indicate
3762 +   we've made a potentially-destructive change to the hash table, so
3763 +   the traversal must be restarted.  */
3764 +static int
3765 +ubicom32fdpic_resolve_final_relocs_info (void **entryp, void *p)
3766 +{
3767 +  struct ubicom32fdpic_relocs_info *entry = *entryp;
3768 +  htab_t *htab = p;
3769 +
3770 +  if (entry->symndx == -1)
3771 +    {
3772 +      struct elf_link_hash_entry *h = entry->d.h;
3773 +      struct ubicom32fdpic_relocs_info *oentry;
3774 +
3775 +      while (h->root.type == bfd_link_hash_indirect
3776 +            || h->root.type == bfd_link_hash_warning)
3777 +       h = (struct elf_link_hash_entry *)h->root.u.i.link;
3778 +
3779 +      if (entry->d.h == h)
3780 +       return 1;
3781 +
3782 +      oentry = ubicom32fdpic_relocs_info_for_global (*htab, 0, h, entry->addend,
3783 +                                                    NO_INSERT);
3784 +
3785 +      if (oentry)
3786 +       {
3787 +         /* Merge the two entries.  */
3788 +         ubicom32fdpic_pic_merge_early_relocs_info (oentry, entry);
3789 +         htab_clear_slot (*htab, entryp);
3790 +         return 1;
3791 +       }
3792 +
3793 +      entry->d.h = h;
3794 +
3795 +      /* If we can't find this entry with the new bfd hash, re-insert
3796 +        it, and get the traversal restarted.  */
3797 +      if (! htab_find (*htab, entry))
3798 +       {
3799 +         htab_clear_slot (*htab, entryp);
3800 +         entryp = htab_find_slot (*htab, entry, INSERT);
3801 +         if (! *entryp)
3802 +           *entryp = entry;
3803 +         /* Abort the traversal, since the whole table may have
3804 +            moved, and leave it up to the parent to restart the
3805 +            process.  */
3806 +         *(htab_t *)p = NULL;
3807 +         return 0;
3808 +       }
3809 +    }
3810 +
3811 +  return 1;
3812 +}
3813 +
3814 +/* Assign GOT offsets to private function descriptors used by PLT
3815 +   entries (or referenced by 32-bit offsets), as well as PLT entries
3816 +   and lazy PLT entries.  */
3817 +static int
3818 +ubicom32fdpic_assign_plt_entries (void **entryp, void *info_)
3819 +{
3820 +  struct ubicom32fdpic_relocs_info *entry = *entryp;
3821 +  struct ubicom32fdpic_dynamic_got_plt_info *dinfo = info_;
3822 +
3823 +  if (entry->privfd && entry->fd_entry == 0)
3824 +    {
3825 +      //      dinfo->current_fd -= FUNCTION_DESCRIPTOR_SIZE;
3826 +      //      entry->fd_entry = dinfo->current_fd;
3827 +      DPRINTF(" late assign fd  % 5d:%p \n", entry->fd_entry, entry);
3828 +    }
3829 +
3830 +  if (entry->plt)
3831 +    {
3832 +      /* We use the section's raw size to mark the location of the
3833 +        next PLT entry.  */
3834 +      entry->plt_entry = dinfo->current_plt;
3835 +      entry->plt_trampoline_entry = dinfo->current_plt_trampoline;
3836 +      dinfo->current_plt_trampoline += PLT_TRAMPOLINE_SIZE;
3837 +
3838 +      if (entry->fd_entry >= (-512))
3839 +       {
3840 +         /* This entry is going to be of type seq2 */
3841 +         dinfo->current_plt += LZPLT_SIZE_SEQ2;
3842 +         entry->plt_type = 2;
3843 +       }
3844 +      else
3845 +       {
3846 +         /* This entry is going to be of type seq1 */
3847 +         dinfo->current_plt += LZPLT_SIZE_SEQ1;
3848 +         entry->plt_type = 1;
3849 +       }
3850 +      DPRINTF(" assign plt % 4d for fd=% 4d:%p next %d plttype %d\n", entry->plt_entry, entry->fd_entry, entry,  dinfo->current_plt, entry->plt_type);
3851 +
3852 +    }
3853 +
3854 +  return 1;
3855 +}
3856 +
3857 +/* Assign GOT offsets for every GOT entry and function descriptor.
3858 +   Doing everything in a single pass is tricky.  */
3859 +static int
3860 +ubicom32fdpic_assign_got_entries (void **entryp, void *info_)
3861 +{
3862 +  struct ubicom32fdpic_relocs_info *entry = *entryp;
3863 +  struct ubicom32fdpic_dynamic_got_plt_info *dinfo = info_;
3864 +
3865 +  if (entry->gotoffset_lo || entry->gotoffset_hi)
3866 +    {
3867 +      entry->got_entry = dinfo->current_got;
3868 +      DPRINTF(" assign got % 5d:%p \n", entry->got_entry, entry);
3869 +      dinfo->current_got += 4;
3870 +    }
3871 +
3872 +  if (entry->fd_gotoffset_lo || entry->fd_gotoffset_hi)
3873 +    {
3874 +      entry->fdgot_entry = dinfo->current_got;
3875 +      DPRINTF(" assign fdgot % 5d:%p \n", entry->fdgot_entry, entry);
3876 +      dinfo->current_got += 4;
3877 +    }
3878 +
3879 +  if (entry->plt)
3880 +    {
3881 +      dinfo->current_fd -= FUNCTION_DESCRIPTOR_SIZE;
3882 +      entry->fd_entry = dinfo->current_fd;
3883 +
3884 +      dinfo->total_trampoline += PLT_TRAMPOLINE_SIZE;
3885 +
3886 +      if (entry->fd_entry >= (-512))
3887 +       {
3888 +         /* This entry is going to be of type seq2 */
3889 +         dinfo->total_lzplt += LZPLT_SIZE_SEQ2;
3890 +         entry->plt_type = 2;
3891 +       }
3892 +      else
3893 +       {
3894 +         /* This entry is going to be of type seq1 */
3895 +         dinfo->total_lzplt += LZPLT_SIZE_SEQ1;
3896 +         entry->plt_type = 1;
3897 +       }
3898 +
3899 +      DPRINTF(" assign fd  % 5d:%p \n", entry->fd_entry, entry);
3900 +    }
3901 +  else if (entry->privfd)
3902 +    {
3903 +      dinfo->current_privfd -= FUNCTION_DESCRIPTOR_SIZE;
3904 +      entry->fd_entry = dinfo->current_privfd;
3905 +      DPRINTF(" assign private fd  % 5d:%p %p \n", entry->fd_entry, entry, entry->plt);
3906 +    }
3907 +
3908 +  return 1;
3909 +}
3910 +
3911 +/* Set the sizes of the dynamic sections.  */
3912 +
3913 +static bfd_boolean
3914 +ubicom32fdpic_elf_size_dynamic_sections (bfd *output_bfd,
3915 +                                        struct bfd_link_info *info)
3916 +{
3917 +  bfd *dynobj;
3918 +  asection *s;
3919 +  struct ubicom32fdpic_dynamic_got_plt_info gpinfo;
3920 +  bfd_vma total_plt_size;
3921 +
3922 +  dynobj = elf_hash_table (info)->dynobj;
3923 +  BFD_ASSERT (dynobj != NULL);
3924 +
3925 +  if (elf_hash_table (info)->dynamic_sections_created)
3926 +    {
3927 +      /* Set the contents of the .interp section to the interpreter.  */
3928 +      if (info->executable)
3929 +       {
3930 +         s = bfd_get_section_by_name (dynobj, ".interp");
3931 +         BFD_ASSERT (s != NULL);
3932 +         s->size = sizeof ELF_DYNAMIC_INTERPRETER;
3933 +         s->contents = (bfd_byte *) ELF_DYNAMIC_INTERPRETER;
3934 +       }
3935 +    }
3936 +
3937 +  memset (&gpinfo, 0, sizeof (gpinfo));
3938 +  gpinfo.g.info = info;
3939 +
3940 +  for (;;)
3941 +    {
3942 +      htab_t relocs = ubicom32fdpic_relocs_info (info);
3943 +
3944 +      htab_traverse (relocs, ubicom32fdpic_resolve_final_relocs_info, &relocs);
3945 +
3946 +      if (relocs == ubicom32fdpic_relocs_info (info))
3947 +       break;
3948 +    }
3949 +
3950 +  htab_traverse (ubicom32fdpic_relocs_info (info), ubicom32fdpic_count_got_plt_entries,
3951 +                &gpinfo.g);
3952 +
3953 +  /* At this point we know how many PLT entries we need. We know how many got entries we need and the total number of function descriptors in this link. */
3954 +  gpinfo.total_fdplt = gpinfo.g.fdplt + gpinfo.g.privfdplt;
3955 +  gpinfo.total_got = gpinfo.g.gotoffset_lo;
3956 +  gpinfo.total_lzplt = 0;
3957 +
3958 +  gpinfo.current_got = 12;     /* The first 12 bytes are reserved to get to resolver. */
3959 +  gpinfo.current_fd = 0;       /* We will decrement this by FUNCTION_DESCRIPTOR_SIZE for each allocation. */
3960 +  gpinfo.current_privfd = -gpinfo.g.fdplt;     /* We will decrement this by FUNCTION_DESCRIPTOR_SIZE for each allocation. */
3961 +  gpinfo.current_plt = 0;      /* Initialize this to 0. The trampoline code is at the start of the plt section.
3962 +                                  We will decrement this by LZPLT_NORMAL_SIZE each time we allocate. */
3963 +  gpinfo.current_plt_trampoline = 0;
3964 +
3965 +  DPRINTF("Total plts = %d \n", gpinfo.g.num_plts);
3966 +
3967 +  /* Now assign (most) GOT offsets.  */
3968 +  htab_traverse (ubicom32fdpic_relocs_info (info), ubicom32fdpic_assign_got_entries,
3969 +                &gpinfo);
3970 +
3971 +
3972 +  ubicom32fdpic_got_section (info)->size = gpinfo.total_fdplt + gpinfo.total_got + 12;
3973 +
3974 +  DPRINTF("GOT size = fd=%d, got=%d\n", gpinfo.total_fdplt, gpinfo.total_got);
3975 +
3976 +  if (ubicom32fdpic_got_section (info)->size == 0)
3977 +    ubicom32fdpic_got_section (info)->flags |= SEC_EXCLUDE;
3978 +  else if (ubicom32fdpic_got_section (info)->size == 12
3979 +          && ! elf_hash_table (info)->dynamic_sections_created)
3980 +    {
3981 +      ubicom32fdpic_got_section (info)->flags |= SEC_EXCLUDE;
3982 +      ubicom32fdpic_got_section (info)->size = 0;
3983 +    }
3984 +  else
3985 +    {
3986 +      DPRINTF(" Alloc GOT size = %d\n", ubicom32fdpic_got_section (info)->size);
3987 +      ubicom32fdpic_got_section (info)->contents =
3988 +       (bfd_byte *) bfd_zalloc (dynobj,
3989 +                                ubicom32fdpic_got_section (info)->size);
3990 +      if (ubicom32fdpic_got_section (info)->contents == NULL)
3991 +       return FALSE;
3992 +    }
3993 +
3994 +  if (elf_hash_table (info)->dynamic_sections_created)
3995 +    /* Subtract the number of lzplt entries, since those will generate
3996 +       relocations in the pltrel section.  */
3997 +    ubicom32fdpic_gotrel_section (info)->size =
3998 +      (gpinfo.g.relocs - gpinfo.g.num_plts)
3999 +      * get_elf_backend_data (output_bfd)->s->sizeof_rel;
4000 +  else
4001 +    BFD_ASSERT (gpinfo.g.relocs == 0);
4002 +  if (ubicom32fdpic_gotrel_section (info)->size == 0)
4003 +    ubicom32fdpic_gotrel_section (info)->flags |= SEC_EXCLUDE;
4004 +  else
4005 +    {
4006 +      ubicom32fdpic_gotrel_section (info)->contents =
4007 +       (bfd_byte *) bfd_zalloc (dynobj,
4008 +                                ubicom32fdpic_gotrel_section (info)->size);
4009 +      if (ubicom32fdpic_gotrel_section (info)->contents == NULL)
4010 +       return FALSE;
4011 +    }
4012 +
4013 +  ubicom32fdpic_gotfixup_section (info)->size = (gpinfo.g.fixups + 1) * 4;
4014 +  if (ubicom32fdpic_gotfixup_section (info)->size == 0)
4015 +    ubicom32fdpic_gotfixup_section (info)->flags |= SEC_EXCLUDE;
4016 +  else
4017 +    {
4018 +      ubicom32fdpic_gotfixup_section (info)->contents =
4019 +       (bfd_byte *) bfd_zalloc (dynobj,
4020 +                                ubicom32fdpic_gotfixup_section (info)->size);
4021 +      if (ubicom32fdpic_gotfixup_section (info)->contents == NULL)
4022 +       return FALSE;
4023 +    }
4024 +
4025 +  if (elf_hash_table (info)->dynamic_sections_created)
4026 +    {
4027 +      ubicom32fdpic_pltrel_section (info)->size =
4028 +       gpinfo.g.num_plts * get_elf_backend_data (output_bfd)->s->sizeof_rel;
4029 +      if (ubicom32fdpic_pltrel_section (info)->size == 0)
4030 +       ubicom32fdpic_pltrel_section (info)->flags |= SEC_EXCLUDE;
4031 +      else
4032 +       {
4033 +         ubicom32fdpic_pltrel_section (info)->contents =
4034 +           (bfd_byte *) bfd_zalloc (dynobj,
4035 +                                    ubicom32fdpic_pltrel_section (info)->size);
4036 +         if (ubicom32fdpic_pltrel_section (info)->contents == NULL)
4037 +           return FALSE;
4038 +       }
4039 +    }
4040 +
4041 +  /* The Pltsection is g.lzplt . The 4 is for the trampoline code. */
4042 +  total_plt_size = gpinfo.total_lzplt + gpinfo.total_trampoline;
4043 +  gpinfo.current_plt_trampoline = gpinfo.total_lzplt;
4044 +
4045 +  if (elf_hash_table (info)->dynamic_sections_created)
4046 +    {
4047 +      DPRINTF(" PLT size = %d\n", (total_plt_size ));
4048 +      ubicom32fdpic_plt_section (info)->size = (total_plt_size);
4049 +    }
4050 +
4051 +  /* Save information that we're going to need to generate GOT and PLT
4052 +     entries.  */
4053 +  ubicom32fdpic_got_initial_offset (info) = gpinfo.total_fdplt;
4054 +
4055 +  if (get_elf_backend_data (output_bfd)->want_got_sym)
4056 +    elf_hash_table (info)->hgot->root.u.def.value
4057 +      += ubicom32fdpic_got_initial_offset (info);
4058 +
4059 +  /* Allocate the PLT section contents.  */
4060 +  if (elf_hash_table (info)->dynamic_sections_created)
4061 +    {
4062 +      if (ubicom32fdpic_plt_section (info)->size == 4)
4063 +       {
4064 +         ubicom32fdpic_plt_section (info)->flags |= SEC_EXCLUDE;
4065 +         ubicom32fdpic_plt_section (info)->size = 0;
4066 +       }
4067 +      else
4068 +       {
4069 +         DPRINTF(" Alloc PLT size = %d\n", (total_plt_size));
4070 +         ubicom32fdpic_plt_section (info)->contents =
4071 +           (bfd_byte *) bfd_zalloc (dynobj,
4072 +                                    ubicom32fdpic_plt_section (info)->size);
4073 +         if (ubicom32fdpic_plt_section (info)->contents == NULL)
4074 +           return FALSE;
4075 +       }
4076 +    }
4077 +
4078 +  
4079 +  htab_traverse (ubicom32fdpic_relocs_info (info), ubicom32fdpic_assign_plt_entries,
4080 +                &gpinfo);
4081 +
4082 +
4083 +  if (elf_hash_table (info)->dynamic_sections_created)
4084 +    {
4085 +      if (ubicom32fdpic_got_section (info)->size)
4086 +       if (!_bfd_elf_add_dynamic_entry (info, DT_PLTGOT, 0))
4087 +         return FALSE;
4088 +
4089 +      if (ubicom32fdpic_pltrel_section (info)->size)
4090 +       if (!_bfd_elf_add_dynamic_entry (info, DT_PLTRELSZ, 0)
4091 +           || !_bfd_elf_add_dynamic_entry (info, DT_PLTREL, DT_REL)
4092 +           || !_bfd_elf_add_dynamic_entry (info, DT_JMPREL, 0))
4093 +         return FALSE;
4094 +
4095 +      if (ubicom32fdpic_gotrel_section (info)->size)
4096 +       if (!_bfd_elf_add_dynamic_entry (info, DT_REL, 0)
4097 +           || !_bfd_elf_add_dynamic_entry (info, DT_RELSZ, 0)
4098 +           || !_bfd_elf_add_dynamic_entry (info, DT_RELENT,
4099 +                                           sizeof (Elf32_External_Rel)))
4100 +         return FALSE;
4101 +    }
4102 +
4103 +  s = bfd_get_section_by_name (dynobj, ".rela.bss");
4104 +  if (s && s->size == 0)
4105 +    s->flags |= SEC_EXCLUDE;
4106 +
4107 +  s = bfd_get_section_by_name (dynobj, ".rel.plt");
4108 +  if (s && s->size == 0)
4109 +    s->flags |= SEC_EXCLUDE;
4110 +
4111 +  return TRUE;
4112 +}
4113 +
4114 +
4115 +/* Adjust a symbol defined by a dynamic object and referenced by a
4116 +   regular object.  */
4117 +
4118 +static bfd_boolean
4119 +ubicom32fdpic_elf_adjust_dynamic_symbol
4120 +(struct bfd_link_info *info ATTRIBUTE_UNUSED,
4121 + struct elf_link_hash_entry *h ATTRIBUTE_UNUSED)
4122 +{
4123 +  bfd * dynobj;
4124 +
4125 +  dynobj = elf_hash_table (info)->dynobj;
4126 +
4127 +  /* Make sure we know what is going on here.  */
4128 +  BFD_ASSERT (dynobj != NULL
4129 +             && (h->u.weakdef != NULL
4130 +                 || (h->def_dynamic
4131 +                     && h->ref_regular
4132 +                     && !h->def_regular)));
4133 +
4134 +  /* If this is a weak symbol, and there is a real definition, the
4135 +     processor independent code will have arranged for us to see the
4136 +     real definition first, and we can just use the same value.  */
4137 +  if (h->u.weakdef != NULL)
4138 +    {
4139 +      BFD_ASSERT (h->u.weakdef->root.type == bfd_link_hash_defined
4140 +                 || h->u.weakdef->root.type == bfd_link_hash_defweak);
4141 +      h->root.u.def.section = h->u.weakdef->root.u.def.section;
4142 +      h->root.u.def.value = h->u.weakdef->root.u.def.value;
4143 +    }
4144 +
4145 +  return TRUE;
4146 +}
4147 +
4148 +static bfd_boolean
4149 +ubicom32fdpic_elf_always_size_sections (bfd *output_bfd,
4150 +                                       struct bfd_link_info *info)
4151 +{
4152 +  if (!info->relocatable)
4153 +    {
4154 +      struct elf_link_hash_entry *h;
4155 +
4156 +      /* Force a PT_GNU_STACK segment to be created.  */
4157 +      if (! elf_tdata (output_bfd)->stack_flags)
4158 +       elf_tdata (output_bfd)->stack_flags = PF_R | PF_W | PF_X;
4159 +
4160 +      /* Define __stacksize if it's not defined yet.  */
4161 +      h = elf_link_hash_lookup (elf_hash_table (info), "__stacksize",
4162 +                               FALSE, FALSE, FALSE);
4163 +      if (! h || h->root.type != bfd_link_hash_defined
4164 +         || h->type != STT_OBJECT
4165 +         || !h->def_regular)
4166 +       {
4167 +         struct bfd_link_hash_entry *bh = NULL;
4168 +
4169 +         if (!(_bfd_generic_link_add_one_symbol
4170 +               (info, output_bfd, "__stacksize",
4171 +                BSF_GLOBAL, bfd_abs_section_ptr, DEFAULT_STACK_SIZE,
4172 +                (const char *) NULL, FALSE,
4173 +                get_elf_backend_data (output_bfd)->collect, &bh)))
4174 +           return FALSE;
4175 +
4176 +         h = (struct elf_link_hash_entry *) bh;
4177 +         h->def_regular = 1;
4178 +         h->type = STT_OBJECT;
4179 +       }
4180 +    }
4181 +
4182 +  return TRUE;
4183 +}
4184 +
4185 +static bfd_boolean
4186 +ubicom32fdpic_elf_finish_dynamic_sections (bfd *output_bfd,
4187 +                                          struct bfd_link_info *info)
4188 +{
4189 +  bfd *dynobj;
4190 +  asection *sdyn;
4191 +
4192 +  dynobj = elf_hash_table (info)->dynobj;
4193 +
4194 +  if (ubicom32fdpic_got_section (info))
4195 +    {
4196 +      BFD_ASSERT (ubicom32fdpic_gotrel_section (info)->size
4197 +                 == (ubicom32fdpic_gotrel_section (info)->reloc_count
4198 +                     * sizeof (Elf32_External_Rel)));
4199 +
4200 +      if (ubicom32fdpic_gotfixup_section (info))
4201 +       {
4202 +         struct elf_link_hash_entry *hgot = elf_hash_table (info)->hgot;
4203 +         bfd_vma got_value = hgot->root.u.def.value
4204 +           + hgot->root.u.def.section->output_section->vma
4205 +           + hgot->root.u.def.section->output_offset;
4206 +
4207 +         ubicom32fdpic_add_rofixup (output_bfd, ubicom32fdpic_gotfixup_section (info),
4208 +                                    got_value, 0);
4209 +
4210 +         if (ubicom32fdpic_gotfixup_section (info)->size
4211 +             != (ubicom32fdpic_gotfixup_section (info)->reloc_count * 4))
4212 +           {
4213 +             (*_bfd_error_handler)
4214 +               ("LINKER BUG: .rofixup section size mismatch Size %d, should be %d ",
4215 +                ubicom32fdpic_gotfixup_section (info)->size, ubicom32fdpic_gotfixup_section (info)->reloc_count * 4);
4216 +             return FALSE;
4217 +           }
4218 +       }
4219 +    }
4220 +  if (elf_hash_table (info)->dynamic_sections_created)
4221 +    {
4222 +      BFD_ASSERT (ubicom32fdpic_pltrel_section (info)->size
4223 +                 == (ubicom32fdpic_pltrel_section (info)->reloc_count
4224 +                     * sizeof (Elf32_External_Rel)));
4225 +    }
4226 +
4227 +  sdyn = bfd_get_section_by_name (dynobj, ".dynamic");
4228 +
4229 +  if (elf_hash_table (info)->dynamic_sections_created)
4230 +    {
4231 +      Elf32_External_Dyn * dyncon;
4232 +      Elf32_External_Dyn * dynconend;
4233 +
4234 +      BFD_ASSERT (sdyn != NULL);
4235 +
4236 +      dyncon = (Elf32_External_Dyn *) sdyn->contents;
4237 +      dynconend = (Elf32_External_Dyn *) (sdyn->contents + sdyn->size);
4238 +
4239 +      for (; dyncon < dynconend; dyncon++)
4240 +       {
4241 +         Elf_Internal_Dyn dyn;
4242 +
4243 +         bfd_elf32_swap_dyn_in (dynobj, dyncon, &dyn);
4244 +
4245 +         switch (dyn.d_tag)
4246 +           {
4247 +           default:
4248 +             break;
4249 +
4250 +           case DT_PLTGOT:
4251 +             dyn.d_un.d_ptr = ubicom32fdpic_got_section (info)->output_section->vma
4252 +               + ubicom32fdpic_got_section (info)->output_offset
4253 +               + ubicom32fdpic_got_initial_offset (info);
4254 +             bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
4255 +             break;
4256 +
4257 +           case DT_JMPREL:
4258 +             dyn.d_un.d_ptr = ubicom32fdpic_pltrel_section (info)
4259 +               ->output_section->vma
4260 +               + ubicom32fdpic_pltrel_section (info)->output_offset;
4261 +             bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
4262 +             break;
4263 +
4264 +           case DT_PLTRELSZ:
4265 +             dyn.d_un.d_val = ubicom32fdpic_pltrel_section (info)->size;
4266 +             bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
4267 +             break;
4268 +           }
4269 +       }
4270 +    }
4271 +
4272 +  return TRUE;
4273 +}
4274 +
4275 +/* Perform any actions needed for dynamic symbols.  */
4276 +static bfd_boolean
4277 +ubicom32fdpic_elf_finish_dynamic_symbol
4278 +(bfd *output_bfd ATTRIBUTE_UNUSED,
4279 + struct bfd_link_info *info ATTRIBUTE_UNUSED,
4280 + struct elf_link_hash_entry *h ATTRIBUTE_UNUSED,
4281 + Elf_Internal_Sym *sym ATTRIBUTE_UNUSED)
4282 +{
4283 +  return TRUE;
4284 +}
4285 +
4286 +static bfd_boolean
4287 +ubicom32fdpic_elf_modify_program_headers (bfd *output_bfd,
4288 +                                         struct bfd_link_info *info)
4289 +{
4290 +  struct elf_obj_tdata *tdata = elf_tdata (output_bfd);
4291 +  struct elf_segment_map *m;
4292 +  Elf_Internal_Phdr *p;
4293 +
4294 +  if (! info)
4295 +    return TRUE;
4296 +
4297 +  for (p = tdata->phdr, m = tdata->segment_map; m != NULL; m = m->next, p++)
4298 +    if (m->p_type == PT_GNU_STACK)
4299 +      break;
4300 +
4301 +  if (m)
4302 +    {
4303 +      struct elf_link_hash_entry *h;
4304 +
4305 +      /* Obtain the pointer to the __stacksize symbol.  */
4306 +      h = elf_link_hash_lookup (elf_hash_table (info), "__stacksize",
4307 +                               FALSE, FALSE, FALSE);
4308 +      if (h)
4309 +       {
4310 +         while (h->root.type == bfd_link_hash_indirect
4311 +                || h->root.type == bfd_link_hash_warning)
4312 +           h = (struct elf_link_hash_entry *) h->root.u.i.link;
4313 +         BFD_ASSERT (h->root.type == bfd_link_hash_defined);
4314 +       }
4315 +
4316 +      /* Set the header p_memsz from the symbol value.  We
4317 +        intentionally ignore the symbol section.  */
4318 +      if (h && h->root.type == bfd_link_hash_defined)
4319 +       p->p_memsz = h->root.u.def.value;
4320 +      else
4321 +       p->p_memsz = DEFAULT_STACK_SIZE;
4322 +
4323 +      p->p_align = 8;
4324 +    }
4325 +
4326 +  return TRUE;
4327 +}
4328 +
4329 +static bfd_boolean
4330 +ubicom32fdpic_elf_gc_sweep_hook (bfd *abfd,
4331 +                                struct bfd_link_info *info,
4332 +                                asection *sec,
4333 +                                const Elf_Internal_Rela *relocs)
4334 +{
4335 +  Elf_Internal_Shdr *symtab_hdr;
4336 +  struct elf_link_hash_entry **sym_hashes, **sym_hashes_end;
4337 +  const Elf_Internal_Rela *rel;
4338 +  const Elf_Internal_Rela *rel_end;
4339 +  struct ubicom32fdpic_relocs_info *picrel;
4340 +
4341 +  BFD_ASSERT (IS_FDPIC (abfd));
4342 +
4343 +  symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
4344 +  sym_hashes = elf_sym_hashes (abfd);
4345 +  sym_hashes_end = sym_hashes + symtab_hdr->sh_size/sizeof(Elf32_External_Sym);
4346 +  if (!elf_bad_symtab (abfd))
4347 +    sym_hashes_end -= symtab_hdr->sh_info;
4348 +
4349 +  rel_end = relocs + sec->reloc_count;
4350 +  for (rel = relocs; rel < rel_end; rel++)
4351 +    {
4352 +      struct elf_link_hash_entry *h;
4353 +      unsigned long r_symndx;
4354 +
4355 +      r_symndx = ELF32_R_SYM (rel->r_info);
4356 +      if (r_symndx < symtab_hdr->sh_info)
4357 +       h = NULL;
4358 +      else
4359 +       h = sym_hashes[r_symndx - symtab_hdr->sh_info];
4360 +
4361 +      if (h != NULL)
4362 +       picrel = ubicom32fdpic_relocs_info_for_global (ubicom32fdpic_relocs_info (info),
4363 +                                                      abfd, h,
4364 +                                                      rel->r_addend, NO_INSERT);
4365 +      else
4366 +       picrel = ubicom32fdpic_relocs_info_for_local (ubicom32fdpic_relocs_info
4367 +                                                     (info), abfd, r_symndx,
4368 +                                                     rel->r_addend, NO_INSERT);
4369 +
4370 +      if (!picrel)
4371 +       continue;
4372 +
4373 +      switch (ELF32_R_TYPE (rel->r_info))
4374 +       {
4375 +       case R_UBICOM32_24_PCREL:
4376 +         picrel->call--;
4377 +         break;
4378 +
4379 +       case R_UBICOM32_FUNCDESC_VALUE:
4380 +         picrel->relocsfdv--;
4381 +         picrel->sym--;
4382 +         break;
4383 +
4384 +       case R_UBICOM32_GOTOFFSET_LO:
4385 +         picrel->gotoffset_lo--;
4386 +         break;
4387 +
4388 +       case R_UBICOM32_FUNCDESC_GOTOFFSET_LO:
4389 +         picrel->fd_gotoffset_lo--;
4390 +         break;
4391 +
4392 +       case R_UBICOM32_FUNCDESC_GOTOFFSET_HI:
4393 +         picrel->fd_gotoffset_hi--;
4394 +         break;
4395 +
4396 +       case R_UBICOM32_FUNCDESC:
4397 +         picrel->fd--;
4398 +         picrel->relocsfd--;
4399 +         break;
4400 +
4401 +       case R_UBICOM32_32:
4402 +         if (! IS_FDPIC (abfd))
4403 +           break;
4404 +
4405 +         if (picrel->sym)
4406 +           picrel->relocs32--;;
4407 +
4408 +         picrel->sym--;
4409 +         break;
4410 +
4411 +       default:
4412 +         break;
4413 +       }
4414 +    }
4415 +
4416 +  return TRUE;
4417 +}
4418 +/* Decide whether to attempt to turn absptr or lsda encodings in
4419 +   shared libraries into pcrel within the given input section.  */
4420 +
4421 +static bfd_boolean
4422 +ubicom32fdpic_elf_use_relative_eh_frame
4423 +(bfd *input_bfd ATTRIBUTE_UNUSED,
4424 + struct bfd_link_info *info ATTRIBUTE_UNUSED,
4425 + asection *eh_frame_section ATTRIBUTE_UNUSED)
4426 +{
4427 +  /* We can't use PC-relative encodings in FDPIC binaries, in general.  */
4428 +  return FALSE;
4429 +}
4430 +
4431 +/* Adjust the contents of an eh_frame_hdr section before they're output.  */
4432 +
4433 +static bfd_byte
4434 +ubicom32fdpic_elf_encode_eh_address (bfd *abfd,
4435 +                                    struct bfd_link_info *info,
4436 +                                    asection *osec, bfd_vma offset,
4437 +                                    asection *loc_sec, bfd_vma loc_offset,
4438 +                                    bfd_vma *encoded)
4439 +{
4440 +  struct elf_link_hash_entry *h;
4441 +
4442 +  h = elf_hash_table (info)->hgot;
4443 +  BFD_ASSERT (h && h->root.type == bfd_link_hash_defined);
4444 +
4445 +  if (! h || (ubicom32fdpic_osec_to_segment (abfd, osec)
4446 +             == ubicom32fdpic_osec_to_segment (abfd, loc_sec->output_section)))
4447 +    return _bfd_elf_encode_eh_address (abfd, info, osec, offset,
4448 +                                      loc_sec, loc_offset, encoded);
4449 +
4450 +  BFD_ASSERT (ubicom32fdpic_osec_to_segment (abfd, osec)
4451 +             == (ubicom32fdpic_osec_to_segment
4452 +                 (abfd, h->root.u.def.section->output_section)));
4453 +
4454 +  *encoded = osec->vma + offset
4455 +    - (h->root.u.def.value
4456 +       + h->root.u.def.section->output_section->vma
4457 +       + h->root.u.def.section->output_offset);
4458 +
4459 +  return DW_EH_PE_datarel | DW_EH_PE_sdata4;
4460 +}
4461 +static bfd_boolean
4462 +ubicom32fdpic_elf_copy_private_bfd_data (bfd *ibfd, bfd *obfd)
4463 +{
4464 +  unsigned i;
4465 +
4466 +  if (bfd_get_flavour (ibfd) != bfd_target_elf_flavour
4467 +      || bfd_get_flavour (obfd) != bfd_target_elf_flavour)
4468 +    return TRUE;
4469 +
4470 +  if (! ubicom32_elf_copy_private_bfd_data (ibfd, obfd))
4471 +    return FALSE;
4472 +
4473 +  if (! elf_tdata (ibfd) || ! elf_tdata (ibfd)->phdr
4474 +      || ! elf_tdata (obfd) || ! elf_tdata (obfd)->phdr)
4475 +    return TRUE;
4476 +
4477 +  /* Copy the stack size.  */
4478 +  for (i = 0; i < elf_elfheader (ibfd)->e_phnum; i++)
4479 +    if (elf_tdata (ibfd)->phdr[i].p_type == PT_GNU_STACK)
4480 +      {
4481 +       Elf_Internal_Phdr *iphdr = &elf_tdata (ibfd)->phdr[i];
4482 +
4483 +       for (i = 0; i < elf_elfheader (obfd)->e_phnum; i++)
4484 +         if (elf_tdata (obfd)->phdr[i].p_type == PT_GNU_STACK)
4485 +           {
4486 +             memcpy (&elf_tdata (obfd)->phdr[i], iphdr, sizeof (*iphdr));
4487 +
4488 +             /* Rewrite the phdrs, since we're only called after they
4489 +                were first written.  */
4490 +             if (bfd_seek (obfd, (bfd_signed_vma) get_elf_backend_data (obfd)
4491 +                           ->s->sizeof_ehdr, SEEK_SET) != 0
4492 +                 || get_elf_backend_data (obfd)->s
4493 +                 ->write_out_phdrs (obfd, elf_tdata (obfd)->phdr,
4494 +                                    elf_elfheader (obfd)->e_phnum) != 0)
4495 +               return FALSE;
4496 +             break;
4497 +           }
4498 +
4499 +       break;
4500 +      }
4501 +
4502 +  return TRUE;
4503 +}
4504 +
4505 +static bfd_boolean
4506 +ubicom32fdpic_elf_relocate_section (bfd * output_bfd,
4507 +                                   struct bfd_link_info *info,
4508 +                                   bfd * input_bfd,
4509 +                                   asection * input_section,
4510 +                                   bfd_byte * contents,
4511 +                                   Elf_Internal_Rela * relocs,
4512 +                                   Elf_Internal_Sym * local_syms,
4513 +                                   asection ** local_sections)
4514 +{
4515 +  Elf_Internal_Shdr *symtab_hdr;
4516 +  struct elf_link_hash_entry **sym_hashes;
4517 +  Elf_Internal_Rela *rel;
4518 +  Elf_Internal_Rela *relend;
4519 +  unsigned isec_segment, got_segment, plt_segment,
4520 +    check_segment[2];
4521 +  int silence_segment_error = !(info->shared || info->pie);
4522 +
4523 +  if (info->relocatable)
4524 +    return TRUE;
4525 +
4526 +  symtab_hdr = & elf_tdata (input_bfd)->symtab_hdr;
4527 +  sym_hashes = elf_sym_hashes (input_bfd);
4528 +  relend     = relocs + input_section->reloc_count;
4529 +
4530 +  isec_segment = ubicom32fdpic_osec_to_segment (output_bfd,
4531 +                                               input_section->output_section);
4532 +  if (IS_FDPIC (output_bfd) && ubicom32fdpic_got_section (info))
4533 +    got_segment = ubicom32fdpic_osec_to_segment (output_bfd,
4534 +                                                ubicom32fdpic_got_section (info)
4535 +                                                ->output_section);
4536 +  else
4537 +    got_segment = -1;
4538 +  if (IS_FDPIC (output_bfd) && elf_hash_table (info)->dynamic_sections_created)
4539 +    plt_segment = ubicom32fdpic_osec_to_segment (output_bfd,
4540 +                                                ubicom32fdpic_plt_section (info)
4541 +                                                ->output_section);
4542 +  else
4543 +    plt_segment = -1;
4544 +
4545 +  for (rel = relocs; rel < relend; rel ++)
4546 +    {
4547 +      reloc_howto_type *howto;
4548 +      unsigned long r_symndx;
4549 +      Elf_Internal_Sym *sym;
4550 +      asection *sec;
4551 +      struct elf_link_hash_entry *h;
4552 +      bfd_vma relocation;
4553 +      bfd_reloc_status_type r;
4554 +      const char * name = NULL;
4555 +      int r_type;
4556 +      asection *osec;
4557 +      struct ubicom32fdpic_relocs_info *picrel;
4558 +      bfd_vma orig_addend = rel->r_addend;
4559 +
4560 +      r_type = ELF32_R_TYPE (rel->r_info);
4561 +
4562 +      if (r_type == R_UBICOM32_GNU_VTINHERIT
4563 +         || r_type == R_UBICOM32_GNU_VTENTRY)
4564 +       continue;
4565 +
4566 +      /* This is a final link.  */
4567 +      r_symndx = ELF32_R_SYM (rel->r_info);
4568 +
4569 +      //howto = ubicom32_reloc_type_lookup (input_bfd, r_type);
4570 +      howto  = ubicom32_elf_howto_table + ELF32_R_TYPE (rel->r_info);
4571 +      if (howto == NULL)
4572 +       {
4573 +         bfd_set_error (bfd_error_bad_value);
4574 +         return FALSE;
4575 +       }
4576 +
4577 +      h      = NULL;
4578 +      sym    = NULL;
4579 +      sec    = NULL;
4580 +
4581 +      if (r_symndx < symtab_hdr->sh_info)
4582 +       {
4583 +         sym = local_syms + r_symndx;
4584 +         osec = sec = local_sections [r_symndx];
4585 +         relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
4586 +
4587 +         name = bfd_elf_string_from_elf_section
4588 +           (input_bfd, symtab_hdr->sh_link, sym->st_name);
4589 +         name = (name == NULL) ? bfd_section_name (input_bfd, sec) : name;
4590 +       }
4591 +      else
4592 +       {
4593 +         h = sym_hashes [r_symndx - symtab_hdr->sh_info];
4594 +
4595 +         while (h->root.type == bfd_link_hash_indirect
4596 +                || h->root.type == bfd_link_hash_warning)
4597 +           h = (struct elf_link_hash_entry *) h->root.u.i.link;
4598 +
4599 +         name = h->root.root.string;
4600 +
4601 +         if ((h->root.type == bfd_link_hash_defined
4602 +              || h->root.type == bfd_link_hash_defweak)
4603 +             && ! UBICOM32FDPIC_SYM_LOCAL (info, h))
4604 +           {
4605 +             sec = NULL;
4606 +             relocation = 0;
4607 +           }
4608 +         else
4609 +           if (h->root.type == bfd_link_hash_defined
4610 +               || h->root.type == bfd_link_hash_defweak)
4611 +             {
4612 +               sec = h->root.u.def.section;
4613 +               relocation = (h->root.u.def.value
4614 +                             + sec->output_section->vma
4615 +                             + sec->output_offset);
4616 +             }
4617 +           else if (h->root.type == bfd_link_hash_undefweak)
4618 +             {
4619 +               relocation = 0;
4620 +             }
4621 +           else if (info->unresolved_syms_in_objects == RM_IGNORE
4622 +                    && ELF_ST_VISIBILITY (h->other) == STV_DEFAULT)
4623 +             relocation = 0;
4624 +           else
4625 +             {
4626 +               if (! ((*info->callbacks->undefined_symbol)
4627 +                      (info, h->root.root.string, input_bfd,
4628 +                       input_section, rel->r_offset,
4629 +                       (info->unresolved_syms_in_objects == RM_GENERATE_ERROR
4630 +                        || ELF_ST_VISIBILITY (h->other)))))
4631 +                 return FALSE;
4632 +               relocation = 0;
4633 +             }
4634 +         osec = sec;
4635 +       }
4636 +
4637 +      switch (r_type)
4638 +       {
4639 +       case R_UBICOM32_24_PCREL:
4640 +       case R_UBICOM32_32:
4641 +         if (! IS_FDPIC (output_bfd))
4642 +           goto non_fdpic;
4643 +
4644 +       case R_UBICOM32_FUNCDESC_VALUE:
4645 +       case R_UBICOM32_FUNCDESC:
4646 +       case R_UBICOM32_GOTOFFSET_LO:
4647 +       case R_UBICOM32_GOTOFFSET_HI:
4648 +       case R_UBICOM32_FUNCDESC_GOTOFFSET_LO:
4649 +       case R_UBICOM32_FUNCDESC_GOTOFFSET_HI:
4650 +         if (h != NULL)
4651 +           picrel = ubicom32fdpic_relocs_info_for_global (ubicom32fdpic_relocs_info
4652 +                                                          (info), input_bfd, h,
4653 +                                                          orig_addend, INSERT);
4654 +         else
4655 +           /* In order to find the entry we created before, we must
4656 +              use the original addend, not the one that may have been
4657 +              modified by _bfd_elf_rela_local_sym().  */
4658 +           picrel = ubicom32fdpic_relocs_info_for_local (ubicom32fdpic_relocs_info
4659 +                                                         (info), input_bfd, r_symndx,
4660 +                                                         orig_addend, INSERT);
4661 +         if (! picrel)
4662 +           return FALSE;
4663 +
4664 +         if (!ubicom32fdpic_emit_got_relocs_plt_entries (picrel, output_bfd, info,
4665 +                                                         osec, sym,
4666 +                                                         rel->r_addend))
4667 +           {
4668 +             (*_bfd_error_handler)
4669 +               (_("%B: relocation at `%A+0x%x' references symbol `%s' with nonzero addend"),
4670 +                input_bfd, input_section, rel->r_offset, name);
4671 +             return FALSE;
4672 +
4673 +           }
4674 +
4675 +         break;
4676 +       case R_UBICOM32_21_PCREL:
4677 +       case R_UBICOM32_HI24:
4678 +       case R_UBICOM32_LO7_S:
4679 +         //printf("Seeing this stuff Don;t know what to do. r_type %d r_symndx %d %s %s\n", r_type, r_symndx, input_bfd->filename, input_section->name);
4680 +         break;
4681 +
4682 +       default:
4683 +       non_fdpic:
4684 +         picrel = NULL;
4685 +         //printf("h = 0x%x %d\n", h, UBICOM32FDPIC_SYM_LOCAL (info, h));
4686 +         if (h && ! UBICOM32FDPIC_SYM_LOCAL (info, h))
4687 +           {
4688 +             printf("h = 0x%x %d\n", h, UBICOM32FDPIC_SYM_LOCAL (info, h));
4689 +             printf("Seeing this stuff. r_type %d r_symndx %d %s %s\n", r_type, r_symndx, input_bfd->filename, input_section->name);
4690 +             info->callbacks->warning
4691 +               (info, _("relocation references symbol not defined in the module"),
4692 +                name, input_bfd, input_section, rel->r_offset);
4693 +             return FALSE;
4694 +           }
4695 +         break;
4696 +       }
4697 +
4698 +      switch (r_type)
4699 +       {
4700 +       case R_UBICOM32_21_PCREL:
4701 +       case R_UBICOM32_HI24:
4702 +       case R_UBICOM32_LO7_S:
4703 +         //printf("Seeing this stuff. r_type %d r_symndx %d %s %s\n", r_type, r_symndx, input_bfd->filename, input_section->name);
4704 +         check_segment[0] = check_segment[1] = got_segment;
4705 +         break;
4706 +
4707 +       case R_UBICOM32_24_PCREL:
4708 +         check_segment[0] = isec_segment;
4709 +         if (! IS_FDPIC (output_bfd))
4710 +           check_segment[1] = isec_segment;
4711 +         else if (picrel->plt)
4712 +           {
4713 +             relocation = ubicom32fdpic_plt_section (info)->output_section->vma
4714 +               + ubicom32fdpic_plt_section (info)->output_offset
4715 +               + picrel->plt_entry;
4716 +
4717 +             /* subtract rel->addend. This will get added back in the 23pcrel howto routine. */
4718 +             relocation -= rel->r_addend;
4719 +
4720 +             check_segment[1] = plt_segment;
4721 +           }
4722 +         /* We don't want to warn on calls to undefined weak symbols,
4723 +            as calls to them must be protected by non-NULL tests
4724 +            anyway, and unprotected calls would invoke undefined
4725 +            behavior.  */
4726 +         else if (picrel->symndx == -1
4727 +                  && picrel->d.h->root.type == bfd_link_hash_undefweak)
4728 +           check_segment[1] = check_segment[0];
4729 +         else
4730 +           check_segment[1] = sec
4731 +             ? ubicom32fdpic_osec_to_segment (output_bfd, sec->output_section)
4732 +             : (unsigned)-1;
4733 +         break;
4734 +
4735 +       case R_UBICOM32_GOTOFFSET_LO:
4736 +         relocation = picrel->got_entry >> 2;
4737 +         check_segment[0] = check_segment[1] = got_segment;
4738 +         break;
4739 +
4740 +       case R_UBICOM32_FUNCDESC_GOTOFFSET_LO:
4741 +         relocation = picrel->fdgot_entry >> 2;
4742 +         check_segment[0] = check_segment[1] = got_segment;
4743 +         break;
4744 +
4745 +       case R_UBICOM32_FUNCDESC:
4746 +         {
4747 +           int dynindx;
4748 +           bfd_vma addend = rel->r_addend;
4749 +
4750 +           if (! (h && h->root.type == bfd_link_hash_undefweak
4751 +                  && UBICOM32FDPIC_SYM_LOCAL (info, h)))
4752 +             {
4753 +               /* If the symbol is dynamic and there may be dynamic
4754 +                  symbol resolution because we are or are linked with a
4755 +                  shared library, emit a FUNCDESC relocation such that
4756 +                  the dynamic linker will allocate the function
4757 +                  descriptor.  If the symbol needs a non-local function
4758 +                  descriptor but binds locally (e.g., its visibility is
4759 +                  protected, emit a dynamic relocation decayed to
4760 +                  section+offset.  */
4761 +               if (h && ! UBICOM32FDPIC_FUNCDESC_LOCAL (info, h)
4762 +                   && UBICOM32FDPIC_SYM_LOCAL (info, h)
4763 +                   && !(info->executable && !info->pie))
4764 +                 {
4765 +                   dynindx = elf_section_data (h->root.u.def.section
4766 +                                               ->output_section)->dynindx;
4767 +                   addend += h->root.u.def.section->output_offset
4768 +                     + h->root.u.def.value;
4769 +                 }
4770 +               else if (h && ! UBICOM32FDPIC_FUNCDESC_LOCAL (info, h))
4771 +                 {
4772 +                   if (addend)
4773 +                     {
4774 +                       info->callbacks->warning
4775 +                         (info, _("R_UBICOM32_FUNCDESC references dynamic symbol with nonzero addend"),
4776 +                          name, input_bfd, input_section, rel->r_offset);
4777 +                       return FALSE;
4778 +                     }
4779 +                   dynindx = h->dynindx;
4780 +                 }
4781 +               else
4782 +                 {
4783 +                   /* Otherwise, we know we have a private function
4784 +                      descriptor, so reference it directly.  */
4785 +                   BFD_ASSERT (picrel->privfd);
4786 +                   r_type = R_UBICOM32_32; // was FUNCDESC but bfin uses 32 bit
4787 +                   dynindx = elf_section_data (ubicom32fdpic_got_section (info)
4788 +                                               ->output_section)->dynindx;
4789 +                   addend = ubicom32fdpic_got_section (info)->output_offset
4790 +                     + ubicom32fdpic_got_initial_offset (info)
4791 +                     + picrel->fd_entry;
4792 +                 }
4793 +
4794 +               /* If there is room for dynamic symbol resolution, emit
4795 +                  the dynamic relocation.  However, if we're linking an
4796 +                  executable at a fixed location, we won't have emitted a
4797 +                  dynamic symbol entry for the got section, so idx will
4798 +                  be zero, which means we can and should compute the
4799 +                  address of the private descriptor ourselves.  */
4800 +               if (info->executable && !info->pie
4801 +                   && (!h || UBICOM32FDPIC_FUNCDESC_LOCAL (info, h)))
4802 +                 {
4803 +                   addend += ubicom32fdpic_got_section (info)->output_section->vma;
4804 +                   if ((bfd_get_section_flags (output_bfd,
4805 +                                               input_section->output_section)
4806 +                        & (SEC_ALLOC | SEC_LOAD)) == (SEC_ALLOC | SEC_LOAD))
4807 +                     {
4808 +                       if (ubicom32fdpic_osec_readonly_p (output_bfd,
4809 +                                                          input_section
4810 +                                                          ->output_section))
4811 +                         {
4812 +                           info->callbacks->warning
4813 +                             (info,
4814 +                              _("cannot emit fixups in read-only section"),
4815 +                              name, input_bfd, input_section, rel->r_offset);
4816 +                           return FALSE;
4817 +                         }
4818 +                       ubicom32fdpic_add_rofixup (output_bfd,
4819 +                                                  ubicom32fdpic_gotfixup_section
4820 +                                                  (info),
4821 +                                                  _bfd_elf_section_offset
4822 +                                                  (output_bfd, info,
4823 +                                                   input_section, rel->r_offset)
4824 +                                                  + input_section
4825 +                                                  ->output_section->vma
4826 +                                                  + input_section->output_offset,
4827 +                                                  picrel);
4828 +                     }
4829 +                 }
4830 +               else if ((bfd_get_section_flags (output_bfd,
4831 +                                                input_section->output_section)
4832 +                         & (SEC_ALLOC | SEC_LOAD)) == (SEC_ALLOC | SEC_LOAD))
4833 +                 {
4834 +                   bfd_vma offset;
4835 +
4836 +                   if (ubicom32fdpic_osec_readonly_p (output_bfd,
4837 +                                                      input_section
4838 +                                                      ->output_section))
4839 +                     {
4840 +                       info->callbacks->warning
4841 +                         (info,
4842 +                          _("cannot emit dynamic relocations in read-only section"),
4843 +                          name, input_bfd, input_section, rel->r_offset);
4844 +                       return FALSE;
4845 +                     }
4846 +                   offset = _bfd_elf_section_offset (output_bfd, info,
4847 +                                                     input_section, rel->r_offset);
4848 +                   /* Only output a reloc for a not deleted entry.  */
4849 +                   if (offset >= (bfd_vma) -2)
4850 +                     ubicom32fdpic_add_dyn_reloc (output_bfd,
4851 +                                                  ubicom32fdpic_gotrel_section (info),
4852 +                                                  0,
4853 +                                                  R_UBICOM32_NONE,
4854 +                                                  dynindx, addend, picrel);
4855 +                   else
4856 +                     ubicom32fdpic_add_dyn_reloc (output_bfd,
4857 +                                                  ubicom32fdpic_gotrel_section (info),
4858 +                                                  offset + input_section
4859 +                                                  ->output_section->vma
4860 +                                                  + input_section->output_offset,
4861 +                                                  r_type,
4862 +                                                  dynindx, addend, picrel);
4863 +                 }
4864 +               else
4865 +                 addend += ubicom32fdpic_got_section (info)->output_section->vma;
4866 +             }
4867 +
4868 +           /* We want the addend in-place because dynamic
4869 +              relocations are REL.  Setting relocation to it should
4870 +              arrange for it to be installed.  */
4871 +           relocation = addend - rel->r_addend;
4872 +         }
4873 +         check_segment[0] = check_segment[1] = got_segment;
4874 +         break;
4875 +
4876 +       case R_UBICOM32_32:
4877 +         if (! IS_FDPIC (output_bfd))
4878 +           {
4879 +             check_segment[0] = check_segment[1] = -1;
4880 +             break;
4881 +           }
4882 +         /* Fall through.  */
4883 +       case R_UBICOM32_FUNCDESC_VALUE:
4884 +         {
4885 +           int dynindx;
4886 +           bfd_vma addend = rel->r_addend;
4887 +           bfd_vma offset;
4888 +           offset = _bfd_elf_section_offset (output_bfd, info,
4889 +                                             input_section, rel->r_offset);
4890 +
4891 +           /* If the symbol is dynamic but binds locally, use
4892 +              section+offset.  */
4893 +           if (h && ! UBICOM32FDPIC_SYM_LOCAL (info, h))
4894 +             {
4895 +               if (addend && r_type == R_UBICOM32_FUNCDESC_VALUE)
4896 +                 {
4897 +                   info->callbacks->warning
4898 +                     (info, _("R_UBICOM32_FUNCDESC_VALUE references dynamic symbol with nonzero addend"),
4899 +                      name, input_bfd, input_section, rel->r_offset);
4900 +                   return FALSE;
4901 +                 }
4902 +               dynindx = h->dynindx;
4903 +             }
4904 +           else
4905 +             {
4906 +               if (h)
4907 +                 addend += h->root.u.def.value;
4908 +               else
4909 +                 addend += sym->st_value;
4910 +               if (osec)
4911 +                 addend += osec->output_offset;
4912 +               if (osec && osec->output_section
4913 +                   && ! bfd_is_abs_section (osec->output_section)
4914 +                   && ! bfd_is_und_section (osec->output_section))
4915 +                 dynindx = elf_section_data (osec->output_section)->dynindx;
4916 +               else
4917 +                 dynindx = 0;
4918 +             }
4919 +
4920 +           /* If we're linking an executable at a fixed address, we
4921 +              can omit the dynamic relocation as long as the symbol
4922 +              is defined in the current link unit (which is implied
4923 +              by its output section not being NULL).  */
4924 +           if (info->executable && !info->pie
4925 +               && (!h || UBICOM32FDPIC_SYM_LOCAL (info, h)))
4926 +             {
4927 +               if (osec)
4928 +                 addend += osec->output_section->vma;
4929 +               if (IS_FDPIC (input_bfd)
4930 +                   && (bfd_get_section_flags (output_bfd,
4931 +                                              input_section->output_section)
4932 +                       & (SEC_ALLOC | SEC_LOAD)) == (SEC_ALLOC | SEC_LOAD))
4933 +                 {
4934 +                   if (ubicom32fdpic_osec_readonly_p (output_bfd,
4935 +                                                      input_section
4936 +                                                      ->output_section))
4937 +                     {
4938 +                       info->callbacks->warning
4939 +                         (info,
4940 +                          _("cannot emit fixups in read-only section"),
4941 +                          name, input_bfd, input_section, rel->r_offset);
4942 +                       return FALSE;
4943 +                     }
4944 +                   if (!h || h->root.type != bfd_link_hash_undefweak)
4945 +                     {
4946 +                       /* Only output a reloc for a not deleted entry.  */
4947 +                       if (offset >= (bfd_vma)-2)
4948 +                         ubicom32fdpic_add_rofixup (output_bfd,
4949 +                                                    ubicom32fdpic_gotfixup_section
4950 +                                                    (info), -1, picrel);
4951 +                       else
4952 +                         ubicom32fdpic_add_rofixup (output_bfd,
4953 +                                                    ubicom32fdpic_gotfixup_section
4954 +                                                    (info),
4955 +                                                    offset + input_section
4956 +                                                    ->output_section->vma
4957 +                                                    + input_section->output_offset,
4958 +                                                    picrel);
4959 +
4960 +                       if (r_type == R_UBICOM32_FUNCDESC_VALUE)
4961 +                         {
4962 +                           if (offset >= (bfd_vma)-2)
4963 +                             ubicom32fdpic_add_rofixup
4964 +                               (output_bfd,
4965 +                                ubicom32fdpic_gotfixup_section (info),
4966 +                                -1, picrel);
4967 +                           else
4968 +                             ubicom32fdpic_add_rofixup
4969 +                               (output_bfd,
4970 +                                ubicom32fdpic_gotfixup_section (info),
4971 +                                offset + input_section->output_section->vma
4972 +                                + input_section->output_offset + 4, picrel);
4973 +                         }
4974 +                     }
4975 +                 }
4976 +             }
4977 +           else
4978 +             {
4979 +               if ((bfd_get_section_flags (output_bfd,
4980 +                                           input_section->output_section)
4981 +                    & (SEC_ALLOC | SEC_LOAD)) == (SEC_ALLOC | SEC_LOAD))
4982 +                 {
4983 +                   if (ubicom32fdpic_osec_readonly_p (output_bfd,
4984 +                                                      input_section
4985 +                                                      ->output_section))
4986 +                     {
4987 +                       info->callbacks->warning
4988 +                         (info,
4989 +                          _("cannot emit dynamic relocations in read-only section"),
4990 +                          name, input_bfd, input_section, rel->r_offset);
4991 +                       return FALSE;
4992 +                     }
4993 +                   /* Only output a reloc for a not deleted entry.  */
4994 +                   if (offset >= (bfd_vma)-2)
4995 +                     ubicom32fdpic_add_dyn_reloc (output_bfd,
4996 +                                                  ubicom32fdpic_gotrel_section (info),
4997 +                                                  0, R_UBICOM32_NONE, dynindx, addend, picrel);
4998 +                   else
4999 +                     ubicom32fdpic_add_dyn_reloc (output_bfd,
5000 +                                                  ubicom32fdpic_gotrel_section (info),
5001 +                                                  offset
5002 +                                                  + input_section
5003 +                                                  ->output_section->vma
5004 +                                                  + input_section->output_offset,
5005 +                                                  r_type, dynindx, addend, picrel);
5006 +                 }
5007 +               else if (osec)
5008 +                 addend += osec->output_section->vma;
5009 +               /* We want the addend in-place because dynamic
5010 +                  relocations are REL.  Setting relocation to it
5011 +                  should arrange for it to be installed.  */
5012 +               relocation = addend - rel->r_addend;
5013 +             }
5014 +
5015 +           if (r_type == R_UBICOM32_FUNCDESC_VALUE && offset < (bfd_vma)-2)
5016 +             {
5017 +               /* If we've omitted the dynamic relocation, just emit
5018 +                  the fixed addresses of the symbol and of the local
5019 +                  GOT base offset.  */
5020 +               if (info->executable && !info->pie
5021 +                   && (!h || UBICOM32FDPIC_SYM_LOCAL (info, h)))
5022 +                 bfd_put_32 (output_bfd,
5023 +                             ubicom32fdpic_got_section (info)->output_section->vma
5024 +                             + ubicom32fdpic_got_section (info)->output_offset
5025 +                             + ubicom32fdpic_got_initial_offset (info),
5026 +                             contents + rel->r_offset + 4);
5027 +               else
5028 +                 /* A function descriptor used for lazy or local
5029 +                    resolving is initialized such that its high word
5030 +                    contains the output section index in which the
5031 +                    PLT entries are located, and the low word
5032 +                    contains the offset of the lazy PLT entry entry
5033 +                    point into that section.  */
5034 +                 bfd_put_32 (output_bfd,
5035 +                             h && ! UBICOM32FDPIC_SYM_LOCAL (info, h)
5036 +                             ? 0
5037 +                             : ubicom32fdpic_osec_to_segment (output_bfd,
5038 +                                                              sec
5039 +                                                              ->output_section),
5040 +                             contents + rel->r_offset + 4);
5041 +             }
5042 +         }
5043 +         check_segment[0] = check_segment[1] = got_segment;
5044 +         break;
5045 +
5046 +       default:
5047 +         check_segment[0] = isec_segment;
5048 +         check_segment[1] = sec
5049 +           ? ubicom32fdpic_osec_to_segment (output_bfd, sec->output_section)
5050 +           : (unsigned)-1;
5051 +         break;
5052 +       }
5053 +
5054 +      if (check_segment[0] != check_segment[1] && IS_FDPIC (output_bfd))
5055 +       {
5056 +#if 1 /* If you take this out, remove the #error from fdpic-static-6.d
5057 +        in the ld testsuite.  */
5058 +         /* This helps catch problems in GCC while we can't do more
5059 +            than static linking.  The idea is to test whether the
5060 +            input file basename is crt0.o only once.  */
5061 +         if (silence_segment_error == 1)
5062 +           silence_segment_error =
5063 +             (strlen (input_bfd->filename) == 6
5064 +              && strcmp (input_bfd->filename, "crt0.o") == 0)
5065 +             || (strlen (input_bfd->filename) > 6
5066 +                 && strcmp (input_bfd->filename
5067 +                            + strlen (input_bfd->filename) - 7,
5068 +                            "/crt0.o") == 0)
5069 +             ? -1 : 0;
5070 +#endif
5071 +         if (!silence_segment_error
5072 +             /* We don't want duplicate errors for undefined
5073 +                symbols.  */
5074 +             && !(picrel && picrel->symndx == -1
5075 +                  && picrel->d.h->root.type == bfd_link_hash_undefined))
5076 +           info->callbacks->warning
5077 +             (info,
5078 +              (info->shared || info->pie)
5079 +              ? _("relocations between different segments are not supported")
5080 +              : _("warning: relocation references a different segment"),
5081 +              name, input_bfd, input_section, rel->r_offset);
5082 +         if (!silence_segment_error && (info->shared || info->pie))
5083 +           return FALSE;
5084 +         elf_elfheader (output_bfd)->e_flags |= 0x80000000;
5085 +       }
5086 +
5087 +      switch (r_type)
5088 +       {
5089 +       case R_UBICOM32_LO16:
5090 +         r = ubicom32_elf_relocate_lo16 (input_bfd, rel, contents, relocation);
5091 +         break;
5092 +
5093 +       case R_UBICOM32_HI16:
5094 +         r = ubicom32_elf_relocate_hi16 (input_bfd, rel, contents, relocation);
5095 +         break;
5096 +
5097 +       case R_UBICOM32_HI24:
5098 +         r = ubicom32_elf_relocate_hi24 (input_bfd, rel, contents, relocation);
5099 +         break;
5100 +
5101 +       case R_UBICOM32_LO7_S:
5102 +         r = ubicom32_elf_relocate_lo7_s (input_bfd, rel, contents, relocation);
5103 +         break;
5104 +
5105 +       case R_UBICOM32_LO7_2_S:
5106 +         r = ubicom32_elf_relocate_lo7_2_s (input_bfd, rel, contents, relocation);
5107 +         break;
5108 +
5109 +       case R_UBICOM32_LO7_4_S:
5110 +         r = ubicom32_elf_relocate_lo7_4_s (input_bfd, rel, contents, relocation);
5111 +         break;
5112 +
5113 +       case R_UBICOM32_LO7_D:
5114 +         r = ubicom32_elf_relocate_lo7_d (input_bfd, rel, contents, relocation);
5115 +         break;
5116 +
5117 +       case R_UBICOM32_LO7_2_D:
5118 +         r = ubicom32_elf_relocate_lo7_2_d (input_bfd, rel, contents, relocation);
5119 +         break;
5120 +
5121 +       case R_UBICOM32_LO7_4_D:
5122 +         r = ubicom32_elf_relocate_lo7_4_d (input_bfd, rel, contents, relocation);
5123 +         break;
5124 +
5125 +       case R_UBICOM32_24_PCREL:
5126 +         r = ubicom32_elf_relocate_pcrel24 (input_bfd, input_section, rel, contents, relocation);
5127 +         break;
5128 +
5129 +       case R_UBICOM32_LO7_CALLI:
5130 +         r = ubicom32_elf_relocate_lo_calli (input_bfd, rel, contents, relocation, 7);
5131 +         break;
5132 +
5133 +       case R_UBICOM32_LO16_CALLI:
5134 +         r = ubicom32_elf_relocate_lo_calli (input_bfd, rel, contents, relocation, 18);
5135 +         break;
5136 +
5137 +       case R_UBICOM32_GOTOFFSET_LO:
5138 +         r = ubicom32_elf_relocate_gotoffset_lo(input_bfd, input_section, rel, contents, relocation);
5139 +         break;
5140 +
5141 +       case R_UBICOM32_FUNCDESC_GOTOFFSET_LO:
5142 +         r = ubicom32_elf_relocate_funcdesc_gotoffset_lo(input_bfd, input_section, rel, contents, relocation);
5143 +         break;
5144 +
5145 +       case R_UBICOM32_32:
5146 +       case R_UBICOM32_FUNCDESC:
5147 +         /* relocation &= ~(0xff << 24); */
5148 +         /* FALLTHROUGH */
5149 +
5150 +       default:
5151 +         r = ubicom32_final_link_relocate (howto, input_bfd, input_section,
5152 +                                           contents, rel, relocation);
5153 +         break;
5154 +       }
5155 +    }
5156 +
5157 +  return TRUE;
5158 +}
5159 +\f
5160 +#define elf_info_to_howto                      ubicom32_info_to_howto_rela
5161 +#define elf_info_to_howto_rel                  NULL
5162 +
5163 +#define bfd_elf32_bfd_reloc_type_lookup                ubicom32_reloc_type_lookup
5164 +#define bfd_elf32_bfd_reloc_name_lookup                ubicom32_reloc_name_lookup
5165 +#define bfd_elf32_bfd_relax_section            ubicom32_elf_relax_section
5166 +
5167 +#define elf_backend_relocate_section           ubicom32_elf_relocate_section
5168 +#define elf_backend_gc_mark_hook               ubicom32_elf_gc_mark_hook
5169 +#define elf_backend_gc_sweep_hook              ubicom32_elf_gc_sweep_hook
5170 +#define elf_backend_check_relocs                ubicom32_elf_check_relocs
5171 +#define elf_backend_object_p                   ubicom32_elf_object_p
5172 +
5173 +#define elf_backend_discard_info               ubicom32_elf_discard_info
5174 +
5175 +#define elf_backend_can_gc_sections            1
5176 +
5177 +#define bfd_elf32_bfd_set_private_flags                ubicom32_elf_set_private_flags
5178 +#define bfd_elf32_bfd_copy_private_bfd_data    ubicom32_elf_copy_private_bfd_data
5179 +#define bfd_elf32_bfd_merge_private_bfd_data   ubicom32_elf_merge_private_bfd_data
5180 +#define bfd_elf32_bfd_print_private_bfd_data   ubicom32_elf_print_private_bfd_data
5181 +
5182 +#define bfd_elf32_bfd_extcode_relax            NULL
5183 +
5184 +#define TARGET_BIG_SYM  bfd_elf32_ubicom32_vec
5185 +#define TARGET_BIG_NAME  "elf32-ubicom32"
5186 +
5187 +#define ELF_ARCH        bfd_arch_ubicom32
5188 +#define ELF_MACHINE_CODE EM_UBICOM32
5189 +#define ELF_MAXPAGESIZE  0x1000
5190 +
5191 +#include "elf32-target.h"
5192 +
5193 +#undef TARGET_BIG_SYM
5194 +#define TARGET_BIG_SYM  bfd_elf32_ubicom32fdpic_vec
5195 +#undef TARGET_BIG_NAME
5196 +#define TARGET_BIG_NAME  "elf32-ubicom32fdpic"
5197 +#undef elf32_bed
5198 +#define        elf32_bed               elf32_ubicom32fdpic_bed
5199 +
5200 +#undef elf_backend_relocate_section
5201 +#define elf_backend_relocate_section           ubicom32fdpic_elf_relocate_section
5202 +
5203 +#undef elf_backend_check_relocs
5204 +#define elf_backend_check_relocs                ubicom32fdpic_elf_check_relocs
5205 +
5206 +#undef elf_backend_gc_sweep_hook
5207 +#define elf_backend_gc_sweep_hook              ubicom32fdpic_elf_gc_sweep_hook
5208 +#undef bfd_elf32_bfd_link_hash_table_create
5209 +#define bfd_elf32_bfd_link_hash_table_create \
5210 +               ubicom32fdpic_elf_link_hash_table_create
5211 +#undef elf_backend_always_size_sections
5212 +#define elf_backend_always_size_sections \
5213 +               ubicom32fdpic_elf_always_size_sections
5214 +#undef elf_backend_modify_program_headers
5215 +#define elf_backend_modify_program_headers \
5216 +               ubicom32fdpic_elf_modify_program_headers
5217 +#undef bfd_elf32_bfd_copy_private_bfd_data
5218 +#define bfd_elf32_bfd_copy_private_bfd_data \
5219 +               ubicom32fdpic_elf_copy_private_bfd_data
5220 +
5221 +#undef elf_backend_create_dynamic_sections
5222 +#define elf_backend_create_dynamic_sections \
5223 +               ubicom32fdpic_elf_create_dynamic_sections
5224 +#undef elf_backend_adjust_dynamic_symbol
5225 +#define elf_backend_adjust_dynamic_symbol \
5226 +               ubicom32fdpic_elf_adjust_dynamic_symbol
5227 +#undef elf_backend_size_dynamic_sections
5228 +#define elf_backend_size_dynamic_sections \
5229 +               ubicom32fdpic_elf_size_dynamic_sections
5230 +#undef elf_backend_finish_dynamic_symbol
5231 +#define elf_backend_finish_dynamic_symbol \
5232 +               ubicom32fdpic_elf_finish_dynamic_symbol
5233 +#undef elf_backend_finish_dynamic_sections
5234 +#define elf_backend_finish_dynamic_sections \
5235 +               ubicom32fdpic_elf_finish_dynamic_sections
5236 +
5237 +#undef elf_backend_can_make_relative_eh_frame
5238 +#define elf_backend_can_make_relative_eh_frame \
5239 +               ubicom32fdpic_elf_use_relative_eh_frame
5240 +#undef elf_backend_can_make_lsda_relative_eh_frame
5241 +#define elf_backend_can_make_lsda_relative_eh_frame \
5242 +               ubicom32fdpic_elf_use_relative_eh_frame
5243 +#undef elf_backend_encode_eh_address
5244 +#define elf_backend_encode_eh_address \
5245 +               ubicom32fdpic_elf_encode_eh_address
5246 +
5247 +#undef elf_backend_may_use_rel_p
5248 +#define elf_backend_may_use_rel_p       1
5249 +#undef elf_backend_may_use_rela_p
5250 +#define elf_backend_may_use_rela_p      1
5251 +/* We use REL for dynamic relocations only.  */
5252 +#undef elf_backend_default_use_rela_p
5253 +#define elf_backend_default_use_rela_p  1
5254 +
5255 +#undef elf_backend_omit_section_dynsym
5256 +#define elf_backend_omit_section_dynsym ubicom32fdpic_elf_link_omit_section_dynsym
5257 +
5258 +#undef elf_backend_can_refcount
5259 +#define elf_backend_can_refcount 1
5260 +
5261 +#undef elf_backend_want_got_plt
5262 +#define elf_backend_want_got_plt 0
5263 +
5264 +#undef elf_backend_plt_readonly
5265 +#define elf_backend_plt_readonly 1
5266 +
5267 +#undef elf_backend_want_plt_sym
5268 +#define elf_backend_want_plt_sym 1
5269 +
5270 +#undef elf_backend_got_header_size
5271 +#define elf_backend_got_header_size     12
5272 +
5273 +#undef elf_backend_rela_normal
5274 +#define elf_backend_rela_normal         1
5275 +
5276 +#include "elf32-target.h"
5277 --- a/bfd/libbfd.h
5278 +++ b/bfd/libbfd.h
5279 @@ -1689,6 +1689,39 @@ static const char *const bfd_reloc_code_
5280    "BFD_RELOC_IP2K_FR_OFFSET",
5281    "BFD_RELOC_VPE4KMATH_DATA",
5282    "BFD_RELOC_VPE4KMATH_INSN",
5283 +  "BFD_RELOC_UBICOM32_21_PCREL",
5284 +  "BFD_RELOC_UBICOM32_24_PCREL",
5285 +  "BFD_RELOC_UBICOM32_HI24",
5286 +  "BFD_RELOC_UBICOM32_LO7_S",
5287 +  "BFD_RELOC_UBICOM32_LO7_2_S",
5288 +  "BFD_RELOC_UBICOM32_LO7_4_S",
5289 +  "BFD_RELOC_UBICOM32_LO7_D",
5290 +  "BFD_RELOC_UBICOM32_LO7_2_D",
5291 +  "BFD_RELOC_UBICOM32_LO7_4_D",
5292 +  "BFD_RELOC_UBICOM32_LO7_CALLI",
5293 +  "BFD_RELOC_UBICOM32_LO16_CALLI",
5294 +  "BFD_RELOC_UBICOM32_GOT_HI24",
5295 +  "BFD_RELOC_UBICOM32_GOT_LO7_S",
5296 +  "BFD_RELOC_UBICOM32_GOT_LO7_2_S",
5297 +  "BFD_RELOC_UBICOM32_GOT_LO7_4_S",
5298 +  "BFD_RELOC_UBICOM32_GOT_LO7_D",
5299 +  "BFD_RELOC_UBICOM32_GOT_LO7_2_D",
5300 +  "BFD_RELOC_UBICOM32_GOT_LO7_4_D",
5301 +  "BFD_RELOC_UBICOM32_FUNCDESC_GOT_HI24",
5302 +  "BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_S",
5303 +  "BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_2_S",
5304 +  "BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_4_S",
5305 +  "BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_D",
5306 +  "BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_2_D",
5307 +  "BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_4_D",
5308 +  "BFD_RELOC_UBICOM32_GOT_LO7_CALLI",
5309 +  "BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_CALLI",
5310 +  "BFD_RELOC_UBICOM32_FUNCDESC_VALUE",
5311 +  "BFD_RELOC_UBICOM32_FUNCDESC",
5312 +  "BFD_RELOC_UBICOM32_GOTOFFSET_LO",
5313 +  "BFD_RELOC_UBICOM32_GOTOFFSET_HI",
5314 +  "BFD_RELOC_UBICOM32_FUNCDESC_GOTOFFSET_LO",
5315 +  "BFD_RELOC_UBICOM32_FUNCDESC_GOTOFFSET_HI",
5316    "BFD_RELOC_VTABLE_INHERIT",
5317    "BFD_RELOC_VTABLE_ENTRY",
5318    "BFD_RELOC_IA64_IMM14",
5319 --- a/bfd/Makefile.am
5320 +++ b/bfd/Makefile.am
5321 @@ -114,6 +114,7 @@ ALL_MACHINES = \
5322         cpu-tic4x.lo \
5323         cpu-tic54x.lo \
5324         cpu-tic80.lo \
5325 +       cpu-ubicom32.lo \
5326         cpu-v850.lo \
5327         cpu-vax.lo \
5328         cpu-we32k.lo \
5329 @@ -180,6 +181,7 @@ ALL_MACHINES_CFILES = \
5330         cpu-tic4x.c \
5331         cpu-tic54x.c \
5332         cpu-tic80.c \
5333 +       cpu-ubicom32.c \
5334         cpu-v850.c \
5335         cpu-vax.c \
5336         cpu-we32k.c \
5337 @@ -292,6 +294,7 @@ BFD32_BACKENDS = \
5338         elfxx-sparc.lo \
5339         elf32-sparc.lo \
5340         elf32-spu.lo \
5341 +       elf32-ubicom32.lo \
5342         elf32-v850.lo \
5343         elf32-vax.lo \
5344         elf32-xstormy16.lo \
5345 @@ -473,6 +476,7 @@ BFD32_BACKENDS_CFILES = \
5346         elfxx-sparc.c \
5347         elf32-sparc.c \
5348         elf32-spu.c \
5349 +       elf32-ubicom32.c \
5350         elf32-v850.c \
5351         elf32-vax.c \
5352         elf32-xstormy16.c \
5353 @@ -1131,6 +1135,7 @@ cpu-tic30.lo: cpu-tic30.c $(INCDIR)/file
5354  cpu-tic4x.lo: cpu-tic4x.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
5355  cpu-tic54x.lo: cpu-tic54x.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
5356  cpu-tic80.lo: cpu-tic80.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
5357 +cpu-ubicom32.lo: cpu-ubicom32.c $(INCDIR)/filenames.h
5358  cpu-v850.lo: cpu-v850.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
5359    $(INCDIR)/safe-ctype.h
5360  cpu-vax.lo: cpu-vax.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
5361 @@ -1556,6 +1561,10 @@ elf32-spu.lo: elf32-spu.c $(INCDIR)/file
5362    $(INCDIR)/bfdlink.h $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
5363    $(INCDIR)/elf/external.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/spu.h \
5364    $(INCDIR)/elf/reloc-macros.h elf32-spu.h elf32-target.h
5365 +elf32-ubicom32.lo: elf32-ubicom32.c $(INCDIR)/filenames.h elf-bfd.h \
5366 +  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
5367 +  $(INCDIR)/bfdlink.h $(INCDIR)/elf/ubicom32.h $(INCDIR)/elf/reloc-macros.h \
5368 +  elf32-target.h
5369  elf32-v850.lo: elf32-v850.c $(INCDIR)/filenames.h $(INCDIR)/bfdlink.h \
5370    $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
5371    $(INCDIR)/elf/external.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/v850.h \
5372 --- a/bfd/Makefile.in
5373 +++ b/bfd/Makefile.in
5374 @@ -367,6 +367,7 @@ ALL_MACHINES = \
5375         cpu-tic4x.lo \
5376         cpu-tic54x.lo \
5377         cpu-tic80.lo \
5378 +       cpu-ubicom32.lo \
5379         cpu-v850.lo \
5380         cpu-vax.lo \
5381         cpu-we32k.lo \
5382 @@ -433,6 +434,7 @@ ALL_MACHINES_CFILES = \
5383         cpu-tic4x.c \
5384         cpu-tic54x.c \
5385         cpu-tic80.c \
5386 +       cpu-ubicom32.c \
5387         cpu-v850.c \
5388         cpu-vax.c \
5389         cpu-we32k.c \
5390 @@ -546,6 +548,7 @@ BFD32_BACKENDS = \
5391         elfxx-sparc.lo \
5392         elf32-sparc.lo \
5393         elf32-spu.lo \
5394 +       elf32-ubicom32.lo \
5395         elf32-v850.lo \
5396         elf32-vax.lo \
5397         elf32-xstormy16.lo \
5398 @@ -727,6 +730,7 @@ BFD32_BACKENDS_CFILES = \
5399         elfxx-sparc.c \
5400         elf32-sparc.c \
5401         elf32-spu.c \
5402 +       elf32-ubicom32.c \
5403         elf32-v850.c \
5404         elf32-vax.c \
5405         elf32-xstormy16.c \
5406 @@ -1715,6 +1719,7 @@ cpu-tic30.lo: cpu-tic30.c $(INCDIR)/file
5407  cpu-tic4x.lo: cpu-tic4x.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
5408  cpu-tic54x.lo: cpu-tic54x.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
5409  cpu-tic80.lo: cpu-tic80.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
5410 +cpu-ubicom32.lo: cpu-ubicom32.c $(INCDIR)/filenames.h
5411  cpu-v850.lo: cpu-v850.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
5412    $(INCDIR)/safe-ctype.h
5413  cpu-vax.lo: cpu-vax.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
5414 @@ -2140,6 +2145,10 @@ elf32-spu.lo: elf32-spu.c $(INCDIR)/file
5415    $(INCDIR)/bfdlink.h $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
5416    $(INCDIR)/elf/external.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/spu.h \
5417    $(INCDIR)/elf/reloc-macros.h elf32-spu.h elf32-target.h
5418 +elf32-ubicom32.lo: elf32-ubicom32.c $(INCDIR)/filenames.h elf-bfd.h \
5419 +  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
5420 +  $(INCDIR)/bfdlink.h $(INCDIR)/elf/ubicom32.h $(INCDIR)/elf/reloc-macros.h \
5421 +  elf32-target.h
5422  elf32-v850.lo: elf32-v850.c $(INCDIR)/filenames.h $(INCDIR)/bfdlink.h \
5423    $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
5424    $(INCDIR)/elf/external.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/v850.h \
5425 --- a/bfd/reloc.c
5426 +++ b/bfd/reloc.c
5427 @@ -4227,6 +4227,75 @@ ENUMDOC
5428    Scenix VPE4K coprocessor - data/insn-space addressing
5429  
5430  ENUM
5431 +  BFD_RELOC_UBICOM32_21_PCREL
5432 +ENUMX
5433 +  BFD_RELOC_UBICOM32_24_PCREL
5434 +ENUMX
5435 +  BFD_RELOC_UBICOM32_HI24
5436 +ENUMX
5437 +  BFD_RELOC_UBICOM32_LO7_S
5438 +ENUMX
5439 +  BFD_RELOC_UBICOM32_LO7_2_S
5440 +ENUMX
5441 +  BFD_RELOC_UBICOM32_LO7_4_S
5442 +ENUMX
5443 +  BFD_RELOC_UBICOM32_LO7_D
5444 +ENUMX
5445 +  BFD_RELOC_UBICOM32_LO7_2_D
5446 +ENUMX
5447 +  BFD_RELOC_UBICOM32_LO7_4_D
5448 +ENUMX
5449 +  BFD_RELOC_UBICOM32_LO7_CALLI
5450 +ENUMX
5451 +  BFD_RELOC_UBICOM32_LO16_CALLI
5452 +ENUMX
5453 +  BFD_RELOC_UBICOM32_GOT_HI24
5454 +ENUMX
5455 +  BFD_RELOC_UBICOM32_GOT_LO7_S
5456 +ENUMX
5457 +  BFD_RELOC_UBICOM32_GOT_LO7_2_S
5458 +ENUMX
5459 +  BFD_RELOC_UBICOM32_GOT_LO7_4_S
5460 +ENUMX
5461 +  BFD_RELOC_UBICOM32_GOT_LO7_D
5462 +ENUMX
5463 +  BFD_RELOC_UBICOM32_GOT_LO7_2_D
5464 +ENUMX
5465 +  BFD_RELOC_UBICOM32_GOT_LO7_4_D
5466 +ENUMX
5467 +  BFD_RELOC_UBICOM32_FUNCDESC_GOT_HI24
5468 +ENUMX
5469 +  BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_S
5470 +ENUMX
5471 +  BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_2_S
5472 +ENUMX
5473 +  BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_4_S
5474 +ENUMX
5475 +  BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_D
5476 +ENUMX
5477 +  BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_2_D
5478 +ENUMX
5479 +  BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_4_D
5480 +ENUMX
5481 +  BFD_RELOC_UBICOM32_GOT_LO7_CALLI
5482 +ENUMX
5483 +  BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_CALLI
5484 +ENUMX
5485 +  BFD_RELOC_UBICOM32_FUNCDESC_VALUE
5486 +ENUMX
5487 +  BFD_RELOC_UBICOM32_FUNCDESC
5488 +ENUMX
5489 +  BFD_RELOC_UBICOM32_GOTOFFSET_LO
5490 +ENUMX
5491 +  BFD_RELOC_UBICOM32_GOTOFFSET_HI
5492 +ENUMX
5493 +  BFD_RELOC_UBICOM32_FUNCDESC_GOTOFFSET_LO
5494 +ENUMX
5495 +  BFD_RELOC_UBICOM32_FUNCDESC_GOTOFFSET_HI
5496 +ENUMDOC
5497 +  Ubicom UBICOM32 Relocations.
5498 +
5499 +ENUM
5500    BFD_RELOC_VTABLE_INHERIT
5501  ENUMX
5502    BFD_RELOC_VTABLE_ENTRY
5503 --- a/bfd/targets.c
5504 +++ b/bfd/targets.c
5505 @@ -663,6 +663,8 @@ extern const bfd_target bfd_elf32_spu_ve
5506  extern const bfd_target bfd_elf32_tradbigmips_vec;
5507  extern const bfd_target bfd_elf32_tradlittlemips_vec;
5508  extern const bfd_target bfd_elf32_us_cris_vec;
5509 +extern const bfd_target bfd_elf32_ubicom32_vec;
5510 +extern const bfd_target bfd_elf32_ubicom32fdpic_vec;
5511  extern const bfd_target bfd_elf32_v850_vec;
5512  extern const bfd_target bfd_elf32_vax_vec;
5513  extern const bfd_target bfd_elf32_xc16x_vec;
5514 @@ -1001,6 +1003,7 @@ static const bfd_target * const _bfd_tar
5515         &bfd_elf32_tradbigmips_vec,
5516         &bfd_elf32_tradlittlemips_vec,
5517         &bfd_elf32_us_cris_vec,
5518 +       &bfd_elf32_ubicom32_vec,
5519         &bfd_elf32_v850_vec,
5520         &bfd_elf32_vax_vec,
5521         &bfd_elf32_xc16x_vec,
5522 --- a/binutils/Makefile.am
5523 +++ b/binutils/Makefile.am
5524 @@ -584,7 +584,7 @@ readelf.o: readelf.c config.h sysdep.h $
5525    $(INCDIR)/elf/dlx.h $(INCDIR)/elf/fr30.h $(INCDIR)/elf/frv.h \
5526    $(INCDIR)/elf/hppa.h $(INCDIR)/elf/i386.h $(INCDIR)/elf/i370.h \
5527    $(INCDIR)/elf/i860.h $(INCDIR)/elf/i960.h $(INCDIR)/elf/ia64.h \
5528 -  $(INCDIR)/elf/ip2k.h $(INCDIR)/elf/iq2000.h $(INCDIR)/elf/m32c.h \
5529 +  $(INCDIR)/elf/ip2k.h $(INCDIR)/elf/ubicom32.h $(INCDIR)/elf/iq2000.h $(INCDIR)/elf/m32c.h \
5530    $(INCDIR)/elf/m32r.h $(INCDIR)/elf/m68k.h $(INCDIR)/elf/m68hc11.h \
5531    $(INCDIR)/elf/mcore.h $(INCDIR)/elf/mep.h $(INCDIR)/elf/mips.h \
5532    $(INCDIR)/elf/mmix.h $(INCDIR)/elf/mn10200.h $(INCDIR)/elf/mn10300.h \
5533 --- a/binutils/Makefile.in
5534 +++ b/binutils/Makefile.in
5535 @@ -1338,7 +1338,7 @@ readelf.o: readelf.c config.h sysdep.h $
5536    $(INCDIR)/elf/dlx.h $(INCDIR)/elf/fr30.h $(INCDIR)/elf/frv.h \
5537    $(INCDIR)/elf/hppa.h $(INCDIR)/elf/i386.h $(INCDIR)/elf/i370.h \
5538    $(INCDIR)/elf/i860.h $(INCDIR)/elf/i960.h $(INCDIR)/elf/ia64.h \
5539 -  $(INCDIR)/elf/ip2k.h $(INCDIR)/elf/iq2000.h $(INCDIR)/elf/m32c.h \
5540 +  $(INCDIR)/elf/ip2k.h $(INCDIR)/elf/ubicom32.h $(INCDIR)/elf/iq2000.h $(INCDIR)/elf/m32c.h \
5541    $(INCDIR)/elf/m32r.h $(INCDIR)/elf/m68k.h $(INCDIR)/elf/m68hc11.h \
5542    $(INCDIR)/elf/mcore.h $(INCDIR)/elf/mep.h $(INCDIR)/elf/mips.h \
5543    $(INCDIR)/elf/mmix.h $(INCDIR)/elf/mn10200.h $(INCDIR)/elf/mn10300.h \
5544 --- a/binutils/readelf.c
5545 +++ b/binutils/readelf.c
5546 @@ -152,6 +152,7 @@
5547  #include "elf/sh.h"
5548  #include "elf/sparc.h"
5549  #include "elf/spu.h"
5550 +#include "elf/ubicom32.h"
5551  #include "elf/v850.h"
5552  #include "elf/vax.h"
5553  #include "elf/x86-64.h"
5554 @@ -612,6 +613,7 @@ guess_is_rela (unsigned int e_machine)
5555      case EM_SPARC32PLUS:
5556      case EM_SPARCV9:
5557      case EM_SPU:
5558 +    case EM_UBICOM32:
5559      case EM_V850:
5560      case EM_CYGNUS_V850:
5561      case EM_VAX:
5562 @@ -1159,6 +1161,10 @@ dump_relocations (FILE *file,
5563           rtype = elf_crx_reloc_type (type);
5564           break;
5565  
5566 +       case EM_UBICOM32:
5567 +         rtype = elf_ubicom32_reloc_type (type);
5568 +         break;
5569 +
5570         case EM_VAX:
5571           rtype = elf_vax_reloc_type (type);
5572           break;
5573 @@ -1812,6 +1818,7 @@ get_machine_name (unsigned e_machine)
5574      case EM_DLX:               return "OpenDLX";
5575      case EM_IP2K_OLD:
5576      case EM_IP2K:              return "Ubicom IP2xxx 8-bit microcontrollers";
5577 +    case EM_UBICOM32:          return "Ubicom32 32-bit microcontrollers";
5578      case EM_IQ2000:            return "Vitesse IQ2000";
5579      case EM_XTENSA_OLD:
5580      case EM_XTENSA:            return "Tensilica Xtensa Processor";
5581 --- a/config.sub
5582 +++ b/config.sub
5583 @@ -285,6 +285,7 @@ case $basic_machine in
5584         | sparcv8 | sparcv9 | sparcv9b | sparcv9v \
5585         | spu | strongarm \
5586         | tahoe | thumb | tic4x | tic80 | tron \
5587 +       | ubicom32 \
5588         | v850 | v850e \
5589         | we32k \
5590         | x86 | xc16x | xscale | xscalee[bl] | xstormy16 | xtensa \
5591 @@ -370,6 +371,7 @@ case $basic_machine in
5592         | tahoe-* | thumb-* \
5593         | tic30-* | tic4x-* | tic54x-* | tic55x-* | tic6x-* | tic80-* | tile-* \
5594         | tron-* \
5595 +       | ubicom32-* \
5596         | v850-* | v850e-* | vax-* \
5597         | we32k-* \
5598         | x86-* | x86_64-* | xc16x-* | xps100-* | xscale-* | xscalee[bl]-* \
5599 --- a/configure
5600 +++ b/configure
5601 @@ -2666,6 +2666,12 @@ case "${target}" in
5602    xtensa*-*-*)
5603      noconfigdirs="$noconfigdirs ${libgcj}"
5604      ;;
5605 +  ubicom32-*-*linux*)
5606 +    noconfigdirs="$noconfigdirs target-libffi target-newlib"
5607 +    ;;
5608 +  ubicom32-*-*)
5609 +    noconfigdirs="$noconfigdirs target-libffi target-newlib"
5610 +    ;;
5611    ip2k-*-*)
5612      noconfigdirs="$noconfigdirs target-libiberty target-libstdc++-v3 ${libgcj}"
5613      ;;
5614 --- a/configure.ac
5615 +++ b/configure.ac
5616 @@ -915,6 +915,12 @@ case "${target}" in
5617    xtensa*-*-*)
5618      noconfigdirs="$noconfigdirs ${libgcj}"
5619      ;;
5620 +  ubicom32-*-*linux*)
5621 +    noconfigdirs="$noconfigdirs target-libffi target-newlib"
5622 +    ;;
5623 +  ubicom32-*-*)
5624 +    noconfigdirs="$noconfigdirs target-libffi"
5625 +    ;;
5626    ip2k-*-*)
5627      noconfigdirs="$noconfigdirs target-libiberty target-libstdc++-v3 ${libgcj}"
5628      ;;
5629 --- /dev/null
5630 +++ b/gas/config/tc-ubicom32.c
5631 @@ -0,0 +1,609 @@
5632 +/* tc-ubicom32.c -- Assembler for the Ubicom32
5633 +   Copyright (C) 2000, 2002 Free Software Foundation.
5634 +
5635 +   This file is part of GAS, the GNU Assembler.
5636 +
5637 +   GAS is free software; you can redistribute it and/or modify
5638 +   it under the terms of the GNU General Public License as published by
5639 +   the Free Software Foundation; either version 2, or (at your option)
5640 +   any later version.
5641 +
5642 +   GAS is distributed in the hope that it will be useful,
5643 +   but WITHOUT ANY WARRANTY; without even the implied warranty of
5644 +   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
5645 +   GNU General Public License for more details.
5646 +
5647 +   You should have received a copy of the GNU General Public License
5648 +   along with GAS; see the file COPYING.  If not, write to
5649 +   the Free Software Foundation, 59 Temple Place - Suite 330,
5650 +   Boston, MA 02111-1307, USA.  */
5651 +
5652 +#include <stdio.h>
5653 +#include <ctype.h>
5654 +
5655 +#include "as.h"
5656 +#include "dwarf2dbg.h"
5657 +#include "subsegs.h"
5658 +#include "symcat.h"
5659 +#include "opcodes/ubicom32-desc.h"
5660 +#include "opcodes/ubicom32-opc.h"
5661 +#include "cgen.h"
5662 +#include "elf/common.h"
5663 +#include "elf/ubicom32.h"
5664 +#include "libbfd.h"
5665 +
5666 +extern void gas_cgen_md_operand (expressionS *);
5667 +
5668 +/* Structure to hold all of the different components describing
5669 +   an individual instruction.  */
5670 +typedef struct
5671 +{
5672 +  const CGEN_INSN *    insn;
5673 +  const CGEN_INSN *    orig_insn;
5674 +  CGEN_FIELDS          fields;
5675 +#if CGEN_INT_INSN_P
5676 +  CGEN_INSN_INT         buffer [1];
5677 +#define INSN_VALUE(buf) (*(buf))
5678 +#else
5679 +  unsigned char         buffer [CGEN_MAX_INSN_SIZE];
5680 +#define INSN_VALUE(buf) (buf)
5681 +#endif
5682 +  char *               addr;
5683 +  fragS *              frag;
5684 +  int                   num_fixups;
5685 +  fixS *                fixups [GAS_CGEN_MAX_FIXUPS];
5686 +  int                   indices [MAX_OPERAND_INSTANCES];
5687 +}
5688 +ubicom32_insn;
5689 +
5690 +const char comment_chars[]        = ";";
5691 +const char line_comment_chars[]   = "#";
5692 +const char line_separator_chars[] = "";
5693 +const char EXP_CHARS[]            = "eE";
5694 +const char FLT_CHARS[]            = "dD";
5695 +
5696 +/* Ubicom32 specific function to handle FD-PIC pointer initializations.  */
5697 +
5698 +static void
5699 +ubicom32_pic_ptr (int nbytes)
5700 +{
5701 +  expressionS exp;
5702 +  char *p;
5703 +
5704 +  if (nbytes != 4)
5705 +    abort ();
5706 +
5707 +#ifdef md_flush_pending_output
5708 +  md_flush_pending_output ();
5709 +#endif
5710 +
5711 +  if (is_it_end_of_statement ())
5712 +    {
5713 +      demand_empty_rest_of_line ();
5714 +      return;
5715 +    }
5716 +
5717 +#ifdef md_cons_align
5718 +  md_cons_align (nbytes);
5719 +#endif
5720 +
5721 +  do
5722 +    {
5723 +      bfd_reloc_code_real_type reloc_type = BFD_RELOC_UBICOM32_FUNCDESC;
5724 +
5725 +      if (strncasecmp (input_line_pointer, "%funcdesc(", strlen("%funcdesc(")) == 0)
5726 +       {
5727 +         input_line_pointer += strlen("%funcdesc(");
5728 +         expression (&exp);
5729 +         if (*input_line_pointer == ')')
5730 +           input_line_pointer++;
5731 +         else
5732 +           as_bad (_("missing ')'"));
5733 +       }
5734 +      else
5735 +       as_bad ("missing funcdesc in picptr");
5736 +
5737 +      p = frag_more (4);
5738 +      memset (p, 0, 4);
5739 +      fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &exp, 0,
5740 +                  reloc_type);
5741 +    }
5742 +  while (*input_line_pointer++ == ',');
5743 +
5744 +  input_line_pointer--;                        /* Put terminator back into stream. */
5745 +  demand_empty_rest_of_line ();
5746 +}
5747 +
5748 +/* The target specific pseudo-ops which we support.  */
5749 +const pseudo_typeS md_pseudo_table[] =
5750 +{
5751 +    { "file",  (void (*)(int))dwarf2_directive_file,   0 },
5752 +    { "loc",   dwarf2_directive_loc,   0 },
5753 +    { "picptr", ubicom32_pic_ptr,      4 },
5754 +    { "word",  cons,                   4 },
5755 +    { NULL,    NULL,                   0 }
5756 +};
5757 +
5758 +/* A table of the register symbols */
5759 +#if 0
5760 +static symbolS *ubicom32_register_table[40];   /* 32 data & 8 address */
5761 +#endif
5762 +
5763 +\f
5764 +#define OPTION_CPU_IP3035    (OPTION_MD_BASE)
5765 +#define OPTION_CPU_UBICOM32DSP   (OPTION_MD_BASE+1)
5766 +#define OPTION_CPU_UBICOM32VER4  (OPTION_MD_BASE+2)
5767 +#define OPTION_CPU_UBICOM32VER3FDPIC  (OPTION_MD_BASE+3)
5768 +#define OPTION_CPU_UBICOM32VER4FDPIC  (OPTION_MD_BASE+4)
5769 +#define OPTION_CPU_UBICOM32_FDPIC  (OPTION_MD_BASE+5)
5770 +
5771 +struct option md_longopts[] =
5772 +{
5773 +  { "mubicom32v1",     no_argument, NULL, OPTION_CPU_IP3035 },
5774 +  { "mubicom32v2",     no_argument, NULL, OPTION_CPU_UBICOM32DSP },
5775 +  { "mubicom32v3",     no_argument, NULL, OPTION_CPU_UBICOM32DSP },
5776 +  { "mubicom32v4",     no_argument, NULL, OPTION_CPU_UBICOM32VER4 },
5777 +  { "mubicom32v3fdpic", no_argument, NULL, OPTION_CPU_UBICOM32VER3FDPIC },
5778 +  { "mubicom32v4fdpic",        no_argument, NULL, OPTION_CPU_UBICOM32VER4FDPIC },
5779 +  { "mfdpic",  no_argument, NULL, OPTION_CPU_UBICOM32_FDPIC },
5780 +  { NULL,      no_argument, NULL, 0 },
5781 +};
5782 +size_t md_longopts_size = sizeof (md_longopts);
5783 +
5784 +const char * md_shortopts = "";
5785 +
5786 +/* Mach selected from command line.  */
5787 +int ubicom32_mach = 0;
5788 +unsigned ubicom32_mach_bitmask = 0;
5789 +
5790 +int
5791 +md_parse_option (c, arg)
5792 +    int c ATTRIBUTE_UNUSED;
5793 +    char * arg ATTRIBUTE_UNUSED;
5794 +{
5795 +  int pic_state = ubicom32_mach & 0xffff0000;
5796 +  switch (c)
5797 +    {
5798 +    case OPTION_CPU_IP3035:
5799 +      ubicom32_mach = bfd_mach_ubicom32;
5800 +      ubicom32_mach_bitmask = 1 << MACH_IP3035;
5801 +      break;
5802 +
5803 +    case OPTION_CPU_UBICOM32DSP:
5804 +      ubicom32_mach = bfd_mach_ubicom32dsp;
5805 +      ubicom32_mach_bitmask = (1 << MACH_UBICOM32DSP)| (1 << MACH_IP3023COMPATIBILITY);
5806 +      break;
5807 +
5808 +    case OPTION_CPU_UBICOM32VER4:
5809 +      ubicom32_mach = bfd_mach_ubicom32ver4;
5810 +      ubicom32_mach_bitmask = (1 << MACH_UBICOM32DSP)| (1 << MACH_IP3023COMPATIBILITY) | (1 << MACH_UBICOM32_VER4);
5811 +      break;
5812 +
5813 +    case OPTION_CPU_UBICOM32VER3FDPIC:
5814 +      ubicom32_mach = bfd_mach_ubicom32dsp | EF_UBICOM32_FDPIC;
5815 +      ubicom32_mach_bitmask = (1 << MACH_UBICOM32DSP)| (1 << MACH_IP3023COMPATIBILITY);
5816 +      break;
5817 +
5818 +    case OPTION_CPU_UBICOM32VER4FDPIC:
5819 +      ubicom32_mach = bfd_mach_ubicom32ver4 | EF_UBICOM32_FDPIC;
5820 +      ubicom32_mach_bitmask = (1 << MACH_UBICOM32DSP)| (1 << MACH_IP3023COMPATIBILITY) | (1 << MACH_UBICOM32_VER4);
5821 +      break;
5822 +
5823 +    case OPTION_CPU_UBICOM32_FDPIC:
5824 +      ubicom32_mach |= EF_UBICOM32_FDPIC;
5825 +      break;
5826 +
5827 +    default:
5828 +      return 0;
5829 +    }
5830 +  ubicom32_mach |= pic_state;
5831 +
5832 +  return 1;
5833 +}
5834 +
5835 +
5836 +void
5837 +md_show_usage (stream)
5838 +    FILE * stream;
5839 +{
5840 +  fprintf (stream, _("UBICOM32 specific command line options:\n"));
5841 +  fprintf (stream, _("  -mubicom32v1               restrict to IP3023 insns \n"));
5842 +  fprintf (stream, _("  -mubicom32v3               permit DSP extended insn\n"));
5843 +  fprintf (stream, _("  -mubicom32v4               permit DSP extended insn and additional .1 instructions.\n"));
5844 +  fprintf (stream, _("  -mfdpic                    This in addition to the v3 or v4 flags will produce a FDPIC .o.\n"));
5845 +
5846 +}
5847 +
5848 +\f
5849 +void
5850 +md_begin ()
5851 +{
5852 +  /* Initialize the `cgen' interface.  */
5853 +  if(ubicom32_mach_bitmask == 0) {
5854 +         /* md_parse_option has not been called */
5855 +         ubicom32_mach_bitmask = 1<<MACH_IP3035;
5856 +         ubicom32_mach = bfd_mach_ubicom32;
5857 +  }
5858 +
5859 +  /* Record the specific machine in the elf header flags area */
5860 +  bfd_set_private_flags (stdoutput, ubicom32_mach);
5861 +
5862 +
5863 +  /* Set the machine number and endian.  */
5864 +  gas_cgen_cpu_desc = ubicom32_cgen_cpu_open (CGEN_CPU_OPEN_MACHS,
5865 +                                         ubicom32_mach_bitmask,
5866 +                                         CGEN_CPU_OPEN_ENDIAN,
5867 +                                         CGEN_ENDIAN_BIG,
5868 +                                         CGEN_CPU_OPEN_END);
5869 +  ubicom32_cgen_init_asm (gas_cgen_cpu_desc);
5870 +
5871 +#if 0
5872 +  /* Construct symbols for each of the registers */
5873 +
5874 +  for (i = 0; i < 32; ++i)
5875 +    {
5876 +      char name[4];
5877 +      sprintf(name, "d%d", i);
5878 +      ubicom32_register_table[i] = symbol_create(name, reg_section, i,
5879 +                                             &zero_address_frag);
5880 +    }
5881 +  for (; i < 40; ++i)
5882 +    {
5883 +      char name[4];
5884 +      sprintf(name, "a%d", i-32);
5885 +      ubicom32_register_table[i] = symbol_create(name, reg_section, i,
5886 +                                             &zero_address_frag);
5887 +    }
5888 +#endif
5889 +
5890 +  /* This is a callback from cgen to gas to parse operands.  */
5891 +  cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand);
5892 +
5893 +  /* Set the machine type */
5894 +  bfd_default_set_arch_mach (stdoutput, bfd_arch_ubicom32, ubicom32_mach & 0xffff);
5895 +
5896 +  /* Cuz our bit fields are shifted from their values */
5897 +  flag_signed_overflow_ok = 1;
5898 +}
5899 +
5900 +void
5901 +md_assemble (str)
5902 +     char * str;
5903 +{
5904 +  ubicom32_insn insn;
5905 +  char * errmsg;
5906 +
5907 +  /* Initialize GAS's cgen interface for a new instruction.  */
5908 +  gas_cgen_init_parse ();
5909 +  gas_cgen_cpu_desc->signed_overflow_ok_p=1;
5910 +
5911 +  /* need a way to detect when we have multiple increments to same An register */
5912 +  insn.fields.f_s1_i4_1 = 0;
5913 +  insn.fields.f_s1_i4_2 = 0;
5914 +  insn.fields.f_s1_i4_4 = 0;
5915 +  insn.fields.f_d_i4_1 = 0;
5916 +  insn.fields.f_d_i4_2 = 0;
5917 +  insn.fields.f_d_i4_4 = 0;
5918 +  insn.fields.f_s1_direct = 0;
5919 +  insn.fields.f_d_direct = 0;
5920 +
5921 +  memset(&insn.fields, 0, sizeof(insn.fields));
5922 +  insn.insn = ubicom32_cgen_assemble_insn
5923 +      (gas_cgen_cpu_desc, str, & insn.fields, insn.buffer, & errmsg);
5924 +
5925 +  if (!insn.insn)
5926 +    {
5927 +      as_bad ("%s", errmsg);
5928 +      return;
5929 +    }
5930 +
5931 +  if (insn.fields.f_s1_An == insn.fields.f_d_An)
5932 +    {
5933 +      if ((insn.fields.f_s1_i4_1 != 0 && insn.fields.f_d_i4_1 != 0) ||
5934 +         (insn.fields.f_s1_i4_2 != 0 && insn.fields.f_d_i4_2 != 0) ||
5935 +         (insn.fields.f_s1_i4_4 != 0 && insn.fields.f_d_i4_4 != 0))
5936 +       {
5937 +         /* user has tried to increment the same An register in both the s1
5938 +            and d operands which is illegal */
5939 +         static char errbuf[255];
5940 +         char *first_part;
5941 +         first_part = _("s1 and d operands update same An register");
5942 +         if (strlen (str) > 50)
5943 +           sprintf (errbuf, "%s `%.50s...'", first_part, str);
5944 +         else
5945 +           sprintf (errbuf, "%s `%.50s'", first_part, str);
5946 +
5947 +         as_bad ("%s", errbuf);
5948 +         return;
5949 +       }
5950 +    }
5951 +
5952 +  if(insn.fields.f_d_direct &&
5953 +     insn.fields.f_d_An == 0 &&
5954 +     insn.fields.f_d_imm7_4 == 0 &&
5955 +     insn.fields.f_d_imm7_2 == 0 &&
5956 +     insn.fields.f_d_imm7_1 == 0 &&
5957 +     insn.fields.f_d_i4_1 == 0 &&
5958 +     insn.fields.f_d_i4_2 == 0 &&
5959 +     insn.fields.f_d_i4_4 == 0)
5960 +    {
5961 +      if (insn.fields.f_d_direct >= A0_ADDRESS &&
5962 +         insn.fields.f_d_direct <= A7_ADDRESS)
5963 +       {
5964 +         long d_direct = (insn.fields.f_d_direct - A0_ADDRESS) >> 2;
5965 +         if (d_direct == insn.fields.f_s1_An &&
5966 +             (insn.fields.f_s1_i4_1 != 0 ||
5967 +              insn.fields.f_s1_i4_2 != 0 ||
5968 +              insn.fields.f_s1_i4_4 != 0))
5969 +           {
5970 +             /* user has tried to increment an An register that is also the destination register */
5971 +             static char errbuf[255];
5972 +             char *first_part;
5973 +             first_part = _("s1 and d operands update same An register");
5974 +             if (strlen (str) > 50)
5975 +               sprintf (errbuf, "%s `%.50s...'", first_part, str);
5976 +             else
5977 +               sprintf (errbuf, "%s `%.50s'", first_part, str);
5978 +
5979 +             as_bad ("%s", errbuf);
5980 +             return;
5981 +           }
5982 +       }
5983 +    }
5984 +
5985 +  /* Doesn't really matter what we pass for RELAX_P here.  */
5986 +  gas_cgen_finish_insn (insn.insn, insn.buffer,
5987 +                       CGEN_FIELDS_BITSIZE (& insn.fields), 1, NULL);
5988 +
5989 +}
5990 +
5991 +/* The syntax in the manual says constants begin with '#'.
5992 +   We just ignore it.  */
5993 +
5994 +void
5995 +md_operand (expressionP)
5996 +     expressionS * expressionP;
5997 +{
5998 +  /* In case of a syntax error, escape back to try next syntax combo. */
5999 +  if (expressionP->X_op == O_absent)
6000 +    gas_cgen_md_operand (expressionP);
6001 +}
6002 +
6003 +valueT
6004 +md_section_align (segment, size)
6005 +     segT   segment;
6006 +     valueT size;
6007 +{
6008 +  int align = bfd_get_section_alignment (stdoutput, segment);
6009 +  return ((size + (1 << align) - 1) & (-1 << align));
6010 +}
6011 +
6012 +
6013 +/* Be sure to use our register symbols. */
6014 +symbolS *
6015 +md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
6016 +{
6017 +#if 0
6018 +  char c;
6019 +  unsigned int u;
6020 +
6021 +  if (sscanf(name, "%c%u", &c, &u) == 2)
6022 +    {
6023 +      if (c == 'd' && u < 32)
6024 +       return ubicom32_register_table[u];
6025 +      if (c == 'a' && u < 8)
6026 +       return ubicom32_register_table[u + 32];
6027 +    }
6028 +#endif
6029 +  return (0);
6030 +}
6031 +\f
6032 +/* Interface to relax_segment.  */
6033 +
6034 +/* Return an initial guess of the length by which a fragment must grow to
6035 +   hold a branch to reach its destination.
6036 +   Also updates fr_type/fr_subtype as necessary.
6037 +
6038 +   Called just before doing relaxation.
6039 +   Any symbol that is now undefined will not become defined.
6040 +   The guess for fr_var is ACTUALLY the growth beyond fr_fix.
6041 +   Whatever we do to grow fr_fix or fr_var contributes to our returned value.
6042 +   Although it may not be explicit in the frag, pretend fr_var starts with a
6043 +   0 value.  */
6044 +
6045 +int
6046 +md_estimate_size_before_relax (fragP, segment)
6047 +     fragS * fragP;
6048 +     segT    segment ATTRIBUTE_UNUSED;
6049 +{
6050 +  int    old_fr_fix = fragP->fr_fix;
6051 +
6052 +  /* The only thing we have to handle here are symbols outside of the
6053 +     current segment.  They may be undefined or in a different segment in
6054 +     which case linker scripts may place them anywhere.
6055 +     However, we can't finish the fragment here and emit the reloc as insn
6056 +     alignment requirements may move the insn about.  */
6057 +
6058 +  return (fragP->fr_var + fragP->fr_fix - old_fr_fix);
6059 +}
6060 +
6061 +/* *fragP has been relaxed to its final size, and now needs to have
6062 +   the bytes inside it modified to conform to the new size.
6063 +
6064 +   Called after relaxation is finished.
6065 +   fragP->fr_type == rs_machine_dependent.
6066 +   fragP->fr_subtype is the subtype of what the address relaxed to.  */
6067 +
6068 +void
6069 +md_convert_frag (abfd, sec, fragP)
6070 +    bfd   * abfd  ATTRIBUTE_UNUSED;
6071 +    segT    sec   ATTRIBUTE_UNUSED;
6072 +    fragS * fragP ATTRIBUTE_UNUSED;
6073 +{
6074 +}
6075 +
6076 +\f
6077 +/* Functions concerning relocs.  */
6078 +
6079 +long
6080 +md_pcrel_from_section (fixS *fixP ATTRIBUTE_UNUSED, segT   sec ATTRIBUTE_UNUSED)
6081 +{
6082 +  /* Leave it for the linker to figure out so relaxation can work*/
6083 +  return 0;
6084 +}
6085 +
6086 +/* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
6087 +   Returns BFD_RELOC_NONE if no reloc type can be found.
6088 +   *FIXP may be modified if desired.  */
6089 +
6090 +bfd_reloc_code_real_type
6091 +md_cgen_lookup_reloc (insn, operand, fixP)
6092 +     const CGEN_INSN *    insn     ATTRIBUTE_UNUSED;
6093 +     const CGEN_OPERAND * operand;
6094 +     fixS *               fixP;
6095 +{
6096 +  switch (operand->type)
6097 +    {
6098 +    case UBICOM32_OPERAND_IMM16_2:
6099 +    case UBICOM32_OPERAND_IMM24:
6100 +    case UBICOM32_OPERAND_S1_IMM7_1:
6101 +    case UBICOM32_OPERAND_S1_IMM7_2:
6102 +    case UBICOM32_OPERAND_S1_IMM7_4:
6103 +    case UBICOM32_OPERAND_D_IMM7_1:
6104 +    case UBICOM32_OPERAND_D_IMM7_2:
6105 +    case UBICOM32_OPERAND_D_IMM7_4:
6106 +    case UBICOM32_OPERAND_OFFSET16:
6107 +     /* The relocation type should be recorded in opinfo */
6108 +      if (fixP->fx_cgen.opinfo != 0)
6109 +       return fixP->fx_cgen.opinfo;
6110 +
6111 +    case UBICOM32_OPERAND_OFFSET21:
6112 +      fixP->fx_pcrel = TRUE;
6113 +      return BFD_RELOC_UBICOM32_21_PCREL;
6114 +
6115 +    case UBICOM32_OPERAND_OFFSET24:
6116 +      fixP->fx_pcrel = TRUE;
6117 +      return BFD_RELOC_UBICOM32_24_PCREL;
6118 +
6119 +    default:
6120 +      /* Pacify gcc -Wall. */
6121 +      return BFD_RELOC_NONE;
6122 +    }
6123 +}
6124 +
6125 +/* See whether we need to force a relocation into the output file. */
6126 +
6127 +int
6128 +ubicom32_force_relocation (fix)
6129 +     fixS * fix;
6130 +{
6131 +  if (fix->fx_r_type == BFD_RELOC_UNUSED)
6132 +    return 0;
6133 +
6134 +  /* Force all relocations so linker relaxation can work.  */
6135 +  return 1;
6136 +}
6137 +
6138 +/* Write a value out to the object file, using the appropriate endianness.  */
6139 +
6140 +void
6141 +md_number_to_chars (buf, val, n)
6142 +     char * buf;
6143 +     valueT val;
6144 +     int    n;
6145 +{
6146 +  number_to_chars_bigendian (buf, val, n);
6147 +}
6148 +
6149 +/* Turn a string in input_line_pointer into a floating point constant of type
6150 +   type, and store the appropriate bytes in *litP.  The number of LITTLENUMS
6151 +   emitted is stored in *sizeP .  An error message is returned, or NULL on OK.
6152 +*/
6153 +
6154 +/* Equal to MAX_PRECISION in atof-ieee.c */
6155 +#define MAX_LITTLENUMS 6
6156 +
6157 +char *
6158 +md_atof (int  type,
6159 +        char * litP,
6160 +        int *  sizeP)
6161 +{
6162 +  int              prec;
6163 +  LITTLENUM_TYPE   words [MAX_LITTLENUMS];
6164 +  LITTLENUM_TYPE  *wordP;
6165 +  char *           t;
6166 +  //char *           atof_ieee (void);
6167 +
6168 +  switch (type)
6169 +    {
6170 +    case 'f':
6171 +    case 'F':
6172 +    case 's':
6173 +    case 'S':
6174 +      prec = 2;
6175 +      break;
6176 +
6177 +    case 'd':
6178 +    case 'D':
6179 +    case 'r':
6180 +    case 'R':
6181 +      prec = 4;
6182 +      break;
6183 +
6184 +   /* FIXME: Some targets allow other format chars for bigger sizes here.  */
6185 +
6186 +    default:
6187 +      * sizeP = 0;
6188 +      return _("Bad call to md_atof()");
6189 +    }
6190 +
6191 +  t = atof_ieee (input_line_pointer, type, words);
6192 +  if (t)
6193 +    input_line_pointer = t;
6194 +  * sizeP = prec * sizeof (LITTLENUM_TYPE);
6195 +
6196 +  /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
6197 +     the ubicom32 endianness.  */
6198 +  for (wordP = words; prec--;)
6199 +    {
6200 +      md_number_to_chars (litP, (valueT) (*wordP++), sizeof (LITTLENUM_TYPE));
6201 +      litP += sizeof (LITTLENUM_TYPE);
6202 +    }
6203 +
6204 +  return 0;
6205 +}
6206 +
6207 +bfd_boolean
6208 +ubicom32_fix_adjustable (fixP)
6209 +   fixS * fixP;
6210 +{
6211 +  bfd_reloc_code_real_type reloc_type;
6212 +
6213 +  if ((int) fixP->fx_r_type >= (int) BFD_RELOC_UNUSED)
6214 +    {
6215 +      const CGEN_INSN *insn = NULL;
6216 +      int opindex = (int) fixP->fx_r_type - (int) BFD_RELOC_UNUSED;
6217 +      const CGEN_OPERAND *operand = cgen_operand_lookup_by_num(gas_cgen_cpu_desc, opindex);
6218 +      reloc_type = md_cgen_lookup_reloc (insn, operand, fixP);
6219 +    }
6220 +  else
6221 +    reloc_type = fixP->fx_r_type;
6222 +
6223 +  if (fixP->fx_addsy == NULL)
6224 +    return 1;
6225 +
6226 +  if (!S_IS_LOCAL (fixP->fx_addsy))
6227 +    /* Let the linker resolve all symbols not within the local function
6228 +       so the linker can relax correctly.  */
6229 +    return 0;
6230 +
6231 +  if (S_IS_WEAK (fixP->fx_addsy))
6232 +    return 0;
6233 +
6234 +  /* We need the symbol name for the VTABLE entries */
6235 +  if (   reloc_type == BFD_RELOC_VTABLE_INHERIT
6236 +      || reloc_type == BFD_RELOC_VTABLE_ENTRY)
6237 +    return 0;
6238 +
6239 +  return 1;
6240 +}
6241 --- /dev/null
6242 +++ b/gas/config/tc-ubicom32.h
6243 @@ -0,0 +1,74 @@
6244 +/* tc-ubicom32.h -- Header file for tc-ubicom32.c.
6245 +   Copyright (C) 2000 Free Software Foundation, Inc.
6246 +
6247 +   This file is part of GAS, the GNU Assembler.
6248 +
6249 +   GAS is free software; you can redistribute it and/or modify
6250 +   it under the terms of the GNU General Public License as published by
6251 +   the Free Software Foundation; either version 2, or (at your option)
6252 +   any later version.
6253 +
6254 +   GAS is distributed in the hope that it will be useful,
6255 +   but WITHOUT ANY WARRANTY; without even the implied warranty of
6256 +   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
6257 +   GNU General Public License for more details.
6258 +
6259 +   You should have received a copy of the GNU General Public License
6260 +   along with GAS; see the file COPYING.  If not, write to
6261 +   the Free Software Foundation, 59 Temple Place - Suite 330,
6262 +   Boston, MA 02111-1307, USA. */
6263 +
6264 +#define TC_UBICOM32
6265 +
6266 +#if 0
6267 +#ifndef BFD_ASSEMBLER
6268 +/* leading space so will compile with cc */
6269 + #error UBICOM32 support requires BFD_ASSEMBLER
6270 +#endif
6271 +#endif
6272 +
6273 +#define LISTING_HEADER "IP3xxx GAS "
6274 +
6275 +/* The target BFD architecture.  */
6276 +#define TARGET_ARCH bfd_arch_ubicom32
6277 +
6278 +#define TARGET_FORMAT "elf32-ubicom32"
6279 +
6280 +#define TARGET_BYTES_BIG_ENDIAN 1
6281 +
6282 +/* Permit temporary numeric labels. */
6283 +#define LOCAL_LABELS_FB 1
6284 +
6285 +/* .-foo gets turned into PC relative relocs. */
6286 +#define DIFF_EXPR_OK
6287 +
6288 +/* UBICOM32 uses '(' and ')' as punctuation in addressing mode syntax. */
6289 +#define RELAX_PAREN_GROUPING
6290 +
6291 +/* We don't need to handle .word strangely. */
6292 +#define WORKING_DOT_WORD
6293 +
6294 +#define MD_APPLY_FIX3
6295 +#define md_apply_fix gas_cgen_md_apply_fix
6296 +
6297 +/* special characters for hex and bin literals */
6298 +#define LITERAL_PREFIXDOLLAR_HEX
6299 +#define LITERAL_PREFIXPERCENT_BIN
6300 +#define DOUBLESLASH_LINE_COMMENTS
6301 +
6302 +/* call md_pcrel_from_section, not md_pcrel_from */
6303 +long md_pcrel_from_section PARAMS ((struct fix *, segT));
6304 +#define MD_PCREL_FROM_SECTION(FIXP, SEC) md_pcrel_from_section (FIXP, SEC)
6305 +
6306 +#define obj_fix_adjustable(fixP) ubicom32_fix_adjustable (fixP)
6307 +extern bfd_boolean ubicom32_fix_adjustable PARAMS ((struct fix *));
6308 +
6309 +/* Permit temporary numeric labels.  */
6310 +#define LOCAL_LABELS_FB 1
6311 +
6312 +#define TC_HANDLES_FX_DONE
6313 +
6314 +#define tc_gen_reloc gas_cgen_tc_gen_reloc
6315 +
6316 +#define TC_FORCE_RELOCATION(fixp) ubicom32_force_relocation(fixp)
6317 +extern int ubicom32_force_relocation PARAMS ((struct fix *));
6318 --- a/gas/configure
6319 +++ b/gas/configure
6320 @@ -11188,7 +11188,7 @@ _ACEOF
6321          fi
6322          ;;
6323  
6324 -      fr30 | ip2k | iq2000 | m32r | openrisc)
6325 +      fr30 | ubicom32 | ip2k | iq2000 | m32r | openrisc)
6326         using_cgen=yes
6327         ;;
6328  
6329 --- a/gas/configure.in
6330 +++ b/gas/configure.in
6331 @@ -307,7 +307,7 @@ changequote([,])dnl
6332          fi
6333          ;;
6334  
6335 -      fr30 | ip2k | iq2000 | m32r | openrisc)
6336 +      fr30 | ubicom32 | ip2k | iq2000 | m32r | openrisc)
6337         using_cgen=yes
6338         ;;
6339  
6340 --- a/gas/configure.tgt
6341 +++ b/gas/configure.tgt
6342 @@ -81,6 +81,7 @@ case ${cpu} in
6343    strongarm*be)                cpu_type=arm endian=big ;;
6344    strongarm*b)         cpu_type=arm endian=big ;;
6345    strongarm*)          cpu_type=arm endian=little ;;
6346 +  ubicom32)            cpu_type=ubicom32 endian=big ;; 
6347    v850*)               cpu_type=v850 ;;
6348    x86_64*)             cpu_type=i386 arch=x86_64;;
6349    xscale*be|xscale*b)  cpu_type=arm endian=big ;;
6350 @@ -384,6 +385,8 @@ case ${generic_target} in
6351    tic4x-*-* | c4x-*-*)                 fmt=coff bfd_gas=yes ;;
6352    tic54x-*-* | c54x*-*-*)              fmt=coff bfd_gas=yes need_libm=yes;;
6353  
6354 +  ubicom32-*-*)                                fmt=elf ;;
6355 +
6356    v850-*-*)                            fmt=elf ;;
6357    v850e-*-*)                           fmt=elf ;;
6358    v850ea-*-*)                          fmt=elf ;;
6359 --- a/gas/Makefile.am
6360 +++ b/gas/Makefile.am
6361 @@ -92,6 +92,7 @@ CPU_TYPES = \
6362         tic30 \
6363         tic4x \
6364         tic54x \
6365 +       ubicom32 \
6366         v850 \
6367         vax \
6368         xc16x \
6369 @@ -287,6 +288,7 @@ TARGET_CPU_CFILES = \
6370         config/tc-tic30.c \
6371         config/tc-tic4x.c \
6372         config/tc-tic54x.c \
6373 +       config/tc-ubicom32.c \
6374         config/tc-vax.c \
6375         config/tc-v850.c \
6376         config/tc-xstormy16.c \
6377 @@ -1415,6 +1417,14 @@ DEPTC_tic54x_coff = $(srcdir)/config/obj
6378    $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
6379    sb.h macro.h subsegs.h $(INCDIR)/obstack.h struc-symbol.h \
6380    $(INCDIR)/opcode/tic54x.h
6381 +DEPTC_ubicom32_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
6382 +  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
6383 +  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ubicom32.h dwarf2dbg.h \
6384 +  subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/ubicom32-desc.h \
6385 +  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
6386 +  $(INCDIR)/opcode/cgen-bitset.h $(srcdir)/../opcodes/ubicom32-opc.h \
6387 +  cgen.h $(INCDIR)/elf/common.h $(INCDIR)/elf/ubicom32.h \
6388 +  $(INCDIR)/elf/reloc-macros.h $(BFDDIR)/libbfd.h $(INCDIR)/hashtab.h
6389  DEPTC_v850_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
6390    $(INCDIR)/elf/common.h $(INCDIR)/elf/external.h $(INCDIR)/elf/internal.h \
6391    $(INCDIR)/bfdlink.h $(srcdir)/config/tc-v850.h $(INCDIR)/elf/v850.h \
6392 @@ -1791,6 +1801,11 @@ DEPOBJ_tic54x_coff = $(srcdir)/config/ob
6393    $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic54x.h $(INCDIR)/coff/ti.h \
6394    $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
6395    subsegs.h
6396 +DEPOBJ_ubicomm32_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
6397 +  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
6398 +  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ubicom32.h dwarf2dbg.h \
6399 +  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
6400 +  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
6401  DEPOBJ_v850_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
6402    $(INCDIR)/elf/common.h $(INCDIR)/elf/external.h $(INCDIR)/elf/internal.h \
6403    $(INCDIR)/bfdlink.h $(srcdir)/config/tc-v850.h $(INCDIR)/elf/v850.h \
6404 @@ -2106,6 +2121,11 @@ DEP_tic4x_coff = $(srcdir)/config/obj-co
6405  DEP_tic54x_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-tic54x.h \
6406    $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic54x.h $(INCDIR)/coff/ti.h \
6407    $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
6408 +DEP_ubicom32_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
6409 +  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
6410 +  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ubicom32.h dwarf2dbg.h \
6411 +  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
6412 +  $(BFDDIR)/libcoff.h
6413  DEP_v850_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
6414    $(INCDIR)/elf/common.h $(INCDIR)/elf/external.h $(INCDIR)/elf/internal.h \
6415    $(INCDIR)/bfdlink.h $(srcdir)/config/tc-v850.h $(INCDIR)/elf/v850.h \
6416 --- a/gas/Makefile.in
6417 +++ b/gas/Makefile.in
6418 @@ -341,6 +341,7 @@ CPU_TYPES = \
6419         tic30 \
6420         tic4x \
6421         tic54x \
6422 +       ubicom32 \
6423         v850 \
6424         vax \
6425         xc16x \
6426 @@ -534,6 +535,7 @@ TARGET_CPU_CFILES = \
6427         config/tc-tic30.c \
6428         config/tc-tic4x.c \
6429         config/tc-tic54x.c \
6430 +       config/tc-ubicom32.c \
6431         config/tc-vax.c \
6432         config/tc-v850.c \
6433         config/tc-xstormy16.c \
6434 @@ -594,6 +596,7 @@ TARGET_CPU_HFILES = \
6435         config/tc-tic30.h \
6436         config/tc-tic4x.h \
6437         config/tc-tic54x.h \
6438 +       config/tc-ubicom32.h \
6439         config/tc-vax.h \
6440         config/tc-v850.h \
6441         config/tc-xstormy16.h \
6442 @@ -1244,6 +1247,13 @@ DEPTC_tic54x_coff = $(srcdir)/config/obj
6443    $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
6444    sb.h macro.h subsegs.h $(INCDIR)/obstack.h struc-symbol.h \
6445    $(INCDIR)/opcode/tic54x.h
6446 +DEPTC_ubicom32_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
6447 +  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
6448 +  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ubicom32.h dwarf2dbg.h \
6449 +  subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/ubicom32-desc.h \
6450 +  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
6451 +  $(srcdir)/../opcodes/ubicom32-opc.h cgen.h $(INCDIR)/elf/ubicom32.h \
6452 +  $(INCDIR)/elf/reloc-macros.h $(BFDDIR)/libbfd.h $(INCDIR)/hashtab.h
6453  
6454  DEPTC_v850_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
6455    $(INCDIR)/elf/common.h $(INCDIR)/elf/external.h $(INCDIR)/elf/internal.h \
6456 @@ -1700,6 +1710,11 @@ DEPOBJ_tic54x_coff = $(srcdir)/config/ob
6457    $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic54x.h $(INCDIR)/coff/ti.h \
6458    $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
6459    subsegs.h
6460 +DEPOBJ_ubicom32_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
6461 +  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
6462 +  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ubicom32.h dwarf2dbg.h \
6463 +  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
6464 +  struc-symbol.h $(INCDIR)/aout/aout64.h
6465  
6466  DEPOBJ_v850_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
6467    $(INCDIR)/elf/common.h $(INCDIR)/elf/external.h $(INCDIR)/elf/internal.h \
6468 @@ -2096,6 +2111,11 @@ DEP_tic54x_coff = $(srcdir)/config/obj-c
6469    $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic54x.h $(INCDIR)/coff/ti.h \
6470    $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
6471  
6472 +DEP_ubicom32_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
6473 +  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
6474 +  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ubicom32.h dwarf2dbg.h \
6475 +  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
6476 +  $(BFDDIR)/libcoff.h
6477  DEP_v850_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
6478    $(INCDIR)/elf/common.h $(INCDIR)/elf/external.h $(INCDIR)/elf/internal.h \
6479    $(INCDIR)/bfdlink.h $(srcdir)/config/tc-v850.h $(INCDIR)/elf/v850.h \
6480 --- a/include/dis-asm.h
6481 +++ b/include/dis-asm.h
6482 @@ -275,6 +275,7 @@ extern int print_insn_tic30         (bfd_vma, d
6483  extern int print_insn_tic4x            (bfd_vma, disassemble_info *);
6484  extern int print_insn_tic54x           (bfd_vma, disassemble_info *);
6485  extern int print_insn_tic80            (bfd_vma, disassemble_info *);
6486 +extern int print_insn_ubicom32         (bfd_vma, disassemble_info *);
6487  extern int print_insn_v850             (bfd_vma, disassemble_info *);
6488  extern int print_insn_vax              (bfd_vma, disassemble_info *);
6489  extern int print_insn_w65              (bfd_vma, disassemble_info *);
6490 --- /dev/null
6491 +++ b/include/dis-asm_ubicom32.h
6492 @@ -0,0 +1,339 @@
6493 +/* Interface between the opcode library and its callers.
6494 +
6495 +   Copyright 1999, 2000, 2001, 2002, 2003, 2004, 2005
6496 +   Free Software Foundation, Inc.
6497 +
6498 +   This program is free software; you can redistribute it and/or modify
6499 +   it under the terms of the GNU General Public License as published by
6500 +   the Free Software Foundation; either version 2, or (at your option)
6501 +   any later version.
6502 +
6503 +   This program is distributed in the hope that it will be useful,
6504 +   but WITHOUT ANY WARRANTY; without even the implied warranty of
6505 +   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
6506 +   GNU General Public License for more details.
6507 +
6508 +   You should have received a copy of the GNU General Public License
6509 +   along with this program; if not, write to the Free Software
6510 +   Foundation, Inc., 51 Franklin Street - Fifth Floor,
6511 +   Boston, MA 02110-1301, USA.
6512 +
6513 +   Written by Cygnus Support, 1993.
6514 +
6515 +   The opcode library (libopcodes.a) provides instruction decoders for
6516 +   a large variety of instruction sets, callable with an identical
6517 +   interface, for making instruction-processing programs more independent
6518 +   of the instruction set being processed.  */
6519 +
6520 +#ifndef DIS_ASM_H
6521 +#define DIS_ASM_H
6522 +
6523 +#ifdef __cplusplus
6524 +extern "C" {
6525 +#endif
6526 +
6527 +#include <stdio.h>
6528 +#include "bfd.h"
6529 +
6530 +typedef int (*fprintf_ftype) (void *, const char*, ...) ATTRIBUTE_FPTR_PRINTF_2;
6531 +
6532 +enum dis_insn_type {
6533 +  dis_noninsn,                 /* Not a valid instruction */
6534 +  dis_nonbranch,               /* Not a branch instruction */
6535 +  dis_branch,                  /* Unconditional branch */
6536 +  dis_condbranch,              /* Conditional branch */
6537 +  dis_jsr,                     /* Jump to subroutine */
6538 +  dis_condjsr,                 /* Conditional jump to subroutine */
6539 +  dis_dref,                    /* Data reference instruction */
6540 +  dis_dref2                    /* Two data references in instruction */
6541 +};
6542 +
6543 +/* This struct is passed into the instruction decoding routine,
6544 +   and is passed back out into each callback.  The various fields are used
6545 +   for conveying information from your main routine into your callbacks,
6546 +   for passing information into the instruction decoders (such as the
6547 +   addresses of the callback functions), or for passing information
6548 +   back from the instruction decoders to their callers.
6549 +
6550 +   It must be initialized before it is first passed; this can be done
6551 +   by hand, or using one of the initialization macros below.  */
6552 +
6553 +typedef struct disassemble_info {
6554 +  fprintf_ftype fprintf_func;
6555 +  void *stream;
6556 +  void *application_data;
6557 +
6558 +  /* Target description.  We could replace this with a pointer to the bfd,
6559 +     but that would require one.  There currently isn't any such requirement
6560 +     so to avoid introducing one we record these explicitly.  */
6561 +  /* The bfd_flavour.  This can be bfd_target_unknown_flavour.  */
6562 +  enum bfd_flavour flavour;
6563 +  /* The bfd_arch value.  */
6564 +  enum bfd_architecture arch;
6565 +  /* The bfd_mach value.  */
6566 +  unsigned long mach;
6567 +  /* Endianness (for bi-endian cpus).  Mono-endian cpus can ignore this.  */
6568 +  enum bfd_endian endian;
6569 +  /* An arch/mach-specific bitmask of selected instruction subsets, mainly
6570 +     for processors with run-time-switchable instruction sets.  The default,
6571 +     zero, means that there is no constraint.  CGEN-based opcodes ports
6572 +     may use ISA_foo masks.  */
6573 +  void *insn_sets;
6574 +
6575 +  /* Some targets need information about the current section to accurately
6576 +     display insns.  If this is NULL, the target disassembler function
6577 +     will have to make its best guess.  */
6578 +  asection *section;
6579 +
6580 +  /* An array of pointers to symbols either at the location being disassembled
6581 +     or at the start of the function being disassembled.  The array is sorted
6582 +     so that the first symbol is intended to be the one used.  The others are
6583 +     present for any misc. purposes.  This is not set reliably, but if it is
6584 +     not NULL, it is correct.  */
6585 +  asymbol **symbols;
6586 +  /* Number of symbols in array.  */
6587 +  int num_symbols;
6588 +
6589 +  /* For use by the disassembler.
6590 +     The top 16 bits are reserved for public use (and are documented here).
6591 +     The bottom 16 bits are for the internal use of the disassembler.  */
6592 +  unsigned long flags;
6593 +#define INSN_HAS_RELOC 0x80000000
6594 +  void *private_data;
6595 +
6596 +  /* Function used to get bytes to disassemble.  MEMADDR is the
6597 +     address of the stuff to be disassembled, MYADDR is the address to
6598 +     put the bytes in, and LENGTH is the number of bytes to read.
6599 +     INFO is a pointer to this struct.
6600 +     Returns an errno value or 0 for success.  */
6601 +  int (*read_memory_func)
6602 +    (bfd_vma memaddr, bfd_byte *myaddr, unsigned int length,
6603 +     struct disassemble_info *info);
6604 +
6605 +  /* Function which should be called if we get an error that we can't
6606 +     recover from.  STATUS is the errno value from read_memory_func and
6607 +     MEMADDR is the address that we were trying to read.  INFO is a
6608 +     pointer to this struct.  */
6609 +  void (*memory_error_func)
6610 +    (int status, bfd_vma memaddr, struct disassemble_info *info);
6611 +
6612 +  /* Function called to print ADDR.  */
6613 +  void (*print_address_func)
6614 +    (bfd_vma addr, struct disassemble_info *info);
6615 +
6616 +  /* Function called to determine if there is a symbol at the given ADDR.
6617 +     If there is, the function returns 1, otherwise it returns 0.
6618 +     This is used by ports which support an overlay manager where
6619 +     the overlay number is held in the top part of an address.  In
6620 +     some circumstances we want to include the overlay number in the
6621 +     address, (normally because there is a symbol associated with
6622 +     that address), but sometimes we want to mask out the overlay bits.  */
6623 +  int (* symbol_at_address_func)
6624 +    (bfd_vma addr, struct disassemble_info * info);
6625 +
6626 +  /* Function called to check if a SYMBOL is can be displayed to the user.
6627 +     This is used by some ports that want to hide special symbols when
6628 +     displaying debugging outout.  */
6629 +  bfd_boolean (* symbol_is_valid)
6630 +    (asymbol *, struct disassemble_info * info);
6631 +
6632 +  /* These are for buffer_read_memory.  */
6633 +  bfd_byte *buffer;
6634 +  bfd_vma buffer_vma;
6635 +  unsigned int buffer_length;
6636 +
6637 +  /* This variable may be set by the instruction decoder.  It suggests
6638 +      the number of bytes objdump should display on a single line.  If
6639 +      the instruction decoder sets this, it should always set it to
6640 +      the same value in order to get reasonable looking output.  */
6641 +  int bytes_per_line;
6642 +
6643 +  /* The next two variables control the way objdump displays the raw data.  */
6644 +  /* For example, if bytes_per_line is 8 and bytes_per_chunk is 4, the */
6645 +  /* output will look like this:
6646 +     00:   00000000 00000000
6647 +     with the chunks displayed according to "display_endian". */
6648 +  int bytes_per_chunk;
6649 +  enum bfd_endian display_endian;
6650 +
6651 +  /* Number of octets per incremented target address
6652 +     Normally one, but some DSPs have byte sizes of 16 or 32 bits.  */
6653 +  unsigned int octets_per_byte;
6654 +
6655 +  /* The number of zeroes we want to see at the end of a section before we
6656 +     start skipping them.  */
6657 +  unsigned int skip_zeroes;
6658 +
6659 +  /* The number of zeroes to skip at the end of a section.  If the number
6660 +     of zeroes at the end is between SKIP_ZEROES_AT_END and SKIP_ZEROES,
6661 +     they will be disassembled.  If there are fewer than
6662 +     SKIP_ZEROES_AT_END, they will be skipped.  This is a heuristic
6663 +     attempt to avoid disassembling zeroes inserted by section
6664 +     alignment.  */
6665 +  unsigned int skip_zeroes_at_end;
6666 +
6667 +  /* Whether the disassembler always needs the relocations.  */
6668 +  bfd_boolean disassembler_needs_relocs;
6669 +
6670 +  /* Results from instruction decoders.  Not all decoders yet support
6671 +     this information.  This info is set each time an instruction is
6672 +     decoded, and is only valid for the last such instruction.
6673 +
6674 +     To determine whether this decoder supports this information, set
6675 +     insn_info_valid to 0, decode an instruction, then check it.  */
6676 +
6677 +  char insn_info_valid;                /* Branch info has been set. */
6678 +  char branch_delay_insns;     /* How many sequential insn's will run before
6679 +                                  a branch takes effect.  (0 = normal) */
6680 +  char data_size;              /* Size of data reference in insn, in bytes */
6681 +  enum dis_insn_type insn_type;        /* Type of instruction */
6682 +  bfd_vma target;              /* Target address of branch or dref, if known;
6683 +                                  zero if unknown.  */
6684 +  bfd_vma target2;             /* Second target address for dref2 */
6685 +
6686 +  /* Command line options specific to the target disassembler.  */
6687 +  char * disassembler_options;
6688 +
6689 +} disassemble_info;
6690 +
6691 +\f
6692 +/* Standard disassemblers.  Disassemble one instruction at the given
6693 +   target address.  Return number of octets processed.  */
6694 +typedef int (*disassembler_ftype) (bfd_vma, disassemble_info *);
6695 +
6696 +extern int print_insn_big_mips         (bfd_vma, disassemble_info *);
6697 +extern int print_insn_little_mips      (bfd_vma, disassemble_info *);
6698 +extern int print_insn_i386             (bfd_vma, disassemble_info *);
6699 +extern int print_insn_i386_att         (bfd_vma, disassemble_info *);
6700 +extern int print_insn_i386_intel       (bfd_vma, disassemble_info *);
6701 +extern int print_insn_ia64             (bfd_vma, disassemble_info *);
6702 +extern int print_insn_i370             (bfd_vma, disassemble_info *);
6703 +extern int print_insn_m68hc11          (bfd_vma, disassemble_info *);
6704 +extern int print_insn_m68hc12          (bfd_vma, disassemble_info *);
6705 +extern int print_insn_m68k             (bfd_vma, disassemble_info *);
6706 +extern int print_insn_z80              (bfd_vma, disassemble_info *);
6707 +extern int print_insn_z8001            (bfd_vma, disassemble_info *);
6708 +extern int print_insn_z8002            (bfd_vma, disassemble_info *);
6709 +extern int print_insn_h8300            (bfd_vma, disassemble_info *);
6710 +extern int print_insn_h8300h           (bfd_vma, disassemble_info *);
6711 +extern int print_insn_h8300s           (bfd_vma, disassemble_info *);
6712 +extern int print_insn_h8500            (bfd_vma, disassemble_info *);
6713 +extern int print_insn_alpha            (bfd_vma, disassemble_info *);
6714 +extern int print_insn_big_arm          (bfd_vma, disassemble_info *);
6715 +extern int print_insn_little_arm       (bfd_vma, disassemble_info *);
6716 +extern int print_insn_sparc            (bfd_vma, disassemble_info *);
6717 +extern int print_insn_avr              (bfd_vma, disassemble_info *);
6718 +extern int print_insn_bfin             (bfd_vma, disassemble_info *);
6719 +extern int print_insn_d10v             (bfd_vma, disassemble_info *);
6720 +extern int print_insn_d30v             (bfd_vma, disassemble_info *);
6721 +extern int print_insn_dlx              (bfd_vma, disassemble_info *);
6722 +extern int print_insn_fr30             (bfd_vma, disassemble_info *);
6723 +extern int print_insn_hppa             (bfd_vma, disassemble_info *);
6724 +extern int print_insn_i860             (bfd_vma, disassemble_info *);
6725 +extern int print_insn_i960             (bfd_vma, disassemble_info *);
6726 +extern int print_insn_m32r             (bfd_vma, disassemble_info *);
6727 +extern int print_insn_m88k             (bfd_vma, disassemble_info *);
6728 +extern int print_insn_maxq_little      (bfd_vma, disassemble_info *);
6729 +extern int print_insn_maxq_big         (bfd_vma, disassemble_info *);
6730 +extern int print_insn_mcore            (bfd_vma, disassemble_info *);
6731 +extern int print_insn_mmix             (bfd_vma, disassemble_info *);
6732 +extern int print_insn_mn10200          (bfd_vma, disassemble_info *);
6733 +extern int print_insn_mn10300          (bfd_vma, disassemble_info *);
6734 +extern int print_insn_mt                (bfd_vma, disassemble_info *);
6735 +extern int print_insn_msp430           (bfd_vma, disassemble_info *);
6736 +extern int print_insn_ns32k            (bfd_vma, disassemble_info *);
6737 +extern int print_insn_crx               (bfd_vma, disassemble_info *);
6738 +extern int print_insn_openrisc         (bfd_vma, disassemble_info *);
6739 +extern int print_insn_big_or32         (bfd_vma, disassemble_info *);
6740 +extern int print_insn_little_or32      (bfd_vma, disassemble_info *);
6741 +extern int print_insn_pdp11            (bfd_vma, disassemble_info *);
6742 +extern int print_insn_pj               (bfd_vma, disassemble_info *);
6743 +extern int print_insn_big_powerpc      (bfd_vma, disassemble_info *);
6744 +extern int print_insn_little_powerpc   (bfd_vma, disassemble_info *);
6745 +extern int print_insn_rs6000           (bfd_vma, disassemble_info *);
6746 +extern int print_insn_s390             (bfd_vma, disassemble_info *);
6747 +extern int print_insn_sh               (bfd_vma, disassemble_info *);
6748 +extern int print_insn_tic30            (bfd_vma, disassemble_info *);
6749 +extern int print_insn_tic4x            (bfd_vma, disassemble_info *);
6750 +extern int print_insn_tic54x           (bfd_vma, disassemble_info *);
6751 +extern int print_insn_tic80            (bfd_vma, disassemble_info *);
6752 +extern int print_insn_ubicom32         (bfd_vma, disassemble_info *);
6753 +extern int print_insn_v850             (bfd_vma, disassemble_info *);
6754 +extern int print_insn_vax              (bfd_vma, disassemble_info *);
6755 +extern int print_insn_w65              (bfd_vma, disassemble_info *);
6756 +extern int print_insn_xstormy16                (bfd_vma, disassemble_info *);
6757 +extern int print_insn_xtensa           (bfd_vma, disassemble_info *);
6758 +extern int print_insn_sh64             (bfd_vma, disassemble_info *);
6759 +extern int print_insn_sh64x_media      (bfd_vma, disassemble_info *);
6760 +extern int print_insn_frv              (bfd_vma, disassemble_info *);
6761 +extern int print_insn_iq2000           (bfd_vma, disassemble_info *);
6762 +extern int print_insn_xc16x            (bfd_vma, disassemble_info *);
6763 +extern int print_insn_m32c     (bfd_vma, disassemble_info *);
6764 +
6765 +extern disassembler_ftype arc_get_disassembler (void *);
6766 +extern disassembler_ftype cris_get_disassembler (bfd *);
6767 +
6768 +extern void print_mips_disassembler_options (FILE *);
6769 +extern void print_ppc_disassembler_options (FILE *);
6770 +extern void print_arm_disassembler_options (FILE *);
6771 +extern void parse_arm_disassembler_option (char *);
6772 +extern int get_arm_regname_num_options (void);
6773 +extern int set_arm_regname_option (int);
6774 +extern int get_arm_regnames (int, const char **, const char **, const char *const **);
6775 +extern bfd_boolean arm_symbol_is_valid (asymbol *, struct disassemble_info *);
6776 +
6777 +/* Fetch the disassembler for a given BFD, if that support is available.  */
6778 +extern disassembler_ftype disassembler (bfd *);
6779 +
6780 +/* Amend the disassemble_info structure as necessary for the target architecture.
6781 +   Should only be called after initialising the info->arch field.  */
6782 +extern void disassemble_init_for_target (struct disassemble_info * info);
6783 +
6784 +/* Document any target specific options available from the disassembler.  */
6785 +extern void disassembler_usage (FILE *);
6786 +
6787 +\f
6788 +/* This block of definitions is for particular callers who read instructions
6789 +   into a buffer before calling the instruction decoder.  */
6790 +
6791 +/* Here is a function which callers may wish to use for read_memory_func.
6792 +   It gets bytes from a buffer.  */
6793 +extern int buffer_read_memory
6794 +  (bfd_vma, bfd_byte *, unsigned int, struct disassemble_info *);
6795 +
6796 +/* This function goes with buffer_read_memory.
6797 +   It prints a message using info->fprintf_func and info->stream.  */
6798 +extern void perror_memory (int, bfd_vma, struct disassemble_info *);
6799 +
6800 +
6801 +/* Just print the address in hex.  This is included for completeness even
6802 +   though both GDB and objdump provide their own (to print symbolic
6803 +   addresses).  */
6804 +extern void generic_print_address
6805 +  (bfd_vma, struct disassemble_info *);
6806 +
6807 +/* Always true.  */
6808 +extern int generic_symbol_at_address
6809 +  (bfd_vma, struct disassemble_info *);
6810 +
6811 +/* Also always true.  */
6812 +extern bfd_boolean generic_symbol_is_valid
6813 +  (asymbol *, struct disassemble_info *);
6814 +
6815 +/* Method to initialize a disassemble_info struct.  This should be
6816 +   called by all applications creating such a struct.  */
6817 +extern void init_disassemble_info (struct disassemble_info *info, void *stream,
6818 +                                  fprintf_ftype fprintf_func);
6819 +
6820 +/* For compatibility with existing code.  */
6821 +#define INIT_DISASSEMBLE_INFO(INFO, STREAM, FPRINTF_FUNC) \
6822 +  init_disassemble_info (&(INFO), (STREAM), (fprintf_ftype) (FPRINTF_FUNC))
6823 +#define INIT_DISASSEMBLE_INFO_NO_ARCH(INFO, STREAM, FPRINTF_FUNC) \
6824 +  init_disassemble_info (&(INFO), (STREAM), (fprintf_ftype) (FPRINTF_FUNC))
6825 +
6826 +
6827 +#ifdef __cplusplus
6828 +}
6829 +#endif
6830 +
6831 +#endif /* ! defined (DIS_ASM_H) */
6832 --- a/include/elf/common.h
6833 +++ b/include/elf/common.h
6834 @@ -318,6 +318,9 @@
6835  
6836  #define EM_XSTORMY16           0xad45
6837  
6838 +#define EM_UBICOM32            0xde3d  /* Ubicom32; no ABI */
6839 +#define EM_UBICOM32MATH        0xde3e  /* Ubicom32 co-processor; no ABI */
6840 +
6841  /* mn10200 and mn10300 backend magic numbers.
6842     Written in the absense of an ABI.  */
6843  #define EM_CYGNUS_MN10300      0xbeef
6844 --- /dev/null
6845 +++ b/include/elf/ubicom32.h
6846 @@ -0,0 +1,79 @@
6847 +/* ubicom32 ELF support for BFD.
6848 +   Copyright (C) 2000 Free Software Foundation, Inc.
6849 +
6850 +This file is part of BFD, the Binary File Descriptor library.
6851 +
6852 +This program is free software; you can redistribute it and/or modify
6853 +it under the terms of the GNU General Public License as published by
6854 +the Free Software Foundation; either version 2 of the License, or
6855 +(at your option) any later version.
6856 +
6857 +This program is distributed in the hope that it will be useful,
6858 +but WITHOUT ANY WARRANTY; without even the implied warranty of
6859 +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
6860 +GNU General Public License for more details.
6861 +
6862 +You should have received a copy of the GNU General Public License
6863 +along with this program; if not, write to the Free Software Foundation, Inc.,
6864 +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
6865 +
6866 +#ifndef _ELF_UBICOM32_H
6867 +#define _ELF_UBICOM32_H
6868 +
6869 +#include "elf/reloc-macros.h"
6870 +
6871 +/* Relocations.  */
6872 +START_RELOC_NUMBERS (elf_ubicom32_reloc_type)
6873 +  RELOC_NUMBER (R_UBICOM32_NONE, 0)
6874 +  RELOC_NUMBER (R_UBICOM32_16, 1)
6875 +  RELOC_NUMBER (R_UBICOM32_32, 2)
6876 +  RELOC_NUMBER (R_UBICOM32_LO16, 3)
6877 +  RELOC_NUMBER (R_UBICOM32_HI16, 4)
6878 +  RELOC_NUMBER (R_UBICOM32_21_PCREL, 5)
6879 +  RELOC_NUMBER (R_UBICOM32_24_PCREL, 6)
6880 +  RELOC_NUMBER (R_UBICOM32_HI24, 7)
6881 +  RELOC_NUMBER (R_UBICOM32_LO7_S, 8)
6882 +  RELOC_NUMBER (R_UBICOM32_LO7_2_S, 9)
6883 +  RELOC_NUMBER (R_UBICOM32_LO7_4_S, 10)
6884 +  RELOC_NUMBER (R_UBICOM32_LO7_D, 11)
6885 +  RELOC_NUMBER (R_UBICOM32_LO7_2_D, 12)
6886 +  RELOC_NUMBER (R_UBICOM32_LO7_4_D, 13)
6887 +  RELOC_NUMBER (R_UBICOM32_32_HARVARD, 14)
6888 +  RELOC_NUMBER (R_UBICOM32_LO7_CALLI, 15)
6889 +  RELOC_NUMBER (R_UBICOM32_LO16_CALLI, 16)
6890 +  RELOC_NUMBER (R_UBICOM32_GOT_HI24, 17)
6891 +  RELOC_NUMBER (R_UBICOM32_GOT_LO7_S, 18)
6892 +  RELOC_NUMBER (R_UBICOM32_GOT_LO7_2_S, 19)
6893 +  RELOC_NUMBER (R_UBICOM32_GOT_LO7_4_S, 20)
6894 +  RELOC_NUMBER (R_UBICOM32_GOT_LO7_D, 21)
6895 +  RELOC_NUMBER (R_UBICOM32_GOT_LO7_2_D, 22)
6896 +  RELOC_NUMBER (R_UBICOM32_GOT_LO7_4_D, 23)
6897 +  RELOC_NUMBER (R_UBICOM32_FUNCDESC_GOT_HI24, 24)
6898 +  RELOC_NUMBER (R_UBICOM32_FUNCDESC_GOT_LO7_S, 25)
6899 +  RELOC_NUMBER (R_UBICOM32_FUNCDESC_GOT_LO7_2_S, 26)
6900 +  RELOC_NUMBER (R_UBICOM32_FUNCDESC_GOT_LO7_4_S, 27)
6901 +  RELOC_NUMBER (R_UBICOM32_FUNCDESC_GOT_LO7_D, 28)
6902 +  RELOC_NUMBER (R_UBICOM32_FUNCDESC_GOT_LO7_2_D, 29)
6903 +  RELOC_NUMBER (R_UBICOM32_FUNCDESC_GOT_LO7_4_D, 30)
6904 +  RELOC_NUMBER (R_UBICOM32_GOT_LO7_CALLI, 31)
6905 +  RELOC_NUMBER (R_UBICOM32_FUNCDESC_GOT_LO7_CALLI, 32)
6906 +  RELOC_NUMBER (R_UBICOM32_FUNCDESC_VALUE, 33)
6907 +  RELOC_NUMBER (R_UBICOM32_FUNCDESC, 34)
6908 +  RELOC_NUMBER (R_UBICOM32_GOTOFFSET_LO, 35)
6909 +  RELOC_NUMBER (R_UBICOM32_GOTOFFSET_HI, 36)
6910 +  RELOC_NUMBER (R_UBICOM32_FUNCDESC_GOTOFFSET_LO, 37)
6911 +  RELOC_NUMBER (R_UBICOM32_FUNCDESC_GOTOFFSET_HI, 38)
6912 +  RELOC_NUMBER (R_UBICOM32_GNU_VTINHERIT, 200)
6913 +  RELOC_NUMBER (R_UBICOM32_GNU_VTENTRY, 201)
6914 +END_RELOC_NUMBERS(R_UBICOM32_max)
6915 +
6916 +
6917 +/*
6918 + * Processor specific flags for the ELF header e_flags field.
6919 + */
6920 +#define EF_UBICOM32_PIC         0x80000000      /* -fpic */
6921 +#define EF_UBICOM32_FDPIC       0x40000000      /* -mfdpic */
6922 +
6923 +#define EF_UBICOM32_PIC_FLAGS   (EF_UBICOM32_PIC | EF_UBICOM32_FDPIC)
6924 +
6925 +#endif /* _ELF_IP_H */
6926 --- a/ld/configure.tgt
6927 +++ b/ld/configure.tgt
6928 @@ -607,6 +607,15 @@ tic4x-*-* | c4x-*-*)    targ_emul=tic4xc
6929  tic54x-*-* | c54x*-*-*)        targ_emul=tic54xcoff ;;
6930  tic80-*-*)             targ_emul=tic80coff
6931                         ;;
6932 +ubicom32-*-linux-*)    targ_emul=elf32ubicom32
6933 +                       targ_extra_emuls=elf32ubicom32fdpic
6934 +                       targ_extra_libpath=$targ_extra_emuls
6935 +                       ;;
6936 +ubicom32-*-*)          targ_emul=elf32ubicom32
6937 +                       targ_extra_emuls=elf32ubicom32fdpic
6938 +                       targ_extra_libpath=$targ_extra_emuls
6939 +                       ;;
6940 +
6941  v850-*-*)              targ_emul=v850 ;;
6942  v850e-*-*)             targ_emul=v850 ;;
6943  v850ea-*-*)            targ_emul=v850
6944 --- /dev/null
6945 +++ b/ld/emulparams/elf32ubicom32fdpic.sh
6946 @@ -0,0 +1,28 @@
6947 +MACHINE=
6948 +SCRIPT_NAME=elf
6949 +OUTPUT_FORMAT="elf32-ubicom32fdpic"
6950 +TEXT_START_ADDR=0x000000
6951 +MAXPAGESIZE=0x1000
6952 +TARGET_PAGE_SIZE=0x1000
6953 +NONPAGED_TEXT_START_ADDR=${TEXT_START_ADDR}
6954 +ARCH=ubicom32
6955 +TEMPLATE_NAME=elf32
6956 +ENTRY=_start
6957 +EMBEDDED=yes
6958 +GENERATE_SHLIB_SCRIPT=yes
6959 +EMBEDDED= # This gets us program headers mapped as part of the text segment.
6960 +OTHER_GOT_SYMBOLS=
6961 +OTHER_READONLY_SECTIONS="
6962 +  .rofixup        : {
6963 +    ${RELOCATING+__ROFIXUP_LIST__ = .;}
6964 +    *(.rofixup)
6965 +    ${RELOCATING+__ROFIXUP_END__ = .;}
6966 +  }
6967 +"
6968 +ELFSIZE=32
6969 +WRITABLE_RODATA=""
6970 +DATA_START_SYMBOLS=
6971 +CTOR_START='___ctors = .;'
6972 +CTOR_END='___ctors_end = .;'
6973 +DTOR_START='___dtors = .;'
6974 +DTOR_END='___dtors_end = .;'
6975 --- /dev/null
6976 +++ b/ld/emulparams/elf32ubicom32.sh
6977 @@ -0,0 +1,23 @@
6978 +MACHINE=
6979 +SCRIPT_NAME=elf
6980 +OUTPUT_FORMAT="elf32-ubicom32"
6981 +DATA_ADDR=0x100000
6982 +EXT_DATA_START_ADDR=0x100000
6983 +EXT_DATA_SIZE=0x10000
6984 +TEXT_START_ADDR=0x40000000
6985 +EXT_PROGRAM_START_ADDR=0x40000000
6986 +EXT_PROGRAM_SIZE=0x80000
6987 +FLASHRAM_START_ADDR=0x20000000
6988 +COPROCESSOR_MEMORY=0x400000
6989 +COPROCESSOR_MEM_SIZE=0x100000
6990 +ARCH=ubicom32
6991 +TEMPLATE_NAME=elf32
6992 +ENTRY=_start
6993 +EMBEDDED=yes
6994 +ELFSIZE=32
6995 +MAXPAGESIZE=256
6996 +DATA_START_SYMBOLS=
6997 +CTOR_START='___ctors = .;'
6998 +CTOR_END='___ctors_end = .;'
6999 +DTOR_START='___dtors = .;'
7000 +DTOR_END='___dtors_end = .;'
7001 --- a/ld/Makefile.am
7002 +++ b/ld/Makefile.am
7003 @@ -198,6 +198,8 @@ ALL_EMULATIONS = \
7004         eelf32ppcsim.o \
7005         eelf32ppcwindiss.o \
7006         eelf32ppcvxworks.o \
7007 +       eelf32ubicom32.o \
7008 +       eelf32ubicom32fdpic.o \
7009         eelf32vax.o \
7010          eelf32xc16x.o \
7011          eelf32xc16xl.o \
7012 @@ -927,6 +929,14 @@ eelf64lppc.c: $(srcdir)/emulparams/elf64
7013  eelf32i370.c: $(srcdir)/emulparams/elf32i370.sh \
7014    $(ELF_DEPS) $(srcdir)/scripttempl/elfi370.sc ${GEN_DEPENDS}
7015         ${GENSCRIPTS} elf32i370 "$(tdir_elf32i370)"
7016 +eelf32ubicom32.c: $(srcdir)/emulparams/elf32ubicom32.sh \
7017 +  $(ELF_DEPS) \
7018 +  $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
7019 +       ${GENSCRIPTS} elf32ubicom32 "$(tdir_ubicom32)"
7020 +eelf32ubicom32fdpic.c: $(srcdir)/emulparams/elf32ubicom32fdpic.sh \
7021 +  $(ELF_DEPS) \
7022 +  $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
7023 +       ${GENSCRIPTS} elf32ubicom32fdpic "$(tdir_ubicom32fdpic)"
7024  eelf32ip2k.c: $(srcdir)/emulparams/elf32ip2k.sh \
7025    $(ELF_DEPS) $(srcdir)/scripttempl/ip2k.sc ${GEN_DEPENDS}
7026         ${GENSCRIPTS} elf32ip2k "$(tdir_ip2k)"
7027 --- a/ld/Makefile.in
7028 +++ b/ld/Makefile.in
7029 @@ -449,6 +449,8 @@ ALL_EMULATIONS = \
7030         eelf32ppcsim.o \
7031         eelf32ppcwindiss.o \
7032         eelf32ppcvxworks.o \
7033 +       eelf32ubicom32.o \
7034 +       eelf32ubicom32fdpic.o \
7035         eelf32vax.o \
7036          eelf32xc16x.o \
7037          eelf32xc16xl.o \
7038 @@ -1759,6 +1761,14 @@ eelf64lppc.c: $(srcdir)/emulparams/elf64
7039  eelf32i370.c: $(srcdir)/emulparams/elf32i370.sh \
7040    $(ELF_DEPS) $(srcdir)/scripttempl/elfi370.sc ${GEN_DEPENDS}
7041         ${GENSCRIPTS} elf32i370 "$(tdir_elf32i370)"
7042 +eelf32ubicom32.c: $(srcdir)/emulparams/elf32ubicom32.sh \
7043 +  $(ELF_DEPS) \
7044 +  $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
7045 +       ${GENSCRIPTS} elf32ubicom32 "$(tdir_ubicom32)"
7046 +eelf32ubicom32fdpic.c: $(srcdir)/emulparams/elf32ubicom32fdpic.sh \
7047 +  $(ELF_DEPS) \
7048 +  $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
7049 +       ${GENSCRIPTS} elf32ubicom32fdpic "$(tdir_ubicom32fdpic)"
7050  eelf32ip2k.c: $(srcdir)/emulparams/elf32ip2k.sh \
7051    $(ELF_DEPS) $(srcdir)/scripttempl/ip2k.sc ${GEN_DEPENDS}
7052         ${GENSCRIPTS} elf32ip2k "$(tdir_ip2k)"
7053 --- /dev/null
7054 +++ b/ld/scripttempl/ubicom32.sc
7055 @@ -0,0 +1,395 @@
7056 +#
7057 +# Unusual variables checked by this code:
7058 +#       EXT_DATA_START_ADDR - virtual address start of extended data storage
7059 +#       EXT_DATA_SIZE - size of extended data storage
7060 +#       EXT_PROGRAM_START_ADDR - virtual address start of extended prog storage
7061 +#       EXT_PROGRAM_SIZE - size of extended program storage
7062 +#       FLASHRAM1_START_ADDR - virtual address start of flash ram 1 storage
7063 +#       FLASHRAM2_START_ADDR - virtual address start of flash ram 2 storage
7064 +#       FLASHRAM3_START_ADDR - virtual address start of flash ram 3 storage
7065 +#       FLASHRAM4_START_ADDR - virtual address start of flash ram 4 storage
7066 +#       FLASHRAM5_START_ADDR - virtual address start of flash ram 5 storage
7067 +#       FLASHRAM6_START_ADDR - virtual address start of flash ram 6 storage
7068 +#       FLASHRAM7_START_ADDR - virtual address start of flash ram 7 storage
7069 +#       FLASHRAM8_START_ADDR - virtual address start of flash ram 8 storage
7070 +#       PROGRAM_SRAM_START_ADDR - virtual address start of program sram storage
7071 +#      NOP - two byte opcode for no-op (defaults to 0)
7072 +#      DATA_ADDR - if end-of-text-plus-one-page isn't right for data start
7073 +#      INITIAL_READONLY_SECTIONS - at start of text segment
7074 +#      OTHER_READONLY_SECTIONS - other than .text .init .rodata ...
7075 +#              (e.g., .PARISC.milli)
7076 +#      OTHER_TEXT_SECTIONS - these get put in .text when relocating
7077 +#      OTHER_READWRITE_SECTIONS - other than .data .bss .ctors .sdata ...
7078 +#              (e.g., .PARISC.global)
7079 +#      OTHER_BSS_SECTIONS - other than .bss .sbss ...
7080 +#      OTHER_SECTIONS - at the end
7081 +#      EXECUTABLE_SYMBOLS - symbols that must be defined for an
7082 +#              executable (e.g., _DYNAMIC_LINK)
7083 +#      TEXT_START_SYMBOLS - symbols that appear at the start of the
7084 +#              .text section.
7085 +#      DATA_START_SYMBOLS - symbols that appear at the start of the
7086 +#              .data section.
7087 +#      OTHER_GOT_SYMBOLS - symbols defined just before .got.
7088 +#      OTHER_GOT_SECTIONS - sections just after .got and .sdata.
7089 +#      OTHER_BSS_SYMBOLS - symbols that appear at the start of the
7090 +#              .bss section besides __bss_start.
7091 +#      DATA_PLT - .plt should be in data segment, not text segment.
7092 +#      BSS_PLT - .plt should be in bss segment
7093 +#      TEXT_DYNAMIC - .dynamic in text segment, not data segment.
7094 +#      EMBEDDED - whether this is for an embedded system. 
7095 +#      SHLIB_TEXT_START_ADDR - if set, add to SIZEOF_HEADERS to set
7096 +#              start address of shared library.
7097 +#      INPUT_FILES - INPUT command of files to always include
7098 +#      WRITABLE_RODATA - if set, the .rodata section should be writable
7099 +#      INIT_START, INIT_END -  statements just before and just after
7100 +#      combination of .init sections.
7101 +#      FINI_START, FINI_END - statements just before and just after
7102 +#      combination of .fini sections.
7103 +#
7104 +# When adding sections, do note that the names of some sections are used
7105 +# when specifying the start address of the next.
7106 +#
7107 +
7108 +test -z "$ENTRY" && ENTRY=_start
7109 +test -z "${BIG_OUTPUT_FORMAT}" && BIG_OUTPUT_FORMAT=${OUTPUT_FORMAT}
7110 +test -z "${LITTLE_OUTPUT_FORMAT}" && LITTLE_OUTPUT_FORMAT=${OUTPUT_FORMAT}
7111 +if [ -z "$MACHINE" ]; then OUTPUT_ARCH=${ARCH}; else OUTPUT_ARCH=${ARCH}:${MACHINE}; fi
7112 +test -z "${ELFSIZE}" && ELFSIZE=32
7113 +test -z "${ALIGNMENT}" && ALIGNMENT="${ELFSIZE} / 8"
7114 +test "$LD_FLAG" = "N" && DATA_ADDR=.
7115 +INTERP=".interp   ${RELOCATING-0} : { *(.interp)       } ${RELOCATING+ > datamem}"
7116 +PLT=".plt    ${RELOCATING-0} : { *(.plt)       } ${RELOCATING+ > datamem}"
7117 +DYNAMIC=".dynamic     ${RELOCATING-0} : { *(.dynamic) } ${RELOCATING+ > datamem}"
7118 +RODATA=".rodata ${RELOCATING-0} : { *(.rodata) ${RELOCATING+*(.rodata.*)} ${RELOCATING+*(.gnu.linkonce.r*)} } ${RELOCATING+ > datamem}"
7119 +SBSS2=".sbss2 ${RELOCATING-0} : { *(.sbss2) } ${RELOCATING+ > datamem}"
7120 +SDATA2=".sdata2 ${RELOCATING-0} : { *(.sdata2) } ${RELOCATING+ >datamem}"
7121 +CTOR=".ctors ${CONSTRUCTING-0} : 
7122 +  {
7123 +    ${RELOCATING+. = ALIGN(${ALIGNMENT});}
7124 +    ${CONSTRUCTING+${CTOR_START}}
7125 +    LONG (-1)
7126 +    /* gcc uses crtbegin.o to find the start of
7127 +       the constructors, so we make sure it is
7128 +       first.  Because this is a wildcard, it
7129 +       doesn't matter if the user does not
7130 +       actually link against crtbegin.o; the
7131 +       linker won't look for a file to match a
7132 +       wildcard.  The wildcard also means that it
7133 +       doesn't matter which directory crtbegin.o
7134 +       is in.  */
7135 +
7136 +    KEEP (*crtbegin.o(.ctors))
7137 +
7138 +    /* We don't want to include the .ctor section from
7139 +       from the crtend.o file until after the sorted ctors.
7140 +       The .ctor section from the crtend file contains the
7141 +       end of ctors marker and it must be last */
7142 +
7143 +    KEEP (*(EXCLUDE_FILE (*crtend.o $OTHER_EXCLUDE_FILES) .ctors))
7144 +    KEEP (*(SORT(.ctors.*)))
7145 +    KEEP (*(.ctors))
7146 +    LONG (0)
7147 +    ${CONSTRUCTING+${CTOR_END}}
7148 +  } ${RELOCATING+ > datamem}"
7149 +
7150 +DTOR=" .dtors       ${CONSTRUCTING-0} :
7151 +  {
7152 +    ${RELOCATING+. = ALIGN(${ALIGNMENT});}
7153 +    ${CONSTRUCTING+${DTOR_START}}
7154 +    LONG (-1)
7155 +    KEEP (*crtbegin.o(.dtors))
7156 +    KEEP (*(EXCLUDE_FILE (*crtend.o $OTHER_EXCLUDE_FILES) .dtors))
7157 +    KEEP (*(SORT(.dtors.*)))
7158 +    KEEP (*(.dtors))
7159 +    LONG (0)
7160 +    ${CONSTRUCTING+${DTOR_END}}
7161 +  } ${RELOCATING+ > datamem}"
7162 +
7163 +# if this is for an embedded system, don't add SIZEOF_HEADERS.
7164 +if [ -z "$EMBEDDED" ]; then
7165 +   test -z "${TEXT_BASE_ADDRESS}" && TEXT_BASE_ADDRESS="${TEXT_START_ADDR} + SIZEOF_HEADERS"
7166 +else
7167 +   test -z "${TEXT_BASE_ADDRESS}" && TEXT_BASE_ADDRESS="${TEXT_START_ADDR}"
7168 +fi
7169 +
7170 +cat <<EOF
7171 +OUTPUT_FORMAT("${OUTPUT_FORMAT}", "${BIG_OUTPUT_FORMAT}",
7172 +             "${LITTLE_OUTPUT_FORMAT}")
7173 +OUTPUT_ARCH(${OUTPUT_ARCH})
7174 +ENTRY(${ENTRY})
7175 +
7176 +${RELOCATING+${LIB_SEARCH_DIRS}}
7177 +${RELOCATING+/* Do we need any of these for elf?
7178 +   __DYNAMIC = 0; ${STACKZERO+${STACKZERO}} ${SHLIB_PATH+${SHLIB_PATH}}  */}
7179 +${RELOCATING+${EXECUTABLE_SYMBOLS}}
7180 +${RELOCATING+${INPUT_FILES}}
7181 +${RELOCATING- /* For some reason, the Solaris linker makes bad executables
7182 +  if gld -r is used and the intermediate file has sections starting
7183 +  at non-zero addresses.  Could be a Solaris ld bug, could be a GNU ld
7184 +  bug.  But for now assigning the zero vmas works.  */}
7185 +
7186 +MEMORY
7187 +{
7188 +  datamem (w) : ORIGIN = ${EXT_DATA_START_ADDR}, LENGTH = ${EXT_DATA_SIZE}
7189 +  progmem (wx): ORIGIN = ${EXT_PROGRAM_START_ADDR}, LENGTH = ${EXT_PROGRAM_SIZE}
7190 +  flashram (wx) : ORIGIN = ${FLASHRAM_START_ADDR}, LENGTH = 0x400000
7191 +  copromem (w) : ORIGIN = ${COPROCESSOR_MEMORY}, LENGTH = ${COPROCESSOR_MEM_SIZE}
7192 +}
7193 +
7194 +SECTIONS
7195 +{
7196 +  .flram ${RELOCATING-0} : { *(.start) *(.flram) } ${RELOCATING+ > flashram}
7197 +  .copro ${RELOCATING-0} : {*(.copro) } ${RELOCATING+ > copromem}
7198 +
7199 +  ${CREATE_SHLIB-${RELOCATING+. = ${TEXT_BASE_ADDRESS};}}
7200 +  ${CREATE_SHLIB+${RELOCATING+. = ${SHLIB_TEXT_START_ADDR:-0} + SIZEOF_HEADERS;}}
7201 +  .text    ${RELOCATING-0} :
7202 +  {
7203 +    ${RELOCATING+${TEXT_START_SYMBOLS}}
7204 +    *(.text)
7205 +    ${RELOCATING+*(.text.*)}
7206 +    *(.stub)
7207 +    /* .gnu.warning sections are handled specially by elf32.em.  */
7208 +    *(.gnu.warning)
7209 +    ${RELOCATING+*(.gnu.linkonce.t*)}
7210 +    ${RELOCATING+${OTHER_TEXT_SECTIONS}}
7211 +  } ${RELOCATING+ > progmem} =${NOP-0}
7212 +
7213 +  .rel.text    ${RELOCATING-0} :
7214 +    {
7215 +      *(.rel.text)
7216 +      ${RELOCATING+*(.rel.text.*)}
7217 +      ${RELOCATING+*(.rel.gnu.linkonce.t*)}
7218 +    } ${RELOCATING+ > progmem}
7219 +
7220 +  .rela.text   ${RELOCATING-0} :
7221 +    {
7222 +      *(.rela.text)
7223 +      ${RELOCATING+*(.rela.text.*)}
7224 +      ${RELOCATING+*(.rela.gnu.linkonce.t*)}
7225 +    } ${RELOCATING+ > progmem}
7226 +
7227 +  ${RELOCATING+PROVIDE (__etext = .);}
7228 +  ${RELOCATING+PROVIDE (_etext = .);}
7229 +  ${RELOCATING+PROVIDE (etext = .);}
7230 +
7231 +  /* Adjust the address for the data segment.  We want to adjust up to
7232 +     the same address within the page on the next page up.  */
7233 +  ${CREATE_SHLIB-${RELOCATING+. = ${DATA_ADDR-ALIGN(${MAXPAGESIZE}) + (. & (${MAXPAGESIZE} - 1))};}}
7234 +  ${CREATE_SHLIB+${RELOCATING+. = ${SHLIB_DATA_ADDR-ALIGN(${MAXPAGESIZE}) + (. & (${MAXPAGESIZE} - 1))};}}
7235 +
7236 +  /* Skip first word to ensure first data element can't end up having address
7237 +     0 in code (NULL pointer) */
7238 +  . = . + 4;
7239 +  .data  ${RELOCATING-0} :
7240 +  {
7241 +    ${RELOCATING+${DATA_START_SYMBOLS}}
7242 +    *(.data)
7243 +    ${RELOCATING+*(.data.*)}
7244 +    ${RELOCATING+*(.gnu.linkonce.d*)}
7245 +    ${CONSTRUCTING+SORT(CONSTRUCTORS)}
7246 +  } ${RELOCATING+ > datamem}
7247 +  .data1 ${RELOCATING-0} : { *(.data1) } ${RELOCATING+ > datamem}
7248 +  .eh_frame ${RELOCATING-0} : 
7249 +  { 
7250 +    ${RELOCATING+PROVIDE (___eh_frame_begin = .);}
7251 +    *(.eh_frame) 
7252 +    LONG (0);
7253 +    ${RELOCATING+PROVIDE (___eh_frame_end = .);}
7254 +  } ${RELOCATING+ > datamem}
7255 +  .gcc_except_table : { *(.gcc_except_table) } ${RELOCATING+ > datamem}
7256 +  
7257 +  /* Read-only sections, placed in data space: */
7258 +  ${CREATE_SHLIB-${INTERP}}
7259 +  ${INITIAL_READONLY_SECTIONS}
7260 +  ${TEXT_DYNAMIC+${DYNAMIC}}
7261 +  .hash        ${RELOCATING-0} : { *(.hash)            } ${RELOCATING+ > datamem}
7262 +  .dynsym      ${RELOCATING-0} : { *(.dynsym)          } ${RELOCATING+ > datamem}
7263 +  .dynstr      ${RELOCATING-0} : { *(.dynstr)          } ${RELOCATING+ > datamem}
7264 +  .gnu.version ${RELOCATING-0} : { *(.gnu.version)     } ${RELOCATING+ > datamem}
7265 +  .gnu.version_d ${RELOCATING-0} : { *(.gnu.version_d) } ${RELOCATING+ > datamem}
7266 +  .gnu.version_r ${RELOCATING-0} : { *(.gnu.version_r) } ${RELOCATING+ > datamem}
7267 +
7268 +  .rel.init    ${RELOCATING-0} : { *(.rel.init)        } ${RELOCATING+ > datamem}
7269 +  .rela.init   ${RELOCATING-0} : { *(.rela.init)       } ${RELOCATING+ > datamem}
7270 +  .rel.fini    ${RELOCATING-0} : { *(.rel.fini)        } ${RELOCATING+ > datamem}
7271 +  .rela.fini   ${RELOCATING-0} : { *(.rela.fini)       } ${RELOCATING+ > datamem}
7272 +  .rel.rodata  ${RELOCATING-0} :
7273 +    {
7274 +      *(.rel.rodata)
7275 +      ${RELOCATING+*(.rel.rodata.*)}
7276 +      ${RELOCATING+*(.rel.gnu.linkonce.r*)}
7277 +    } ${RELOCATING+ > datamem}
7278 +  .rela.rodata ${RELOCATING-0} :
7279 +    {
7280 +      *(.rela.rodata)
7281 +      ${RELOCATING+*(.rela.rodata.*)}
7282 +      ${RELOCATING+*(.rela.gnu.linkonce.r*)}
7283 +    } ${RELOCATING+ > datamem}
7284 +  ${OTHER_READONLY_RELOC_SECTIONS}
7285 +  .rel.data    ${RELOCATING-0} :
7286 +    {
7287 +      *(.rel.data)
7288 +      ${RELOCATING+*(.rel.data.*)}
7289 +      ${RELOCATING+*(.rel.gnu.linkonce.d*)}
7290 +    } ${RELOCATING+ > datamem}
7291 +  .rela.data   ${RELOCATING-0} :
7292 +    {
7293 +      *(.rela.data)
7294 +      ${RELOCATING+*(.rela.data.*)}
7295 +      ${RELOCATING+*(.rela.gnu.linkonce.d*)}
7296 +    } ${RELOCATING+ > datamem}
7297 +  .rel.ctors   ${RELOCATING-0} : { *(.rel.ctors)       } ${RELOCATING+ > datamem}
7298 +  .rela.ctors  ${RELOCATING-0} : { *(.rela.ctors)      } ${RELOCATING+ > datamem}
7299 +  .rel.dtors   ${RELOCATING-0} : { *(.rel.dtors)       } ${RELOCATING+ > datamem}
7300 +  .rela.dtors  ${RELOCATING-0} : { *(.rela.dtors)      } ${RELOCATING+ > datamem}
7301 +  .rel.got     ${RELOCATING-0} : { *(.rel.got)         } ${RELOCATING+ > datamem}
7302 +  .rela.got    ${RELOCATING-0} : { *(.rela.got)                } ${RELOCATING+ > datamem}
7303 +  ${OTHER_GOT_RELOC_SECTIONS}
7304 +  .rel.sdata   ${RELOCATING-0} :
7305 +    {
7306 +      *(.rel.sdata)
7307 +      ${RELOCATING+*(.rel.sdata.*)}
7308 +      ${RELOCATING+*(.rel.gnu.linkonce.s*)}
7309 +    } ${RELOCATING+ > datamem}
7310 +  .rela.sdata   ${RELOCATING-0} :
7311 +    {
7312 +      *(.rela.sdata)
7313 +      ${RELOCATING+*(.rela.sdata.*)}
7314 +      ${RELOCATING+*(.rela.gnu.linkonce.s*)}
7315 +    } ${RELOCATING+ > datamem}
7316 +  .rel.sbss    ${RELOCATING-0} : { *(.rel.sbss)                } ${RELOCATING+ > datamem}
7317 +  .rela.sbss   ${RELOCATING-0} : { *(.rela.sbss)       } ${RELOCATING+ > datamem}
7318 +  .rel.sdata2  ${RELOCATING-0} : { *(.rel.sdata2)      } ${RELOCATING+ > datamem}
7319 +  .rela.sdata2 ${RELOCATING-0} : { *(.rela.sdata2)     } ${RELOCATING+ > datamem}
7320 +  .rel.sbss2   ${RELOCATING-0} : { *(.rel.sbss2)       } ${RELOCATING+ > datamem}
7321 +  .rela.sbss2  ${RELOCATING-0} : { *(.rela.sbss2)      } ${RELOCATING+ > datamem}
7322 +  .rel.bss     ${RELOCATING-0} : { *(.rel.bss)         } ${RELOCATING+ > datamem}
7323 +  .rela.bss    ${RELOCATING-0} : { *(.rela.bss)                } ${RELOCATING+ > datamem}
7324 +  .rel.plt     ${RELOCATING-0} : { *(.rel.plt)         } ${RELOCATING+ > datamem}
7325 +  .rela.plt    ${RELOCATING-0} : { *(.rela.plt)                } ${RELOCATING+ > datamem}
7326 +  ${OTHER_PLT_RELOC_SECTIONS}
7327 +
7328 +  .init        ${RELOCATING-0} : 
7329 +  { 
7330 +    ${RELOCATING+${INIT_START}}
7331 +    KEEP (*(.init))
7332 +    ${RELOCATING+${INIT_END}}
7333 +  } ${RELOCATING+ > datamem} =${NOP-0}
7334 +
7335 +  ${DATA_PLT-${BSS_PLT-${PLT}}}
7336 +
7337 +  .fini    ${RELOCATING-0} :
7338 +  {
7339 +    ${RELOCATING+${FINI_START}}
7340 +    KEEP (*(.fini))
7341 +    ${RELOCATING+${FINI_END}}
7342 +  } ${RELOCATING+ > datamem} =${NOP-0}
7343 +
7344 +  ${WRITABLE_RODATA-${RODATA}}
7345 +  .rodata1 ${RELOCATING-0} : { *(.rodata1) } ${RELOCATING+ > datamem}
7346 +  ${CREATE_SHLIB-${SDATA2}}
7347 +  ${CREATE_SHLIB-${SBSS2}}
7348 +  ${RELOCATING+${OTHER_READONLY_SECTIONS}}
7349 +  ${WRITABLE_RODATA+${RODATA}}
7350 +  ${RELOCATING+${OTHER_READWRITE_SECTIONS}}
7351 +  ${RELOCATING+. = ALIGN(${ALIGNMENT});}
7352 +  ${RELOCATING+${CTOR}}
7353 +  ${RELOCATING+${DTOR}}
7354 +  ${DATA_PLT+${PLT}}
7355 +  ${RELOCATING+${OTHER_GOT_SYMBOLS}}
7356 +  .got         ${RELOCATING-0} : { *(.got.plt) *(.got) } ${RELOCATING+ > datamem}
7357 +  ${CREATE_SHLIB+${SDATA2}}
7358 +  ${CREATE_SHLIB+${SBSS2}}
7359 +  ${TEXT_DYNAMIC-${DYNAMIC}}
7360 +  /* We want the small data sections together, so single-instruction offsets
7361 +     can access them all, and initialized data all before uninitialized, so
7362 +     we can shorten the on-disk segment size.  */
7363 +  .sdata   ${RELOCATING-0} : 
7364 +  {
7365 +    ${RELOCATING+${SDATA_START_SYMBOLS}}
7366 +    *(.sdata) 
7367 +    ${RELOCATING+*(.sdata.*)}
7368 +    ${RELOCATING+*(.gnu.linkonce.s.*)}
7369 +  } ${RELOCATING+ > datamem}
7370 +  ${RELOCATING+${OTHER_GOT_SECTIONS}}
7371 +  ${RELOCATING+_edata = .;}
7372 +  ${RELOCATING+PROVIDE (edata = .);}
7373 +  ${RELOCATING+__bss_start = .;}
7374 +  ${RELOCATING+${OTHER_BSS_SYMBOLS}}
7375 +  .sbss    ${RELOCATING-0} :
7376 +  {
7377 +    ${RELOCATING+PROVIDE (__sbss_start = .);}
7378 +    ${RELOCATING+PROVIDE (___sbss_start = .);}
7379 +    *(.dynsbss)
7380 +    *(.sbss)
7381 +    ${RELOCATING+*(.sbss.*)}
7382 +    *(.scommon)
7383 +    ${RELOCATING+PROVIDE (__sbss_end = .);}
7384 +    ${RELOCATING+PROVIDE (___sbss_end = .);}
7385 +  } ${RELOCATING+ > datamem}
7386 +  ${BSS_PLT+${PLT}}
7387 +  .bss     ${RELOCATING-0} :
7388 +  {
7389 +   *(.dynbss)
7390 +   *(.bss)
7391 +   ${RELOCATING+*(.bss.*)}
7392 +   *(COMMON)
7393 +   /* Align here to ensure that the .bss section occupies space up to
7394 +      _end.  Align after .bss to ensure correct alignment even if the
7395 +      .bss section disappears because there are no input sections.  */
7396 +   ${RELOCATING+. = ALIGN(${ALIGNMENT});}
7397 +  } ${RELOCATING+ > datamem}
7398 +  ${RELOCATING+${OTHER_BSS_SECTIONS}}
7399 +  ${RELOCATING+. = ALIGN(${ALIGNMENT});}
7400 +  ${RELOCATING+_end = .;}
7401 +  ${RELOCATING+${OTHER_BSS_END_SYMBOLS}}
7402 +  ${RELOCATING+PROVIDE (end = .);}
7403 +
7404 +  /* Stabs debugging sections.  */
7405 +  .stab 0 : { *(.stab) }
7406 +  .stabstr 0 : { *(.stabstr) }
7407 +  .stab.excl 0 : { *(.stab.excl) }
7408 +  .stab.exclstr 0 : { *(.stab.exclstr) }
7409 +  .stab.index 0 : { *(.stab.index) }
7410 +  .stab.indexstr 0 : { *(.stab.indexstr) }
7411 +
7412 +  .comment 0 : { *(.comment) }
7413 +
7414 +  /* DWARF debug sections.
7415 +     Symbols in the DWARF debugging sections are relative to the beginning
7416 +     of the section so we begin them at 0.  */
7417 +
7418 +  /* DWARF 1 */
7419 +  .debug          0 : { *(.debug) }
7420 +  .line           0 : { *(.line) }
7421 +
7422 +  /* GNU DWARF 1 extensions */
7423 +  .debug_srcinfo  0 : { *(.debug_srcinfo) }
7424 +  .debug_sfnames  0 : { *(.debug_sfnames) }
7425 +
7426 +  /* DWARF 1.1 and DWARF 2 */
7427 +  .debug_aranges  0 : { *(.debug_aranges) }
7428 +  .debug_pubnames 0 : { *(.debug_pubnames) }
7429 +
7430 +  /* DWARF 2 */
7431 +  .debug_info     0 : { *(.debug_info) }
7432 +  .debug_abbrev   0 : { *(.debug_abbrev) }
7433 +  .debug_line     0 : { *(.debug_line) }
7434 +  .debug_frame    0 : { *(.debug_frame) }
7435 +  .debug_str      0 : { *(.debug_str) }
7436 +  .debug_loc      0 : { *(.debug_loc) }
7437 +  .debug_macinfo  0 : { *(.debug_macinfo) }
7438 +
7439 +  /* SGI/MIPS DWARF 2 extensions */
7440 +  .debug_weaknames 0 : { *(.debug_weaknames) }
7441 +  .debug_funcnames 0 : { *(.debug_funcnames) }
7442 +  .debug_typenames 0 : { *(.debug_typenames) }
7443 +  .debug_varnames  0 : { *(.debug_varnames) }
7444 +
7445 +  ${RELOCATING+${OTHER_RELOCATING_SECTIONS}}
7446 +
7447 +  /* These must appear regardless of ${RELOCATING}.  */
7448 +  ${OTHER_SECTIONS}
7449 +}
7450 +EOF
7451 --- a/opcodes/configure
7452 +++ b/opcodes/configure
7453 @@ -11885,6 +11885,7 @@ if test x${all_targets} = xfalse ; then
7454          bfd_tic4x_arch)         ta="$ta tic4x-dis.lo" ;;
7455         bfd_tic54x_arch)        ta="$ta tic54x-dis.lo tic54x-opc.lo" ;;
7456         bfd_tic80_arch)         ta="$ta tic80-dis.lo tic80-opc.lo" ;;
7457 +       bfd_ubicom32_arch)              ta="$ta ubicom32-asm.lo ubicom32-desc.lo ubicom32-dis.lo ubicom32-ibld.lo ubicom32-opc.lo" using_cgen=yes ;;
7458         bfd_v850_arch)          ta="$ta v850-opc.lo v850-dis.lo" ;;
7459         bfd_v850e_arch)         ta="$ta v850-opc.lo v850-dis.lo" ;;
7460         bfd_v850ea_arch)        ta="$ta v850-opc.lo v850-dis.lo" ;;
7461 --- a/opcodes/configure.in
7462 +++ b/opcodes/configure.in
7463 @@ -245,6 +245,7 @@ if test x${all_targets} = xfalse ; then
7464          bfd_tic4x_arch)         ta="$ta tic4x-dis.lo" ;;
7465         bfd_tic54x_arch)        ta="$ta tic54x-dis.lo tic54x-opc.lo" ;;
7466         bfd_tic80_arch)         ta="$ta tic80-dis.lo tic80-opc.lo" ;;
7467 +       bfd_ubicom32_arch)              ta="$ta ubicom32-asm.lo ubicom32-desc.lo ubicom32-dis.lo ubicom32-ibld.lo ubicom32-opc.lo" using_cgen=yes ;;
7468         bfd_v850_arch)          ta="$ta v850-opc.lo v850-dis.lo" ;;
7469         bfd_v850e_arch)         ta="$ta v850-opc.lo v850-dis.lo" ;;
7470         bfd_v850ea_arch)        ta="$ta v850-opc.lo v850-dis.lo" ;;
7471 --- a/opcodes/disassemble.c
7472 +++ b/opcodes/disassemble.c
7473 @@ -77,6 +77,7 @@
7474  #define ARCH_tic4x
7475  #define ARCH_tic54x
7476  #define ARCH_tic80
7477 +#define ARCH_ubicom32
7478  #define ARCH_v850
7479  #define ARCH_vax
7480  #define ARCH_w65
7481 @@ -386,6 +387,11 @@ disassembler (abfd)
7482        disassemble = print_insn_tic80;
7483        break;
7484  #endif
7485 +#ifdef ARCH_ubicom32
7486 +    case bfd_arch_ubicom32:
7487 +      disassemble = print_insn_ubicom32;
7488 +      break;
7489 +#endif
7490  #ifdef ARCH_v850
7491      case bfd_arch_v850:
7492        disassemble = print_insn_v850;
7493 --- a/opcodes/Makefile.am
7494 +++ b/opcodes/Makefile.am
7495 @@ -50,6 +50,7 @@ HFILES = \
7496         sh-opc.h \
7497         sh64-opc.h \
7498         sysdep.h \
7499 +       ubicom32-desc.h ubicom32-opc.h \
7500         w65-opc.h \
7501         xc16x-desc.h xc16x-opc.h \
7502         xstormy16-desc.h xstormy16-opc.h \
7503 @@ -191,6 +192,11 @@ CFILES = \
7504         tic54x-opc.c \
7505         tic80-dis.c \
7506         tic80-opc.c \
7507 +       ubicom32-asm.c \
7508 +       ubicom32-desc.c \
7509 +       ubicom32-dis.c \
7510 +       ubicom32-ibld.c \
7511 +       ubicom32-opc.c \
7512         v850-dis.c \
7513         v850-opc.c \
7514         vax-dis.c \
7515 @@ -333,6 +339,11 @@ ALL_MACHINES = \
7516         tic54x-opc.lo \
7517         tic80-dis.lo \
7518         tic80-opc.lo \
7519 +       ubicom32-asm.lo \
7520 +       ubicom32-desc.lo \
7521 +       ubicom32-dis.lo \
7522 +       ubicom32-ibld.lo \
7523 +       ubicom32-opc.lo \
7524         v850-dis.lo \
7525         v850-opc.lo \
7526         vax-dis.lo \
7527 @@ -421,7 +432,7 @@ uninstall_libopcodes:
7528         rm -f $(DESTDIR)$(bfdincludedir)/dis-asm.h
7529  
7530  CLEANFILES = \
7531 -       stamp-ip2k stamp-m32c stamp-m32r stamp-fr30 stamp-frv \
7532 +       stamp-ubicom32 stamp-ip2k stamp-m32c stamp-m32r stamp-fr30 stamp-frv \
7533         stamp-openrisc stamp-iq2000 stamp-mep stamp-mt stamp-xstormy16 stamp-xc16x\
7534         libopcodes.a stamp-lib dep.sed DEP DEPA DEP1 DEP2
7535  
7536 @@ -438,10 +449,11 @@ CGENDEPS = \
7537         $(CGENDIR)/opc-opinst.scm \
7538         cgen-asm.in cgen-dis.in cgen-ibld.in
7539  
7540 -CGEN_CPUS = fr30 frv ip2k m32c m32r mep mt openrisc xc16x xstormy16
7541 +CGEN_CPUS = fr30 frv ip2k ubicom32 m32c m32r mep mt openrisc xc16x xstormy16
7542  
7543  if CGEN_MAINT
7544  IP2K_DEPS = stamp-ip2k
7545 +UBICOM32_DEPS = stamp-ubicom32
7546  M32C_DEPS = stamp-m32c
7547  M32R_DEPS = stamp-m32r
7548  FR30_DEPS = stamp-fr30
7549 @@ -454,6 +466,7 @@ XC16X_DEPS = stamp-xc16x
7550  XSTORMY16_DEPS = stamp-xstormy16
7551  else
7552  IP2K_DEPS =
7553 +UBICOM32_DEPS =
7554  M32C_DEPS =
7555  M32R_DEPS =
7556  FR30_DEPS =
7557 @@ -482,6 +495,10 @@ run-cgen-all:
7558  .PHONY: run-cgen-all
7559  
7560  # For now, require developers to configure with --enable-cgen-maint.
7561 +$(srcdir)/ubicom32-desc.h $(srcdir)/ubicom32-desc.c $(srcdir)/ubicom32-opc.h $(srcdir)/ubicom32-opc.c $(srcdir)/ubicom32-ibld.c $(srcdir)/ubicom32-asm.c $(srcdir)/ubicom32-dis.c: $(UBICOM32_DEPS)
7562 +#      @true
7563 +stamp-ubicom32: $(CGENDEPS) $(CPUDIR)/ubicom32.cpu $(CPUDIR)/ubicom32.opc
7564 +       $(MAKE) run-cgen arch=ubicom32 prefix=ubicom32 options= extrafiles=
7565  $(srcdir)/ip2k-desc.h $(srcdir)/ip2k-desc.c $(srcdir)/ip2k-opc.h $(srcdir)/ip2k-opc.c $(srcdir)/ip2k-ibld.c $(srcdir)/ip2k-asm.c $(srcdir)/ip2k-dis.c: $(IP2K_DEPS)
7566         @true
7567  stamp-ip2k: $(CGENDEPS) $(CPUDIR)/ip2k.cpu $(CPUDIR)/ip2k.opc
7568 @@ -823,6 +840,34 @@ ia64-gen.lo: ia64-gen.c $(INCDIR)/anside
7569    ia64-opc-m.c ia64-opc-b.c ia64-opc-f.c ia64-opc-x.c \
7570    ia64-opc-d.c
7571  ia64-asmtab.lo: ia64-asmtab.c
7572 +ubicom32-asm.lo: ubicom32-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \
7573 +  $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
7574 +  ubicom32-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
7575 +  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h ubicom32-opc.h \
7576 +  opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h \
7577 +  $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h
7578 +ubicom32-desc.lo: ubicom32-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
7579 +  $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
7580 +  ubicom32-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
7581 +  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h ubicom32-opc.h \
7582 +  opintl.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
7583 +  $(INCDIR)/xregex.h $(INCDIR)/xregex2.h
7584 +ubicom32-dis.lo: ubicom32-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
7585 +  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
7586 +  $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
7587 +  ubicom32-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
7588 +  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h ubicom32-opc.h \
7589 +  opintl.h
7590 +ubicom32-ibld.lo: ubicom32-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \
7591 +  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
7592 +  $(BFD_H) $(INCDIR)/symcat.h ubicom32-desc.h $(INCDIR)/opcode/cgen-bitset.h \
7593 +  $(INCDIR)/opcode/cgen.h $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h \
7594 +  ubicom32-opc.h opintl.h $(INCDIR)/safe-ctype.h
7595 +ubicom32-opc.lo: ubicom32-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
7596 +  $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
7597 +  ubicom32-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
7598 +  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h ubicom32-opc.h \
7599 +  $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h
7600  ip2k-asm.lo: ip2k-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \
7601    $(BFD_H) $(INCDIR)/symcat.h ip2k-desc.h $(INCDIR)/opcode/cgen-bitset.h \
7602    $(INCDIR)/opcode/cgen.h $(INCDIR)/opcode/cgen-bitset.h \
7603 --- a/opcodes/Makefile.in
7604 +++ b/opcodes/Makefile.in
7605 @@ -278,6 +278,7 @@ HFILES = \
7606         sh-opc.h \
7607         sh64-opc.h \
7608         sysdep.h \
7609 +       ubicom32-desc.h ubicom32-opc.h \
7610         w65-opc.h \
7611         xc16x-desc.h xc16x-opc.h \
7612         xstormy16-desc.h xstormy16-opc.h \
7613 @@ -420,6 +421,11 @@ CFILES = \
7614         tic54x-opc.c \
7615         tic80-dis.c \
7616         tic80-opc.c \
7617 +       ubicom32-asm.c \
7618 +       ubicom32-desc.c \
7619 +       ubicom32-dis.c \
7620 +       ubicom32-ibld.c \
7621 +       ubicom32-opc.c \
7622         v850-dis.c \
7623         v850-opc.c \
7624         vax-dis.c \
7625 @@ -562,6 +568,11 @@ ALL_MACHINES = \
7626         tic54x-opc.lo \
7627         tic80-dis.lo \
7628         tic80-opc.lo \
7629 +       ubicom32-asm.lo \
7630 +       ubicom32-desc.lo \
7631 +       ubicom32-dis.lo \
7632 +       ubicom32-ibld.lo \
7633 +       ubicom32-opc.lo \
7634         v850-dis.lo \
7635         v850-opc.lo \
7636         vax-dis.lo \
7637 @@ -604,7 +615,7 @@ libopcodes_la_LDFLAGS = -release `cat ..
7638  noinst_LIBRARIES = libopcodes.a
7639  POTFILES = $(HFILES) $(CFILES)
7640  CLEANFILES = \
7641 -       stamp-ip2k stamp-m32c stamp-m32r stamp-fr30 stamp-frv \
7642 +       stamp-ip2k stamp-ubicom32 stamp-m32c stamp-m32r stamp-fr30 stamp-frv \
7643         stamp-openrisc stamp-iq2000 stamp-mep stamp-mt stamp-xstormy16 stamp-xc16x\
7644         libopcodes.a stamp-lib dep.sed DEP DEPA DEP1 DEP2
7645  
7646 @@ -619,9 +630,11 @@ CGENDEPS = \
7647         $(CGENDIR)/opc-opinst.scm \
7648         cgen-asm.in cgen-dis.in cgen-ibld.in
7649  
7650 -CGEN_CPUS = fr30 frv ip2k m32c m32r mep mt openrisc xc16x xstormy16
7651 +CGEN_CPUS = fr30 frv ip2k ubicom32 m32c m32r mep mt openrisc xc16x xstormy16
7652  @CGEN_MAINT_FALSE@IP2K_DEPS = 
7653  @CGEN_MAINT_TRUE@IP2K_DEPS = stamp-ip2k
7654 +@CGEN_MAINT_FALSE@UBICOM32_DEPS = 
7655 +@CGEN_MAINT_TRUE@UBICOM32_DEPS = stamp-ubicom32
7656  @CGEN_MAINT_FALSE@M32C_DEPS = 
7657  @CGEN_MAINT_TRUE@M32C_DEPS = stamp-m32c
7658  @CGEN_MAINT_FALSE@M32R_DEPS = 
7659 @@ -1035,6 +1048,11 @@ run-cgen-all:
7660  .PHONY: run-cgen-all
7661  
7662  # For now, require developers to configure with --enable-cgen-maint.
7663 +$(srcdir)/ubicom32-desc.h $(srcdir)/ubicom32-desc.c $(srcdir)/ubicom32-opc.h $(srcdir)/ubicom32-opc.c $(srcdir)/ubicom32-ibld.c $(srcdir)/ubicom32-asm.c $(srcdir)/ubicom32-dis.c: $(UBICOM32_DEPS)
7664 +#      @true
7665 +stamp-ubicom32: $(CGENDEPS) $(CPUDIR)/ubicom32.cpu $(CPUDIR)/ubicom32.opc
7666 +       $(MAKE) run-cgen arch=ubicom32 prefix=ubicom32 \
7667 +               archfile=$(CPUDIR)/ubicom32.cpu opcfile=$(CPUDIR)/ubicom32.opc options= extrafiles=
7668  $(srcdir)/ip2k-desc.h $(srcdir)/ip2k-desc.c $(srcdir)/ip2k-opc.h $(srcdir)/ip2k-opc.c $(srcdir)/ip2k-ibld.c $(srcdir)/ip2k-asm.c $(srcdir)/ip2k-dis.c: $(IP2K_DEPS)
7669         @true
7670  stamp-ip2k: $(CGENDEPS) $(CPUDIR)/ip2k.cpu $(CPUDIR)/ip2k.opc
7671 @@ -1375,6 +1393,34 @@ ia64-gen.lo: ia64-gen.c $(INCDIR)/anside
7672    ia64-opc-m.c ia64-opc-b.c ia64-opc-f.c ia64-opc-x.c \
7673    ia64-opc-d.c
7674  ia64-asmtab.lo: ia64-asmtab.c
7675 +ubicom32-asm.lo: ubicom32-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \
7676 +  $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
7677 +  ubicom32-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
7678 +  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h ubicom32-opc.h \
7679 +  opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h \
7680 +  $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h
7681 +ubicom32-desc.lo: ubicom32-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
7682 +  $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
7683 +  ubicom32-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
7684 +  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h ubicom32-opc.h \
7685 +  opintl.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
7686 +  $(INCDIR)/xregex.h $(INCDIR)/xregex2.h
7687 +ubicom32-dis.lo: ubicom32-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
7688 +  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
7689 +  $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
7690 +  ubicom32-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
7691 +  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h ubicom32-opc.h \
7692 +  opintl.h
7693 +ubicom32-ibld.lo: ubicom32-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \
7694 +  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
7695 +  $(BFD_H) $(INCDIR)/symcat.h ubicom32-desc.h $(INCDIR)/opcode/cgen-bitset.h \
7696 +  $(INCDIR)/opcode/cgen.h $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h \
7697 +  ubicom32-opc.h opintl.h $(INCDIR)/safe-ctype.h
7698 +ubicom32-opc.lo: ubicom32-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
7699 +  $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
7700 +  ubicom32-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
7701 +  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h ubicom32-opc.h \
7702 +  $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h
7703  ip2k-asm.lo: ip2k-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \
7704    $(BFD_H) $(INCDIR)/symcat.h ip2k-desc.h $(INCDIR)/opcode/cgen-bitset.h \
7705    $(INCDIR)/opcode/cgen.h $(INCDIR)/opcode/cgen-bitset.h \
7706 --- /dev/null
7707 +++ b/opcodes/ubicom32-asm.c
7708 @@ -0,0 +1,1863 @@
7709 +/* Assembler interface for targets using CGEN. -*- C -*-
7710 +   CGEN: Cpu tools GENerator
7711 +
7712 +   THIS FILE IS MACHINE GENERATED WITH CGEN.
7713 +   - the resultant file is machine generated, cgen-asm.in isn't
7714 +
7715 +   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005, 2007
7716 +   Free Software Foundation, Inc.
7717 +
7718 +   This file is part of libopcodes.
7719 +
7720 +   This library is free software; you can redistribute it and/or modify
7721 +   it under the terms of the GNU General Public License as published by
7722 +   the Free Software Foundation; either version 3, or (at your option)
7723 +   any later version.
7724 +
7725 +   It is distributed in the hope that it will be useful, but WITHOUT
7726 +   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
7727 +   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
7728 +   License for more details.
7729 +
7730 +   You should have received a copy of the GNU General Public License
7731 +   along with this program; if not, write to the Free Software Foundation, Inc.,
7732 +   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
7733 +
7734 +
7735 +/* ??? Eventually more and more of this stuff can go to cpu-independent files.
7736 +   Keep that in mind.  */
7737 +
7738 +#include "sysdep.h"
7739 +#include <stdio.h>
7740 +#include "ansidecl.h"
7741 +#include "bfd.h"
7742 +#include "symcat.h"
7743 +#include "ubicom32-desc.h"
7744 +#include "ubicom32-opc.h"
7745 +#include "opintl.h"
7746 +#include "xregex.h"
7747 +#include "libiberty.h"
7748 +#include "safe-ctype.h"
7749 +
7750 +#undef  min
7751 +#define min(a,b) ((a) < (b) ? (a) : (b))
7752 +#undef  max
7753 +#define max(a,b) ((a) > (b) ? (a) : (b))
7754 +
7755 +static const char * parse_insn_normal
7756 +  (CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *);
7757 +\f
7758 +/* -- assembler routines inserted here.  */
7759 +
7760 +/* -- asm.c */
7761 +
7762 +/* Directly addressable registers on the UBICOM32.
7763 + */
7764 +
7765 +#define RW  0  /* read/write */
7766 +#define RO  1  /* read-only  */
7767 +#define WO  2  /* write-only */
7768 +
7769 +struct ubicom32_cgen_data_space_map ubicom32_cgen_data_space_map_mercury[] = {
7770 +       { 0x0,          "d0", RW, },    /* data registers */
7771 +       /* d1, d2 and d3 are later */
7772 +       { 0x10,         "d4", RW, },
7773 +       { 0x14,         "d5", RW, },
7774 +       { 0x18,         "d6", RW, },
7775 +       { 0x1c,         "d7", RW, },
7776 +       { 0x20,         "d8", RW, },
7777 +       { 0x24,         "d9", RW, },
7778 +       { 0x28,         "d10", RW, },
7779 +       { 0x2c,         "d11", RW, },
7780 +       { 0x30,         "d12", RW, },
7781 +       { 0x34,         "d13", RW, },
7782 +       { 0x38,         "d14", RW, },
7783 +       { 0x3c,         "d15", RW, },
7784 +       { 0x4,          "d1", RW, },    /* put them here where they work */
7785 +       { 0x8,          "d2", RW, },
7786 +       { 0xc,          "d3", RW, },
7787 +       { A0_ADDRESS,   "a0", RW, },    /* address registers */
7788 +       { A1_ADDRESS,   "a1", RW, },
7789 +       { A2_ADDRESS,   "a2", RW, },
7790 +       { A3_ADDRESS,   "a3", RW, },
7791 +       { A4_ADDRESS,   "a4", RW, },
7792 +       { A5_ADDRESS,   "a5", RW, },
7793 +       { A6_ADDRESS,   "a6", RW, },
7794 +       { A7_ADDRESS,   "sp", RW, },    /* sp is a7; first so we use it */
7795 +       { A7_ADDRESS,   "a7", RW, },
7796 +       { 0xa0,         "mac_hi", RW, },
7797 +       { 0xa4,         "mac_lo", RW, },
7798 +       { 0xa8,         "mac_rc16", RW, },
7799 +       { 0xac,         "source3", RW, },
7800 +       { 0xac,         "source_3", RW, },
7801 +       { 0xb0,         "context_cnt", RO,},
7802 +       { 0xb0,         "inst_cnt", RO,},
7803 +       { 0xb4,         "csr", RW, },
7804 +       { 0xb8,         "rosr", RO, },
7805 +       { 0xbc,         "iread_data", RW, },
7806 +       { 0xc0,         "int_mask0", RW, },
7807 +       { 0xc4,         "int_mask1", RW, },
7808 +       /* 0xc8 - 0xcf reserved for future interrupt masks */
7809 +       { 0xd0,         "pc", RW, },
7810 +       /* 0xd4 - ff reserved */
7811 +       { 0x100,        "chip_id", RO, },
7812 +       { 0x104,        "int_stat0", RO, },
7813 +       { 0x108,        "int_stat1", RO, },
7814 +       /* 0x10c - 0x113 reserved for future interrupt masks */
7815 +       { 0x114,        "int_set0", WO, },
7816 +       { 0x118,        "int_set1", WO, },
7817 +        /* 0x11c - 0x123 reserved for future interrupt set */
7818 +       { 0x124,        "int_clr0", WO, },
7819 +        { 0x128,        "int_clr1", WO, },
7820 +        /* 0x13c - 0x133 reserved for future interrupt clear */
7821 +       { 0x134,        "global_ctrl", RW, },
7822 +       { 0x13c,        "mt_active_set", WO, },
7823 +       { 0x140,        "mt_active_clr", WO, },
7824 +       { 0x138,        "mt_active", RO, },
7825 +       { 0x148,        "mt_dbg_active_set", WO, },
7826 +       { 0x144,        "mt_dbg_active", RO, },
7827 +       { 0x14C,        "mt_en", RW, },
7828 +       { 0x150,        "mt_hpri", RW, }, 
7829 +       { 0x150,        "mt_pri", RW, }, 
7830 +       { 0x154,        "mt_hrt", RW, },
7831 +       { 0x154,        "mt_sched", RW, },
7832 +       { 0x15C,        "mt_break_clr", WO, },
7833 +       { 0x158,        "mt_break", RO, },
7834 +       { 0x160,        "mt_single_step", RW, },
7835 +       { 0x164,        "mt_min_delay_en", RW, },
7836 +       { 0x164,        "mt_min_del_en", RW, },
7837 +
7838 +       { 0x16c,        "perr_addr", RO, },
7839 +       { 0x178,        "dcapt_tnum", RO, },
7840 +       { 0x174,        "dcapt_pc", RO, },
7841 +       { 0x170,        "dcapt", RW, },
7842 +       /* 0x17c - 0x1ff reserved */
7843 +       { 0x17c,        "mt_dbg_active_clr", WO, },
7844 +       { 0x180,        "scratchpad0", RW, },
7845 +       { 0x184,        "scratchpad1", RW, },
7846 +       { 0x188,        "scratchpad2", RW, },
7847 +       { 0x18c,        "scratchpad3", RW, },
7848 +
7849 +       { 0x0,          0, RW, },
7850 +};
7851 +
7852 +struct ubicom32_cgen_data_space_map ubicom32_cgen_data_space_map_mars[] = {
7853 +       { 0x0,          "d0", RW, },    /* data registers */
7854 +       /* d1, d2 and d3 are later */
7855 +       { 0x10,         "d4", RW, },
7856 +       { 0x14,         "d5", RW, },
7857 +       { 0x18,         "d6", RW, },
7858 +       { 0x1c,         "d7", RW, },
7859 +       { 0x20,         "d8", RW, },
7860 +       { 0x24,         "d9", RW, },
7861 +       { 0x28,         "d10", RW, },
7862 +       { 0x2c,         "d11", RW, },
7863 +       { 0x30,         "d12", RW, },
7864 +       { 0x34,         "d13", RW, },
7865 +       { 0x38,         "d14", RW, },
7866 +       { 0x3c,         "d15", RW, },
7867 +       { 0x4,          "d1", RW, },    /* put them here where they work */
7868 +       { 0x8,          "d2", RW, },
7869 +       { 0xc,          "d3", RW, },
7870 +       { A0_ADDRESS,   "a0", RW, },    /* address registers */
7871 +       { A1_ADDRESS,   "a1", RW, },
7872 +       { A2_ADDRESS,   "a2", RW, },
7873 +       { A3_ADDRESS,   "a3", RW, },
7874 +       { A4_ADDRESS,   "a4", RW, },
7875 +       { A5_ADDRESS,   "a5", RW, },
7876 +       { A6_ADDRESS,   "a6", RW, },
7877 +       { A7_ADDRESS,   "sp", RW, },    /* sp is a7; first so we use it */
7878 +       { A7_ADDRESS,   "a7", RW, },
7879 +       { 0xa0,         "mac_hi", RW, },
7880 +       { 0xa0,         "acc0_hi", RW, }, /* mac_hi and mac_lo are also known as acc0_hi and acc0_lo */
7881 +       { 0xa4,         "mac_lo", RW, },
7882 +       { 0xa4,         "acc0_lo", RW, },
7883 +       { 0xa8,         "mac_rc16", RW, },
7884 +       { 0xac,         "source3", RW, },
7885 +       { 0xac,         "source_3", RW, },
7886 +       { 0xb0,         "context_cnt", RO,},
7887 +       { 0xb0,         "inst_cnt", RO,},
7888 +       { 0xb4,         "csr", RW, },
7889 +       { 0xb8,         "rosr", RO, },
7890 +       { 0xbc,         "iread_data", RW, },
7891 +       { 0xc0,         "int_mask0", RW, },
7892 +       { 0xc4,         "int_mask1", RW, },
7893 +       /* 0xc8 - 0xcf reserved for future interrupt masks */
7894 +       { 0xd0,         "pc", RW, },
7895 +       { 0xd4,         "trap_cause", RW, },
7896 +       { 0xd8,         "acc1_hi", RW, }, /* Defines for acc1 */
7897 +       { 0xdc,         "acc1_lo", RW, },
7898 +       { 0xe0,         "previous_pc", RO, },
7899 +
7900 +       /* 0xe4 - ff reserved */
7901 +       { 0x100,        "chip_id", RO, },
7902 +       { 0x104,        "int_stat0", RO, },
7903 +       { 0x108,        "int_stat1", RO, },
7904 +       /* 0x10c - 0x113 reserved for future interrupt masks */
7905 +       { 0x114,        "int_set0", WO, },
7906 +       { 0x118,        "int_set1", WO, },
7907 +        /* 0x11c - 0x123 reserved for future interrupt set */
7908 +       { 0x124,        "int_clr0", WO, },
7909 +        { 0x128,        "int_clr1", WO, },
7910 +        /* 0x130 - 0x133 reserved for future interrupt clear */
7911 +       { 0x134,        "global_ctrl", RW, },
7912 +       { 0x13c,        "mt_active_set", WO, },
7913 +       { 0x140,        "mt_active_clr", WO, },
7914 +       { 0x138,        "mt_active", RO, },
7915 +       { 0x148,        "mt_dbg_active_set", WO, },
7916 +       { 0x144,        "mt_dbg_active", RO, },
7917 +       { 0x14C,        "mt_en", RW, },
7918 +       { 0x150,        "mt_hpri", RW, }, 
7919 +       { 0x150,        "mt_pri", RW, }, 
7920 +       { 0x154,        "mt_hrt", RW, },
7921 +       { 0x154,        "mt_sched", RW, },
7922 +       { 0x15C,        "mt_break_clr", WO, },
7923 +       { 0x158,        "mt_break", RO, },
7924 +       { 0x160,        "mt_single_step", RW, },
7925 +       { 0x164,        "mt_min_delay_en", RW, },
7926 +       { 0x164,        "mt_min_del_en", RW, },
7927 +       { 0x168,        "mt_break_set", WO, },
7928 +       /* 0x16c - 0x16f reserved */
7929 +       { 0x170,        "dcapt", RW, },
7930 +       /* 0x174 - 0x17b reserved */
7931 +       { 0x17c,        "mt_dbg_active_clr", WO, },
7932 +       { 0x180,        "scratchpad0", RW, },
7933 +       { 0x184,        "scratchpad1", RW, },
7934 +       { 0x188,        "scratchpad2", RW, },
7935 +       { 0x18c,        "scratchpad3", RW, },
7936 +
7937 +       /* 0x190 - 0x19f Reserved */
7938 +       { 0x1a0,        "chip_cfg", RW, },
7939 +       { 0x1a4,        "mt_i_blocked", RO, },
7940 +       { 0x1a8,        "mt_d_blocked", RO, },
7941 +       { 0x1ac,        "mt_i_blocked_set", WO},
7942 +       { 0x1b0,        "mt_d_blocked_set", WO},
7943 +       { 0x1b4,        "mt_blocked_clr", WO},
7944 +       { 0x1b8,        "mt_trap_en", RW, },
7945 +       { 0x1bc,        "mt_trap", RO, },
7946 +       { 0x1c0,        "mt_trap_set", WO, },
7947 +       { 0x1c4,        "mt_trap_clr", WO, },
7948 +       /* 0x1c8-0x1FF Reserved */
7949 +       { 0x200,        "i_range0_hi", RW},
7950 +       { 0x204,        "i_range1_hi", RW},
7951 +       { 0x208,        "i_range2_hi", RW},
7952 +       { 0x20c,        "i_range3_hi", RW},
7953 +
7954 +       /* 0x210-0x21f Reserved */
7955 +       { 0x220,        "i_range0_lo", RW},
7956 +       { 0x224,        "i_range1_lo", RW},
7957 +       { 0x228,        "i_range2_lo", RW},
7958 +       { 0x22c,        "i_range3_lo", RW},
7959 +
7960 +       /* 0x230-0x23f Reserved */
7961 +       { 0x240,        "i_range0_en", RW},
7962 +       { 0x244,        "i_range1_en", RW},
7963 +       { 0x248,        "i_range2_en", RW},
7964 +       { 0x24c,        "i_range3_en", RW},
7965 +
7966 +       /* 0x250-0x25f Reserved */
7967 +       { 0x260,        "d_range0_hi", RW},
7968 +       { 0x264,        "d_range1_hi", RW},
7969 +       { 0x268,        "d_range2_hi", RW},
7970 +       { 0x26c,        "d_range3_hi", RW},
7971 +       { 0x270,        "d_range4_hi", RW},
7972 +
7973 +       /* 0x274-0x27f Reserved */
7974 +       { 0x280,        "d_range0_lo", RW},
7975 +       { 0x284,        "d_range1_lo", RW},
7976 +       { 0x288,        "d_range2_lo", RW},
7977 +       { 0x28c,        "d_range3_lo", RW},
7978 +       { 0x290,        "d_range4_lo", RW},
7979 +
7980 +       /* 0x294-0x29f Reserved */
7981 +       { 0x2a0,        "d_range0_en", RW},
7982 +       { 0x2a4,        "d_range1_en", RW},
7983 +       { 0x2a8,        "d_range2_en", RW},
7984 +       { 0x2ac,        "d_range3_en", RW},
7985 +       { 0x2b0,        "d_range4_en", RW},
7986 +
7987 +       /* 0x2b4-0x3ff Reserved */
7988 +
7989 +       { 0x0,          0, RW, },
7990 +};
7991 +
7992 +/* t_is_set will be 1 if .t is set for the madd.2 and msub.2 instructions */
7993 +static unsigned char t_is_set =0;
7994 +
7995 +static const char *
7996 +parse_t_is_set_for_addsub (
7997 +                          CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
7998 +                          const char **strp,
7999 +                          CGEN_KEYWORD *keyword_table,
8000 +                          long *valuep)
8001 +{
8002 +  const char *errmsg;
8003 +
8004 +  t_is_set = 0;
8005 +
8006 +  errmsg = cgen_parse_keyword (cd, strp, keyword_table, valuep);
8007 +  if (errmsg)
8008 +    {
8009 +      t_is_set = 0;
8010 +
8011 +      return errmsg;
8012 +    }
8013 +
8014 +  if((int)*valuep)
8015 +     t_is_set = 1;
8016 +
8017 +  return NULL;
8018 +}
8019 +
8020 +char myerrmsg[128];
8021 +
8022 +/* 
8023 + * If accumulator is selected for madd.2 and msub.2 instructions then
8024 + * the T bit should not be selected. Flag an assembler error in those
8025 + * cases.
8026 + */
8027 +static const char *
8028 +parse_acc_for_addsub (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
8029 +                     const char **strp,
8030 +                     CGEN_KEYWORD *keyword_table,
8031 +                     long *valuep)
8032 +{
8033 +  const char *errmsg;
8034 +
8035 +  errmsg = cgen_parse_keyword (cd, strp, keyword_table, valuep);
8036 +  if (errmsg)
8037 +    {
8038 +      t_is_set = 0;
8039 +
8040 +      return errmsg;
8041 +    }
8042 +
8043 +  
8044 +  if(t_is_set)
8045 +    {
8046 +      /* This is erroneous. */
8047 +      sprintf(myerrmsg, "Extenstion \".t\" is illegal when using acc%d as Source 2 register.", (int)*valuep);
8048 +      t_is_set=0;
8049 +      return (myerrmsg);
8050 +    }
8051 +
8052 +  t_is_set=0;
8053 +  return NULL;
8054 +}
8055 +
8056 +/*
8057 + * For dsp madd/msub cases if S2 is a data register then t_is_set flag should be set to zero.
8058 + */
8059 +static const char *
8060 +parse_dr_for_addsub (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
8061 +                    const char **strp,
8062 +                    CGEN_KEYWORD *keyword_table,
8063 +                    long *valuep)
8064 +{
8065 +  const char *errmsg;
8066 +
8067 +  errmsg = cgen_parse_keyword (cd, strp, keyword_table, valuep);
8068 +  if (errmsg)
8069 +    {
8070 +      t_is_set = 0;
8071 +
8072 +      return errmsg;
8073 +    }
8074 +  t_is_set=0;
8075 +  return NULL;
8076 +}
8077 +
8078 +static const char *
8079 +parse_bit5 (CGEN_CPU_DESC cd,
8080 +           const char **strp,
8081 +           int opindex,
8082 +           long *valuep)
8083 +{
8084 +  const char *errmsg;
8085 +  char mode = 0;
8086 +  long count = 0;
8087 +  unsigned long value;
8088 +
8089 +  if (strncmp (*strp, "%bit", 4) == 0)
8090 +    {
8091 +      *strp += 4;
8092 +      mode = 1;
8093 +    }
8094 +  else if (strncmp (*strp, "%msbbit", 7) == 0)
8095 +    {
8096 +      *strp += 7;
8097 +      mode = 2;
8098 +    }
8099 +  else if (strncmp (*strp, "%lsbbit", 7) == 0)
8100 +    {
8101 +      *strp += 7;
8102 +      mode = 3;
8103 +    }
8104 +
8105 +  errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep);
8106 +  if (errmsg) {
8107 +    return errmsg;
8108 +  }
8109 +
8110 +  if (mode) {
8111 +    value = (unsigned long) *valuep;
8112 +    if (value == 0) {
8113 +      errmsg = _("Attempt to find bit index of 0");
8114 +      return errmsg;
8115 +    }
8116 +    
8117 +    if (mode == 1) {
8118 +      count = 31;
8119 +      while ((value & 0x80000000) == 0) {
8120 +        count--;
8121 +        value <<= 1;
8122 +      }
8123 +      if ((value & 0x7FFFFFFF) != 0) {
8124 +        errmsg = _("More than one bit set in bitmask");
8125 +        return errmsg;
8126 +      }
8127 +    } else if (mode == 2) {
8128 +      count = 31;
8129 +      while ((value & 0x80000000) == 0) {
8130 +        count--;
8131 +        value <<= 1;
8132 +      }
8133 +    } else if (mode == 3) {
8134 +      count = 0;
8135 +      while ((value & 0x00000001) == 0) {
8136 +        count++;
8137 +        value >>= 1;
8138 +      }
8139 +    }
8140 +    
8141 +    *valuep = count;
8142 +  }
8143 +
8144 +  return errmsg;
8145 +}
8146 +
8147 +/*
8148 + * For dsp madd/msub cases if S2 is a #bit5 then t_is_set flag should be set to zero.
8149 + */
8150 +static const char *
8151 +parse_bit5_for_addsub (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
8152 +                      const char **strp,
8153 +                      int opindex,
8154 +                      long *valuep)
8155 +{
8156 +  const char *errmsg;
8157 +
8158 +  errmsg = parse_bit5(cd, strp, opindex, valuep);
8159 +  if (errmsg)
8160 +    {
8161 +      t_is_set = 0;
8162 +
8163 +      return errmsg;
8164 +    }
8165 +  t_is_set=0;
8166 +  return NULL;
8167 +}
8168 +
8169 +/* Parse signed 4 bit immediate value, being careful (hacky) to avoid
8170 +   eating a `++' that might be present */
8171 +static const char *
8172 +parse_imm4 (CGEN_CPU_DESC cd,
8173 +           const char **strp,
8174 +           int opindex,
8175 +           long *valuep,
8176 +           int size)
8177 +{
8178 +  const char *errmsg;
8179 +  char *plusplus;
8180 +  long value;
8181 +
8182 +  plusplus = strstr(*strp, "++");
8183 +  if (plusplus)
8184 +    *plusplus = 0;
8185 +  errmsg = cgen_parse_signed_integer (cd, strp, opindex, &value);
8186 +  if (plusplus)
8187 +    *plusplus = '+';
8188 +
8189 +  if (errmsg == NULL)
8190 +    {
8191 +      if ((size == 2 && (value % 2)) ||
8192 +          (size == 4 && (value % 4)))
8193 +       errmsg = _("unaligned increment");
8194 +      else if ((size == 1 && (value < -8 || value > 7)) ||
8195 +          (size == 2 && (value < -16 || value > 15)) ||
8196 +          (size == 4 && (value < -32 || value > 31)))
8197 +       errmsg = _("out of bounds increment");
8198 +      else
8199 +        *valuep = value;
8200 +    }
8201 +  return errmsg;
8202 +}
8203 +
8204 +/* as above, for single byte addresses */
8205 +static const char *
8206 +parse_imm4_1 (CGEN_CPU_DESC cd,
8207 +             const char **strp,
8208 +             int opindex,
8209 +             long *valuep)
8210 +{
8211 +  return parse_imm4 (cd, strp, opindex, valuep, 1);
8212 +}
8213 +
8214 +/* as above, for half-word addresses */
8215 +static const char *
8216 +parse_imm4_2 (CGEN_CPU_DESC cd,
8217 +             const char **strp,
8218 +             int opindex,
8219 +             long *valuep)
8220 +{
8221 +  return parse_imm4 (cd, strp, opindex, valuep, 2);
8222 +}
8223 +
8224 +/* as above, for word addresses */
8225 +static const char *
8226 +parse_imm4_4 (CGEN_CPU_DESC cd,
8227 +             const char **strp,
8228 +             int opindex,
8229 +             long *valuep)
8230 +{
8231 +  return parse_imm4 (cd, strp, opindex, valuep, 4);
8232 +}
8233 +
8234 +/* Parse a direct address.  This can be either `$xx' or a Register
8235 +   Mnemonic.
8236 + */
8237 +static const char *
8238 +parse_direct_addr (CGEN_CPU_DESC cd,
8239 +                  const char **strp,
8240 +                  int opindex,
8241 +                  long *valuep,
8242 +                  int isdest)
8243 +{
8244 +  const char *errmsg = NULL;
8245 +  bfd_vma value;
8246 +  struct ubicom32_cgen_data_space_map *cur;
8247 +  size_t len;
8248 +
8249 +  if(cd->machs & (1<<MACH_IP3035))
8250 +    {
8251 +      /* cpu is mercury */
8252 +      cur = ubicom32_cgen_data_space_map_mercury;
8253 +    }
8254 +  else
8255 +    {
8256 +      /* cpu is mars */
8257 +      cur = ubicom32_cgen_data_space_map_mars;
8258 +    }
8259 +
8260 +  /* First, try to look for the literal register name. */
8261 +  for (; cur->name; cur++)
8262 +    if (strncasecmp(cur->name, *strp, (len = strlen(cur->name))) == 0 &&
8263 +        !ISALNUM((*strp)[len]) && (*strp)[len] != '_' )
8264 +      {
8265 +       *strp += len;
8266 +        /* fail if specifying a read-only register as a destination */
8267 +       if (isdest && cur->type == RO)
8268 +         return _("attempt to write to read-only register");
8269 +       
8270 +       /* fail if specifying a write-only register as a source */
8271 +       if ((isdest==0) && cur->type == WO)
8272 +         return _("attempt to read a write-only register");
8273 +       value = cur->address;
8274 +       errmsg = NULL;
8275 +       break;
8276 +      }
8277 +  
8278 +  /* Not found: try parsing it as a literal */
8279 +  if (cur->name == NULL)
8280 +    {
8281 +      char *plusplus;
8282 +      if (**strp == '(')
8283 +       {
8284 +         return _("parentheses are reserved for indirect addressing");
8285 +       }
8286 +
8287 +      if (strncasecmp(*strp, "%f", 2) == 0)
8288 +       {
8289 +         *valuep = 0;
8290 +         return NULL;
8291 +       }
8292 +
8293 +      /* we want to avoid parsing a negative post-increment expression as a numeric
8294 +        expression because the parser assumes zeroes exist between the pluses and
8295 +        issues an extraneous warning message. */
8296 +      plusplus = strstr(*strp, "++");
8297 +      if (plusplus)
8298 +       *plusplus = 0;
8299 +      errmsg = cgen_parse_signed_integer (cd, strp, opindex, &value);
8300 +      if (plusplus)
8301 +       *plusplus = '+';
8302 +
8303 +      if (errmsg)
8304 +       return errmsg;
8305 +    }
8306 +
8307 +  value &= 0x3ff;
8308 +  *valuep = value;
8309 +  return errmsg;
8310 +}
8311 +
8312 +static const char *
8313 +parse_d_direct_addr (CGEN_CPU_DESC cd,
8314 +                    const char **strp,
8315 +                    int opindex,
8316 +                    long *valuep)
8317 +{
8318 +  return parse_direct_addr (cd, strp, opindex, valuep, 1);
8319 +}
8320 +
8321 +static const char *
8322 +parse_s1_direct_addr (CGEN_CPU_DESC cd,
8323 +                     const char **strp,
8324 +                     int opindex,
8325 +                     long *valuep)
8326 +{
8327 +  return parse_direct_addr (cd, strp, opindex, valuep, 0);
8328 +}
8329 +
8330 +/* support for source-1 and destination operand 7-bit immediates for indirect addressing */
8331 +static const char *imm7_1_rangemsg = "7-bit byte immediate value out of range";
8332 +static const char *imm7_2_rangemsg = "7-bit halfword immediate value out of range";
8333 +static const char *imm7_4_rangemsg = "7-bit word immediate value out of range";
8334 +static const char *imm7_pdec_rangemsg = "Pdec offset out of range. Allowed range is >=4 and <=512.";
8335 +static const char *imm7_2_maskmsg = "7-bit halfword immediate not a multiple of 2";
8336 +static const char *imm7_4_maskmsg = "7-bit word immediate not a multiple of 4";
8337 +
8338 +/* Parse 7-bit immediates, allow %lo() operator */
8339 +static const char *
8340 +parse_imm7_basic (CGEN_CPU_DESC cd,
8341 +                 const char **strp,
8342 +                 int opindex,
8343 +                 unsigned long *valuep,
8344 +                 const char *rangemsg,
8345 +                 const char *maskmsg,
8346 +                 bfd_vma max,
8347 +                 int mask,
8348 +                 int reloc)
8349 +{
8350 +  const char *errmsg;
8351 +  enum cgen_parse_operand_result result_type = CGEN_PARSE_OPERAND_RESULT_NUMBER;
8352 +  bfd_vma value;
8353 +  int newreloc;
8354 +
8355 +  /* in this case we want low 7-bits to accompany the 24-bit immediate of a moveai instruction */
8356 +  if (strncasecmp (*strp, "%lo(", 4) == 0)
8357 +    {
8358 +      *strp += 4;
8359 +      errmsg = cgen_parse_address (cd, strp, opindex, reloc,
8360 +                                  &result_type, &value);
8361 +      if (**strp != ')')
8362 +       return _("missing `)'");
8363 +      ++*strp;
8364 +      if (errmsg == NULL
8365 +         && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
8366 +       value &= 0x7f;  /* always want 7 bits, regardless of imm7 type */
8367 +      *valuep = value;
8368 +      return errmsg;
8369 +    }
8370 +  else if (strncasecmp (*strp, "%got_lo(", strlen("%got_lo(")) == 0)
8371 +    {
8372 +      *strp += strlen("%got_lo(");
8373 +
8374 +      /* Switch the relocation to the GOT relocation. */
8375 +      switch(reloc)
8376 +       {
8377 +       case BFD_RELOC_UBICOM32_LO7_S:
8378 +         reloc = BFD_RELOC_UBICOM32_GOT_LO7_S;
8379 +         break;
8380 +       case BFD_RELOC_UBICOM32_LO7_2_S:
8381 +         reloc = BFD_RELOC_UBICOM32_GOT_LO7_2_S;
8382 +         break;
8383 +       case BFD_RELOC_UBICOM32_LO7_4_S:
8384 +         reloc = BFD_RELOC_UBICOM32_GOT_LO7_4_S;
8385 +         break;
8386 +       case BFD_RELOC_UBICOM32_LO7_D:
8387 +         reloc = BFD_RELOC_UBICOM32_GOT_LO7_D;
8388 +         break;
8389 +       case BFD_RELOC_UBICOM32_LO7_2_D:
8390 +         reloc = BFD_RELOC_UBICOM32_GOT_LO7_2_D;
8391 +         break;
8392 +       case BFD_RELOC_UBICOM32_LO7_4_D:
8393 +         reloc = BFD_RELOC_UBICOM32_GOT_LO7_4_D;
8394 +         break;
8395 +       }
8396 +      errmsg = cgen_parse_address (cd, strp, opindex, reloc,
8397 +                                  &result_type, &value);
8398 +      if (**strp != ')')
8399 +       return _("missing `)'");
8400 +      ++*strp;
8401 +      if (errmsg == NULL
8402 +         && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
8403 +       value &= 0x7f;  /* always want 7 bits, regardless of imm7 type */
8404 +      *valuep = value;
8405 +      return errmsg;
8406 +    }
8407 +  else if (strncasecmp (*strp, "%funcdesc_got_lo(", strlen("%funcdesc_got_lo(")) == 0)
8408 +    {
8409 +      *strp += strlen("%funcdesc_got_lo(");
8410 +
8411 +      /* Switch the relocation to the GOT relocation. */
8412 +      switch(reloc)
8413 +       {
8414 +       case BFD_RELOC_UBICOM32_LO7_S:
8415 +         reloc = BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_S;
8416 +         break;
8417 +       case BFD_RELOC_UBICOM32_LO7_2_S:
8418 +         reloc = BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_2_S;
8419 +         break;
8420 +       case BFD_RELOC_UBICOM32_LO7_4_S:
8421 +         reloc = BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_4_S;
8422 +         break;
8423 +       case BFD_RELOC_UBICOM32_LO7_D:
8424 +         reloc = BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_D;
8425 +         break;
8426 +       case BFD_RELOC_UBICOM32_LO7_2_D:
8427 +         reloc = BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_2_D;
8428 +         break;
8429 +       case BFD_RELOC_UBICOM32_LO7_4_D:
8430 +         reloc = BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_4_D;
8431 +         break;
8432 +       }
8433 +      errmsg = cgen_parse_address (cd, strp, opindex, reloc,
8434 +                                  &result_type, &value);
8435 +      if (**strp != ')')
8436 +       return _("missing `)'");
8437 +      ++*strp;
8438 +      if (errmsg == NULL
8439 +         && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
8440 +       value &= 0x7f;  /* always want 7 bits, regardless of imm7 type */
8441 +      *valuep = value;
8442 +      return errmsg;
8443 +    }
8444 +  else
8445 +    {
8446 +      if (**strp == '(')
8447 +       {
8448 +         return _("parentheses are reserved for indirect addressing");
8449 +       }
8450 +
8451 +      errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, &value);
8452 +    }
8453 +
8454 +  if (errmsg == NULL)
8455 +    {
8456 +      if (value > max)
8457 +       return rangemsg;
8458 +      if (value & mask)
8459 +       return maskmsg;
8460 +    }
8461 +
8462 +  *valuep = value & max;
8463 +  return errmsg;
8464 +}
8465 +
8466 +/* Parse 7-bit immediates, allow %lo() operator */
8467 +static const char *
8468 +parse_imm7_pdec (CGEN_CPU_DESC cd,
8469 +                const char **strp,
8470 +                int opindex,
8471 +                unsigned long *valuep,
8472 +                const char *rangemsg,
8473 +                const char *maskmsg,
8474 +                int reloc)
8475 +{
8476 +  const char *errmsg;
8477 +  enum cgen_parse_operand_result result_type = CGEN_PARSE_OPERAND_RESULT_NUMBER;
8478 +  bfd_vma value;
8479 +
8480 +  /* in this case we want low 7-bits to accompany the 24-bit immediate of a moveai instruction */
8481 +  if (strncasecmp (*strp, "%lo(", 4) == 0)
8482 +    {
8483 +      *strp += 4;
8484 +      errmsg = cgen_parse_address (cd, strp, opindex, reloc,
8485 +                                  &result_type, &value);
8486 +      if (**strp != ')')
8487 +       return _("missing `)'");
8488 +      ++*strp;
8489 +      if (errmsg == NULL
8490 +         && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
8491 +       value &= 0x7f;  /* always want 7 bits, regardless of imm7 type */
8492 +      *valuep = value;
8493 +      return errmsg;
8494 +    }
8495 +  else
8496 +    {
8497 +      if (**strp == '(')
8498 +       {
8499 +         return _("parentheses are reserved for indirect addressing");
8500 +       }
8501 +
8502 +      errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, &value);
8503 +    }
8504 +
8505 +  if (errmsg == NULL)
8506 +    {
8507 +      if (((long)value > 512) || ((long)value < 4))
8508 +       return rangemsg;
8509 +      if (value & 0x3)
8510 +       return maskmsg;
8511 +    }
8512 +
8513 +  *valuep = value;
8514 +  return errmsg;
8515 +}
8516 +
8517 +/* single byte imm7 */
8518 +static const char *
8519 +parse_imm7_1_s (CGEN_CPU_DESC cd,
8520 +               const char **strp,
8521 +               int opindex,
8522 +               unsigned long *valuep)
8523 +{
8524 +  return parse_imm7_basic (cd, strp, opindex, valuep, _(imm7_1_rangemsg),
8525 +                          NULL, 0x7f, 0, BFD_RELOC_UBICOM32_LO7_S);
8526 +}
8527 +
8528 +/* halfword imm7 */
8529 +static const char *
8530 +parse_imm7_2_s (CGEN_CPU_DESC cd,
8531 +               const char **strp,
8532 +               int opindex,
8533 +               unsigned long *valuep)
8534 +{
8535 +  return parse_imm7_basic (cd, strp, opindex, valuep, 
8536 +                          _(imm7_2_rangemsg),
8537 +                          _(imm7_2_maskmsg),
8538 +                          0xfe, 0x1, BFD_RELOC_UBICOM32_LO7_2_S);
8539 +}
8540 +
8541 +/* word imm7 */
8542 +static const char *
8543 +parse_imm7_4_s (CGEN_CPU_DESC cd,
8544 +               const char **strp,
8545 +               int opindex,
8546 +               unsigned long *valuep)
8547 +{
8548 +  return parse_imm7_basic (cd, strp, opindex, valuep, 
8549 +                          _(imm7_4_rangemsg),
8550 +                          _(imm7_4_maskmsg),
8551 +                          0x1fc, 0x3, BFD_RELOC_UBICOM32_LO7_4_S);
8552 +}
8553 +
8554 +/* word imm7 */
8555 +static const char *
8556 +parse_pdec_imm7_4_s (CGEN_CPU_DESC cd,
8557 +                    const char **strp,
8558 +                    int opindex,
8559 +                    unsigned long *valuep)
8560 +{
8561 +  unsigned long value;
8562 +  const char *errmsg = parse_imm7_pdec (cd, strp, opindex, &value, 
8563 +                                       _(imm7_pdec_rangemsg),
8564 +                                       _(imm7_4_maskmsg),
8565 +                                       BFD_RELOC_UBICOM32_LO7_4_S);
8566 +
8567 +  if(errmsg == NULL)
8568 +    {
8569 +      /* at this point we have a valid value. Take the 2's comp and truncate to 7 bits */
8570 +      if(value == 0)
8571 +       return _("Offset for PDEC source cannot be 0");
8572 +
8573 +      value = ~value;
8574 +      value ++;
8575 +      value &= 0x1fc;
8576 +      *valuep = value;
8577 +    }
8578 +
8579 +  return errmsg;
8580 +}
8581 +
8582 +/* single byte dest imm7 */
8583 +static const char *
8584 +parse_imm7_1_d (CGEN_CPU_DESC cd,
8585 +               const char **strp,
8586 +               int opindex,
8587 +               unsigned long *valuep)
8588 +{
8589 +  return parse_imm7_basic (cd, strp, opindex, valuep, _(imm7_1_rangemsg),
8590 +                          NULL, 0x7f, 0, BFD_RELOC_UBICOM32_LO7_D);
8591 +}
8592 +
8593 +/* halfword dest imm7 */
8594 +static const char *
8595 +parse_imm7_2_d (CGEN_CPU_DESC cd,
8596 +               const char **strp,
8597 +               int opindex,
8598 +               unsigned long *valuep)
8599 +{
8600 +  return parse_imm7_basic (cd, strp, opindex, valuep, 
8601 +                          _(imm7_2_rangemsg),
8602 +                          _(imm7_2_maskmsg),
8603 +                          0xfe, 0x1, BFD_RELOC_UBICOM32_LO7_2_D);
8604 +}
8605 +
8606 +/* word dest imm7 */
8607 +static const char *
8608 +parse_imm7_4_d (CGEN_CPU_DESC cd,
8609 +               const char **strp,
8610 +               int opindex,
8611 +               unsigned long *valuep)
8612 +{
8613 +  return parse_imm7_basic (cd, strp, opindex, valuep, 
8614 +                          _(imm7_4_rangemsg),
8615 +                          _(imm7_4_maskmsg),
8616 +                          0x1fc, 0x3, BFD_RELOC_UBICOM32_LO7_4_D);
8617 +}
8618 +
8619 +/* Parse 16-bit immediate, allow %hi() or %lo() operators */
8620 +static const char *
8621 +parse_imm16 (CGEN_CPU_DESC cd,
8622 +            const char **strp,
8623 +            int opindex,
8624 +            unsigned long *valuep)
8625 +{
8626 +  const char *errmsg;
8627 +  enum cgen_parse_operand_result result_type = CGEN_PARSE_OPERAND_RESULT_NUMBER;
8628 +  bfd_vma value;
8629 +
8630 +  if (strncasecmp (*strp, "%hi(", 4) == 0)
8631 +    {
8632 +      *strp += 4;
8633 +      errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_HI16,
8634 +                                  &result_type, &value);
8635 +      if (**strp != ')')
8636 +       return _("missing `)'");
8637 +      ++*strp;
8638 +      if (errmsg == NULL
8639 +         && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
8640 +       value >>= 16;
8641 +      *valuep = value;
8642 +      return errmsg;
8643 +    }
8644 +  else if (strncasecmp (*strp, "%got_hi(", strlen("%got_hi(")) == 0)
8645 +    {
8646 +      *strp += strlen("%got_hi(");
8647 +      errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_UBICOM32_GOTOFFSET_HI,
8648 +                                  &result_type, &value);
8649 +      if (**strp != ')')
8650 +       return _("missing `)'");
8651 +      ++*strp;
8652 +      if (errmsg == NULL
8653 +         && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
8654 +       value >>= 16;
8655 +      *valuep = value;
8656 +      return errmsg;
8657 +    }
8658 +  else if (strncasecmp (*strp, "%got_funcdesc_hi(", strlen("%got_funcdesc_hi(")) == 0)
8659 +    {
8660 +      *strp += strlen("%got_funcdesc_hi(");
8661 +      errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_UBICOM32_FUNCDESC_GOTOFFSET_HI,
8662 +                                  &result_type, &value);
8663 +      if (**strp != ')')
8664 +       return _("missing `)'");
8665 +      ++*strp;
8666 +      if (errmsg == NULL
8667 +         && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
8668 +       value >>= 16;
8669 +      *valuep = value;
8670 +      return errmsg;
8671 +    }
8672 +  else if (strncasecmp (*strp, "%lo(", 4) == 0)
8673 +    {
8674 +      *strp += 4;
8675 +      errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16,
8676 +                                  &result_type, &value);
8677 +      if (**strp != ')')
8678 +       return _("missing `)'");
8679 +      ++*strp;
8680 +      if (errmsg == NULL
8681 +         && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
8682 +       value &= 0xffff;
8683 +      *valuep = value;
8684 +      return errmsg;
8685 +    }
8686 +  else if (strncasecmp (*strp, "%got_lo(", strlen("%got_lo(")) == 0)
8687 +    {
8688 +      *strp += strlen("%got_lo(");
8689 +      errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_UBICOM32_GOTOFFSET_LO,
8690 +                                  &result_type, &value);
8691 +      if (**strp != ')')
8692 +       return _("missing `)'");
8693 +      ++*strp;
8694 +      if (errmsg == NULL
8695 +         && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
8696 +       value &= 0xffff;
8697 +      *valuep = value;
8698 +      return errmsg;
8699 +    }
8700 +  else if (strncasecmp (*strp, "%got_funcdesc_lo(", strlen("%got_funcdesc_lo(")) == 0)
8701 +    {
8702 +      *strp += strlen("%got_funcdesc_lo(");
8703 +      errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_UBICOM32_FUNCDESC_GOTOFFSET_LO,
8704 +                                  &result_type, &value);
8705 +      if (**strp != ')')
8706 +       return _("missing `)'");
8707 +      ++*strp;
8708 +      if (errmsg == NULL
8709 +         && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
8710 +       value &= 0xffff;
8711 +      *valuep = value;
8712 +      return errmsg;
8713 +    }
8714 +  else
8715 +    {
8716 +      errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, &value);
8717 +    }
8718 +
8719 +  if (errmsg == NULL
8720 +      && ((long)value > 65535 || (long)value < -32768))
8721 +    return _("16-bit immediate value out of range");
8722 +
8723 +  *valuep = value & 0xffff;
8724 +  return errmsg;
8725 +}
8726 +
8727 +/* Parse 24-bit immediate for moveai instruction and allow %hi() operator */
8728 +static const char *
8729 +parse_imm24 (CGEN_CPU_DESC cd,
8730 +            const char **strp,
8731 +            int opindex,
8732 +            unsigned long *valuep)
8733 +{
8734 +  const char *errmsg;
8735 +  enum cgen_parse_operand_result result_type = CGEN_PARSE_OPERAND_RESULT_NUMBER;
8736 +  bfd_vma value;
8737 +
8738 +  if (strncasecmp (*strp, "%hi(", 4) == 0)
8739 +    {
8740 +      *strp += 4;
8741 +      errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_UBICOM32_HI24,
8742 +                                  &result_type, &value);
8743 +      if (**strp != ')')
8744 +       return _("missing `)'");
8745 +      ++*strp;
8746 +      if (errmsg == NULL
8747 +         && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
8748 +       value >>= 7;
8749 +      *valuep = value;
8750 +      return errmsg;
8751 +    }
8752 +  else if (strncasecmp (*strp, "%got_hi(", strlen("%got_hi(")) == 0)
8753 +    {
8754 +      *strp += strlen("%got_hi(");
8755 +      errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_UBICOM32_GOT_HI24,
8756 +                                  &result_type, &value);
8757 +      if (**strp != ')')
8758 +       return _("missing `)'");
8759 +      ++*strp;
8760 +      if (errmsg == NULL
8761 +         && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
8762 +       value >>= 7;
8763 +      *valuep = value;
8764 +      return errmsg;
8765 +    }
8766 +  else if (strncasecmp (*strp, "%funcdesc_got_hi(", strlen("%funcdesc_got_hi(")) == 0)
8767 +    {
8768 +      *strp += strlen("%funcdesc_got_hi(");
8769 +      errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_UBICOM32_FUNCDESC_GOT_HI24,
8770 +                                  &result_type, &value);
8771 +      if (**strp != ')')
8772 +       return _("missing `)'");
8773 +      ++*strp;
8774 +      if (errmsg == NULL
8775 +         && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
8776 +       value >>= 7;
8777 +      *valuep = value;
8778 +      return errmsg;
8779 +    }
8780 +  else
8781 +    {
8782 +      errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, &value);
8783 +    }
8784 +
8785 +  if (errmsg == NULL
8786 +      && ((long)value > 16777215 || (long)value < 0))
8787 +    return _("24-bit immediate value out of range");
8788 +
8789 +  *valuep = value;
8790 +  return errmsg;
8791 +}
8792 +
8793 +static const char *
8794 +parse_offset21 (CGEN_CPU_DESC cd,
8795 +               const char **strp,
8796 +               int opindex,
8797 +               int reloc ATTRIBUTE_UNUSED,
8798 +               enum cgen_parse_operand_result *type_addr ATTRIBUTE_UNUSED, 
8799 +               unsigned long *valuep)
8800 +{
8801 +  const char *errmsg;
8802 +  enum cgen_parse_operand_result result_type = CGEN_PARSE_OPERAND_RESULT_NUMBER;
8803 +  bfd_vma value;
8804 +
8805 +  if (**strp == '#')
8806 +    {
8807 +      ++*strp;
8808 +      errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, &value);
8809 +    }
8810 +  else
8811 +    errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_UBICOM32_21_PCREL,
8812 +                              &result_type, &value);
8813 +
8814 +  if (errmsg == NULL && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
8815 +    {
8816 +      /* we treat jmp #constant as being jump to pc + constant * 4 */
8817 +      if ((long)value > 1048575 || (long)value < -1048576)
8818 +        return _("21-bit relative offset out of range");
8819 +    }
8820 +
8821 +  *valuep = value & 0x7fffff; /* address is actually 23 bits before shift */
8822 +  return errmsg;
8823 +}
8824 +
8825 +static const char *
8826 +parse_offset16 (CGEN_CPU_DESC cd,
8827 +               const char **strp,
8828 +               int opindex,
8829 +               unsigned long *valuep)
8830 +{
8831 +  const char *errmsg;
8832 +  enum cgen_parse_operand_result result_type = CGEN_PARSE_OPERAND_RESULT_NUMBER;
8833 +  bfd_vma value;
8834 +
8835 +  /* in this case we want low 7-bits to accompany the 24-bit immediate of a moveai instruction */
8836 +  if (strncasecmp (*strp, "%lo(", 4) == 0)
8837 +    {
8838 +      *strp += 4;
8839 +      errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_UBICOM32_LO7_CALLI,
8840 +                                  &result_type, &value);
8841 +      if (errmsg != NULL)
8842 +        return errmsg;
8843 +
8844 +      if (**strp != ')')
8845 +       return _("missing `)'");
8846 +      ++*strp;
8847 +
8848 +      if (result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
8849 +        *valuep = value & 0x7c;
8850 +
8851 +      return NULL;
8852 +    }
8853 +
8854 +  if (strncasecmp (*strp, "%got_lo(", strlen("%got_lo(")) == 0)
8855 +    {
8856 +      *strp += strlen("%got_lo(");
8857 +      errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_UBICOM32_GOT_LO7_CALLI,
8858 +                                  &result_type, &value);
8859 +      if (errmsg != NULL)
8860 +        return errmsg;
8861 +
8862 +      if (**strp != ')')
8863 +       return _("missing `)'");
8864 +      ++*strp;
8865 +
8866 +      if (result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
8867 +        *valuep = value & 0x7c;
8868 +
8869 +      return NULL;
8870 +    }
8871 +
8872 +  if (strncasecmp (*strp, "%funcdesc_got_lo(", strlen("%funcdesc_got_lo(")) == 0)
8873 +    {
8874 +      *strp += strlen("%funcdesc_got_lo(");
8875 +      errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_UBICOM32_FUNCDESC_GOT_LO7_CALLI,
8876 +                                  &result_type, &value);
8877 +      if (errmsg != NULL)
8878 +        return errmsg;
8879 +
8880 +      if (**strp != ')')
8881 +       return _("missing `)'");
8882 +      ++*strp;
8883 +
8884 +      if (result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
8885 +        *valuep = value & 0x7c;
8886 +
8887 +      return NULL;
8888 +    }
8889 +
8890 +  if (strncasecmp (*strp, "%lo18(", 6) == 0)
8891 +    {
8892 +      *strp += 6;
8893 +      errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_UBICOM32_LO16_CALLI,
8894 +                                  &result_type, &value);
8895 +      if (errmsg != NULL)
8896 +        return errmsg;
8897 +
8898 +      if (**strp != ')')
8899 +       return _("missing `)'");
8900 +      ++*strp;
8901 +
8902 +      if (result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
8903 +        *valuep = value & 0x0003fffc;
8904 +
8905 +      return NULL;
8906 +    }
8907 +
8908 +  errmsg = cgen_parse_signed_integer (cd, strp, opindex, &value);
8909 +  if (errmsg != NULL)
8910 +    return errmsg;
8911 +
8912 +  /* ensure calli constant within limits and is multiple of 4 */
8913 +  if (value & 0x3)
8914 +    return _("calli offset must be multiple of 4");
8915 +
8916 +  if ((long)value > 131071 || (long)value < -131072)
8917 +    return _("16-bit calli offset out of range");
8918 +
8919 +  *valuep = value & 0x0003fffc; /* address is actually 18 bits before shift */
8920 +  return NULL;
8921 +}
8922 +
8923 +static const char *
8924 +parse_imm8 (CGEN_CPU_DESC cd,
8925 +           const char **strp,
8926 +           int opindex,
8927 +           unsigned long *valuep)
8928 +{
8929 +  const char *errmsg;
8930 +  bfd_vma value;
8931 +  int no_sign = 0;
8932 +
8933 +  if (**strp == '0' && TOUPPER(*(*strp+1)) == 'X')
8934 +    no_sign = 1;
8935 +
8936 +  errmsg = cgen_parse_signed_integer (cd, strp, opindex, &value);
8937 +
8938 +  if (errmsg == NULL)
8939 +    {
8940 +      if ((no_sign && ((long)value > 255)) || 
8941 +         (!no_sign && (((long)value > 127) || ((long)value < -128))))
8942 +        return _("8-bit immediate value out of range");
8943 +    }
8944 +
8945 +  *valuep = value & 0xff;
8946 +  return errmsg;
8947 +}
8948 +
8949 +/* -- dis.c */
8950 +
8951 +const char * ubicom32_cgen_parse_operand
8952 +  (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *);
8953 +
8954 +/* Main entry point for operand parsing.
8955 +
8956 +   This function is basically just a big switch statement.  Earlier versions
8957 +   used tables to look up the function to use, but
8958 +   - if the table contains both assembler and disassembler functions then
8959 +     the disassembler contains much of the assembler and vice-versa,
8960 +   - there's a lot of inlining possibilities as things grow,
8961 +   - using a switch statement avoids the function call overhead.
8962 +
8963 +   This function could be moved into `parse_insn_normal', but keeping it
8964 +   separate makes clear the interface between `parse_insn_normal' and each of
8965 +   the handlers.  */
8966 +
8967 +const char *
8968 +ubicom32_cgen_parse_operand (CGEN_CPU_DESC cd,
8969 +                          int opindex,
8970 +                          const char ** strp,
8971 +                          CGEN_FIELDS * fields)
8972 +{
8973 +  const char * errmsg = NULL;
8974 +  /* Used by scalar operands that still need to be parsed.  */
8975 +  long junk ATTRIBUTE_UNUSED;
8976 +
8977 +  switch (opindex)
8978 +    {
8979 +    case UBICOM32_OPERAND_AM :
8980 +      errmsg = cgen_parse_keyword (cd, strp, & ubicom32_cgen_opval_addr_names, & fields->f_Am);
8981 +      break;
8982 +    case UBICOM32_OPERAND_AN :
8983 +      errmsg = cgen_parse_keyword (cd, strp, & ubicom32_cgen_opval_addr_names, & fields->f_An);
8984 +      break;
8985 +    case UBICOM32_OPERAND_C :
8986 +      errmsg = cgen_parse_keyword (cd, strp, & ubicom32_cgen_opval_h_C, & fields->f_C);
8987 +      break;
8988 +    case UBICOM32_OPERAND_DN :
8989 +      errmsg = cgen_parse_keyword (cd, strp, & ubicom32_cgen_opval_data_names, & fields->f_Dn);
8990 +      break;
8991 +    case UBICOM32_OPERAND_P :
8992 +      errmsg = cgen_parse_keyword (cd, strp, & ubicom32_cgen_opval_h_P, & fields->f_P);
8993 +      break;
8994 +    case UBICOM32_OPERAND_ACC1HI :
8995 +      errmsg = cgen_parse_unsigned_integer (cd, strp, UBICOM32_OPERAND_ACC1HI, (unsigned long *) (& junk));
8996 +      break;
8997 +    case UBICOM32_OPERAND_ACC1LO :
8998 +      errmsg = cgen_parse_unsigned_integer (cd, strp, UBICOM32_OPERAND_ACC1LO, (unsigned long *) (& junk));
8999 +      break;
9000 +    case UBICOM32_OPERAND_BIT5 :
9001 +      errmsg = parse_bit5 (cd, strp, UBICOM32_OPERAND_BIT5, (unsigned long *) (& fields->f_bit5));
9002 +      break;
9003 +    case UBICOM32_OPERAND_BIT5_ADDSUB :
9004 +      errmsg = parse_bit5_for_addsub (cd, strp, UBICOM32_OPERAND_BIT5_ADDSUB, (unsigned long *) (& fields->f_bit5));
9005 +      break;
9006 +    case UBICOM32_OPERAND_CC :
9007 +      errmsg = cgen_parse_keyword (cd, strp, & ubicom32_cgen_opval_h_cc, & fields->f_cond);
9008 +      break;
9009 +    case UBICOM32_OPERAND_D_AN :
9010 +      errmsg = cgen_parse_keyword (cd, strp, & ubicom32_cgen_opval_addr_names, & fields->f_d_An);
9011 +      break;
9012 +    case UBICOM32_OPERAND_D_DIRECT_ADDR :
9013 +      errmsg = parse_d_direct_addr (cd, strp, UBICOM32_OPERAND_D_DIRECT_ADDR, (unsigned long *) (& fields->f_d_direct));
9014 +      break;
9015 +    case UBICOM32_OPERAND_D_I4_1 :
9016 +      errmsg = parse_imm4_1 (cd, strp, UBICOM32_OPERAND_D_I4_1, (long *) (& fields->f_d_i4_1));
9017 +      break;
9018 +    case UBICOM32_OPERAND_D_I4_2 :
9019 +      errmsg = parse_imm4_2 (cd, strp, UBICOM32_OPERAND_D_I4_2, (long *) (& fields->f_d_i4_2));
9020 +      break;
9021 +    case UBICOM32_OPERAND_D_I4_4 :
9022 +      errmsg = parse_imm4_4 (cd, strp, UBICOM32_OPERAND_D_I4_4, (long *) (& fields->f_d_i4_4));
9023 +      break;
9024 +    case UBICOM32_OPERAND_D_IMM7_1 :
9025 +      errmsg = parse_imm7_1_d (cd, strp, UBICOM32_OPERAND_D_IMM7_1, (unsigned long *) (& fields->f_d_imm7_1));
9026 +      break;
9027 +    case UBICOM32_OPERAND_D_IMM7_2 :
9028 +      errmsg = parse_imm7_2_d (cd, strp, UBICOM32_OPERAND_D_IMM7_2, (unsigned long *) (& fields->f_d_imm7_2));
9029 +      break;
9030 +    case UBICOM32_OPERAND_D_IMM7_4 :
9031 +      errmsg = parse_imm7_4_d (cd, strp, UBICOM32_OPERAND_D_IMM7_4, (unsigned long *) (& fields->f_d_imm7_4));
9032 +      break;
9033 +    case UBICOM32_OPERAND_D_IMM8 :
9034 +      errmsg = parse_imm8 (cd, strp, UBICOM32_OPERAND_D_IMM8, (long *) (& fields->f_d_imm8));
9035 +      break;
9036 +    case UBICOM32_OPERAND_D_R :
9037 +      errmsg = cgen_parse_keyword (cd, strp, & ubicom32_cgen_opval_data_names, & fields->f_d_r);
9038 +      break;
9039 +    case UBICOM32_OPERAND_DSP_S2_ACC_REG_ADDSUB :
9040 +      errmsg = parse_acc_for_addsub (cd, strp, & ubicom32_cgen_opval_acc_names, & fields->f_dsp_S2);
9041 +      break;
9042 +    case UBICOM32_OPERAND_DSP_S2_ACC_REG_MUL :
9043 +      errmsg = cgen_parse_keyword (cd, strp, & ubicom32_cgen_opval_acc_names, & fields->f_dsp_S2);
9044 +      break;
9045 +    case UBICOM32_OPERAND_DSP_S2_DATA_REG :
9046 +      errmsg = cgen_parse_keyword (cd, strp, & ubicom32_cgen_opval_data_names, & fields->f_dsp_S2);
9047 +      break;
9048 +    case UBICOM32_OPERAND_DSP_S2_DATA_REG_ADDSUB :
9049 +      errmsg = parse_dr_for_addsub (cd, strp, & ubicom32_cgen_opval_data_names, & fields->f_dsp_S2);
9050 +      break;
9051 +    case UBICOM32_OPERAND_DSP_S2_SEL :
9052 +      errmsg = cgen_parse_unsigned_integer (cd, strp, UBICOM32_OPERAND_DSP_S2_SEL, (unsigned long *) (& fields->f_dsp_S2_sel));
9053 +      break;
9054 +    case UBICOM32_OPERAND_DSP_C :
9055 +      errmsg = cgen_parse_keyword (cd, strp, & ubicom32_cgen_opval_h_DSP_C, & fields->f_dsp_C);
9056 +      break;
9057 +    case UBICOM32_OPERAND_DSP_DESTA :
9058 +      errmsg = cgen_parse_keyword (cd, strp, & ubicom32_cgen_opval_h_DSP_Dest_A, & fields->f_dsp_destA);
9059 +      break;
9060 +    case UBICOM32_OPERAND_DSP_T :
9061 +      errmsg = cgen_parse_keyword (cd, strp, & ubicom32_cgen_opval_h_DSP_T, & fields->f_dsp_T);
9062 +      break;
9063 +    case UBICOM32_OPERAND_DSP_T_ADDSUB :
9064 +      errmsg = parse_t_is_set_for_addsub (cd, strp, & ubicom32_cgen_opval_h_DSP_T_addsub, & fields->f_dsp_T);
9065 +      break;
9066 +    case UBICOM32_OPERAND_IMM16_1 :
9067 +      errmsg = cgen_parse_signed_integer (cd, strp, UBICOM32_OPERAND_IMM16_1, (long *) (& fields->f_imm16_1));
9068 +      break;
9069 +    case UBICOM32_OPERAND_IMM16_2 :
9070 +      errmsg = parse_imm16 (cd, strp, UBICOM32_OPERAND_IMM16_2, (long *) (& fields->f_imm16_2));
9071 +      break;
9072 +    case UBICOM32_OPERAND_IMM24 :
9073 +      errmsg = parse_imm24 (cd, strp, UBICOM32_OPERAND_IMM24, (unsigned long *) (& fields->f_imm24));
9074 +      break;
9075 +    case UBICOM32_OPERAND_INTERRUPT :
9076 +      errmsg = cgen_parse_unsigned_integer (cd, strp, UBICOM32_OPERAND_INTERRUPT, (unsigned long *) (& fields->f_int));
9077 +      break;
9078 +    case UBICOM32_OPERAND_IREAD :
9079 +      errmsg = cgen_parse_unsigned_integer (cd, strp, UBICOM32_OPERAND_IREAD, (unsigned long *) (& junk));
9080 +      break;
9081 +    case UBICOM32_OPERAND_IRQ_0 :
9082 +      errmsg = cgen_parse_unsigned_integer (cd, strp, UBICOM32_OPERAND_IRQ_0, (unsigned long *) (& junk));
9083 +      break;
9084 +    case UBICOM32_OPERAND_IRQ_1 :
9085 +      errmsg = cgen_parse_unsigned_integer (cd, strp, UBICOM32_OPERAND_IRQ_1, (unsigned long *) (& junk));
9086 +      break;
9087 +    case UBICOM32_OPERAND_MACHI :
9088 +      errmsg = cgen_parse_unsigned_integer (cd, strp, UBICOM32_OPERAND_MACHI, (unsigned long *) (& junk));
9089 +      break;
9090 +    case UBICOM32_OPERAND_MACLO :
9091 +      errmsg = cgen_parse_unsigned_integer (cd, strp, UBICOM32_OPERAND_MACLO, (unsigned long *) (& junk));
9092 +      break;
9093 +    case UBICOM32_OPERAND_OFFSET16 :
9094 +      errmsg = parse_offset16 (cd, strp, UBICOM32_OPERAND_OFFSET16, (long *) (& fields->f_o16));
9095 +      break;
9096 +    case UBICOM32_OPERAND_OFFSET21 :
9097 +      {
9098 +        bfd_vma value = 0;
9099 +        errmsg = parse_offset21 (cd, strp, UBICOM32_OPERAND_OFFSET21, 0, NULL,  & value);
9100 +        fields->f_o21 = value;
9101 +      }
9102 +      break;
9103 +    case UBICOM32_OPERAND_OFFSET24 :
9104 +      {
9105 +        bfd_vma value = 0;
9106 +        errmsg = cgen_parse_address (cd, strp, UBICOM32_OPERAND_OFFSET24, 0, NULL,  & value);
9107 +        fields->f_o24 = value;
9108 +      }
9109 +      break;
9110 +    case UBICOM32_OPERAND_OPC1 :
9111 +      errmsg = cgen_parse_unsigned_integer (cd, strp, UBICOM32_OPERAND_OPC1, (unsigned long *) (& fields->f_op1));
9112 +      break;
9113 +    case UBICOM32_OPERAND_OPC2 :
9114 +      errmsg = cgen_parse_unsigned_integer (cd, strp, UBICOM32_OPERAND_OPC2, (unsigned long *) (& fields->f_op2));
9115 +      break;
9116 +    case UBICOM32_OPERAND_PDEC_S1_IMM7_4 :
9117 +      errmsg = parse_pdec_imm7_4_s (cd, strp, UBICOM32_OPERAND_PDEC_S1_IMM7_4, (unsigned long *) (& fields->f_s1_imm7_4));
9118 +      break;
9119 +    case UBICOM32_OPERAND_S1_AN :
9120 +      errmsg = cgen_parse_keyword (cd, strp, & ubicom32_cgen_opval_addr_names, & fields->f_s1_An);
9121 +      break;
9122 +    case UBICOM32_OPERAND_S1_DIRECT_ADDR :
9123 +      errmsg = parse_s1_direct_addr (cd, strp, UBICOM32_OPERAND_S1_DIRECT_ADDR, (unsigned long *) (& fields->f_s1_direct));
9124 +      break;
9125 +    case UBICOM32_OPERAND_S1_I4_1 :
9126 +      errmsg = parse_imm4_1 (cd, strp, UBICOM32_OPERAND_S1_I4_1, (long *) (& fields->f_s1_i4_1));
9127 +      break;
9128 +    case UBICOM32_OPERAND_S1_I4_2 :
9129 +      errmsg = parse_imm4_2 (cd, strp, UBICOM32_OPERAND_S1_I4_2, (long *) (& fields->f_s1_i4_2));
9130 +      break;
9131 +    case UBICOM32_OPERAND_S1_I4_4 :
9132 +      errmsg = parse_imm4_4 (cd, strp, UBICOM32_OPERAND_S1_I4_4, (long *) (& fields->f_s1_i4_4));
9133 +      break;
9134 +    case UBICOM32_OPERAND_S1_IMM7_1 :
9135 +      errmsg = parse_imm7_1_s (cd, strp, UBICOM32_OPERAND_S1_IMM7_1, (unsigned long *) (& fields->f_s1_imm7_1));
9136 +      break;
9137 +    case UBICOM32_OPERAND_S1_IMM7_2 :
9138 +      errmsg = parse_imm7_2_s (cd, strp, UBICOM32_OPERAND_S1_IMM7_2, (unsigned long *) (& fields->f_s1_imm7_2));
9139 +      break;
9140 +    case UBICOM32_OPERAND_S1_IMM7_4 :
9141 +      errmsg = parse_imm7_4_s (cd, strp, UBICOM32_OPERAND_S1_IMM7_4, (unsigned long *) (& fields->f_s1_imm7_4));
9142 +      break;
9143 +    case UBICOM32_OPERAND_S1_IMM8 :
9144 +      errmsg = parse_imm8 (cd, strp, UBICOM32_OPERAND_S1_IMM8, (long *) (& fields->f_s1_imm8));
9145 +      break;
9146 +    case UBICOM32_OPERAND_S1_R :
9147 +      errmsg = cgen_parse_keyword (cd, strp, & ubicom32_cgen_opval_data_names, & fields->f_s1_r);
9148 +      break;
9149 +    case UBICOM32_OPERAND_S2 :
9150 +      errmsg = cgen_parse_keyword (cd, strp, & ubicom32_cgen_opval_data_names, & fields->f_s2);
9151 +      break;
9152 +    case UBICOM32_OPERAND_SRC3 :
9153 +      errmsg = cgen_parse_unsigned_integer (cd, strp, UBICOM32_OPERAND_SRC3, (unsigned long *) (& junk));
9154 +      break;
9155 +    case UBICOM32_OPERAND_X_BIT26 :
9156 +      errmsg = cgen_parse_unsigned_integer (cd, strp, UBICOM32_OPERAND_X_BIT26, (unsigned long *) (& fields->f_bit26));
9157 +      break;
9158 +    case UBICOM32_OPERAND_X_D :
9159 +      errmsg = cgen_parse_unsigned_integer (cd, strp, UBICOM32_OPERAND_X_D, (unsigned long *) (& fields->f_d));
9160 +      break;
9161 +    case UBICOM32_OPERAND_X_DN :
9162 +      errmsg = cgen_parse_unsigned_integer (cd, strp, UBICOM32_OPERAND_X_DN, (unsigned long *) (& fields->f_Dn));
9163 +      break;
9164 +    case UBICOM32_OPERAND_X_OP2 :
9165 +      errmsg = cgen_parse_unsigned_integer (cd, strp, UBICOM32_OPERAND_X_OP2, (unsigned long *) (& fields->f_op2));
9166 +      break;
9167 +    case UBICOM32_OPERAND_X_S1 :
9168 +      errmsg = cgen_parse_unsigned_integer (cd, strp, UBICOM32_OPERAND_X_S1, (unsigned long *) (& fields->f_s1));
9169 +      break;
9170 +
9171 +    default :
9172 +      /* xgettext:c-format */
9173 +      fprintf (stderr, _("Unrecognized field %d while parsing.\n"), opindex);
9174 +      abort ();
9175 +  }
9176 +
9177 +  return errmsg;
9178 +}
9179 +
9180 +cgen_parse_fn * const ubicom32_cgen_parse_handlers[] = 
9181 +{
9182 +  parse_insn_normal,
9183 +};
9184 +
9185 +void
9186 +ubicom32_cgen_init_asm (CGEN_CPU_DESC cd)
9187 +{
9188 +  ubicom32_cgen_init_opcode_table (cd);
9189 +  ubicom32_cgen_init_ibld_table (cd);
9190 +  cd->parse_handlers = & ubicom32_cgen_parse_handlers[0];
9191 +  cd->parse_operand = ubicom32_cgen_parse_operand;
9192 +#ifdef CGEN_ASM_INIT_HOOK
9193 +CGEN_ASM_INIT_HOOK
9194 +#endif
9195 +}
9196 +
9197 +\f
9198 +
9199 +/* Regex construction routine.
9200 +
9201 +   This translates an opcode syntax string into a regex string,
9202 +   by replacing any non-character syntax element (such as an
9203 +   opcode) with the pattern '.*'
9204 +
9205 +   It then compiles the regex and stores it in the opcode, for
9206 +   later use by ubicom32_cgen_assemble_insn
9207 +
9208 +   Returns NULL for success, an error message for failure.  */
9209 +
9210 +char * 
9211 +ubicom32_cgen_build_insn_regex (CGEN_INSN *insn)
9212 +{  
9213 +  CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
9214 +  const char *mnem = CGEN_INSN_MNEMONIC (insn);
9215 +  char rxbuf[CGEN_MAX_RX_ELEMENTS];
9216 +  char *rx = rxbuf;
9217 +  const CGEN_SYNTAX_CHAR_TYPE *syn;
9218 +  int reg_err;
9219 +
9220 +  syn = CGEN_SYNTAX_STRING (CGEN_OPCODE_SYNTAX (opc));
9221 +
9222 +  /* Mnemonics come first in the syntax string.  */
9223 +  if (! CGEN_SYNTAX_MNEMONIC_P (* syn))
9224 +    return _("missing mnemonic in syntax string");
9225 +  ++syn;
9226 +
9227 +  /* Generate a case sensitive regular expression that emulates case
9228 +     insensitive matching in the "C" locale.  We cannot generate a case
9229 +     insensitive regular expression because in Turkish locales, 'i' and 'I'
9230 +     are not equal modulo case conversion.  */
9231 +
9232 +  /* Copy the literal mnemonic out of the insn.  */
9233 +  for (; *mnem; mnem++)
9234 +    {
9235 +      char c = *mnem;
9236 +
9237 +      if (ISALPHA (c))
9238 +       {
9239 +         *rx++ = '[';
9240 +         *rx++ = TOLOWER (c);
9241 +         *rx++ = TOUPPER (c);
9242 +         *rx++ = ']';
9243 +       }
9244 +      else
9245 +       *rx++ = c;
9246 +    }
9247 +
9248 +  /* Copy any remaining literals from the syntax string into the rx.  */
9249 +  for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn)
9250 +    {
9251 +      if (CGEN_SYNTAX_CHAR_P (* syn)) 
9252 +       {
9253 +         char c = CGEN_SYNTAX_CHAR (* syn);
9254 +
9255 +         switch (c) 
9256 +           {
9257 +             /* Escape any regex metacharacters in the syntax.  */
9258 +           case '.': case '[': case '\\': 
9259 +           case '*': case '^': case '$': 
9260 +
9261 +#ifdef CGEN_ESCAPE_EXTENDED_REGEX
9262 +           case '?': case '{': case '}': 
9263 +           case '(': case ')': case '*':
9264 +           case '|': case '+': case ']':
9265 +#endif
9266 +             *rx++ = '\\';
9267 +             *rx++ = c;
9268 +             break;
9269 +
9270 +           default:
9271 +             if (ISALPHA (c))
9272 +               {
9273 +                 *rx++ = '[';
9274 +                 *rx++ = TOLOWER (c);
9275 +                 *rx++ = TOUPPER (c);
9276 +                 *rx++ = ']';
9277 +               }
9278 +             else
9279 +               *rx++ = c;
9280 +             break;
9281 +           }
9282 +       }
9283 +      else
9284 +       {
9285 +         /* Replace non-syntax fields with globs.  */
9286 +         *rx++ = '.';
9287 +         *rx++ = '*';
9288 +       }
9289 +    }
9290 +
9291 +  /* Trailing whitespace ok.  */
9292 +  * rx++ = '['; 
9293 +  * rx++ = ' '; 
9294 +  * rx++ = '\t'; 
9295 +  * rx++ = ']'; 
9296 +  * rx++ = '*'; 
9297 +
9298 +  /* But anchor it after that.  */
9299 +  * rx++ = '$'; 
9300 +  * rx = '\0';
9301 +
9302 +  CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t));
9303 +  reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB);
9304 +
9305 +  if (reg_err == 0) 
9306 +    return NULL;
9307 +  else
9308 +    {
9309 +      static char msg[80];
9310 +
9311 +      regerror (reg_err, (regex_t *) CGEN_INSN_RX (insn), msg, 80);
9312 +      regfree ((regex_t *) CGEN_INSN_RX (insn));
9313 +      free (CGEN_INSN_RX (insn));
9314 +      (CGEN_INSN_RX (insn)) = NULL;
9315 +      return msg;
9316 +    }
9317 +}
9318 +
9319 +\f
9320 +/* Default insn parser.
9321 +
9322 +   The syntax string is scanned and operands are parsed and stored in FIELDS.
9323 +   Relocs are queued as we go via other callbacks.
9324 +
9325 +   ??? Note that this is currently an all-or-nothing parser.  If we fail to
9326 +   parse the instruction, we return 0 and the caller will start over from
9327 +   the beginning.  Backtracking will be necessary in parsing subexpressions,
9328 +   but that can be handled there.  Not handling backtracking here may get
9329 +   expensive in the case of the m68k.  Deal with later.
9330 +
9331 +   Returns NULL for success, an error message for failure.  */
9332 +
9333 +static const char *
9334 +parse_insn_normal (CGEN_CPU_DESC cd,
9335 +                  const CGEN_INSN *insn,
9336 +                  const char **strp,
9337 +                  CGEN_FIELDS *fields)
9338 +{
9339 +  /* ??? Runtime added insns not handled yet.  */
9340 +  const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
9341 +  const char *str = *strp;
9342 +  const char *errmsg;
9343 +  const char *p;
9344 +  const CGEN_SYNTAX_CHAR_TYPE * syn;
9345 +#ifdef CGEN_MNEMONIC_OPERANDS
9346 +  /* FIXME: wip */
9347 +  int past_opcode_p;
9348 +#endif
9349 +
9350 +  /* For now we assume the mnemonic is first (there are no leading operands).
9351 +     We can parse it without needing to set up operand parsing.
9352 +     GAS's input scrubber will ensure mnemonics are lowercase, but we may
9353 +     not be called from GAS.  */
9354 +  p = CGEN_INSN_MNEMONIC (insn);
9355 +  while (*p && TOLOWER (*p) == TOLOWER (*str))
9356 +    ++p, ++str;
9357 +
9358 +  if (* p)
9359 +    return _("unrecognized instruction");
9360 +
9361 +#ifndef CGEN_MNEMONIC_OPERANDS
9362 +  if (* str && ! ISSPACE (* str))
9363 +    return _("unrecognized instruction");
9364 +#endif
9365 +
9366 +  CGEN_INIT_PARSE (cd);
9367 +  cgen_init_parse_operand (cd);
9368 +#ifdef CGEN_MNEMONIC_OPERANDS
9369 +  past_opcode_p = 0;
9370 +#endif
9371 +
9372 +  /* We don't check for (*str != '\0') here because we want to parse
9373 +     any trailing fake arguments in the syntax string.  */
9374 +  syn = CGEN_SYNTAX_STRING (syntax);
9375 +
9376 +  /* Mnemonics come first for now, ensure valid string.  */
9377 +  if (! CGEN_SYNTAX_MNEMONIC_P (* syn))
9378 +    abort ();
9379 +
9380 +  ++syn;
9381 +
9382 +  while (* syn != 0)
9383 +    {
9384 +      /* Non operand chars must match exactly.  */
9385 +      if (CGEN_SYNTAX_CHAR_P (* syn))
9386 +       {
9387 +         /* FIXME: While we allow for non-GAS callers above, we assume the
9388 +            first char after the mnemonic part is a space.  */
9389 +         /* FIXME: We also take inappropriate advantage of the fact that
9390 +            GAS's input scrubber will remove extraneous blanks.  */
9391 +         if (TOLOWER (*str) == TOLOWER (CGEN_SYNTAX_CHAR (* syn)))
9392 +           {
9393 +#ifdef CGEN_MNEMONIC_OPERANDS
9394 +             if (CGEN_SYNTAX_CHAR(* syn) == ' ')
9395 +               past_opcode_p = 1;
9396 +#endif
9397 +             ++ syn;
9398 +             ++ str;
9399 +           }
9400 +         else if (*str)
9401 +           {
9402 +             /* Syntax char didn't match.  Can't be this insn.  */
9403 +             static char msg [80];
9404 +
9405 +             /* xgettext:c-format */
9406 +             sprintf (msg, _("syntax error (expected char `%c', found `%c')"),
9407 +                      CGEN_SYNTAX_CHAR(*syn), *str);
9408 +             return msg;
9409 +           }
9410 +         else
9411 +           {
9412 +             /* Ran out of input.  */
9413 +             static char msg [80];
9414 +
9415 +             /* xgettext:c-format */
9416 +             sprintf (msg, _("syntax error (expected char `%c', found end of instruction)"),
9417 +                      CGEN_SYNTAX_CHAR(*syn));
9418 +             return msg;
9419 +           }
9420 +         continue;
9421 +       }
9422 +
9423 +      /* We have an operand of some sort.  */
9424 +      errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn),
9425 +                                         &str, fields);
9426 +      if (errmsg)
9427 +       return errmsg;
9428 +
9429 +      /* Done with this operand, continue with next one.  */
9430 +      ++ syn;
9431 +    }
9432 +
9433 +  /* If we're at the end of the syntax string, we're done.  */
9434 +  if (* syn == 0)
9435 +    {
9436 +      /* FIXME: For the moment we assume a valid `str' can only contain
9437 +        blanks now.  IE: We needn't try again with a longer version of
9438 +        the insn and it is assumed that longer versions of insns appear
9439 +        before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3).  */
9440 +      while (ISSPACE (* str))
9441 +       ++ str;
9442 +
9443 +      if (* str != '\0')
9444 +       return _("junk at end of line"); /* FIXME: would like to include `str' */
9445 +
9446 +      return NULL;
9447 +    }
9448 +
9449 +  /* We couldn't parse it.  */
9450 +  return _("unrecognized instruction");
9451 +}
9452 +\f
9453 +/* Main entry point.
9454 +   This routine is called for each instruction to be assembled.
9455 +   STR points to the insn to be assembled.
9456 +   We assume all necessary tables have been initialized.
9457 +   The assembled instruction, less any fixups, is stored in BUF.
9458 +   Remember that if CGEN_INT_INSN_P then BUF is an int and thus the value
9459 +   still needs to be converted to target byte order, otherwise BUF is an array
9460 +   of bytes in target byte order.
9461 +   The result is a pointer to the insn's entry in the opcode table,
9462 +   or NULL if an error occured (an error message will have already been
9463 +   printed).
9464 +
9465 +   Note that when processing (non-alias) macro-insns,
9466 +   this function recurses.
9467 +
9468 +   ??? It's possible to make this cpu-independent.
9469 +   One would have to deal with a few minor things.
9470 +   At this point in time doing so would be more of a curiosity than useful
9471 +   [for example this file isn't _that_ big], but keeping the possibility in
9472 +   mind helps keep the design clean.  */
9473 +
9474 +const CGEN_INSN *
9475 +ubicom32_cgen_assemble_insn (CGEN_CPU_DESC cd,
9476 +                          const char *str,
9477 +                          CGEN_FIELDS *fields,
9478 +                          CGEN_INSN_BYTES_PTR buf,
9479 +                          char **errmsg)
9480 +{
9481 +  const char *start;
9482 +  CGEN_INSN_LIST *ilist;
9483 +  const char *parse_errmsg = NULL;
9484 +  const char *insert_errmsg = NULL;
9485 +  int recognized_mnemonic = 0;
9486 +
9487 +  /* Skip leading white space.  */
9488 +  while (ISSPACE (* str))
9489 +    ++ str;
9490 +
9491 +  /* The instructions are stored in hashed lists.
9492 +     Get the first in the list.  */
9493 +  ilist = CGEN_ASM_LOOKUP_INSN (cd, str);
9494 +
9495 +  /* Keep looking until we find a match.  */
9496 +  start = str;
9497 +  for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist))
9498 +    {
9499 +      const CGEN_INSN *insn = ilist->insn;
9500 +      recognized_mnemonic = 1;
9501 +
9502 +#ifdef CGEN_VALIDATE_INSN_SUPPORTED 
9503 +      /* Not usually needed as unsupported opcodes
9504 +        shouldn't be in the hash lists.  */
9505 +      /* Is this insn supported by the selected cpu?  */
9506 +      if (! ubicom32_cgen_insn_supported (cd, insn))
9507 +       continue;
9508 +#endif
9509 +      /* If the RELAXED attribute is set, this is an insn that shouldn't be
9510 +        chosen immediately.  Instead, it is used during assembler/linker
9511 +        relaxation if possible.  */
9512 +      if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0)
9513 +       continue;
9514 +
9515 +      str = start;
9516 +
9517 +      /* Skip this insn if str doesn't look right lexically.  */
9518 +      if (CGEN_INSN_RX (insn) != NULL &&
9519 +         regexec ((regex_t *) CGEN_INSN_RX (insn), str, 0, NULL, 0) == REG_NOMATCH)
9520 +       continue;
9521 +
9522 +      /* Allow parse/insert handlers to obtain length of insn.  */
9523 +      CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
9524 +
9525 +      parse_errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields);
9526 +      if (parse_errmsg != NULL)
9527 +       continue;
9528 +
9529 +      /* ??? 0 is passed for `pc'.  */
9530 +      insert_errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf,
9531 +                                                (bfd_vma) 0);
9532 +      if (insert_errmsg != NULL)
9533 +        continue;
9534 +
9535 +      /* It is up to the caller to actually output the insn and any
9536 +         queued relocs.  */
9537 +      return insn;
9538 +    }
9539 +
9540 +  {
9541 +    static char errbuf[150];
9542 +#ifdef CGEN_VERBOSE_ASSEMBLER_ERRORS
9543 +    const char *tmp_errmsg;
9544 +
9545 +    /* If requesting verbose error messages, use insert_errmsg.
9546 +       Failing that, use parse_errmsg.  */
9547 +    tmp_errmsg = (insert_errmsg ? insert_errmsg :
9548 +                 parse_errmsg ? parse_errmsg :
9549 +                 recognized_mnemonic ?
9550 +                 _("unrecognized form of instruction") :
9551 +                 _("unrecognized instruction"));
9552 +
9553 +    if (strlen (start) > 50)
9554 +      /* xgettext:c-format */
9555 +      sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start);
9556 +    else 
9557 +      /* xgettext:c-format */
9558 +      sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start);
9559 +#else
9560 +    if (strlen (start) > 50)
9561 +      /* xgettext:c-format */
9562 +      sprintf (errbuf, _("bad instruction `%.50s...'"), start);
9563 +    else 
9564 +      /* xgettext:c-format */
9565 +      sprintf (errbuf, _("bad instruction `%.50s'"), start);
9566 +#endif
9567 +      
9568 +    *errmsg = errbuf;
9569 +    return NULL;
9570 +  }
9571 +}
9572 --- /dev/null
9573 +++ b/opcodes/ubicom32-desc.c
9574 @@ -0,0 +1,15137 @@
9575 +/* CPU data for ubicom32.
9576 +
9577 +THIS FILE IS MACHINE GENERATED WITH CGEN.
9578 +
9579 +Copyright 1996-2007 Free Software Foundation, Inc.
9580 +
9581 +This file is part of the GNU Binutils and/or GDB, the GNU debugger.
9582 +
9583 +   This file is free software; you can redistribute it and/or modify
9584 +   it under the terms of the GNU General Public License as published by
9585 +   the Free Software Foundation; either version 3, or (at your option)
9586 +   any later version.
9587 +
9588 +   It is distributed in the hope that it will be useful, but WITHOUT
9589 +   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
9590 +   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
9591 +   License for more details.
9592 +
9593 +   You should have received a copy of the GNU General Public License along
9594 +   with this program; if not, write to the Free Software Foundation, Inc.,
9595 +   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
9596 +
9597 +*/
9598 +
9599 +#include "sysdep.h"
9600 +#include <stdio.h>
9601 +#include <stdarg.h>
9602 +#include "ansidecl.h"
9603 +#include "bfd.h"
9604 +#include "symcat.h"
9605 +#include "ubicom32-desc.h"
9606 +#include "ubicom32-opc.h"
9607 +#include "opintl.h"
9608 +#include "libiberty.h"
9609 +#include "xregex.h"
9610 +
9611 +/* Attributes.  */
9612 +
9613 +static const CGEN_ATTR_ENTRY bool_attr[] =
9614 +{
9615 +  { "#f", 0 },
9616 +  { "#t", 1 },
9617 +  { 0, 0 }
9618 +};
9619 +
9620 +static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
9621 +{
9622 +  { "base", MACH_BASE },
9623 +  { "ip3035", MACH_IP3035 },
9624 +  { "ubicom32dsp", MACH_UBICOM32DSP },
9625 +  { "ip3023compatibility", MACH_IP3023COMPATIBILITY },
9626 +  { "ubicom32_ver4", MACH_UBICOM32_VER4 },
9627 +  { "max", MACH_MAX },
9628 +  { 0, 0 }
9629 +};
9630 +
9631 +static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
9632 +{
9633 +  { "ubicom32", ISA_UBICOM32 },
9634 +  { "max", ISA_MAX },
9635 +  { 0, 0 }
9636 +};
9637 +
9638 +const CGEN_ATTR_TABLE ubicom32_cgen_ifield_attr_table[] =
9639 +{
9640 +  { "MACH", & MACH_attr[0], & MACH_attr[0] },
9641 +  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
9642 +  { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
9643 +  { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
9644 +  { "RESERVED", &bool_attr[0], &bool_attr[0] },
9645 +  { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
9646 +  { "SIGNED", &bool_attr[0], &bool_attr[0] },
9647 +  { 0, 0, 0 }
9648 +};
9649 +
9650 +const CGEN_ATTR_TABLE ubicom32_cgen_hardware_attr_table[] =
9651 +{
9652 +  { "MACH", & MACH_attr[0], & MACH_attr[0] },
9653 +  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
9654 +  { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
9655 +  { "PC", &bool_attr[0], &bool_attr[0] },
9656 +  { "PROFILE", &bool_attr[0], &bool_attr[0] },
9657 +  { 0, 0, 0 }
9658 +};
9659 +
9660 +const CGEN_ATTR_TABLE ubicom32_cgen_operand_attr_table[] =
9661 +{
9662 +  { "MACH", & MACH_attr[0], & MACH_attr[0] },
9663 +  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
9664 +  { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
9665 +  { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
9666 +  { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
9667 +  { "SIGNED", &bool_attr[0], &bool_attr[0] },
9668 +  { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
9669 +  { "RELAX", &bool_attr[0], &bool_attr[0] },
9670 +  { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
9671 +  { 0, 0, 0 }
9672 +};
9673 +
9674 +const CGEN_ATTR_TABLE ubicom32_cgen_insn_attr_table[] =
9675 +{
9676 +  { "MACH", & MACH_attr[0], & MACH_attr[0] },
9677 +  { "ALIAS", &bool_attr[0], &bool_attr[0] },
9678 +  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
9679 +  { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
9680 +  { "COND-CTI", &bool_attr[0], &bool_attr[0] },
9681 +  { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
9682 +  { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
9683 +  { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
9684 +  { "RELAXED", &bool_attr[0], &bool_attr[0] },
9685 +  { "NO-DIS", &bool_attr[0], &bool_attr[0] },
9686 +  { "PBB", &bool_attr[0], &bool_attr[0] },
9687 +  { 0, 0, 0 }
9688 +};
9689 +
9690 +/* Instruction set variants.  */
9691 +
9692 +static const CGEN_ISA ubicom32_cgen_isa_table[] = {
9693 +  { "ubicom32", 32, 32, 32, 32 },
9694 +  { 0, 0, 0, 0, 0 }
9695 +};
9696 +
9697 +/* Machine variants.  */
9698 +
9699 +static const CGEN_MACH ubicom32_cgen_mach_table[] = {
9700 +  { "ip3035", "ubicom32", MACH_IP3035, 0 },
9701 +  { "ubicom32dsp", "ubicom32dsp", MACH_UBICOM32DSP, 0 },
9702 +  { "ip3023compatibility", "ubicom32dsp", MACH_IP3023COMPATIBILITY, 0 },
9703 +  { "ubicom32_ver4", "ubicom32ver4", MACH_UBICOM32_VER4, 0 },
9704 +  { 0, 0, 0, 0 }
9705 +};
9706 +
9707 +static CGEN_KEYWORD_ENTRY ubicom32_cgen_opval_data_names_entries[] =
9708 +{
9709 +  { "d0", 0, {0, {{{0, 0}}}}, 0, 0 },
9710 +  { "d1", 1, {0, {{{0, 0}}}}, 0, 0 },
9711 +  { "d2", 2, {0, {{{0, 0}}}}, 0, 0 },
9712 +  { "d3", 3, {0, {{{0, 0}}}}, 0, 0 },
9713 +  { "d4", 4, {0, {{{0, 0}}}}, 0, 0 },
9714 +  { "d5", 5, {0, {{{0, 0}}}}, 0, 0 },
9715 +  { "d6", 6, {0, {{{0, 0}}}}, 0, 0 },
9716 +  { "d7", 7, {0, {{{0, 0}}}}, 0, 0 },
9717 +  { "d8", 8, {0, {{{0, 0}}}}, 0, 0 },
9718 +  { "d9", 9, {0, {{{0, 0}}}}, 0, 0 },
9719 +  { "d10", 10, {0, {{{0, 0}}}}, 0, 0 },
9720 +  { "d11", 11, {0, {{{0, 0}}}}, 0, 0 },
9721 +  { "d12", 12, {0, {{{0, 0}}}}, 0, 0 },
9722 +  { "d13", 13, {0, {{{0, 0}}}}, 0, 0 },
9723 +  { "d14", 14, {0, {{{0, 0}}}}, 0, 0 },
9724 +  { "d15", 15, {0, {{{0, 0}}}}, 0, 0 }
9725 +};
9726 +
9727 +CGEN_KEYWORD ubicom32_cgen_opval_data_names =
9728 +{
9729 +  & ubicom32_cgen_opval_data_names_entries[0],
9730 +  16,
9731 +  0, 0, 0, 0, ""
9732 +};
9733 +
9734 +static CGEN_KEYWORD_ENTRY ubicom32_cgen_opval_addr_names_entries[] =
9735 +{
9736 +  { "sp", 7, {0, {{{0, 0}}}}, 0, 0 },
9737 +  { "a0", 0, {0, {{{0, 0}}}}, 0, 0 },
9738 +  { "a1", 1, {0, {{{0, 0}}}}, 0, 0 },
9739 +  { "a2", 2, {0, {{{0, 0}}}}, 0, 0 },
9740 +  { "a3", 3, {0, {{{0, 0}}}}, 0, 0 },
9741 +  { "a4", 4, {0, {{{0, 0}}}}, 0, 0 },
9742 +  { "a5", 5, {0, {{{0, 0}}}}, 0, 0 },
9743 +  { "a6", 6, {0, {{{0, 0}}}}, 0, 0 },
9744 +  { "a7", 7, {0, {{{0, 0}}}}, 0, 0 }
9745 +};
9746 +
9747 +CGEN_KEYWORD ubicom32_cgen_opval_addr_names =
9748 +{
9749 +  & ubicom32_cgen_opval_addr_names_entries[0],
9750 +  9,
9751 +  0, 0, 0, 0, ""
9752 +};
9753 +
9754 +static CGEN_KEYWORD_ENTRY ubicom32_cgen_opval_acc_names_entries[] =
9755 +{
9756 +  { "acc0", 0, {0, {{{0, 0}}}}, 0, 0 },
9757 +  { "acc1", 1, {0, {{{0, 0}}}}, 0, 0 }
9758 +};
9759 +
9760 +CGEN_KEYWORD ubicom32_cgen_opval_acc_names =
9761 +{
9762 +  & ubicom32_cgen_opval_acc_names_entries[0],
9763 +  2,
9764 +  0, 0, 0, 0, ""
9765 +};
9766 +
9767 +static CGEN_KEYWORD_ENTRY ubicom32_cgen_opval_spad_names_entries[] =
9768 +{
9769 +  { "scratchpad0", 0, {0, {{{0, 0}}}}, 0, 0 },
9770 +  { "scratchpad1", 0, {0, {{{0, 0}}}}, 0, 0 },
9771 +  { "scratchpad2", 0, {0, {{{0, 0}}}}, 0, 0 },
9772 +  { "scratchpad3", 0, {0, {{{0, 0}}}}, 0, 0 }
9773 +};
9774 +
9775 +CGEN_KEYWORD ubicom32_cgen_opval_spad_names =
9776 +{
9777 +  & ubicom32_cgen_opval_spad_names_entries[0],
9778 +  4,
9779 +  0, 0, 0, 0, ""
9780 +};
9781 +
9782 +static CGEN_KEYWORD_ENTRY ubicom32_cgen_opval_h_cc_entries[] =
9783 +{
9784 +  { "f", 0, {0, {{{0, 0}}}}, 0, 0 },
9785 +  { "lo", 1, {0, {{{0, 0}}}}, 0, 0 },
9786 +  { "cc", 1, {0, {{{0, 0}}}}, 0, 0 },
9787 +  { "hs", 2, {0, {{{0, 0}}}}, 0, 0 },
9788 +  { "cs", 2, {0, {{{0, 0}}}}, 0, 0 },
9789 +  { "eq", 3, {0, {{{0, 0}}}}, 0, 0 },
9790 +  { "ge", 4, {0, {{{0, 0}}}}, 0, 0 },
9791 +  { "gt", 5, {0, {{{0, 0}}}}, 0, 0 },
9792 +  { "hi", 6, {0, {{{0, 0}}}}, 0, 0 },
9793 +  { "le", 7, {0, {{{0, 0}}}}, 0, 0 },
9794 +  { "ls", 8, {0, {{{0, 0}}}}, 0, 0 },
9795 +  { "lt", 9, {0, {{{0, 0}}}}, 0, 0 },
9796 +  { "mi", 10, {0, {{{0, 0}}}}, 0, 0 },
9797 +  { "ne", 11, {0, {{{0, 0}}}}, 0, 0 },
9798 +  { "pl", 12, {0, {{{0, 0}}}}, 0, 0 },
9799 +  { "t", 13, {0, {{{0, 0}}}}, 0, 0 },
9800 +  { "vc", 14, {0, {{{0, 0}}}}, 0, 0 },
9801 +  { "vs", 15, {0, {{{0, 0}}}}, 0, 0 }
9802 +};
9803 +
9804 +CGEN_KEYWORD ubicom32_cgen_opval_h_cc =
9805 +{
9806 +  & ubicom32_cgen_opval_h_cc_entries[0],
9807 +  18,
9808 +  0, 0, 0, 0, ""
9809 +};
9810 +
9811 +static CGEN_KEYWORD_ENTRY ubicom32_cgen_opval_h_C_entries[] =
9812 +{
9813 +  { "", 1, {0, {{{0, 0}}}}, 0, 0 },
9814 +  { ".s", 0, {0, {{{0, 0}}}}, 0, 0 },
9815 +  { ".w", 1, {0, {{{0, 0}}}}, 0, 0 }
9816 +};
9817 +
9818 +CGEN_KEYWORD ubicom32_cgen_opval_h_C =
9819 +{
9820 +  & ubicom32_cgen_opval_h_C_entries[0],
9821 +  3,
9822 +  0, 0, 0, 0, ""
9823 +};
9824 +
9825 +static CGEN_KEYWORD_ENTRY ubicom32_cgen_opval_h_P_entries[] =
9826 +{
9827 +  { ".t", 1, {0, {{{0, 0}}}}, 0, 0 },
9828 +  { ".f", 0, {0, {{{0, 0}}}}, 0, 0 },
9829 +  { "", 1, {0, {{{0, 0}}}}, 0, 0 }
9830 +};
9831 +
9832 +CGEN_KEYWORD ubicom32_cgen_opval_h_P =
9833 +{
9834 +  & ubicom32_cgen_opval_h_P_entries[0],
9835 +  3,
9836 +  0, 0, 0, 0, ""
9837 +};
9838 +
9839 +static CGEN_KEYWORD_ENTRY ubicom32_cgen_opval_h_DSP_C_entries[] =
9840 +{
9841 +  { ".c", 1, {0, {{{0, 0}}}}, 0, 0 },
9842 +  { "", 0, {0, {{{0, 0}}}}, 0, 0 }
9843 +};
9844 +
9845 +CGEN_KEYWORD ubicom32_cgen_opval_h_DSP_C =
9846 +{
9847 +  & ubicom32_cgen_opval_h_DSP_C_entries[0],
9848 +  2,
9849 +  0, 0, 0, 0, ""
9850 +};
9851 +
9852 +static CGEN_KEYWORD_ENTRY ubicom32_cgen_opval_h_DSP_Dest_A_entries[] =
9853 +{
9854 +  { "acc0", 0, {0, {{{0, 0}}}}, 0, 0 },
9855 +  { "acc1", 1, {0, {{{0, 0}}}}, 0, 0 }
9856 +};
9857 +
9858 +CGEN_KEYWORD ubicom32_cgen_opval_h_DSP_Dest_A =
9859 +{
9860 +  & ubicom32_cgen_opval_h_DSP_Dest_A_entries[0],
9861 +  2,
9862 +  0, 0, 0, 0, ""
9863 +};
9864 +
9865 +static CGEN_KEYWORD_ENTRY ubicom32_cgen_opval_h_DSP_T_entries[] =
9866 +{
9867 +  { "", 0, {0, {{{0, 0}}}}, 0, 0 },
9868 +  { ".t", 1, {0, {{{0, 0}}}}, 0, 0 }
9869 +};
9870 +
9871 +CGEN_KEYWORD ubicom32_cgen_opval_h_DSP_T =
9872 +{
9873 +  & ubicom32_cgen_opval_h_DSP_T_entries[0],
9874 +  2,
9875 +  0, 0, 0, 0, ""
9876 +};
9877 +
9878 +static CGEN_KEYWORD_ENTRY ubicom32_cgen_opval_h_DSP_T_addsub_entries[] =
9879 +{
9880 +  { "", 0, {0, {{{0, 0}}}}, 0, 0 },
9881 +  { ".t", 1, {0, {{{0, 0}}}}, 0, 0 }
9882 +};
9883 +
9884 +CGEN_KEYWORD ubicom32_cgen_opval_h_DSP_T_addsub =
9885 +{
9886 +  & ubicom32_cgen_opval_h_DSP_T_addsub_entries[0],
9887 +  2,
9888 +  0, 0, 0, 0, ""
9889 +};
9890 +
9891 +
9892 +/* The hardware table.  */
9893 +
9894 +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
9895 +#define A(a) (1 << CGEN_HW_##a)
9896 +#else
9897 +#define A(a) (1 << CGEN_HW_/**/a)
9898 +#endif
9899 +
9900 +const CGEN_HW_ENTRY ubicom32_cgen_hw_table[] =
9901 +{
9902 +  { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
9903 +  { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
9904 +  { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
9905 +  { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
9906 +  { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
9907 +  { "h-global-control", HW_H_GLOBAL_CONTROL, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
9908 +  { "h-mt-break", HW_H_MT_BREAK, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
9909 +  { "h-mt-active", HW_H_MT_ACTIVE, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
9910 +  { "h-mt-enable", HW_H_MT_ENABLE, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
9911 +  { "h-mt-priority", HW_H_MT_PRIORITY, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
9912 +  { "h-mt-schedule", HW_H_MT_SCHEDULE, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
9913 +  { "h-irq-status-0", HW_H_IRQ_STATUS_0, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
9914 +  { "h-irq-status-1", HW_H_IRQ_STATUS_1, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
9915 +  { "h-dr", HW_H_DR, CGEN_ASM_KEYWORD, (PTR) & ubicom32_cgen_opval_data_names, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
9916 +  { "h-s1-dr", HW_H_S1_DR, CGEN_ASM_KEYWORD, (PTR) & ubicom32_cgen_opval_data_names, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
9917 +  { "h-ar", HW_H_AR, CGEN_ASM_KEYWORD, (PTR) & ubicom32_cgen_opval_addr_names, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
9918 +  { "h-ar-inc", HW_H_AR_INC, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
9919 +  { "h-ar-inc-flag", HW_H_AR_INC_FLAG, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
9920 +  { "h-mac-hi", HW_H_MAC_HI, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
9921 +  { "h-mac-lo", HW_H_MAC_LO, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
9922 +  { "h-src-3", HW_H_SRC_3, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
9923 +  { "h-csr", HW_H_CSR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
9924 +  { "h-iread", HW_H_IREAD, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
9925 +  { "h-acc1-hi", HW_H_ACC1_HI, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } } },
9926 +  { "h-acc1-lo", HW_H_ACC1_LO, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } } },
9927 +  { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
9928 +  { "h-nbit-16", HW_H_NBIT_16, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
9929 +  { "h-zbit-16", HW_H_ZBIT_16, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
9930 +  { "h-vbit-16", HW_H_VBIT_16, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
9931 +  { "h-cbit-16", HW_H_CBIT_16, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
9932 +  { "h-nbit-32", HW_H_NBIT_32, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
9933 +  { "h-zbit-32", HW_H_ZBIT_32, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
9934 +  { "h-vbit-32", HW_H_VBIT_32, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
9935 +  { "h-cbit-32", HW_H_CBIT_32, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
9936 +  { "h-cc", HW_H_CC, CGEN_ASM_KEYWORD, (PTR) & ubicom32_cgen_opval_h_cc, { 0, { { { (1<<MACH_BASE), 0 } } } } },
9937 +  { "h-C", HW_H_C, CGEN_ASM_KEYWORD, (PTR) & ubicom32_cgen_opval_h_C, { 0, { { { (1<<MACH_BASE), 0 } } } } },
9938 +  { "h-P", HW_H_P, CGEN_ASM_KEYWORD, (PTR) & ubicom32_cgen_opval_h_P, { 0, { { { (1<<MACH_BASE), 0 } } } } },
9939 +  { "h-DSP-C", HW_H_DSP_C, CGEN_ASM_KEYWORD, (PTR) & ubicom32_cgen_opval_h_DSP_C, { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } } },
9940 +  { "h-DSP-Dest-A", HW_H_DSP_DEST_A, CGEN_ASM_KEYWORD, (PTR) & ubicom32_cgen_opval_h_DSP_Dest_A, { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } } },
9941 +  { "h-DSP-T", HW_H_DSP_T, CGEN_ASM_KEYWORD, (PTR) & ubicom32_cgen_opval_h_DSP_T, { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } } },
9942 +  { "h-DSP-T-addsub", HW_H_DSP_T_ADDSUB, CGEN_ASM_KEYWORD, (PTR) & ubicom32_cgen_opval_h_DSP_T_addsub, { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } } },
9943 +  { "h-DSP-S2-Acc-reg-mul", HW_H_DSP_S2_ACC_REG_MUL, CGEN_ASM_KEYWORD, (PTR) & ubicom32_cgen_opval_acc_names, { 0|A(VIRTUAL), { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } } },
9944 +  { "h-DSP-S2-Acc-reg-addsub", HW_H_DSP_S2_ACC_REG_ADDSUB, CGEN_ASM_KEYWORD, (PTR) & ubicom32_cgen_opval_acc_names, { 0|A(VIRTUAL), { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } } },
9945 +  { "h-sp", HW_H_SP, CGEN_ASM_KEYWORD, (PTR) & ubicom32_cgen_opval_spad_names, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
9946 +  { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
9947 +};
9948 +
9949 +#undef A
9950 +
9951 +
9952 +/* The instruction field table.  */
9953 +
9954 +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
9955 +#define A(a) (1 << CGEN_IFLD_##a)
9956 +#else
9957 +#define A(a) (1 << CGEN_IFLD_/**/a)
9958 +#endif
9959 +
9960 +const CGEN_IFLD ubicom32_cgen_ifld_table[] =
9961 +{
9962 +  { UBICOM32_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
9963 +  { UBICOM32_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
9964 +  { UBICOM32_F_D, "f-d", 0, 32, 26, 11, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
9965 +  { UBICOM32_F_D_BIT10, "f-d-bit10", 0, 32, 26, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
9966 +  { UBICOM32_F_D_TYPE, "f-d-type", 0, 32, 25, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
9967 +  { UBICOM32_F_D_R, "f-d-r", 0, 32, 20, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
9968 +  { UBICOM32_F_D_M, "f-d-M", 0, 32, 20, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
9969 +  { UBICOM32_F_D_I4_1, "f-d-i4-1", 0, 32, 19, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
9970 +  { UBICOM32_F_D_I4_2, "f-d-i4-2", 0, 32, 19, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
9971 +  { UBICOM32_F_D_I4_4, "f-d-i4-4", 0, 32, 19, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
9972 +  { UBICOM32_F_D_AN, "f-d-An", 0, 32, 23, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
9973 +  { UBICOM32_F_D_DIRECT, "f-d-direct", 0, 32, 23, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
9974 +  { UBICOM32_F_D_IMM8, "f-d-imm8", 0, 32, 23, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
9975 +  { UBICOM32_F_D_IMM7_T, "f-d-imm7-t", 0, 32, 25, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
9976 +  { UBICOM32_F_D_IMM7_B, "f-d-imm7-b", 0, 32, 20, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
9977 +  { UBICOM32_F_D_IMM7_1, "f-d-imm7-1", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
9978 +  { UBICOM32_F_D_IMM7_2, "f-d-imm7-2", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
9979 +  { UBICOM32_F_D_IMM7_4, "f-d-imm7-4", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
9980 +  { UBICOM32_F_S1, "f-s1", 0, 32, 10, 11, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
9981 +  { UBICOM32_F_S1_BIT10, "f-s1-bit10", 0, 32, 10, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
9982 +  { UBICOM32_F_S1_TYPE, "f-s1-type", 0, 32, 9, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
9983 +  { UBICOM32_F_S1_R, "f-s1-r", 0, 32, 4, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
9984 +  { UBICOM32_F_S1_M, "f-s1-M", 0, 32, 4, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
9985 +  { UBICOM32_F_S1_I4_1, "f-s1-i4-1", 0, 32, 3, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
9986 +  { UBICOM32_F_S1_I4_2, "f-s1-i4-2", 0, 32, 3, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
9987 +  { UBICOM32_F_S1_I4_4, "f-s1-i4-4", 0, 32, 3, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
9988 +  { UBICOM32_F_S1_AN, "f-s1-An", 0, 32, 7, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
9989 +  { UBICOM32_F_S1_DIRECT, "f-s1-direct", 0, 32, 7, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
9990 +  { UBICOM32_F_S1_IMM8, "f-s1-imm8", 0, 32, 7, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
9991 +  { UBICOM32_F_S1_IMM7_T, "f-s1-imm7-t", 0, 32, 9, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
9992 +  { UBICOM32_F_S1_IMM7_B, "f-s1-imm7-b", 0, 32, 4, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
9993 +  { UBICOM32_F_S1_IMM7_1, "f-s1-imm7-1", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
9994 +  { UBICOM32_F_S1_IMM7_2, "f-s1-imm7-2", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
9995 +  { UBICOM32_F_S1_IMM7_4, "f-s1-imm7-4", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
9996 +  { UBICOM32_F_OP1, "f-op1", 0, 32, 31, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
9997 +  { UBICOM32_F_OP2, "f-op2", 0, 32, 15, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
9998 +  { UBICOM32_F_BIT26, "f-bit26", 0, 32, 26, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
9999 +  { UBICOM32_F_OPEXT, "f-opext", 0, 32, 25, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
10000 +  { UBICOM32_F_COND, "f-cond", 0, 32, 26, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
10001 +  { UBICOM32_F_IMM16_1, "f-imm16-1", 0, 32, 26, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
10002 +  { UBICOM32_F_IMM16_2, "f-imm16-2", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
10003 +  { UBICOM32_F_O21, "f-o21", 0, 32, 20, 21, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
10004 +  { UBICOM32_F_O23_21, "f-o23-21", 0, 32, 26, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
10005 +  { UBICOM32_F_O20_0, "f-o20-0", 0, 32, 20, 21, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
10006 +  { UBICOM32_F_O24, "f-o24", 0, 0, 0, 0,{ 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
10007 +  { UBICOM32_F_IMM23_21, "f-imm23-21", 0, 32, 26, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
10008 +  { UBICOM32_F_IMM24, "f-imm24", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
10009 +  { UBICOM32_F_O15_13, "f-o15-13", 0, 32, 26, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
10010 +  { UBICOM32_F_O12_8, "f-o12-8", 0, 32, 20, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
10011 +  { UBICOM32_F_O7_5, "f-o7-5", 0, 32, 10, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
10012 +  { UBICOM32_F_O4_0, "f-o4-0", 0, 32, 4, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
10013 +  { UBICOM32_F_O16, "f-o16", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
10014 +  { UBICOM32_F_AN, "f-An", 0, 32, 23, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
10015 +  { UBICOM32_F_AM, "f-Am", 0, 32, 7, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
10016 +  { UBICOM32_F_DN, "f-Dn", 0, 32, 20, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
10017 +  { UBICOM32_F_BIT5, "f-bit5", 0, 32, 15, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
10018 +  { UBICOM32_F_P, "f-P", 0, 32, 22, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
10019 +  { UBICOM32_F_C, "f-C", 0, 32, 21, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
10020 +  { UBICOM32_F_INT, "f-int", 0, 32, 5, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
10021 +  { UBICOM32_F_DSP_C, "f-dsp-C", 0, 32, 20, 1, { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }  },
10022 +  { UBICOM32_F_DSP_T, "f-dsp-T", 0, 32, 19, 1, { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }  },
10023 +  { UBICOM32_F_DSP_S2_SEL, "f-dsp-S2-sel", 0, 32, 18, 1, { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }  },
10024 +  { UBICOM32_F_DSP_R, "f-dsp-R", 0, 32, 17, 1, { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }  },
10025 +  { UBICOM32_F_DSP_DESTA, "f-dsp-destA", 0, 32, 16, 1, { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }  },
10026 +  { UBICOM32_F_DSP_B15, "f-dsp-b15", 0, 32, 15, 1, { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }  },
10027 +  { UBICOM32_F_DSP_S2, "f-dsp-S2", 0, 32, 14, 4, { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }  },
10028 +  { UBICOM32_F_DSP_J, "f-dsp-J", 0, 32, 26, 1, { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }  },
10029 +  { UBICOM32_F_S2, "f-s2", 0, 32, 14, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
10030 +  { UBICOM32_F_B15, "f-b15", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
10031 +  { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
10032 +};
10033 +
10034 +#undef A
10035 +
10036 +
10037 +
10038 +/* multi ifield declarations */
10039 +
10040 +const CGEN_MAYBE_MULTI_IFLD UBICOM32_F_D_IMM7_1_MULTI_IFIELD [];
10041 +const CGEN_MAYBE_MULTI_IFLD UBICOM32_F_D_IMM7_2_MULTI_IFIELD [];
10042 +const CGEN_MAYBE_MULTI_IFLD UBICOM32_F_D_IMM7_4_MULTI_IFIELD [];
10043 +const CGEN_MAYBE_MULTI_IFLD UBICOM32_F_S1_IMM7_1_MULTI_IFIELD [];
10044 +const CGEN_MAYBE_MULTI_IFLD UBICOM32_F_S1_IMM7_2_MULTI_IFIELD [];
10045 +const CGEN_MAYBE_MULTI_IFLD UBICOM32_F_S1_IMM7_4_MULTI_IFIELD [];
10046 +const CGEN_MAYBE_MULTI_IFLD UBICOM32_F_O24_MULTI_IFIELD [];
10047 +const CGEN_MAYBE_MULTI_IFLD UBICOM32_F_IMM24_MULTI_IFIELD [];
10048 +const CGEN_MAYBE_MULTI_IFLD UBICOM32_F_O16_MULTI_IFIELD [];
10049 +
10050 +
10051 +/* multi ifield definitions */
10052 +
10053 +const CGEN_MAYBE_MULTI_IFLD UBICOM32_F_D_IMM7_1_MULTI_IFIELD [] =
10054 +{
10055 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_D_IMM7_T] } },
10056 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_D_IMM7_B] } },
10057 +    { 0, { (const PTR) 0 } }
10058 +};
10059 +const CGEN_MAYBE_MULTI_IFLD UBICOM32_F_D_IMM7_2_MULTI_IFIELD [] =
10060 +{
10061 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_D_IMM7_T] } },
10062 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_D_IMM7_B] } },
10063 +    { 0, { (const PTR) 0 } }
10064 +};
10065 +const CGEN_MAYBE_MULTI_IFLD UBICOM32_F_D_IMM7_4_MULTI_IFIELD [] =
10066 +{
10067 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_D_IMM7_T] } },
10068 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_D_IMM7_B] } },
10069 +    { 0, { (const PTR) 0 } }
10070 +};
10071 +const CGEN_MAYBE_MULTI_IFLD UBICOM32_F_S1_IMM7_1_MULTI_IFIELD [] =
10072 +{
10073 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_S1_IMM7_T] } },
10074 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_S1_IMM7_B] } },
10075 +    { 0, { (const PTR) 0 } }
10076 +};
10077 +const CGEN_MAYBE_MULTI_IFLD UBICOM32_F_S1_IMM7_2_MULTI_IFIELD [] =
10078 +{
10079 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_S1_IMM7_T] } },
10080 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_S1_IMM7_B] } },
10081 +    { 0, { (const PTR) 0 } }
10082 +};
10083 +const CGEN_MAYBE_MULTI_IFLD UBICOM32_F_S1_IMM7_4_MULTI_IFIELD [] =
10084 +{
10085 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_S1_IMM7_T] } },
10086 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_S1_IMM7_B] } },
10087 +    { 0, { (const PTR) 0 } }
10088 +};
10089 +const CGEN_MAYBE_MULTI_IFLD UBICOM32_F_O24_MULTI_IFIELD [] =
10090 +{
10091 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_O23_21] } },
10092 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_O20_0] } },
10093 +    { 0, { (const PTR) 0 } }
10094 +};
10095 +const CGEN_MAYBE_MULTI_IFLD UBICOM32_F_IMM24_MULTI_IFIELD [] =
10096 +{
10097 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_IMM23_21] } },
10098 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_O20_0] } },
10099 +    { 0, { (const PTR) 0 } }
10100 +};
10101 +const CGEN_MAYBE_MULTI_IFLD UBICOM32_F_O16_MULTI_IFIELD [] =
10102 +{
10103 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_O15_13] } },
10104 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_O12_8] } },
10105 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_O7_5] } },
10106 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_O4_0] } },
10107 +    { 0, { (const PTR) 0 } }
10108 +};
10109 +
10110 +/* The operand table.  */
10111 +
10112 +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
10113 +#define A(a) (1 << CGEN_OPERAND_##a)
10114 +#else
10115 +#define A(a) (1 << CGEN_OPERAND_/**/a)
10116 +#endif
10117 +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
10118 +#define OPERAND(op) UBICOM32_OPERAND_##op
10119 +#else
10120 +#define OPERAND(op) UBICOM32_OPERAND_/**/op
10121 +#endif
10122 +
10123 +const CGEN_OPERAND ubicom32_cgen_operand_table[] =
10124 +{
10125 +/* pc: program counter */
10126 +  { "pc", UBICOM32_OPERAND_PC, HW_H_PC, 0, 0,
10127 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_NIL] } }, 
10128 +    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
10129 +/* s2: s2 register for op3 */
10130 +  { "s2", UBICOM32_OPERAND_S2, HW_H_DR, 14, 4,
10131 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_S2] } }, 
10132 +    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
10133 +/* src3: src-3 register */
10134 +  { "src3", UBICOM32_OPERAND_SRC3, HW_H_SRC_3, 0, 0,
10135 +    { 0, { (const PTR) 0 } }, 
10136 +    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
10137 +/* offset24: 24-bit relative word offset */
10138 +  { "offset24", UBICOM32_OPERAND_OFFSET24, HW_H_IADDR, 20, 24,
10139 +    { 2, { (const PTR) &UBICOM32_F_O24_MULTI_IFIELD[0] } }, 
10140 +    { 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
10141 +/* An: An register for call */
10142 +  { "An", UBICOM32_OPERAND_AN, HW_H_AR, 23, 3,
10143 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_AN] } }, 
10144 +    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
10145 +/* cc: condition code */
10146 +  { "cc", UBICOM32_OPERAND_CC, HW_H_CC, 26, 4,
10147 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_COND] } }, 
10148 +    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
10149 +/* C: condition code select bits */
10150 +  { "C", UBICOM32_OPERAND_C, HW_H_C, 21, 1,
10151 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_C] } }, 
10152 +    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
10153 +/* P: prediction bit */
10154 +  { "P", UBICOM32_OPERAND_P, HW_H_P, 22, 1,
10155 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_P] } }, 
10156 +    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
10157 +/* Am: Am register for calli */
10158 +  { "Am", UBICOM32_OPERAND_AM, HW_H_AR, 7, 3,
10159 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_AM] } }, 
10160 +    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
10161 +/* Dn: Dn reg for mac/mulu/mulf */
10162 +  { "Dn", UBICOM32_OPERAND_DN, HW_H_DR, 20, 5,
10163 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_DN] } }, 
10164 +    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
10165 +/* interrupt: interrupt code */
10166 +  { "interrupt", UBICOM32_OPERAND_INTERRUPT, HW_H_UINT, 5, 6,
10167 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_INT] } }, 
10168 +    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
10169 +/* imm16-1: 16 bit immediate for cmpi */
10170 +  { "imm16-1", UBICOM32_OPERAND_IMM16_1, HW_H_SINT, 26, 16,
10171 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_IMM16_1] } }, 
10172 +    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
10173 +/* x-op2: ignored secondary opcode */
10174 +  { "x-op2", UBICOM32_OPERAND_X_OP2, HW_H_UINT, 15, 5,
10175 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_OP2] } }, 
10176 +    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
10177 +/* x-bit26: ignored bit 26 */
10178 +  { "x-bit26", UBICOM32_OPERAND_X_BIT26, HW_H_UINT, 26, 1,
10179 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_BIT26] } }, 
10180 +    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
10181 +/* x-s1: ignored s1 operand */
10182 +  { "x-s1", UBICOM32_OPERAND_X_S1, HW_H_UINT, 10, 11,
10183 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_S1] } }, 
10184 +    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
10185 +/* x-d: ignored d operand */
10186 +  { "x-d", UBICOM32_OPERAND_X_D, HW_H_UINT, 26, 11,
10187 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_D] } }, 
10188 +    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
10189 +/* x-dn: ignored dn operand */
10190 +  { "x-dn", UBICOM32_OPERAND_X_DN, HW_H_UINT, 20, 5,
10191 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_DN] } }, 
10192 +    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
10193 +/* machi: mac hi register */
10194 +  { "machi", UBICOM32_OPERAND_MACHI, HW_H_MAC_HI, 0, 0,
10195 +    { 0, { (const PTR) 0 } }, 
10196 +    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
10197 +/* maclo: mac lo register */
10198 +  { "maclo", UBICOM32_OPERAND_MACLO, HW_H_MAC_LO, 0, 0,
10199 +    { 0, { (const PTR) 0 } }, 
10200 +    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
10201 +/* acc1hi: acc1 hi register */
10202 +  { "acc1hi", UBICOM32_OPERAND_ACC1HI, HW_H_ACC1_HI, 0, 0,
10203 +    { 0, { (const PTR) 0 } }, 
10204 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }  },
10205 +/* acc1lo: acc1 lo register */
10206 +  { "acc1lo", UBICOM32_OPERAND_ACC1LO, HW_H_ACC1_LO, 0, 0,
10207 +    { 0, { (const PTR) 0 } }, 
10208 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }  },
10209 +/* irq-0: irq status register 0 */
10210 +  { "irq-0", UBICOM32_OPERAND_IRQ_0, HW_H_IRQ_STATUS_0, 0, 0,
10211 +    { 0, { (const PTR) 0 } }, 
10212 +    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
10213 +/* irq-1: irq status register 1 */
10214 +  { "irq-1", UBICOM32_OPERAND_IRQ_1, HW_H_IRQ_STATUS_1, 0, 0,
10215 +    { 0, { (const PTR) 0 } }, 
10216 +    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
10217 +/* iread: iread register */
10218 +  { "iread", UBICOM32_OPERAND_IREAD, HW_H_IREAD, 0, 0,
10219 +    { 0, { (const PTR) 0 } }, 
10220 +    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
10221 +/* opc1: primary opcode */
10222 +  { "opc1", UBICOM32_OPERAND_OPC1, HW_H_UINT, 31, 5,
10223 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_OP1] } }, 
10224 +    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
10225 +/* opc2: secondary opcode */
10226 +  { "opc2", UBICOM32_OPERAND_OPC2, HW_H_UINT, 15, 5,
10227 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_OP2] } }, 
10228 +    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
10229 +/* An-inc: An pre/post inc flag */
10230 +  { "An-inc", UBICOM32_OPERAND_AN_INC, HW_H_AR_INC_FLAG, 0, 0,
10231 +    { 0, { (const PTR) 0 } }, 
10232 +    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
10233 +/* dsp-c: DSP Clip bit */
10234 +  { "dsp-c", UBICOM32_OPERAND_DSP_C, HW_H_DSP_C, 20, 1,
10235 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_DSP_C] } }, 
10236 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }  },
10237 +/* dsp-t: DSP Top Half bit */
10238 +  { "dsp-t", UBICOM32_OPERAND_DSP_T, HW_H_DSP_T, 19, 1,
10239 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_DSP_T] } }, 
10240 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }  },
10241 +/* dsp-destA: DSP Destination Acc Sel */
10242 +  { "dsp-destA", UBICOM32_OPERAND_DSP_DESTA, HW_H_DSP_DEST_A, 16, 1,
10243 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_DSP_DESTA] } }, 
10244 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }  },
10245 +/* dsp-S2-sel: DSP S2 reg Select */
10246 +  { "dsp-S2-sel", UBICOM32_OPERAND_DSP_S2_SEL, HW_H_UINT, 18, 1,
10247 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_DSP_S2_SEL] } }, 
10248 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }  },
10249 +/* dsp-S2-data-reg: DSP S2 is a data reg  */
10250 +  { "dsp-S2-data-reg", UBICOM32_OPERAND_DSP_S2_DATA_REG, HW_H_DR, 14, 4,
10251 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_DSP_S2] } }, 
10252 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }  },
10253 +/* dsp-S2-acc-reg-mul: DSP S2 reg is a  Acc Lo reg */
10254 +  { "dsp-S2-acc-reg-mul", UBICOM32_OPERAND_DSP_S2_ACC_REG_MUL, HW_H_DSP_S2_ACC_REG_MUL, 14, 4,
10255 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_DSP_S2] } }, 
10256 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }  },
10257 +/* dsp-S2-acc-reg-addsub: DSP S2 reg is a  Acc reg for madd and msuub */
10258 +  { "dsp-S2-acc-reg-addsub", UBICOM32_OPERAND_DSP_S2_ACC_REG_ADDSUB, HW_H_DSP_S2_ACC_REG_ADDSUB, 14, 4,
10259 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_DSP_S2] } }, 
10260 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }  },
10261 +/* dsp-S2-data-reg-addsub: DSP S2 reg is a data reg for madd and msuub */
10262 +  { "dsp-S2-data-reg-addsub", UBICOM32_OPERAND_DSP_S2_DATA_REG_ADDSUB, HW_H_DR, 14, 4,
10263 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_DSP_S2] } }, 
10264 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }  },
10265 +/* dsp-t-addsub: DSP Top Half spec for madd.2 and msub.2 */
10266 +  { "dsp-t-addsub", UBICOM32_OPERAND_DSP_T_ADDSUB, HW_H_DSP_T_ADDSUB, 19, 1,
10267 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_DSP_T] } }, 
10268 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }  },
10269 +/* bit5: immediate bit index */
10270 +  { "bit5", UBICOM32_OPERAND_BIT5, HW_H_UINT, 15, 5,
10271 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_BIT5] } }, 
10272 +    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
10273 +/* bit5-addsub: immediate bit index */
10274 +  { "bit5-addsub", UBICOM32_OPERAND_BIT5_ADDSUB, HW_H_UINT, 15, 5,
10275 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_BIT5] } }, 
10276 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }  },
10277 +/* dsp-src2-reg-acc-reg-mul:  */
10278 +/* dsp-src2-reg-acc-reg-addsub:  */
10279 +/* dsp-src2-data-reg:  */
10280 +/* dsp-src2-data-reg-addsub:  */
10281 +/* dsp-src2-data-reg-addsub2:  */
10282 +/* dsp-imm-bit5:  */
10283 +/* dsp-imm-bit5-addsub:  */
10284 +/* dsp-imm-bit5-addsub2:  */
10285 +/* imm-bit5:  */
10286 +/* dyn-reg:  */
10287 +/* op3: 5-bit immediate value or dynamic register specification */
10288 +/* dsp-src2-mul: Data register or accumulator lo register specification */
10289 +/* dsp-compatibility-src2-mul: Data register or accumulator lo register specification */
10290 +/* dsp-src2-addsub: Data register or accumulator register specification for madd msub instructions */
10291 +/* dsp-src2-addsub2: Data register or accumulator register specification for madd msub instructions */
10292 +/* offset21: 21-bit relative offset */
10293 +  { "offset21", UBICOM32_OPERAND_OFFSET21, HW_H_IADDR, 20, 21,
10294 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_O21] } }, 
10295 +    { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
10296 +/* offset16: 16-bit calli offset */
10297 +  { "offset16", UBICOM32_OPERAND_OFFSET16, HW_H_SINT, 4, 16,
10298 +    { 4, { (const PTR) &UBICOM32_F_O16_MULTI_IFIELD[0] } }, 
10299 +    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
10300 +/* imm24: 24-bit immediate */
10301 +  { "imm24", UBICOM32_OPERAND_IMM24, HW_H_UINT, 20, 24,
10302 +    { 2, { (const PTR) &UBICOM32_F_IMM24_MULTI_IFIELD[0] } }, 
10303 +    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
10304 +/* nbit-16: 16-bit negative    bit */
10305 +  { "nbit-16", UBICOM32_OPERAND_NBIT_16, HW_H_NBIT_16, 0, 0,
10306 +    { 0, { (const PTR) 0 } }, 
10307 +    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
10308 +/* vbit-16: 16-bit overflow    bit */
10309 +  { "vbit-16", UBICOM32_OPERAND_VBIT_16, HW_H_VBIT_16, 0, 0,
10310 +    { 0, { (const PTR) 0 } }, 
10311 +    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
10312 +/* zbit-16: 16-bit zero        bit */
10313 +  { "zbit-16", UBICOM32_OPERAND_ZBIT_16, HW_H_ZBIT_16, 0, 0,
10314 +    { 0, { (const PTR) 0 } }, 
10315 +    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
10316 +/* cbit-16: 16-bit carry       bit */
10317 +  { "cbit-16", UBICOM32_OPERAND_CBIT_16, HW_H_CBIT_16, 0, 0,
10318 +    { 0, { (const PTR) 0 } }, 
10319 +    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
10320 +/* nbit-32: 32-bit negative    bit */
10321 +  { "nbit-32", UBICOM32_OPERAND_NBIT_32, HW_H_NBIT_32, 0, 0,
10322 +    { 0, { (const PTR) 0 } }, 
10323 +    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
10324 +/* vbit-32: 32-bit overflow    bit */
10325 +  { "vbit-32", UBICOM32_OPERAND_VBIT_32, HW_H_VBIT_32, 0, 0,
10326 +    { 0, { (const PTR) 0 } }, 
10327 +    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
10328 +/* zbit-32: 32-bit zero        bit */
10329 +  { "zbit-32", UBICOM32_OPERAND_ZBIT_32, HW_H_ZBIT_32, 0, 0,
10330 +    { 0, { (const PTR) 0 } }, 
10331 +    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
10332 +/* cbit-32: 32-bit carry       bit */
10333 +  { "cbit-32", UBICOM32_OPERAND_CBIT_32, HW_H_CBIT_32, 0, 0,
10334 +    { 0, { (const PTR) 0 } }, 
10335 +    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
10336 +/* s1-imm7-1: 7-bit immediate byte */
10337 +  { "s1-imm7-1", UBICOM32_OPERAND_S1_IMM7_1, HW_H_UINT, 4, 7,
10338 +    { 2, { (const PTR) &UBICOM32_F_S1_IMM7_1_MULTI_IFIELD[0] } }, 
10339 +    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
10340 +/* s1-imm7-2: 7-bit immediate halfword */
10341 +  { "s1-imm7-2", UBICOM32_OPERAND_S1_IMM7_2, HW_H_UINT, 4, 7,
10342 +    { 2, { (const PTR) &UBICOM32_F_S1_IMM7_2_MULTI_IFIELD[0] } }, 
10343 +    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
10344 +/* s1-imm7-4: 7-bit immediate word */
10345 +  { "s1-imm7-4", UBICOM32_OPERAND_S1_IMM7_4, HW_H_UINT, 4, 7,
10346 +    { 2, { (const PTR) &UBICOM32_F_S1_IMM7_4_MULTI_IFIELD[0] } }, 
10347 +    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
10348 +/* pdec-s1-imm7-4: 7-bit immediate word for pdec */
10349 +  { "pdec-s1-imm7-4", UBICOM32_OPERAND_PDEC_S1_IMM7_4, HW_H_UINT, 4, 7,
10350 +    { 2, { (const PTR) &UBICOM32_F_S1_IMM7_4_MULTI_IFIELD[0] } }, 
10351 +    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
10352 +/* s1-imm8: 8-bit signed immediate */
10353 +  { "s1-imm8", UBICOM32_OPERAND_S1_IMM8, HW_H_SINT, 7, 8,
10354 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_S1_IMM8] } }, 
10355 +    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
10356 +/* s1-An: s1 address register */
10357 +  { "s1-An", UBICOM32_OPERAND_S1_AN, HW_H_AR, 7, 3,
10358 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_S1_AN] } }, 
10359 +    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
10360 +/* s1-r: s1 index register */
10361 +  { "s1-r", UBICOM32_OPERAND_S1_R, HW_H_S1_DR, 4, 5,
10362 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_S1_R] } }, 
10363 +    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
10364 +/* s1-An-inc: s1 An register pre/post inc */
10365 +  { "s1-An-inc", UBICOM32_OPERAND_S1_AN_INC, HW_H_AR_INC, 7, 3,
10366 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_S1_AN] } }, 
10367 +    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
10368 +/* s1-i4-1: 4 bit signed-immediate value */
10369 +  { "s1-i4-1", UBICOM32_OPERAND_S1_I4_1, HW_H_SINT, 3, 4,
10370 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_S1_I4_1] } }, 
10371 +    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
10372 +/* s1-i4-2: 4 bit signed-immediate value */
10373 +  { "s1-i4-2", UBICOM32_OPERAND_S1_I4_2, HW_H_SINT, 3, 4,
10374 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_S1_I4_2] } }, 
10375 +    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
10376 +/* s1-i4-4: 4 bit signed-immediate value */
10377 +  { "s1-i4-4", UBICOM32_OPERAND_S1_I4_4, HW_H_SINT, 3, 4,
10378 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_S1_I4_4] } }, 
10379 +    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
10380 +/* s1-indirect-1:  */
10381 +/* s1-indirect-2:  */
10382 +/* s1-indirect-4:  */
10383 +/* s1-indirect-with-offset-1:  */
10384 +/* s1-indirect-with-offset-2:  */
10385 +/* s1-indirect-with-offset-4:  */
10386 +/* s1-indirect-with-index-1:  */
10387 +/* s1-indirect-with-index-2:  */
10388 +/* s1-indirect-with-index-4:  */
10389 +/* s1-indirect-with-post-increment-1:  */
10390 +/* s1-indirect-with-post-increment-2:  */
10391 +/* s1-indirect-with-post-increment-4:  */
10392 +/* s1-indirect-with-pre-increment-1:  */
10393 +/* s1-indirect-with-pre-increment-2:  */
10394 +/* s1-indirect-with-pre-increment-4:  */
10395 +/* s1-direct-addr: s1 direct address */
10396 +  { "s1-direct-addr", UBICOM32_OPERAND_S1_DIRECT_ADDR, HW_H_UINT, 7, 8,
10397 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_S1_DIRECT] } }, 
10398 +    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
10399 +/* s1-direct:  */
10400 +/* s1-immediate:  */
10401 +/* s1-1: source 1 operand 1 */
10402 +/* s1-2: source 1 operand 2 */
10403 +/* s1-4: source 1 operand 4 */
10404 +/* s1-ea-indirect:  */
10405 +/* s1-ea-indirect-with-offset-1:  */
10406 +/* s1-ea-indirect-with-offset-2:  */
10407 +/* s1-ea-indirect-with-offset-4:  */
10408 +/* s1-ea-indirect-with-index-1:  */
10409 +/* s1-ea-indirect-with-index-2:  */
10410 +/* s1-ea-indirect-with-index-4:  */
10411 +/* s1-ea-indirect-with-post-increment-1:  */
10412 +/* s1-ea-indirect-with-post-increment-2:  */
10413 +/* s1-ea-indirect-with-post-increment-4:  */
10414 +/* s1-ea-indirect-with-pre-increment-1:  */
10415 +/* s1-ea-indirect-with-pre-increment-2:  */
10416 +/* s1-ea-indirect-with-pre-increment-4:  */
10417 +/* s1-ea-immediate:  */
10418 +/* s1-ea-direct:  */
10419 +/* s1-ea-1: source 1 ea operand */
10420 +/* s1-ea-2: source 1 ea operand */
10421 +/* s1-ea-4: source 1 ea operand */
10422 +/* s1-pea: source 1 pea operand */
10423 +/* pdec-s1-ea-indirect-with-offset-4:  */
10424 +/* pdec-pea-s1: source 1 pea operand for pdec instruction */
10425 +/* d-imm7-1: 7-bit immediate byte */
10426 +  { "d-imm7-1", UBICOM32_OPERAND_D_IMM7_1, HW_H_UINT, 20, 7,
10427 +    { 2, { (const PTR) &UBICOM32_F_D_IMM7_1_MULTI_IFIELD[0] } }, 
10428 +    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
10429 +/* d-imm7-2: 7-bit immediate halfword */
10430 +  { "d-imm7-2", UBICOM32_OPERAND_D_IMM7_2, HW_H_UINT, 20, 7,
10431 +    { 2, { (const PTR) &UBICOM32_F_D_IMM7_2_MULTI_IFIELD[0] } }, 
10432 +    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
10433 +/* d-imm7-4: 7-bit immediate word */
10434 +  { "d-imm7-4", UBICOM32_OPERAND_D_IMM7_4, HW_H_UINT, 20, 7,
10435 +    { 2, { (const PTR) &UBICOM32_F_D_IMM7_4_MULTI_IFIELD[0] } }, 
10436 +    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
10437 +/* d-imm8: 8-bit signed immediate */
10438 +  { "d-imm8", UBICOM32_OPERAND_D_IMM8, HW_H_SINT, 23, 8,
10439 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_D_IMM8] } }, 
10440 +    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
10441 +/* d-An: d address register */
10442 +  { "d-An", UBICOM32_OPERAND_D_AN, HW_H_AR, 23, 3,
10443 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_D_AN] } }, 
10444 +    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
10445 +/* d-r: d index register */
10446 +  { "d-r", UBICOM32_OPERAND_D_R, HW_H_DR, 20, 5,
10447 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_D_R] } }, 
10448 +    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
10449 +/* d-An-inc: d An register pre/post inc */
10450 +  { "d-An-inc", UBICOM32_OPERAND_D_AN_INC, HW_H_AR_INC, 23, 3,
10451 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_D_AN] } }, 
10452 +    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
10453 +/* d-i4-1: 4 bit signed-immediate value */
10454 +  { "d-i4-1", UBICOM32_OPERAND_D_I4_1, HW_H_SINT, 19, 4,
10455 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_D_I4_1] } }, 
10456 +    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
10457 +/* d-i4-2: 4 bit signed-immediate value */
10458 +  { "d-i4-2", UBICOM32_OPERAND_D_I4_2, HW_H_SINT, 19, 4,
10459 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_D_I4_2] } }, 
10460 +    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
10461 +/* d-i4-4: 4 bit signed-immediate value */
10462 +  { "d-i4-4", UBICOM32_OPERAND_D_I4_4, HW_H_SINT, 19, 4,
10463 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_D_I4_4] } }, 
10464 +    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
10465 +/* d-indirect-1:  */
10466 +/* d-indirect-2:  */
10467 +/* d-indirect-4:  */
10468 +/* d-indirect-with-offset-1:  */
10469 +/* d-indirect-with-offset-2:  */
10470 +/* d-indirect-with-offset-4:  */
10471 +/* d-indirect-with-index-1:  */
10472 +/* d-indirect-with-index-2:  */
10473 +/* d-indirect-with-index-4:  */
10474 +/* d-indirect-with-post-increment-1:  */
10475 +/* d-indirect-with-post-increment-2:  */
10476 +/* d-indirect-with-post-increment-4:  */
10477 +/* d-indirect-with-pre-increment-1:  */
10478 +/* d-indirect-with-pre-increment-2:  */
10479 +/* d-indirect-with-pre-increment-4:  */
10480 +/* d-direct-addr: dest direct address */
10481 +  { "d-direct-addr", UBICOM32_OPERAND_D_DIRECT_ADDR, HW_H_UINT, 23, 8,
10482 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_D_DIRECT] } }, 
10483 +    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
10484 +/* d-direct:  */
10485 +/* d-immediate-1:  */
10486 +/* d-immediate-2:  */
10487 +/* d-immediate-4:  */
10488 +/* d-1: destination operand 1 */
10489 +/* d-2: destination operand 2 */
10490 +/* d-4: destination operand 4 */
10491 +/* d-pea-indirect:  */
10492 +/* d-pea-indirect-with-offset:  */
10493 +/* d-pea-indirect-with-post-increment:  */
10494 +/* d-pea-indirect-with-pre-increment:  */
10495 +/* d-pea-indirect-with-index:  */
10496 +/* d-pea: destination 1 pea operand */
10497 +/* imm16-2: 16 bit immediate, for movei */
10498 +  { "imm16-2", UBICOM32_OPERAND_IMM16_2, HW_H_SINT, 15, 16,
10499 +    { 0, { (const PTR) &ubicom32_cgen_ifld_table[UBICOM32_F_IMM16_2] } }, 
10500 +    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
10501 +/* sentinel */
10502 +  { 0, 0, 0, 0, 0,
10503 +    { 0, { (const PTR) 0 } },
10504 +    { 0, { { { (1<<MACH_BASE), 0 } } } } }
10505 +};
10506 +
10507 +#undef A
10508 +
10509 +
10510 +/* The instruction table.  */
10511 +
10512 +#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
10513 +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
10514 +#define A(a) (1 << CGEN_INSN_##a)
10515 +#else
10516 +#define A(a) (1 << CGEN_INSN_/**/a)
10517 +#endif
10518 +
10519 +static const CGEN_IBASE ubicom32_cgen_insn_table[MAX_INSNS] =
10520 +{
10521 +  /* Special null first entry.
10522 +     A `num' value of zero is thus invalid.
10523 +     Also, the special `invalid' insn resides here.  */
10524 +  { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
10525 +/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},${s1-direct-addr},${dsp-S2-data-reg-addsub} */
10526 +  {
10527 +    UBICOM32_INSN_DSP_MSUB_2_S1_DIRECT_DSP_SRC2_DATA_REG_ADDSUB2, "dsp-msub.2-s1-direct-dsp-src2-data-reg-addsub2", "msub.2", 32,
10528 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10529 +  },
10530 +/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},#${s1-imm8},${dsp-S2-data-reg-addsub} */
10531 +  {
10532 +    UBICOM32_INSN_DSP_MSUB_2_S1_IMMEDIATE_DSP_SRC2_DATA_REG_ADDSUB2, "dsp-msub.2-s1-immediate-dsp-src2-data-reg-addsub2", "msub.2", 32,
10533 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10534 +  },
10535 +/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-data-reg-addsub} */
10536 +  {
10537 +    UBICOM32_INSN_DSP_MSUB_2_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_DATA_REG_ADDSUB2, "dsp-msub.2-s1-indirect-with-index-2-dsp-src2-data-reg-addsub2", "msub.2", 32,
10538 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10539 +  },
10540 +/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},${s1-imm7-2}(${s1-An}),${dsp-S2-data-reg-addsub} */
10541 +  {
10542 +    UBICOM32_INSN_DSP_MSUB_2_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_DATA_REG_ADDSUB2, "dsp-msub.2-s1-indirect-with-offset-2-dsp-src2-data-reg-addsub2", "msub.2", 32,
10543 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10544 +  },
10545 +/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},(${s1-An}),${dsp-S2-data-reg-addsub} */
10546 +  {
10547 +    UBICOM32_INSN_DSP_MSUB_2_S1_INDIRECT_2_DSP_SRC2_DATA_REG_ADDSUB2, "dsp-msub.2-s1-indirect-2-dsp-src2-data-reg-addsub2", "msub.2", 32,
10548 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10549 +  },
10550 +/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},(${s1-An})${s1-i4-2}++,${dsp-S2-data-reg-addsub} */
10551 +  {
10552 +    UBICOM32_INSN_DSP_MSUB_2_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_DATA_REG_ADDSUB2, "dsp-msub.2-s1-indirect-with-post-increment-2-dsp-src2-data-reg-addsub2", "msub.2", 32,
10553 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10554 +  },
10555 +/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},${s1-i4-2}(${s1-An})++,${dsp-S2-data-reg-addsub} */
10556 +  {
10557 +    UBICOM32_INSN_DSP_MSUB_2_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_DATA_REG_ADDSUB2, "dsp-msub.2-s1-indirect-with-pre-increment-2-dsp-src2-data-reg-addsub2", "msub.2", 32,
10558 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10559 +  },
10560 +/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},${s1-direct-addr},${dsp-S2-acc-reg-addsub} */
10561 +  {
10562 +    UBICOM32_INSN_DSP_MSUB_2_S1_DIRECT_DSP_SRC2_REG_ACC_REG_ADDSUB, "dsp-msub.2-s1-direct-dsp-src2-reg-acc-reg-addsub", "msub.2", 32,
10563 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10564 +  },
10565 +/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},#${s1-imm8},${dsp-S2-acc-reg-addsub} */
10566 +  {
10567 +    UBICOM32_INSN_DSP_MSUB_2_S1_IMMEDIATE_DSP_SRC2_REG_ACC_REG_ADDSUB, "dsp-msub.2-s1-immediate-dsp-src2-reg-acc-reg-addsub", "msub.2", 32,
10568 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10569 +  },
10570 +/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-acc-reg-addsub} */
10571 +  {
10572 +    UBICOM32_INSN_DSP_MSUB_2_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_REG_ACC_REG_ADDSUB, "dsp-msub.2-s1-indirect-with-index-2-dsp-src2-reg-acc-reg-addsub", "msub.2", 32,
10573 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10574 +  },
10575 +/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},${s1-imm7-2}(${s1-An}),${dsp-S2-acc-reg-addsub} */
10576 +  {
10577 +    UBICOM32_INSN_DSP_MSUB_2_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_REG_ACC_REG_ADDSUB, "dsp-msub.2-s1-indirect-with-offset-2-dsp-src2-reg-acc-reg-addsub", "msub.2", 32,
10578 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10579 +  },
10580 +/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},(${s1-An}),${dsp-S2-acc-reg-addsub} */
10581 +  {
10582 +    UBICOM32_INSN_DSP_MSUB_2_S1_INDIRECT_2_DSP_SRC2_REG_ACC_REG_ADDSUB, "dsp-msub.2-s1-indirect-2-dsp-src2-reg-acc-reg-addsub", "msub.2", 32,
10583 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10584 +  },
10585 +/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},(${s1-An})${s1-i4-2}++,${dsp-S2-acc-reg-addsub} */
10586 +  {
10587 +    UBICOM32_INSN_DSP_MSUB_2_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_REG_ACC_REG_ADDSUB, "dsp-msub.2-s1-indirect-with-post-increment-2-dsp-src2-reg-acc-reg-addsub", "msub.2", 32,
10588 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10589 +  },
10590 +/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},${s1-i4-2}(${s1-An})++,${dsp-S2-acc-reg-addsub} */
10591 +  {
10592 +    UBICOM32_INSN_DSP_MSUB_2_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_REG_ACC_REG_ADDSUB, "dsp-msub.2-s1-indirect-with-pre-increment-2-dsp-src2-reg-acc-reg-addsub", "msub.2", 32,
10593 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10594 +  },
10595 +/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},${s1-direct-addr},#${bit5-addsub} */
10596 +  {
10597 +    UBICOM32_INSN_DSP_MSUB_2_S1_DIRECT_DSP_IMM_BIT5_ADDSUB2, "dsp-msub.2-s1-direct-dsp-imm-bit5-addsub2", "msub.2", 32,
10598 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10599 +  },
10600 +/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},#${s1-imm8},#${bit5-addsub} */
10601 +  {
10602 +    UBICOM32_INSN_DSP_MSUB_2_S1_IMMEDIATE_DSP_IMM_BIT5_ADDSUB2, "dsp-msub.2-s1-immediate-dsp-imm-bit5-addsub2", "msub.2", 32,
10603 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10604 +  },
10605 +/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},(${s1-An},${s1-r}),#${bit5-addsub} */
10606 +  {
10607 +    UBICOM32_INSN_DSP_MSUB_2_S1_INDIRECT_WITH_INDEX_2_DSP_IMM_BIT5_ADDSUB2, "dsp-msub.2-s1-indirect-with-index-2-dsp-imm-bit5-addsub2", "msub.2", 32,
10608 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10609 +  },
10610 +/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},${s1-imm7-2}(${s1-An}),#${bit5-addsub} */
10611 +  {
10612 +    UBICOM32_INSN_DSP_MSUB_2_S1_INDIRECT_WITH_OFFSET_2_DSP_IMM_BIT5_ADDSUB2, "dsp-msub.2-s1-indirect-with-offset-2-dsp-imm-bit5-addsub2", "msub.2", 32,
10613 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10614 +  },
10615 +/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},(${s1-An}),#${bit5-addsub} */
10616 +  {
10617 +    UBICOM32_INSN_DSP_MSUB_2_S1_INDIRECT_2_DSP_IMM_BIT5_ADDSUB2, "dsp-msub.2-s1-indirect-2-dsp-imm-bit5-addsub2", "msub.2", 32,
10618 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10619 +  },
10620 +/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},(${s1-An})${s1-i4-2}++,#${bit5-addsub} */
10621 +  {
10622 +    UBICOM32_INSN_DSP_MSUB_2_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_IMM_BIT5_ADDSUB2, "dsp-msub.2-s1-indirect-with-post-increment-2-dsp-imm-bit5-addsub2", "msub.2", 32,
10623 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10624 +  },
10625 +/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},${s1-i4-2}(${s1-An})++,#${bit5-addsub} */
10626 +  {
10627 +    UBICOM32_INSN_DSP_MSUB_2_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_IMM_BIT5_ADDSUB2, "dsp-msub.2-s1-indirect-with-pre-increment-2-dsp-imm-bit5-addsub2", "msub.2", 32,
10628 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10629 +  },
10630 +/* msub.4${dsp-c} ${dsp-destA},${s1-direct-addr},${dsp-S2-data-reg-addsub} */
10631 +  {
10632 +    UBICOM32_INSN_DSP_MSUB_4_S1_DIRECT_DSP_SRC2_DATA_REG_ADDSUB, "dsp-msub.4-s1-direct-dsp-src2-data-reg-addsub", "msub.4", 32,
10633 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10634 +  },
10635 +/* msub.4${dsp-c} ${dsp-destA},#${s1-imm8},${dsp-S2-data-reg-addsub} */
10636 +  {
10637 +    UBICOM32_INSN_DSP_MSUB_4_S1_IMMEDIATE_DSP_SRC2_DATA_REG_ADDSUB, "dsp-msub.4-s1-immediate-dsp-src2-data-reg-addsub", "msub.4", 32,
10638 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10639 +  },
10640 +/* msub.4${dsp-c} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-data-reg-addsub} */
10641 +  {
10642 +    UBICOM32_INSN_DSP_MSUB_4_S1_INDIRECT_WITH_INDEX_4_DSP_SRC2_DATA_REG_ADDSUB, "dsp-msub.4-s1-indirect-with-index-4-dsp-src2-data-reg-addsub", "msub.4", 32,
10643 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10644 +  },
10645 +/* msub.4${dsp-c} ${dsp-destA},${s1-imm7-4}(${s1-An}),${dsp-S2-data-reg-addsub} */
10646 +  {
10647 +    UBICOM32_INSN_DSP_MSUB_4_S1_INDIRECT_WITH_OFFSET_4_DSP_SRC2_DATA_REG_ADDSUB, "dsp-msub.4-s1-indirect-with-offset-4-dsp-src2-data-reg-addsub", "msub.4", 32,
10648 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10649 +  },
10650 +/* msub.4${dsp-c} ${dsp-destA},(${s1-An}),${dsp-S2-data-reg-addsub} */
10651 +  {
10652 +    UBICOM32_INSN_DSP_MSUB_4_S1_INDIRECT_4_DSP_SRC2_DATA_REG_ADDSUB, "dsp-msub.4-s1-indirect-4-dsp-src2-data-reg-addsub", "msub.4", 32,
10653 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10654 +  },
10655 +/* msub.4${dsp-c} ${dsp-destA},(${s1-An})${s1-i4-4}++,${dsp-S2-data-reg-addsub} */
10656 +  {
10657 +    UBICOM32_INSN_DSP_MSUB_4_S1_INDIRECT_WITH_POST_INCREMENT_4_DSP_SRC2_DATA_REG_ADDSUB, "dsp-msub.4-s1-indirect-with-post-increment-4-dsp-src2-data-reg-addsub", "msub.4", 32,
10658 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10659 +  },
10660 +/* msub.4${dsp-c} ${dsp-destA},${s1-i4-4}(${s1-An})++,${dsp-S2-data-reg-addsub} */
10661 +  {
10662 +    UBICOM32_INSN_DSP_MSUB_4_S1_INDIRECT_WITH_PRE_INCREMENT_4_DSP_SRC2_DATA_REG_ADDSUB, "dsp-msub.4-s1-indirect-with-pre-increment-4-dsp-src2-data-reg-addsub", "msub.4", 32,
10663 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10664 +  },
10665 +/* msub.4${dsp-c} ${dsp-destA},${s1-direct-addr},${dsp-S2-acc-reg-addsub} */
10666 +  {
10667 +    UBICOM32_INSN_DSP_MSUB_4_S1_DIRECT_DSP_SRC2_REG_ACC_REG_ADDSUB, "dsp-msub.4-s1-direct-dsp-src2-reg-acc-reg-addsub", "msub.4", 32,
10668 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10669 +  },
10670 +/* msub.4${dsp-c} ${dsp-destA},#${s1-imm8},${dsp-S2-acc-reg-addsub} */
10671 +  {
10672 +    UBICOM32_INSN_DSP_MSUB_4_S1_IMMEDIATE_DSP_SRC2_REG_ACC_REG_ADDSUB, "dsp-msub.4-s1-immediate-dsp-src2-reg-acc-reg-addsub", "msub.4", 32,
10673 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10674 +  },
10675 +/* msub.4${dsp-c} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-acc-reg-addsub} */
10676 +  {
10677 +    UBICOM32_INSN_DSP_MSUB_4_S1_INDIRECT_WITH_INDEX_4_DSP_SRC2_REG_ACC_REG_ADDSUB, "dsp-msub.4-s1-indirect-with-index-4-dsp-src2-reg-acc-reg-addsub", "msub.4", 32,
10678 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10679 +  },
10680 +/* msub.4${dsp-c} ${dsp-destA},${s1-imm7-4}(${s1-An}),${dsp-S2-acc-reg-addsub} */
10681 +  {
10682 +    UBICOM32_INSN_DSP_MSUB_4_S1_INDIRECT_WITH_OFFSET_4_DSP_SRC2_REG_ACC_REG_ADDSUB, "dsp-msub.4-s1-indirect-with-offset-4-dsp-src2-reg-acc-reg-addsub", "msub.4", 32,
10683 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10684 +  },
10685 +/* msub.4${dsp-c} ${dsp-destA},(${s1-An}),${dsp-S2-acc-reg-addsub} */
10686 +  {
10687 +    UBICOM32_INSN_DSP_MSUB_4_S1_INDIRECT_4_DSP_SRC2_REG_ACC_REG_ADDSUB, "dsp-msub.4-s1-indirect-4-dsp-src2-reg-acc-reg-addsub", "msub.4", 32,
10688 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10689 +  },
10690 +/* msub.4${dsp-c} ${dsp-destA},(${s1-An})${s1-i4-4}++,${dsp-S2-acc-reg-addsub} */
10691 +  {
10692 +    UBICOM32_INSN_DSP_MSUB_4_S1_INDIRECT_WITH_POST_INCREMENT_4_DSP_SRC2_REG_ACC_REG_ADDSUB, "dsp-msub.4-s1-indirect-with-post-increment-4-dsp-src2-reg-acc-reg-addsub", "msub.4", 32,
10693 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10694 +  },
10695 +/* msub.4${dsp-c} ${dsp-destA},${s1-i4-4}(${s1-An})++,${dsp-S2-acc-reg-addsub} */
10696 +  {
10697 +    UBICOM32_INSN_DSP_MSUB_4_S1_INDIRECT_WITH_PRE_INCREMENT_4_DSP_SRC2_REG_ACC_REG_ADDSUB, "dsp-msub.4-s1-indirect-with-pre-increment-4-dsp-src2-reg-acc-reg-addsub", "msub.4", 32,
10698 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10699 +  },
10700 +/* msub.4${dsp-c} ${dsp-destA},${s1-direct-addr},#${bit5-addsub} */
10701 +  {
10702 +    UBICOM32_INSN_DSP_MSUB_4_S1_DIRECT_DSP_IMM_BIT5_ADDSUB, "dsp-msub.4-s1-direct-dsp-imm-bit5-addsub", "msub.4", 32,
10703 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10704 +  },
10705 +/* msub.4${dsp-c} ${dsp-destA},#${s1-imm8},#${bit5-addsub} */
10706 +  {
10707 +    UBICOM32_INSN_DSP_MSUB_4_S1_IMMEDIATE_DSP_IMM_BIT5_ADDSUB, "dsp-msub.4-s1-immediate-dsp-imm-bit5-addsub", "msub.4", 32,
10708 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10709 +  },
10710 +/* msub.4${dsp-c} ${dsp-destA},(${s1-An},${s1-r}),#${bit5-addsub} */
10711 +  {
10712 +    UBICOM32_INSN_DSP_MSUB_4_S1_INDIRECT_WITH_INDEX_4_DSP_IMM_BIT5_ADDSUB, "dsp-msub.4-s1-indirect-with-index-4-dsp-imm-bit5-addsub", "msub.4", 32,
10713 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10714 +  },
10715 +/* msub.4${dsp-c} ${dsp-destA},${s1-imm7-4}(${s1-An}),#${bit5-addsub} */
10716 +  {
10717 +    UBICOM32_INSN_DSP_MSUB_4_S1_INDIRECT_WITH_OFFSET_4_DSP_IMM_BIT5_ADDSUB, "dsp-msub.4-s1-indirect-with-offset-4-dsp-imm-bit5-addsub", "msub.4", 32,
10718 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10719 +  },
10720 +/* msub.4${dsp-c} ${dsp-destA},(${s1-An}),#${bit5-addsub} */
10721 +  {
10722 +    UBICOM32_INSN_DSP_MSUB_4_S1_INDIRECT_4_DSP_IMM_BIT5_ADDSUB, "dsp-msub.4-s1-indirect-4-dsp-imm-bit5-addsub", "msub.4", 32,
10723 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10724 +  },
10725 +/* msub.4${dsp-c} ${dsp-destA},(${s1-An})${s1-i4-4}++,#${bit5-addsub} */
10726 +  {
10727 +    UBICOM32_INSN_DSP_MSUB_4_S1_INDIRECT_WITH_POST_INCREMENT_4_DSP_IMM_BIT5_ADDSUB, "dsp-msub.4-s1-indirect-with-post-increment-4-dsp-imm-bit5-addsub", "msub.4", 32,
10728 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10729 +  },
10730 +/* msub.4${dsp-c} ${dsp-destA},${s1-i4-4}(${s1-An})++,#${bit5-addsub} */
10731 +  {
10732 +    UBICOM32_INSN_DSP_MSUB_4_S1_INDIRECT_WITH_PRE_INCREMENT_4_DSP_IMM_BIT5_ADDSUB, "dsp-msub.4-s1-indirect-with-pre-increment-4-dsp-imm-bit5-addsub", "msub.4", 32,
10733 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10734 +  },
10735 +/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},${s1-direct-addr},${dsp-S2-data-reg-addsub} */
10736 +  {
10737 +    UBICOM32_INSN_DSP_MADD_2_S1_DIRECT_DSP_SRC2_DATA_REG_ADDSUB2, "dsp-madd.2-s1-direct-dsp-src2-data-reg-addsub2", "madd.2", 32,
10738 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10739 +  },
10740 +/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},#${s1-imm8},${dsp-S2-data-reg-addsub} */
10741 +  {
10742 +    UBICOM32_INSN_DSP_MADD_2_S1_IMMEDIATE_DSP_SRC2_DATA_REG_ADDSUB2, "dsp-madd.2-s1-immediate-dsp-src2-data-reg-addsub2", "madd.2", 32,
10743 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10744 +  },
10745 +/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-data-reg-addsub} */
10746 +  {
10747 +    UBICOM32_INSN_DSP_MADD_2_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_DATA_REG_ADDSUB2, "dsp-madd.2-s1-indirect-with-index-2-dsp-src2-data-reg-addsub2", "madd.2", 32,
10748 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10749 +  },
10750 +/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},${s1-imm7-2}(${s1-An}),${dsp-S2-data-reg-addsub} */
10751 +  {
10752 +    UBICOM32_INSN_DSP_MADD_2_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_DATA_REG_ADDSUB2, "dsp-madd.2-s1-indirect-with-offset-2-dsp-src2-data-reg-addsub2", "madd.2", 32,
10753 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10754 +  },
10755 +/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},(${s1-An}),${dsp-S2-data-reg-addsub} */
10756 +  {
10757 +    UBICOM32_INSN_DSP_MADD_2_S1_INDIRECT_2_DSP_SRC2_DATA_REG_ADDSUB2, "dsp-madd.2-s1-indirect-2-dsp-src2-data-reg-addsub2", "madd.2", 32,
10758 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10759 +  },
10760 +/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},(${s1-An})${s1-i4-2}++,${dsp-S2-data-reg-addsub} */
10761 +  {
10762 +    UBICOM32_INSN_DSP_MADD_2_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_DATA_REG_ADDSUB2, "dsp-madd.2-s1-indirect-with-post-increment-2-dsp-src2-data-reg-addsub2", "madd.2", 32,
10763 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10764 +  },
10765 +/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},${s1-i4-2}(${s1-An})++,${dsp-S2-data-reg-addsub} */
10766 +  {
10767 +    UBICOM32_INSN_DSP_MADD_2_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_DATA_REG_ADDSUB2, "dsp-madd.2-s1-indirect-with-pre-increment-2-dsp-src2-data-reg-addsub2", "madd.2", 32,
10768 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10769 +  },
10770 +/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},${s1-direct-addr},${dsp-S2-acc-reg-addsub} */
10771 +  {
10772 +    UBICOM32_INSN_DSP_MADD_2_S1_DIRECT_DSP_SRC2_REG_ACC_REG_ADDSUB, "dsp-madd.2-s1-direct-dsp-src2-reg-acc-reg-addsub", "madd.2", 32,
10773 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10774 +  },
10775 +/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},#${s1-imm8},${dsp-S2-acc-reg-addsub} */
10776 +  {
10777 +    UBICOM32_INSN_DSP_MADD_2_S1_IMMEDIATE_DSP_SRC2_REG_ACC_REG_ADDSUB, "dsp-madd.2-s1-immediate-dsp-src2-reg-acc-reg-addsub", "madd.2", 32,
10778 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10779 +  },
10780 +/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-acc-reg-addsub} */
10781 +  {
10782 +    UBICOM32_INSN_DSP_MADD_2_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_REG_ACC_REG_ADDSUB, "dsp-madd.2-s1-indirect-with-index-2-dsp-src2-reg-acc-reg-addsub", "madd.2", 32,
10783 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10784 +  },
10785 +/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},${s1-imm7-2}(${s1-An}),${dsp-S2-acc-reg-addsub} */
10786 +  {
10787 +    UBICOM32_INSN_DSP_MADD_2_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_REG_ACC_REG_ADDSUB, "dsp-madd.2-s1-indirect-with-offset-2-dsp-src2-reg-acc-reg-addsub", "madd.2", 32,
10788 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10789 +  },
10790 +/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},(${s1-An}),${dsp-S2-acc-reg-addsub} */
10791 +  {
10792 +    UBICOM32_INSN_DSP_MADD_2_S1_INDIRECT_2_DSP_SRC2_REG_ACC_REG_ADDSUB, "dsp-madd.2-s1-indirect-2-dsp-src2-reg-acc-reg-addsub", "madd.2", 32,
10793 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10794 +  },
10795 +/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},(${s1-An})${s1-i4-2}++,${dsp-S2-acc-reg-addsub} */
10796 +  {
10797 +    UBICOM32_INSN_DSP_MADD_2_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_REG_ACC_REG_ADDSUB, "dsp-madd.2-s1-indirect-with-post-increment-2-dsp-src2-reg-acc-reg-addsub", "madd.2", 32,
10798 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10799 +  },
10800 +/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},${s1-i4-2}(${s1-An})++,${dsp-S2-acc-reg-addsub} */
10801 +  {
10802 +    UBICOM32_INSN_DSP_MADD_2_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_REG_ACC_REG_ADDSUB, "dsp-madd.2-s1-indirect-with-pre-increment-2-dsp-src2-reg-acc-reg-addsub", "madd.2", 32,
10803 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10804 +  },
10805 +/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},${s1-direct-addr},#${bit5-addsub} */
10806 +  {
10807 +    UBICOM32_INSN_DSP_MADD_2_S1_DIRECT_DSP_IMM_BIT5_ADDSUB2, "dsp-madd.2-s1-direct-dsp-imm-bit5-addsub2", "madd.2", 32,
10808 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10809 +  },
10810 +/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},#${s1-imm8},#${bit5-addsub} */
10811 +  {
10812 +    UBICOM32_INSN_DSP_MADD_2_S1_IMMEDIATE_DSP_IMM_BIT5_ADDSUB2, "dsp-madd.2-s1-immediate-dsp-imm-bit5-addsub2", "madd.2", 32,
10813 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10814 +  },
10815 +/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},(${s1-An},${s1-r}),#${bit5-addsub} */
10816 +  {
10817 +    UBICOM32_INSN_DSP_MADD_2_S1_INDIRECT_WITH_INDEX_2_DSP_IMM_BIT5_ADDSUB2, "dsp-madd.2-s1-indirect-with-index-2-dsp-imm-bit5-addsub2", "madd.2", 32,
10818 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10819 +  },
10820 +/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},${s1-imm7-2}(${s1-An}),#${bit5-addsub} */
10821 +  {
10822 +    UBICOM32_INSN_DSP_MADD_2_S1_INDIRECT_WITH_OFFSET_2_DSP_IMM_BIT5_ADDSUB2, "dsp-madd.2-s1-indirect-with-offset-2-dsp-imm-bit5-addsub2", "madd.2", 32,
10823 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10824 +  },
10825 +/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},(${s1-An}),#${bit5-addsub} */
10826 +  {
10827 +    UBICOM32_INSN_DSP_MADD_2_S1_INDIRECT_2_DSP_IMM_BIT5_ADDSUB2, "dsp-madd.2-s1-indirect-2-dsp-imm-bit5-addsub2", "madd.2", 32,
10828 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10829 +  },
10830 +/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},(${s1-An})${s1-i4-2}++,#${bit5-addsub} */
10831 +  {
10832 +    UBICOM32_INSN_DSP_MADD_2_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_IMM_BIT5_ADDSUB2, "dsp-madd.2-s1-indirect-with-post-increment-2-dsp-imm-bit5-addsub2", "madd.2", 32,
10833 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10834 +  },
10835 +/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},${s1-i4-2}(${s1-An})++,#${bit5-addsub} */
10836 +  {
10837 +    UBICOM32_INSN_DSP_MADD_2_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_IMM_BIT5_ADDSUB2, "dsp-madd.2-s1-indirect-with-pre-increment-2-dsp-imm-bit5-addsub2", "madd.2", 32,
10838 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10839 +  },
10840 +/* madd.4${dsp-c} ${dsp-destA},${s1-direct-addr},${dsp-S2-data-reg-addsub} */
10841 +  {
10842 +    UBICOM32_INSN_DSP_MADD_4_S1_DIRECT_DSP_SRC2_DATA_REG_ADDSUB, "dsp-madd.4-s1-direct-dsp-src2-data-reg-addsub", "madd.4", 32,
10843 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10844 +  },
10845 +/* madd.4${dsp-c} ${dsp-destA},#${s1-imm8},${dsp-S2-data-reg-addsub} */
10846 +  {
10847 +    UBICOM32_INSN_DSP_MADD_4_S1_IMMEDIATE_DSP_SRC2_DATA_REG_ADDSUB, "dsp-madd.4-s1-immediate-dsp-src2-data-reg-addsub", "madd.4", 32,
10848 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10849 +  },
10850 +/* madd.4${dsp-c} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-data-reg-addsub} */
10851 +  {
10852 +    UBICOM32_INSN_DSP_MADD_4_S1_INDIRECT_WITH_INDEX_4_DSP_SRC2_DATA_REG_ADDSUB, "dsp-madd.4-s1-indirect-with-index-4-dsp-src2-data-reg-addsub", "madd.4", 32,
10853 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10854 +  },
10855 +/* madd.4${dsp-c} ${dsp-destA},${s1-imm7-4}(${s1-An}),${dsp-S2-data-reg-addsub} */
10856 +  {
10857 +    UBICOM32_INSN_DSP_MADD_4_S1_INDIRECT_WITH_OFFSET_4_DSP_SRC2_DATA_REG_ADDSUB, "dsp-madd.4-s1-indirect-with-offset-4-dsp-src2-data-reg-addsub", "madd.4", 32,
10858 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10859 +  },
10860 +/* madd.4${dsp-c} ${dsp-destA},(${s1-An}),${dsp-S2-data-reg-addsub} */
10861 +  {
10862 +    UBICOM32_INSN_DSP_MADD_4_S1_INDIRECT_4_DSP_SRC2_DATA_REG_ADDSUB, "dsp-madd.4-s1-indirect-4-dsp-src2-data-reg-addsub", "madd.4", 32,
10863 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10864 +  },
10865 +/* madd.4${dsp-c} ${dsp-destA},(${s1-An})${s1-i4-4}++,${dsp-S2-data-reg-addsub} */
10866 +  {
10867 +    UBICOM32_INSN_DSP_MADD_4_S1_INDIRECT_WITH_POST_INCREMENT_4_DSP_SRC2_DATA_REG_ADDSUB, "dsp-madd.4-s1-indirect-with-post-increment-4-dsp-src2-data-reg-addsub", "madd.4", 32,
10868 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10869 +  },
10870 +/* madd.4${dsp-c} ${dsp-destA},${s1-i4-4}(${s1-An})++,${dsp-S2-data-reg-addsub} */
10871 +  {
10872 +    UBICOM32_INSN_DSP_MADD_4_S1_INDIRECT_WITH_PRE_INCREMENT_4_DSP_SRC2_DATA_REG_ADDSUB, "dsp-madd.4-s1-indirect-with-pre-increment-4-dsp-src2-data-reg-addsub", "madd.4", 32,
10873 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10874 +  },
10875 +/* madd.4${dsp-c} ${dsp-destA},${s1-direct-addr},${dsp-S2-acc-reg-addsub} */
10876 +  {
10877 +    UBICOM32_INSN_DSP_MADD_4_S1_DIRECT_DSP_SRC2_REG_ACC_REG_ADDSUB, "dsp-madd.4-s1-direct-dsp-src2-reg-acc-reg-addsub", "madd.4", 32,
10878 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10879 +  },
10880 +/* madd.4${dsp-c} ${dsp-destA},#${s1-imm8},${dsp-S2-acc-reg-addsub} */
10881 +  {
10882 +    UBICOM32_INSN_DSP_MADD_4_S1_IMMEDIATE_DSP_SRC2_REG_ACC_REG_ADDSUB, "dsp-madd.4-s1-immediate-dsp-src2-reg-acc-reg-addsub", "madd.4", 32,
10883 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10884 +  },
10885 +/* madd.4${dsp-c} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-acc-reg-addsub} */
10886 +  {
10887 +    UBICOM32_INSN_DSP_MADD_4_S1_INDIRECT_WITH_INDEX_4_DSP_SRC2_REG_ACC_REG_ADDSUB, "dsp-madd.4-s1-indirect-with-index-4-dsp-src2-reg-acc-reg-addsub", "madd.4", 32,
10888 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10889 +  },
10890 +/* madd.4${dsp-c} ${dsp-destA},${s1-imm7-4}(${s1-An}),${dsp-S2-acc-reg-addsub} */
10891 +  {
10892 +    UBICOM32_INSN_DSP_MADD_4_S1_INDIRECT_WITH_OFFSET_4_DSP_SRC2_REG_ACC_REG_ADDSUB, "dsp-madd.4-s1-indirect-with-offset-4-dsp-src2-reg-acc-reg-addsub", "madd.4", 32,
10893 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10894 +  },
10895 +/* madd.4${dsp-c} ${dsp-destA},(${s1-An}),${dsp-S2-acc-reg-addsub} */
10896 +  {
10897 +    UBICOM32_INSN_DSP_MADD_4_S1_INDIRECT_4_DSP_SRC2_REG_ACC_REG_ADDSUB, "dsp-madd.4-s1-indirect-4-dsp-src2-reg-acc-reg-addsub", "madd.4", 32,
10898 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10899 +  },
10900 +/* madd.4${dsp-c} ${dsp-destA},(${s1-An})${s1-i4-4}++,${dsp-S2-acc-reg-addsub} */
10901 +  {
10902 +    UBICOM32_INSN_DSP_MADD_4_S1_INDIRECT_WITH_POST_INCREMENT_4_DSP_SRC2_REG_ACC_REG_ADDSUB, "dsp-madd.4-s1-indirect-with-post-increment-4-dsp-src2-reg-acc-reg-addsub", "madd.4", 32,
10903 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10904 +  },
10905 +/* madd.4${dsp-c} ${dsp-destA},${s1-i4-4}(${s1-An})++,${dsp-S2-acc-reg-addsub} */
10906 +  {
10907 +    UBICOM32_INSN_DSP_MADD_4_S1_INDIRECT_WITH_PRE_INCREMENT_4_DSP_SRC2_REG_ACC_REG_ADDSUB, "dsp-madd.4-s1-indirect-with-pre-increment-4-dsp-src2-reg-acc-reg-addsub", "madd.4", 32,
10908 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10909 +  },
10910 +/* madd.4${dsp-c} ${dsp-destA},${s1-direct-addr},#${bit5-addsub} */
10911 +  {
10912 +    UBICOM32_INSN_DSP_MADD_4_S1_DIRECT_DSP_IMM_BIT5_ADDSUB, "dsp-madd.4-s1-direct-dsp-imm-bit5-addsub", "madd.4", 32,
10913 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10914 +  },
10915 +/* madd.4${dsp-c} ${dsp-destA},#${s1-imm8},#${bit5-addsub} */
10916 +  {
10917 +    UBICOM32_INSN_DSP_MADD_4_S1_IMMEDIATE_DSP_IMM_BIT5_ADDSUB, "dsp-madd.4-s1-immediate-dsp-imm-bit5-addsub", "madd.4", 32,
10918 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10919 +  },
10920 +/* madd.4${dsp-c} ${dsp-destA},(${s1-An},${s1-r}),#${bit5-addsub} */
10921 +  {
10922 +    UBICOM32_INSN_DSP_MADD_4_S1_INDIRECT_WITH_INDEX_4_DSP_IMM_BIT5_ADDSUB, "dsp-madd.4-s1-indirect-with-index-4-dsp-imm-bit5-addsub", "madd.4", 32,
10923 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10924 +  },
10925 +/* madd.4${dsp-c} ${dsp-destA},${s1-imm7-4}(${s1-An}),#${bit5-addsub} */
10926 +  {
10927 +    UBICOM32_INSN_DSP_MADD_4_S1_INDIRECT_WITH_OFFSET_4_DSP_IMM_BIT5_ADDSUB, "dsp-madd.4-s1-indirect-with-offset-4-dsp-imm-bit5-addsub", "madd.4", 32,
10928 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10929 +  },
10930 +/* madd.4${dsp-c} ${dsp-destA},(${s1-An}),#${bit5-addsub} */
10931 +  {
10932 +    UBICOM32_INSN_DSP_MADD_4_S1_INDIRECT_4_DSP_IMM_BIT5_ADDSUB, "dsp-madd.4-s1-indirect-4-dsp-imm-bit5-addsub", "madd.4", 32,
10933 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10934 +  },
10935 +/* madd.4${dsp-c} ${dsp-destA},(${s1-An})${s1-i4-4}++,#${bit5-addsub} */
10936 +  {
10937 +    UBICOM32_INSN_DSP_MADD_4_S1_INDIRECT_WITH_POST_INCREMENT_4_DSP_IMM_BIT5_ADDSUB, "dsp-madd.4-s1-indirect-with-post-increment-4-dsp-imm-bit5-addsub", "madd.4", 32,
10938 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10939 +  },
10940 +/* madd.4${dsp-c} ${dsp-destA},${s1-i4-4}(${s1-An})++,#${bit5-addsub} */
10941 +  {
10942 +    UBICOM32_INSN_DSP_MADD_4_S1_INDIRECT_WITH_PRE_INCREMENT_4_DSP_IMM_BIT5_ADDSUB, "dsp-madd.4-s1-indirect-with-pre-increment-4-dsp-imm-bit5-addsub", "madd.4", 32,
10943 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10944 +  },
10945 +/* msuf${dsp-c}${dsp-t} ${dsp-destA},${s1-direct-addr},${dsp-S2-data-reg} */
10946 +  {
10947 +    UBICOM32_INSN_DSP_MSUF_S1_DIRECT_DSP_SRC2_DATA_REG, "dsp-msuf-s1-direct-dsp-src2-data-reg", "msuf", 32,
10948 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10949 +  },
10950 +/* msuf${dsp-c}${dsp-t} ${dsp-destA},#${s1-imm8},${dsp-S2-data-reg} */
10951 +  {
10952 +    UBICOM32_INSN_DSP_MSUF_S1_IMMEDIATE_DSP_SRC2_DATA_REG, "dsp-msuf-s1-immediate-dsp-src2-data-reg", "msuf", 32,
10953 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10954 +  },
10955 +/* msuf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-data-reg} */
10956 +  {
10957 +    UBICOM32_INSN_DSP_MSUF_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_DATA_REG, "dsp-msuf-s1-indirect-with-index-2-dsp-src2-data-reg", "msuf", 32,
10958 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10959 +  },
10960 +/* msuf${dsp-c}${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),${dsp-S2-data-reg} */
10961 +  {
10962 +    UBICOM32_INSN_DSP_MSUF_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_DATA_REG, "dsp-msuf-s1-indirect-with-offset-2-dsp-src2-data-reg", "msuf", 32,
10963 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10964 +  },
10965 +/* msuf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An}),${dsp-S2-data-reg} */
10966 +  {
10967 +    UBICOM32_INSN_DSP_MSUF_S1_INDIRECT_2_DSP_SRC2_DATA_REG, "dsp-msuf-s1-indirect-2-dsp-src2-data-reg", "msuf", 32,
10968 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10969 +  },
10970 +/* msuf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,${dsp-S2-data-reg} */
10971 +  {
10972 +    UBICOM32_INSN_DSP_MSUF_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_DATA_REG, "dsp-msuf-s1-indirect-with-post-increment-2-dsp-src2-data-reg", "msuf", 32,
10973 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10974 +  },
10975 +/* msuf${dsp-c}${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,${dsp-S2-data-reg} */
10976 +  {
10977 +    UBICOM32_INSN_DSP_MSUF_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_DATA_REG, "dsp-msuf-s1-indirect-with-pre-increment-2-dsp-src2-data-reg", "msuf", 32,
10978 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10979 +  },
10980 +/* msuf${dsp-c}${dsp-t} ${dsp-destA},${s1-direct-addr},${dsp-S2-acc-reg-mul} */
10981 +  {
10982 +    UBICOM32_INSN_DSP_MSUF_S1_DIRECT_DSP_SRC2_REG_ACC_REG_MUL, "dsp-msuf-s1-direct-dsp-src2-reg-acc-reg-mul", "msuf", 32,
10983 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10984 +  },
10985 +/* msuf${dsp-c}${dsp-t} ${dsp-destA},#${s1-imm8},${dsp-S2-acc-reg-mul} */
10986 +  {
10987 +    UBICOM32_INSN_DSP_MSUF_S1_IMMEDIATE_DSP_SRC2_REG_ACC_REG_MUL, "dsp-msuf-s1-immediate-dsp-src2-reg-acc-reg-mul", "msuf", 32,
10988 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10989 +  },
10990 +/* msuf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-acc-reg-mul} */
10991 +  {
10992 +    UBICOM32_INSN_DSP_MSUF_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_REG_ACC_REG_MUL, "dsp-msuf-s1-indirect-with-index-2-dsp-src2-reg-acc-reg-mul", "msuf", 32,
10993 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10994 +  },
10995 +/* msuf${dsp-c}${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),${dsp-S2-acc-reg-mul} */
10996 +  {
10997 +    UBICOM32_INSN_DSP_MSUF_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_REG_ACC_REG_MUL, "dsp-msuf-s1-indirect-with-offset-2-dsp-src2-reg-acc-reg-mul", "msuf", 32,
10998 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
10999 +  },
11000 +/* msuf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An}),${dsp-S2-acc-reg-mul} */
11001 +  {
11002 +    UBICOM32_INSN_DSP_MSUF_S1_INDIRECT_2_DSP_SRC2_REG_ACC_REG_MUL, "dsp-msuf-s1-indirect-2-dsp-src2-reg-acc-reg-mul", "msuf", 32,
11003 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11004 +  },
11005 +/* msuf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,${dsp-S2-acc-reg-mul} */
11006 +  {
11007 +    UBICOM32_INSN_DSP_MSUF_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_REG_ACC_REG_MUL, "dsp-msuf-s1-indirect-with-post-increment-2-dsp-src2-reg-acc-reg-mul", "msuf", 32,
11008 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11009 +  },
11010 +/* msuf${dsp-c}${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,${dsp-S2-acc-reg-mul} */
11011 +  {
11012 +    UBICOM32_INSN_DSP_MSUF_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_REG_ACC_REG_MUL, "dsp-msuf-s1-indirect-with-pre-increment-2-dsp-src2-reg-acc-reg-mul", "msuf", 32,
11013 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11014 +  },
11015 +/* msuf${dsp-c}${dsp-t} ${dsp-destA},${s1-direct-addr},#${bit5} */
11016 +  {
11017 +    UBICOM32_INSN_DSP_MSUF_S1_DIRECT_DSP_IMM_BIT5, "dsp-msuf-s1-direct-dsp-imm-bit5", "msuf", 32,
11018 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11019 +  },
11020 +/* msuf${dsp-c}${dsp-t} ${dsp-destA},#${s1-imm8},#${bit5} */
11021 +  {
11022 +    UBICOM32_INSN_DSP_MSUF_S1_IMMEDIATE_DSP_IMM_BIT5, "dsp-msuf-s1-immediate-dsp-imm-bit5", "msuf", 32,
11023 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11024 +  },
11025 +/* msuf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),#${bit5} */
11026 +  {
11027 +    UBICOM32_INSN_DSP_MSUF_S1_INDIRECT_WITH_INDEX_2_DSP_IMM_BIT5, "dsp-msuf-s1-indirect-with-index-2-dsp-imm-bit5", "msuf", 32,
11028 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11029 +  },
11030 +/* msuf${dsp-c}${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),#${bit5} */
11031 +  {
11032 +    UBICOM32_INSN_DSP_MSUF_S1_INDIRECT_WITH_OFFSET_2_DSP_IMM_BIT5, "dsp-msuf-s1-indirect-with-offset-2-dsp-imm-bit5", "msuf", 32,
11033 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11034 +  },
11035 +/* msuf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An}),#${bit5} */
11036 +  {
11037 +    UBICOM32_INSN_DSP_MSUF_S1_INDIRECT_2_DSP_IMM_BIT5, "dsp-msuf-s1-indirect-2-dsp-imm-bit5", "msuf", 32,
11038 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11039 +  },
11040 +/* msuf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,#${bit5} */
11041 +  {
11042 +    UBICOM32_INSN_DSP_MSUF_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_IMM_BIT5, "dsp-msuf-s1-indirect-with-post-increment-2-dsp-imm-bit5", "msuf", 32,
11043 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11044 +  },
11045 +/* msuf${dsp-c}${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,#${bit5} */
11046 +  {
11047 +    UBICOM32_INSN_DSP_MSUF_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_IMM_BIT5, "dsp-msuf-s1-indirect-with-pre-increment-2-dsp-imm-bit5", "msuf", 32,
11048 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11049 +  },
11050 +/* macus${dsp-c}${dsp-t} ${dsp-destA},${s1-direct-addr},${dsp-S2-data-reg} */
11051 +  {
11052 +    UBICOM32_INSN_DSP_MACUS_S1_DIRECT_DSP_SRC2_DATA_REG, "dsp-macus-s1-direct-dsp-src2-data-reg", "macus", 32,
11053 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11054 +  },
11055 +/* macus${dsp-c}${dsp-t} ${dsp-destA},#${s1-imm8},${dsp-S2-data-reg} */
11056 +  {
11057 +    UBICOM32_INSN_DSP_MACUS_S1_IMMEDIATE_DSP_SRC2_DATA_REG, "dsp-macus-s1-immediate-dsp-src2-data-reg", "macus", 32,
11058 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11059 +  },
11060 +/* macus${dsp-c}${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-data-reg} */
11061 +  {
11062 +    UBICOM32_INSN_DSP_MACUS_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_DATA_REG, "dsp-macus-s1-indirect-with-index-2-dsp-src2-data-reg", "macus", 32,
11063 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11064 +  },
11065 +/* macus${dsp-c}${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),${dsp-S2-data-reg} */
11066 +  {
11067 +    UBICOM32_INSN_DSP_MACUS_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_DATA_REG, "dsp-macus-s1-indirect-with-offset-2-dsp-src2-data-reg", "macus", 32,
11068 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11069 +  },
11070 +/* macus${dsp-c}${dsp-t} ${dsp-destA},(${s1-An}),${dsp-S2-data-reg} */
11071 +  {
11072 +    UBICOM32_INSN_DSP_MACUS_S1_INDIRECT_2_DSP_SRC2_DATA_REG, "dsp-macus-s1-indirect-2-dsp-src2-data-reg", "macus", 32,
11073 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11074 +  },
11075 +/* macus${dsp-c}${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,${dsp-S2-data-reg} */
11076 +  {
11077 +    UBICOM32_INSN_DSP_MACUS_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_DATA_REG, "dsp-macus-s1-indirect-with-post-increment-2-dsp-src2-data-reg", "macus", 32,
11078 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11079 +  },
11080 +/* macus${dsp-c}${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,${dsp-S2-data-reg} */
11081 +  {
11082 +    UBICOM32_INSN_DSP_MACUS_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_DATA_REG, "dsp-macus-s1-indirect-with-pre-increment-2-dsp-src2-data-reg", "macus", 32,
11083 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11084 +  },
11085 +/* macus${dsp-c}${dsp-t} ${dsp-destA},${s1-direct-addr},${dsp-S2-acc-reg-mul} */
11086 +  {
11087 +    UBICOM32_INSN_DSP_MACUS_S1_DIRECT_DSP_SRC2_REG_ACC_REG_MUL, "dsp-macus-s1-direct-dsp-src2-reg-acc-reg-mul", "macus", 32,
11088 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11089 +  },
11090 +/* macus${dsp-c}${dsp-t} ${dsp-destA},#${s1-imm8},${dsp-S2-acc-reg-mul} */
11091 +  {
11092 +    UBICOM32_INSN_DSP_MACUS_S1_IMMEDIATE_DSP_SRC2_REG_ACC_REG_MUL, "dsp-macus-s1-immediate-dsp-src2-reg-acc-reg-mul", "macus", 32,
11093 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11094 +  },
11095 +/* macus${dsp-c}${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-acc-reg-mul} */
11096 +  {
11097 +    UBICOM32_INSN_DSP_MACUS_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_REG_ACC_REG_MUL, "dsp-macus-s1-indirect-with-index-2-dsp-src2-reg-acc-reg-mul", "macus", 32,
11098 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11099 +  },
11100 +/* macus${dsp-c}${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),${dsp-S2-acc-reg-mul} */
11101 +  {
11102 +    UBICOM32_INSN_DSP_MACUS_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_REG_ACC_REG_MUL, "dsp-macus-s1-indirect-with-offset-2-dsp-src2-reg-acc-reg-mul", "macus", 32,
11103 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11104 +  },
11105 +/* macus${dsp-c}${dsp-t} ${dsp-destA},(${s1-An}),${dsp-S2-acc-reg-mul} */
11106 +  {
11107 +    UBICOM32_INSN_DSP_MACUS_S1_INDIRECT_2_DSP_SRC2_REG_ACC_REG_MUL, "dsp-macus-s1-indirect-2-dsp-src2-reg-acc-reg-mul", "macus", 32,
11108 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11109 +  },
11110 +/* macus${dsp-c}${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,${dsp-S2-acc-reg-mul} */
11111 +  {
11112 +    UBICOM32_INSN_DSP_MACUS_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_REG_ACC_REG_MUL, "dsp-macus-s1-indirect-with-post-increment-2-dsp-src2-reg-acc-reg-mul", "macus", 32,
11113 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11114 +  },
11115 +/* macus${dsp-c}${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,${dsp-S2-acc-reg-mul} */
11116 +  {
11117 +    UBICOM32_INSN_DSP_MACUS_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_REG_ACC_REG_MUL, "dsp-macus-s1-indirect-with-pre-increment-2-dsp-src2-reg-acc-reg-mul", "macus", 32,
11118 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11119 +  },
11120 +/* macus${dsp-c}${dsp-t} ${dsp-destA},${s1-direct-addr},#${bit5} */
11121 +  {
11122 +    UBICOM32_INSN_DSP_MACUS_S1_DIRECT_DSP_IMM_BIT5, "dsp-macus-s1-direct-dsp-imm-bit5", "macus", 32,
11123 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11124 +  },
11125 +/* macus${dsp-c}${dsp-t} ${dsp-destA},#${s1-imm8},#${bit5} */
11126 +  {
11127 +    UBICOM32_INSN_DSP_MACUS_S1_IMMEDIATE_DSP_IMM_BIT5, "dsp-macus-s1-immediate-dsp-imm-bit5", "macus", 32,
11128 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11129 +  },
11130 +/* macus${dsp-c}${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),#${bit5} */
11131 +  {
11132 +    UBICOM32_INSN_DSP_MACUS_S1_INDIRECT_WITH_INDEX_2_DSP_IMM_BIT5, "dsp-macus-s1-indirect-with-index-2-dsp-imm-bit5", "macus", 32,
11133 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11134 +  },
11135 +/* macus${dsp-c}${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),#${bit5} */
11136 +  {
11137 +    UBICOM32_INSN_DSP_MACUS_S1_INDIRECT_WITH_OFFSET_2_DSP_IMM_BIT5, "dsp-macus-s1-indirect-with-offset-2-dsp-imm-bit5", "macus", 32,
11138 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11139 +  },
11140 +/* macus${dsp-c}${dsp-t} ${dsp-destA},(${s1-An}),#${bit5} */
11141 +  {
11142 +    UBICOM32_INSN_DSP_MACUS_S1_INDIRECT_2_DSP_IMM_BIT5, "dsp-macus-s1-indirect-2-dsp-imm-bit5", "macus", 32,
11143 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11144 +  },
11145 +/* macus${dsp-c}${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,#${bit5} */
11146 +  {
11147 +    UBICOM32_INSN_DSP_MACUS_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_IMM_BIT5, "dsp-macus-s1-indirect-with-post-increment-2-dsp-imm-bit5", "macus", 32,
11148 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11149 +  },
11150 +/* macus${dsp-c}${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,#${bit5} */
11151 +  {
11152 +    UBICOM32_INSN_DSP_MACUS_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_IMM_BIT5, "dsp-macus-s1-indirect-with-pre-increment-2-dsp-imm-bit5", "macus", 32,
11153 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11154 +  },
11155 +/* macf${dsp-c}${dsp-t} ${dsp-destA},${s1-direct-addr},${dsp-S2-data-reg} */
11156 +  {
11157 +    UBICOM32_INSN_DSP_MACF_S1_DIRECT_DSP_SRC2_DATA_REG, "dsp-macf-s1-direct-dsp-src2-data-reg", "macf", 32,
11158 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11159 +  },
11160 +/* macf${dsp-c}${dsp-t} ${dsp-destA},#${s1-imm8},${dsp-S2-data-reg} */
11161 +  {
11162 +    UBICOM32_INSN_DSP_MACF_S1_IMMEDIATE_DSP_SRC2_DATA_REG, "dsp-macf-s1-immediate-dsp-src2-data-reg", "macf", 32,
11163 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11164 +  },
11165 +/* macf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-data-reg} */
11166 +  {
11167 +    UBICOM32_INSN_DSP_MACF_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_DATA_REG, "dsp-macf-s1-indirect-with-index-2-dsp-src2-data-reg", "macf", 32,
11168 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11169 +  },
11170 +/* macf${dsp-c}${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),${dsp-S2-data-reg} */
11171 +  {
11172 +    UBICOM32_INSN_DSP_MACF_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_DATA_REG, "dsp-macf-s1-indirect-with-offset-2-dsp-src2-data-reg", "macf", 32,
11173 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11174 +  },
11175 +/* macf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An}),${dsp-S2-data-reg} */
11176 +  {
11177 +    UBICOM32_INSN_DSP_MACF_S1_INDIRECT_2_DSP_SRC2_DATA_REG, "dsp-macf-s1-indirect-2-dsp-src2-data-reg", "macf", 32,
11178 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11179 +  },
11180 +/* macf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,${dsp-S2-data-reg} */
11181 +  {
11182 +    UBICOM32_INSN_DSP_MACF_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_DATA_REG, "dsp-macf-s1-indirect-with-post-increment-2-dsp-src2-data-reg", "macf", 32,
11183 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11184 +  },
11185 +/* macf${dsp-c}${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,${dsp-S2-data-reg} */
11186 +  {
11187 +    UBICOM32_INSN_DSP_MACF_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_DATA_REG, "dsp-macf-s1-indirect-with-pre-increment-2-dsp-src2-data-reg", "macf", 32,
11188 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11189 +  },
11190 +/* macf${dsp-c}${dsp-t} ${dsp-destA},${s1-direct-addr},${dsp-S2-acc-reg-mul} */
11191 +  {
11192 +    UBICOM32_INSN_DSP_MACF_S1_DIRECT_DSP_SRC2_REG_ACC_REG_MUL, "dsp-macf-s1-direct-dsp-src2-reg-acc-reg-mul", "macf", 32,
11193 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11194 +  },
11195 +/* macf${dsp-c}${dsp-t} ${dsp-destA},#${s1-imm8},${dsp-S2-acc-reg-mul} */
11196 +  {
11197 +    UBICOM32_INSN_DSP_MACF_S1_IMMEDIATE_DSP_SRC2_REG_ACC_REG_MUL, "dsp-macf-s1-immediate-dsp-src2-reg-acc-reg-mul", "macf", 32,
11198 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11199 +  },
11200 +/* macf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-acc-reg-mul} */
11201 +  {
11202 +    UBICOM32_INSN_DSP_MACF_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_REG_ACC_REG_MUL, "dsp-macf-s1-indirect-with-index-2-dsp-src2-reg-acc-reg-mul", "macf", 32,
11203 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11204 +  },
11205 +/* macf${dsp-c}${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),${dsp-S2-acc-reg-mul} */
11206 +  {
11207 +    UBICOM32_INSN_DSP_MACF_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_REG_ACC_REG_MUL, "dsp-macf-s1-indirect-with-offset-2-dsp-src2-reg-acc-reg-mul", "macf", 32,
11208 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11209 +  },
11210 +/* macf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An}),${dsp-S2-acc-reg-mul} */
11211 +  {
11212 +    UBICOM32_INSN_DSP_MACF_S1_INDIRECT_2_DSP_SRC2_REG_ACC_REG_MUL, "dsp-macf-s1-indirect-2-dsp-src2-reg-acc-reg-mul", "macf", 32,
11213 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11214 +  },
11215 +/* macf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,${dsp-S2-acc-reg-mul} */
11216 +  {
11217 +    UBICOM32_INSN_DSP_MACF_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_REG_ACC_REG_MUL, "dsp-macf-s1-indirect-with-post-increment-2-dsp-src2-reg-acc-reg-mul", "macf", 32,
11218 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11219 +  },
11220 +/* macf${dsp-c}${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,${dsp-S2-acc-reg-mul} */
11221 +  {
11222 +    UBICOM32_INSN_DSP_MACF_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_REG_ACC_REG_MUL, "dsp-macf-s1-indirect-with-pre-increment-2-dsp-src2-reg-acc-reg-mul", "macf", 32,
11223 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11224 +  },
11225 +/* macf${dsp-c}${dsp-t} ${dsp-destA},${s1-direct-addr},#${bit5} */
11226 +  {
11227 +    UBICOM32_INSN_DSP_MACF_S1_DIRECT_DSP_IMM_BIT5, "dsp-macf-s1-direct-dsp-imm-bit5", "macf", 32,
11228 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11229 +  },
11230 +/* macf${dsp-c}${dsp-t} ${dsp-destA},#${s1-imm8},#${bit5} */
11231 +  {
11232 +    UBICOM32_INSN_DSP_MACF_S1_IMMEDIATE_DSP_IMM_BIT5, "dsp-macf-s1-immediate-dsp-imm-bit5", "macf", 32,
11233 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11234 +  },
11235 +/* macf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),#${bit5} */
11236 +  {
11237 +    UBICOM32_INSN_DSP_MACF_S1_INDIRECT_WITH_INDEX_2_DSP_IMM_BIT5, "dsp-macf-s1-indirect-with-index-2-dsp-imm-bit5", "macf", 32,
11238 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11239 +  },
11240 +/* macf${dsp-c}${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),#${bit5} */
11241 +  {
11242 +    UBICOM32_INSN_DSP_MACF_S1_INDIRECT_WITH_OFFSET_2_DSP_IMM_BIT5, "dsp-macf-s1-indirect-with-offset-2-dsp-imm-bit5", "macf", 32,
11243 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11244 +  },
11245 +/* macf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An}),#${bit5} */
11246 +  {
11247 +    UBICOM32_INSN_DSP_MACF_S1_INDIRECT_2_DSP_IMM_BIT5, "dsp-macf-s1-indirect-2-dsp-imm-bit5", "macf", 32,
11248 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11249 +  },
11250 +/* macf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,#${bit5} */
11251 +  {
11252 +    UBICOM32_INSN_DSP_MACF_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_IMM_BIT5, "dsp-macf-s1-indirect-with-post-increment-2-dsp-imm-bit5", "macf", 32,
11253 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11254 +  },
11255 +/* macf${dsp-c}${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,#${bit5} */
11256 +  {
11257 +    UBICOM32_INSN_DSP_MACF_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_IMM_BIT5, "dsp-macf-s1-indirect-with-pre-increment-2-dsp-imm-bit5", "macf", 32,
11258 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11259 +  },
11260 +/* mulf${dsp-c}${dsp-t} ${dsp-destA},${s1-direct-addr},${dsp-S2-data-reg} */
11261 +  {
11262 +    UBICOM32_INSN_DSP_MULF_S1_DIRECT_DSP_SRC2_DATA_REG, "dsp-mulf-s1-direct-dsp-src2-data-reg", "mulf", 32,
11263 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11264 +  },
11265 +/* mulf${dsp-c}${dsp-t} ${dsp-destA},#${s1-imm8},${dsp-S2-data-reg} */
11266 +  {
11267 +    UBICOM32_INSN_DSP_MULF_S1_IMMEDIATE_DSP_SRC2_DATA_REG, "dsp-mulf-s1-immediate-dsp-src2-data-reg", "mulf", 32,
11268 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11269 +  },
11270 +/* mulf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-data-reg} */
11271 +  {
11272 +    UBICOM32_INSN_DSP_MULF_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_DATA_REG, "dsp-mulf-s1-indirect-with-index-2-dsp-src2-data-reg", "mulf", 32,
11273 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11274 +  },
11275 +/* mulf${dsp-c}${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),${dsp-S2-data-reg} */
11276 +  {
11277 +    UBICOM32_INSN_DSP_MULF_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_DATA_REG, "dsp-mulf-s1-indirect-with-offset-2-dsp-src2-data-reg", "mulf", 32,
11278 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11279 +  },
11280 +/* mulf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An}),${dsp-S2-data-reg} */
11281 +  {
11282 +    UBICOM32_INSN_DSP_MULF_S1_INDIRECT_2_DSP_SRC2_DATA_REG, "dsp-mulf-s1-indirect-2-dsp-src2-data-reg", "mulf", 32,
11283 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11284 +  },
11285 +/* mulf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,${dsp-S2-data-reg} */
11286 +  {
11287 +    UBICOM32_INSN_DSP_MULF_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_DATA_REG, "dsp-mulf-s1-indirect-with-post-increment-2-dsp-src2-data-reg", "mulf", 32,
11288 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11289 +  },
11290 +/* mulf${dsp-c}${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,${dsp-S2-data-reg} */
11291 +  {
11292 +    UBICOM32_INSN_DSP_MULF_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_DATA_REG, "dsp-mulf-s1-indirect-with-pre-increment-2-dsp-src2-data-reg", "mulf", 32,
11293 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11294 +  },
11295 +/* mulf${dsp-c}${dsp-t} ${dsp-destA},${s1-direct-addr},${dsp-S2-acc-reg-mul} */
11296 +  {
11297 +    UBICOM32_INSN_DSP_MULF_S1_DIRECT_DSP_SRC2_REG_ACC_REG_MUL, "dsp-mulf-s1-direct-dsp-src2-reg-acc-reg-mul", "mulf", 32,
11298 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11299 +  },
11300 +/* mulf${dsp-c}${dsp-t} ${dsp-destA},#${s1-imm8},${dsp-S2-acc-reg-mul} */
11301 +  {
11302 +    UBICOM32_INSN_DSP_MULF_S1_IMMEDIATE_DSP_SRC2_REG_ACC_REG_MUL, "dsp-mulf-s1-immediate-dsp-src2-reg-acc-reg-mul", "mulf", 32,
11303 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11304 +  },
11305 +/* mulf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-acc-reg-mul} */
11306 +  {
11307 +    UBICOM32_INSN_DSP_MULF_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_REG_ACC_REG_MUL, "dsp-mulf-s1-indirect-with-index-2-dsp-src2-reg-acc-reg-mul", "mulf", 32,
11308 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11309 +  },
11310 +/* mulf${dsp-c}${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),${dsp-S2-acc-reg-mul} */
11311 +  {
11312 +    UBICOM32_INSN_DSP_MULF_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_REG_ACC_REG_MUL, "dsp-mulf-s1-indirect-with-offset-2-dsp-src2-reg-acc-reg-mul", "mulf", 32,
11313 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11314 +  },
11315 +/* mulf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An}),${dsp-S2-acc-reg-mul} */
11316 +  {
11317 +    UBICOM32_INSN_DSP_MULF_S1_INDIRECT_2_DSP_SRC2_REG_ACC_REG_MUL, "dsp-mulf-s1-indirect-2-dsp-src2-reg-acc-reg-mul", "mulf", 32,
11318 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11319 +  },
11320 +/* mulf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,${dsp-S2-acc-reg-mul} */
11321 +  {
11322 +    UBICOM32_INSN_DSP_MULF_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_REG_ACC_REG_MUL, "dsp-mulf-s1-indirect-with-post-increment-2-dsp-src2-reg-acc-reg-mul", "mulf", 32,
11323 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11324 +  },
11325 +/* mulf${dsp-c}${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,${dsp-S2-acc-reg-mul} */
11326 +  {
11327 +    UBICOM32_INSN_DSP_MULF_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_REG_ACC_REG_MUL, "dsp-mulf-s1-indirect-with-pre-increment-2-dsp-src2-reg-acc-reg-mul", "mulf", 32,
11328 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11329 +  },
11330 +/* mulf${dsp-c}${dsp-t} ${dsp-destA},${s1-direct-addr},#${bit5} */
11331 +  {
11332 +    UBICOM32_INSN_DSP_MULF_S1_DIRECT_DSP_IMM_BIT5, "dsp-mulf-s1-direct-dsp-imm-bit5", "mulf", 32,
11333 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11334 +  },
11335 +/* mulf${dsp-c}${dsp-t} ${dsp-destA},#${s1-imm8},#${bit5} */
11336 +  {
11337 +    UBICOM32_INSN_DSP_MULF_S1_IMMEDIATE_DSP_IMM_BIT5, "dsp-mulf-s1-immediate-dsp-imm-bit5", "mulf", 32,
11338 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11339 +  },
11340 +/* mulf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),#${bit5} */
11341 +  {
11342 +    UBICOM32_INSN_DSP_MULF_S1_INDIRECT_WITH_INDEX_2_DSP_IMM_BIT5, "dsp-mulf-s1-indirect-with-index-2-dsp-imm-bit5", "mulf", 32,
11343 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11344 +  },
11345 +/* mulf${dsp-c}${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),#${bit5} */
11346 +  {
11347 +    UBICOM32_INSN_DSP_MULF_S1_INDIRECT_WITH_OFFSET_2_DSP_IMM_BIT5, "dsp-mulf-s1-indirect-with-offset-2-dsp-imm-bit5", "mulf", 32,
11348 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11349 +  },
11350 +/* mulf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An}),#${bit5} */
11351 +  {
11352 +    UBICOM32_INSN_DSP_MULF_S1_INDIRECT_2_DSP_IMM_BIT5, "dsp-mulf-s1-indirect-2-dsp-imm-bit5", "mulf", 32,
11353 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11354 +  },
11355 +/* mulf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,#${bit5} */
11356 +  {
11357 +    UBICOM32_INSN_DSP_MULF_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_IMM_BIT5, "dsp-mulf-s1-indirect-with-post-increment-2-dsp-imm-bit5", "mulf", 32,
11358 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11359 +  },
11360 +/* mulf${dsp-c}${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,#${bit5} */
11361 +  {
11362 +    UBICOM32_INSN_DSP_MULF_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_IMM_BIT5, "dsp-mulf-s1-indirect-with-pre-increment-2-dsp-imm-bit5", "mulf", 32,
11363 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11364 +  },
11365 +/* macu${dsp-c}${dsp-t} ${dsp-destA},${s1-direct-addr},${dsp-S2-data-reg} */
11366 +  {
11367 +    UBICOM32_INSN_DSP_MACU_S1_DIRECT_DSP_SRC2_DATA_REG, "dsp-macu-s1-direct-dsp-src2-data-reg", "macu", 32,
11368 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11369 +  },
11370 +/* macu${dsp-c}${dsp-t} ${dsp-destA},#${s1-imm8},${dsp-S2-data-reg} */
11371 +  {
11372 +    UBICOM32_INSN_DSP_MACU_S1_IMMEDIATE_DSP_SRC2_DATA_REG, "dsp-macu-s1-immediate-dsp-src2-data-reg", "macu", 32,
11373 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11374 +  },
11375 +/* macu${dsp-c}${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-data-reg} */
11376 +  {
11377 +    UBICOM32_INSN_DSP_MACU_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_DATA_REG, "dsp-macu-s1-indirect-with-index-2-dsp-src2-data-reg", "macu", 32,
11378 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11379 +  },
11380 +/* macu${dsp-c}${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),${dsp-S2-data-reg} */
11381 +  {
11382 +    UBICOM32_INSN_DSP_MACU_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_DATA_REG, "dsp-macu-s1-indirect-with-offset-2-dsp-src2-data-reg", "macu", 32,
11383 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11384 +  },
11385 +/* macu${dsp-c}${dsp-t} ${dsp-destA},(${s1-An}),${dsp-S2-data-reg} */
11386 +  {
11387 +    UBICOM32_INSN_DSP_MACU_S1_INDIRECT_2_DSP_SRC2_DATA_REG, "dsp-macu-s1-indirect-2-dsp-src2-data-reg", "macu", 32,
11388 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11389 +  },
11390 +/* macu${dsp-c}${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,${dsp-S2-data-reg} */
11391 +  {
11392 +    UBICOM32_INSN_DSP_MACU_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_DATA_REG, "dsp-macu-s1-indirect-with-post-increment-2-dsp-src2-data-reg", "macu", 32,
11393 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11394 +  },
11395 +/* macu${dsp-c}${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,${dsp-S2-data-reg} */
11396 +  {
11397 +    UBICOM32_INSN_DSP_MACU_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_DATA_REG, "dsp-macu-s1-indirect-with-pre-increment-2-dsp-src2-data-reg", "macu", 32,
11398 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11399 +  },
11400 +/* macu${dsp-c}${dsp-t} ${dsp-destA},${s1-direct-addr},${dsp-S2-acc-reg-mul} */
11401 +  {
11402 +    UBICOM32_INSN_DSP_MACU_S1_DIRECT_DSP_SRC2_REG_ACC_REG_MUL, "dsp-macu-s1-direct-dsp-src2-reg-acc-reg-mul", "macu", 32,
11403 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11404 +  },
11405 +/* macu${dsp-c}${dsp-t} ${dsp-destA},#${s1-imm8},${dsp-S2-acc-reg-mul} */
11406 +  {
11407 +    UBICOM32_INSN_DSP_MACU_S1_IMMEDIATE_DSP_SRC2_REG_ACC_REG_MUL, "dsp-macu-s1-immediate-dsp-src2-reg-acc-reg-mul", "macu", 32,
11408 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11409 +  },
11410 +/* macu${dsp-c}${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-acc-reg-mul} */
11411 +  {
11412 +    UBICOM32_INSN_DSP_MACU_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_REG_ACC_REG_MUL, "dsp-macu-s1-indirect-with-index-2-dsp-src2-reg-acc-reg-mul", "macu", 32,
11413 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11414 +  },
11415 +/* macu${dsp-c}${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),${dsp-S2-acc-reg-mul} */
11416 +  {
11417 +    UBICOM32_INSN_DSP_MACU_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_REG_ACC_REG_MUL, "dsp-macu-s1-indirect-with-offset-2-dsp-src2-reg-acc-reg-mul", "macu", 32,
11418 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11419 +  },
11420 +/* macu${dsp-c}${dsp-t} ${dsp-destA},(${s1-An}),${dsp-S2-acc-reg-mul} */
11421 +  {
11422 +    UBICOM32_INSN_DSP_MACU_S1_INDIRECT_2_DSP_SRC2_REG_ACC_REG_MUL, "dsp-macu-s1-indirect-2-dsp-src2-reg-acc-reg-mul", "macu", 32,
11423 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11424 +  },
11425 +/* macu${dsp-c}${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,${dsp-S2-acc-reg-mul} */
11426 +  {
11427 +    UBICOM32_INSN_DSP_MACU_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_REG_ACC_REG_MUL, "dsp-macu-s1-indirect-with-post-increment-2-dsp-src2-reg-acc-reg-mul", "macu", 32,
11428 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11429 +  },
11430 +/* macu${dsp-c}${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,${dsp-S2-acc-reg-mul} */
11431 +  {
11432 +    UBICOM32_INSN_DSP_MACU_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_REG_ACC_REG_MUL, "dsp-macu-s1-indirect-with-pre-increment-2-dsp-src2-reg-acc-reg-mul", "macu", 32,
11433 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11434 +  },
11435 +/* macu${dsp-c}${dsp-t} ${dsp-destA},${s1-direct-addr},#${bit5} */
11436 +  {
11437 +    UBICOM32_INSN_DSP_MACU_S1_DIRECT_DSP_IMM_BIT5, "dsp-macu-s1-direct-dsp-imm-bit5", "macu", 32,
11438 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11439 +  },
11440 +/* macu${dsp-c}${dsp-t} ${dsp-destA},#${s1-imm8},#${bit5} */
11441 +  {
11442 +    UBICOM32_INSN_DSP_MACU_S1_IMMEDIATE_DSP_IMM_BIT5, "dsp-macu-s1-immediate-dsp-imm-bit5", "macu", 32,
11443 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11444 +  },
11445 +/* macu${dsp-c}${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),#${bit5} */
11446 +  {
11447 +    UBICOM32_INSN_DSP_MACU_S1_INDIRECT_WITH_INDEX_2_DSP_IMM_BIT5, "dsp-macu-s1-indirect-with-index-2-dsp-imm-bit5", "macu", 32,
11448 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11449 +  },
11450 +/* macu${dsp-c}${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),#${bit5} */
11451 +  {
11452 +    UBICOM32_INSN_DSP_MACU_S1_INDIRECT_WITH_OFFSET_2_DSP_IMM_BIT5, "dsp-macu-s1-indirect-with-offset-2-dsp-imm-bit5", "macu", 32,
11453 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11454 +  },
11455 +/* macu${dsp-c}${dsp-t} ${dsp-destA},(${s1-An}),#${bit5} */
11456 +  {
11457 +    UBICOM32_INSN_DSP_MACU_S1_INDIRECT_2_DSP_IMM_BIT5, "dsp-macu-s1-indirect-2-dsp-imm-bit5", "macu", 32,
11458 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11459 +  },
11460 +/* macu${dsp-c}${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,#${bit5} */
11461 +  {
11462 +    UBICOM32_INSN_DSP_MACU_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_IMM_BIT5, "dsp-macu-s1-indirect-with-post-increment-2-dsp-imm-bit5", "macu", 32,
11463 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11464 +  },
11465 +/* macu${dsp-c}${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,#${bit5} */
11466 +  {
11467 +    UBICOM32_INSN_DSP_MACU_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_IMM_BIT5, "dsp-macu-s1-indirect-with-pre-increment-2-dsp-imm-bit5", "macu", 32,
11468 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11469 +  },
11470 +/* mulu.4 ${dsp-destA},${s1-direct-addr},${dsp-S2-data-reg} */
11471 +  {
11472 +    UBICOM32_INSN_DSP_MULU_4_S1_DIRECT_DSP_SRC2_DATA_REG, "dsp-mulu.4-s1-direct-dsp-src2-data-reg", "mulu.4", 32,
11473 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
11474 +  },
11475 +/* mulu.4 ${dsp-destA},#${s1-imm8},${dsp-S2-data-reg} */
11476 +  {
11477 +    UBICOM32_INSN_DSP_MULU_4_S1_IMMEDIATE_DSP_SRC2_DATA_REG, "dsp-mulu.4-s1-immediate-dsp-src2-data-reg", "mulu.4", 32,
11478 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
11479 +  },
11480 +/* mulu.4 ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-data-reg} */
11481 +  {
11482 +    UBICOM32_INSN_DSP_MULU_4_S1_INDIRECT_WITH_INDEX_4_DSP_SRC2_DATA_REG, "dsp-mulu.4-s1-indirect-with-index-4-dsp-src2-data-reg", "mulu.4", 32,
11483 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
11484 +  },
11485 +/* mulu.4 ${dsp-destA},${s1-imm7-4}(${s1-An}),${dsp-S2-data-reg} */
11486 +  {
11487 +    UBICOM32_INSN_DSP_MULU_4_S1_INDIRECT_WITH_OFFSET_4_DSP_SRC2_DATA_REG, "dsp-mulu.4-s1-indirect-with-offset-4-dsp-src2-data-reg", "mulu.4", 32,
11488 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
11489 +  },
11490 +/* mulu.4 ${dsp-destA},(${s1-An}),${dsp-S2-data-reg} */
11491 +  {
11492 +    UBICOM32_INSN_DSP_MULU_4_S1_INDIRECT_4_DSP_SRC2_DATA_REG, "dsp-mulu.4-s1-indirect-4-dsp-src2-data-reg", "mulu.4", 32,
11493 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
11494 +  },
11495 +/* mulu.4 ${dsp-destA},(${s1-An})${s1-i4-4}++,${dsp-S2-data-reg} */
11496 +  {
11497 +    UBICOM32_INSN_DSP_MULU_4_S1_INDIRECT_WITH_POST_INCREMENT_4_DSP_SRC2_DATA_REG, "dsp-mulu.4-s1-indirect-with-post-increment-4-dsp-src2-data-reg", "mulu.4", 32,
11498 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
11499 +  },
11500 +/* mulu.4 ${dsp-destA},${s1-i4-4}(${s1-An})++,${dsp-S2-data-reg} */
11501 +  {
11502 +    UBICOM32_INSN_DSP_MULU_4_S1_INDIRECT_WITH_PRE_INCREMENT_4_DSP_SRC2_DATA_REG, "dsp-mulu.4-s1-indirect-with-pre-increment-4-dsp-src2-data-reg", "mulu.4", 32,
11503 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
11504 +  },
11505 +/* mulu.4 ${dsp-destA},${s1-direct-addr},${dsp-S2-acc-reg-mul} */
11506 +  {
11507 +    UBICOM32_INSN_DSP_MULU_4_S1_DIRECT_DSP_SRC2_REG_ACC_REG_MUL, "dsp-mulu.4-s1-direct-dsp-src2-reg-acc-reg-mul", "mulu.4", 32,
11508 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
11509 +  },
11510 +/* mulu.4 ${dsp-destA},#${s1-imm8},${dsp-S2-acc-reg-mul} */
11511 +  {
11512 +    UBICOM32_INSN_DSP_MULU_4_S1_IMMEDIATE_DSP_SRC2_REG_ACC_REG_MUL, "dsp-mulu.4-s1-immediate-dsp-src2-reg-acc-reg-mul", "mulu.4", 32,
11513 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
11514 +  },
11515 +/* mulu.4 ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-acc-reg-mul} */
11516 +  {
11517 +    UBICOM32_INSN_DSP_MULU_4_S1_INDIRECT_WITH_INDEX_4_DSP_SRC2_REG_ACC_REG_MUL, "dsp-mulu.4-s1-indirect-with-index-4-dsp-src2-reg-acc-reg-mul", "mulu.4", 32,
11518 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
11519 +  },
11520 +/* mulu.4 ${dsp-destA},${s1-imm7-4}(${s1-An}),${dsp-S2-acc-reg-mul} */
11521 +  {
11522 +    UBICOM32_INSN_DSP_MULU_4_S1_INDIRECT_WITH_OFFSET_4_DSP_SRC2_REG_ACC_REG_MUL, "dsp-mulu.4-s1-indirect-with-offset-4-dsp-src2-reg-acc-reg-mul", "mulu.4", 32,
11523 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
11524 +  },
11525 +/* mulu.4 ${dsp-destA},(${s1-An}),${dsp-S2-acc-reg-mul} */
11526 +  {
11527 +    UBICOM32_INSN_DSP_MULU_4_S1_INDIRECT_4_DSP_SRC2_REG_ACC_REG_MUL, "dsp-mulu.4-s1-indirect-4-dsp-src2-reg-acc-reg-mul", "mulu.4", 32,
11528 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
11529 +  },
11530 +/* mulu.4 ${dsp-destA},(${s1-An})${s1-i4-4}++,${dsp-S2-acc-reg-mul} */
11531 +  {
11532 +    UBICOM32_INSN_DSP_MULU_4_S1_INDIRECT_WITH_POST_INCREMENT_4_DSP_SRC2_REG_ACC_REG_MUL, "dsp-mulu.4-s1-indirect-with-post-increment-4-dsp-src2-reg-acc-reg-mul", "mulu.4", 32,
11533 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
11534 +  },
11535 +/* mulu.4 ${dsp-destA},${s1-i4-4}(${s1-An})++,${dsp-S2-acc-reg-mul} */
11536 +  {
11537 +    UBICOM32_INSN_DSP_MULU_4_S1_INDIRECT_WITH_PRE_INCREMENT_4_DSP_SRC2_REG_ACC_REG_MUL, "dsp-mulu.4-s1-indirect-with-pre-increment-4-dsp-src2-reg-acc-reg-mul", "mulu.4", 32,
11538 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
11539 +  },
11540 +/* mulu.4 ${dsp-destA},${s1-direct-addr},#${bit5} */
11541 +  {
11542 +    UBICOM32_INSN_DSP_MULU_4_S1_DIRECT_DSP_IMM_BIT5, "dsp-mulu.4-s1-direct-dsp-imm-bit5", "mulu.4", 32,
11543 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
11544 +  },
11545 +/* mulu.4 ${dsp-destA},#${s1-imm8},#${bit5} */
11546 +  {
11547 +    UBICOM32_INSN_DSP_MULU_4_S1_IMMEDIATE_DSP_IMM_BIT5, "dsp-mulu.4-s1-immediate-dsp-imm-bit5", "mulu.4", 32,
11548 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
11549 +  },
11550 +/* mulu.4 ${dsp-destA},(${s1-An},${s1-r}),#${bit5} */
11551 +  {
11552 +    UBICOM32_INSN_DSP_MULU_4_S1_INDIRECT_WITH_INDEX_4_DSP_IMM_BIT5, "dsp-mulu.4-s1-indirect-with-index-4-dsp-imm-bit5", "mulu.4", 32,
11553 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
11554 +  },
11555 +/* mulu.4 ${dsp-destA},${s1-imm7-4}(${s1-An}),#${bit5} */
11556 +  {
11557 +    UBICOM32_INSN_DSP_MULU_4_S1_INDIRECT_WITH_OFFSET_4_DSP_IMM_BIT5, "dsp-mulu.4-s1-indirect-with-offset-4-dsp-imm-bit5", "mulu.4", 32,
11558 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
11559 +  },
11560 +/* mulu.4 ${dsp-destA},(${s1-An}),#${bit5} */
11561 +  {
11562 +    UBICOM32_INSN_DSP_MULU_4_S1_INDIRECT_4_DSP_IMM_BIT5, "dsp-mulu.4-s1-indirect-4-dsp-imm-bit5", "mulu.4", 32,
11563 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
11564 +  },
11565 +/* mulu.4 ${dsp-destA},(${s1-An})${s1-i4-4}++,#${bit5} */
11566 +  {
11567 +    UBICOM32_INSN_DSP_MULU_4_S1_INDIRECT_WITH_POST_INCREMENT_4_DSP_IMM_BIT5, "dsp-mulu.4-s1-indirect-with-post-increment-4-dsp-imm-bit5", "mulu.4", 32,
11568 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
11569 +  },
11570 +/* mulu.4 ${dsp-destA},${s1-i4-4}(${s1-An})++,#${bit5} */
11571 +  {
11572 +    UBICOM32_INSN_DSP_MULU_4_S1_INDIRECT_WITH_PRE_INCREMENT_4_DSP_IMM_BIT5, "dsp-mulu.4-s1-indirect-with-pre-increment-4-dsp-imm-bit5", "mulu.4", 32,
11573 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
11574 +  },
11575 +/* mulu${dsp-t} ${dsp-destA},${s1-direct-addr},${dsp-S2-data-reg} */
11576 +  {
11577 +    UBICOM32_INSN_DSP_MULU_S1_DIRECT_DSP_SRC2_DATA_REG, "dsp-mulu-s1-direct-dsp-src2-data-reg", "mulu", 32,
11578 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11579 +  },
11580 +/* mulu${dsp-t} ${dsp-destA},#${s1-imm8},${dsp-S2-data-reg} */
11581 +  {
11582 +    UBICOM32_INSN_DSP_MULU_S1_IMMEDIATE_DSP_SRC2_DATA_REG, "dsp-mulu-s1-immediate-dsp-src2-data-reg", "mulu", 32,
11583 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11584 +  },
11585 +/* mulu${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-data-reg} */
11586 +  {
11587 +    UBICOM32_INSN_DSP_MULU_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_DATA_REG, "dsp-mulu-s1-indirect-with-index-2-dsp-src2-data-reg", "mulu", 32,
11588 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11589 +  },
11590 +/* mulu${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),${dsp-S2-data-reg} */
11591 +  {
11592 +    UBICOM32_INSN_DSP_MULU_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_DATA_REG, "dsp-mulu-s1-indirect-with-offset-2-dsp-src2-data-reg", "mulu", 32,
11593 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11594 +  },
11595 +/* mulu${dsp-t} ${dsp-destA},(${s1-An}),${dsp-S2-data-reg} */
11596 +  {
11597 +    UBICOM32_INSN_DSP_MULU_S1_INDIRECT_2_DSP_SRC2_DATA_REG, "dsp-mulu-s1-indirect-2-dsp-src2-data-reg", "mulu", 32,
11598 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11599 +  },
11600 +/* mulu${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,${dsp-S2-data-reg} */
11601 +  {
11602 +    UBICOM32_INSN_DSP_MULU_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_DATA_REG, "dsp-mulu-s1-indirect-with-post-increment-2-dsp-src2-data-reg", "mulu", 32,
11603 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11604 +  },
11605 +/* mulu${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,${dsp-S2-data-reg} */
11606 +  {
11607 +    UBICOM32_INSN_DSP_MULU_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_DATA_REG, "dsp-mulu-s1-indirect-with-pre-increment-2-dsp-src2-data-reg", "mulu", 32,
11608 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11609 +  },
11610 +/* mulu${dsp-t} ${dsp-destA},${s1-direct-addr},${dsp-S2-acc-reg-mul} */
11611 +  {
11612 +    UBICOM32_INSN_DSP_MULU_S1_DIRECT_DSP_SRC2_REG_ACC_REG_MUL, "dsp-mulu-s1-direct-dsp-src2-reg-acc-reg-mul", "mulu", 32,
11613 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11614 +  },
11615 +/* mulu${dsp-t} ${dsp-destA},#${s1-imm8},${dsp-S2-acc-reg-mul} */
11616 +  {
11617 +    UBICOM32_INSN_DSP_MULU_S1_IMMEDIATE_DSP_SRC2_REG_ACC_REG_MUL, "dsp-mulu-s1-immediate-dsp-src2-reg-acc-reg-mul", "mulu", 32,
11618 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11619 +  },
11620 +/* mulu${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-acc-reg-mul} */
11621 +  {
11622 +    UBICOM32_INSN_DSP_MULU_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_REG_ACC_REG_MUL, "dsp-mulu-s1-indirect-with-index-2-dsp-src2-reg-acc-reg-mul", "mulu", 32,
11623 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11624 +  },
11625 +/* mulu${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),${dsp-S2-acc-reg-mul} */
11626 +  {
11627 +    UBICOM32_INSN_DSP_MULU_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_REG_ACC_REG_MUL, "dsp-mulu-s1-indirect-with-offset-2-dsp-src2-reg-acc-reg-mul", "mulu", 32,
11628 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11629 +  },
11630 +/* mulu${dsp-t} ${dsp-destA},(${s1-An}),${dsp-S2-acc-reg-mul} */
11631 +  {
11632 +    UBICOM32_INSN_DSP_MULU_S1_INDIRECT_2_DSP_SRC2_REG_ACC_REG_MUL, "dsp-mulu-s1-indirect-2-dsp-src2-reg-acc-reg-mul", "mulu", 32,
11633 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11634 +  },
11635 +/* mulu${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,${dsp-S2-acc-reg-mul} */
11636 +  {
11637 +    UBICOM32_INSN_DSP_MULU_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_REG_ACC_REG_MUL, "dsp-mulu-s1-indirect-with-post-increment-2-dsp-src2-reg-acc-reg-mul", "mulu", 32,
11638 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11639 +  },
11640 +/* mulu${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,${dsp-S2-acc-reg-mul} */
11641 +  {
11642 +    UBICOM32_INSN_DSP_MULU_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_REG_ACC_REG_MUL, "dsp-mulu-s1-indirect-with-pre-increment-2-dsp-src2-reg-acc-reg-mul", "mulu", 32,
11643 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11644 +  },
11645 +/* mulu${dsp-t} ${dsp-destA},${s1-direct-addr},#${bit5} */
11646 +  {
11647 +    UBICOM32_INSN_DSP_MULU_S1_DIRECT_DSP_IMM_BIT5, "dsp-mulu-s1-direct-dsp-imm-bit5", "mulu", 32,
11648 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11649 +  },
11650 +/* mulu${dsp-t} ${dsp-destA},#${s1-imm8},#${bit5} */
11651 +  {
11652 +    UBICOM32_INSN_DSP_MULU_S1_IMMEDIATE_DSP_IMM_BIT5, "dsp-mulu-s1-immediate-dsp-imm-bit5", "mulu", 32,
11653 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11654 +  },
11655 +/* mulu${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),#${bit5} */
11656 +  {
11657 +    UBICOM32_INSN_DSP_MULU_S1_INDIRECT_WITH_INDEX_2_DSP_IMM_BIT5, "dsp-mulu-s1-indirect-with-index-2-dsp-imm-bit5", "mulu", 32,
11658 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11659 +  },
11660 +/* mulu${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),#${bit5} */
11661 +  {
11662 +    UBICOM32_INSN_DSP_MULU_S1_INDIRECT_WITH_OFFSET_2_DSP_IMM_BIT5, "dsp-mulu-s1-indirect-with-offset-2-dsp-imm-bit5", "mulu", 32,
11663 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11664 +  },
11665 +/* mulu${dsp-t} ${dsp-destA},(${s1-An}),#${bit5} */
11666 +  {
11667 +    UBICOM32_INSN_DSP_MULU_S1_INDIRECT_2_DSP_IMM_BIT5, "dsp-mulu-s1-indirect-2-dsp-imm-bit5", "mulu", 32,
11668 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11669 +  },
11670 +/* mulu${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,#${bit5} */
11671 +  {
11672 +    UBICOM32_INSN_DSP_MULU_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_IMM_BIT5, "dsp-mulu-s1-indirect-with-post-increment-2-dsp-imm-bit5", "mulu", 32,
11673 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11674 +  },
11675 +/* mulu${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,#${bit5} */
11676 +  {
11677 +    UBICOM32_INSN_DSP_MULU_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_IMM_BIT5, "dsp-mulu-s1-indirect-with-pre-increment-2-dsp-imm-bit5", "mulu", 32,
11678 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11679 +  },
11680 +/* macs${dsp-c}${dsp-t} ${dsp-destA},${s1-direct-addr},${dsp-S2-data-reg} */
11681 +  {
11682 +    UBICOM32_INSN_DSP_MACS_S1_DIRECT_DSP_SRC2_DATA_REG, "dsp-macs-s1-direct-dsp-src2-data-reg", "macs", 32,
11683 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11684 +  },
11685 +/* macs${dsp-c}${dsp-t} ${dsp-destA},#${s1-imm8},${dsp-S2-data-reg} */
11686 +  {
11687 +    UBICOM32_INSN_DSP_MACS_S1_IMMEDIATE_DSP_SRC2_DATA_REG, "dsp-macs-s1-immediate-dsp-src2-data-reg", "macs", 32,
11688 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11689 +  },
11690 +/* macs${dsp-c}${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-data-reg} */
11691 +  {
11692 +    UBICOM32_INSN_DSP_MACS_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_DATA_REG, "dsp-macs-s1-indirect-with-index-2-dsp-src2-data-reg", "macs", 32,
11693 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11694 +  },
11695 +/* macs${dsp-c}${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),${dsp-S2-data-reg} */
11696 +  {
11697 +    UBICOM32_INSN_DSP_MACS_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_DATA_REG, "dsp-macs-s1-indirect-with-offset-2-dsp-src2-data-reg", "macs", 32,
11698 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11699 +  },
11700 +/* macs${dsp-c}${dsp-t} ${dsp-destA},(${s1-An}),${dsp-S2-data-reg} */
11701 +  {
11702 +    UBICOM32_INSN_DSP_MACS_S1_INDIRECT_2_DSP_SRC2_DATA_REG, "dsp-macs-s1-indirect-2-dsp-src2-data-reg", "macs", 32,
11703 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11704 +  },
11705 +/* macs${dsp-c}${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,${dsp-S2-data-reg} */
11706 +  {
11707 +    UBICOM32_INSN_DSP_MACS_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_DATA_REG, "dsp-macs-s1-indirect-with-post-increment-2-dsp-src2-data-reg", "macs", 32,
11708 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11709 +  },
11710 +/* macs${dsp-c}${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,${dsp-S2-data-reg} */
11711 +  {
11712 +    UBICOM32_INSN_DSP_MACS_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_DATA_REG, "dsp-macs-s1-indirect-with-pre-increment-2-dsp-src2-data-reg", "macs", 32,
11713 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11714 +  },
11715 +/* macs${dsp-c}${dsp-t} ${dsp-destA},${s1-direct-addr},${dsp-S2-acc-reg-mul} */
11716 +  {
11717 +    UBICOM32_INSN_DSP_MACS_S1_DIRECT_DSP_SRC2_REG_ACC_REG_MUL, "dsp-macs-s1-direct-dsp-src2-reg-acc-reg-mul", "macs", 32,
11718 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11719 +  },
11720 +/* macs${dsp-c}${dsp-t} ${dsp-destA},#${s1-imm8},${dsp-S2-acc-reg-mul} */
11721 +  {
11722 +    UBICOM32_INSN_DSP_MACS_S1_IMMEDIATE_DSP_SRC2_REG_ACC_REG_MUL, "dsp-macs-s1-immediate-dsp-src2-reg-acc-reg-mul", "macs", 32,
11723 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11724 +  },
11725 +/* macs${dsp-c}${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-acc-reg-mul} */
11726 +  {
11727 +    UBICOM32_INSN_DSP_MACS_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_REG_ACC_REG_MUL, "dsp-macs-s1-indirect-with-index-2-dsp-src2-reg-acc-reg-mul", "macs", 32,
11728 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11729 +  },
11730 +/* macs${dsp-c}${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),${dsp-S2-acc-reg-mul} */
11731 +  {
11732 +    UBICOM32_INSN_DSP_MACS_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_REG_ACC_REG_MUL, "dsp-macs-s1-indirect-with-offset-2-dsp-src2-reg-acc-reg-mul", "macs", 32,
11733 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11734 +  },
11735 +/* macs${dsp-c}${dsp-t} ${dsp-destA},(${s1-An}),${dsp-S2-acc-reg-mul} */
11736 +  {
11737 +    UBICOM32_INSN_DSP_MACS_S1_INDIRECT_2_DSP_SRC2_REG_ACC_REG_MUL, "dsp-macs-s1-indirect-2-dsp-src2-reg-acc-reg-mul", "macs", 32,
11738 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11739 +  },
11740 +/* macs${dsp-c}${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,${dsp-S2-acc-reg-mul} */
11741 +  {
11742 +    UBICOM32_INSN_DSP_MACS_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_REG_ACC_REG_MUL, "dsp-macs-s1-indirect-with-post-increment-2-dsp-src2-reg-acc-reg-mul", "macs", 32,
11743 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11744 +  },
11745 +/* macs${dsp-c}${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,${dsp-S2-acc-reg-mul} */
11746 +  {
11747 +    UBICOM32_INSN_DSP_MACS_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_REG_ACC_REG_MUL, "dsp-macs-s1-indirect-with-pre-increment-2-dsp-src2-reg-acc-reg-mul", "macs", 32,
11748 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11749 +  },
11750 +/* macs${dsp-c}${dsp-t} ${dsp-destA},${s1-direct-addr},#${bit5} */
11751 +  {
11752 +    UBICOM32_INSN_DSP_MACS_S1_DIRECT_DSP_IMM_BIT5, "dsp-macs-s1-direct-dsp-imm-bit5", "macs", 32,
11753 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11754 +  },
11755 +/* macs${dsp-c}${dsp-t} ${dsp-destA},#${s1-imm8},#${bit5} */
11756 +  {
11757 +    UBICOM32_INSN_DSP_MACS_S1_IMMEDIATE_DSP_IMM_BIT5, "dsp-macs-s1-immediate-dsp-imm-bit5", "macs", 32,
11758 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11759 +  },
11760 +/* macs${dsp-c}${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),#${bit5} */
11761 +  {
11762 +    UBICOM32_INSN_DSP_MACS_S1_INDIRECT_WITH_INDEX_2_DSP_IMM_BIT5, "dsp-macs-s1-indirect-with-index-2-dsp-imm-bit5", "macs", 32,
11763 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11764 +  },
11765 +/* macs${dsp-c}${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),#${bit5} */
11766 +  {
11767 +    UBICOM32_INSN_DSP_MACS_S1_INDIRECT_WITH_OFFSET_2_DSP_IMM_BIT5, "dsp-macs-s1-indirect-with-offset-2-dsp-imm-bit5", "macs", 32,
11768 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11769 +  },
11770 +/* macs${dsp-c}${dsp-t} ${dsp-destA},(${s1-An}),#${bit5} */
11771 +  {
11772 +    UBICOM32_INSN_DSP_MACS_S1_INDIRECT_2_DSP_IMM_BIT5, "dsp-macs-s1-indirect-2-dsp-imm-bit5", "macs", 32,
11773 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11774 +  },
11775 +/* macs${dsp-c}${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,#${bit5} */
11776 +  {
11777 +    UBICOM32_INSN_DSP_MACS_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_IMM_BIT5, "dsp-macs-s1-indirect-with-post-increment-2-dsp-imm-bit5", "macs", 32,
11778 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11779 +  },
11780 +/* macs${dsp-c}${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,#${bit5} */
11781 +  {
11782 +    UBICOM32_INSN_DSP_MACS_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_IMM_BIT5, "dsp-macs-s1-indirect-with-pre-increment-2-dsp-imm-bit5", "macs", 32,
11783 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11784 +  },
11785 +/* muls.4 ${dsp-destA},${s1-direct-addr},${dsp-S2-data-reg} */
11786 +  {
11787 +    UBICOM32_INSN_DSP_MULS_4_S1_DIRECT_DSP_SRC2_DATA_REG, "dsp-muls.4-s1-direct-dsp-src2-data-reg", "muls.4", 32,
11788 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
11789 +  },
11790 +/* muls.4 ${dsp-destA},#${s1-imm8},${dsp-S2-data-reg} */
11791 +  {
11792 +    UBICOM32_INSN_DSP_MULS_4_S1_IMMEDIATE_DSP_SRC2_DATA_REG, "dsp-muls.4-s1-immediate-dsp-src2-data-reg", "muls.4", 32,
11793 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
11794 +  },
11795 +/* muls.4 ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-data-reg} */
11796 +  {
11797 +    UBICOM32_INSN_DSP_MULS_4_S1_INDIRECT_WITH_INDEX_4_DSP_SRC2_DATA_REG, "dsp-muls.4-s1-indirect-with-index-4-dsp-src2-data-reg", "muls.4", 32,
11798 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
11799 +  },
11800 +/* muls.4 ${dsp-destA},${s1-imm7-4}(${s1-An}),${dsp-S2-data-reg} */
11801 +  {
11802 +    UBICOM32_INSN_DSP_MULS_4_S1_INDIRECT_WITH_OFFSET_4_DSP_SRC2_DATA_REG, "dsp-muls.4-s1-indirect-with-offset-4-dsp-src2-data-reg", "muls.4", 32,
11803 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
11804 +  },
11805 +/* muls.4 ${dsp-destA},(${s1-An}),${dsp-S2-data-reg} */
11806 +  {
11807 +    UBICOM32_INSN_DSP_MULS_4_S1_INDIRECT_4_DSP_SRC2_DATA_REG, "dsp-muls.4-s1-indirect-4-dsp-src2-data-reg", "muls.4", 32,
11808 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
11809 +  },
11810 +/* muls.4 ${dsp-destA},(${s1-An})${s1-i4-4}++,${dsp-S2-data-reg} */
11811 +  {
11812 +    UBICOM32_INSN_DSP_MULS_4_S1_INDIRECT_WITH_POST_INCREMENT_4_DSP_SRC2_DATA_REG, "dsp-muls.4-s1-indirect-with-post-increment-4-dsp-src2-data-reg", "muls.4", 32,
11813 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
11814 +  },
11815 +/* muls.4 ${dsp-destA},${s1-i4-4}(${s1-An})++,${dsp-S2-data-reg} */
11816 +  {
11817 +    UBICOM32_INSN_DSP_MULS_4_S1_INDIRECT_WITH_PRE_INCREMENT_4_DSP_SRC2_DATA_REG, "dsp-muls.4-s1-indirect-with-pre-increment-4-dsp-src2-data-reg", "muls.4", 32,
11818 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
11819 +  },
11820 +/* muls.4 ${dsp-destA},${s1-direct-addr},${dsp-S2-acc-reg-mul} */
11821 +  {
11822 +    UBICOM32_INSN_DSP_MULS_4_S1_DIRECT_DSP_SRC2_REG_ACC_REG_MUL, "dsp-muls.4-s1-direct-dsp-src2-reg-acc-reg-mul", "muls.4", 32,
11823 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
11824 +  },
11825 +/* muls.4 ${dsp-destA},#${s1-imm8},${dsp-S2-acc-reg-mul} */
11826 +  {
11827 +    UBICOM32_INSN_DSP_MULS_4_S1_IMMEDIATE_DSP_SRC2_REG_ACC_REG_MUL, "dsp-muls.4-s1-immediate-dsp-src2-reg-acc-reg-mul", "muls.4", 32,
11828 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
11829 +  },
11830 +/* muls.4 ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-acc-reg-mul} */
11831 +  {
11832 +    UBICOM32_INSN_DSP_MULS_4_S1_INDIRECT_WITH_INDEX_4_DSP_SRC2_REG_ACC_REG_MUL, "dsp-muls.4-s1-indirect-with-index-4-dsp-src2-reg-acc-reg-mul", "muls.4", 32,
11833 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
11834 +  },
11835 +/* muls.4 ${dsp-destA},${s1-imm7-4}(${s1-An}),${dsp-S2-acc-reg-mul} */
11836 +  {
11837 +    UBICOM32_INSN_DSP_MULS_4_S1_INDIRECT_WITH_OFFSET_4_DSP_SRC2_REG_ACC_REG_MUL, "dsp-muls.4-s1-indirect-with-offset-4-dsp-src2-reg-acc-reg-mul", "muls.4", 32,
11838 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
11839 +  },
11840 +/* muls.4 ${dsp-destA},(${s1-An}),${dsp-S2-acc-reg-mul} */
11841 +  {
11842 +    UBICOM32_INSN_DSP_MULS_4_S1_INDIRECT_4_DSP_SRC2_REG_ACC_REG_MUL, "dsp-muls.4-s1-indirect-4-dsp-src2-reg-acc-reg-mul", "muls.4", 32,
11843 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
11844 +  },
11845 +/* muls.4 ${dsp-destA},(${s1-An})${s1-i4-4}++,${dsp-S2-acc-reg-mul} */
11846 +  {
11847 +    UBICOM32_INSN_DSP_MULS_4_S1_INDIRECT_WITH_POST_INCREMENT_4_DSP_SRC2_REG_ACC_REG_MUL, "dsp-muls.4-s1-indirect-with-post-increment-4-dsp-src2-reg-acc-reg-mul", "muls.4", 32,
11848 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
11849 +  },
11850 +/* muls.4 ${dsp-destA},${s1-i4-4}(${s1-An})++,${dsp-S2-acc-reg-mul} */
11851 +  {
11852 +    UBICOM32_INSN_DSP_MULS_4_S1_INDIRECT_WITH_PRE_INCREMENT_4_DSP_SRC2_REG_ACC_REG_MUL, "dsp-muls.4-s1-indirect-with-pre-increment-4-dsp-src2-reg-acc-reg-mul", "muls.4", 32,
11853 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
11854 +  },
11855 +/* muls.4 ${dsp-destA},${s1-direct-addr},#${bit5} */
11856 +  {
11857 +    UBICOM32_INSN_DSP_MULS_4_S1_DIRECT_DSP_IMM_BIT5, "dsp-muls.4-s1-direct-dsp-imm-bit5", "muls.4", 32,
11858 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
11859 +  },
11860 +/* muls.4 ${dsp-destA},#${s1-imm8},#${bit5} */
11861 +  {
11862 +    UBICOM32_INSN_DSP_MULS_4_S1_IMMEDIATE_DSP_IMM_BIT5, "dsp-muls.4-s1-immediate-dsp-imm-bit5", "muls.4", 32,
11863 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
11864 +  },
11865 +/* muls.4 ${dsp-destA},(${s1-An},${s1-r}),#${bit5} */
11866 +  {
11867 +    UBICOM32_INSN_DSP_MULS_4_S1_INDIRECT_WITH_INDEX_4_DSP_IMM_BIT5, "dsp-muls.4-s1-indirect-with-index-4-dsp-imm-bit5", "muls.4", 32,
11868 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
11869 +  },
11870 +/* muls.4 ${dsp-destA},${s1-imm7-4}(${s1-An}),#${bit5} */
11871 +  {
11872 +    UBICOM32_INSN_DSP_MULS_4_S1_INDIRECT_WITH_OFFSET_4_DSP_IMM_BIT5, "dsp-muls.4-s1-indirect-with-offset-4-dsp-imm-bit5", "muls.4", 32,
11873 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
11874 +  },
11875 +/* muls.4 ${dsp-destA},(${s1-An}),#${bit5} */
11876 +  {
11877 +    UBICOM32_INSN_DSP_MULS_4_S1_INDIRECT_4_DSP_IMM_BIT5, "dsp-muls.4-s1-indirect-4-dsp-imm-bit5", "muls.4", 32,
11878 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
11879 +  },
11880 +/* muls.4 ${dsp-destA},(${s1-An})${s1-i4-4}++,#${bit5} */
11881 +  {
11882 +    UBICOM32_INSN_DSP_MULS_4_S1_INDIRECT_WITH_POST_INCREMENT_4_DSP_IMM_BIT5, "dsp-muls.4-s1-indirect-with-post-increment-4-dsp-imm-bit5", "muls.4", 32,
11883 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
11884 +  },
11885 +/* muls.4 ${dsp-destA},${s1-i4-4}(${s1-An})++,#${bit5} */
11886 +  {
11887 +    UBICOM32_INSN_DSP_MULS_4_S1_INDIRECT_WITH_PRE_INCREMENT_4_DSP_IMM_BIT5, "dsp-muls.4-s1-indirect-with-pre-increment-4-dsp-imm-bit5", "muls.4", 32,
11888 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
11889 +  },
11890 +/* muls${dsp-t} ${dsp-destA},${s1-direct-addr},${dsp-S2-data-reg} */
11891 +  {
11892 +    UBICOM32_INSN_DSP_MULS_S1_DIRECT_DSP_SRC2_DATA_REG, "dsp-muls-s1-direct-dsp-src2-data-reg", "muls", 32,
11893 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11894 +  },
11895 +/* muls${dsp-t} ${dsp-destA},#${s1-imm8},${dsp-S2-data-reg} */
11896 +  {
11897 +    UBICOM32_INSN_DSP_MULS_S1_IMMEDIATE_DSP_SRC2_DATA_REG, "dsp-muls-s1-immediate-dsp-src2-data-reg", "muls", 32,
11898 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11899 +  },
11900 +/* muls${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-data-reg} */
11901 +  {
11902 +    UBICOM32_INSN_DSP_MULS_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_DATA_REG, "dsp-muls-s1-indirect-with-index-2-dsp-src2-data-reg", "muls", 32,
11903 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11904 +  },
11905 +/* muls${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),${dsp-S2-data-reg} */
11906 +  {
11907 +    UBICOM32_INSN_DSP_MULS_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_DATA_REG, "dsp-muls-s1-indirect-with-offset-2-dsp-src2-data-reg", "muls", 32,
11908 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11909 +  },
11910 +/* muls${dsp-t} ${dsp-destA},(${s1-An}),${dsp-S2-data-reg} */
11911 +  {
11912 +    UBICOM32_INSN_DSP_MULS_S1_INDIRECT_2_DSP_SRC2_DATA_REG, "dsp-muls-s1-indirect-2-dsp-src2-data-reg", "muls", 32,
11913 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11914 +  },
11915 +/* muls${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,${dsp-S2-data-reg} */
11916 +  {
11917 +    UBICOM32_INSN_DSP_MULS_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_DATA_REG, "dsp-muls-s1-indirect-with-post-increment-2-dsp-src2-data-reg", "muls", 32,
11918 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11919 +  },
11920 +/* muls${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,${dsp-S2-data-reg} */
11921 +  {
11922 +    UBICOM32_INSN_DSP_MULS_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_DATA_REG, "dsp-muls-s1-indirect-with-pre-increment-2-dsp-src2-data-reg", "muls", 32,
11923 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11924 +  },
11925 +/* muls${dsp-t} ${dsp-destA},${s1-direct-addr},${dsp-S2-acc-reg-mul} */
11926 +  {
11927 +    UBICOM32_INSN_DSP_MULS_S1_DIRECT_DSP_SRC2_REG_ACC_REG_MUL, "dsp-muls-s1-direct-dsp-src2-reg-acc-reg-mul", "muls", 32,
11928 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11929 +  },
11930 +/* muls${dsp-t} ${dsp-destA},#${s1-imm8},${dsp-S2-acc-reg-mul} */
11931 +  {
11932 +    UBICOM32_INSN_DSP_MULS_S1_IMMEDIATE_DSP_SRC2_REG_ACC_REG_MUL, "dsp-muls-s1-immediate-dsp-src2-reg-acc-reg-mul", "muls", 32,
11933 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11934 +  },
11935 +/* muls${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-acc-reg-mul} */
11936 +  {
11937 +    UBICOM32_INSN_DSP_MULS_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_REG_ACC_REG_MUL, "dsp-muls-s1-indirect-with-index-2-dsp-src2-reg-acc-reg-mul", "muls", 32,
11938 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11939 +  },
11940 +/* muls${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),${dsp-S2-acc-reg-mul} */
11941 +  {
11942 +    UBICOM32_INSN_DSP_MULS_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_REG_ACC_REG_MUL, "dsp-muls-s1-indirect-with-offset-2-dsp-src2-reg-acc-reg-mul", "muls", 32,
11943 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11944 +  },
11945 +/* muls${dsp-t} ${dsp-destA},(${s1-An}),${dsp-S2-acc-reg-mul} */
11946 +  {
11947 +    UBICOM32_INSN_DSP_MULS_S1_INDIRECT_2_DSP_SRC2_REG_ACC_REG_MUL, "dsp-muls-s1-indirect-2-dsp-src2-reg-acc-reg-mul", "muls", 32,
11948 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11949 +  },
11950 +/* muls${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,${dsp-S2-acc-reg-mul} */
11951 +  {
11952 +    UBICOM32_INSN_DSP_MULS_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_REG_ACC_REG_MUL, "dsp-muls-s1-indirect-with-post-increment-2-dsp-src2-reg-acc-reg-mul", "muls", 32,
11953 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11954 +  },
11955 +/* muls${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,${dsp-S2-acc-reg-mul} */
11956 +  {
11957 +    UBICOM32_INSN_DSP_MULS_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_REG_ACC_REG_MUL, "dsp-muls-s1-indirect-with-pre-increment-2-dsp-src2-reg-acc-reg-mul", "muls", 32,
11958 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11959 +  },
11960 +/* muls${dsp-t} ${dsp-destA},${s1-direct-addr},#${bit5} */
11961 +  {
11962 +    UBICOM32_INSN_DSP_MULS_S1_DIRECT_DSP_IMM_BIT5, "dsp-muls-s1-direct-dsp-imm-bit5", "muls", 32,
11963 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11964 +  },
11965 +/* muls${dsp-t} ${dsp-destA},#${s1-imm8},#${bit5} */
11966 +  {
11967 +    UBICOM32_INSN_DSP_MULS_S1_IMMEDIATE_DSP_IMM_BIT5, "dsp-muls-s1-immediate-dsp-imm-bit5", "muls", 32,
11968 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11969 +  },
11970 +/* muls${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),#${bit5} */
11971 +  {
11972 +    UBICOM32_INSN_DSP_MULS_S1_INDIRECT_WITH_INDEX_2_DSP_IMM_BIT5, "dsp-muls-s1-indirect-with-index-2-dsp-imm-bit5", "muls", 32,
11973 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11974 +  },
11975 +/* muls${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),#${bit5} */
11976 +  {
11977 +    UBICOM32_INSN_DSP_MULS_S1_INDIRECT_WITH_OFFSET_2_DSP_IMM_BIT5, "dsp-muls-s1-indirect-with-offset-2-dsp-imm-bit5", "muls", 32,
11978 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11979 +  },
11980 +/* muls${dsp-t} ${dsp-destA},(${s1-An}),#${bit5} */
11981 +  {
11982 +    UBICOM32_INSN_DSP_MULS_S1_INDIRECT_2_DSP_IMM_BIT5, "dsp-muls-s1-indirect-2-dsp-imm-bit5", "muls", 32,
11983 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11984 +  },
11985 +/* muls${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,#${bit5} */
11986 +  {
11987 +    UBICOM32_INSN_DSP_MULS_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_IMM_BIT5, "dsp-muls-s1-indirect-with-post-increment-2-dsp-imm-bit5", "muls", 32,
11988 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11989 +  },
11990 +/* muls${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,#${bit5} */
11991 +  {
11992 +    UBICOM32_INSN_DSP_MULS_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_IMM_BIT5, "dsp-muls-s1-indirect-with-pre-increment-2-dsp-imm-bit5", "muls", 32,
11993 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
11994 +  },
11995 +/* ierase (${d-An},${d-r}) */
11996 +  {
11997 +    UBICOM32_INSN_IERASE_D_PEA_INDIRECT_WITH_INDEX, "ierase-d-pea-indirect-with-index", "ierase", 32,
11998 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
11999 +  },
12000 +/* ierase ${d-imm7-4}(${d-An}) */
12001 +  {
12002 +    UBICOM32_INSN_IERASE_D_PEA_INDIRECT_WITH_OFFSET, "ierase-d-pea-indirect-with-offset", "ierase", 32,
12003 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
12004 +  },
12005 +/* ierase (${d-An}) */
12006 +  {
12007 +    UBICOM32_INSN_IERASE_D_PEA_INDIRECT, "ierase-d-pea-indirect", "ierase", 32,
12008 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
12009 +  },
12010 +/* ierase (${d-An})${d-i4-4}++ */
12011 +  {
12012 +    UBICOM32_INSN_IERASE_D_PEA_INDIRECT_WITH_POST_INCREMENT, "ierase-d-pea-indirect-with-post-increment", "ierase", 32,
12013 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
12014 +  },
12015 +/* ierase ${d-i4-4}(${d-An})++ */
12016 +  {
12017 +    UBICOM32_INSN_IERASE_D_PEA_INDIRECT_WITH_PRE_INCREMENT, "ierase-d-pea-indirect-with-pre-increment", "ierase", 32,
12018 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
12019 +  },
12020 +/* iread (${s1-An}) */
12021 +  {
12022 +    UBICOM32_INSN_IREAD_S1_EA_INDIRECT, "iread-s1-ea-indirect", "iread", 32,
12023 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
12024 +  },
12025 +/* iread (${s1-An},${s1-r}) */
12026 +  {
12027 +    UBICOM32_INSN_IREAD_S1_EA_INDIRECT_WITH_INDEX_4, "iread-s1-ea-indirect-with-index-4", "iread", 32,
12028 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
12029 +  },
12030 +/* iread (${s1-An})${s1-i4-4}++ */
12031 +  {
12032 +    UBICOM32_INSN_IREAD_S1_EA_INDIRECT_WITH_POST_INCREMENT_4, "iread-s1-ea-indirect-with-post-increment-4", "iread", 32,
12033 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
12034 +  },
12035 +/* iread ${s1-i4-4}(${s1-An})++ */
12036 +  {
12037 +    UBICOM32_INSN_IREAD_S1_EA_INDIRECT_WITH_PRE_INCREMENT_4, "iread-s1-ea-indirect-with-pre-increment-4", "iread", 32,
12038 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
12039 +  },
12040 +/* iread ${s1-imm7-4}(${s1-An}) */
12041 +  {
12042 +    UBICOM32_INSN_IREAD_S1_EA_INDIRECT_WITH_OFFSET_4, "iread-s1-ea-indirect-with-offset-4", "iread", 32,
12043 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
12044 +  },
12045 +/* iwrite (${d-An},${d-r}),${s1-direct-addr} */
12046 +  {
12047 +    UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_INDEX_S1_DIRECT, "iwrite-d-pea-indirect-with-index-s1-direct", "iwrite", 32,
12048 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
12049 +  },
12050 +/* iwrite ${d-imm7-4}(${d-An}),${s1-direct-addr} */
12051 +  {
12052 +    UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_OFFSET_S1_DIRECT, "iwrite-d-pea-indirect-with-offset-s1-direct", "iwrite", 32,
12053 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
12054 +  },
12055 +/* iwrite (${d-An}),${s1-direct-addr} */
12056 +  {
12057 +    UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_S1_DIRECT, "iwrite-d-pea-indirect-s1-direct", "iwrite", 32,
12058 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
12059 +  },
12060 +/* iwrite (${d-An})${d-i4-4}++,${s1-direct-addr} */
12061 +  {
12062 +    UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_POST_INCREMENT_S1_DIRECT, "iwrite-d-pea-indirect-with-post-increment-s1-direct", "iwrite", 32,
12063 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
12064 +  },
12065 +/* iwrite ${d-i4-4}(${d-An})++,${s1-direct-addr} */
12066 +  {
12067 +    UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_PRE_INCREMENT_S1_DIRECT, "iwrite-d-pea-indirect-with-pre-increment-s1-direct", "iwrite", 32,
12068 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
12069 +  },
12070 +/* iwrite (${d-An},${d-r}),#${s1-imm8} */
12071 +  {
12072 +    UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_INDEX_S1_IMMEDIATE, "iwrite-d-pea-indirect-with-index-s1-immediate", "iwrite", 32,
12073 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
12074 +  },
12075 +/* iwrite ${d-imm7-4}(${d-An}),#${s1-imm8} */
12076 +  {
12077 +    UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_OFFSET_S1_IMMEDIATE, "iwrite-d-pea-indirect-with-offset-s1-immediate", "iwrite", 32,
12078 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
12079 +  },
12080 +/* iwrite (${d-An}),#${s1-imm8} */
12081 +  {
12082 +    UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_S1_IMMEDIATE, "iwrite-d-pea-indirect-s1-immediate", "iwrite", 32,
12083 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
12084 +  },
12085 +/* iwrite (${d-An})${d-i4-4}++,#${s1-imm8} */
12086 +  {
12087 +    UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_POST_INCREMENT_S1_IMMEDIATE, "iwrite-d-pea-indirect-with-post-increment-s1-immediate", "iwrite", 32,
12088 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
12089 +  },
12090 +/* iwrite ${d-i4-4}(${d-An})++,#${s1-imm8} */
12091 +  {
12092 +    UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_PRE_INCREMENT_S1_IMMEDIATE, "iwrite-d-pea-indirect-with-pre-increment-s1-immediate", "iwrite", 32,
12093 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
12094 +  },
12095 +/* iwrite (${d-An},${d-r}),(${s1-An},${s1-r}) */
12096 +  {
12097 +    UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_INDEX_S1_INDIRECT_WITH_INDEX_4, "iwrite-d-pea-indirect-with-index-s1-indirect-with-index-4", "iwrite", 32,
12098 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
12099 +  },
12100 +/* iwrite ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}) */
12101 +  {
12102 +    UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_OFFSET_S1_INDIRECT_WITH_INDEX_4, "iwrite-d-pea-indirect-with-offset-s1-indirect-with-index-4", "iwrite", 32,
12103 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
12104 +  },
12105 +/* iwrite (${d-An}),(${s1-An},${s1-r}) */
12106 +  {
12107 +    UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_S1_INDIRECT_WITH_INDEX_4, "iwrite-d-pea-indirect-s1-indirect-with-index-4", "iwrite", 32,
12108 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
12109 +  },
12110 +/* iwrite (${d-An})${d-i4-4}++,(${s1-An},${s1-r}) */
12111 +  {
12112 +    UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_POST_INCREMENT_S1_INDIRECT_WITH_INDEX_4, "iwrite-d-pea-indirect-with-post-increment-s1-indirect-with-index-4", "iwrite", 32,
12113 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
12114 +  },
12115 +/* iwrite ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}) */
12116 +  {
12117 +    UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_PRE_INCREMENT_S1_INDIRECT_WITH_INDEX_4, "iwrite-d-pea-indirect-with-pre-increment-s1-indirect-with-index-4", "iwrite", 32,
12118 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
12119 +  },
12120 +/* iwrite (${d-An},${d-r}),${s1-imm7-4}(${s1-An}) */
12121 +  {
12122 +    UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_INDEX_S1_INDIRECT_WITH_OFFSET_4, "iwrite-d-pea-indirect-with-index-s1-indirect-with-offset-4", "iwrite", 32,
12123 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
12124 +  },
12125 +/* iwrite ${d-imm7-4}(${d-An}),${s1-imm7-4}(${s1-An}) */
12126 +  {
12127 +    UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_OFFSET_S1_INDIRECT_WITH_OFFSET_4, "iwrite-d-pea-indirect-with-offset-s1-indirect-with-offset-4", "iwrite", 32,
12128 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
12129 +  },
12130 +/* iwrite (${d-An}),${s1-imm7-4}(${s1-An}) */
12131 +  {
12132 +    UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_S1_INDIRECT_WITH_OFFSET_4, "iwrite-d-pea-indirect-s1-indirect-with-offset-4", "iwrite", 32,
12133 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
12134 +  },
12135 +/* iwrite (${d-An})${d-i4-4}++,${s1-imm7-4}(${s1-An}) */
12136 +  {
12137 +    UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_POST_INCREMENT_S1_INDIRECT_WITH_OFFSET_4, "iwrite-d-pea-indirect-with-post-increment-s1-indirect-with-offset-4", "iwrite", 32,
12138 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
12139 +  },
12140 +/* iwrite ${d-i4-4}(${d-An})++,${s1-imm7-4}(${s1-An}) */
12141 +  {
12142 +    UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_PRE_INCREMENT_S1_INDIRECT_WITH_OFFSET_4, "iwrite-d-pea-indirect-with-pre-increment-s1-indirect-with-offset-4", "iwrite", 32,
12143 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
12144 +  },
12145 +/* iwrite (${d-An},${d-r}),(${s1-An}) */
12146 +  {
12147 +    UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_INDEX_S1_INDIRECT_4, "iwrite-d-pea-indirect-with-index-s1-indirect-4", "iwrite", 32,
12148 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
12149 +  },
12150 +/* iwrite ${d-imm7-4}(${d-An}),(${s1-An}) */
12151 +  {
12152 +    UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_OFFSET_S1_INDIRECT_4, "iwrite-d-pea-indirect-with-offset-s1-indirect-4", "iwrite", 32,
12153 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
12154 +  },
12155 +/* iwrite (${d-An}),(${s1-An}) */
12156 +  {
12157 +    UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_S1_INDIRECT_4, "iwrite-d-pea-indirect-s1-indirect-4", "iwrite", 32,
12158 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
12159 +  },
12160 +/* iwrite (${d-An})${d-i4-4}++,(${s1-An}) */
12161 +  {
12162 +    UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_POST_INCREMENT_S1_INDIRECT_4, "iwrite-d-pea-indirect-with-post-increment-s1-indirect-4", "iwrite", 32,
12163 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
12164 +  },
12165 +/* iwrite ${d-i4-4}(${d-An})++,(${s1-An}) */
12166 +  {
12167 +    UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_PRE_INCREMENT_S1_INDIRECT_4, "iwrite-d-pea-indirect-with-pre-increment-s1-indirect-4", "iwrite", 32,
12168 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
12169 +  },
12170 +/* iwrite (${d-An},${d-r}),(${s1-An})${s1-i4-4}++ */
12171 +  {
12172 +    UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_INDEX_S1_INDIRECT_WITH_POST_INCREMENT_4, "iwrite-d-pea-indirect-with-index-s1-indirect-with-post-increment-4", "iwrite", 32,
12173 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
12174 +  },
12175 +/* iwrite ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-4}++ */
12176 +  {
12177 +    UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_OFFSET_S1_INDIRECT_WITH_POST_INCREMENT_4, "iwrite-d-pea-indirect-with-offset-s1-indirect-with-post-increment-4", "iwrite", 32,
12178 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
12179 +  },
12180 +/* iwrite (${d-An}),(${s1-An})${s1-i4-4}++ */
12181 +  {
12182 +    UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4, "iwrite-d-pea-indirect-s1-indirect-with-post-increment-4", "iwrite", 32,
12183 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
12184 +  },
12185 +/* iwrite (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-4}++ */
12186 +  {
12187 +    UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_POST_INCREMENT_S1_INDIRECT_WITH_POST_INCREMENT_4, "iwrite-d-pea-indirect-with-post-increment-s1-indirect-with-post-increment-4", "iwrite", 32,
12188 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
12189 +  },
12190 +/* iwrite ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-4}++ */
12191 +  {
12192 +    UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_PRE_INCREMENT_S1_INDIRECT_WITH_POST_INCREMENT_4, "iwrite-d-pea-indirect-with-pre-increment-s1-indirect-with-post-increment-4", "iwrite", 32,
12193 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
12194 +  },
12195 +/* iwrite (${d-An},${d-r}),${s1-i4-4}(${s1-An})++ */
12196 +  {
12197 +    UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_INDEX_S1_INDIRECT_WITH_PRE_INCREMENT_4, "iwrite-d-pea-indirect-with-index-s1-indirect-with-pre-increment-4", "iwrite", 32,
12198 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
12199 +  },
12200 +/* iwrite ${d-imm7-4}(${d-An}),${s1-i4-4}(${s1-An})++ */
12201 +  {
12202 +    UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_OFFSET_S1_INDIRECT_WITH_PRE_INCREMENT_4, "iwrite-d-pea-indirect-with-offset-s1-indirect-with-pre-increment-4", "iwrite", 32,
12203 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
12204 +  },
12205 +/* iwrite (${d-An}),${s1-i4-4}(${s1-An})++ */
12206 +  {
12207 +    UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4, "iwrite-d-pea-indirect-s1-indirect-with-pre-increment-4", "iwrite", 32,
12208 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
12209 +  },
12210 +/* iwrite (${d-An})${d-i4-4}++,${s1-i4-4}(${s1-An})++ */
12211 +  {
12212 +    UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_POST_INCREMENT_S1_INDIRECT_WITH_PRE_INCREMENT_4, "iwrite-d-pea-indirect-with-post-increment-s1-indirect-with-pre-increment-4", "iwrite", 32,
12213 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
12214 +  },
12215 +/* iwrite ${d-i4-4}(${d-An})++,${s1-i4-4}(${s1-An})++ */
12216 +  {
12217 +    UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_PRE_INCREMENT_S1_INDIRECT_WITH_PRE_INCREMENT_4, "iwrite-d-pea-indirect-with-pre-increment-s1-indirect-with-pre-increment-4", "iwrite", 32,
12218 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
12219 +  },
12220 +/* setcsr ${s1-direct-addr} */
12221 +  {
12222 +    UBICOM32_INSN_SETCSR_S1_DIRECT, "setcsr-s1-direct", "setcsr", 32,
12223 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
12224 +  },
12225 +/* setcsr #${s1-imm8} */
12226 +  {
12227 +    UBICOM32_INSN_SETCSR_S1_IMMEDIATE, "setcsr-s1-immediate", "setcsr", 32,
12228 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
12229 +  },
12230 +/* setcsr (${s1-An},${s1-r}) */
12231 +  {
12232 +    UBICOM32_INSN_SETCSR_S1_INDIRECT_WITH_INDEX_4, "setcsr-s1-indirect-with-index-4", "setcsr", 32,
12233 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
12234 +  },
12235 +/* setcsr ${s1-imm7-4}(${s1-An}) */
12236 +  {
12237 +    UBICOM32_INSN_SETCSR_S1_INDIRECT_WITH_OFFSET_4, "setcsr-s1-indirect-with-offset-4", "setcsr", 32,
12238 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
12239 +  },
12240 +/* setcsr (${s1-An}) */
12241 +  {
12242 +    UBICOM32_INSN_SETCSR_S1_INDIRECT_4, "setcsr-s1-indirect-4", "setcsr", 32,
12243 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
12244 +  },
12245 +/* setcsr (${s1-An})${s1-i4-4}++ */
12246 +  {
12247 +    UBICOM32_INSN_SETCSR_S1_INDIRECT_WITH_POST_INCREMENT_4, "setcsr-s1-indirect-with-post-increment-4", "setcsr", 32,
12248 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
12249 +  },
12250 +/* setcsr ${s1-i4-4}(${s1-An})++ */
12251 +  {
12252 +    UBICOM32_INSN_SETCSR_S1_INDIRECT_WITH_PRE_INCREMENT_4, "setcsr-s1-indirect-with-pre-increment-4", "setcsr", 32,
12253 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
12254 +  },
12255 +/* bkpt ${s1-direct-addr} */
12256 +  {
12257 +    UBICOM32_INSN_BKPT_S1_DIRECT, "bkpt-s1-direct", "bkpt", 32,
12258 +    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
12259 +  },
12260 +/* bkpt #${s1-imm8} */
12261 +  {
12262 +    UBICOM32_INSN_BKPT_S1_IMMEDIATE, "bkpt-s1-immediate", "bkpt", 32,
12263 +    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
12264 +  },
12265 +/* bkpt (${s1-An},${s1-r}) */
12266 +  {
12267 +    UBICOM32_INSN_BKPT_S1_INDIRECT_WITH_INDEX_4, "bkpt-s1-indirect-with-index-4", "bkpt", 32,
12268 +    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
12269 +  },
12270 +/* bkpt ${s1-imm7-4}(${s1-An}) */
12271 +  {
12272 +    UBICOM32_INSN_BKPT_S1_INDIRECT_WITH_OFFSET_4, "bkpt-s1-indirect-with-offset-4", "bkpt", 32,
12273 +    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
12274 +  },
12275 +/* bkpt (${s1-An}) */
12276 +  {
12277 +    UBICOM32_INSN_BKPT_S1_INDIRECT_4, "bkpt-s1-indirect-4", "bkpt", 32,
12278 +    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
12279 +  },
12280 +/* bkpt (${s1-An})${s1-i4-4}++ */
12281 +  {
12282 +    UBICOM32_INSN_BKPT_S1_INDIRECT_WITH_POST_INCREMENT_4, "bkpt-s1-indirect-with-post-increment-4", "bkpt", 32,
12283 +    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
12284 +  },
12285 +/* bkpt ${s1-i4-4}(${s1-An})++ */
12286 +  {
12287 +    UBICOM32_INSN_BKPT_S1_INDIRECT_WITH_PRE_INCREMENT_4, "bkpt-s1-indirect-with-pre-increment-4", "bkpt", 32,
12288 +    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
12289 +  },
12290 +/* ret ${s1-direct-addr} */
12291 +  {
12292 +    UBICOM32_INSN_RET_S1_DIRECT, "ret-s1-direct", "ret", 32,
12293 +    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
12294 +  },
12295 +/* ret #${s1-imm8} */
12296 +  {
12297 +    UBICOM32_INSN_RET_S1_IMMEDIATE, "ret-s1-immediate", "ret", 32,
12298 +    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
12299 +  },
12300 +/* ret (${s1-An},${s1-r}) */
12301 +  {
12302 +    UBICOM32_INSN_RET_S1_INDIRECT_WITH_INDEX_4, "ret-s1-indirect-with-index-4", "ret", 32,
12303 +    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
12304 +  },
12305 +/* ret ${s1-imm7-4}(${s1-An}) */
12306 +  {
12307 +    UBICOM32_INSN_RET_S1_INDIRECT_WITH_OFFSET_4, "ret-s1-indirect-with-offset-4", "ret", 32,
12308 +    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
12309 +  },
12310 +/* ret (${s1-An}) */
12311 +  {
12312 +    UBICOM32_INSN_RET_S1_INDIRECT_4, "ret-s1-indirect-4", "ret", 32,
12313 +    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
12314 +  },
12315 +/* ret (${s1-An})${s1-i4-4}++ */
12316 +  {
12317 +    UBICOM32_INSN_RET_S1_INDIRECT_WITH_POST_INCREMENT_4, "ret-s1-indirect-with-post-increment-4", "ret", 32,
12318 +    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
12319 +  },
12320 +/* ret ${s1-i4-4}(${s1-An})++ */
12321 +  {
12322 +    UBICOM32_INSN_RET_S1_INDIRECT_WITH_PRE_INCREMENT_4, "ret-s1-indirect-with-pre-increment-4", "ret", 32,
12323 +    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
12324 +  },
12325 +/* movea ${d-direct-addr},${s1-direct-addr} */
12326 +  {
12327 +    UBICOM32_INSN_MOVEA_D_DIRECT_S1_DIRECT, "movea-d-direct-s1-direct", "movea", 32,
12328 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
12329 +  },
12330 +/* movea #${d-imm8},${s1-direct-addr} */
12331 +  {
12332 +    UBICOM32_INSN_MOVEA_D_IMMEDIATE_4_S1_DIRECT, "movea-d-immediate-4-s1-direct", "movea", 32,
12333 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
12334 +  },
12335 +/* movea (${d-An},${d-r}),${s1-direct-addr} */
12336 +  {
12337 +    UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_INDEX_4_S1_DIRECT, "movea-d-indirect-with-index-4-s1-direct", "movea", 32,
12338 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
12339 +  },
12340 +/* movea ${d-imm7-4}(${d-An}),${s1-direct-addr} */
12341 +  {
12342 +    UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_OFFSET_4_S1_DIRECT, "movea-d-indirect-with-offset-4-s1-direct", "movea", 32,
12343 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
12344 +  },
12345 +/* movea (${d-An}),${s1-direct-addr} */
12346 +  {
12347 +    UBICOM32_INSN_MOVEA_D_INDIRECT_4_S1_DIRECT, "movea-d-indirect-4-s1-direct", "movea", 32,
12348 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
12349 +  },
12350 +/* movea (${d-An})${d-i4-4}++,${s1-direct-addr} */
12351 +  {
12352 +    UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_POST_INCREMENT_4_S1_DIRECT, "movea-d-indirect-with-post-increment-4-s1-direct", "movea", 32,
12353 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
12354 +  },
12355 +/* movea ${d-i4-4}(${d-An})++,${s1-direct-addr} */
12356 +  {
12357 +    UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_DIRECT, "movea-d-indirect-with-pre-increment-4-s1-direct", "movea", 32,
12358 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
12359 +  },
12360 +/* movea ${d-direct-addr},#${s1-imm8} */
12361 +  {
12362 +    UBICOM32_INSN_MOVEA_D_DIRECT_S1_IMMEDIATE, "movea-d-direct-s1-immediate", "movea", 32,
12363 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
12364 +  },
12365 +/* movea #${d-imm8},#${s1-imm8} */
12366 +  {
12367 +    UBICOM32_INSN_MOVEA_D_IMMEDIATE_4_S1_IMMEDIATE, "movea-d-immediate-4-s1-immediate", "movea", 32,
12368 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
12369 +  },
12370 +/* movea (${d-An},${d-r}),#${s1-imm8} */
12371 +  {
12372 +    UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_INDEX_4_S1_IMMEDIATE, "movea-d-indirect-with-index-4-s1-immediate", "movea", 32,
12373 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
12374 +  },
12375 +/* movea ${d-imm7-4}(${d-An}),#${s1-imm8} */
12376 +  {
12377 +    UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_OFFSET_4_S1_IMMEDIATE, "movea-d-indirect-with-offset-4-s1-immediate", "movea", 32,
12378 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
12379 +  },
12380 +/* movea (${d-An}),#${s1-imm8} */
12381 +  {
12382 +    UBICOM32_INSN_MOVEA_D_INDIRECT_4_S1_IMMEDIATE, "movea-d-indirect-4-s1-immediate", "movea", 32,
12383 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
12384 +  },
12385 +/* movea (${d-An})${d-i4-4}++,#${s1-imm8} */
12386 +  {
12387 +    UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_POST_INCREMENT_4_S1_IMMEDIATE, "movea-d-indirect-with-post-increment-4-s1-immediate", "movea", 32,
12388 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
12389 +  },
12390 +/* movea ${d-i4-4}(${d-An})++,#${s1-imm8} */
12391 +  {
12392 +    UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_IMMEDIATE, "movea-d-indirect-with-pre-increment-4-s1-immediate", "movea", 32,
12393 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
12394 +  },
12395 +/* movea ${d-direct-addr},(${s1-An},${s1-r}) */
12396 +  {
12397 +    UBICOM32_INSN_MOVEA_D_DIRECT_S1_INDIRECT_WITH_INDEX_4, "movea-d-direct-s1-indirect-with-index-4", "movea", 32,
12398 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
12399 +  },
12400 +/* movea #${d-imm8},(${s1-An},${s1-r}) */
12401 +  {
12402 +    UBICOM32_INSN_MOVEA_D_IMMEDIATE_4_S1_INDIRECT_WITH_INDEX_4, "movea-d-immediate-4-s1-indirect-with-index-4", "movea", 32,
12403 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
12404 +  },
12405 +/* movea (${d-An},${d-r}),(${s1-An},${s1-r}) */
12406 +  {
12407 +    UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_INDEX_4, "movea-d-indirect-with-index-4-s1-indirect-with-index-4", "movea", 32,
12408 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
12409 +  },
12410 +/* movea ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}) */
12411 +  {
12412 +    UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_INDEX_4, "movea-d-indirect-with-offset-4-s1-indirect-with-index-4", "movea", 32,
12413 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
12414 +  },
12415 +/* movea (${d-An}),(${s1-An},${s1-r}) */
12416 +  {
12417 +    UBICOM32_INSN_MOVEA_D_INDIRECT_4_S1_INDIRECT_WITH_INDEX_4, "movea-d-indirect-4-s1-indirect-with-index-4", "movea", 32,
12418 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
12419 +  },
12420 +/* movea (${d-An})${d-i4-4}++,(${s1-An},${s1-r}) */
12421 +  {
12422 +    UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, "movea-d-indirect-with-post-increment-4-s1-indirect-with-index-4", "movea", 32,
12423 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
12424 +  },
12425 +/* movea ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}) */
12426 +  {
12427 +    UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, "movea-d-indirect-with-pre-increment-4-s1-indirect-with-index-4", "movea", 32,
12428 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
12429 +  },
12430 +/* movea ${d-direct-addr},${s1-imm7-4}(${s1-An}) */
12431 +  {
12432 +    UBICOM32_INSN_MOVEA_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4, "movea-d-direct-s1-indirect-with-offset-4", "movea", 32,
12433 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
12434 +  },
12435 +/* movea #${d-imm8},${s1-imm7-4}(${s1-An}) */
12436 +  {
12437 +    UBICOM32_INSN_MOVEA_D_IMMEDIATE_4_S1_INDIRECT_WITH_OFFSET_4, "movea-d-immediate-4-s1-indirect-with-offset-4", "movea", 32,
12438 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
12439 +  },
12440 +/* movea (${d-An},${d-r}),${s1-imm7-4}(${s1-An}) */
12441 +  {
12442 +    UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_OFFSET_4, "movea-d-indirect-with-index-4-s1-indirect-with-offset-4", "movea", 32,
12443 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
12444 +  },
12445 +/* movea ${d-imm7-4}(${d-An}),${s1-imm7-4}(${s1-An}) */
12446 +  {
12447 +    UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_OFFSET_4, "movea-d-indirect-with-offset-4-s1-indirect-with-offset-4", "movea", 32,
12448 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
12449 +  },
12450 +/* movea (${d-An}),${s1-imm7-4}(${s1-An}) */
12451 +  {
12452 +    UBICOM32_INSN_MOVEA_D_INDIRECT_4_S1_INDIRECT_WITH_OFFSET_4, "movea-d-indirect-4-s1-indirect-with-offset-4", "movea", 32,
12453 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
12454 +  },
12455 +/* movea (${d-An})${d-i4-4}++,${s1-imm7-4}(${s1-An}) */
12456 +  {
12457 +    UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, "movea-d-indirect-with-post-increment-4-s1-indirect-with-offset-4", "movea", 32,
12458 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
12459 +  },
12460 +/* movea ${d-i4-4}(${d-An})++,${s1-imm7-4}(${s1-An}) */
12461 +  {
12462 +    UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, "movea-d-indirect-with-pre-increment-4-s1-indirect-with-offset-4", "movea", 32,
12463 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
12464 +  },
12465 +/* movea ${d-direct-addr},(${s1-An}) */
12466 +  {
12467 +    UBICOM32_INSN_MOVEA_D_DIRECT_S1_INDIRECT_4, "movea-d-direct-s1-indirect-4", "movea", 32,
12468 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
12469 +  },
12470 +/* movea #${d-imm8},(${s1-An}) */
12471 +  {
12472 +    UBICOM32_INSN_MOVEA_D_IMMEDIATE_4_S1_INDIRECT_4, "movea-d-immediate-4-s1-indirect-4", "movea", 32,
12473 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
12474 +  },
12475 +/* movea (${d-An},${d-r}),(${s1-An}) */
12476 +  {
12477 +    UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_4, "movea-d-indirect-with-index-4-s1-indirect-4", "movea", 32,
12478 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
12479 +  },
12480 +/* movea ${d-imm7-4}(${d-An}),(${s1-An}) */
12481 +  {
12482 +    UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_4, "movea-d-indirect-with-offset-4-s1-indirect-4", "movea", 32,
12483 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
12484 +  },
12485 +/* movea (${d-An}),(${s1-An}) */
12486 +  {
12487 +    UBICOM32_INSN_MOVEA_D_INDIRECT_4_S1_INDIRECT_4, "movea-d-indirect-4-s1-indirect-4", "movea", 32,
12488 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
12489 +  },
12490 +/* movea (${d-An})${d-i4-4}++,(${s1-An}) */
12491 +  {
12492 +    UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_4, "movea-d-indirect-with-post-increment-4-s1-indirect-4", "movea", 32,
12493 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
12494 +  },
12495 +/* movea ${d-i4-4}(${d-An})++,(${s1-An}) */
12496 +  {
12497 +    UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_4, "movea-d-indirect-with-pre-increment-4-s1-indirect-4", "movea", 32,
12498 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
12499 +  },
12500 +/* movea ${d-direct-addr},(${s1-An})${s1-i4-4}++ */
12501 +  {
12502 +    UBICOM32_INSN_MOVEA_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4, "movea-d-direct-s1-indirect-with-post-increment-4", "movea", 32,
12503 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
12504 +  },
12505 +/* movea #${d-imm8},(${s1-An})${s1-i4-4}++ */
12506 +  {
12507 +    UBICOM32_INSN_MOVEA_D_IMMEDIATE_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "movea-d-immediate-4-s1-indirect-with-post-increment-4", "movea", 32,
12508 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
12509 +  },
12510 +/* movea (${d-An},${d-r}),(${s1-An})${s1-i4-4}++ */
12511 +  {
12512 +    UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "movea-d-indirect-with-index-4-s1-indirect-with-post-increment-4", "movea", 32,
12513 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
12514 +  },
12515 +/* movea ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-4}++ */
12516 +  {
12517 +    UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "movea-d-indirect-with-offset-4-s1-indirect-with-post-increment-4", "movea", 32,
12518 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
12519 +  },
12520 +/* movea (${d-An}),(${s1-An})${s1-i4-4}++ */
12521 +  {
12522 +    UBICOM32_INSN_MOVEA_D_INDIRECT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "movea-d-indirect-4-s1-indirect-with-post-increment-4", "movea", 32,
12523 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
12524 +  },
12525 +/* movea (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-4}++ */
12526 +  {
12527 +    UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "movea-d-indirect-with-post-increment-4-s1-indirect-with-post-increment-4", "movea", 32,
12528 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
12529 +  },
12530 +/* movea ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-4}++ */
12531 +  {
12532 +    UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "movea-d-indirect-with-pre-increment-4-s1-indirect-with-post-increment-4", "movea", 32,
12533 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
12534 +  },
12535 +/* movea ${d-direct-addr},${s1-i4-4}(${s1-An})++ */
12536 +  {
12537 +    UBICOM32_INSN_MOVEA_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4, "movea-d-direct-s1-indirect-with-pre-increment-4", "movea", 32,
12538 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
12539 +  },
12540 +/* movea #${d-imm8},${s1-i4-4}(${s1-An})++ */
12541 +  {
12542 +    UBICOM32_INSN_MOVEA_D_IMMEDIATE_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "movea-d-immediate-4-s1-indirect-with-pre-increment-4", "movea", 32,
12543 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
12544 +  },
12545 +/* movea (${d-An},${d-r}),${s1-i4-4}(${s1-An})++ */
12546 +  {
12547 +    UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "movea-d-indirect-with-index-4-s1-indirect-with-pre-increment-4", "movea", 32,
12548 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
12549 +  },
12550 +/* movea ${d-imm7-4}(${d-An}),${s1-i4-4}(${s1-An})++ */
12551 +  {
12552 +    UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "movea-d-indirect-with-offset-4-s1-indirect-with-pre-increment-4", "movea", 32,
12553 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
12554 +  },
12555 +/* movea (${d-An}),${s1-i4-4}(${s1-An})++ */
12556 +  {
12557 +    UBICOM32_INSN_MOVEA_D_INDIRECT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "movea-d-indirect-4-s1-indirect-with-pre-increment-4", "movea", 32,
12558 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
12559 +  },
12560 +/* movea (${d-An})${d-i4-4}++,${s1-i4-4}(${s1-An})++ */
12561 +  {
12562 +    UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "movea-d-indirect-with-post-increment-4-s1-indirect-with-pre-increment-4", "movea", 32,
12563 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
12564 +  },
12565 +/* movea ${d-i4-4}(${d-An})++,${s1-i4-4}(${s1-An})++ */
12566 +  {
12567 +    UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "movea-d-indirect-with-pre-increment-4-s1-indirect-with-pre-increment-4", "movea", 32,
12568 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
12569 +  },
12570 +/* move.4 ${d-direct-addr},${s1-direct-addr} */
12571 +  {
12572 +    UBICOM32_INSN_MOVE_4_D_DIRECT_S1_DIRECT, "move.4-d-direct-s1-direct", "move.4", 32,
12573 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
12574 +  },
12575 +/* move.4 #${d-imm8},${s1-direct-addr} */
12576 +  {
12577 +    UBICOM32_INSN_MOVE_4_D_IMMEDIATE_4_S1_DIRECT, "move.4-d-immediate-4-s1-direct", "move.4", 32,
12578 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
12579 +  },
12580 +/* move.4 (${d-An},${d-r}),${s1-direct-addr} */
12581 +  {
12582 +    UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_INDEX_4_S1_DIRECT, "move.4-d-indirect-with-index-4-s1-direct", "move.4", 32,
12583 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
12584 +  },
12585 +/* move.4 ${d-imm7-4}(${d-An}),${s1-direct-addr} */
12586 +  {
12587 +    UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_OFFSET_4_S1_DIRECT, "move.4-d-indirect-with-offset-4-s1-direct", "move.4", 32,
12588 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
12589 +  },
12590 +/* move.4 (${d-An}),${s1-direct-addr} */
12591 +  {
12592 +    UBICOM32_INSN_MOVE_4_D_INDIRECT_4_S1_DIRECT, "move.4-d-indirect-4-s1-direct", "move.4", 32,
12593 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
12594 +  },
12595 +/* move.4 (${d-An})${d-i4-4}++,${s1-direct-addr} */
12596 +  {
12597 +    UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_DIRECT, "move.4-d-indirect-with-post-increment-4-s1-direct", "move.4", 32,
12598 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
12599 +  },
12600 +/* move.4 ${d-i4-4}(${d-An})++,${s1-direct-addr} */
12601 +  {
12602 +    UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_DIRECT, "move.4-d-indirect-with-pre-increment-4-s1-direct", "move.4", 32,
12603 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
12604 +  },
12605 +/* move.4 ${d-direct-addr},#${s1-imm8} */
12606 +  {
12607 +    UBICOM32_INSN_MOVE_4_D_DIRECT_S1_IMMEDIATE, "move.4-d-direct-s1-immediate", "move.4", 32,
12608 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
12609 +  },
12610 +/* move.4 #${d-imm8},#${s1-imm8} */
12611 +  {
12612 +    UBICOM32_INSN_MOVE_4_D_IMMEDIATE_4_S1_IMMEDIATE, "move.4-d-immediate-4-s1-immediate", "move.4", 32,
12613 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
12614 +  },
12615 +/* move.4 (${d-An},${d-r}),#${s1-imm8} */
12616 +  {
12617 +    UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_INDEX_4_S1_IMMEDIATE, "move.4-d-indirect-with-index-4-s1-immediate", "move.4", 32,
12618 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
12619 +  },
12620 +/* move.4 ${d-imm7-4}(${d-An}),#${s1-imm8} */
12621 +  {
12622 +    UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_OFFSET_4_S1_IMMEDIATE, "move.4-d-indirect-with-offset-4-s1-immediate", "move.4", 32,
12623 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
12624 +  },
12625 +/* move.4 (${d-An}),#${s1-imm8} */
12626 +  {
12627 +    UBICOM32_INSN_MOVE_4_D_INDIRECT_4_S1_IMMEDIATE, "move.4-d-indirect-4-s1-immediate", "move.4", 32,
12628 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
12629 +  },
12630 +/* move.4 (${d-An})${d-i4-4}++,#${s1-imm8} */
12631 +  {
12632 +    UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_IMMEDIATE, "move.4-d-indirect-with-post-increment-4-s1-immediate", "move.4", 32,
12633 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
12634 +  },
12635 +/* move.4 ${d-i4-4}(${d-An})++,#${s1-imm8} */
12636 +  {
12637 +    UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_IMMEDIATE, "move.4-d-indirect-with-pre-increment-4-s1-immediate", "move.4", 32,
12638 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
12639 +  },
12640 +/* move.4 ${d-direct-addr},(${s1-An},${s1-r}) */
12641 +  {
12642 +    UBICOM32_INSN_MOVE_4_D_DIRECT_S1_INDIRECT_WITH_INDEX_4, "move.4-d-direct-s1-indirect-with-index-4", "move.4", 32,
12643 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
12644 +  },
12645 +/* move.4 #${d-imm8},(${s1-An},${s1-r}) */
12646 +  {
12647 +    UBICOM32_INSN_MOVE_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_INDEX_4, "move.4-d-immediate-4-s1-indirect-with-index-4", "move.4", 32,
12648 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
12649 +  },
12650 +/* move.4 (${d-An},${d-r}),(${s1-An},${s1-r}) */
12651 +  {
12652 +    UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_INDEX_4, "move.4-d-indirect-with-index-4-s1-indirect-with-index-4", "move.4", 32,
12653 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
12654 +  },
12655 +/* move.4 ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}) */
12656 +  {
12657 +    UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_INDEX_4, "move.4-d-indirect-with-offset-4-s1-indirect-with-index-4", "move.4", 32,
12658 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
12659 +  },
12660 +/* move.4 (${d-An}),(${s1-An},${s1-r}) */
12661 +  {
12662 +    UBICOM32_INSN_MOVE_4_D_INDIRECT_4_S1_INDIRECT_WITH_INDEX_4, "move.4-d-indirect-4-s1-indirect-with-index-4", "move.4", 32,
12663 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
12664 +  },
12665 +/* move.4 (${d-An})${d-i4-4}++,(${s1-An},${s1-r}) */
12666 +  {
12667 +    UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, "move.4-d-indirect-with-post-increment-4-s1-indirect-with-index-4", "move.4", 32,
12668 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
12669 +  },
12670 +/* move.4 ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}) */
12671 +  {
12672 +    UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, "move.4-d-indirect-with-pre-increment-4-s1-indirect-with-index-4", "move.4", 32,
12673 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
12674 +  },
12675 +/* move.4 ${d-direct-addr},${s1-imm7-4}(${s1-An}) */
12676 +  {
12677 +    UBICOM32_INSN_MOVE_4_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4, "move.4-d-direct-s1-indirect-with-offset-4", "move.4", 32,
12678 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
12679 +  },
12680 +/* move.4 #${d-imm8},${s1-imm7-4}(${s1-An}) */
12681 +  {
12682 +    UBICOM32_INSN_MOVE_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_OFFSET_4, "move.4-d-immediate-4-s1-indirect-with-offset-4", "move.4", 32,
12683 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
12684 +  },
12685 +/* move.4 (${d-An},${d-r}),${s1-imm7-4}(${s1-An}) */
12686 +  {
12687 +    UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_OFFSET_4, "move.4-d-indirect-with-index-4-s1-indirect-with-offset-4", "move.4", 32,
12688 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
12689 +  },
12690 +/* move.4 ${d-imm7-4}(${d-An}),${s1-imm7-4}(${s1-An}) */
12691 +  {
12692 +    UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_OFFSET_4, "move.4-d-indirect-with-offset-4-s1-indirect-with-offset-4", "move.4", 32,
12693 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
12694 +  },
12695 +/* move.4 (${d-An}),${s1-imm7-4}(${s1-An}) */
12696 +  {
12697 +    UBICOM32_INSN_MOVE_4_D_INDIRECT_4_S1_INDIRECT_WITH_OFFSET_4, "move.4-d-indirect-4-s1-indirect-with-offset-4", "move.4", 32,
12698 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
12699 +  },
12700 +/* move.4 (${d-An})${d-i4-4}++,${s1-imm7-4}(${s1-An}) */
12701 +  {
12702 +    UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, "move.4-d-indirect-with-post-increment-4-s1-indirect-with-offset-4", "move.4", 32,
12703 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
12704 +  },
12705 +/* move.4 ${d-i4-4}(${d-An})++,${s1-imm7-4}(${s1-An}) */
12706 +  {
12707 +    UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, "move.4-d-indirect-with-pre-increment-4-s1-indirect-with-offset-4", "move.4", 32,
12708 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
12709 +  },
12710 +/* move.4 ${d-direct-addr},(${s1-An}) */
12711 +  {
12712 +    UBICOM32_INSN_MOVE_4_D_DIRECT_S1_INDIRECT_4, "move.4-d-direct-s1-indirect-4", "move.4", 32,
12713 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
12714 +  },
12715 +/* move.4 #${d-imm8},(${s1-An}) */
12716 +  {
12717 +    UBICOM32_INSN_MOVE_4_D_IMMEDIATE_4_S1_INDIRECT_4, "move.4-d-immediate-4-s1-indirect-4", "move.4", 32,
12718 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
12719 +  },
12720 +/* move.4 (${d-An},${d-r}),(${s1-An}) */
12721 +  {
12722 +    UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_4, "move.4-d-indirect-with-index-4-s1-indirect-4", "move.4", 32,
12723 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
12724 +  },
12725 +/* move.4 ${d-imm7-4}(${d-An}),(${s1-An}) */
12726 +  {
12727 +    UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_4, "move.4-d-indirect-with-offset-4-s1-indirect-4", "move.4", 32,
12728 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
12729 +  },
12730 +/* move.4 (${d-An}),(${s1-An}) */
12731 +  {
12732 +    UBICOM32_INSN_MOVE_4_D_INDIRECT_4_S1_INDIRECT_4, "move.4-d-indirect-4-s1-indirect-4", "move.4", 32,
12733 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
12734 +  },
12735 +/* move.4 (${d-An})${d-i4-4}++,(${s1-An}) */
12736 +  {
12737 +    UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_4, "move.4-d-indirect-with-post-increment-4-s1-indirect-4", "move.4", 32,
12738 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
12739 +  },
12740 +/* move.4 ${d-i4-4}(${d-An})++,(${s1-An}) */
12741 +  {
12742 +    UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_4, "move.4-d-indirect-with-pre-increment-4-s1-indirect-4", "move.4", 32,
12743 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
12744 +  },
12745 +/* move.4 ${d-direct-addr},(${s1-An})${s1-i4-4}++ */
12746 +  {
12747 +    UBICOM32_INSN_MOVE_4_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4, "move.4-d-direct-s1-indirect-with-post-increment-4", "move.4", 32,
12748 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
12749 +  },
12750 +/* move.4 #${d-imm8},(${s1-An})${s1-i4-4}++ */
12751 +  {
12752 +    UBICOM32_INSN_MOVE_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "move.4-d-immediate-4-s1-indirect-with-post-increment-4", "move.4", 32,
12753 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
12754 +  },
12755 +/* move.4 (${d-An},${d-r}),(${s1-An})${s1-i4-4}++ */
12756 +  {
12757 +    UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "move.4-d-indirect-with-index-4-s1-indirect-with-post-increment-4", "move.4", 32,
12758 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
12759 +  },
12760 +/* move.4 ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-4}++ */
12761 +  {
12762 +    UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "move.4-d-indirect-with-offset-4-s1-indirect-with-post-increment-4", "move.4", 32,
12763 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
12764 +  },
12765 +/* move.4 (${d-An}),(${s1-An})${s1-i4-4}++ */
12766 +  {
12767 +    UBICOM32_INSN_MOVE_4_D_INDIRECT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "move.4-d-indirect-4-s1-indirect-with-post-increment-4", "move.4", 32,
12768 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
12769 +  },
12770 +/* move.4 (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-4}++ */
12771 +  {
12772 +    UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "move.4-d-indirect-with-post-increment-4-s1-indirect-with-post-increment-4", "move.4", 32,
12773 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
12774 +  },
12775 +/* move.4 ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-4}++ */
12776 +  {
12777 +    UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "move.4-d-indirect-with-pre-increment-4-s1-indirect-with-post-increment-4", "move.4", 32,
12778 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
12779 +  },
12780 +/* move.4 ${d-direct-addr},${s1-i4-4}(${s1-An})++ */
12781 +  {
12782 +    UBICOM32_INSN_MOVE_4_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4, "move.4-d-direct-s1-indirect-with-pre-increment-4", "move.4", 32,
12783 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
12784 +  },
12785 +/* move.4 #${d-imm8},${s1-i4-4}(${s1-An})++ */
12786 +  {
12787 +    UBICOM32_INSN_MOVE_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "move.4-d-immediate-4-s1-indirect-with-pre-increment-4", "move.4", 32,
12788 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
12789 +  },
12790 +/* move.4 (${d-An},${d-r}),${s1-i4-4}(${s1-An})++ */
12791 +  {
12792 +    UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "move.4-d-indirect-with-index-4-s1-indirect-with-pre-increment-4", "move.4", 32,
12793 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
12794 +  },
12795 +/* move.4 ${d-imm7-4}(${d-An}),${s1-i4-4}(${s1-An})++ */
12796 +  {
12797 +    UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "move.4-d-indirect-with-offset-4-s1-indirect-with-pre-increment-4", "move.4", 32,
12798 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
12799 +  },
12800 +/* move.4 (${d-An}),${s1-i4-4}(${s1-An})++ */
12801 +  {
12802 +    UBICOM32_INSN_MOVE_4_D_INDIRECT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "move.4-d-indirect-4-s1-indirect-with-pre-increment-4", "move.4", 32,
12803 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
12804 +  },
12805 +/* move.4 (${d-An})${d-i4-4}++,${s1-i4-4}(${s1-An})++ */
12806 +  {
12807 +    UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "move.4-d-indirect-with-post-increment-4-s1-indirect-with-pre-increment-4", "move.4", 32,
12808 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
12809 +  },
12810 +/* move.4 ${d-i4-4}(${d-An})++,${s1-i4-4}(${s1-An})++ */
12811 +  {
12812 +    UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "move.4-d-indirect-with-pre-increment-4-s1-indirect-with-pre-increment-4", "move.4", 32,
12813 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
12814 +  },
12815 +/* iread (${s1-An}) */
12816 +  {
12817 +    UBICOM32_INSN_COMPATIBILITY_IREAD_S1_EA_INDIRECT, "compatibility-iread-s1-ea-indirect", "iread", 32,
12818 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
12819 +  },
12820 +/* iread (${s1-An},${s1-r}) */
12821 +  {
12822 +    UBICOM32_INSN_COMPATIBILITY_IREAD_S1_EA_INDIRECT_WITH_INDEX_4, "compatibility-iread-s1-ea-indirect-with-index-4", "iread", 32,
12823 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
12824 +  },
12825 +/* iread (${s1-An})${s1-i4-4}++ */
12826 +  {
12827 +    UBICOM32_INSN_COMPATIBILITY_IREAD_S1_EA_INDIRECT_WITH_POST_INCREMENT_4, "compatibility-iread-s1-ea-indirect-with-post-increment-4", "iread", 32,
12828 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
12829 +  },
12830 +/* iread ${s1-i4-4}(${s1-An})++ */
12831 +  {
12832 +    UBICOM32_INSN_COMPATIBILITY_IREAD_S1_EA_INDIRECT_WITH_PRE_INCREMENT_4, "compatibility-iread-s1-ea-indirect-with-pre-increment-4", "iread", 32,
12833 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
12834 +  },
12835 +/* iread ${s1-imm7-4}(${s1-An}) */
12836 +  {
12837 +    UBICOM32_INSN_COMPATIBILITY_IREAD_S1_EA_INDIRECT_WITH_OFFSET_4, "compatibility-iread-s1-ea-indirect-with-offset-4", "iread", 32,
12838 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
12839 +  },
12840 +/* iwrite (${d-An},${d-r}),${s1-direct-addr} */
12841 +  {
12842 +    UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_INDEX_S1_DIRECT, "compatibility-iwrite-d-pea-indirect-with-index-s1-direct", "iwrite", 32,
12843 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
12844 +  },
12845 +/* iwrite ${d-imm7-4}(${d-An}),${s1-direct-addr} */
12846 +  {
12847 +    UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_OFFSET_S1_DIRECT, "compatibility-iwrite-d-pea-indirect-with-offset-s1-direct", "iwrite", 32,
12848 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
12849 +  },
12850 +/* iwrite (${d-An}),${s1-direct-addr} */
12851 +  {
12852 +    UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_S1_DIRECT, "compatibility-iwrite-d-pea-indirect-s1-direct", "iwrite", 32,
12853 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
12854 +  },
12855 +/* iwrite (${d-An})${d-i4-4}++,${s1-direct-addr} */
12856 +  {
12857 +    UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_POST_INCREMENT_S1_DIRECT, "compatibility-iwrite-d-pea-indirect-with-post-increment-s1-direct", "iwrite", 32,
12858 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
12859 +  },
12860 +/* iwrite ${d-i4-4}(${d-An})++,${s1-direct-addr} */
12861 +  {
12862 +    UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_PRE_INCREMENT_S1_DIRECT, "compatibility-iwrite-d-pea-indirect-with-pre-increment-s1-direct", "iwrite", 32,
12863 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
12864 +  },
12865 +/* iwrite (${d-An},${d-r}),#${s1-imm8} */
12866 +  {
12867 +    UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_INDEX_S1_IMMEDIATE, "compatibility-iwrite-d-pea-indirect-with-index-s1-immediate", "iwrite", 32,
12868 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
12869 +  },
12870 +/* iwrite ${d-imm7-4}(${d-An}),#${s1-imm8} */
12871 +  {
12872 +    UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_OFFSET_S1_IMMEDIATE, "compatibility-iwrite-d-pea-indirect-with-offset-s1-immediate", "iwrite", 32,
12873 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
12874 +  },
12875 +/* iwrite (${d-An}),#${s1-imm8} */
12876 +  {
12877 +    UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_S1_IMMEDIATE, "compatibility-iwrite-d-pea-indirect-s1-immediate", "iwrite", 32,
12878 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
12879 +  },
12880 +/* iwrite (${d-An})${d-i4-4}++,#${s1-imm8} */
12881 +  {
12882 +    UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_POST_INCREMENT_S1_IMMEDIATE, "compatibility-iwrite-d-pea-indirect-with-post-increment-s1-immediate", "iwrite", 32,
12883 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
12884 +  },
12885 +/* iwrite ${d-i4-4}(${d-An})++,#${s1-imm8} */
12886 +  {
12887 +    UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_PRE_INCREMENT_S1_IMMEDIATE, "compatibility-iwrite-d-pea-indirect-with-pre-increment-s1-immediate", "iwrite", 32,
12888 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
12889 +  },
12890 +/* iwrite (${d-An},${d-r}),(${s1-An},${s1-r}) */
12891 +  {
12892 +    UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_INDEX_S1_INDIRECT_WITH_INDEX_4, "compatibility-iwrite-d-pea-indirect-with-index-s1-indirect-with-index-4", "iwrite", 32,
12893 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
12894 +  },
12895 +/* iwrite ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}) */
12896 +  {
12897 +    UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_OFFSET_S1_INDIRECT_WITH_INDEX_4, "compatibility-iwrite-d-pea-indirect-with-offset-s1-indirect-with-index-4", "iwrite", 32,
12898 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
12899 +  },
12900 +/* iwrite (${d-An}),(${s1-An},${s1-r}) */
12901 +  {
12902 +    UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_S1_INDIRECT_WITH_INDEX_4, "compatibility-iwrite-d-pea-indirect-s1-indirect-with-index-4", "iwrite", 32,
12903 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
12904 +  },
12905 +/* iwrite (${d-An})${d-i4-4}++,(${s1-An},${s1-r}) */
12906 +  {
12907 +    UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_POST_INCREMENT_S1_INDIRECT_WITH_INDEX_4, "compatibility-iwrite-d-pea-indirect-with-post-increment-s1-indirect-with-index-4", "iwrite", 32,
12908 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
12909 +  },
12910 +/* iwrite ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}) */
12911 +  {
12912 +    UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_PRE_INCREMENT_S1_INDIRECT_WITH_INDEX_4, "compatibility-iwrite-d-pea-indirect-with-pre-increment-s1-indirect-with-index-4", "iwrite", 32,
12913 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
12914 +  },
12915 +/* iwrite (${d-An},${d-r}),${s1-imm7-4}(${s1-An}) */
12916 +  {
12917 +    UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_INDEX_S1_INDIRECT_WITH_OFFSET_4, "compatibility-iwrite-d-pea-indirect-with-index-s1-indirect-with-offset-4", "iwrite", 32,
12918 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
12919 +  },
12920 +/* iwrite ${d-imm7-4}(${d-An}),${s1-imm7-4}(${s1-An}) */
12921 +  {
12922 +    UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_OFFSET_S1_INDIRECT_WITH_OFFSET_4, "compatibility-iwrite-d-pea-indirect-with-offset-s1-indirect-with-offset-4", "iwrite", 32,
12923 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
12924 +  },
12925 +/* iwrite (${d-An}),${s1-imm7-4}(${s1-An}) */
12926 +  {
12927 +    UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_S1_INDIRECT_WITH_OFFSET_4, "compatibility-iwrite-d-pea-indirect-s1-indirect-with-offset-4", "iwrite", 32,
12928 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
12929 +  },
12930 +/* iwrite (${d-An})${d-i4-4}++,${s1-imm7-4}(${s1-An}) */
12931 +  {
12932 +    UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_POST_INCREMENT_S1_INDIRECT_WITH_OFFSET_4, "compatibility-iwrite-d-pea-indirect-with-post-increment-s1-indirect-with-offset-4", "iwrite", 32,
12933 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
12934 +  },
12935 +/* iwrite ${d-i4-4}(${d-An})++,${s1-imm7-4}(${s1-An}) */
12936 +  {
12937 +    UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_PRE_INCREMENT_S1_INDIRECT_WITH_OFFSET_4, "compatibility-iwrite-d-pea-indirect-with-pre-increment-s1-indirect-with-offset-4", "iwrite", 32,
12938 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
12939 +  },
12940 +/* iwrite (${d-An},${d-r}),(${s1-An}) */
12941 +  {
12942 +    UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_INDEX_S1_INDIRECT_4, "compatibility-iwrite-d-pea-indirect-with-index-s1-indirect-4", "iwrite", 32,
12943 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
12944 +  },
12945 +/* iwrite ${d-imm7-4}(${d-An}),(${s1-An}) */
12946 +  {
12947 +    UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_OFFSET_S1_INDIRECT_4, "compatibility-iwrite-d-pea-indirect-with-offset-s1-indirect-4", "iwrite", 32,
12948 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
12949 +  },
12950 +/* iwrite (${d-An}),(${s1-An}) */
12951 +  {
12952 +    UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_S1_INDIRECT_4, "compatibility-iwrite-d-pea-indirect-s1-indirect-4", "iwrite", 32,
12953 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
12954 +  },
12955 +/* iwrite (${d-An})${d-i4-4}++,(${s1-An}) */
12956 +  {
12957 +    UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_POST_INCREMENT_S1_INDIRECT_4, "compatibility-iwrite-d-pea-indirect-with-post-increment-s1-indirect-4", "iwrite", 32,
12958 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
12959 +  },
12960 +/* iwrite ${d-i4-4}(${d-An})++,(${s1-An}) */
12961 +  {
12962 +    UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_PRE_INCREMENT_S1_INDIRECT_4, "compatibility-iwrite-d-pea-indirect-with-pre-increment-s1-indirect-4", "iwrite", 32,
12963 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
12964 +  },
12965 +/* iwrite (${d-An},${d-r}),(${s1-An})${s1-i4-4}++ */
12966 +  {
12967 +    UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_INDEX_S1_INDIRECT_WITH_POST_INCREMENT_4, "compatibility-iwrite-d-pea-indirect-with-index-s1-indirect-with-post-increment-4", "iwrite", 32,
12968 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
12969 +  },
12970 +/* iwrite ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-4}++ */
12971 +  {
12972 +    UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_OFFSET_S1_INDIRECT_WITH_POST_INCREMENT_4, "compatibility-iwrite-d-pea-indirect-with-offset-s1-indirect-with-post-increment-4", "iwrite", 32,
12973 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
12974 +  },
12975 +/* iwrite (${d-An}),(${s1-An})${s1-i4-4}++ */
12976 +  {
12977 +    UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4, "compatibility-iwrite-d-pea-indirect-s1-indirect-with-post-increment-4", "iwrite", 32,
12978 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
12979 +  },
12980 +/* iwrite (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-4}++ */
12981 +  {
12982 +    UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_POST_INCREMENT_S1_INDIRECT_WITH_POST_INCREMENT_4, "compatibility-iwrite-d-pea-indirect-with-post-increment-s1-indirect-with-post-increment-4", "iwrite", 32,
12983 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
12984 +  },
12985 +/* iwrite ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-4}++ */
12986 +  {
12987 +    UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_PRE_INCREMENT_S1_INDIRECT_WITH_POST_INCREMENT_4, "compatibility-iwrite-d-pea-indirect-with-pre-increment-s1-indirect-with-post-increment-4", "iwrite", 32,
12988 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
12989 +  },
12990 +/* iwrite (${d-An},${d-r}),${s1-i4-4}(${s1-An})++ */
12991 +  {
12992 +    UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_INDEX_S1_INDIRECT_WITH_PRE_INCREMENT_4, "compatibility-iwrite-d-pea-indirect-with-index-s1-indirect-with-pre-increment-4", "iwrite", 32,
12993 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
12994 +  },
12995 +/* iwrite ${d-imm7-4}(${d-An}),${s1-i4-4}(${s1-An})++ */
12996 +  {
12997 +    UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_OFFSET_S1_INDIRECT_WITH_PRE_INCREMENT_4, "compatibility-iwrite-d-pea-indirect-with-offset-s1-indirect-with-pre-increment-4", "iwrite", 32,
12998 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
12999 +  },
13000 +/* iwrite (${d-An}),${s1-i4-4}(${s1-An})++ */
13001 +  {
13002 +    UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4, "compatibility-iwrite-d-pea-indirect-s1-indirect-with-pre-increment-4", "iwrite", 32,
13003 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
13004 +  },
13005 +/* iwrite (${d-An})${d-i4-4}++,${s1-i4-4}(${s1-An})++ */
13006 +  {
13007 +    UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_POST_INCREMENT_S1_INDIRECT_WITH_PRE_INCREMENT_4, "compatibility-iwrite-d-pea-indirect-with-post-increment-s1-indirect-with-pre-increment-4", "iwrite", 32,
13008 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
13009 +  },
13010 +/* iwrite ${d-i4-4}(${d-An})++,${s1-i4-4}(${s1-An})++ */
13011 +  {
13012 +    UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_PRE_INCREMENT_S1_INDIRECT_WITH_PRE_INCREMENT_4, "compatibility-iwrite-d-pea-indirect-with-pre-increment-s1-indirect-with-pre-increment-4", "iwrite", 32,
13013 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
13014 +  },
13015 +/* move.2 ${d-direct-addr},${s1-direct-addr} */
13016 +  {
13017 +    UBICOM32_INSN_MOVE_2_D_DIRECT_S1_DIRECT, "move.2-d-direct-s1-direct", "move.2", 32,
13018 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13019 +  },
13020 +/* move.2 #${d-imm8},${s1-direct-addr} */
13021 +  {
13022 +    UBICOM32_INSN_MOVE_2_D_IMMEDIATE_2_S1_DIRECT, "move.2-d-immediate-2-s1-direct", "move.2", 32,
13023 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13024 +  },
13025 +/* move.2 (${d-An},${d-r}),${s1-direct-addr} */
13026 +  {
13027 +    UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_INDEX_2_S1_DIRECT, "move.2-d-indirect-with-index-2-s1-direct", "move.2", 32,
13028 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13029 +  },
13030 +/* move.2 ${d-imm7-2}(${d-An}),${s1-direct-addr} */
13031 +  {
13032 +    UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_OFFSET_2_S1_DIRECT, "move.2-d-indirect-with-offset-2-s1-direct", "move.2", 32,
13033 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13034 +  },
13035 +/* move.2 (${d-An}),${s1-direct-addr} */
13036 +  {
13037 +    UBICOM32_INSN_MOVE_2_D_INDIRECT_2_S1_DIRECT, "move.2-d-indirect-2-s1-direct", "move.2", 32,
13038 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13039 +  },
13040 +/* move.2 (${d-An})${d-i4-2}++,${s1-direct-addr} */
13041 +  {
13042 +    UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_DIRECT, "move.2-d-indirect-with-post-increment-2-s1-direct", "move.2", 32,
13043 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13044 +  },
13045 +/* move.2 ${d-i4-2}(${d-An})++,${s1-direct-addr} */
13046 +  {
13047 +    UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_DIRECT, "move.2-d-indirect-with-pre-increment-2-s1-direct", "move.2", 32,
13048 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13049 +  },
13050 +/* move.2 ${d-direct-addr},#${s1-imm8} */
13051 +  {
13052 +    UBICOM32_INSN_MOVE_2_D_DIRECT_S1_IMMEDIATE, "move.2-d-direct-s1-immediate", "move.2", 32,
13053 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13054 +  },
13055 +/* move.2 #${d-imm8},#${s1-imm8} */
13056 +  {
13057 +    UBICOM32_INSN_MOVE_2_D_IMMEDIATE_2_S1_IMMEDIATE, "move.2-d-immediate-2-s1-immediate", "move.2", 32,
13058 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13059 +  },
13060 +/* move.2 (${d-An},${d-r}),#${s1-imm8} */
13061 +  {
13062 +    UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_INDEX_2_S1_IMMEDIATE, "move.2-d-indirect-with-index-2-s1-immediate", "move.2", 32,
13063 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13064 +  },
13065 +/* move.2 ${d-imm7-2}(${d-An}),#${s1-imm8} */
13066 +  {
13067 +    UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_OFFSET_2_S1_IMMEDIATE, "move.2-d-indirect-with-offset-2-s1-immediate", "move.2", 32,
13068 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13069 +  },
13070 +/* move.2 (${d-An}),#${s1-imm8} */
13071 +  {
13072 +    UBICOM32_INSN_MOVE_2_D_INDIRECT_2_S1_IMMEDIATE, "move.2-d-indirect-2-s1-immediate", "move.2", 32,
13073 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13074 +  },
13075 +/* move.2 (${d-An})${d-i4-2}++,#${s1-imm8} */
13076 +  {
13077 +    UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_IMMEDIATE, "move.2-d-indirect-with-post-increment-2-s1-immediate", "move.2", 32,
13078 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13079 +  },
13080 +/* move.2 ${d-i4-2}(${d-An})++,#${s1-imm8} */
13081 +  {
13082 +    UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_IMMEDIATE, "move.2-d-indirect-with-pre-increment-2-s1-immediate", "move.2", 32,
13083 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13084 +  },
13085 +/* move.2 ${d-direct-addr},(${s1-An},${s1-r}) */
13086 +  {
13087 +    UBICOM32_INSN_MOVE_2_D_DIRECT_S1_INDIRECT_WITH_INDEX_2, "move.2-d-direct-s1-indirect-with-index-2", "move.2", 32,
13088 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13089 +  },
13090 +/* move.2 #${d-imm8},(${s1-An},${s1-r}) */
13091 +  {
13092 +    UBICOM32_INSN_MOVE_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_INDEX_2, "move.2-d-immediate-2-s1-indirect-with-index-2", "move.2", 32,
13093 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13094 +  },
13095 +/* move.2 (${d-An},${d-r}),(${s1-An},${s1-r}) */
13096 +  {
13097 +    UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_INDEX_2, "move.2-d-indirect-with-index-2-s1-indirect-with-index-2", "move.2", 32,
13098 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13099 +  },
13100 +/* move.2 ${d-imm7-2}(${d-An}),(${s1-An},${s1-r}) */
13101 +  {
13102 +    UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_INDEX_2, "move.2-d-indirect-with-offset-2-s1-indirect-with-index-2", "move.2", 32,
13103 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13104 +  },
13105 +/* move.2 (${d-An}),(${s1-An},${s1-r}) */
13106 +  {
13107 +    UBICOM32_INSN_MOVE_2_D_INDIRECT_2_S1_INDIRECT_WITH_INDEX_2, "move.2-d-indirect-2-s1-indirect-with-index-2", "move.2", 32,
13108 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13109 +  },
13110 +/* move.2 (${d-An})${d-i4-2}++,(${s1-An},${s1-r}) */
13111 +  {
13112 +    UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_INDEX_2, "move.2-d-indirect-with-post-increment-2-s1-indirect-with-index-2", "move.2", 32,
13113 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13114 +  },
13115 +/* move.2 ${d-i4-2}(${d-An})++,(${s1-An},${s1-r}) */
13116 +  {
13117 +    UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_INDEX_2, "move.2-d-indirect-with-pre-increment-2-s1-indirect-with-index-2", "move.2", 32,
13118 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13119 +  },
13120 +/* move.2 ${d-direct-addr},${s1-imm7-2}(${s1-An}) */
13121 +  {
13122 +    UBICOM32_INSN_MOVE_2_D_DIRECT_S1_INDIRECT_WITH_OFFSET_2, "move.2-d-direct-s1-indirect-with-offset-2", "move.2", 32,
13123 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13124 +  },
13125 +/* move.2 #${d-imm8},${s1-imm7-2}(${s1-An}) */
13126 +  {
13127 +    UBICOM32_INSN_MOVE_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_OFFSET_2, "move.2-d-immediate-2-s1-indirect-with-offset-2", "move.2", 32,
13128 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13129 +  },
13130 +/* move.2 (${d-An},${d-r}),${s1-imm7-2}(${s1-An}) */
13131 +  {
13132 +    UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_OFFSET_2, "move.2-d-indirect-with-index-2-s1-indirect-with-offset-2", "move.2", 32,
13133 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13134 +  },
13135 +/* move.2 ${d-imm7-2}(${d-An}),${s1-imm7-2}(${s1-An}) */
13136 +  {
13137 +    UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_OFFSET_2, "move.2-d-indirect-with-offset-2-s1-indirect-with-offset-2", "move.2", 32,
13138 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13139 +  },
13140 +/* move.2 (${d-An}),${s1-imm7-2}(${s1-An}) */
13141 +  {
13142 +    UBICOM32_INSN_MOVE_2_D_INDIRECT_2_S1_INDIRECT_WITH_OFFSET_2, "move.2-d-indirect-2-s1-indirect-with-offset-2", "move.2", 32,
13143 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13144 +  },
13145 +/* move.2 (${d-An})${d-i4-2}++,${s1-imm7-2}(${s1-An}) */
13146 +  {
13147 +    UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_2, "move.2-d-indirect-with-post-increment-2-s1-indirect-with-offset-2", "move.2", 32,
13148 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13149 +  },
13150 +/* move.2 ${d-i4-2}(${d-An})++,${s1-imm7-2}(${s1-An}) */
13151 +  {
13152 +    UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_2, "move.2-d-indirect-with-pre-increment-2-s1-indirect-with-offset-2", "move.2", 32,
13153 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13154 +  },
13155 +/* move.2 ${d-direct-addr},(${s1-An}) */
13156 +  {
13157 +    UBICOM32_INSN_MOVE_2_D_DIRECT_S1_INDIRECT_2, "move.2-d-direct-s1-indirect-2", "move.2", 32,
13158 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13159 +  },
13160 +/* move.2 #${d-imm8},(${s1-An}) */
13161 +  {
13162 +    UBICOM32_INSN_MOVE_2_D_IMMEDIATE_2_S1_INDIRECT_2, "move.2-d-immediate-2-s1-indirect-2", "move.2", 32,
13163 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13164 +  },
13165 +/* move.2 (${d-An},${d-r}),(${s1-An}) */
13166 +  {
13167 +    UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_2, "move.2-d-indirect-with-index-2-s1-indirect-2", "move.2", 32,
13168 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13169 +  },
13170 +/* move.2 ${d-imm7-2}(${d-An}),(${s1-An}) */
13171 +  {
13172 +    UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_2, "move.2-d-indirect-with-offset-2-s1-indirect-2", "move.2", 32,
13173 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13174 +  },
13175 +/* move.2 (${d-An}),(${s1-An}) */
13176 +  {
13177 +    UBICOM32_INSN_MOVE_2_D_INDIRECT_2_S1_INDIRECT_2, "move.2-d-indirect-2-s1-indirect-2", "move.2", 32,
13178 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13179 +  },
13180 +/* move.2 (${d-An})${d-i4-2}++,(${s1-An}) */
13181 +  {
13182 +    UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_2, "move.2-d-indirect-with-post-increment-2-s1-indirect-2", "move.2", 32,
13183 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13184 +  },
13185 +/* move.2 ${d-i4-2}(${d-An})++,(${s1-An}) */
13186 +  {
13187 +    UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_2, "move.2-d-indirect-with-pre-increment-2-s1-indirect-2", "move.2", 32,
13188 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13189 +  },
13190 +/* move.2 ${d-direct-addr},(${s1-An})${s1-i4-2}++ */
13191 +  {
13192 +    UBICOM32_INSN_MOVE_2_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_2, "move.2-d-direct-s1-indirect-with-post-increment-2", "move.2", 32,
13193 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13194 +  },
13195 +/* move.2 #${d-imm8},(${s1-An})${s1-i4-2}++ */
13196 +  {
13197 +    UBICOM32_INSN_MOVE_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_POST_INCREMENT_2, "move.2-d-immediate-2-s1-indirect-with-post-increment-2", "move.2", 32,
13198 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13199 +  },
13200 +/* move.2 (${d-An},${d-r}),(${s1-An})${s1-i4-2}++ */
13201 +  {
13202 +    UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_POST_INCREMENT_2, "move.2-d-indirect-with-index-2-s1-indirect-with-post-increment-2", "move.2", 32,
13203 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13204 +  },
13205 +/* move.2 ${d-imm7-2}(${d-An}),(${s1-An})${s1-i4-2}++ */
13206 +  {
13207 +    UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_POST_INCREMENT_2, "move.2-d-indirect-with-offset-2-s1-indirect-with-post-increment-2", "move.2", 32,
13208 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13209 +  },
13210 +/* move.2 (${d-An}),(${s1-An})${s1-i4-2}++ */
13211 +  {
13212 +    UBICOM32_INSN_MOVE_2_D_INDIRECT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, "move.2-d-indirect-2-s1-indirect-with-post-increment-2", "move.2", 32,
13213 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13214 +  },
13215 +/* move.2 (${d-An})${d-i4-2}++,(${s1-An})${s1-i4-2}++ */
13216 +  {
13217 +    UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, "move.2-d-indirect-with-post-increment-2-s1-indirect-with-post-increment-2", "move.2", 32,
13218 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13219 +  },
13220 +/* move.2 ${d-i4-2}(${d-An})++,(${s1-An})${s1-i4-2}++ */
13221 +  {
13222 +    UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, "move.2-d-indirect-with-pre-increment-2-s1-indirect-with-post-increment-2", "move.2", 32,
13223 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13224 +  },
13225 +/* move.2 ${d-direct-addr},${s1-i4-2}(${s1-An})++ */
13226 +  {
13227 +    UBICOM32_INSN_MOVE_2_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_2, "move.2-d-direct-s1-indirect-with-pre-increment-2", "move.2", 32,
13228 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13229 +  },
13230 +/* move.2 #${d-imm8},${s1-i4-2}(${s1-An})++ */
13231 +  {
13232 +    UBICOM32_INSN_MOVE_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, "move.2-d-immediate-2-s1-indirect-with-pre-increment-2", "move.2", 32,
13233 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13234 +  },
13235 +/* move.2 (${d-An},${d-r}),${s1-i4-2}(${s1-An})++ */
13236 +  {
13237 +    UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, "move.2-d-indirect-with-index-2-s1-indirect-with-pre-increment-2", "move.2", 32,
13238 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13239 +  },
13240 +/* move.2 ${d-imm7-2}(${d-An}),${s1-i4-2}(${s1-An})++ */
13241 +  {
13242 +    UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, "move.2-d-indirect-with-offset-2-s1-indirect-with-pre-increment-2", "move.2", 32,
13243 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13244 +  },
13245 +/* move.2 (${d-An}),${s1-i4-2}(${s1-An})++ */
13246 +  {
13247 +    UBICOM32_INSN_MOVE_2_D_INDIRECT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, "move.2-d-indirect-2-s1-indirect-with-pre-increment-2", "move.2", 32,
13248 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13249 +  },
13250 +/* move.2 (${d-An})${d-i4-2}++,${s1-i4-2}(${s1-An})++ */
13251 +  {
13252 +    UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, "move.2-d-indirect-with-post-increment-2-s1-indirect-with-pre-increment-2", "move.2", 32,
13253 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13254 +  },
13255 +/* move.2 ${d-i4-2}(${d-An})++,${s1-i4-2}(${s1-An})++ */
13256 +  {
13257 +    UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, "move.2-d-indirect-with-pre-increment-2-s1-indirect-with-pre-increment-2", "move.2", 32,
13258 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13259 +  },
13260 +/* move.1 ${d-direct-addr},${s1-direct-addr} */
13261 +  {
13262 +    UBICOM32_INSN_MOVE_1_D_DIRECT_S1_DIRECT, "move.1-d-direct-s1-direct", "move.1", 32,
13263 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13264 +  },
13265 +/* move.1 #${d-imm8},${s1-direct-addr} */
13266 +  {
13267 +    UBICOM32_INSN_MOVE_1_D_IMMEDIATE_1_S1_DIRECT, "move.1-d-immediate-1-s1-direct", "move.1", 32,
13268 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13269 +  },
13270 +/* move.1 (${d-An},${d-r}),${s1-direct-addr} */
13271 +  {
13272 +    UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_INDEX_1_S1_DIRECT, "move.1-d-indirect-with-index-1-s1-direct", "move.1", 32,
13273 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13274 +  },
13275 +/* move.1 ${d-imm7-1}(${d-An}),${s1-direct-addr} */
13276 +  {
13277 +    UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_OFFSET_1_S1_DIRECT, "move.1-d-indirect-with-offset-1-s1-direct", "move.1", 32,
13278 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13279 +  },
13280 +/* move.1 (${d-An}),${s1-direct-addr} */
13281 +  {
13282 +    UBICOM32_INSN_MOVE_1_D_INDIRECT_1_S1_DIRECT, "move.1-d-indirect-1-s1-direct", "move.1", 32,
13283 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13284 +  },
13285 +/* move.1 (${d-An})${d-i4-1}++,${s1-direct-addr} */
13286 +  {
13287 +    UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_DIRECT, "move.1-d-indirect-with-post-increment-1-s1-direct", "move.1", 32,
13288 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13289 +  },
13290 +/* move.1 ${d-i4-1}(${d-An})++,${s1-direct-addr} */
13291 +  {
13292 +    UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_DIRECT, "move.1-d-indirect-with-pre-increment-1-s1-direct", "move.1", 32,
13293 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13294 +  },
13295 +/* move.1 ${d-direct-addr},#${s1-imm8} */
13296 +  {
13297 +    UBICOM32_INSN_MOVE_1_D_DIRECT_S1_IMMEDIATE, "move.1-d-direct-s1-immediate", "move.1", 32,
13298 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13299 +  },
13300 +/* move.1 #${d-imm8},#${s1-imm8} */
13301 +  {
13302 +    UBICOM32_INSN_MOVE_1_D_IMMEDIATE_1_S1_IMMEDIATE, "move.1-d-immediate-1-s1-immediate", "move.1", 32,
13303 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13304 +  },
13305 +/* move.1 (${d-An},${d-r}),#${s1-imm8} */
13306 +  {
13307 +    UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_INDEX_1_S1_IMMEDIATE, "move.1-d-indirect-with-index-1-s1-immediate", "move.1", 32,
13308 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13309 +  },
13310 +/* move.1 ${d-imm7-1}(${d-An}),#${s1-imm8} */
13311 +  {
13312 +    UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_OFFSET_1_S1_IMMEDIATE, "move.1-d-indirect-with-offset-1-s1-immediate", "move.1", 32,
13313 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13314 +  },
13315 +/* move.1 (${d-An}),#${s1-imm8} */
13316 +  {
13317 +    UBICOM32_INSN_MOVE_1_D_INDIRECT_1_S1_IMMEDIATE, "move.1-d-indirect-1-s1-immediate", "move.1", 32,
13318 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13319 +  },
13320 +/* move.1 (${d-An})${d-i4-1}++,#${s1-imm8} */
13321 +  {
13322 +    UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_IMMEDIATE, "move.1-d-indirect-with-post-increment-1-s1-immediate", "move.1", 32,
13323 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13324 +  },
13325 +/* move.1 ${d-i4-1}(${d-An})++,#${s1-imm8} */
13326 +  {
13327 +    UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_IMMEDIATE, "move.1-d-indirect-with-pre-increment-1-s1-immediate", "move.1", 32,
13328 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13329 +  },
13330 +/* move.1 ${d-direct-addr},(${s1-An},${s1-r}) */
13331 +  {
13332 +    UBICOM32_INSN_MOVE_1_D_DIRECT_S1_INDIRECT_WITH_INDEX_1, "move.1-d-direct-s1-indirect-with-index-1", "move.1", 32,
13333 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13334 +  },
13335 +/* move.1 #${d-imm8},(${s1-An},${s1-r}) */
13336 +  {
13337 +    UBICOM32_INSN_MOVE_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_INDEX_1, "move.1-d-immediate-1-s1-indirect-with-index-1", "move.1", 32,
13338 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13339 +  },
13340 +/* move.1 (${d-An},${d-r}),(${s1-An},${s1-r}) */
13341 +  {
13342 +    UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_INDEX_1, "move.1-d-indirect-with-index-1-s1-indirect-with-index-1", "move.1", 32,
13343 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13344 +  },
13345 +/* move.1 ${d-imm7-1}(${d-An}),(${s1-An},${s1-r}) */
13346 +  {
13347 +    UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_INDEX_1, "move.1-d-indirect-with-offset-1-s1-indirect-with-index-1", "move.1", 32,
13348 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13349 +  },
13350 +/* move.1 (${d-An}),(${s1-An},${s1-r}) */
13351 +  {
13352 +    UBICOM32_INSN_MOVE_1_D_INDIRECT_1_S1_INDIRECT_WITH_INDEX_1, "move.1-d-indirect-1-s1-indirect-with-index-1", "move.1", 32,
13353 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13354 +  },
13355 +/* move.1 (${d-An})${d-i4-1}++,(${s1-An},${s1-r}) */
13356 +  {
13357 +    UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_INDEX_1, "move.1-d-indirect-with-post-increment-1-s1-indirect-with-index-1", "move.1", 32,
13358 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13359 +  },
13360 +/* move.1 ${d-i4-1}(${d-An})++,(${s1-An},${s1-r}) */
13361 +  {
13362 +    UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_INDEX_1, "move.1-d-indirect-with-pre-increment-1-s1-indirect-with-index-1", "move.1", 32,
13363 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13364 +  },
13365 +/* move.1 ${d-direct-addr},${s1-imm7-1}(${s1-An}) */
13366 +  {
13367 +    UBICOM32_INSN_MOVE_1_D_DIRECT_S1_INDIRECT_WITH_OFFSET_1, "move.1-d-direct-s1-indirect-with-offset-1", "move.1", 32,
13368 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13369 +  },
13370 +/* move.1 #${d-imm8},${s1-imm7-1}(${s1-An}) */
13371 +  {
13372 +    UBICOM32_INSN_MOVE_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_OFFSET_1, "move.1-d-immediate-1-s1-indirect-with-offset-1", "move.1", 32,
13373 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13374 +  },
13375 +/* move.1 (${d-An},${d-r}),${s1-imm7-1}(${s1-An}) */
13376 +  {
13377 +    UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_OFFSET_1, "move.1-d-indirect-with-index-1-s1-indirect-with-offset-1", "move.1", 32,
13378 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13379 +  },
13380 +/* move.1 ${d-imm7-1}(${d-An}),${s1-imm7-1}(${s1-An}) */
13381 +  {
13382 +    UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_OFFSET_1, "move.1-d-indirect-with-offset-1-s1-indirect-with-offset-1", "move.1", 32,
13383 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13384 +  },
13385 +/* move.1 (${d-An}),${s1-imm7-1}(${s1-An}) */
13386 +  {
13387 +    UBICOM32_INSN_MOVE_1_D_INDIRECT_1_S1_INDIRECT_WITH_OFFSET_1, "move.1-d-indirect-1-s1-indirect-with-offset-1", "move.1", 32,
13388 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13389 +  },
13390 +/* move.1 (${d-An})${d-i4-1}++,${s1-imm7-1}(${s1-An}) */
13391 +  {
13392 +    UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_OFFSET_1, "move.1-d-indirect-with-post-increment-1-s1-indirect-with-offset-1", "move.1", 32,
13393 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13394 +  },
13395 +/* move.1 ${d-i4-1}(${d-An})++,${s1-imm7-1}(${s1-An}) */
13396 +  {
13397 +    UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_OFFSET_1, "move.1-d-indirect-with-pre-increment-1-s1-indirect-with-offset-1", "move.1", 32,
13398 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13399 +  },
13400 +/* move.1 ${d-direct-addr},(${s1-An}) */
13401 +  {
13402 +    UBICOM32_INSN_MOVE_1_D_DIRECT_S1_INDIRECT_1, "move.1-d-direct-s1-indirect-1", "move.1", 32,
13403 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13404 +  },
13405 +/* move.1 #${d-imm8},(${s1-An}) */
13406 +  {
13407 +    UBICOM32_INSN_MOVE_1_D_IMMEDIATE_1_S1_INDIRECT_1, "move.1-d-immediate-1-s1-indirect-1", "move.1", 32,
13408 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13409 +  },
13410 +/* move.1 (${d-An},${d-r}),(${s1-An}) */
13411 +  {
13412 +    UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_1, "move.1-d-indirect-with-index-1-s1-indirect-1", "move.1", 32,
13413 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13414 +  },
13415 +/* move.1 ${d-imm7-1}(${d-An}),(${s1-An}) */
13416 +  {
13417 +    UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_1, "move.1-d-indirect-with-offset-1-s1-indirect-1", "move.1", 32,
13418 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13419 +  },
13420 +/* move.1 (${d-An}),(${s1-An}) */
13421 +  {
13422 +    UBICOM32_INSN_MOVE_1_D_INDIRECT_1_S1_INDIRECT_1, "move.1-d-indirect-1-s1-indirect-1", "move.1", 32,
13423 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13424 +  },
13425 +/* move.1 (${d-An})${d-i4-1}++,(${s1-An}) */
13426 +  {
13427 +    UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_1, "move.1-d-indirect-with-post-increment-1-s1-indirect-1", "move.1", 32,
13428 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13429 +  },
13430 +/* move.1 ${d-i4-1}(${d-An})++,(${s1-An}) */
13431 +  {
13432 +    UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_1, "move.1-d-indirect-with-pre-increment-1-s1-indirect-1", "move.1", 32,
13433 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13434 +  },
13435 +/* move.1 ${d-direct-addr},(${s1-An})${s1-i4-1}++ */
13436 +  {
13437 +    UBICOM32_INSN_MOVE_1_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_1, "move.1-d-direct-s1-indirect-with-post-increment-1", "move.1", 32,
13438 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13439 +  },
13440 +/* move.1 #${d-imm8},(${s1-An})${s1-i4-1}++ */
13441 +  {
13442 +    UBICOM32_INSN_MOVE_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_POST_INCREMENT_1, "move.1-d-immediate-1-s1-indirect-with-post-increment-1", "move.1", 32,
13443 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13444 +  },
13445 +/* move.1 (${d-An},${d-r}),(${s1-An})${s1-i4-1}++ */
13446 +  {
13447 +    UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_POST_INCREMENT_1, "move.1-d-indirect-with-index-1-s1-indirect-with-post-increment-1", "move.1", 32,
13448 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13449 +  },
13450 +/* move.1 ${d-imm7-1}(${d-An}),(${s1-An})${s1-i4-1}++ */
13451 +  {
13452 +    UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_POST_INCREMENT_1, "move.1-d-indirect-with-offset-1-s1-indirect-with-post-increment-1", "move.1", 32,
13453 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13454 +  },
13455 +/* move.1 (${d-An}),(${s1-An})${s1-i4-1}++ */
13456 +  {
13457 +    UBICOM32_INSN_MOVE_1_D_INDIRECT_1_S1_INDIRECT_WITH_POST_INCREMENT_1, "move.1-d-indirect-1-s1-indirect-with-post-increment-1", "move.1", 32,
13458 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13459 +  },
13460 +/* move.1 (${d-An})${d-i4-1}++,(${s1-An})${s1-i4-1}++ */
13461 +  {
13462 +    UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_POST_INCREMENT_1, "move.1-d-indirect-with-post-increment-1-s1-indirect-with-post-increment-1", "move.1", 32,
13463 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13464 +  },
13465 +/* move.1 ${d-i4-1}(${d-An})++,(${s1-An})${s1-i4-1}++ */
13466 +  {
13467 +    UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_POST_INCREMENT_1, "move.1-d-indirect-with-pre-increment-1-s1-indirect-with-post-increment-1", "move.1", 32,
13468 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13469 +  },
13470 +/* move.1 ${d-direct-addr},${s1-i4-1}(${s1-An})++ */
13471 +  {
13472 +    UBICOM32_INSN_MOVE_1_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_1, "move.1-d-direct-s1-indirect-with-pre-increment-1", "move.1", 32,
13473 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13474 +  },
13475 +/* move.1 #${d-imm8},${s1-i4-1}(${s1-An})++ */
13476 +  {
13477 +    UBICOM32_INSN_MOVE_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, "move.1-d-immediate-1-s1-indirect-with-pre-increment-1", "move.1", 32,
13478 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13479 +  },
13480 +/* move.1 (${d-An},${d-r}),${s1-i4-1}(${s1-An})++ */
13481 +  {
13482 +    UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, "move.1-d-indirect-with-index-1-s1-indirect-with-pre-increment-1", "move.1", 32,
13483 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13484 +  },
13485 +/* move.1 ${d-imm7-1}(${d-An}),${s1-i4-1}(${s1-An})++ */
13486 +  {
13487 +    UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, "move.1-d-indirect-with-offset-1-s1-indirect-with-pre-increment-1", "move.1", 32,
13488 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13489 +  },
13490 +/* move.1 (${d-An}),${s1-i4-1}(${s1-An})++ */
13491 +  {
13492 +    UBICOM32_INSN_MOVE_1_D_INDIRECT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, "move.1-d-indirect-1-s1-indirect-with-pre-increment-1", "move.1", 32,
13493 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13494 +  },
13495 +/* move.1 (${d-An})${d-i4-1}++,${s1-i4-1}(${s1-An})++ */
13496 +  {
13497 +    UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, "move.1-d-indirect-with-post-increment-1-s1-indirect-with-pre-increment-1", "move.1", 32,
13498 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13499 +  },
13500 +/* move.1 ${d-i4-1}(${d-An})++,${s1-i4-1}(${s1-An})++ */
13501 +  {
13502 +    UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, "move.1-d-indirect-with-pre-increment-1-s1-indirect-with-pre-increment-1", "move.1", 32,
13503 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13504 +  },
13505 +/* ext.2 ${d-direct-addr},${s1-direct-addr} */
13506 +  {
13507 +    UBICOM32_INSN_EXT_2_D_DIRECT_S1_DIRECT, "ext.2-d-direct-s1-direct", "ext.2", 32,
13508 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13509 +  },
13510 +/* ext.2 #${d-imm8},${s1-direct-addr} */
13511 +  {
13512 +    UBICOM32_INSN_EXT_2_D_IMMEDIATE_2_S1_DIRECT, "ext.2-d-immediate-2-s1-direct", "ext.2", 32,
13513 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13514 +  },
13515 +/* ext.2 (${d-An},${d-r}),${s1-direct-addr} */
13516 +  {
13517 +    UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_INDEX_2_S1_DIRECT, "ext.2-d-indirect-with-index-2-s1-direct", "ext.2", 32,
13518 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13519 +  },
13520 +/* ext.2 ${d-imm7-2}(${d-An}),${s1-direct-addr} */
13521 +  {
13522 +    UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_OFFSET_2_S1_DIRECT, "ext.2-d-indirect-with-offset-2-s1-direct", "ext.2", 32,
13523 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13524 +  },
13525 +/* ext.2 (${d-An}),${s1-direct-addr} */
13526 +  {
13527 +    UBICOM32_INSN_EXT_2_D_INDIRECT_2_S1_DIRECT, "ext.2-d-indirect-2-s1-direct", "ext.2", 32,
13528 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13529 +  },
13530 +/* ext.2 (${d-An})${d-i4-2}++,${s1-direct-addr} */
13531 +  {
13532 +    UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_DIRECT, "ext.2-d-indirect-with-post-increment-2-s1-direct", "ext.2", 32,
13533 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13534 +  },
13535 +/* ext.2 ${d-i4-2}(${d-An})++,${s1-direct-addr} */
13536 +  {
13537 +    UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_DIRECT, "ext.2-d-indirect-with-pre-increment-2-s1-direct", "ext.2", 32,
13538 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13539 +  },
13540 +/* ext.2 ${d-direct-addr},#${s1-imm8} */
13541 +  {
13542 +    UBICOM32_INSN_EXT_2_D_DIRECT_S1_IMMEDIATE, "ext.2-d-direct-s1-immediate", "ext.2", 32,
13543 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13544 +  },
13545 +/* ext.2 #${d-imm8},#${s1-imm8} */
13546 +  {
13547 +    UBICOM32_INSN_EXT_2_D_IMMEDIATE_2_S1_IMMEDIATE, "ext.2-d-immediate-2-s1-immediate", "ext.2", 32,
13548 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13549 +  },
13550 +/* ext.2 (${d-An},${d-r}),#${s1-imm8} */
13551 +  {
13552 +    UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_INDEX_2_S1_IMMEDIATE, "ext.2-d-indirect-with-index-2-s1-immediate", "ext.2", 32,
13553 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13554 +  },
13555 +/* ext.2 ${d-imm7-2}(${d-An}),#${s1-imm8} */
13556 +  {
13557 +    UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_OFFSET_2_S1_IMMEDIATE, "ext.2-d-indirect-with-offset-2-s1-immediate", "ext.2", 32,
13558 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13559 +  },
13560 +/* ext.2 (${d-An}),#${s1-imm8} */
13561 +  {
13562 +    UBICOM32_INSN_EXT_2_D_INDIRECT_2_S1_IMMEDIATE, "ext.2-d-indirect-2-s1-immediate", "ext.2", 32,
13563 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13564 +  },
13565 +/* ext.2 (${d-An})${d-i4-2}++,#${s1-imm8} */
13566 +  {
13567 +    UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_IMMEDIATE, "ext.2-d-indirect-with-post-increment-2-s1-immediate", "ext.2", 32,
13568 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13569 +  },
13570 +/* ext.2 ${d-i4-2}(${d-An})++,#${s1-imm8} */
13571 +  {
13572 +    UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_IMMEDIATE, "ext.2-d-indirect-with-pre-increment-2-s1-immediate", "ext.2", 32,
13573 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13574 +  },
13575 +/* ext.2 ${d-direct-addr},(${s1-An},${s1-r}) */
13576 +  {
13577 +    UBICOM32_INSN_EXT_2_D_DIRECT_S1_INDIRECT_WITH_INDEX_2, "ext.2-d-direct-s1-indirect-with-index-2", "ext.2", 32,
13578 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13579 +  },
13580 +/* ext.2 #${d-imm8},(${s1-An},${s1-r}) */
13581 +  {
13582 +    UBICOM32_INSN_EXT_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_INDEX_2, "ext.2-d-immediate-2-s1-indirect-with-index-2", "ext.2", 32,
13583 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13584 +  },
13585 +/* ext.2 (${d-An},${d-r}),(${s1-An},${s1-r}) */
13586 +  {
13587 +    UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_INDEX_2, "ext.2-d-indirect-with-index-2-s1-indirect-with-index-2", "ext.2", 32,
13588 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13589 +  },
13590 +/* ext.2 ${d-imm7-2}(${d-An}),(${s1-An},${s1-r}) */
13591 +  {
13592 +    UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_INDEX_2, "ext.2-d-indirect-with-offset-2-s1-indirect-with-index-2", "ext.2", 32,
13593 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13594 +  },
13595 +/* ext.2 (${d-An}),(${s1-An},${s1-r}) */
13596 +  {
13597 +    UBICOM32_INSN_EXT_2_D_INDIRECT_2_S1_INDIRECT_WITH_INDEX_2, "ext.2-d-indirect-2-s1-indirect-with-index-2", "ext.2", 32,
13598 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13599 +  },
13600 +/* ext.2 (${d-An})${d-i4-2}++,(${s1-An},${s1-r}) */
13601 +  {
13602 +    UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_INDEX_2, "ext.2-d-indirect-with-post-increment-2-s1-indirect-with-index-2", "ext.2", 32,
13603 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13604 +  },
13605 +/* ext.2 ${d-i4-2}(${d-An})++,(${s1-An},${s1-r}) */
13606 +  {
13607 +    UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_INDEX_2, "ext.2-d-indirect-with-pre-increment-2-s1-indirect-with-index-2", "ext.2", 32,
13608 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13609 +  },
13610 +/* ext.2 ${d-direct-addr},${s1-imm7-2}(${s1-An}) */
13611 +  {
13612 +    UBICOM32_INSN_EXT_2_D_DIRECT_S1_INDIRECT_WITH_OFFSET_2, "ext.2-d-direct-s1-indirect-with-offset-2", "ext.2", 32,
13613 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13614 +  },
13615 +/* ext.2 #${d-imm8},${s1-imm7-2}(${s1-An}) */
13616 +  {
13617 +    UBICOM32_INSN_EXT_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_OFFSET_2, "ext.2-d-immediate-2-s1-indirect-with-offset-2", "ext.2", 32,
13618 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13619 +  },
13620 +/* ext.2 (${d-An},${d-r}),${s1-imm7-2}(${s1-An}) */
13621 +  {
13622 +    UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_OFFSET_2, "ext.2-d-indirect-with-index-2-s1-indirect-with-offset-2", "ext.2", 32,
13623 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13624 +  },
13625 +/* ext.2 ${d-imm7-2}(${d-An}),${s1-imm7-2}(${s1-An}) */
13626 +  {
13627 +    UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_OFFSET_2, "ext.2-d-indirect-with-offset-2-s1-indirect-with-offset-2", "ext.2", 32,
13628 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13629 +  },
13630 +/* ext.2 (${d-An}),${s1-imm7-2}(${s1-An}) */
13631 +  {
13632 +    UBICOM32_INSN_EXT_2_D_INDIRECT_2_S1_INDIRECT_WITH_OFFSET_2, "ext.2-d-indirect-2-s1-indirect-with-offset-2", "ext.2", 32,
13633 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13634 +  },
13635 +/* ext.2 (${d-An})${d-i4-2}++,${s1-imm7-2}(${s1-An}) */
13636 +  {
13637 +    UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_2, "ext.2-d-indirect-with-post-increment-2-s1-indirect-with-offset-2", "ext.2", 32,
13638 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13639 +  },
13640 +/* ext.2 ${d-i4-2}(${d-An})++,${s1-imm7-2}(${s1-An}) */
13641 +  {
13642 +    UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_2, "ext.2-d-indirect-with-pre-increment-2-s1-indirect-with-offset-2", "ext.2", 32,
13643 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13644 +  },
13645 +/* ext.2 ${d-direct-addr},(${s1-An}) */
13646 +  {
13647 +    UBICOM32_INSN_EXT_2_D_DIRECT_S1_INDIRECT_2, "ext.2-d-direct-s1-indirect-2", "ext.2", 32,
13648 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13649 +  },
13650 +/* ext.2 #${d-imm8},(${s1-An}) */
13651 +  {
13652 +    UBICOM32_INSN_EXT_2_D_IMMEDIATE_2_S1_INDIRECT_2, "ext.2-d-immediate-2-s1-indirect-2", "ext.2", 32,
13653 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13654 +  },
13655 +/* ext.2 (${d-An},${d-r}),(${s1-An}) */
13656 +  {
13657 +    UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_2, "ext.2-d-indirect-with-index-2-s1-indirect-2", "ext.2", 32,
13658 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13659 +  },
13660 +/* ext.2 ${d-imm7-2}(${d-An}),(${s1-An}) */
13661 +  {
13662 +    UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_2, "ext.2-d-indirect-with-offset-2-s1-indirect-2", "ext.2", 32,
13663 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13664 +  },
13665 +/* ext.2 (${d-An}),(${s1-An}) */
13666 +  {
13667 +    UBICOM32_INSN_EXT_2_D_INDIRECT_2_S1_INDIRECT_2, "ext.2-d-indirect-2-s1-indirect-2", "ext.2", 32,
13668 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13669 +  },
13670 +/* ext.2 (${d-An})${d-i4-2}++,(${s1-An}) */
13671 +  {
13672 +    UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_2, "ext.2-d-indirect-with-post-increment-2-s1-indirect-2", "ext.2", 32,
13673 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13674 +  },
13675 +/* ext.2 ${d-i4-2}(${d-An})++,(${s1-An}) */
13676 +  {
13677 +    UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_2, "ext.2-d-indirect-with-pre-increment-2-s1-indirect-2", "ext.2", 32,
13678 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13679 +  },
13680 +/* ext.2 ${d-direct-addr},(${s1-An})${s1-i4-2}++ */
13681 +  {
13682 +    UBICOM32_INSN_EXT_2_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_2, "ext.2-d-direct-s1-indirect-with-post-increment-2", "ext.2", 32,
13683 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13684 +  },
13685 +/* ext.2 #${d-imm8},(${s1-An})${s1-i4-2}++ */
13686 +  {
13687 +    UBICOM32_INSN_EXT_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_POST_INCREMENT_2, "ext.2-d-immediate-2-s1-indirect-with-post-increment-2", "ext.2", 32,
13688 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13689 +  },
13690 +/* ext.2 (${d-An},${d-r}),(${s1-An})${s1-i4-2}++ */
13691 +  {
13692 +    UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_POST_INCREMENT_2, "ext.2-d-indirect-with-index-2-s1-indirect-with-post-increment-2", "ext.2", 32,
13693 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13694 +  },
13695 +/* ext.2 ${d-imm7-2}(${d-An}),(${s1-An})${s1-i4-2}++ */
13696 +  {
13697 +    UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_POST_INCREMENT_2, "ext.2-d-indirect-with-offset-2-s1-indirect-with-post-increment-2", "ext.2", 32,
13698 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13699 +  },
13700 +/* ext.2 (${d-An}),(${s1-An})${s1-i4-2}++ */
13701 +  {
13702 +    UBICOM32_INSN_EXT_2_D_INDIRECT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, "ext.2-d-indirect-2-s1-indirect-with-post-increment-2", "ext.2", 32,
13703 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13704 +  },
13705 +/* ext.2 (${d-An})${d-i4-2}++,(${s1-An})${s1-i4-2}++ */
13706 +  {
13707 +    UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, "ext.2-d-indirect-with-post-increment-2-s1-indirect-with-post-increment-2", "ext.2", 32,
13708 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13709 +  },
13710 +/* ext.2 ${d-i4-2}(${d-An})++,(${s1-An})${s1-i4-2}++ */
13711 +  {
13712 +    UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, "ext.2-d-indirect-with-pre-increment-2-s1-indirect-with-post-increment-2", "ext.2", 32,
13713 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13714 +  },
13715 +/* ext.2 ${d-direct-addr},${s1-i4-2}(${s1-An})++ */
13716 +  {
13717 +    UBICOM32_INSN_EXT_2_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_2, "ext.2-d-direct-s1-indirect-with-pre-increment-2", "ext.2", 32,
13718 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13719 +  },
13720 +/* ext.2 #${d-imm8},${s1-i4-2}(${s1-An})++ */
13721 +  {
13722 +    UBICOM32_INSN_EXT_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, "ext.2-d-immediate-2-s1-indirect-with-pre-increment-2", "ext.2", 32,
13723 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13724 +  },
13725 +/* ext.2 (${d-An},${d-r}),${s1-i4-2}(${s1-An})++ */
13726 +  {
13727 +    UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, "ext.2-d-indirect-with-index-2-s1-indirect-with-pre-increment-2", "ext.2", 32,
13728 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13729 +  },
13730 +/* ext.2 ${d-imm7-2}(${d-An}),${s1-i4-2}(${s1-An})++ */
13731 +  {
13732 +    UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, "ext.2-d-indirect-with-offset-2-s1-indirect-with-pre-increment-2", "ext.2", 32,
13733 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13734 +  },
13735 +/* ext.2 (${d-An}),${s1-i4-2}(${s1-An})++ */
13736 +  {
13737 +    UBICOM32_INSN_EXT_2_D_INDIRECT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, "ext.2-d-indirect-2-s1-indirect-with-pre-increment-2", "ext.2", 32,
13738 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13739 +  },
13740 +/* ext.2 (${d-An})${d-i4-2}++,${s1-i4-2}(${s1-An})++ */
13741 +  {
13742 +    UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, "ext.2-d-indirect-with-post-increment-2-s1-indirect-with-pre-increment-2", "ext.2", 32,
13743 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13744 +  },
13745 +/* ext.2 ${d-i4-2}(${d-An})++,${s1-i4-2}(${s1-An})++ */
13746 +  {
13747 +    UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, "ext.2-d-indirect-with-pre-increment-2-s1-indirect-with-pre-increment-2", "ext.2", 32,
13748 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13749 +  },
13750 +/* ext.1 ${d-direct-addr},${s1-direct-addr} */
13751 +  {
13752 +    UBICOM32_INSN_EXT_1_D_DIRECT_S1_DIRECT, "ext.1-d-direct-s1-direct", "ext.1", 32,
13753 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13754 +  },
13755 +/* ext.1 #${d-imm8},${s1-direct-addr} */
13756 +  {
13757 +    UBICOM32_INSN_EXT_1_D_IMMEDIATE_1_S1_DIRECT, "ext.1-d-immediate-1-s1-direct", "ext.1", 32,
13758 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13759 +  },
13760 +/* ext.1 (${d-An},${d-r}),${s1-direct-addr} */
13761 +  {
13762 +    UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_INDEX_1_S1_DIRECT, "ext.1-d-indirect-with-index-1-s1-direct", "ext.1", 32,
13763 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13764 +  },
13765 +/* ext.1 ${d-imm7-1}(${d-An}),${s1-direct-addr} */
13766 +  {
13767 +    UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_OFFSET_1_S1_DIRECT, "ext.1-d-indirect-with-offset-1-s1-direct", "ext.1", 32,
13768 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13769 +  },
13770 +/* ext.1 (${d-An}),${s1-direct-addr} */
13771 +  {
13772 +    UBICOM32_INSN_EXT_1_D_INDIRECT_1_S1_DIRECT, "ext.1-d-indirect-1-s1-direct", "ext.1", 32,
13773 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13774 +  },
13775 +/* ext.1 (${d-An})${d-i4-1}++,${s1-direct-addr} */
13776 +  {
13777 +    UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_DIRECT, "ext.1-d-indirect-with-post-increment-1-s1-direct", "ext.1", 32,
13778 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13779 +  },
13780 +/* ext.1 ${d-i4-1}(${d-An})++,${s1-direct-addr} */
13781 +  {
13782 +    UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_DIRECT, "ext.1-d-indirect-with-pre-increment-1-s1-direct", "ext.1", 32,
13783 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13784 +  },
13785 +/* ext.1 ${d-direct-addr},#${s1-imm8} */
13786 +  {
13787 +    UBICOM32_INSN_EXT_1_D_DIRECT_S1_IMMEDIATE, "ext.1-d-direct-s1-immediate", "ext.1", 32,
13788 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13789 +  },
13790 +/* ext.1 #${d-imm8},#${s1-imm8} */
13791 +  {
13792 +    UBICOM32_INSN_EXT_1_D_IMMEDIATE_1_S1_IMMEDIATE, "ext.1-d-immediate-1-s1-immediate", "ext.1", 32,
13793 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13794 +  },
13795 +/* ext.1 (${d-An},${d-r}),#${s1-imm8} */
13796 +  {
13797 +    UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_INDEX_1_S1_IMMEDIATE, "ext.1-d-indirect-with-index-1-s1-immediate", "ext.1", 32,
13798 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13799 +  },
13800 +/* ext.1 ${d-imm7-1}(${d-An}),#${s1-imm8} */
13801 +  {
13802 +    UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_OFFSET_1_S1_IMMEDIATE, "ext.1-d-indirect-with-offset-1-s1-immediate", "ext.1", 32,
13803 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13804 +  },
13805 +/* ext.1 (${d-An}),#${s1-imm8} */
13806 +  {
13807 +    UBICOM32_INSN_EXT_1_D_INDIRECT_1_S1_IMMEDIATE, "ext.1-d-indirect-1-s1-immediate", "ext.1", 32,
13808 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13809 +  },
13810 +/* ext.1 (${d-An})${d-i4-1}++,#${s1-imm8} */
13811 +  {
13812 +    UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_IMMEDIATE, "ext.1-d-indirect-with-post-increment-1-s1-immediate", "ext.1", 32,
13813 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13814 +  },
13815 +/* ext.1 ${d-i4-1}(${d-An})++,#${s1-imm8} */
13816 +  {
13817 +    UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_IMMEDIATE, "ext.1-d-indirect-with-pre-increment-1-s1-immediate", "ext.1", 32,
13818 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13819 +  },
13820 +/* ext.1 ${d-direct-addr},(${s1-An},${s1-r}) */
13821 +  {
13822 +    UBICOM32_INSN_EXT_1_D_DIRECT_S1_INDIRECT_WITH_INDEX_1, "ext.1-d-direct-s1-indirect-with-index-1", "ext.1", 32,
13823 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13824 +  },
13825 +/* ext.1 #${d-imm8},(${s1-An},${s1-r}) */
13826 +  {
13827 +    UBICOM32_INSN_EXT_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_INDEX_1, "ext.1-d-immediate-1-s1-indirect-with-index-1", "ext.1", 32,
13828 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13829 +  },
13830 +/* ext.1 (${d-An},${d-r}),(${s1-An},${s1-r}) */
13831 +  {
13832 +    UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_INDEX_1, "ext.1-d-indirect-with-index-1-s1-indirect-with-index-1", "ext.1", 32,
13833 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13834 +  },
13835 +/* ext.1 ${d-imm7-1}(${d-An}),(${s1-An},${s1-r}) */
13836 +  {
13837 +    UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_INDEX_1, "ext.1-d-indirect-with-offset-1-s1-indirect-with-index-1", "ext.1", 32,
13838 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13839 +  },
13840 +/* ext.1 (${d-An}),(${s1-An},${s1-r}) */
13841 +  {
13842 +    UBICOM32_INSN_EXT_1_D_INDIRECT_1_S1_INDIRECT_WITH_INDEX_1, "ext.1-d-indirect-1-s1-indirect-with-index-1", "ext.1", 32,
13843 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13844 +  },
13845 +/* ext.1 (${d-An})${d-i4-1}++,(${s1-An},${s1-r}) */
13846 +  {
13847 +    UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_INDEX_1, "ext.1-d-indirect-with-post-increment-1-s1-indirect-with-index-1", "ext.1", 32,
13848 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13849 +  },
13850 +/* ext.1 ${d-i4-1}(${d-An})++,(${s1-An},${s1-r}) */
13851 +  {
13852 +    UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_INDEX_1, "ext.1-d-indirect-with-pre-increment-1-s1-indirect-with-index-1", "ext.1", 32,
13853 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13854 +  },
13855 +/* ext.1 ${d-direct-addr},${s1-imm7-1}(${s1-An}) */
13856 +  {
13857 +    UBICOM32_INSN_EXT_1_D_DIRECT_S1_INDIRECT_WITH_OFFSET_1, "ext.1-d-direct-s1-indirect-with-offset-1", "ext.1", 32,
13858 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13859 +  },
13860 +/* ext.1 #${d-imm8},${s1-imm7-1}(${s1-An}) */
13861 +  {
13862 +    UBICOM32_INSN_EXT_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_OFFSET_1, "ext.1-d-immediate-1-s1-indirect-with-offset-1", "ext.1", 32,
13863 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13864 +  },
13865 +/* ext.1 (${d-An},${d-r}),${s1-imm7-1}(${s1-An}) */
13866 +  {
13867 +    UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_OFFSET_1, "ext.1-d-indirect-with-index-1-s1-indirect-with-offset-1", "ext.1", 32,
13868 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13869 +  },
13870 +/* ext.1 ${d-imm7-1}(${d-An}),${s1-imm7-1}(${s1-An}) */
13871 +  {
13872 +    UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_OFFSET_1, "ext.1-d-indirect-with-offset-1-s1-indirect-with-offset-1", "ext.1", 32,
13873 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13874 +  },
13875 +/* ext.1 (${d-An}),${s1-imm7-1}(${s1-An}) */
13876 +  {
13877 +    UBICOM32_INSN_EXT_1_D_INDIRECT_1_S1_INDIRECT_WITH_OFFSET_1, "ext.1-d-indirect-1-s1-indirect-with-offset-1", "ext.1", 32,
13878 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13879 +  },
13880 +/* ext.1 (${d-An})${d-i4-1}++,${s1-imm7-1}(${s1-An}) */
13881 +  {
13882 +    UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_OFFSET_1, "ext.1-d-indirect-with-post-increment-1-s1-indirect-with-offset-1", "ext.1", 32,
13883 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13884 +  },
13885 +/* ext.1 ${d-i4-1}(${d-An})++,${s1-imm7-1}(${s1-An}) */
13886 +  {
13887 +    UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_OFFSET_1, "ext.1-d-indirect-with-pre-increment-1-s1-indirect-with-offset-1", "ext.1", 32,
13888 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13889 +  },
13890 +/* ext.1 ${d-direct-addr},(${s1-An}) */
13891 +  {
13892 +    UBICOM32_INSN_EXT_1_D_DIRECT_S1_INDIRECT_1, "ext.1-d-direct-s1-indirect-1", "ext.1", 32,
13893 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13894 +  },
13895 +/* ext.1 #${d-imm8},(${s1-An}) */
13896 +  {
13897 +    UBICOM32_INSN_EXT_1_D_IMMEDIATE_1_S1_INDIRECT_1, "ext.1-d-immediate-1-s1-indirect-1", "ext.1", 32,
13898 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13899 +  },
13900 +/* ext.1 (${d-An},${d-r}),(${s1-An}) */
13901 +  {
13902 +    UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_1, "ext.1-d-indirect-with-index-1-s1-indirect-1", "ext.1", 32,
13903 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13904 +  },
13905 +/* ext.1 ${d-imm7-1}(${d-An}),(${s1-An}) */
13906 +  {
13907 +    UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_1, "ext.1-d-indirect-with-offset-1-s1-indirect-1", "ext.1", 32,
13908 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13909 +  },
13910 +/* ext.1 (${d-An}),(${s1-An}) */
13911 +  {
13912 +    UBICOM32_INSN_EXT_1_D_INDIRECT_1_S1_INDIRECT_1, "ext.1-d-indirect-1-s1-indirect-1", "ext.1", 32,
13913 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13914 +  },
13915 +/* ext.1 (${d-An})${d-i4-1}++,(${s1-An}) */
13916 +  {
13917 +    UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_1, "ext.1-d-indirect-with-post-increment-1-s1-indirect-1", "ext.1", 32,
13918 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13919 +  },
13920 +/* ext.1 ${d-i4-1}(${d-An})++,(${s1-An}) */
13921 +  {
13922 +    UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_1, "ext.1-d-indirect-with-pre-increment-1-s1-indirect-1", "ext.1", 32,
13923 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13924 +  },
13925 +/* ext.1 ${d-direct-addr},(${s1-An})${s1-i4-1}++ */
13926 +  {
13927 +    UBICOM32_INSN_EXT_1_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_1, "ext.1-d-direct-s1-indirect-with-post-increment-1", "ext.1", 32,
13928 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13929 +  },
13930 +/* ext.1 #${d-imm8},(${s1-An})${s1-i4-1}++ */
13931 +  {
13932 +    UBICOM32_INSN_EXT_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_POST_INCREMENT_1, "ext.1-d-immediate-1-s1-indirect-with-post-increment-1", "ext.1", 32,
13933 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13934 +  },
13935 +/* ext.1 (${d-An},${d-r}),(${s1-An})${s1-i4-1}++ */
13936 +  {
13937 +    UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_POST_INCREMENT_1, "ext.1-d-indirect-with-index-1-s1-indirect-with-post-increment-1", "ext.1", 32,
13938 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13939 +  },
13940 +/* ext.1 ${d-imm7-1}(${d-An}),(${s1-An})${s1-i4-1}++ */
13941 +  {
13942 +    UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_POST_INCREMENT_1, "ext.1-d-indirect-with-offset-1-s1-indirect-with-post-increment-1", "ext.1", 32,
13943 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13944 +  },
13945 +/* ext.1 (${d-An}),(${s1-An})${s1-i4-1}++ */
13946 +  {
13947 +    UBICOM32_INSN_EXT_1_D_INDIRECT_1_S1_INDIRECT_WITH_POST_INCREMENT_1, "ext.1-d-indirect-1-s1-indirect-with-post-increment-1", "ext.1", 32,
13948 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13949 +  },
13950 +/* ext.1 (${d-An})${d-i4-1}++,(${s1-An})${s1-i4-1}++ */
13951 +  {
13952 +    UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_POST_INCREMENT_1, "ext.1-d-indirect-with-post-increment-1-s1-indirect-with-post-increment-1", "ext.1", 32,
13953 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13954 +  },
13955 +/* ext.1 ${d-i4-1}(${d-An})++,(${s1-An})${s1-i4-1}++ */
13956 +  {
13957 +    UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_POST_INCREMENT_1, "ext.1-d-indirect-with-pre-increment-1-s1-indirect-with-post-increment-1", "ext.1", 32,
13958 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13959 +  },
13960 +/* ext.1 ${d-direct-addr},${s1-i4-1}(${s1-An})++ */
13961 +  {
13962 +    UBICOM32_INSN_EXT_1_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_1, "ext.1-d-direct-s1-indirect-with-pre-increment-1", "ext.1", 32,
13963 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13964 +  },
13965 +/* ext.1 #${d-imm8},${s1-i4-1}(${s1-An})++ */
13966 +  {
13967 +    UBICOM32_INSN_EXT_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, "ext.1-d-immediate-1-s1-indirect-with-pre-increment-1", "ext.1", 32,
13968 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13969 +  },
13970 +/* ext.1 (${d-An},${d-r}),${s1-i4-1}(${s1-An})++ */
13971 +  {
13972 +    UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, "ext.1-d-indirect-with-index-1-s1-indirect-with-pre-increment-1", "ext.1", 32,
13973 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13974 +  },
13975 +/* ext.1 ${d-imm7-1}(${d-An}),${s1-i4-1}(${s1-An})++ */
13976 +  {
13977 +    UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, "ext.1-d-indirect-with-offset-1-s1-indirect-with-pre-increment-1", "ext.1", 32,
13978 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13979 +  },
13980 +/* ext.1 (${d-An}),${s1-i4-1}(${s1-An})++ */
13981 +  {
13982 +    UBICOM32_INSN_EXT_1_D_INDIRECT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, "ext.1-d-indirect-1-s1-indirect-with-pre-increment-1", "ext.1", 32,
13983 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13984 +  },
13985 +/* ext.1 (${d-An})${d-i4-1}++,${s1-i4-1}(${s1-An})++ */
13986 +  {
13987 +    UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, "ext.1-d-indirect-with-post-increment-1-s1-indirect-with-pre-increment-1", "ext.1", 32,
13988 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13989 +  },
13990 +/* ext.1 ${d-i4-1}(${d-An})++,${s1-i4-1}(${s1-An})++ */
13991 +  {
13992 +    UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, "ext.1-d-indirect-with-pre-increment-1-s1-indirect-with-pre-increment-1", "ext.1", 32,
13993 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13994 +  },
13995 +/* movei ${d-direct-addr},#${imm16-2} */
13996 +  {
13997 +    UBICOM32_INSN_MOVEI_D_DIRECT, "movei-d-direct", "movei", 32,
13998 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
13999 +  },
14000 +/* movei #${d-imm8},#${imm16-2} */
14001 +  {
14002 +    UBICOM32_INSN_MOVEI_D_IMMEDIATE_2, "movei-d-immediate-2", "movei", 32,
14003 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14004 +  },
14005 +/* movei (${d-An},${d-r}),#${imm16-2} */
14006 +  {
14007 +    UBICOM32_INSN_MOVEI_D_INDIRECT_WITH_INDEX_2, "movei-d-indirect-with-index-2", "movei", 32,
14008 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14009 +  },
14010 +/* movei ${d-imm7-2}(${d-An}),#${imm16-2} */
14011 +  {
14012 +    UBICOM32_INSN_MOVEI_D_INDIRECT_WITH_OFFSET_2, "movei-d-indirect-with-offset-2", "movei", 32,
14013 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14014 +  },
14015 +/* movei (${d-An}),#${imm16-2} */
14016 +  {
14017 +    UBICOM32_INSN_MOVEI_D_INDIRECT_2, "movei-d-indirect-2", "movei", 32,
14018 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14019 +  },
14020 +/* movei (${d-An})${d-i4-2}++,#${imm16-2} */
14021 +  {
14022 +    UBICOM32_INSN_MOVEI_D_INDIRECT_WITH_POST_INCREMENT_2, "movei-d-indirect-with-post-increment-2", "movei", 32,
14023 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14024 +  },
14025 +/* movei ${d-i4-2}(${d-An})++,#${imm16-2} */
14026 +  {
14027 +    UBICOM32_INSN_MOVEI_D_INDIRECT_WITH_PRE_INCREMENT_2, "movei-d-indirect-with-pre-increment-2", "movei", 32,
14028 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14029 +  },
14030 +/* bclr ${d-direct-addr},${s1-direct-addr},#${bit5} */
14031 +  {
14032 +    UBICOM32_INSN_BCLR_D_DIRECT_S1_DIRECT, "bclr-d-direct-s1-direct", "bclr", 32,
14033 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14034 +  },
14035 +/* bclr #${d-imm8},${s1-direct-addr},#${bit5} */
14036 +  {
14037 +    UBICOM32_INSN_BCLR_D_IMMEDIATE_4_S1_DIRECT, "bclr-d-immediate-4-s1-direct", "bclr", 32,
14038 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14039 +  },
14040 +/* bclr (${d-An},${d-r}),${s1-direct-addr},#${bit5} */
14041 +  {
14042 +    UBICOM32_INSN_BCLR_D_INDIRECT_WITH_INDEX_4_S1_DIRECT, "bclr-d-indirect-with-index-4-s1-direct", "bclr", 32,
14043 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14044 +  },
14045 +/* bclr ${d-imm7-4}(${d-An}),${s1-direct-addr},#${bit5} */
14046 +  {
14047 +    UBICOM32_INSN_BCLR_D_INDIRECT_WITH_OFFSET_4_S1_DIRECT, "bclr-d-indirect-with-offset-4-s1-direct", "bclr", 32,
14048 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14049 +  },
14050 +/* bclr (${d-An}),${s1-direct-addr},#${bit5} */
14051 +  {
14052 +    UBICOM32_INSN_BCLR_D_INDIRECT_4_S1_DIRECT, "bclr-d-indirect-4-s1-direct", "bclr", 32,
14053 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14054 +  },
14055 +/* bclr (${d-An})${d-i4-4}++,${s1-direct-addr},#${bit5} */
14056 +  {
14057 +    UBICOM32_INSN_BCLR_D_INDIRECT_WITH_POST_INCREMENT_4_S1_DIRECT, "bclr-d-indirect-with-post-increment-4-s1-direct", "bclr", 32,
14058 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14059 +  },
14060 +/* bclr ${d-i4-4}(${d-An})++,${s1-direct-addr},#${bit5} */
14061 +  {
14062 +    UBICOM32_INSN_BCLR_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_DIRECT, "bclr-d-indirect-with-pre-increment-4-s1-direct", "bclr", 32,
14063 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14064 +  },
14065 +/* bclr ${d-direct-addr},#${s1-imm8},#${bit5} */
14066 +  {
14067 +    UBICOM32_INSN_BCLR_D_DIRECT_S1_IMMEDIATE, "bclr-d-direct-s1-immediate", "bclr", 32,
14068 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14069 +  },
14070 +/* bclr #${d-imm8},#${s1-imm8},#${bit5} */
14071 +  {
14072 +    UBICOM32_INSN_BCLR_D_IMMEDIATE_4_S1_IMMEDIATE, "bclr-d-immediate-4-s1-immediate", "bclr", 32,
14073 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14074 +  },
14075 +/* bclr (${d-An},${d-r}),#${s1-imm8},#${bit5} */
14076 +  {
14077 +    UBICOM32_INSN_BCLR_D_INDIRECT_WITH_INDEX_4_S1_IMMEDIATE, "bclr-d-indirect-with-index-4-s1-immediate", "bclr", 32,
14078 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14079 +  },
14080 +/* bclr ${d-imm7-4}(${d-An}),#${s1-imm8},#${bit5} */
14081 +  {
14082 +    UBICOM32_INSN_BCLR_D_INDIRECT_WITH_OFFSET_4_S1_IMMEDIATE, "bclr-d-indirect-with-offset-4-s1-immediate", "bclr", 32,
14083 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14084 +  },
14085 +/* bclr (${d-An}),#${s1-imm8},#${bit5} */
14086 +  {
14087 +    UBICOM32_INSN_BCLR_D_INDIRECT_4_S1_IMMEDIATE, "bclr-d-indirect-4-s1-immediate", "bclr", 32,
14088 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14089 +  },
14090 +/* bclr (${d-An})${d-i4-4}++,#${s1-imm8},#${bit5} */
14091 +  {
14092 +    UBICOM32_INSN_BCLR_D_INDIRECT_WITH_POST_INCREMENT_4_S1_IMMEDIATE, "bclr-d-indirect-with-post-increment-4-s1-immediate", "bclr", 32,
14093 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14094 +  },
14095 +/* bclr ${d-i4-4}(${d-An})++,#${s1-imm8},#${bit5} */
14096 +  {
14097 +    UBICOM32_INSN_BCLR_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_IMMEDIATE, "bclr-d-indirect-with-pre-increment-4-s1-immediate", "bclr", 32,
14098 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14099 +  },
14100 +/* bclr ${d-direct-addr},(${s1-An},${s1-r}),#${bit5} */
14101 +  {
14102 +    UBICOM32_INSN_BCLR_D_DIRECT_S1_INDIRECT_WITH_INDEX_4, "bclr-d-direct-s1-indirect-with-index-4", "bclr", 32,
14103 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14104 +  },
14105 +/* bclr #${d-imm8},(${s1-An},${s1-r}),#${bit5} */
14106 +  {
14107 +    UBICOM32_INSN_BCLR_D_IMMEDIATE_4_S1_INDIRECT_WITH_INDEX_4, "bclr-d-immediate-4-s1-indirect-with-index-4", "bclr", 32,
14108 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14109 +  },
14110 +/* bclr (${d-An},${d-r}),(${s1-An},${s1-r}),#${bit5} */
14111 +  {
14112 +    UBICOM32_INSN_BCLR_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_INDEX_4, "bclr-d-indirect-with-index-4-s1-indirect-with-index-4", "bclr", 32,
14113 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14114 +  },
14115 +/* bclr ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}),#${bit5} */
14116 +  {
14117 +    UBICOM32_INSN_BCLR_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_INDEX_4, "bclr-d-indirect-with-offset-4-s1-indirect-with-index-4", "bclr", 32,
14118 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14119 +  },
14120 +/* bclr (${d-An}),(${s1-An},${s1-r}),#${bit5} */
14121 +  {
14122 +    UBICOM32_INSN_BCLR_D_INDIRECT_4_S1_INDIRECT_WITH_INDEX_4, "bclr-d-indirect-4-s1-indirect-with-index-4", "bclr", 32,
14123 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14124 +  },
14125 +/* bclr (${d-An})${d-i4-4}++,(${s1-An},${s1-r}),#${bit5} */
14126 +  {
14127 +    UBICOM32_INSN_BCLR_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, "bclr-d-indirect-with-post-increment-4-s1-indirect-with-index-4", "bclr", 32,
14128 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14129 +  },
14130 +/* bclr ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}),#${bit5} */
14131 +  {
14132 +    UBICOM32_INSN_BCLR_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, "bclr-d-indirect-with-pre-increment-4-s1-indirect-with-index-4", "bclr", 32,
14133 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14134 +  },
14135 +/* bclr ${d-direct-addr},${s1-imm7-4}(${s1-An}),#${bit5} */
14136 +  {
14137 +    UBICOM32_INSN_BCLR_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4, "bclr-d-direct-s1-indirect-with-offset-4", "bclr", 32,
14138 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14139 +  },
14140 +/* bclr #${d-imm8},${s1-imm7-4}(${s1-An}),#${bit5} */
14141 +  {
14142 +    UBICOM32_INSN_BCLR_D_IMMEDIATE_4_S1_INDIRECT_WITH_OFFSET_4, "bclr-d-immediate-4-s1-indirect-with-offset-4", "bclr", 32,
14143 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14144 +  },
14145 +/* bclr (${d-An},${d-r}),${s1-imm7-4}(${s1-An}),#${bit5} */
14146 +  {
14147 +    UBICOM32_INSN_BCLR_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_OFFSET_4, "bclr-d-indirect-with-index-4-s1-indirect-with-offset-4", "bclr", 32,
14148 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14149 +  },
14150 +/* bclr ${d-imm7-4}(${d-An}),${s1-imm7-4}(${s1-An}),#${bit5} */
14151 +  {
14152 +    UBICOM32_INSN_BCLR_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_OFFSET_4, "bclr-d-indirect-with-offset-4-s1-indirect-with-offset-4", "bclr", 32,
14153 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14154 +  },
14155 +/* bclr (${d-An}),${s1-imm7-4}(${s1-An}),#${bit5} */
14156 +  {
14157 +    UBICOM32_INSN_BCLR_D_INDIRECT_4_S1_INDIRECT_WITH_OFFSET_4, "bclr-d-indirect-4-s1-indirect-with-offset-4", "bclr", 32,
14158 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14159 +  },
14160 +/* bclr (${d-An})${d-i4-4}++,${s1-imm7-4}(${s1-An}),#${bit5} */
14161 +  {
14162 +    UBICOM32_INSN_BCLR_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, "bclr-d-indirect-with-post-increment-4-s1-indirect-with-offset-4", "bclr", 32,
14163 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14164 +  },
14165 +/* bclr ${d-i4-4}(${d-An})++,${s1-imm7-4}(${s1-An}),#${bit5} */
14166 +  {
14167 +    UBICOM32_INSN_BCLR_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, "bclr-d-indirect-with-pre-increment-4-s1-indirect-with-offset-4", "bclr", 32,
14168 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14169 +  },
14170 +/* bclr ${d-direct-addr},(${s1-An}),#${bit5} */
14171 +  {
14172 +    UBICOM32_INSN_BCLR_D_DIRECT_S1_INDIRECT_4, "bclr-d-direct-s1-indirect-4", "bclr", 32,
14173 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14174 +  },
14175 +/* bclr #${d-imm8},(${s1-An}),#${bit5} */
14176 +  {
14177 +    UBICOM32_INSN_BCLR_D_IMMEDIATE_4_S1_INDIRECT_4, "bclr-d-immediate-4-s1-indirect-4", "bclr", 32,
14178 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14179 +  },
14180 +/* bclr (${d-An},${d-r}),(${s1-An}),#${bit5} */
14181 +  {
14182 +    UBICOM32_INSN_BCLR_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_4, "bclr-d-indirect-with-index-4-s1-indirect-4", "bclr", 32,
14183 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14184 +  },
14185 +/* bclr ${d-imm7-4}(${d-An}),(${s1-An}),#${bit5} */
14186 +  {
14187 +    UBICOM32_INSN_BCLR_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_4, "bclr-d-indirect-with-offset-4-s1-indirect-4", "bclr", 32,
14188 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14189 +  },
14190 +/* bclr (${d-An}),(${s1-An}),#${bit5} */
14191 +  {
14192 +    UBICOM32_INSN_BCLR_D_INDIRECT_4_S1_INDIRECT_4, "bclr-d-indirect-4-s1-indirect-4", "bclr", 32,
14193 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14194 +  },
14195 +/* bclr (${d-An})${d-i4-4}++,(${s1-An}),#${bit5} */
14196 +  {
14197 +    UBICOM32_INSN_BCLR_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_4, "bclr-d-indirect-with-post-increment-4-s1-indirect-4", "bclr", 32,
14198 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14199 +  },
14200 +/* bclr ${d-i4-4}(${d-An})++,(${s1-An}),#${bit5} */
14201 +  {
14202 +    UBICOM32_INSN_BCLR_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_4, "bclr-d-indirect-with-pre-increment-4-s1-indirect-4", "bclr", 32,
14203 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14204 +  },
14205 +/* bclr ${d-direct-addr},(${s1-An})${s1-i4-4}++,#${bit5} */
14206 +  {
14207 +    UBICOM32_INSN_BCLR_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4, "bclr-d-direct-s1-indirect-with-post-increment-4", "bclr", 32,
14208 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14209 +  },
14210 +/* bclr #${d-imm8},(${s1-An})${s1-i4-4}++,#${bit5} */
14211 +  {
14212 +    UBICOM32_INSN_BCLR_D_IMMEDIATE_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "bclr-d-immediate-4-s1-indirect-with-post-increment-4", "bclr", 32,
14213 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14214 +  },
14215 +/* bclr (${d-An},${d-r}),(${s1-An})${s1-i4-4}++,#${bit5} */
14216 +  {
14217 +    UBICOM32_INSN_BCLR_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "bclr-d-indirect-with-index-4-s1-indirect-with-post-increment-4", "bclr", 32,
14218 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14219 +  },
14220 +/* bclr ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-4}++,#${bit5} */
14221 +  {
14222 +    UBICOM32_INSN_BCLR_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "bclr-d-indirect-with-offset-4-s1-indirect-with-post-increment-4", "bclr", 32,
14223 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14224 +  },
14225 +/* bclr (${d-An}),(${s1-An})${s1-i4-4}++,#${bit5} */
14226 +  {
14227 +    UBICOM32_INSN_BCLR_D_INDIRECT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "bclr-d-indirect-4-s1-indirect-with-post-increment-4", "bclr", 32,
14228 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14229 +  },
14230 +/* bclr (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-4}++,#${bit5} */
14231 +  {
14232 +    UBICOM32_INSN_BCLR_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "bclr-d-indirect-with-post-increment-4-s1-indirect-with-post-increment-4", "bclr", 32,
14233 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14234 +  },
14235 +/* bclr ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-4}++,#${bit5} */
14236 +  {
14237 +    UBICOM32_INSN_BCLR_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "bclr-d-indirect-with-pre-increment-4-s1-indirect-with-post-increment-4", "bclr", 32,
14238 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14239 +  },
14240 +/* bclr ${d-direct-addr},${s1-i4-4}(${s1-An})++,#${bit5} */
14241 +  {
14242 +    UBICOM32_INSN_BCLR_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4, "bclr-d-direct-s1-indirect-with-pre-increment-4", "bclr", 32,
14243 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14244 +  },
14245 +/* bclr #${d-imm8},${s1-i4-4}(${s1-An})++,#${bit5} */
14246 +  {
14247 +    UBICOM32_INSN_BCLR_D_IMMEDIATE_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "bclr-d-immediate-4-s1-indirect-with-pre-increment-4", "bclr", 32,
14248 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14249 +  },
14250 +/* bclr (${d-An},${d-r}),${s1-i4-4}(${s1-An})++,#${bit5} */
14251 +  {
14252 +    UBICOM32_INSN_BCLR_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "bclr-d-indirect-with-index-4-s1-indirect-with-pre-increment-4", "bclr", 32,
14253 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14254 +  },
14255 +/* bclr ${d-imm7-4}(${d-An}),${s1-i4-4}(${s1-An})++,#${bit5} */
14256 +  {
14257 +    UBICOM32_INSN_BCLR_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "bclr-d-indirect-with-offset-4-s1-indirect-with-pre-increment-4", "bclr", 32,
14258 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14259 +  },
14260 +/* bclr (${d-An}),${s1-i4-4}(${s1-An})++,#${bit5} */
14261 +  {
14262 +    UBICOM32_INSN_BCLR_D_INDIRECT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "bclr-d-indirect-4-s1-indirect-with-pre-increment-4", "bclr", 32,
14263 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14264 +  },
14265 +/* bclr (${d-An})${d-i4-4}++,${s1-i4-4}(${s1-An})++,#${bit5} */
14266 +  {
14267 +    UBICOM32_INSN_BCLR_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "bclr-d-indirect-with-post-increment-4-s1-indirect-with-pre-increment-4", "bclr", 32,
14268 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14269 +  },
14270 +/* bclr ${d-i4-4}(${d-An})++,${s1-i4-4}(${s1-An})++,#${bit5} */
14271 +  {
14272 +    UBICOM32_INSN_BCLR_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "bclr-d-indirect-with-pre-increment-4-s1-indirect-with-pre-increment-4", "bclr", 32,
14273 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14274 +  },
14275 +/* bset ${d-direct-addr},${s1-direct-addr},#${bit5} */
14276 +  {
14277 +    UBICOM32_INSN_BSET_D_DIRECT_S1_DIRECT, "bset-d-direct-s1-direct", "bset", 32,
14278 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14279 +  },
14280 +/* bset #${d-imm8},${s1-direct-addr},#${bit5} */
14281 +  {
14282 +    UBICOM32_INSN_BSET_D_IMMEDIATE_4_S1_DIRECT, "bset-d-immediate-4-s1-direct", "bset", 32,
14283 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14284 +  },
14285 +/* bset (${d-An},${d-r}),${s1-direct-addr},#${bit5} */
14286 +  {
14287 +    UBICOM32_INSN_BSET_D_INDIRECT_WITH_INDEX_4_S1_DIRECT, "bset-d-indirect-with-index-4-s1-direct", "bset", 32,
14288 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14289 +  },
14290 +/* bset ${d-imm7-4}(${d-An}),${s1-direct-addr},#${bit5} */
14291 +  {
14292 +    UBICOM32_INSN_BSET_D_INDIRECT_WITH_OFFSET_4_S1_DIRECT, "bset-d-indirect-with-offset-4-s1-direct", "bset", 32,
14293 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14294 +  },
14295 +/* bset (${d-An}),${s1-direct-addr},#${bit5} */
14296 +  {
14297 +    UBICOM32_INSN_BSET_D_INDIRECT_4_S1_DIRECT, "bset-d-indirect-4-s1-direct", "bset", 32,
14298 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14299 +  },
14300 +/* bset (${d-An})${d-i4-4}++,${s1-direct-addr},#${bit5} */
14301 +  {
14302 +    UBICOM32_INSN_BSET_D_INDIRECT_WITH_POST_INCREMENT_4_S1_DIRECT, "bset-d-indirect-with-post-increment-4-s1-direct", "bset", 32,
14303 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14304 +  },
14305 +/* bset ${d-i4-4}(${d-An})++,${s1-direct-addr},#${bit5} */
14306 +  {
14307 +    UBICOM32_INSN_BSET_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_DIRECT, "bset-d-indirect-with-pre-increment-4-s1-direct", "bset", 32,
14308 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14309 +  },
14310 +/* bset ${d-direct-addr},#${s1-imm8},#${bit5} */
14311 +  {
14312 +    UBICOM32_INSN_BSET_D_DIRECT_S1_IMMEDIATE, "bset-d-direct-s1-immediate", "bset", 32,
14313 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14314 +  },
14315 +/* bset #${d-imm8},#${s1-imm8},#${bit5} */
14316 +  {
14317 +    UBICOM32_INSN_BSET_D_IMMEDIATE_4_S1_IMMEDIATE, "bset-d-immediate-4-s1-immediate", "bset", 32,
14318 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14319 +  },
14320 +/* bset (${d-An},${d-r}),#${s1-imm8},#${bit5} */
14321 +  {
14322 +    UBICOM32_INSN_BSET_D_INDIRECT_WITH_INDEX_4_S1_IMMEDIATE, "bset-d-indirect-with-index-4-s1-immediate", "bset", 32,
14323 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14324 +  },
14325 +/* bset ${d-imm7-4}(${d-An}),#${s1-imm8},#${bit5} */
14326 +  {
14327 +    UBICOM32_INSN_BSET_D_INDIRECT_WITH_OFFSET_4_S1_IMMEDIATE, "bset-d-indirect-with-offset-4-s1-immediate", "bset", 32,
14328 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14329 +  },
14330 +/* bset (${d-An}),#${s1-imm8},#${bit5} */
14331 +  {
14332 +    UBICOM32_INSN_BSET_D_INDIRECT_4_S1_IMMEDIATE, "bset-d-indirect-4-s1-immediate", "bset", 32,
14333 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14334 +  },
14335 +/* bset (${d-An})${d-i4-4}++,#${s1-imm8},#${bit5} */
14336 +  {
14337 +    UBICOM32_INSN_BSET_D_INDIRECT_WITH_POST_INCREMENT_4_S1_IMMEDIATE, "bset-d-indirect-with-post-increment-4-s1-immediate", "bset", 32,
14338 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14339 +  },
14340 +/* bset ${d-i4-4}(${d-An})++,#${s1-imm8},#${bit5} */
14341 +  {
14342 +    UBICOM32_INSN_BSET_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_IMMEDIATE, "bset-d-indirect-with-pre-increment-4-s1-immediate", "bset", 32,
14343 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14344 +  },
14345 +/* bset ${d-direct-addr},(${s1-An},${s1-r}),#${bit5} */
14346 +  {
14347 +    UBICOM32_INSN_BSET_D_DIRECT_S1_INDIRECT_WITH_INDEX_4, "bset-d-direct-s1-indirect-with-index-4", "bset", 32,
14348 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14349 +  },
14350 +/* bset #${d-imm8},(${s1-An},${s1-r}),#${bit5} */
14351 +  {
14352 +    UBICOM32_INSN_BSET_D_IMMEDIATE_4_S1_INDIRECT_WITH_INDEX_4, "bset-d-immediate-4-s1-indirect-with-index-4", "bset", 32,
14353 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14354 +  },
14355 +/* bset (${d-An},${d-r}),(${s1-An},${s1-r}),#${bit5} */
14356 +  {
14357 +    UBICOM32_INSN_BSET_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_INDEX_4, "bset-d-indirect-with-index-4-s1-indirect-with-index-4", "bset", 32,
14358 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14359 +  },
14360 +/* bset ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}),#${bit5} */
14361 +  {
14362 +    UBICOM32_INSN_BSET_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_INDEX_4, "bset-d-indirect-with-offset-4-s1-indirect-with-index-4", "bset", 32,
14363 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14364 +  },
14365 +/* bset (${d-An}),(${s1-An},${s1-r}),#${bit5} */
14366 +  {
14367 +    UBICOM32_INSN_BSET_D_INDIRECT_4_S1_INDIRECT_WITH_INDEX_4, "bset-d-indirect-4-s1-indirect-with-index-4", "bset", 32,
14368 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14369 +  },
14370 +/* bset (${d-An})${d-i4-4}++,(${s1-An},${s1-r}),#${bit5} */
14371 +  {
14372 +    UBICOM32_INSN_BSET_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, "bset-d-indirect-with-post-increment-4-s1-indirect-with-index-4", "bset", 32,
14373 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14374 +  },
14375 +/* bset ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}),#${bit5} */
14376 +  {
14377 +    UBICOM32_INSN_BSET_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, "bset-d-indirect-with-pre-increment-4-s1-indirect-with-index-4", "bset", 32,
14378 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14379 +  },
14380 +/* bset ${d-direct-addr},${s1-imm7-4}(${s1-An}),#${bit5} */
14381 +  {
14382 +    UBICOM32_INSN_BSET_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4, "bset-d-direct-s1-indirect-with-offset-4", "bset", 32,
14383 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14384 +  },
14385 +/* bset #${d-imm8},${s1-imm7-4}(${s1-An}),#${bit5} */
14386 +  {
14387 +    UBICOM32_INSN_BSET_D_IMMEDIATE_4_S1_INDIRECT_WITH_OFFSET_4, "bset-d-immediate-4-s1-indirect-with-offset-4", "bset", 32,
14388 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14389 +  },
14390 +/* bset (${d-An},${d-r}),${s1-imm7-4}(${s1-An}),#${bit5} */
14391 +  {
14392 +    UBICOM32_INSN_BSET_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_OFFSET_4, "bset-d-indirect-with-index-4-s1-indirect-with-offset-4", "bset", 32,
14393 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14394 +  },
14395 +/* bset ${d-imm7-4}(${d-An}),${s1-imm7-4}(${s1-An}),#${bit5} */
14396 +  {
14397 +    UBICOM32_INSN_BSET_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_OFFSET_4, "bset-d-indirect-with-offset-4-s1-indirect-with-offset-4", "bset", 32,
14398 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14399 +  },
14400 +/* bset (${d-An}),${s1-imm7-4}(${s1-An}),#${bit5} */
14401 +  {
14402 +    UBICOM32_INSN_BSET_D_INDIRECT_4_S1_INDIRECT_WITH_OFFSET_4, "bset-d-indirect-4-s1-indirect-with-offset-4", "bset", 32,
14403 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14404 +  },
14405 +/* bset (${d-An})${d-i4-4}++,${s1-imm7-4}(${s1-An}),#${bit5} */
14406 +  {
14407 +    UBICOM32_INSN_BSET_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, "bset-d-indirect-with-post-increment-4-s1-indirect-with-offset-4", "bset", 32,
14408 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14409 +  },
14410 +/* bset ${d-i4-4}(${d-An})++,${s1-imm7-4}(${s1-An}),#${bit5} */
14411 +  {
14412 +    UBICOM32_INSN_BSET_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, "bset-d-indirect-with-pre-increment-4-s1-indirect-with-offset-4", "bset", 32,
14413 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14414 +  },
14415 +/* bset ${d-direct-addr},(${s1-An}),#${bit5} */
14416 +  {
14417 +    UBICOM32_INSN_BSET_D_DIRECT_S1_INDIRECT_4, "bset-d-direct-s1-indirect-4", "bset", 32,
14418 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14419 +  },
14420 +/* bset #${d-imm8},(${s1-An}),#${bit5} */
14421 +  {
14422 +    UBICOM32_INSN_BSET_D_IMMEDIATE_4_S1_INDIRECT_4, "bset-d-immediate-4-s1-indirect-4", "bset", 32,
14423 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14424 +  },
14425 +/* bset (${d-An},${d-r}),(${s1-An}),#${bit5} */
14426 +  {
14427 +    UBICOM32_INSN_BSET_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_4, "bset-d-indirect-with-index-4-s1-indirect-4", "bset", 32,
14428 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14429 +  },
14430 +/* bset ${d-imm7-4}(${d-An}),(${s1-An}),#${bit5} */
14431 +  {
14432 +    UBICOM32_INSN_BSET_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_4, "bset-d-indirect-with-offset-4-s1-indirect-4", "bset", 32,
14433 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14434 +  },
14435 +/* bset (${d-An}),(${s1-An}),#${bit5} */
14436 +  {
14437 +    UBICOM32_INSN_BSET_D_INDIRECT_4_S1_INDIRECT_4, "bset-d-indirect-4-s1-indirect-4", "bset", 32,
14438 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14439 +  },
14440 +/* bset (${d-An})${d-i4-4}++,(${s1-An}),#${bit5} */
14441 +  {
14442 +    UBICOM32_INSN_BSET_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_4, "bset-d-indirect-with-post-increment-4-s1-indirect-4", "bset", 32,
14443 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14444 +  },
14445 +/* bset ${d-i4-4}(${d-An})++,(${s1-An}),#${bit5} */
14446 +  {
14447 +    UBICOM32_INSN_BSET_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_4, "bset-d-indirect-with-pre-increment-4-s1-indirect-4", "bset", 32,
14448 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14449 +  },
14450 +/* bset ${d-direct-addr},(${s1-An})${s1-i4-4}++,#${bit5} */
14451 +  {
14452 +    UBICOM32_INSN_BSET_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4, "bset-d-direct-s1-indirect-with-post-increment-4", "bset", 32,
14453 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14454 +  },
14455 +/* bset #${d-imm8},(${s1-An})${s1-i4-4}++,#${bit5} */
14456 +  {
14457 +    UBICOM32_INSN_BSET_D_IMMEDIATE_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "bset-d-immediate-4-s1-indirect-with-post-increment-4", "bset", 32,
14458 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14459 +  },
14460 +/* bset (${d-An},${d-r}),(${s1-An})${s1-i4-4}++,#${bit5} */
14461 +  {
14462 +    UBICOM32_INSN_BSET_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "bset-d-indirect-with-index-4-s1-indirect-with-post-increment-4", "bset", 32,
14463 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14464 +  },
14465 +/* bset ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-4}++,#${bit5} */
14466 +  {
14467 +    UBICOM32_INSN_BSET_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "bset-d-indirect-with-offset-4-s1-indirect-with-post-increment-4", "bset", 32,
14468 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14469 +  },
14470 +/* bset (${d-An}),(${s1-An})${s1-i4-4}++,#${bit5} */
14471 +  {
14472 +    UBICOM32_INSN_BSET_D_INDIRECT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "bset-d-indirect-4-s1-indirect-with-post-increment-4", "bset", 32,
14473 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14474 +  },
14475 +/* bset (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-4}++,#${bit5} */
14476 +  {
14477 +    UBICOM32_INSN_BSET_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "bset-d-indirect-with-post-increment-4-s1-indirect-with-post-increment-4", "bset", 32,
14478 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14479 +  },
14480 +/* bset ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-4}++,#${bit5} */
14481 +  {
14482 +    UBICOM32_INSN_BSET_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "bset-d-indirect-with-pre-increment-4-s1-indirect-with-post-increment-4", "bset", 32,
14483 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14484 +  },
14485 +/* bset ${d-direct-addr},${s1-i4-4}(${s1-An})++,#${bit5} */
14486 +  {
14487 +    UBICOM32_INSN_BSET_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4, "bset-d-direct-s1-indirect-with-pre-increment-4", "bset", 32,
14488 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14489 +  },
14490 +/* bset #${d-imm8},${s1-i4-4}(${s1-An})++,#${bit5} */
14491 +  {
14492 +    UBICOM32_INSN_BSET_D_IMMEDIATE_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "bset-d-immediate-4-s1-indirect-with-pre-increment-4", "bset", 32,
14493 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14494 +  },
14495 +/* bset (${d-An},${d-r}),${s1-i4-4}(${s1-An})++,#${bit5} */
14496 +  {
14497 +    UBICOM32_INSN_BSET_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "bset-d-indirect-with-index-4-s1-indirect-with-pre-increment-4", "bset", 32,
14498 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14499 +  },
14500 +/* bset ${d-imm7-4}(${d-An}),${s1-i4-4}(${s1-An})++,#${bit5} */
14501 +  {
14502 +    UBICOM32_INSN_BSET_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "bset-d-indirect-with-offset-4-s1-indirect-with-pre-increment-4", "bset", 32,
14503 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14504 +  },
14505 +/* bset (${d-An}),${s1-i4-4}(${s1-An})++,#${bit5} */
14506 +  {
14507 +    UBICOM32_INSN_BSET_D_INDIRECT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "bset-d-indirect-4-s1-indirect-with-pre-increment-4", "bset", 32,
14508 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14509 +  },
14510 +/* bset (${d-An})${d-i4-4}++,${s1-i4-4}(${s1-An})++,#${bit5} */
14511 +  {
14512 +    UBICOM32_INSN_BSET_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "bset-d-indirect-with-post-increment-4-s1-indirect-with-pre-increment-4", "bset", 32,
14513 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14514 +  },
14515 +/* bset ${d-i4-4}(${d-An})++,${s1-i4-4}(${s1-An})++,#${bit5} */
14516 +  {
14517 +    UBICOM32_INSN_BSET_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "bset-d-indirect-with-pre-increment-4-s1-indirect-with-pre-increment-4", "bset", 32,
14518 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14519 +  },
14520 +/* btst ${s1-direct-addr},#${bit5} */
14521 +  {
14522 +    UBICOM32_INSN_BTST_S1_DIRECT_IMM_BIT5, "btst-s1-direct-imm-bit5", "btst", 32,
14523 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14524 +  },
14525 +/* btst #${s1-imm8},#${bit5} */
14526 +  {
14527 +    UBICOM32_INSN_BTST_S1_IMMEDIATE_IMM_BIT5, "btst-s1-immediate-imm-bit5", "btst", 32,
14528 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14529 +  },
14530 +/* btst (${s1-An},${s1-r}),#${bit5} */
14531 +  {
14532 +    UBICOM32_INSN_BTST_S1_INDIRECT_WITH_INDEX_4_IMM_BIT5, "btst-s1-indirect-with-index-4-imm-bit5", "btst", 32,
14533 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14534 +  },
14535 +/* btst ${s1-imm7-4}(${s1-An}),#${bit5} */
14536 +  {
14537 +    UBICOM32_INSN_BTST_S1_INDIRECT_WITH_OFFSET_4_IMM_BIT5, "btst-s1-indirect-with-offset-4-imm-bit5", "btst", 32,
14538 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14539 +  },
14540 +/* btst (${s1-An}),#${bit5} */
14541 +  {
14542 +    UBICOM32_INSN_BTST_S1_INDIRECT_4_IMM_BIT5, "btst-s1-indirect-4-imm-bit5", "btst", 32,
14543 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14544 +  },
14545 +/* btst (${s1-An})${s1-i4-4}++,#${bit5} */
14546 +  {
14547 +    UBICOM32_INSN_BTST_S1_INDIRECT_WITH_POST_INCREMENT_4_IMM_BIT5, "btst-s1-indirect-with-post-increment-4-imm-bit5", "btst", 32,
14548 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14549 +  },
14550 +/* btst ${s1-i4-4}(${s1-An})++,#${bit5} */
14551 +  {
14552 +    UBICOM32_INSN_BTST_S1_INDIRECT_WITH_PRE_INCREMENT_4_IMM_BIT5, "btst-s1-indirect-with-pre-increment-4-imm-bit5", "btst", 32,
14553 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14554 +  },
14555 +/* btst ${s1-direct-addr},${s2} */
14556 +  {
14557 +    UBICOM32_INSN_BTST_S1_DIRECT_DYN_REG, "btst-s1-direct-dyn-reg", "btst", 32,
14558 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14559 +  },
14560 +/* btst #${s1-imm8},${s2} */
14561 +  {
14562 +    UBICOM32_INSN_BTST_S1_IMMEDIATE_DYN_REG, "btst-s1-immediate-dyn-reg", "btst", 32,
14563 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14564 +  },
14565 +/* btst (${s1-An},${s1-r}),${s2} */
14566 +  {
14567 +    UBICOM32_INSN_BTST_S1_INDIRECT_WITH_INDEX_4_DYN_REG, "btst-s1-indirect-with-index-4-dyn-reg", "btst", 32,
14568 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14569 +  },
14570 +/* btst ${s1-imm7-4}(${s1-An}),${s2} */
14571 +  {
14572 +    UBICOM32_INSN_BTST_S1_INDIRECT_WITH_OFFSET_4_DYN_REG, "btst-s1-indirect-with-offset-4-dyn-reg", "btst", 32,
14573 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14574 +  },
14575 +/* btst (${s1-An}),${s2} */
14576 +  {
14577 +    UBICOM32_INSN_BTST_S1_INDIRECT_4_DYN_REG, "btst-s1-indirect-4-dyn-reg", "btst", 32,
14578 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14579 +  },
14580 +/* btst (${s1-An})${s1-i4-4}++,${s2} */
14581 +  {
14582 +    UBICOM32_INSN_BTST_S1_INDIRECT_WITH_POST_INCREMENT_4_DYN_REG, "btst-s1-indirect-with-post-increment-4-dyn-reg", "btst", 32,
14583 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14584 +  },
14585 +/* btst ${s1-i4-4}(${s1-An})++,${s2} */
14586 +  {
14587 +    UBICOM32_INSN_BTST_S1_INDIRECT_WITH_PRE_INCREMENT_4_DYN_REG, "btst-s1-indirect-with-pre-increment-4-dyn-reg", "btst", 32,
14588 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14589 +  },
14590 +/* shmrg.2 ${Dn},${s1-direct-addr},#${bit5} */
14591 +  {
14592 +    UBICOM32_INSN_SHMRG_2_IMM_BIT5_S1_DIRECT, "shmrg.2-imm-bit5-s1-direct", "shmrg.2", 32,
14593 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14594 +  },
14595 +/* shmrg.2 ${Dn},${s1-direct-addr},${s2} */
14596 +  {
14597 +    UBICOM32_INSN_SHMRG_2_DYN_REG_S1_DIRECT, "shmrg.2-dyn-reg-s1-direct", "shmrg.2", 32,
14598 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14599 +  },
14600 +/* shmrg.2 ${Dn},#${s1-imm8},#${bit5} */
14601 +  {
14602 +    UBICOM32_INSN_SHMRG_2_IMM_BIT5_S1_IMMEDIATE, "shmrg.2-imm-bit5-s1-immediate", "shmrg.2", 32,
14603 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14604 +  },
14605 +/* shmrg.2 ${Dn},#${s1-imm8},${s2} */
14606 +  {
14607 +    UBICOM32_INSN_SHMRG_2_DYN_REG_S1_IMMEDIATE, "shmrg.2-dyn-reg-s1-immediate", "shmrg.2", 32,
14608 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14609 +  },
14610 +/* shmrg.2 ${Dn},(${s1-An},${s1-r}),#${bit5} */
14611 +  {
14612 +    UBICOM32_INSN_SHMRG_2_IMM_BIT5_S1_INDIRECT_WITH_INDEX_2, "shmrg.2-imm-bit5-s1-indirect-with-index-2", "shmrg.2", 32,
14613 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14614 +  },
14615 +/* shmrg.2 ${Dn},(${s1-An},${s1-r}),${s2} */
14616 +  {
14617 +    UBICOM32_INSN_SHMRG_2_DYN_REG_S1_INDIRECT_WITH_INDEX_2, "shmrg.2-dyn-reg-s1-indirect-with-index-2", "shmrg.2", 32,
14618 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14619 +  },
14620 +/* shmrg.2 ${Dn},${s1-imm7-2}(${s1-An}),#${bit5} */
14621 +  {
14622 +    UBICOM32_INSN_SHMRG_2_IMM_BIT5_S1_INDIRECT_WITH_OFFSET_2, "shmrg.2-imm-bit5-s1-indirect-with-offset-2", "shmrg.2", 32,
14623 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14624 +  },
14625 +/* shmrg.2 ${Dn},${s1-imm7-2}(${s1-An}),${s2} */
14626 +  {
14627 +    UBICOM32_INSN_SHMRG_2_DYN_REG_S1_INDIRECT_WITH_OFFSET_2, "shmrg.2-dyn-reg-s1-indirect-with-offset-2", "shmrg.2", 32,
14628 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14629 +  },
14630 +/* shmrg.2 ${Dn},(${s1-An}),#${bit5} */
14631 +  {
14632 +    UBICOM32_INSN_SHMRG_2_IMM_BIT5_S1_INDIRECT_2, "shmrg.2-imm-bit5-s1-indirect-2", "shmrg.2", 32,
14633 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14634 +  },
14635 +/* shmrg.2 ${Dn},(${s1-An}),${s2} */
14636 +  {
14637 +    UBICOM32_INSN_SHMRG_2_DYN_REG_S1_INDIRECT_2, "shmrg.2-dyn-reg-s1-indirect-2", "shmrg.2", 32,
14638 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14639 +  },
14640 +/* shmrg.2 ${Dn},(${s1-An})${s1-i4-2}++,#${bit5} */
14641 +  {
14642 +    UBICOM32_INSN_SHMRG_2_IMM_BIT5_S1_INDIRECT_WITH_POST_INCREMENT_2, "shmrg.2-imm-bit5-s1-indirect-with-post-increment-2", "shmrg.2", 32,
14643 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14644 +  },
14645 +/* shmrg.2 ${Dn},(${s1-An})${s1-i4-2}++,${s2} */
14646 +  {
14647 +    UBICOM32_INSN_SHMRG_2_DYN_REG_S1_INDIRECT_WITH_POST_INCREMENT_2, "shmrg.2-dyn-reg-s1-indirect-with-post-increment-2", "shmrg.2", 32,
14648 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14649 +  },
14650 +/* shmrg.2 ${Dn},${s1-i4-2}(${s1-An})++,#${bit5} */
14651 +  {
14652 +    UBICOM32_INSN_SHMRG_2_IMM_BIT5_S1_INDIRECT_WITH_PRE_INCREMENT_2, "shmrg.2-imm-bit5-s1-indirect-with-pre-increment-2", "shmrg.2", 32,
14653 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14654 +  },
14655 +/* shmrg.2 ${Dn},${s1-i4-2}(${s1-An})++,${s2} */
14656 +  {
14657 +    UBICOM32_INSN_SHMRG_2_DYN_REG_S1_INDIRECT_WITH_PRE_INCREMENT_2, "shmrg.2-dyn-reg-s1-indirect-with-pre-increment-2", "shmrg.2", 32,
14658 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14659 +  },
14660 +/* shmrg.1 ${Dn},${s1-direct-addr},#${bit5} */
14661 +  {
14662 +    UBICOM32_INSN_SHMRG_1_IMM_BIT5_S1_DIRECT, "shmrg.1-imm-bit5-s1-direct", "shmrg.1", 32,
14663 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14664 +  },
14665 +/* shmrg.1 ${Dn},${s1-direct-addr},${s2} */
14666 +  {
14667 +    UBICOM32_INSN_SHMRG_1_DYN_REG_S1_DIRECT, "shmrg.1-dyn-reg-s1-direct", "shmrg.1", 32,
14668 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14669 +  },
14670 +/* shmrg.1 ${Dn},#${s1-imm8},#${bit5} */
14671 +  {
14672 +    UBICOM32_INSN_SHMRG_1_IMM_BIT5_S1_IMMEDIATE, "shmrg.1-imm-bit5-s1-immediate", "shmrg.1", 32,
14673 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14674 +  },
14675 +/* shmrg.1 ${Dn},#${s1-imm8},${s2} */
14676 +  {
14677 +    UBICOM32_INSN_SHMRG_1_DYN_REG_S1_IMMEDIATE, "shmrg.1-dyn-reg-s1-immediate", "shmrg.1", 32,
14678 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14679 +  },
14680 +/* shmrg.1 ${Dn},(${s1-An},${s1-r}),#${bit5} */
14681 +  {
14682 +    UBICOM32_INSN_SHMRG_1_IMM_BIT5_S1_INDIRECT_WITH_INDEX_1, "shmrg.1-imm-bit5-s1-indirect-with-index-1", "shmrg.1", 32,
14683 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14684 +  },
14685 +/* shmrg.1 ${Dn},(${s1-An},${s1-r}),${s2} */
14686 +  {
14687 +    UBICOM32_INSN_SHMRG_1_DYN_REG_S1_INDIRECT_WITH_INDEX_1, "shmrg.1-dyn-reg-s1-indirect-with-index-1", "shmrg.1", 32,
14688 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14689 +  },
14690 +/* shmrg.1 ${Dn},${s1-imm7-1}(${s1-An}),#${bit5} */
14691 +  {
14692 +    UBICOM32_INSN_SHMRG_1_IMM_BIT5_S1_INDIRECT_WITH_OFFSET_1, "shmrg.1-imm-bit5-s1-indirect-with-offset-1", "shmrg.1", 32,
14693 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14694 +  },
14695 +/* shmrg.1 ${Dn},${s1-imm7-1}(${s1-An}),${s2} */
14696 +  {
14697 +    UBICOM32_INSN_SHMRG_1_DYN_REG_S1_INDIRECT_WITH_OFFSET_1, "shmrg.1-dyn-reg-s1-indirect-with-offset-1", "shmrg.1", 32,
14698 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14699 +  },
14700 +/* shmrg.1 ${Dn},(${s1-An}),#${bit5} */
14701 +  {
14702 +    UBICOM32_INSN_SHMRG_1_IMM_BIT5_S1_INDIRECT_1, "shmrg.1-imm-bit5-s1-indirect-1", "shmrg.1", 32,
14703 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14704 +  },
14705 +/* shmrg.1 ${Dn},(${s1-An}),${s2} */
14706 +  {
14707 +    UBICOM32_INSN_SHMRG_1_DYN_REG_S1_INDIRECT_1, "shmrg.1-dyn-reg-s1-indirect-1", "shmrg.1", 32,
14708 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14709 +  },
14710 +/* shmrg.1 ${Dn},(${s1-An})${s1-i4-1}++,#${bit5} */
14711 +  {
14712 +    UBICOM32_INSN_SHMRG_1_IMM_BIT5_S1_INDIRECT_WITH_POST_INCREMENT_1, "shmrg.1-imm-bit5-s1-indirect-with-post-increment-1", "shmrg.1", 32,
14713 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14714 +  },
14715 +/* shmrg.1 ${Dn},(${s1-An})${s1-i4-1}++,${s2} */
14716 +  {
14717 +    UBICOM32_INSN_SHMRG_1_DYN_REG_S1_INDIRECT_WITH_POST_INCREMENT_1, "shmrg.1-dyn-reg-s1-indirect-with-post-increment-1", "shmrg.1", 32,
14718 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14719 +  },
14720 +/* shmrg.1 ${Dn},${s1-i4-1}(${s1-An})++,#${bit5} */
14721 +  {
14722 +    UBICOM32_INSN_SHMRG_1_IMM_BIT5_S1_INDIRECT_WITH_PRE_INCREMENT_1, "shmrg.1-imm-bit5-s1-indirect-with-pre-increment-1", "shmrg.1", 32,
14723 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14724 +  },
14725 +/* shmrg.1 ${Dn},${s1-i4-1}(${s1-An})++,${s2} */
14726 +  {
14727 +    UBICOM32_INSN_SHMRG_1_DYN_REG_S1_INDIRECT_WITH_PRE_INCREMENT_1, "shmrg.1-dyn-reg-s1-indirect-with-pre-increment-1", "shmrg.1", 32,
14728 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14729 +  },
14730 +/* crcgen ${s1-direct-addr},#${bit5} */
14731 +  {
14732 +    UBICOM32_INSN_CRCGEN_S1_DIRECT_IMM_BIT5, "crcgen-s1-direct-imm-bit5", "crcgen", 32,
14733 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14734 +  },
14735 +/* crcgen #${s1-imm8},#${bit5} */
14736 +  {
14737 +    UBICOM32_INSN_CRCGEN_S1_IMMEDIATE_IMM_BIT5, "crcgen-s1-immediate-imm-bit5", "crcgen", 32,
14738 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14739 +  },
14740 +/* crcgen (${s1-An},${s1-r}),#${bit5} */
14741 +  {
14742 +    UBICOM32_INSN_CRCGEN_S1_INDIRECT_WITH_INDEX_1_IMM_BIT5, "crcgen-s1-indirect-with-index-1-imm-bit5", "crcgen", 32,
14743 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14744 +  },
14745 +/* crcgen ${s1-imm7-1}(${s1-An}),#${bit5} */
14746 +  {
14747 +    UBICOM32_INSN_CRCGEN_S1_INDIRECT_WITH_OFFSET_1_IMM_BIT5, "crcgen-s1-indirect-with-offset-1-imm-bit5", "crcgen", 32,
14748 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14749 +  },
14750 +/* crcgen (${s1-An}),#${bit5} */
14751 +  {
14752 +    UBICOM32_INSN_CRCGEN_S1_INDIRECT_1_IMM_BIT5, "crcgen-s1-indirect-1-imm-bit5", "crcgen", 32,
14753 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14754 +  },
14755 +/* crcgen (${s1-An})${s1-i4-1}++,#${bit5} */
14756 +  {
14757 +    UBICOM32_INSN_CRCGEN_S1_INDIRECT_WITH_POST_INCREMENT_1_IMM_BIT5, "crcgen-s1-indirect-with-post-increment-1-imm-bit5", "crcgen", 32,
14758 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14759 +  },
14760 +/* crcgen ${s1-i4-1}(${s1-An})++,#${bit5} */
14761 +  {
14762 +    UBICOM32_INSN_CRCGEN_S1_INDIRECT_WITH_PRE_INCREMENT_1_IMM_BIT5, "crcgen-s1-indirect-with-pre-increment-1-imm-bit5", "crcgen", 32,
14763 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14764 +  },
14765 +/* crcgen ${s1-direct-addr},${s2} */
14766 +  {
14767 +    UBICOM32_INSN_CRCGEN_S1_DIRECT_DYN_REG, "crcgen-s1-direct-dyn-reg", "crcgen", 32,
14768 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14769 +  },
14770 +/* crcgen #${s1-imm8},${s2} */
14771 +  {
14772 +    UBICOM32_INSN_CRCGEN_S1_IMMEDIATE_DYN_REG, "crcgen-s1-immediate-dyn-reg", "crcgen", 32,
14773 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14774 +  },
14775 +/* crcgen (${s1-An},${s1-r}),${s2} */
14776 +  {
14777 +    UBICOM32_INSN_CRCGEN_S1_INDIRECT_WITH_INDEX_1_DYN_REG, "crcgen-s1-indirect-with-index-1-dyn-reg", "crcgen", 32,
14778 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14779 +  },
14780 +/* crcgen ${s1-imm7-1}(${s1-An}),${s2} */
14781 +  {
14782 +    UBICOM32_INSN_CRCGEN_S1_INDIRECT_WITH_OFFSET_1_DYN_REG, "crcgen-s1-indirect-with-offset-1-dyn-reg", "crcgen", 32,
14783 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14784 +  },
14785 +/* crcgen (${s1-An}),${s2} */
14786 +  {
14787 +    UBICOM32_INSN_CRCGEN_S1_INDIRECT_1_DYN_REG, "crcgen-s1-indirect-1-dyn-reg", "crcgen", 32,
14788 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14789 +  },
14790 +/* crcgen (${s1-An})${s1-i4-1}++,${s2} */
14791 +  {
14792 +    UBICOM32_INSN_CRCGEN_S1_INDIRECT_WITH_POST_INCREMENT_1_DYN_REG, "crcgen-s1-indirect-with-post-increment-1-dyn-reg", "crcgen", 32,
14793 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14794 +  },
14795 +/* crcgen ${s1-i4-1}(${s1-An})++,${s2} */
14796 +  {
14797 +    UBICOM32_INSN_CRCGEN_S1_INDIRECT_WITH_PRE_INCREMENT_1_DYN_REG, "crcgen-s1-indirect-with-pre-increment-1-dyn-reg", "crcgen", 32,
14798 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14799 +  },
14800 +/* bfextu ${Dn},${s1-direct-addr},#${bit5} */
14801 +  {
14802 +    UBICOM32_INSN_BFEXTU_S1_DIRECT_IMM_BIT5, "bfextu-s1-direct-imm-bit5", "bfextu", 32,
14803 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14804 +  },
14805 +/* bfextu ${Dn},#${s1-imm8},#${bit5} */
14806 +  {
14807 +    UBICOM32_INSN_BFEXTU_S1_IMMEDIATE_IMM_BIT5, "bfextu-s1-immediate-imm-bit5", "bfextu", 32,
14808 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14809 +  },
14810 +/* bfextu ${Dn},(${s1-An},${s1-r}),#${bit5} */
14811 +  {
14812 +    UBICOM32_INSN_BFEXTU_S1_INDIRECT_WITH_INDEX_4_IMM_BIT5, "bfextu-s1-indirect-with-index-4-imm-bit5", "bfextu", 32,
14813 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14814 +  },
14815 +/* bfextu ${Dn},${s1-imm7-4}(${s1-An}),#${bit5} */
14816 +  {
14817 +    UBICOM32_INSN_BFEXTU_S1_INDIRECT_WITH_OFFSET_4_IMM_BIT5, "bfextu-s1-indirect-with-offset-4-imm-bit5", "bfextu", 32,
14818 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14819 +  },
14820 +/* bfextu ${Dn},(${s1-An}),#${bit5} */
14821 +  {
14822 +    UBICOM32_INSN_BFEXTU_S1_INDIRECT_4_IMM_BIT5, "bfextu-s1-indirect-4-imm-bit5", "bfextu", 32,
14823 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14824 +  },
14825 +/* bfextu ${Dn},(${s1-An})${s1-i4-4}++,#${bit5} */
14826 +  {
14827 +    UBICOM32_INSN_BFEXTU_S1_INDIRECT_WITH_POST_INCREMENT_4_IMM_BIT5, "bfextu-s1-indirect-with-post-increment-4-imm-bit5", "bfextu", 32,
14828 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14829 +  },
14830 +/* bfextu ${Dn},${s1-i4-4}(${s1-An})++,#${bit5} */
14831 +  {
14832 +    UBICOM32_INSN_BFEXTU_S1_INDIRECT_WITH_PRE_INCREMENT_4_IMM_BIT5, "bfextu-s1-indirect-with-pre-increment-4-imm-bit5", "bfextu", 32,
14833 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14834 +  },
14835 +/* bfextu ${Dn},${s1-direct-addr},${s2} */
14836 +  {
14837 +    UBICOM32_INSN_BFEXTU_S1_DIRECT_DYN_REG, "bfextu-s1-direct-dyn-reg", "bfextu", 32,
14838 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14839 +  },
14840 +/* bfextu ${Dn},#${s1-imm8},${s2} */
14841 +  {
14842 +    UBICOM32_INSN_BFEXTU_S1_IMMEDIATE_DYN_REG, "bfextu-s1-immediate-dyn-reg", "bfextu", 32,
14843 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14844 +  },
14845 +/* bfextu ${Dn},(${s1-An},${s1-r}),${s2} */
14846 +  {
14847 +    UBICOM32_INSN_BFEXTU_S1_INDIRECT_WITH_INDEX_4_DYN_REG, "bfextu-s1-indirect-with-index-4-dyn-reg", "bfextu", 32,
14848 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14849 +  },
14850 +/* bfextu ${Dn},${s1-imm7-4}(${s1-An}),${s2} */
14851 +  {
14852 +    UBICOM32_INSN_BFEXTU_S1_INDIRECT_WITH_OFFSET_4_DYN_REG, "bfextu-s1-indirect-with-offset-4-dyn-reg", "bfextu", 32,
14853 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14854 +  },
14855 +/* bfextu ${Dn},(${s1-An}),${s2} */
14856 +  {
14857 +    UBICOM32_INSN_BFEXTU_S1_INDIRECT_4_DYN_REG, "bfextu-s1-indirect-4-dyn-reg", "bfextu", 32,
14858 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14859 +  },
14860 +/* bfextu ${Dn},(${s1-An})${s1-i4-4}++,${s2} */
14861 +  {
14862 +    UBICOM32_INSN_BFEXTU_S1_INDIRECT_WITH_POST_INCREMENT_4_DYN_REG, "bfextu-s1-indirect-with-post-increment-4-dyn-reg", "bfextu", 32,
14863 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14864 +  },
14865 +/* bfextu ${Dn},${s1-i4-4}(${s1-An})++,${s2} */
14866 +  {
14867 +    UBICOM32_INSN_BFEXTU_S1_INDIRECT_WITH_PRE_INCREMENT_4_DYN_REG, "bfextu-s1-indirect-with-pre-increment-4-dyn-reg", "bfextu", 32,
14868 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14869 +  },
14870 +/* bfrvrs ${Dn},${s1-direct-addr},#${bit5} */
14871 +  {
14872 +    UBICOM32_INSN_BFRVRS_S1_DIRECT_IMM_BIT5, "bfrvrs-s1-direct-imm-bit5", "bfrvrs", 32,
14873 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14874 +  },
14875 +/* bfrvrs ${Dn},#${s1-imm8},#${bit5} */
14876 +  {
14877 +    UBICOM32_INSN_BFRVRS_S1_IMMEDIATE_IMM_BIT5, "bfrvrs-s1-immediate-imm-bit5", "bfrvrs", 32,
14878 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14879 +  },
14880 +/* bfrvrs ${Dn},(${s1-An},${s1-r}),#${bit5} */
14881 +  {
14882 +    UBICOM32_INSN_BFRVRS_S1_INDIRECT_WITH_INDEX_4_IMM_BIT5, "bfrvrs-s1-indirect-with-index-4-imm-bit5", "bfrvrs", 32,
14883 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14884 +  },
14885 +/* bfrvrs ${Dn},${s1-imm7-4}(${s1-An}),#${bit5} */
14886 +  {
14887 +    UBICOM32_INSN_BFRVRS_S1_INDIRECT_WITH_OFFSET_4_IMM_BIT5, "bfrvrs-s1-indirect-with-offset-4-imm-bit5", "bfrvrs", 32,
14888 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14889 +  },
14890 +/* bfrvrs ${Dn},(${s1-An}),#${bit5} */
14891 +  {
14892 +    UBICOM32_INSN_BFRVRS_S1_INDIRECT_4_IMM_BIT5, "bfrvrs-s1-indirect-4-imm-bit5", "bfrvrs", 32,
14893 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14894 +  },
14895 +/* bfrvrs ${Dn},(${s1-An})${s1-i4-4}++,#${bit5} */
14896 +  {
14897 +    UBICOM32_INSN_BFRVRS_S1_INDIRECT_WITH_POST_INCREMENT_4_IMM_BIT5, "bfrvrs-s1-indirect-with-post-increment-4-imm-bit5", "bfrvrs", 32,
14898 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14899 +  },
14900 +/* bfrvrs ${Dn},${s1-i4-4}(${s1-An})++,#${bit5} */
14901 +  {
14902 +    UBICOM32_INSN_BFRVRS_S1_INDIRECT_WITH_PRE_INCREMENT_4_IMM_BIT5, "bfrvrs-s1-indirect-with-pre-increment-4-imm-bit5", "bfrvrs", 32,
14903 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14904 +  },
14905 +/* bfrvrs ${Dn},${s1-direct-addr},${s2} */
14906 +  {
14907 +    UBICOM32_INSN_BFRVRS_S1_DIRECT_DYN_REG, "bfrvrs-s1-direct-dyn-reg", "bfrvrs", 32,
14908 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14909 +  },
14910 +/* bfrvrs ${Dn},#${s1-imm8},${s2} */
14911 +  {
14912 +    UBICOM32_INSN_BFRVRS_S1_IMMEDIATE_DYN_REG, "bfrvrs-s1-immediate-dyn-reg", "bfrvrs", 32,
14913 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14914 +  },
14915 +/* bfrvrs ${Dn},(${s1-An},${s1-r}),${s2} */
14916 +  {
14917 +    UBICOM32_INSN_BFRVRS_S1_INDIRECT_WITH_INDEX_4_DYN_REG, "bfrvrs-s1-indirect-with-index-4-dyn-reg", "bfrvrs", 32,
14918 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14919 +  },
14920 +/* bfrvrs ${Dn},${s1-imm7-4}(${s1-An}),${s2} */
14921 +  {
14922 +    UBICOM32_INSN_BFRVRS_S1_INDIRECT_WITH_OFFSET_4_DYN_REG, "bfrvrs-s1-indirect-with-offset-4-dyn-reg", "bfrvrs", 32,
14923 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14924 +  },
14925 +/* bfrvrs ${Dn},(${s1-An}),${s2} */
14926 +  {
14927 +    UBICOM32_INSN_BFRVRS_S1_INDIRECT_4_DYN_REG, "bfrvrs-s1-indirect-4-dyn-reg", "bfrvrs", 32,
14928 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14929 +  },
14930 +/* bfrvrs ${Dn},(${s1-An})${s1-i4-4}++,${s2} */
14931 +  {
14932 +    UBICOM32_INSN_BFRVRS_S1_INDIRECT_WITH_POST_INCREMENT_4_DYN_REG, "bfrvrs-s1-indirect-with-post-increment-4-dyn-reg", "bfrvrs", 32,
14933 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14934 +  },
14935 +/* bfrvrs ${Dn},${s1-i4-4}(${s1-An})++,${s2} */
14936 +  {
14937 +    UBICOM32_INSN_BFRVRS_S1_INDIRECT_WITH_PRE_INCREMENT_4_DYN_REG, "bfrvrs-s1-indirect-with-pre-increment-4-dyn-reg", "bfrvrs", 32,
14938 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14939 +  },
14940 +/* merge ${Dn},${s1-direct-addr},#${bit5} */
14941 +  {
14942 +    UBICOM32_INSN_MERGE_S1_DIRECT_IMM_BIT5, "merge-s1-direct-imm-bit5", "merge", 32,
14943 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14944 +  },
14945 +/* merge ${Dn},#${s1-imm8},#${bit5} */
14946 +  {
14947 +    UBICOM32_INSN_MERGE_S1_IMMEDIATE_IMM_BIT5, "merge-s1-immediate-imm-bit5", "merge", 32,
14948 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14949 +  },
14950 +/* merge ${Dn},(${s1-An},${s1-r}),#${bit5} */
14951 +  {
14952 +    UBICOM32_INSN_MERGE_S1_INDIRECT_WITH_INDEX_4_IMM_BIT5, "merge-s1-indirect-with-index-4-imm-bit5", "merge", 32,
14953 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14954 +  },
14955 +/* merge ${Dn},${s1-imm7-4}(${s1-An}),#${bit5} */
14956 +  {
14957 +    UBICOM32_INSN_MERGE_S1_INDIRECT_WITH_OFFSET_4_IMM_BIT5, "merge-s1-indirect-with-offset-4-imm-bit5", "merge", 32,
14958 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14959 +  },
14960 +/* merge ${Dn},(${s1-An}),#${bit5} */
14961 +  {
14962 +    UBICOM32_INSN_MERGE_S1_INDIRECT_4_IMM_BIT5, "merge-s1-indirect-4-imm-bit5", "merge", 32,
14963 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14964 +  },
14965 +/* merge ${Dn},(${s1-An})${s1-i4-4}++,#${bit5} */
14966 +  {
14967 +    UBICOM32_INSN_MERGE_S1_INDIRECT_WITH_POST_INCREMENT_4_IMM_BIT5, "merge-s1-indirect-with-post-increment-4-imm-bit5", "merge", 32,
14968 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14969 +  },
14970 +/* merge ${Dn},${s1-i4-4}(${s1-An})++,#${bit5} */
14971 +  {
14972 +    UBICOM32_INSN_MERGE_S1_INDIRECT_WITH_PRE_INCREMENT_4_IMM_BIT5, "merge-s1-indirect-with-pre-increment-4-imm-bit5", "merge", 32,
14973 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14974 +  },
14975 +/* merge ${Dn},${s1-direct-addr},${s2} */
14976 +  {
14977 +    UBICOM32_INSN_MERGE_S1_DIRECT_DYN_REG, "merge-s1-direct-dyn-reg", "merge", 32,
14978 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14979 +  },
14980 +/* merge ${Dn},#${s1-imm8},${s2} */
14981 +  {
14982 +    UBICOM32_INSN_MERGE_S1_IMMEDIATE_DYN_REG, "merge-s1-immediate-dyn-reg", "merge", 32,
14983 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14984 +  },
14985 +/* merge ${Dn},(${s1-An},${s1-r}),${s2} */
14986 +  {
14987 +    UBICOM32_INSN_MERGE_S1_INDIRECT_WITH_INDEX_4_DYN_REG, "merge-s1-indirect-with-index-4-dyn-reg", "merge", 32,
14988 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14989 +  },
14990 +/* merge ${Dn},${s1-imm7-4}(${s1-An}),${s2} */
14991 +  {
14992 +    UBICOM32_INSN_MERGE_S1_INDIRECT_WITH_OFFSET_4_DYN_REG, "merge-s1-indirect-with-offset-4-dyn-reg", "merge", 32,
14993 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14994 +  },
14995 +/* merge ${Dn},(${s1-An}),${s2} */
14996 +  {
14997 +    UBICOM32_INSN_MERGE_S1_INDIRECT_4_DYN_REG, "merge-s1-indirect-4-dyn-reg", "merge", 32,
14998 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
14999 +  },
15000 +/* merge ${Dn},(${s1-An})${s1-i4-4}++,${s2} */
15001 +  {
15002 +    UBICOM32_INSN_MERGE_S1_INDIRECT_WITH_POST_INCREMENT_4_DYN_REG, "merge-s1-indirect-with-post-increment-4-dyn-reg", "merge", 32,
15003 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15004 +  },
15005 +/* merge ${Dn},${s1-i4-4}(${s1-An})++,${s2} */
15006 +  {
15007 +    UBICOM32_INSN_MERGE_S1_INDIRECT_WITH_PRE_INCREMENT_4_DYN_REG, "merge-s1-indirect-with-pre-increment-4-dyn-reg", "merge", 32,
15008 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15009 +  },
15010 +/* shftd ${Dn},${s1-direct-addr},#${bit5} */
15011 +  {
15012 +    UBICOM32_INSN_SHFTD_S1_DIRECT_IMM_BIT5, "shftd-s1-direct-imm-bit5", "shftd", 32,
15013 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15014 +  },
15015 +/* shftd ${Dn},#${s1-imm8},#${bit5} */
15016 +  {
15017 +    UBICOM32_INSN_SHFTD_S1_IMMEDIATE_IMM_BIT5, "shftd-s1-immediate-imm-bit5", "shftd", 32,
15018 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15019 +  },
15020 +/* shftd ${Dn},(${s1-An},${s1-r}),#${bit5} */
15021 +  {
15022 +    UBICOM32_INSN_SHFTD_S1_INDIRECT_WITH_INDEX_4_IMM_BIT5, "shftd-s1-indirect-with-index-4-imm-bit5", "shftd", 32,
15023 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15024 +  },
15025 +/* shftd ${Dn},${s1-imm7-4}(${s1-An}),#${bit5} */
15026 +  {
15027 +    UBICOM32_INSN_SHFTD_S1_INDIRECT_WITH_OFFSET_4_IMM_BIT5, "shftd-s1-indirect-with-offset-4-imm-bit5", "shftd", 32,
15028 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15029 +  },
15030 +/* shftd ${Dn},(${s1-An}),#${bit5} */
15031 +  {
15032 +    UBICOM32_INSN_SHFTD_S1_INDIRECT_4_IMM_BIT5, "shftd-s1-indirect-4-imm-bit5", "shftd", 32,
15033 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15034 +  },
15035 +/* shftd ${Dn},(${s1-An})${s1-i4-4}++,#${bit5} */
15036 +  {
15037 +    UBICOM32_INSN_SHFTD_S1_INDIRECT_WITH_POST_INCREMENT_4_IMM_BIT5, "shftd-s1-indirect-with-post-increment-4-imm-bit5", "shftd", 32,
15038 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15039 +  },
15040 +/* shftd ${Dn},${s1-i4-4}(${s1-An})++,#${bit5} */
15041 +  {
15042 +    UBICOM32_INSN_SHFTD_S1_INDIRECT_WITH_PRE_INCREMENT_4_IMM_BIT5, "shftd-s1-indirect-with-pre-increment-4-imm-bit5", "shftd", 32,
15043 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15044 +  },
15045 +/* shftd ${Dn},${s1-direct-addr},${s2} */
15046 +  {
15047 +    UBICOM32_INSN_SHFTD_S1_DIRECT_DYN_REG, "shftd-s1-direct-dyn-reg", "shftd", 32,
15048 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15049 +  },
15050 +/* shftd ${Dn},#${s1-imm8},${s2} */
15051 +  {
15052 +    UBICOM32_INSN_SHFTD_S1_IMMEDIATE_DYN_REG, "shftd-s1-immediate-dyn-reg", "shftd", 32,
15053 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15054 +  },
15055 +/* shftd ${Dn},(${s1-An},${s1-r}),${s2} */
15056 +  {
15057 +    UBICOM32_INSN_SHFTD_S1_INDIRECT_WITH_INDEX_4_DYN_REG, "shftd-s1-indirect-with-index-4-dyn-reg", "shftd", 32,
15058 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15059 +  },
15060 +/* shftd ${Dn},${s1-imm7-4}(${s1-An}),${s2} */
15061 +  {
15062 +    UBICOM32_INSN_SHFTD_S1_INDIRECT_WITH_OFFSET_4_DYN_REG, "shftd-s1-indirect-with-offset-4-dyn-reg", "shftd", 32,
15063 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15064 +  },
15065 +/* shftd ${Dn},(${s1-An}),${s2} */
15066 +  {
15067 +    UBICOM32_INSN_SHFTD_S1_INDIRECT_4_DYN_REG, "shftd-s1-indirect-4-dyn-reg", "shftd", 32,
15068 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15069 +  },
15070 +/* shftd ${Dn},(${s1-An})${s1-i4-4}++,${s2} */
15071 +  {
15072 +    UBICOM32_INSN_SHFTD_S1_INDIRECT_WITH_POST_INCREMENT_4_DYN_REG, "shftd-s1-indirect-with-post-increment-4-dyn-reg", "shftd", 32,
15073 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15074 +  },
15075 +/* shftd ${Dn},${s1-i4-4}(${s1-An})++,${s2} */
15076 +  {
15077 +    UBICOM32_INSN_SHFTD_S1_INDIRECT_WITH_PRE_INCREMENT_4_DYN_REG, "shftd-s1-indirect-with-pre-increment-4-dyn-reg", "shftd", 32,
15078 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15079 +  },
15080 +/* asr.1 ${Dn},${s1-direct-addr},#${bit5} */
15081 +  {
15082 +    UBICOM32_INSN_ASR_1_IMM_BIT5_S1_DIRECT, "asr.1-imm-bit5-s1-direct", "asr.1", 32,
15083 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
15084 +  },
15085 +/* asr.1 ${Dn},${s1-direct-addr},${s2} */
15086 +  {
15087 +    UBICOM32_INSN_ASR_1_DYN_REG_S1_DIRECT, "asr.1-dyn-reg-s1-direct", "asr.1", 32,
15088 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
15089 +  },
15090 +/* asr.1 ${Dn},#${s1-imm8},#${bit5} */
15091 +  {
15092 +    UBICOM32_INSN_ASR_1_IMM_BIT5_S1_IMMEDIATE, "asr.1-imm-bit5-s1-immediate", "asr.1", 32,
15093 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
15094 +  },
15095 +/* asr.1 ${Dn},#${s1-imm8},${s2} */
15096 +  {
15097 +    UBICOM32_INSN_ASR_1_DYN_REG_S1_IMMEDIATE, "asr.1-dyn-reg-s1-immediate", "asr.1", 32,
15098 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
15099 +  },
15100 +/* asr.1 ${Dn},(${s1-An},${s1-r}),#${bit5} */
15101 +  {
15102 +    UBICOM32_INSN_ASR_1_IMM_BIT5_S1_INDIRECT_WITH_INDEX_1, "asr.1-imm-bit5-s1-indirect-with-index-1", "asr.1", 32,
15103 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
15104 +  },
15105 +/* asr.1 ${Dn},(${s1-An},${s1-r}),${s2} */
15106 +  {
15107 +    UBICOM32_INSN_ASR_1_DYN_REG_S1_INDIRECT_WITH_INDEX_1, "asr.1-dyn-reg-s1-indirect-with-index-1", "asr.1", 32,
15108 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
15109 +  },
15110 +/* asr.1 ${Dn},${s1-imm7-1}(${s1-An}),#${bit5} */
15111 +  {
15112 +    UBICOM32_INSN_ASR_1_IMM_BIT5_S1_INDIRECT_WITH_OFFSET_1, "asr.1-imm-bit5-s1-indirect-with-offset-1", "asr.1", 32,
15113 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
15114 +  },
15115 +/* asr.1 ${Dn},${s1-imm7-1}(${s1-An}),${s2} */
15116 +  {
15117 +    UBICOM32_INSN_ASR_1_DYN_REG_S1_INDIRECT_WITH_OFFSET_1, "asr.1-dyn-reg-s1-indirect-with-offset-1", "asr.1", 32,
15118 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
15119 +  },
15120 +/* asr.1 ${Dn},(${s1-An}),#${bit5} */
15121 +  {
15122 +    UBICOM32_INSN_ASR_1_IMM_BIT5_S1_INDIRECT_1, "asr.1-imm-bit5-s1-indirect-1", "asr.1", 32,
15123 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
15124 +  },
15125 +/* asr.1 ${Dn},(${s1-An}),${s2} */
15126 +  {
15127 +    UBICOM32_INSN_ASR_1_DYN_REG_S1_INDIRECT_1, "asr.1-dyn-reg-s1-indirect-1", "asr.1", 32,
15128 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
15129 +  },
15130 +/* asr.1 ${Dn},(${s1-An})${s1-i4-1}++,#${bit5} */
15131 +  {
15132 +    UBICOM32_INSN_ASR_1_IMM_BIT5_S1_INDIRECT_WITH_POST_INCREMENT_1, "asr.1-imm-bit5-s1-indirect-with-post-increment-1", "asr.1", 32,
15133 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
15134 +  },
15135 +/* asr.1 ${Dn},(${s1-An})${s1-i4-1}++,${s2} */
15136 +  {
15137 +    UBICOM32_INSN_ASR_1_DYN_REG_S1_INDIRECT_WITH_POST_INCREMENT_1, "asr.1-dyn-reg-s1-indirect-with-post-increment-1", "asr.1", 32,
15138 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
15139 +  },
15140 +/* asr.1 ${Dn},${s1-i4-1}(${s1-An})++,#${bit5} */
15141 +  {
15142 +    UBICOM32_INSN_ASR_1_IMM_BIT5_S1_INDIRECT_WITH_PRE_INCREMENT_1, "asr.1-imm-bit5-s1-indirect-with-pre-increment-1", "asr.1", 32,
15143 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
15144 +  },
15145 +/* asr.1 ${Dn},${s1-i4-1}(${s1-An})++,${s2} */
15146 +  {
15147 +    UBICOM32_INSN_ASR_1_DYN_REG_S1_INDIRECT_WITH_PRE_INCREMENT_1, "asr.1-dyn-reg-s1-indirect-with-pre-increment-1", "asr.1", 32,
15148 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
15149 +  },
15150 +/* lsl.1 ${Dn},${s1-direct-addr},#${bit5} */
15151 +  {
15152 +    UBICOM32_INSN_LSL_1_IMM_BIT5_S1_DIRECT, "lsl.1-imm-bit5-s1-direct", "lsl.1", 32,
15153 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
15154 +  },
15155 +/* lsl.1 ${Dn},${s1-direct-addr},${s2} */
15156 +  {
15157 +    UBICOM32_INSN_LSL_1_DYN_REG_S1_DIRECT, "lsl.1-dyn-reg-s1-direct", "lsl.1", 32,
15158 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
15159 +  },
15160 +/* lsl.1 ${Dn},#${s1-imm8},#${bit5} */
15161 +  {
15162 +    UBICOM32_INSN_LSL_1_IMM_BIT5_S1_IMMEDIATE, "lsl.1-imm-bit5-s1-immediate", "lsl.1", 32,
15163 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
15164 +  },
15165 +/* lsl.1 ${Dn},#${s1-imm8},${s2} */
15166 +  {
15167 +    UBICOM32_INSN_LSL_1_DYN_REG_S1_IMMEDIATE, "lsl.1-dyn-reg-s1-immediate", "lsl.1", 32,
15168 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
15169 +  },
15170 +/* lsl.1 ${Dn},(${s1-An},${s1-r}),#${bit5} */
15171 +  {
15172 +    UBICOM32_INSN_LSL_1_IMM_BIT5_S1_INDIRECT_WITH_INDEX_1, "lsl.1-imm-bit5-s1-indirect-with-index-1", "lsl.1", 32,
15173 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
15174 +  },
15175 +/* lsl.1 ${Dn},(${s1-An},${s1-r}),${s2} */
15176 +  {
15177 +    UBICOM32_INSN_LSL_1_DYN_REG_S1_INDIRECT_WITH_INDEX_1, "lsl.1-dyn-reg-s1-indirect-with-index-1", "lsl.1", 32,
15178 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
15179 +  },
15180 +/* lsl.1 ${Dn},${s1-imm7-1}(${s1-An}),#${bit5} */
15181 +  {
15182 +    UBICOM32_INSN_LSL_1_IMM_BIT5_S1_INDIRECT_WITH_OFFSET_1, "lsl.1-imm-bit5-s1-indirect-with-offset-1", "lsl.1", 32,
15183 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
15184 +  },
15185 +/* lsl.1 ${Dn},${s1-imm7-1}(${s1-An}),${s2} */
15186 +  {
15187 +    UBICOM32_INSN_LSL_1_DYN_REG_S1_INDIRECT_WITH_OFFSET_1, "lsl.1-dyn-reg-s1-indirect-with-offset-1", "lsl.1", 32,
15188 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
15189 +  },
15190 +/* lsl.1 ${Dn},(${s1-An}),#${bit5} */
15191 +  {
15192 +    UBICOM32_INSN_LSL_1_IMM_BIT5_S1_INDIRECT_1, "lsl.1-imm-bit5-s1-indirect-1", "lsl.1", 32,
15193 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
15194 +  },
15195 +/* lsl.1 ${Dn},(${s1-An}),${s2} */
15196 +  {
15197 +    UBICOM32_INSN_LSL_1_DYN_REG_S1_INDIRECT_1, "lsl.1-dyn-reg-s1-indirect-1", "lsl.1", 32,
15198 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
15199 +  },
15200 +/* lsl.1 ${Dn},(${s1-An})${s1-i4-1}++,#${bit5} */
15201 +  {
15202 +    UBICOM32_INSN_LSL_1_IMM_BIT5_S1_INDIRECT_WITH_POST_INCREMENT_1, "lsl.1-imm-bit5-s1-indirect-with-post-increment-1", "lsl.1", 32,
15203 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
15204 +  },
15205 +/* lsl.1 ${Dn},(${s1-An})${s1-i4-1}++,${s2} */
15206 +  {
15207 +    UBICOM32_INSN_LSL_1_DYN_REG_S1_INDIRECT_WITH_POST_INCREMENT_1, "lsl.1-dyn-reg-s1-indirect-with-post-increment-1", "lsl.1", 32,
15208 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
15209 +  },
15210 +/* lsl.1 ${Dn},${s1-i4-1}(${s1-An})++,#${bit5} */
15211 +  {
15212 +    UBICOM32_INSN_LSL_1_IMM_BIT5_S1_INDIRECT_WITH_PRE_INCREMENT_1, "lsl.1-imm-bit5-s1-indirect-with-pre-increment-1", "lsl.1", 32,
15213 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
15214 +  },
15215 +/* lsl.1 ${Dn},${s1-i4-1}(${s1-An})++,${s2} */
15216 +  {
15217 +    UBICOM32_INSN_LSL_1_DYN_REG_S1_INDIRECT_WITH_PRE_INCREMENT_1, "lsl.1-dyn-reg-s1-indirect-with-pre-increment-1", "lsl.1", 32,
15218 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
15219 +  },
15220 +/* lsr.1 ${Dn},${s1-direct-addr},#${bit5} */
15221 +  {
15222 +    UBICOM32_INSN_LSR_1_IMM_BIT5_S1_DIRECT, "lsr.1-imm-bit5-s1-direct", "lsr.1", 32,
15223 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
15224 +  },
15225 +/* lsr.1 ${Dn},${s1-direct-addr},${s2} */
15226 +  {
15227 +    UBICOM32_INSN_LSR_1_DYN_REG_S1_DIRECT, "lsr.1-dyn-reg-s1-direct", "lsr.1", 32,
15228 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
15229 +  },
15230 +/* lsr.1 ${Dn},#${s1-imm8},#${bit5} */
15231 +  {
15232 +    UBICOM32_INSN_LSR_1_IMM_BIT5_S1_IMMEDIATE, "lsr.1-imm-bit5-s1-immediate", "lsr.1", 32,
15233 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
15234 +  },
15235 +/* lsr.1 ${Dn},#${s1-imm8},${s2} */
15236 +  {
15237 +    UBICOM32_INSN_LSR_1_DYN_REG_S1_IMMEDIATE, "lsr.1-dyn-reg-s1-immediate", "lsr.1", 32,
15238 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
15239 +  },
15240 +/* lsr.1 ${Dn},(${s1-An},${s1-r}),#${bit5} */
15241 +  {
15242 +    UBICOM32_INSN_LSR_1_IMM_BIT5_S1_INDIRECT_WITH_INDEX_1, "lsr.1-imm-bit5-s1-indirect-with-index-1", "lsr.1", 32,
15243 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
15244 +  },
15245 +/* lsr.1 ${Dn},(${s1-An},${s1-r}),${s2} */
15246 +  {
15247 +    UBICOM32_INSN_LSR_1_DYN_REG_S1_INDIRECT_WITH_INDEX_1, "lsr.1-dyn-reg-s1-indirect-with-index-1", "lsr.1", 32,
15248 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
15249 +  },
15250 +/* lsr.1 ${Dn},${s1-imm7-1}(${s1-An}),#${bit5} */
15251 +  {
15252 +    UBICOM32_INSN_LSR_1_IMM_BIT5_S1_INDIRECT_WITH_OFFSET_1, "lsr.1-imm-bit5-s1-indirect-with-offset-1", "lsr.1", 32,
15253 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
15254 +  },
15255 +/* lsr.1 ${Dn},${s1-imm7-1}(${s1-An}),${s2} */
15256 +  {
15257 +    UBICOM32_INSN_LSR_1_DYN_REG_S1_INDIRECT_WITH_OFFSET_1, "lsr.1-dyn-reg-s1-indirect-with-offset-1", "lsr.1", 32,
15258 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
15259 +  },
15260 +/* lsr.1 ${Dn},(${s1-An}),#${bit5} */
15261 +  {
15262 +    UBICOM32_INSN_LSR_1_IMM_BIT5_S1_INDIRECT_1, "lsr.1-imm-bit5-s1-indirect-1", "lsr.1", 32,
15263 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
15264 +  },
15265 +/* lsr.1 ${Dn},(${s1-An}),${s2} */
15266 +  {
15267 +    UBICOM32_INSN_LSR_1_DYN_REG_S1_INDIRECT_1, "lsr.1-dyn-reg-s1-indirect-1", "lsr.1", 32,
15268 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
15269 +  },
15270 +/* lsr.1 ${Dn},(${s1-An})${s1-i4-1}++,#${bit5} */
15271 +  {
15272 +    UBICOM32_INSN_LSR_1_IMM_BIT5_S1_INDIRECT_WITH_POST_INCREMENT_1, "lsr.1-imm-bit5-s1-indirect-with-post-increment-1", "lsr.1", 32,
15273 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
15274 +  },
15275 +/* lsr.1 ${Dn},(${s1-An})${s1-i4-1}++,${s2} */
15276 +  {
15277 +    UBICOM32_INSN_LSR_1_DYN_REG_S1_INDIRECT_WITH_POST_INCREMENT_1, "lsr.1-dyn-reg-s1-indirect-with-post-increment-1", "lsr.1", 32,
15278 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
15279 +  },
15280 +/* lsr.1 ${Dn},${s1-i4-1}(${s1-An})++,#${bit5} */
15281 +  {
15282 +    UBICOM32_INSN_LSR_1_IMM_BIT5_S1_INDIRECT_WITH_PRE_INCREMENT_1, "lsr.1-imm-bit5-s1-indirect-with-pre-increment-1", "lsr.1", 32,
15283 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
15284 +  },
15285 +/* lsr.1 ${Dn},${s1-i4-1}(${s1-An})++,${s2} */
15286 +  {
15287 +    UBICOM32_INSN_LSR_1_DYN_REG_S1_INDIRECT_WITH_PRE_INCREMENT_1, "lsr.1-dyn-reg-s1-indirect-with-pre-increment-1", "lsr.1", 32,
15288 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
15289 +  },
15290 +/* asr.2 ${Dn},${s1-direct-addr},#${bit5} */
15291 +  {
15292 +    UBICOM32_INSN_ASR_2_IMM_BIT5_S1_DIRECT, "asr.2-imm-bit5-s1-direct", "asr.2", 32,
15293 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15294 +  },
15295 +/* asr.2 ${Dn},${s1-direct-addr},${s2} */
15296 +  {
15297 +    UBICOM32_INSN_ASR_2_DYN_REG_S1_DIRECT, "asr.2-dyn-reg-s1-direct", "asr.2", 32,
15298 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15299 +  },
15300 +/* asr.2 ${Dn},#${s1-imm8},#${bit5} */
15301 +  {
15302 +    UBICOM32_INSN_ASR_2_IMM_BIT5_S1_IMMEDIATE, "asr.2-imm-bit5-s1-immediate", "asr.2", 32,
15303 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15304 +  },
15305 +/* asr.2 ${Dn},#${s1-imm8},${s2} */
15306 +  {
15307 +    UBICOM32_INSN_ASR_2_DYN_REG_S1_IMMEDIATE, "asr.2-dyn-reg-s1-immediate", "asr.2", 32,
15308 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15309 +  },
15310 +/* asr.2 ${Dn},(${s1-An},${s1-r}),#${bit5} */
15311 +  {
15312 +    UBICOM32_INSN_ASR_2_IMM_BIT5_S1_INDIRECT_WITH_INDEX_2, "asr.2-imm-bit5-s1-indirect-with-index-2", "asr.2", 32,
15313 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15314 +  },
15315 +/* asr.2 ${Dn},(${s1-An},${s1-r}),${s2} */
15316 +  {
15317 +    UBICOM32_INSN_ASR_2_DYN_REG_S1_INDIRECT_WITH_INDEX_2, "asr.2-dyn-reg-s1-indirect-with-index-2", "asr.2", 32,
15318 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15319 +  },
15320 +/* asr.2 ${Dn},${s1-imm7-2}(${s1-An}),#${bit5} */
15321 +  {
15322 +    UBICOM32_INSN_ASR_2_IMM_BIT5_S1_INDIRECT_WITH_OFFSET_2, "asr.2-imm-bit5-s1-indirect-with-offset-2", "asr.2", 32,
15323 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15324 +  },
15325 +/* asr.2 ${Dn},${s1-imm7-2}(${s1-An}),${s2} */
15326 +  {
15327 +    UBICOM32_INSN_ASR_2_DYN_REG_S1_INDIRECT_WITH_OFFSET_2, "asr.2-dyn-reg-s1-indirect-with-offset-2", "asr.2", 32,
15328 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15329 +  },
15330 +/* asr.2 ${Dn},(${s1-An}),#${bit5} */
15331 +  {
15332 +    UBICOM32_INSN_ASR_2_IMM_BIT5_S1_INDIRECT_2, "asr.2-imm-bit5-s1-indirect-2", "asr.2", 32,
15333 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15334 +  },
15335 +/* asr.2 ${Dn},(${s1-An}),${s2} */
15336 +  {
15337 +    UBICOM32_INSN_ASR_2_DYN_REG_S1_INDIRECT_2, "asr.2-dyn-reg-s1-indirect-2", "asr.2", 32,
15338 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15339 +  },
15340 +/* asr.2 ${Dn},(${s1-An})${s1-i4-2}++,#${bit5} */
15341 +  {
15342 +    UBICOM32_INSN_ASR_2_IMM_BIT5_S1_INDIRECT_WITH_POST_INCREMENT_2, "asr.2-imm-bit5-s1-indirect-with-post-increment-2", "asr.2", 32,
15343 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15344 +  },
15345 +/* asr.2 ${Dn},(${s1-An})${s1-i4-2}++,${s2} */
15346 +  {
15347 +    UBICOM32_INSN_ASR_2_DYN_REG_S1_INDIRECT_WITH_POST_INCREMENT_2, "asr.2-dyn-reg-s1-indirect-with-post-increment-2", "asr.2", 32,
15348 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15349 +  },
15350 +/* asr.2 ${Dn},${s1-i4-2}(${s1-An})++,#${bit5} */
15351 +  {
15352 +    UBICOM32_INSN_ASR_2_IMM_BIT5_S1_INDIRECT_WITH_PRE_INCREMENT_2, "asr.2-imm-bit5-s1-indirect-with-pre-increment-2", "asr.2", 32,
15353 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15354 +  },
15355 +/* asr.2 ${Dn},${s1-i4-2}(${s1-An})++,${s2} */
15356 +  {
15357 +    UBICOM32_INSN_ASR_2_DYN_REG_S1_INDIRECT_WITH_PRE_INCREMENT_2, "asr.2-dyn-reg-s1-indirect-with-pre-increment-2", "asr.2", 32,
15358 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15359 +  },
15360 +/* lsl.2 ${Dn},${s1-direct-addr},#${bit5} */
15361 +  {
15362 +    UBICOM32_INSN_LSL_2_IMM_BIT5_S1_DIRECT, "lsl.2-imm-bit5-s1-direct", "lsl.2", 32,
15363 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15364 +  },
15365 +/* lsl.2 ${Dn},${s1-direct-addr},${s2} */
15366 +  {
15367 +    UBICOM32_INSN_LSL_2_DYN_REG_S1_DIRECT, "lsl.2-dyn-reg-s1-direct", "lsl.2", 32,
15368 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15369 +  },
15370 +/* lsl.2 ${Dn},#${s1-imm8},#${bit5} */
15371 +  {
15372 +    UBICOM32_INSN_LSL_2_IMM_BIT5_S1_IMMEDIATE, "lsl.2-imm-bit5-s1-immediate", "lsl.2", 32,
15373 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15374 +  },
15375 +/* lsl.2 ${Dn},#${s1-imm8},${s2} */
15376 +  {
15377 +    UBICOM32_INSN_LSL_2_DYN_REG_S1_IMMEDIATE, "lsl.2-dyn-reg-s1-immediate", "lsl.2", 32,
15378 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15379 +  },
15380 +/* lsl.2 ${Dn},(${s1-An},${s1-r}),#${bit5} */
15381 +  {
15382 +    UBICOM32_INSN_LSL_2_IMM_BIT5_S1_INDIRECT_WITH_INDEX_2, "lsl.2-imm-bit5-s1-indirect-with-index-2", "lsl.2", 32,
15383 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15384 +  },
15385 +/* lsl.2 ${Dn},(${s1-An},${s1-r}),${s2} */
15386 +  {
15387 +    UBICOM32_INSN_LSL_2_DYN_REG_S1_INDIRECT_WITH_INDEX_2, "lsl.2-dyn-reg-s1-indirect-with-index-2", "lsl.2", 32,
15388 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15389 +  },
15390 +/* lsl.2 ${Dn},${s1-imm7-2}(${s1-An}),#${bit5} */
15391 +  {
15392 +    UBICOM32_INSN_LSL_2_IMM_BIT5_S1_INDIRECT_WITH_OFFSET_2, "lsl.2-imm-bit5-s1-indirect-with-offset-2", "lsl.2", 32,
15393 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15394 +  },
15395 +/* lsl.2 ${Dn},${s1-imm7-2}(${s1-An}),${s2} */
15396 +  {
15397 +    UBICOM32_INSN_LSL_2_DYN_REG_S1_INDIRECT_WITH_OFFSET_2, "lsl.2-dyn-reg-s1-indirect-with-offset-2", "lsl.2", 32,
15398 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15399 +  },
15400 +/* lsl.2 ${Dn},(${s1-An}),#${bit5} */
15401 +  {
15402 +    UBICOM32_INSN_LSL_2_IMM_BIT5_S1_INDIRECT_2, "lsl.2-imm-bit5-s1-indirect-2", "lsl.2", 32,
15403 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15404 +  },
15405 +/* lsl.2 ${Dn},(${s1-An}),${s2} */
15406 +  {
15407 +    UBICOM32_INSN_LSL_2_DYN_REG_S1_INDIRECT_2, "lsl.2-dyn-reg-s1-indirect-2", "lsl.2", 32,
15408 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15409 +  },
15410 +/* lsl.2 ${Dn},(${s1-An})${s1-i4-2}++,#${bit5} */
15411 +  {
15412 +    UBICOM32_INSN_LSL_2_IMM_BIT5_S1_INDIRECT_WITH_POST_INCREMENT_2, "lsl.2-imm-bit5-s1-indirect-with-post-increment-2", "lsl.2", 32,
15413 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15414 +  },
15415 +/* lsl.2 ${Dn},(${s1-An})${s1-i4-2}++,${s2} */
15416 +  {
15417 +    UBICOM32_INSN_LSL_2_DYN_REG_S1_INDIRECT_WITH_POST_INCREMENT_2, "lsl.2-dyn-reg-s1-indirect-with-post-increment-2", "lsl.2", 32,
15418 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15419 +  },
15420 +/* lsl.2 ${Dn},${s1-i4-2}(${s1-An})++,#${bit5} */
15421 +  {
15422 +    UBICOM32_INSN_LSL_2_IMM_BIT5_S1_INDIRECT_WITH_PRE_INCREMENT_2, "lsl.2-imm-bit5-s1-indirect-with-pre-increment-2", "lsl.2", 32,
15423 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15424 +  },
15425 +/* lsl.2 ${Dn},${s1-i4-2}(${s1-An})++,${s2} */
15426 +  {
15427 +    UBICOM32_INSN_LSL_2_DYN_REG_S1_INDIRECT_WITH_PRE_INCREMENT_2, "lsl.2-dyn-reg-s1-indirect-with-pre-increment-2", "lsl.2", 32,
15428 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15429 +  },
15430 +/* lsr.2 ${Dn},${s1-direct-addr},#${bit5} */
15431 +  {
15432 +    UBICOM32_INSN_LSR_2_IMM_BIT5_S1_DIRECT, "lsr.2-imm-bit5-s1-direct", "lsr.2", 32,
15433 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15434 +  },
15435 +/* lsr.2 ${Dn},${s1-direct-addr},${s2} */
15436 +  {
15437 +    UBICOM32_INSN_LSR_2_DYN_REG_S1_DIRECT, "lsr.2-dyn-reg-s1-direct", "lsr.2", 32,
15438 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15439 +  },
15440 +/* lsr.2 ${Dn},#${s1-imm8},#${bit5} */
15441 +  {
15442 +    UBICOM32_INSN_LSR_2_IMM_BIT5_S1_IMMEDIATE, "lsr.2-imm-bit5-s1-immediate", "lsr.2", 32,
15443 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15444 +  },
15445 +/* lsr.2 ${Dn},#${s1-imm8},${s2} */
15446 +  {
15447 +    UBICOM32_INSN_LSR_2_DYN_REG_S1_IMMEDIATE, "lsr.2-dyn-reg-s1-immediate", "lsr.2", 32,
15448 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15449 +  },
15450 +/* lsr.2 ${Dn},(${s1-An},${s1-r}),#${bit5} */
15451 +  {
15452 +    UBICOM32_INSN_LSR_2_IMM_BIT5_S1_INDIRECT_WITH_INDEX_2, "lsr.2-imm-bit5-s1-indirect-with-index-2", "lsr.2", 32,
15453 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15454 +  },
15455 +/* lsr.2 ${Dn},(${s1-An},${s1-r}),${s2} */
15456 +  {
15457 +    UBICOM32_INSN_LSR_2_DYN_REG_S1_INDIRECT_WITH_INDEX_2, "lsr.2-dyn-reg-s1-indirect-with-index-2", "lsr.2", 32,
15458 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15459 +  },
15460 +/* lsr.2 ${Dn},${s1-imm7-2}(${s1-An}),#${bit5} */
15461 +  {
15462 +    UBICOM32_INSN_LSR_2_IMM_BIT5_S1_INDIRECT_WITH_OFFSET_2, "lsr.2-imm-bit5-s1-indirect-with-offset-2", "lsr.2", 32,
15463 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15464 +  },
15465 +/* lsr.2 ${Dn},${s1-imm7-2}(${s1-An}),${s2} */
15466 +  {
15467 +    UBICOM32_INSN_LSR_2_DYN_REG_S1_INDIRECT_WITH_OFFSET_2, "lsr.2-dyn-reg-s1-indirect-with-offset-2", "lsr.2", 32,
15468 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15469 +  },
15470 +/* lsr.2 ${Dn},(${s1-An}),#${bit5} */
15471 +  {
15472 +    UBICOM32_INSN_LSR_2_IMM_BIT5_S1_INDIRECT_2, "lsr.2-imm-bit5-s1-indirect-2", "lsr.2", 32,
15473 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15474 +  },
15475 +/* lsr.2 ${Dn},(${s1-An}),${s2} */
15476 +  {
15477 +    UBICOM32_INSN_LSR_2_DYN_REG_S1_INDIRECT_2, "lsr.2-dyn-reg-s1-indirect-2", "lsr.2", 32,
15478 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15479 +  },
15480 +/* lsr.2 ${Dn},(${s1-An})${s1-i4-2}++,#${bit5} */
15481 +  {
15482 +    UBICOM32_INSN_LSR_2_IMM_BIT5_S1_INDIRECT_WITH_POST_INCREMENT_2, "lsr.2-imm-bit5-s1-indirect-with-post-increment-2", "lsr.2", 32,
15483 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15484 +  },
15485 +/* lsr.2 ${Dn},(${s1-An})${s1-i4-2}++,${s2} */
15486 +  {
15487 +    UBICOM32_INSN_LSR_2_DYN_REG_S1_INDIRECT_WITH_POST_INCREMENT_2, "lsr.2-dyn-reg-s1-indirect-with-post-increment-2", "lsr.2", 32,
15488 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15489 +  },
15490 +/* lsr.2 ${Dn},${s1-i4-2}(${s1-An})++,#${bit5} */
15491 +  {
15492 +    UBICOM32_INSN_LSR_2_IMM_BIT5_S1_INDIRECT_WITH_PRE_INCREMENT_2, "lsr.2-imm-bit5-s1-indirect-with-pre-increment-2", "lsr.2", 32,
15493 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15494 +  },
15495 +/* lsr.2 ${Dn},${s1-i4-2}(${s1-An})++,${s2} */
15496 +  {
15497 +    UBICOM32_INSN_LSR_2_DYN_REG_S1_INDIRECT_WITH_PRE_INCREMENT_2, "lsr.2-dyn-reg-s1-indirect-with-pre-increment-2", "lsr.2", 32,
15498 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15499 +  },
15500 +/* asr.4 ${Dn},${s1-direct-addr},#${bit5} */
15501 +  {
15502 +    UBICOM32_INSN_ASR_4_IMM_BIT5_S1_DIRECT, "asr.4-imm-bit5-s1-direct", "asr.4", 32,
15503 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15504 +  },
15505 +/* asr.4 ${Dn},${s1-direct-addr},${s2} */
15506 +  {
15507 +    UBICOM32_INSN_ASR_4_DYN_REG_S1_DIRECT, "asr.4-dyn-reg-s1-direct", "asr.4", 32,
15508 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15509 +  },
15510 +/* asr.4 ${Dn},#${s1-imm8},#${bit5} */
15511 +  {
15512 +    UBICOM32_INSN_ASR_4_IMM_BIT5_S1_IMMEDIATE, "asr.4-imm-bit5-s1-immediate", "asr.4", 32,
15513 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15514 +  },
15515 +/* asr.4 ${Dn},#${s1-imm8},${s2} */
15516 +  {
15517 +    UBICOM32_INSN_ASR_4_DYN_REG_S1_IMMEDIATE, "asr.4-dyn-reg-s1-immediate", "asr.4", 32,
15518 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15519 +  },
15520 +/* asr.4 ${Dn},(${s1-An},${s1-r}),#${bit5} */
15521 +  {
15522 +    UBICOM32_INSN_ASR_4_IMM_BIT5_S1_INDIRECT_WITH_INDEX_4, "asr.4-imm-bit5-s1-indirect-with-index-4", "asr.4", 32,
15523 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15524 +  },
15525 +/* asr.4 ${Dn},(${s1-An},${s1-r}),${s2} */
15526 +  {
15527 +    UBICOM32_INSN_ASR_4_DYN_REG_S1_INDIRECT_WITH_INDEX_4, "asr.4-dyn-reg-s1-indirect-with-index-4", "asr.4", 32,
15528 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15529 +  },
15530 +/* asr.4 ${Dn},${s1-imm7-4}(${s1-An}),#${bit5} */
15531 +  {
15532 +    UBICOM32_INSN_ASR_4_IMM_BIT5_S1_INDIRECT_WITH_OFFSET_4, "asr.4-imm-bit5-s1-indirect-with-offset-4", "asr.4", 32,
15533 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15534 +  },
15535 +/* asr.4 ${Dn},${s1-imm7-4}(${s1-An}),${s2} */
15536 +  {
15537 +    UBICOM32_INSN_ASR_4_DYN_REG_S1_INDIRECT_WITH_OFFSET_4, "asr.4-dyn-reg-s1-indirect-with-offset-4", "asr.4", 32,
15538 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15539 +  },
15540 +/* asr.4 ${Dn},(${s1-An}),#${bit5} */
15541 +  {
15542 +    UBICOM32_INSN_ASR_4_IMM_BIT5_S1_INDIRECT_4, "asr.4-imm-bit5-s1-indirect-4", "asr.4", 32,
15543 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15544 +  },
15545 +/* asr.4 ${Dn},(${s1-An}),${s2} */
15546 +  {
15547 +    UBICOM32_INSN_ASR_4_DYN_REG_S1_INDIRECT_4, "asr.4-dyn-reg-s1-indirect-4", "asr.4", 32,
15548 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15549 +  },
15550 +/* asr.4 ${Dn},(${s1-An})${s1-i4-4}++,#${bit5} */
15551 +  {
15552 +    UBICOM32_INSN_ASR_4_IMM_BIT5_S1_INDIRECT_WITH_POST_INCREMENT_4, "asr.4-imm-bit5-s1-indirect-with-post-increment-4", "asr.4", 32,
15553 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15554 +  },
15555 +/* asr.4 ${Dn},(${s1-An})${s1-i4-4}++,${s2} */
15556 +  {
15557 +    UBICOM32_INSN_ASR_4_DYN_REG_S1_INDIRECT_WITH_POST_INCREMENT_4, "asr.4-dyn-reg-s1-indirect-with-post-increment-4", "asr.4", 32,
15558 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15559 +  },
15560 +/* asr.4 ${Dn},${s1-i4-4}(${s1-An})++,#${bit5} */
15561 +  {
15562 +    UBICOM32_INSN_ASR_4_IMM_BIT5_S1_INDIRECT_WITH_PRE_INCREMENT_4, "asr.4-imm-bit5-s1-indirect-with-pre-increment-4", "asr.4", 32,
15563 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15564 +  },
15565 +/* asr.4 ${Dn},${s1-i4-4}(${s1-An})++,${s2} */
15566 +  {
15567 +    UBICOM32_INSN_ASR_4_DYN_REG_S1_INDIRECT_WITH_PRE_INCREMENT_4, "asr.4-dyn-reg-s1-indirect-with-pre-increment-4", "asr.4", 32,
15568 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15569 +  },
15570 +/* lsl.4 ${Dn},${s1-direct-addr},#${bit5} */
15571 +  {
15572 +    UBICOM32_INSN_LSL_4_IMM_BIT5_S1_DIRECT, "lsl.4-imm-bit5-s1-direct", "lsl.4", 32,
15573 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15574 +  },
15575 +/* lsl.4 ${Dn},${s1-direct-addr},${s2} */
15576 +  {
15577 +    UBICOM32_INSN_LSL_4_DYN_REG_S1_DIRECT, "lsl.4-dyn-reg-s1-direct", "lsl.4", 32,
15578 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15579 +  },
15580 +/* lsl.4 ${Dn},#${s1-imm8},#${bit5} */
15581 +  {
15582 +    UBICOM32_INSN_LSL_4_IMM_BIT5_S1_IMMEDIATE, "lsl.4-imm-bit5-s1-immediate", "lsl.4", 32,
15583 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15584 +  },
15585 +/* lsl.4 ${Dn},#${s1-imm8},${s2} */
15586 +  {
15587 +    UBICOM32_INSN_LSL_4_DYN_REG_S1_IMMEDIATE, "lsl.4-dyn-reg-s1-immediate", "lsl.4", 32,
15588 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15589 +  },
15590 +/* lsl.4 ${Dn},(${s1-An},${s1-r}),#${bit5} */
15591 +  {
15592 +    UBICOM32_INSN_LSL_4_IMM_BIT5_S1_INDIRECT_WITH_INDEX_4, "lsl.4-imm-bit5-s1-indirect-with-index-4", "lsl.4", 32,
15593 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15594 +  },
15595 +/* lsl.4 ${Dn},(${s1-An},${s1-r}),${s2} */
15596 +  {
15597 +    UBICOM32_INSN_LSL_4_DYN_REG_S1_INDIRECT_WITH_INDEX_4, "lsl.4-dyn-reg-s1-indirect-with-index-4", "lsl.4", 32,
15598 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15599 +  },
15600 +/* lsl.4 ${Dn},${s1-imm7-4}(${s1-An}),#${bit5} */
15601 +  {
15602 +    UBICOM32_INSN_LSL_4_IMM_BIT5_S1_INDIRECT_WITH_OFFSET_4, "lsl.4-imm-bit5-s1-indirect-with-offset-4", "lsl.4", 32,
15603 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15604 +  },
15605 +/* lsl.4 ${Dn},${s1-imm7-4}(${s1-An}),${s2} */
15606 +  {
15607 +    UBICOM32_INSN_LSL_4_DYN_REG_S1_INDIRECT_WITH_OFFSET_4, "lsl.4-dyn-reg-s1-indirect-with-offset-4", "lsl.4", 32,
15608 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15609 +  },
15610 +/* lsl.4 ${Dn},(${s1-An}),#${bit5} */
15611 +  {
15612 +    UBICOM32_INSN_LSL_4_IMM_BIT5_S1_INDIRECT_4, "lsl.4-imm-bit5-s1-indirect-4", "lsl.4", 32,
15613 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15614 +  },
15615 +/* lsl.4 ${Dn},(${s1-An}),${s2} */
15616 +  {
15617 +    UBICOM32_INSN_LSL_4_DYN_REG_S1_INDIRECT_4, "lsl.4-dyn-reg-s1-indirect-4", "lsl.4", 32,
15618 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15619 +  },
15620 +/* lsl.4 ${Dn},(${s1-An})${s1-i4-4}++,#${bit5} */
15621 +  {
15622 +    UBICOM32_INSN_LSL_4_IMM_BIT5_S1_INDIRECT_WITH_POST_INCREMENT_4, "lsl.4-imm-bit5-s1-indirect-with-post-increment-4", "lsl.4", 32,
15623 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15624 +  },
15625 +/* lsl.4 ${Dn},(${s1-An})${s1-i4-4}++,${s2} */
15626 +  {
15627 +    UBICOM32_INSN_LSL_4_DYN_REG_S1_INDIRECT_WITH_POST_INCREMENT_4, "lsl.4-dyn-reg-s1-indirect-with-post-increment-4", "lsl.4", 32,
15628 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15629 +  },
15630 +/* lsl.4 ${Dn},${s1-i4-4}(${s1-An})++,#${bit5} */
15631 +  {
15632 +    UBICOM32_INSN_LSL_4_IMM_BIT5_S1_INDIRECT_WITH_PRE_INCREMENT_4, "lsl.4-imm-bit5-s1-indirect-with-pre-increment-4", "lsl.4", 32,
15633 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15634 +  },
15635 +/* lsl.4 ${Dn},${s1-i4-4}(${s1-An})++,${s2} */
15636 +  {
15637 +    UBICOM32_INSN_LSL_4_DYN_REG_S1_INDIRECT_WITH_PRE_INCREMENT_4, "lsl.4-dyn-reg-s1-indirect-with-pre-increment-4", "lsl.4", 32,
15638 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15639 +  },
15640 +/* lsr.4 ${Dn},${s1-direct-addr},#${bit5} */
15641 +  {
15642 +    UBICOM32_INSN_LSR_4_IMM_BIT5_S1_DIRECT, "lsr.4-imm-bit5-s1-direct", "lsr.4", 32,
15643 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15644 +  },
15645 +/* lsr.4 ${Dn},${s1-direct-addr},${s2} */
15646 +  {
15647 +    UBICOM32_INSN_LSR_4_DYN_REG_S1_DIRECT, "lsr.4-dyn-reg-s1-direct", "lsr.4", 32,
15648 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15649 +  },
15650 +/* lsr.4 ${Dn},#${s1-imm8},#${bit5} */
15651 +  {
15652 +    UBICOM32_INSN_LSR_4_IMM_BIT5_S1_IMMEDIATE, "lsr.4-imm-bit5-s1-immediate", "lsr.4", 32,
15653 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15654 +  },
15655 +/* lsr.4 ${Dn},#${s1-imm8},${s2} */
15656 +  {
15657 +    UBICOM32_INSN_LSR_4_DYN_REG_S1_IMMEDIATE, "lsr.4-dyn-reg-s1-immediate", "lsr.4", 32,
15658 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15659 +  },
15660 +/* lsr.4 ${Dn},(${s1-An},${s1-r}),#${bit5} */
15661 +  {
15662 +    UBICOM32_INSN_LSR_4_IMM_BIT5_S1_INDIRECT_WITH_INDEX_4, "lsr.4-imm-bit5-s1-indirect-with-index-4", "lsr.4", 32,
15663 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15664 +  },
15665 +/* lsr.4 ${Dn},(${s1-An},${s1-r}),${s2} */
15666 +  {
15667 +    UBICOM32_INSN_LSR_4_DYN_REG_S1_INDIRECT_WITH_INDEX_4, "lsr.4-dyn-reg-s1-indirect-with-index-4", "lsr.4", 32,
15668 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15669 +  },
15670 +/* lsr.4 ${Dn},${s1-imm7-4}(${s1-An}),#${bit5} */
15671 +  {
15672 +    UBICOM32_INSN_LSR_4_IMM_BIT5_S1_INDIRECT_WITH_OFFSET_4, "lsr.4-imm-bit5-s1-indirect-with-offset-4", "lsr.4", 32,
15673 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15674 +  },
15675 +/* lsr.4 ${Dn},${s1-imm7-4}(${s1-An}),${s2} */
15676 +  {
15677 +    UBICOM32_INSN_LSR_4_DYN_REG_S1_INDIRECT_WITH_OFFSET_4, "lsr.4-dyn-reg-s1-indirect-with-offset-4", "lsr.4", 32,
15678 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15679 +  },
15680 +/* lsr.4 ${Dn},(${s1-An}),#${bit5} */
15681 +  {
15682 +    UBICOM32_INSN_LSR_4_IMM_BIT5_S1_INDIRECT_4, "lsr.4-imm-bit5-s1-indirect-4", "lsr.4", 32,
15683 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15684 +  },
15685 +/* lsr.4 ${Dn},(${s1-An}),${s2} */
15686 +  {
15687 +    UBICOM32_INSN_LSR_4_DYN_REG_S1_INDIRECT_4, "lsr.4-dyn-reg-s1-indirect-4", "lsr.4", 32,
15688 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15689 +  },
15690 +/* lsr.4 ${Dn},(${s1-An})${s1-i4-4}++,#${bit5} */
15691 +  {
15692 +    UBICOM32_INSN_LSR_4_IMM_BIT5_S1_INDIRECT_WITH_POST_INCREMENT_4, "lsr.4-imm-bit5-s1-indirect-with-post-increment-4", "lsr.4", 32,
15693 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15694 +  },
15695 +/* lsr.4 ${Dn},(${s1-An})${s1-i4-4}++,${s2} */
15696 +  {
15697 +    UBICOM32_INSN_LSR_4_DYN_REG_S1_INDIRECT_WITH_POST_INCREMENT_4, "lsr.4-dyn-reg-s1-indirect-with-post-increment-4", "lsr.4", 32,
15698 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15699 +  },
15700 +/* lsr.4 ${Dn},${s1-i4-4}(${s1-An})++,#${bit5} */
15701 +  {
15702 +    UBICOM32_INSN_LSR_4_IMM_BIT5_S1_INDIRECT_WITH_PRE_INCREMENT_4, "lsr.4-imm-bit5-s1-indirect-with-pre-increment-4", "lsr.4", 32,
15703 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15704 +  },
15705 +/* lsr.4 ${Dn},${s1-i4-4}(${s1-An})++,${s2} */
15706 +  {
15707 +    UBICOM32_INSN_LSR_4_DYN_REG_S1_INDIRECT_WITH_PRE_INCREMENT_4, "lsr.4-dyn-reg-s1-indirect-with-pre-increment-4", "lsr.4", 32,
15708 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
15709 +  },
15710 +/* mac ${s1-direct-addr},${dsp-S2-data-reg} */
15711 +  {
15712 +    UBICOM32_INSN_COMPATIBILITY_MAC_S1_DIRECT_DSP_SRC2_DATA_REG, "compatibility-mac-s1-direct-dsp-src2-data-reg", "mac", 32,
15713 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
15714 +  },
15715 +/* mac #${s1-imm8},${dsp-S2-data-reg} */
15716 +  {
15717 +    UBICOM32_INSN_COMPATIBILITY_MAC_S1_IMMEDIATE_DSP_SRC2_DATA_REG, "compatibility-mac-s1-immediate-dsp-src2-data-reg", "mac", 32,
15718 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
15719 +  },
15720 +/* mac (${s1-An},${s1-r}),${dsp-S2-data-reg} */
15721 +  {
15722 +    UBICOM32_INSN_COMPATIBILITY_MAC_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_DATA_REG, "compatibility-mac-s1-indirect-with-index-2-dsp-src2-data-reg", "mac", 32,
15723 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
15724 +  },
15725 +/* mac ${s1-imm7-2}(${s1-An}),${dsp-S2-data-reg} */
15726 +  {
15727 +    UBICOM32_INSN_COMPATIBILITY_MAC_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_DATA_REG, "compatibility-mac-s1-indirect-with-offset-2-dsp-src2-data-reg", "mac", 32,
15728 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
15729 +  },
15730 +/* mac (${s1-An}),${dsp-S2-data-reg} */
15731 +  {
15732 +    UBICOM32_INSN_COMPATIBILITY_MAC_S1_INDIRECT_2_DSP_SRC2_DATA_REG, "compatibility-mac-s1-indirect-2-dsp-src2-data-reg", "mac", 32,
15733 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
15734 +  },
15735 +/* mac (${s1-An})${s1-i4-2}++,${dsp-S2-data-reg} */
15736 +  {
15737 +    UBICOM32_INSN_COMPATIBILITY_MAC_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_DATA_REG, "compatibility-mac-s1-indirect-with-post-increment-2-dsp-src2-data-reg", "mac", 32,
15738 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
15739 +  },
15740 +/* mac ${s1-i4-2}(${s1-An})++,${dsp-S2-data-reg} */
15741 +  {
15742 +    UBICOM32_INSN_COMPATIBILITY_MAC_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_DATA_REG, "compatibility-mac-s1-indirect-with-pre-increment-2-dsp-src2-data-reg", "mac", 32,
15743 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
15744 +  },
15745 +/* mac ${s1-direct-addr},#${bit5} */
15746 +  {
15747 +    UBICOM32_INSN_COMPATIBILITY_MAC_S1_DIRECT_DSP_IMM_BIT5, "compatibility-mac-s1-direct-dsp-imm-bit5", "mac", 32,
15748 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
15749 +  },
15750 +/* mac #${s1-imm8},#${bit5} */
15751 +  {
15752 +    UBICOM32_INSN_COMPATIBILITY_MAC_S1_IMMEDIATE_DSP_IMM_BIT5, "compatibility-mac-s1-immediate-dsp-imm-bit5", "mac", 32,
15753 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
15754 +  },
15755 +/* mac (${s1-An},${s1-r}),#${bit5} */
15756 +  {
15757 +    UBICOM32_INSN_COMPATIBILITY_MAC_S1_INDIRECT_WITH_INDEX_2_DSP_IMM_BIT5, "compatibility-mac-s1-indirect-with-index-2-dsp-imm-bit5", "mac", 32,
15758 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
15759 +  },
15760 +/* mac ${s1-imm7-2}(${s1-An}),#${bit5} */
15761 +  {
15762 +    UBICOM32_INSN_COMPATIBILITY_MAC_S1_INDIRECT_WITH_OFFSET_2_DSP_IMM_BIT5, "compatibility-mac-s1-indirect-with-offset-2-dsp-imm-bit5", "mac", 32,
15763 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
15764 +  },
15765 +/* mac (${s1-An}),#${bit5} */
15766 +  {
15767 +    UBICOM32_INSN_COMPATIBILITY_MAC_S1_INDIRECT_2_DSP_IMM_BIT5, "compatibility-mac-s1-indirect-2-dsp-imm-bit5", "mac", 32,
15768 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
15769 +  },
15770 +/* mac (${s1-An})${s1-i4-2}++,#${bit5} */
15771 +  {
15772 +    UBICOM32_INSN_COMPATIBILITY_MAC_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_IMM_BIT5, "compatibility-mac-s1-indirect-with-post-increment-2-dsp-imm-bit5", "mac", 32,
15773 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
15774 +  },
15775 +/* mac ${s1-i4-2}(${s1-An})++,#${bit5} */
15776 +  {
15777 +    UBICOM32_INSN_COMPATIBILITY_MAC_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_IMM_BIT5, "compatibility-mac-s1-indirect-with-pre-increment-2-dsp-imm-bit5", "mac", 32,
15778 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
15779 +  },
15780 +/* mac ${s1-direct-addr},#${bit5} */
15781 +  {
15782 +    UBICOM32_INSN_MAC_S1_DIRECT_IMM_BIT5, "mac-s1-direct-imm-bit5", "mac", 32,
15783 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
15784 +  },
15785 +/* mac #${s1-imm8},#${bit5} */
15786 +  {
15787 +    UBICOM32_INSN_MAC_S1_IMMEDIATE_IMM_BIT5, "mac-s1-immediate-imm-bit5", "mac", 32,
15788 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
15789 +  },
15790 +/* mac (${s1-An},${s1-r}),#${bit5} */
15791 +  {
15792 +    UBICOM32_INSN_MAC_S1_INDIRECT_WITH_INDEX_2_IMM_BIT5, "mac-s1-indirect-with-index-2-imm-bit5", "mac", 32,
15793 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
15794 +  },
15795 +/* mac ${s1-imm7-2}(${s1-An}),#${bit5} */
15796 +  {
15797 +    UBICOM32_INSN_MAC_S1_INDIRECT_WITH_OFFSET_2_IMM_BIT5, "mac-s1-indirect-with-offset-2-imm-bit5", "mac", 32,
15798 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
15799 +  },
15800 +/* mac (${s1-An}),#${bit5} */
15801 +  {
15802 +    UBICOM32_INSN_MAC_S1_INDIRECT_2_IMM_BIT5, "mac-s1-indirect-2-imm-bit5", "mac", 32,
15803 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
15804 +  },
15805 +/* mac (${s1-An})${s1-i4-2}++,#${bit5} */
15806 +  {
15807 +    UBICOM32_INSN_MAC_S1_INDIRECT_WITH_POST_INCREMENT_2_IMM_BIT5, "mac-s1-indirect-with-post-increment-2-imm-bit5", "mac", 32,
15808 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
15809 +  },
15810 +/* mac ${s1-i4-2}(${s1-An})++,#${bit5} */
15811 +  {
15812 +    UBICOM32_INSN_MAC_S1_INDIRECT_WITH_PRE_INCREMENT_2_IMM_BIT5, "mac-s1-indirect-with-pre-increment-2-imm-bit5", "mac", 32,
15813 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
15814 +  },
15815 +/* mac ${s1-direct-addr},${s2} */
15816 +  {
15817 +    UBICOM32_INSN_MAC_S1_DIRECT_DYN_REG, "mac-s1-direct-dyn-reg", "mac", 32,
15818 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
15819 +  },
15820 +/* mac #${s1-imm8},${s2} */
15821 +  {
15822 +    UBICOM32_INSN_MAC_S1_IMMEDIATE_DYN_REG, "mac-s1-immediate-dyn-reg", "mac", 32,
15823 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
15824 +  },
15825 +/* mac (${s1-An},${s1-r}),${s2} */
15826 +  {
15827 +    UBICOM32_INSN_MAC_S1_INDIRECT_WITH_INDEX_2_DYN_REG, "mac-s1-indirect-with-index-2-dyn-reg", "mac", 32,
15828 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
15829 +  },
15830 +/* mac ${s1-imm7-2}(${s1-An}),${s2} */
15831 +  {
15832 +    UBICOM32_INSN_MAC_S1_INDIRECT_WITH_OFFSET_2_DYN_REG, "mac-s1-indirect-with-offset-2-dyn-reg", "mac", 32,
15833 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
15834 +  },
15835 +/* mac (${s1-An}),${s2} */
15836 +  {
15837 +    UBICOM32_INSN_MAC_S1_INDIRECT_2_DYN_REG, "mac-s1-indirect-2-dyn-reg", "mac", 32,
15838 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
15839 +  },
15840 +/* mac (${s1-An})${s1-i4-2}++,${s2} */
15841 +  {
15842 +    UBICOM32_INSN_MAC_S1_INDIRECT_WITH_POST_INCREMENT_2_DYN_REG, "mac-s1-indirect-with-post-increment-2-dyn-reg", "mac", 32,
15843 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
15844 +  },
15845 +/* mac ${s1-i4-2}(${s1-An})++,${s2} */
15846 +  {
15847 +    UBICOM32_INSN_MAC_S1_INDIRECT_WITH_PRE_INCREMENT_2_DYN_REG, "mac-s1-indirect-with-pre-increment-2-dyn-reg", "mac", 32,
15848 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
15849 +  },
15850 +/* mulf ${s1-direct-addr},${dsp-S2-data-reg} */
15851 +  {
15852 +    UBICOM32_INSN_COMPATIBILITY_MULF_S1_DIRECT_DSP_SRC2_DATA_REG, "compatibility-mulf-s1-direct-dsp-src2-data-reg", "mulf", 32,
15853 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
15854 +  },
15855 +/* mulf #${s1-imm8},${dsp-S2-data-reg} */
15856 +  {
15857 +    UBICOM32_INSN_COMPATIBILITY_MULF_S1_IMMEDIATE_DSP_SRC2_DATA_REG, "compatibility-mulf-s1-immediate-dsp-src2-data-reg", "mulf", 32,
15858 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
15859 +  },
15860 +/* mulf (${s1-An},${s1-r}),${dsp-S2-data-reg} */
15861 +  {
15862 +    UBICOM32_INSN_COMPATIBILITY_MULF_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_DATA_REG, "compatibility-mulf-s1-indirect-with-index-2-dsp-src2-data-reg", "mulf", 32,
15863 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
15864 +  },
15865 +/* mulf ${s1-imm7-2}(${s1-An}),${dsp-S2-data-reg} */
15866 +  {
15867 +    UBICOM32_INSN_COMPATIBILITY_MULF_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_DATA_REG, "compatibility-mulf-s1-indirect-with-offset-2-dsp-src2-data-reg", "mulf", 32,
15868 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
15869 +  },
15870 +/* mulf (${s1-An}),${dsp-S2-data-reg} */
15871 +  {
15872 +    UBICOM32_INSN_COMPATIBILITY_MULF_S1_INDIRECT_2_DSP_SRC2_DATA_REG, "compatibility-mulf-s1-indirect-2-dsp-src2-data-reg", "mulf", 32,
15873 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
15874 +  },
15875 +/* mulf (${s1-An})${s1-i4-2}++,${dsp-S2-data-reg} */
15876 +  {
15877 +    UBICOM32_INSN_COMPATIBILITY_MULF_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_DATA_REG, "compatibility-mulf-s1-indirect-with-post-increment-2-dsp-src2-data-reg", "mulf", 32,
15878 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
15879 +  },
15880 +/* mulf ${s1-i4-2}(${s1-An})++,${dsp-S2-data-reg} */
15881 +  {
15882 +    UBICOM32_INSN_COMPATIBILITY_MULF_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_DATA_REG, "compatibility-mulf-s1-indirect-with-pre-increment-2-dsp-src2-data-reg", "mulf", 32,
15883 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
15884 +  },
15885 +/* mulf ${s1-direct-addr},#${bit5} */
15886 +  {
15887 +    UBICOM32_INSN_COMPATIBILITY_MULF_S1_DIRECT_DSP_IMM_BIT5, "compatibility-mulf-s1-direct-dsp-imm-bit5", "mulf", 32,
15888 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
15889 +  },
15890 +/* mulf #${s1-imm8},#${bit5} */
15891 +  {
15892 +    UBICOM32_INSN_COMPATIBILITY_MULF_S1_IMMEDIATE_DSP_IMM_BIT5, "compatibility-mulf-s1-immediate-dsp-imm-bit5", "mulf", 32,
15893 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
15894 +  },
15895 +/* mulf (${s1-An},${s1-r}),#${bit5} */
15896 +  {
15897 +    UBICOM32_INSN_COMPATIBILITY_MULF_S1_INDIRECT_WITH_INDEX_2_DSP_IMM_BIT5, "compatibility-mulf-s1-indirect-with-index-2-dsp-imm-bit5", "mulf", 32,
15898 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
15899 +  },
15900 +/* mulf ${s1-imm7-2}(${s1-An}),#${bit5} */
15901 +  {
15902 +    UBICOM32_INSN_COMPATIBILITY_MULF_S1_INDIRECT_WITH_OFFSET_2_DSP_IMM_BIT5, "compatibility-mulf-s1-indirect-with-offset-2-dsp-imm-bit5", "mulf", 32,
15903 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
15904 +  },
15905 +/* mulf (${s1-An}),#${bit5} */
15906 +  {
15907 +    UBICOM32_INSN_COMPATIBILITY_MULF_S1_INDIRECT_2_DSP_IMM_BIT5, "compatibility-mulf-s1-indirect-2-dsp-imm-bit5", "mulf", 32,
15908 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
15909 +  },
15910 +/* mulf (${s1-An})${s1-i4-2}++,#${bit5} */
15911 +  {
15912 +    UBICOM32_INSN_COMPATIBILITY_MULF_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_IMM_BIT5, "compatibility-mulf-s1-indirect-with-post-increment-2-dsp-imm-bit5", "mulf", 32,
15913 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
15914 +  },
15915 +/* mulf ${s1-i4-2}(${s1-An})++,#${bit5} */
15916 +  {
15917 +    UBICOM32_INSN_COMPATIBILITY_MULF_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_IMM_BIT5, "compatibility-mulf-s1-indirect-with-pre-increment-2-dsp-imm-bit5", "mulf", 32,
15918 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
15919 +  },
15920 +/* mulf ${s1-direct-addr},#${bit5} */
15921 +  {
15922 +    UBICOM32_INSN_MULF_S1_DIRECT_IMM_BIT5, "mulf-s1-direct-imm-bit5", "mulf", 32,
15923 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
15924 +  },
15925 +/* mulf #${s1-imm8},#${bit5} */
15926 +  {
15927 +    UBICOM32_INSN_MULF_S1_IMMEDIATE_IMM_BIT5, "mulf-s1-immediate-imm-bit5", "mulf", 32,
15928 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
15929 +  },
15930 +/* mulf (${s1-An},${s1-r}),#${bit5} */
15931 +  {
15932 +    UBICOM32_INSN_MULF_S1_INDIRECT_WITH_INDEX_2_IMM_BIT5, "mulf-s1-indirect-with-index-2-imm-bit5", "mulf", 32,
15933 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
15934 +  },
15935 +/* mulf ${s1-imm7-2}(${s1-An}),#${bit5} */
15936 +  {
15937 +    UBICOM32_INSN_MULF_S1_INDIRECT_WITH_OFFSET_2_IMM_BIT5, "mulf-s1-indirect-with-offset-2-imm-bit5", "mulf", 32,
15938 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
15939 +  },
15940 +/* mulf (${s1-An}),#${bit5} */
15941 +  {
15942 +    UBICOM32_INSN_MULF_S1_INDIRECT_2_IMM_BIT5, "mulf-s1-indirect-2-imm-bit5", "mulf", 32,
15943 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
15944 +  },
15945 +/* mulf (${s1-An})${s1-i4-2}++,#${bit5} */
15946 +  {
15947 +    UBICOM32_INSN_MULF_S1_INDIRECT_WITH_POST_INCREMENT_2_IMM_BIT5, "mulf-s1-indirect-with-post-increment-2-imm-bit5", "mulf", 32,
15948 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
15949 +  },
15950 +/* mulf ${s1-i4-2}(${s1-An})++,#${bit5} */
15951 +  {
15952 +    UBICOM32_INSN_MULF_S1_INDIRECT_WITH_PRE_INCREMENT_2_IMM_BIT5, "mulf-s1-indirect-with-pre-increment-2-imm-bit5", "mulf", 32,
15953 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
15954 +  },
15955 +/* mulf ${s1-direct-addr},${s2} */
15956 +  {
15957 +    UBICOM32_INSN_MULF_S1_DIRECT_DYN_REG, "mulf-s1-direct-dyn-reg", "mulf", 32,
15958 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
15959 +  },
15960 +/* mulf #${s1-imm8},${s2} */
15961 +  {
15962 +    UBICOM32_INSN_MULF_S1_IMMEDIATE_DYN_REG, "mulf-s1-immediate-dyn-reg", "mulf", 32,
15963 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
15964 +  },
15965 +/* mulf (${s1-An},${s1-r}),${s2} */
15966 +  {
15967 +    UBICOM32_INSN_MULF_S1_INDIRECT_WITH_INDEX_2_DYN_REG, "mulf-s1-indirect-with-index-2-dyn-reg", "mulf", 32,
15968 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
15969 +  },
15970 +/* mulf ${s1-imm7-2}(${s1-An}),${s2} */
15971 +  {
15972 +    UBICOM32_INSN_MULF_S1_INDIRECT_WITH_OFFSET_2_DYN_REG, "mulf-s1-indirect-with-offset-2-dyn-reg", "mulf", 32,
15973 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
15974 +  },
15975 +/* mulf (${s1-An}),${s2} */
15976 +  {
15977 +    UBICOM32_INSN_MULF_S1_INDIRECT_2_DYN_REG, "mulf-s1-indirect-2-dyn-reg", "mulf", 32,
15978 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
15979 +  },
15980 +/* mulf (${s1-An})${s1-i4-2}++,${s2} */
15981 +  {
15982 +    UBICOM32_INSN_MULF_S1_INDIRECT_WITH_POST_INCREMENT_2_DYN_REG, "mulf-s1-indirect-with-post-increment-2-dyn-reg", "mulf", 32,
15983 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
15984 +  },
15985 +/* mulf ${s1-i4-2}(${s1-An})++,${s2} */
15986 +  {
15987 +    UBICOM32_INSN_MULF_S1_INDIRECT_WITH_PRE_INCREMENT_2_DYN_REG, "mulf-s1-indirect-with-pre-increment-2-dyn-reg", "mulf", 32,
15988 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
15989 +  },
15990 +/* mulu ${s1-direct-addr},${dsp-S2-data-reg} */
15991 +  {
15992 +    UBICOM32_INSN_COMPATIBILITY_MULU_S1_DIRECT_DSP_SRC2_DATA_REG, "compatibility-mulu-s1-direct-dsp-src2-data-reg", "mulu", 32,
15993 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
15994 +  },
15995 +/* mulu #${s1-imm8},${dsp-S2-data-reg} */
15996 +  {
15997 +    UBICOM32_INSN_COMPATIBILITY_MULU_S1_IMMEDIATE_DSP_SRC2_DATA_REG, "compatibility-mulu-s1-immediate-dsp-src2-data-reg", "mulu", 32,
15998 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
15999 +  },
16000 +/* mulu (${s1-An},${s1-r}),${dsp-S2-data-reg} */
16001 +  {
16002 +    UBICOM32_INSN_COMPATIBILITY_MULU_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_DATA_REG, "compatibility-mulu-s1-indirect-with-index-2-dsp-src2-data-reg", "mulu", 32,
16003 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
16004 +  },
16005 +/* mulu ${s1-imm7-2}(${s1-An}),${dsp-S2-data-reg} */
16006 +  {
16007 +    UBICOM32_INSN_COMPATIBILITY_MULU_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_DATA_REG, "compatibility-mulu-s1-indirect-with-offset-2-dsp-src2-data-reg", "mulu", 32,
16008 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
16009 +  },
16010 +/* mulu (${s1-An}),${dsp-S2-data-reg} */
16011 +  {
16012 +    UBICOM32_INSN_COMPATIBILITY_MULU_S1_INDIRECT_2_DSP_SRC2_DATA_REG, "compatibility-mulu-s1-indirect-2-dsp-src2-data-reg", "mulu", 32,
16013 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
16014 +  },
16015 +/* mulu (${s1-An})${s1-i4-2}++,${dsp-S2-data-reg} */
16016 +  {
16017 +    UBICOM32_INSN_COMPATIBILITY_MULU_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_DATA_REG, "compatibility-mulu-s1-indirect-with-post-increment-2-dsp-src2-data-reg", "mulu", 32,
16018 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
16019 +  },
16020 +/* mulu ${s1-i4-2}(${s1-An})++,${dsp-S2-data-reg} */
16021 +  {
16022 +    UBICOM32_INSN_COMPATIBILITY_MULU_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_DATA_REG, "compatibility-mulu-s1-indirect-with-pre-increment-2-dsp-src2-data-reg", "mulu", 32,
16023 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
16024 +  },
16025 +/* mulu ${s1-direct-addr},#${bit5} */
16026 +  {
16027 +    UBICOM32_INSN_COMPATIBILITY_MULU_S1_DIRECT_DSP_IMM_BIT5, "compatibility-mulu-s1-direct-dsp-imm-bit5", "mulu", 32,
16028 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
16029 +  },
16030 +/* mulu #${s1-imm8},#${bit5} */
16031 +  {
16032 +    UBICOM32_INSN_COMPATIBILITY_MULU_S1_IMMEDIATE_DSP_IMM_BIT5, "compatibility-mulu-s1-immediate-dsp-imm-bit5", "mulu", 32,
16033 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
16034 +  },
16035 +/* mulu (${s1-An},${s1-r}),#${bit5} */
16036 +  {
16037 +    UBICOM32_INSN_COMPATIBILITY_MULU_S1_INDIRECT_WITH_INDEX_2_DSP_IMM_BIT5, "compatibility-mulu-s1-indirect-with-index-2-dsp-imm-bit5", "mulu", 32,
16038 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
16039 +  },
16040 +/* mulu ${s1-imm7-2}(${s1-An}),#${bit5} */
16041 +  {
16042 +    UBICOM32_INSN_COMPATIBILITY_MULU_S1_INDIRECT_WITH_OFFSET_2_DSP_IMM_BIT5, "compatibility-mulu-s1-indirect-with-offset-2-dsp-imm-bit5", "mulu", 32,
16043 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
16044 +  },
16045 +/* mulu (${s1-An}),#${bit5} */
16046 +  {
16047 +    UBICOM32_INSN_COMPATIBILITY_MULU_S1_INDIRECT_2_DSP_IMM_BIT5, "compatibility-mulu-s1-indirect-2-dsp-imm-bit5", "mulu", 32,
16048 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
16049 +  },
16050 +/* mulu (${s1-An})${s1-i4-2}++,#${bit5} */
16051 +  {
16052 +    UBICOM32_INSN_COMPATIBILITY_MULU_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_IMM_BIT5, "compatibility-mulu-s1-indirect-with-post-increment-2-dsp-imm-bit5", "mulu", 32,
16053 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
16054 +  },
16055 +/* mulu ${s1-i4-2}(${s1-An})++,#${bit5} */
16056 +  {
16057 +    UBICOM32_INSN_COMPATIBILITY_MULU_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_IMM_BIT5, "compatibility-mulu-s1-indirect-with-pre-increment-2-dsp-imm-bit5", "mulu", 32,
16058 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
16059 +  },
16060 +/* mulu ${s1-direct-addr},#${bit5} */
16061 +  {
16062 +    UBICOM32_INSN_MULU_S1_DIRECT_IMM_BIT5, "mulu-s1-direct-imm-bit5", "mulu", 32,
16063 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
16064 +  },
16065 +/* mulu #${s1-imm8},#${bit5} */
16066 +  {
16067 +    UBICOM32_INSN_MULU_S1_IMMEDIATE_IMM_BIT5, "mulu-s1-immediate-imm-bit5", "mulu", 32,
16068 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
16069 +  },
16070 +/* mulu (${s1-An},${s1-r}),#${bit5} */
16071 +  {
16072 +    UBICOM32_INSN_MULU_S1_INDIRECT_WITH_INDEX_2_IMM_BIT5, "mulu-s1-indirect-with-index-2-imm-bit5", "mulu", 32,
16073 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
16074 +  },
16075 +/* mulu ${s1-imm7-2}(${s1-An}),#${bit5} */
16076 +  {
16077 +    UBICOM32_INSN_MULU_S1_INDIRECT_WITH_OFFSET_2_IMM_BIT5, "mulu-s1-indirect-with-offset-2-imm-bit5", "mulu", 32,
16078 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
16079 +  },
16080 +/* mulu (${s1-An}),#${bit5} */
16081 +  {
16082 +    UBICOM32_INSN_MULU_S1_INDIRECT_2_IMM_BIT5, "mulu-s1-indirect-2-imm-bit5", "mulu", 32,
16083 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
16084 +  },
16085 +/* mulu (${s1-An})${s1-i4-2}++,#${bit5} */
16086 +  {
16087 +    UBICOM32_INSN_MULU_S1_INDIRECT_WITH_POST_INCREMENT_2_IMM_BIT5, "mulu-s1-indirect-with-post-increment-2-imm-bit5", "mulu", 32,
16088 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
16089 +  },
16090 +/* mulu ${s1-i4-2}(${s1-An})++,#${bit5} */
16091 +  {
16092 +    UBICOM32_INSN_MULU_S1_INDIRECT_WITH_PRE_INCREMENT_2_IMM_BIT5, "mulu-s1-indirect-with-pre-increment-2-imm-bit5", "mulu", 32,
16093 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
16094 +  },
16095 +/* mulu ${s1-direct-addr},${s2} */
16096 +  {
16097 +    UBICOM32_INSN_MULU_S1_DIRECT_DYN_REG, "mulu-s1-direct-dyn-reg", "mulu", 32,
16098 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
16099 +  },
16100 +/* mulu #${s1-imm8},${s2} */
16101 +  {
16102 +    UBICOM32_INSN_MULU_S1_IMMEDIATE_DYN_REG, "mulu-s1-immediate-dyn-reg", "mulu", 32,
16103 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
16104 +  },
16105 +/* mulu (${s1-An},${s1-r}),${s2} */
16106 +  {
16107 +    UBICOM32_INSN_MULU_S1_INDIRECT_WITH_INDEX_2_DYN_REG, "mulu-s1-indirect-with-index-2-dyn-reg", "mulu", 32,
16108 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
16109 +  },
16110 +/* mulu ${s1-imm7-2}(${s1-An}),${s2} */
16111 +  {
16112 +    UBICOM32_INSN_MULU_S1_INDIRECT_WITH_OFFSET_2_DYN_REG, "mulu-s1-indirect-with-offset-2-dyn-reg", "mulu", 32,
16113 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
16114 +  },
16115 +/* mulu (${s1-An}),${s2} */
16116 +  {
16117 +    UBICOM32_INSN_MULU_S1_INDIRECT_2_DYN_REG, "mulu-s1-indirect-2-dyn-reg", "mulu", 32,
16118 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
16119 +  },
16120 +/* mulu (${s1-An})${s1-i4-2}++,${s2} */
16121 +  {
16122 +    UBICOM32_INSN_MULU_S1_INDIRECT_WITH_POST_INCREMENT_2_DYN_REG, "mulu-s1-indirect-with-post-increment-2-dyn-reg", "mulu", 32,
16123 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
16124 +  },
16125 +/* mulu ${s1-i4-2}(${s1-An})++,${s2} */
16126 +  {
16127 +    UBICOM32_INSN_MULU_S1_INDIRECT_WITH_PRE_INCREMENT_2_DYN_REG, "mulu-s1-indirect-with-pre-increment-2-dyn-reg", "mulu", 32,
16128 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
16129 +  },
16130 +/* muls ${s1-direct-addr},${dsp-S2-data-reg} */
16131 +  {
16132 +    UBICOM32_INSN_COMPATIBILITY_MULS_S1_DIRECT_DSP_SRC2_DATA_REG, "compatibility-muls-s1-direct-dsp-src2-data-reg", "muls", 32,
16133 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
16134 +  },
16135 +/* muls #${s1-imm8},${dsp-S2-data-reg} */
16136 +  {
16137 +    UBICOM32_INSN_COMPATIBILITY_MULS_S1_IMMEDIATE_DSP_SRC2_DATA_REG, "compatibility-muls-s1-immediate-dsp-src2-data-reg", "muls", 32,
16138 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
16139 +  },
16140 +/* muls (${s1-An},${s1-r}),${dsp-S2-data-reg} */
16141 +  {
16142 +    UBICOM32_INSN_COMPATIBILITY_MULS_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_DATA_REG, "compatibility-muls-s1-indirect-with-index-2-dsp-src2-data-reg", "muls", 32,
16143 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
16144 +  },
16145 +/* muls ${s1-imm7-2}(${s1-An}),${dsp-S2-data-reg} */
16146 +  {
16147 +    UBICOM32_INSN_COMPATIBILITY_MULS_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_DATA_REG, "compatibility-muls-s1-indirect-with-offset-2-dsp-src2-data-reg", "muls", 32,
16148 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
16149 +  },
16150 +/* muls (${s1-An}),${dsp-S2-data-reg} */
16151 +  {
16152 +    UBICOM32_INSN_COMPATIBILITY_MULS_S1_INDIRECT_2_DSP_SRC2_DATA_REG, "compatibility-muls-s1-indirect-2-dsp-src2-data-reg", "muls", 32,
16153 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
16154 +  },
16155 +/* muls (${s1-An})${s1-i4-2}++,${dsp-S2-data-reg} */
16156 +  {
16157 +    UBICOM32_INSN_COMPATIBILITY_MULS_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_DATA_REG, "compatibility-muls-s1-indirect-with-post-increment-2-dsp-src2-data-reg", "muls", 32,
16158 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
16159 +  },
16160 +/* muls ${s1-i4-2}(${s1-An})++,${dsp-S2-data-reg} */
16161 +  {
16162 +    UBICOM32_INSN_COMPATIBILITY_MULS_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_DATA_REG, "compatibility-muls-s1-indirect-with-pre-increment-2-dsp-src2-data-reg", "muls", 32,
16163 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
16164 +  },
16165 +/* muls ${s1-direct-addr},#${bit5} */
16166 +  {
16167 +    UBICOM32_INSN_COMPATIBILITY_MULS_S1_DIRECT_DSP_IMM_BIT5, "compatibility-muls-s1-direct-dsp-imm-bit5", "muls", 32,
16168 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
16169 +  },
16170 +/* muls #${s1-imm8},#${bit5} */
16171 +  {
16172 +    UBICOM32_INSN_COMPATIBILITY_MULS_S1_IMMEDIATE_DSP_IMM_BIT5, "compatibility-muls-s1-immediate-dsp-imm-bit5", "muls", 32,
16173 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
16174 +  },
16175 +/* muls (${s1-An},${s1-r}),#${bit5} */
16176 +  {
16177 +    UBICOM32_INSN_COMPATIBILITY_MULS_S1_INDIRECT_WITH_INDEX_2_DSP_IMM_BIT5, "compatibility-muls-s1-indirect-with-index-2-dsp-imm-bit5", "muls", 32,
16178 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
16179 +  },
16180 +/* muls ${s1-imm7-2}(${s1-An}),#${bit5} */
16181 +  {
16182 +    UBICOM32_INSN_COMPATIBILITY_MULS_S1_INDIRECT_WITH_OFFSET_2_DSP_IMM_BIT5, "compatibility-muls-s1-indirect-with-offset-2-dsp-imm-bit5", "muls", 32,
16183 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
16184 +  },
16185 +/* muls (${s1-An}),#${bit5} */
16186 +  {
16187 +    UBICOM32_INSN_COMPATIBILITY_MULS_S1_INDIRECT_2_DSP_IMM_BIT5, "compatibility-muls-s1-indirect-2-dsp-imm-bit5", "muls", 32,
16188 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
16189 +  },
16190 +/* muls (${s1-An})${s1-i4-2}++,#${bit5} */
16191 +  {
16192 +    UBICOM32_INSN_COMPATIBILITY_MULS_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_IMM_BIT5, "compatibility-muls-s1-indirect-with-post-increment-2-dsp-imm-bit5", "muls", 32,
16193 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
16194 +  },
16195 +/* muls ${s1-i4-2}(${s1-An})++,#${bit5} */
16196 +  {
16197 +    UBICOM32_INSN_COMPATIBILITY_MULS_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_IMM_BIT5, "compatibility-muls-s1-indirect-with-pre-increment-2-dsp-imm-bit5", "muls", 32,
16198 +    { 0, { { { (1<<MACH_IP3023COMPATIBILITY), 0 } } } }
16199 +  },
16200 +/* muls ${s1-direct-addr},#${bit5} */
16201 +  {
16202 +    UBICOM32_INSN_MULS_S1_DIRECT_IMM_BIT5, "muls-s1-direct-imm-bit5", "muls", 32,
16203 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
16204 +  },
16205 +/* muls #${s1-imm8},#${bit5} */
16206 +  {
16207 +    UBICOM32_INSN_MULS_S1_IMMEDIATE_IMM_BIT5, "muls-s1-immediate-imm-bit5", "muls", 32,
16208 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
16209 +  },
16210 +/* muls (${s1-An},${s1-r}),#${bit5} */
16211 +  {
16212 +    UBICOM32_INSN_MULS_S1_INDIRECT_WITH_INDEX_2_IMM_BIT5, "muls-s1-indirect-with-index-2-imm-bit5", "muls", 32,
16213 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
16214 +  },
16215 +/* muls ${s1-imm7-2}(${s1-An}),#${bit5} */
16216 +  {
16217 +    UBICOM32_INSN_MULS_S1_INDIRECT_WITH_OFFSET_2_IMM_BIT5, "muls-s1-indirect-with-offset-2-imm-bit5", "muls", 32,
16218 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
16219 +  },
16220 +/* muls (${s1-An}),#${bit5} */
16221 +  {
16222 +    UBICOM32_INSN_MULS_S1_INDIRECT_2_IMM_BIT5, "muls-s1-indirect-2-imm-bit5", "muls", 32,
16223 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
16224 +  },
16225 +/* muls (${s1-An})${s1-i4-2}++,#${bit5} */
16226 +  {
16227 +    UBICOM32_INSN_MULS_S1_INDIRECT_WITH_POST_INCREMENT_2_IMM_BIT5, "muls-s1-indirect-with-post-increment-2-imm-bit5", "muls", 32,
16228 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
16229 +  },
16230 +/* muls ${s1-i4-2}(${s1-An})++,#${bit5} */
16231 +  {
16232 +    UBICOM32_INSN_MULS_S1_INDIRECT_WITH_PRE_INCREMENT_2_IMM_BIT5, "muls-s1-indirect-with-pre-increment-2-imm-bit5", "muls", 32,
16233 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
16234 +  },
16235 +/* muls ${s1-direct-addr},${s2} */
16236 +  {
16237 +    UBICOM32_INSN_MULS_S1_DIRECT_DYN_REG, "muls-s1-direct-dyn-reg", "muls", 32,
16238 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
16239 +  },
16240 +/* muls #${s1-imm8},${s2} */
16241 +  {
16242 +    UBICOM32_INSN_MULS_S1_IMMEDIATE_DYN_REG, "muls-s1-immediate-dyn-reg", "muls", 32,
16243 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
16244 +  },
16245 +/* muls (${s1-An},${s1-r}),${s2} */
16246 +  {
16247 +    UBICOM32_INSN_MULS_S1_INDIRECT_WITH_INDEX_2_DYN_REG, "muls-s1-indirect-with-index-2-dyn-reg", "muls", 32,
16248 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
16249 +  },
16250 +/* muls ${s1-imm7-2}(${s1-An}),${s2} */
16251 +  {
16252 +    UBICOM32_INSN_MULS_S1_INDIRECT_WITH_OFFSET_2_DYN_REG, "muls-s1-indirect-with-offset-2-dyn-reg", "muls", 32,
16253 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
16254 +  },
16255 +/* muls (${s1-An}),${s2} */
16256 +  {
16257 +    UBICOM32_INSN_MULS_S1_INDIRECT_2_DYN_REG, "muls-s1-indirect-2-dyn-reg", "muls", 32,
16258 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
16259 +  },
16260 +/* muls (${s1-An})${s1-i4-2}++,${s2} */
16261 +  {
16262 +    UBICOM32_INSN_MULS_S1_INDIRECT_WITH_POST_INCREMENT_2_DYN_REG, "muls-s1-indirect-with-post-increment-2-dyn-reg", "muls", 32,
16263 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
16264 +  },
16265 +/* muls ${s1-i4-2}(${s1-An})++,${s2} */
16266 +  {
16267 +    UBICOM32_INSN_MULS_S1_INDIRECT_WITH_PRE_INCREMENT_2_DYN_REG, "muls-s1-indirect-with-pre-increment-2-dyn-reg", "muls", 32,
16268 +    { 0, { { { (1<<MACH_IP3035), 0 } } } }
16269 +  },
16270 +/* swapb.4 ${d-direct-addr},${s1-direct-addr} */
16271 +  {
16272 +    UBICOM32_INSN_SWAPB_4_D_DIRECT_S1_DIRECT, "swapb.4-d-direct-s1-direct", "swapb.4", 32,
16273 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16274 +  },
16275 +/* swapb.4 #${d-imm8},${s1-direct-addr} */
16276 +  {
16277 +    UBICOM32_INSN_SWAPB_4_D_IMMEDIATE_4_S1_DIRECT, "swapb.4-d-immediate-4-s1-direct", "swapb.4", 32,
16278 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16279 +  },
16280 +/* swapb.4 (${d-An},${d-r}),${s1-direct-addr} */
16281 +  {
16282 +    UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_INDEX_4_S1_DIRECT, "swapb.4-d-indirect-with-index-4-s1-direct", "swapb.4", 32,
16283 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16284 +  },
16285 +/* swapb.4 ${d-imm7-4}(${d-An}),${s1-direct-addr} */
16286 +  {
16287 +    UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_OFFSET_4_S1_DIRECT, "swapb.4-d-indirect-with-offset-4-s1-direct", "swapb.4", 32,
16288 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16289 +  },
16290 +/* swapb.4 (${d-An}),${s1-direct-addr} */
16291 +  {
16292 +    UBICOM32_INSN_SWAPB_4_D_INDIRECT_4_S1_DIRECT, "swapb.4-d-indirect-4-s1-direct", "swapb.4", 32,
16293 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16294 +  },
16295 +/* swapb.4 (${d-An})${d-i4-4}++,${s1-direct-addr} */
16296 +  {
16297 +    UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_DIRECT, "swapb.4-d-indirect-with-post-increment-4-s1-direct", "swapb.4", 32,
16298 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16299 +  },
16300 +/* swapb.4 ${d-i4-4}(${d-An})++,${s1-direct-addr} */
16301 +  {
16302 +    UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_DIRECT, "swapb.4-d-indirect-with-pre-increment-4-s1-direct", "swapb.4", 32,
16303 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16304 +  },
16305 +/* swapb.4 ${d-direct-addr},#${s1-imm8} */
16306 +  {
16307 +    UBICOM32_INSN_SWAPB_4_D_DIRECT_S1_IMMEDIATE, "swapb.4-d-direct-s1-immediate", "swapb.4", 32,
16308 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16309 +  },
16310 +/* swapb.4 #${d-imm8},#${s1-imm8} */
16311 +  {
16312 +    UBICOM32_INSN_SWAPB_4_D_IMMEDIATE_4_S1_IMMEDIATE, "swapb.4-d-immediate-4-s1-immediate", "swapb.4", 32,
16313 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16314 +  },
16315 +/* swapb.4 (${d-An},${d-r}),#${s1-imm8} */
16316 +  {
16317 +    UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_INDEX_4_S1_IMMEDIATE, "swapb.4-d-indirect-with-index-4-s1-immediate", "swapb.4", 32,
16318 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16319 +  },
16320 +/* swapb.4 ${d-imm7-4}(${d-An}),#${s1-imm8} */
16321 +  {
16322 +    UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_OFFSET_4_S1_IMMEDIATE, "swapb.4-d-indirect-with-offset-4-s1-immediate", "swapb.4", 32,
16323 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16324 +  },
16325 +/* swapb.4 (${d-An}),#${s1-imm8} */
16326 +  {
16327 +    UBICOM32_INSN_SWAPB_4_D_INDIRECT_4_S1_IMMEDIATE, "swapb.4-d-indirect-4-s1-immediate", "swapb.4", 32,
16328 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16329 +  },
16330 +/* swapb.4 (${d-An})${d-i4-4}++,#${s1-imm8} */
16331 +  {
16332 +    UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_IMMEDIATE, "swapb.4-d-indirect-with-post-increment-4-s1-immediate", "swapb.4", 32,
16333 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16334 +  },
16335 +/* swapb.4 ${d-i4-4}(${d-An})++,#${s1-imm8} */
16336 +  {
16337 +    UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_IMMEDIATE, "swapb.4-d-indirect-with-pre-increment-4-s1-immediate", "swapb.4", 32,
16338 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16339 +  },
16340 +/* swapb.4 ${d-direct-addr},(${s1-An},${s1-r}) */
16341 +  {
16342 +    UBICOM32_INSN_SWAPB_4_D_DIRECT_S1_INDIRECT_WITH_INDEX_4, "swapb.4-d-direct-s1-indirect-with-index-4", "swapb.4", 32,
16343 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16344 +  },
16345 +/* swapb.4 #${d-imm8},(${s1-An},${s1-r}) */
16346 +  {
16347 +    UBICOM32_INSN_SWAPB_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_INDEX_4, "swapb.4-d-immediate-4-s1-indirect-with-index-4", "swapb.4", 32,
16348 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16349 +  },
16350 +/* swapb.4 (${d-An},${d-r}),(${s1-An},${s1-r}) */
16351 +  {
16352 +    UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_INDEX_4, "swapb.4-d-indirect-with-index-4-s1-indirect-with-index-4", "swapb.4", 32,
16353 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16354 +  },
16355 +/* swapb.4 ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}) */
16356 +  {
16357 +    UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_INDEX_4, "swapb.4-d-indirect-with-offset-4-s1-indirect-with-index-4", "swapb.4", 32,
16358 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16359 +  },
16360 +/* swapb.4 (${d-An}),(${s1-An},${s1-r}) */
16361 +  {
16362 +    UBICOM32_INSN_SWAPB_4_D_INDIRECT_4_S1_INDIRECT_WITH_INDEX_4, "swapb.4-d-indirect-4-s1-indirect-with-index-4", "swapb.4", 32,
16363 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16364 +  },
16365 +/* swapb.4 (${d-An})${d-i4-4}++,(${s1-An},${s1-r}) */
16366 +  {
16367 +    UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, "swapb.4-d-indirect-with-post-increment-4-s1-indirect-with-index-4", "swapb.4", 32,
16368 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16369 +  },
16370 +/* swapb.4 ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}) */
16371 +  {
16372 +    UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, "swapb.4-d-indirect-with-pre-increment-4-s1-indirect-with-index-4", "swapb.4", 32,
16373 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16374 +  },
16375 +/* swapb.4 ${d-direct-addr},${s1-imm7-4}(${s1-An}) */
16376 +  {
16377 +    UBICOM32_INSN_SWAPB_4_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4, "swapb.4-d-direct-s1-indirect-with-offset-4", "swapb.4", 32,
16378 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16379 +  },
16380 +/* swapb.4 #${d-imm8},${s1-imm7-4}(${s1-An}) */
16381 +  {
16382 +    UBICOM32_INSN_SWAPB_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_OFFSET_4, "swapb.4-d-immediate-4-s1-indirect-with-offset-4", "swapb.4", 32,
16383 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16384 +  },
16385 +/* swapb.4 (${d-An},${d-r}),${s1-imm7-4}(${s1-An}) */
16386 +  {
16387 +    UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_OFFSET_4, "swapb.4-d-indirect-with-index-4-s1-indirect-with-offset-4", "swapb.4", 32,
16388 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16389 +  },
16390 +/* swapb.4 ${d-imm7-4}(${d-An}),${s1-imm7-4}(${s1-An}) */
16391 +  {
16392 +    UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_OFFSET_4, "swapb.4-d-indirect-with-offset-4-s1-indirect-with-offset-4", "swapb.4", 32,
16393 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16394 +  },
16395 +/* swapb.4 (${d-An}),${s1-imm7-4}(${s1-An}) */
16396 +  {
16397 +    UBICOM32_INSN_SWAPB_4_D_INDIRECT_4_S1_INDIRECT_WITH_OFFSET_4, "swapb.4-d-indirect-4-s1-indirect-with-offset-4", "swapb.4", 32,
16398 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16399 +  },
16400 +/* swapb.4 (${d-An})${d-i4-4}++,${s1-imm7-4}(${s1-An}) */
16401 +  {
16402 +    UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, "swapb.4-d-indirect-with-post-increment-4-s1-indirect-with-offset-4", "swapb.4", 32,
16403 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16404 +  },
16405 +/* swapb.4 ${d-i4-4}(${d-An})++,${s1-imm7-4}(${s1-An}) */
16406 +  {
16407 +    UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, "swapb.4-d-indirect-with-pre-increment-4-s1-indirect-with-offset-4", "swapb.4", 32,
16408 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16409 +  },
16410 +/* swapb.4 ${d-direct-addr},(${s1-An}) */
16411 +  {
16412 +    UBICOM32_INSN_SWAPB_4_D_DIRECT_S1_INDIRECT_4, "swapb.4-d-direct-s1-indirect-4", "swapb.4", 32,
16413 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16414 +  },
16415 +/* swapb.4 #${d-imm8},(${s1-An}) */
16416 +  {
16417 +    UBICOM32_INSN_SWAPB_4_D_IMMEDIATE_4_S1_INDIRECT_4, "swapb.4-d-immediate-4-s1-indirect-4", "swapb.4", 32,
16418 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16419 +  },
16420 +/* swapb.4 (${d-An},${d-r}),(${s1-An}) */
16421 +  {
16422 +    UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_4, "swapb.4-d-indirect-with-index-4-s1-indirect-4", "swapb.4", 32,
16423 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16424 +  },
16425 +/* swapb.4 ${d-imm7-4}(${d-An}),(${s1-An}) */
16426 +  {
16427 +    UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_4, "swapb.4-d-indirect-with-offset-4-s1-indirect-4", "swapb.4", 32,
16428 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16429 +  },
16430 +/* swapb.4 (${d-An}),(${s1-An}) */
16431 +  {
16432 +    UBICOM32_INSN_SWAPB_4_D_INDIRECT_4_S1_INDIRECT_4, "swapb.4-d-indirect-4-s1-indirect-4", "swapb.4", 32,
16433 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16434 +  },
16435 +/* swapb.4 (${d-An})${d-i4-4}++,(${s1-An}) */
16436 +  {
16437 +    UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_4, "swapb.4-d-indirect-with-post-increment-4-s1-indirect-4", "swapb.4", 32,
16438 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16439 +  },
16440 +/* swapb.4 ${d-i4-4}(${d-An})++,(${s1-An}) */
16441 +  {
16442 +    UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_4, "swapb.4-d-indirect-with-pre-increment-4-s1-indirect-4", "swapb.4", 32,
16443 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16444 +  },
16445 +/* swapb.4 ${d-direct-addr},(${s1-An})${s1-i4-4}++ */
16446 +  {
16447 +    UBICOM32_INSN_SWAPB_4_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4, "swapb.4-d-direct-s1-indirect-with-post-increment-4", "swapb.4", 32,
16448 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16449 +  },
16450 +/* swapb.4 #${d-imm8},(${s1-An})${s1-i4-4}++ */
16451 +  {
16452 +    UBICOM32_INSN_SWAPB_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "swapb.4-d-immediate-4-s1-indirect-with-post-increment-4", "swapb.4", 32,
16453 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16454 +  },
16455 +/* swapb.4 (${d-An},${d-r}),(${s1-An})${s1-i4-4}++ */
16456 +  {
16457 +    UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "swapb.4-d-indirect-with-index-4-s1-indirect-with-post-increment-4", "swapb.4", 32,
16458 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16459 +  },
16460 +/* swapb.4 ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-4}++ */
16461 +  {
16462 +    UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "swapb.4-d-indirect-with-offset-4-s1-indirect-with-post-increment-4", "swapb.4", 32,
16463 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16464 +  },
16465 +/* swapb.4 (${d-An}),(${s1-An})${s1-i4-4}++ */
16466 +  {
16467 +    UBICOM32_INSN_SWAPB_4_D_INDIRECT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "swapb.4-d-indirect-4-s1-indirect-with-post-increment-4", "swapb.4", 32,
16468 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16469 +  },
16470 +/* swapb.4 (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-4}++ */
16471 +  {
16472 +    UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "swapb.4-d-indirect-with-post-increment-4-s1-indirect-with-post-increment-4", "swapb.4", 32,
16473 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16474 +  },
16475 +/* swapb.4 ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-4}++ */
16476 +  {
16477 +    UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "swapb.4-d-indirect-with-pre-increment-4-s1-indirect-with-post-increment-4", "swapb.4", 32,
16478 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16479 +  },
16480 +/* swapb.4 ${d-direct-addr},${s1-i4-4}(${s1-An})++ */
16481 +  {
16482 +    UBICOM32_INSN_SWAPB_4_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4, "swapb.4-d-direct-s1-indirect-with-pre-increment-4", "swapb.4", 32,
16483 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16484 +  },
16485 +/* swapb.4 #${d-imm8},${s1-i4-4}(${s1-An})++ */
16486 +  {
16487 +    UBICOM32_INSN_SWAPB_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "swapb.4-d-immediate-4-s1-indirect-with-pre-increment-4", "swapb.4", 32,
16488 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16489 +  },
16490 +/* swapb.4 (${d-An},${d-r}),${s1-i4-4}(${s1-An})++ */
16491 +  {
16492 +    UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "swapb.4-d-indirect-with-index-4-s1-indirect-with-pre-increment-4", "swapb.4", 32,
16493 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16494 +  },
16495 +/* swapb.4 ${d-imm7-4}(${d-An}),${s1-i4-4}(${s1-An})++ */
16496 +  {
16497 +    UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "swapb.4-d-indirect-with-offset-4-s1-indirect-with-pre-increment-4", "swapb.4", 32,
16498 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16499 +  },
16500 +/* swapb.4 (${d-An}),${s1-i4-4}(${s1-An})++ */
16501 +  {
16502 +    UBICOM32_INSN_SWAPB_4_D_INDIRECT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "swapb.4-d-indirect-4-s1-indirect-with-pre-increment-4", "swapb.4", 32,
16503 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16504 +  },
16505 +/* swapb.4 (${d-An})${d-i4-4}++,${s1-i4-4}(${s1-An})++ */
16506 +  {
16507 +    UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "swapb.4-d-indirect-with-post-increment-4-s1-indirect-with-pre-increment-4", "swapb.4", 32,
16508 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16509 +  },
16510 +/* swapb.4 ${d-i4-4}(${d-An})++,${s1-i4-4}(${s1-An})++ */
16511 +  {
16512 +    UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "swapb.4-d-indirect-with-pre-increment-4-s1-indirect-with-pre-increment-4", "swapb.4", 32,
16513 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16514 +  },
16515 +/* swapb.2 ${d-direct-addr},${s1-direct-addr} */
16516 +  {
16517 +    UBICOM32_INSN_SWAPB_2_D_DIRECT_S1_DIRECT, "swapb.2-d-direct-s1-direct", "swapb.2", 32,
16518 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16519 +  },
16520 +/* swapb.2 #${d-imm8},${s1-direct-addr} */
16521 +  {
16522 +    UBICOM32_INSN_SWAPB_2_D_IMMEDIATE_2_S1_DIRECT, "swapb.2-d-immediate-2-s1-direct", "swapb.2", 32,
16523 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16524 +  },
16525 +/* swapb.2 (${d-An},${d-r}),${s1-direct-addr} */
16526 +  {
16527 +    UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_INDEX_2_S1_DIRECT, "swapb.2-d-indirect-with-index-2-s1-direct", "swapb.2", 32,
16528 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16529 +  },
16530 +/* swapb.2 ${d-imm7-2}(${d-An}),${s1-direct-addr} */
16531 +  {
16532 +    UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_OFFSET_2_S1_DIRECT, "swapb.2-d-indirect-with-offset-2-s1-direct", "swapb.2", 32,
16533 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16534 +  },
16535 +/* swapb.2 (${d-An}),${s1-direct-addr} */
16536 +  {
16537 +    UBICOM32_INSN_SWAPB_2_D_INDIRECT_2_S1_DIRECT, "swapb.2-d-indirect-2-s1-direct", "swapb.2", 32,
16538 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16539 +  },
16540 +/* swapb.2 (${d-An})${d-i4-2}++,${s1-direct-addr} */
16541 +  {
16542 +    UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_DIRECT, "swapb.2-d-indirect-with-post-increment-2-s1-direct", "swapb.2", 32,
16543 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16544 +  },
16545 +/* swapb.2 ${d-i4-2}(${d-An})++,${s1-direct-addr} */
16546 +  {
16547 +    UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_DIRECT, "swapb.2-d-indirect-with-pre-increment-2-s1-direct", "swapb.2", 32,
16548 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16549 +  },
16550 +/* swapb.2 ${d-direct-addr},#${s1-imm8} */
16551 +  {
16552 +    UBICOM32_INSN_SWAPB_2_D_DIRECT_S1_IMMEDIATE, "swapb.2-d-direct-s1-immediate", "swapb.2", 32,
16553 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16554 +  },
16555 +/* swapb.2 #${d-imm8},#${s1-imm8} */
16556 +  {
16557 +    UBICOM32_INSN_SWAPB_2_D_IMMEDIATE_2_S1_IMMEDIATE, "swapb.2-d-immediate-2-s1-immediate", "swapb.2", 32,
16558 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16559 +  },
16560 +/* swapb.2 (${d-An},${d-r}),#${s1-imm8} */
16561 +  {
16562 +    UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_INDEX_2_S1_IMMEDIATE, "swapb.2-d-indirect-with-index-2-s1-immediate", "swapb.2", 32,
16563 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16564 +  },
16565 +/* swapb.2 ${d-imm7-2}(${d-An}),#${s1-imm8} */
16566 +  {
16567 +    UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_OFFSET_2_S1_IMMEDIATE, "swapb.2-d-indirect-with-offset-2-s1-immediate", "swapb.2", 32,
16568 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16569 +  },
16570 +/* swapb.2 (${d-An}),#${s1-imm8} */
16571 +  {
16572 +    UBICOM32_INSN_SWAPB_2_D_INDIRECT_2_S1_IMMEDIATE, "swapb.2-d-indirect-2-s1-immediate", "swapb.2", 32,
16573 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16574 +  },
16575 +/* swapb.2 (${d-An})${d-i4-2}++,#${s1-imm8} */
16576 +  {
16577 +    UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_IMMEDIATE, "swapb.2-d-indirect-with-post-increment-2-s1-immediate", "swapb.2", 32,
16578 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16579 +  },
16580 +/* swapb.2 ${d-i4-2}(${d-An})++,#${s1-imm8} */
16581 +  {
16582 +    UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_IMMEDIATE, "swapb.2-d-indirect-with-pre-increment-2-s1-immediate", "swapb.2", 32,
16583 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16584 +  },
16585 +/* swapb.2 ${d-direct-addr},(${s1-An},${s1-r}) */
16586 +  {
16587 +    UBICOM32_INSN_SWAPB_2_D_DIRECT_S1_INDIRECT_WITH_INDEX_2, "swapb.2-d-direct-s1-indirect-with-index-2", "swapb.2", 32,
16588 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16589 +  },
16590 +/* swapb.2 #${d-imm8},(${s1-An},${s1-r}) */
16591 +  {
16592 +    UBICOM32_INSN_SWAPB_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_INDEX_2, "swapb.2-d-immediate-2-s1-indirect-with-index-2", "swapb.2", 32,
16593 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16594 +  },
16595 +/* swapb.2 (${d-An},${d-r}),(${s1-An},${s1-r}) */
16596 +  {
16597 +    UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_INDEX_2, "swapb.2-d-indirect-with-index-2-s1-indirect-with-index-2", "swapb.2", 32,
16598 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16599 +  },
16600 +/* swapb.2 ${d-imm7-2}(${d-An}),(${s1-An},${s1-r}) */
16601 +  {
16602 +    UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_INDEX_2, "swapb.2-d-indirect-with-offset-2-s1-indirect-with-index-2", "swapb.2", 32,
16603 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16604 +  },
16605 +/* swapb.2 (${d-An}),(${s1-An},${s1-r}) */
16606 +  {
16607 +    UBICOM32_INSN_SWAPB_2_D_INDIRECT_2_S1_INDIRECT_WITH_INDEX_2, "swapb.2-d-indirect-2-s1-indirect-with-index-2", "swapb.2", 32,
16608 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16609 +  },
16610 +/* swapb.2 (${d-An})${d-i4-2}++,(${s1-An},${s1-r}) */
16611 +  {
16612 +    UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_INDEX_2, "swapb.2-d-indirect-with-post-increment-2-s1-indirect-with-index-2", "swapb.2", 32,
16613 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16614 +  },
16615 +/* swapb.2 ${d-i4-2}(${d-An})++,(${s1-An},${s1-r}) */
16616 +  {
16617 +    UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_INDEX_2, "swapb.2-d-indirect-with-pre-increment-2-s1-indirect-with-index-2", "swapb.2", 32,
16618 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16619 +  },
16620 +/* swapb.2 ${d-direct-addr},${s1-imm7-2}(${s1-An}) */
16621 +  {
16622 +    UBICOM32_INSN_SWAPB_2_D_DIRECT_S1_INDIRECT_WITH_OFFSET_2, "swapb.2-d-direct-s1-indirect-with-offset-2", "swapb.2", 32,
16623 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16624 +  },
16625 +/* swapb.2 #${d-imm8},${s1-imm7-2}(${s1-An}) */
16626 +  {
16627 +    UBICOM32_INSN_SWAPB_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_OFFSET_2, "swapb.2-d-immediate-2-s1-indirect-with-offset-2", "swapb.2", 32,
16628 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16629 +  },
16630 +/* swapb.2 (${d-An},${d-r}),${s1-imm7-2}(${s1-An}) */
16631 +  {
16632 +    UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_OFFSET_2, "swapb.2-d-indirect-with-index-2-s1-indirect-with-offset-2", "swapb.2", 32,
16633 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16634 +  },
16635 +/* swapb.2 ${d-imm7-2}(${d-An}),${s1-imm7-2}(${s1-An}) */
16636 +  {
16637 +    UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_OFFSET_2, "swapb.2-d-indirect-with-offset-2-s1-indirect-with-offset-2", "swapb.2", 32,
16638 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16639 +  },
16640 +/* swapb.2 (${d-An}),${s1-imm7-2}(${s1-An}) */
16641 +  {
16642 +    UBICOM32_INSN_SWAPB_2_D_INDIRECT_2_S1_INDIRECT_WITH_OFFSET_2, "swapb.2-d-indirect-2-s1-indirect-with-offset-2", "swapb.2", 32,
16643 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16644 +  },
16645 +/* swapb.2 (${d-An})${d-i4-2}++,${s1-imm7-2}(${s1-An}) */
16646 +  {
16647 +    UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_2, "swapb.2-d-indirect-with-post-increment-2-s1-indirect-with-offset-2", "swapb.2", 32,
16648 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16649 +  },
16650 +/* swapb.2 ${d-i4-2}(${d-An})++,${s1-imm7-2}(${s1-An}) */
16651 +  {
16652 +    UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_2, "swapb.2-d-indirect-with-pre-increment-2-s1-indirect-with-offset-2", "swapb.2", 32,
16653 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16654 +  },
16655 +/* swapb.2 ${d-direct-addr},(${s1-An}) */
16656 +  {
16657 +    UBICOM32_INSN_SWAPB_2_D_DIRECT_S1_INDIRECT_2, "swapb.2-d-direct-s1-indirect-2", "swapb.2", 32,
16658 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16659 +  },
16660 +/* swapb.2 #${d-imm8},(${s1-An}) */
16661 +  {
16662 +    UBICOM32_INSN_SWAPB_2_D_IMMEDIATE_2_S1_INDIRECT_2, "swapb.2-d-immediate-2-s1-indirect-2", "swapb.2", 32,
16663 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16664 +  },
16665 +/* swapb.2 (${d-An},${d-r}),(${s1-An}) */
16666 +  {
16667 +    UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_2, "swapb.2-d-indirect-with-index-2-s1-indirect-2", "swapb.2", 32,
16668 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16669 +  },
16670 +/* swapb.2 ${d-imm7-2}(${d-An}),(${s1-An}) */
16671 +  {
16672 +    UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_2, "swapb.2-d-indirect-with-offset-2-s1-indirect-2", "swapb.2", 32,
16673 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16674 +  },
16675 +/* swapb.2 (${d-An}),(${s1-An}) */
16676 +  {
16677 +    UBICOM32_INSN_SWAPB_2_D_INDIRECT_2_S1_INDIRECT_2, "swapb.2-d-indirect-2-s1-indirect-2", "swapb.2", 32,
16678 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16679 +  },
16680 +/* swapb.2 (${d-An})${d-i4-2}++,(${s1-An}) */
16681 +  {
16682 +    UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_2, "swapb.2-d-indirect-with-post-increment-2-s1-indirect-2", "swapb.2", 32,
16683 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16684 +  },
16685 +/* swapb.2 ${d-i4-2}(${d-An})++,(${s1-An}) */
16686 +  {
16687 +    UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_2, "swapb.2-d-indirect-with-pre-increment-2-s1-indirect-2", "swapb.2", 32,
16688 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16689 +  },
16690 +/* swapb.2 ${d-direct-addr},(${s1-An})${s1-i4-2}++ */
16691 +  {
16692 +    UBICOM32_INSN_SWAPB_2_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_2, "swapb.2-d-direct-s1-indirect-with-post-increment-2", "swapb.2", 32,
16693 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16694 +  },
16695 +/* swapb.2 #${d-imm8},(${s1-An})${s1-i4-2}++ */
16696 +  {
16697 +    UBICOM32_INSN_SWAPB_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_POST_INCREMENT_2, "swapb.2-d-immediate-2-s1-indirect-with-post-increment-2", "swapb.2", 32,
16698 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16699 +  },
16700 +/* swapb.2 (${d-An},${d-r}),(${s1-An})${s1-i4-2}++ */
16701 +  {
16702 +    UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_POST_INCREMENT_2, "swapb.2-d-indirect-with-index-2-s1-indirect-with-post-increment-2", "swapb.2", 32,
16703 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16704 +  },
16705 +/* swapb.2 ${d-imm7-2}(${d-An}),(${s1-An})${s1-i4-2}++ */
16706 +  {
16707 +    UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_POST_INCREMENT_2, "swapb.2-d-indirect-with-offset-2-s1-indirect-with-post-increment-2", "swapb.2", 32,
16708 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16709 +  },
16710 +/* swapb.2 (${d-An}),(${s1-An})${s1-i4-2}++ */
16711 +  {
16712 +    UBICOM32_INSN_SWAPB_2_D_INDIRECT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, "swapb.2-d-indirect-2-s1-indirect-with-post-increment-2", "swapb.2", 32,
16713 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16714 +  },
16715 +/* swapb.2 (${d-An})${d-i4-2}++,(${s1-An})${s1-i4-2}++ */
16716 +  {
16717 +    UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, "swapb.2-d-indirect-with-post-increment-2-s1-indirect-with-post-increment-2", "swapb.2", 32,
16718 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16719 +  },
16720 +/* swapb.2 ${d-i4-2}(${d-An})++,(${s1-An})${s1-i4-2}++ */
16721 +  {
16722 +    UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, "swapb.2-d-indirect-with-pre-increment-2-s1-indirect-with-post-increment-2", "swapb.2", 32,
16723 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16724 +  },
16725 +/* swapb.2 ${d-direct-addr},${s1-i4-2}(${s1-An})++ */
16726 +  {
16727 +    UBICOM32_INSN_SWAPB_2_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_2, "swapb.2-d-direct-s1-indirect-with-pre-increment-2", "swapb.2", 32,
16728 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16729 +  },
16730 +/* swapb.2 #${d-imm8},${s1-i4-2}(${s1-An})++ */
16731 +  {
16732 +    UBICOM32_INSN_SWAPB_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, "swapb.2-d-immediate-2-s1-indirect-with-pre-increment-2", "swapb.2", 32,
16733 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16734 +  },
16735 +/* swapb.2 (${d-An},${d-r}),${s1-i4-2}(${s1-An})++ */
16736 +  {
16737 +    UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, "swapb.2-d-indirect-with-index-2-s1-indirect-with-pre-increment-2", "swapb.2", 32,
16738 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16739 +  },
16740 +/* swapb.2 ${d-imm7-2}(${d-An}),${s1-i4-2}(${s1-An})++ */
16741 +  {
16742 +    UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, "swapb.2-d-indirect-with-offset-2-s1-indirect-with-pre-increment-2", "swapb.2", 32,
16743 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16744 +  },
16745 +/* swapb.2 (${d-An}),${s1-i4-2}(${s1-An})++ */
16746 +  {
16747 +    UBICOM32_INSN_SWAPB_2_D_INDIRECT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, "swapb.2-d-indirect-2-s1-indirect-with-pre-increment-2", "swapb.2", 32,
16748 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16749 +  },
16750 +/* swapb.2 (${d-An})${d-i4-2}++,${s1-i4-2}(${s1-An})++ */
16751 +  {
16752 +    UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, "swapb.2-d-indirect-with-post-increment-2-s1-indirect-with-pre-increment-2", "swapb.2", 32,
16753 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16754 +  },
16755 +/* swapb.2 ${d-i4-2}(${d-An})++,${s1-i4-2}(${s1-An})++ */
16756 +  {
16757 +    UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, "swapb.2-d-indirect-with-pre-increment-2-s1-indirect-with-pre-increment-2", "swapb.2", 32,
16758 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
16759 +  },
16760 +/* pdec ${d-direct-addr},${pdec-s1-imm7-4}(${s1-An}) */
16761 +  {
16762 +    UBICOM32_INSN_PDEC_D_DIRECT_PDEC_S1_EA_INDIRECT_WITH_OFFSET_4, "pdec-d-direct-pdec-s1-ea-indirect-with-offset-4", "pdec", 32,
16763 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
16764 +  },
16765 +/* pdec #${d-imm8},${pdec-s1-imm7-4}(${s1-An}) */
16766 +  {
16767 +    UBICOM32_INSN_PDEC_D_IMMEDIATE_4_PDEC_S1_EA_INDIRECT_WITH_OFFSET_4, "pdec-d-immediate-4-pdec-s1-ea-indirect-with-offset-4", "pdec", 32,
16768 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
16769 +  },
16770 +/* pdec (${d-An},${d-r}),${pdec-s1-imm7-4}(${s1-An}) */
16771 +  {
16772 +    UBICOM32_INSN_PDEC_D_INDIRECT_WITH_INDEX_4_PDEC_S1_EA_INDIRECT_WITH_OFFSET_4, "pdec-d-indirect-with-index-4-pdec-s1-ea-indirect-with-offset-4", "pdec", 32,
16773 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
16774 +  },
16775 +/* pdec ${d-imm7-4}(${d-An}),${pdec-s1-imm7-4}(${s1-An}) */
16776 +  {
16777 +    UBICOM32_INSN_PDEC_D_INDIRECT_WITH_OFFSET_4_PDEC_S1_EA_INDIRECT_WITH_OFFSET_4, "pdec-d-indirect-with-offset-4-pdec-s1-ea-indirect-with-offset-4", "pdec", 32,
16778 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
16779 +  },
16780 +/* pdec (${d-An}),${pdec-s1-imm7-4}(${s1-An}) */
16781 +  {
16782 +    UBICOM32_INSN_PDEC_D_INDIRECT_4_PDEC_S1_EA_INDIRECT_WITH_OFFSET_4, "pdec-d-indirect-4-pdec-s1-ea-indirect-with-offset-4", "pdec", 32,
16783 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
16784 +  },
16785 +/* pdec (${d-An})${d-i4-4}++,${pdec-s1-imm7-4}(${s1-An}) */
16786 +  {
16787 +    UBICOM32_INSN_PDEC_D_INDIRECT_WITH_POST_INCREMENT_4_PDEC_S1_EA_INDIRECT_WITH_OFFSET_4, "pdec-d-indirect-with-post-increment-4-pdec-s1-ea-indirect-with-offset-4", "pdec", 32,
16788 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
16789 +  },
16790 +/* pdec ${d-i4-4}(${d-An})++,${pdec-s1-imm7-4}(${s1-An}) */
16791 +  {
16792 +    UBICOM32_INSN_PDEC_D_INDIRECT_WITH_PRE_INCREMENT_4_PDEC_S1_EA_INDIRECT_WITH_OFFSET_4, "pdec-d-indirect-with-pre-increment-4-pdec-s1-ea-indirect-with-offset-4", "pdec", 32,
16793 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
16794 +  },
16795 +/* lea.4 ${d-direct-addr},(${s1-An}) */
16796 +  {
16797 +    UBICOM32_INSN_LEA_4_D_DIRECT_S1_EA_INDIRECT, "lea.4-d-direct-s1-ea-indirect", "lea.4", 32,
16798 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
16799 +  },
16800 +/* lea.4 #${d-imm8},(${s1-An}) */
16801 +  {
16802 +    UBICOM32_INSN_LEA_4_D_IMMEDIATE_4_S1_EA_INDIRECT, "lea.4-d-immediate-4-s1-ea-indirect", "lea.4", 32,
16803 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
16804 +  },
16805 +/* lea.4 (${d-An},${d-r}),(${s1-An}) */
16806 +  {
16807 +    UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_INDEX_4_S1_EA_INDIRECT, "lea.4-d-indirect-with-index-4-s1-ea-indirect", "lea.4", 32,
16808 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
16809 +  },
16810 +/* lea.4 ${d-imm7-4}(${d-An}),(${s1-An}) */
16811 +  {
16812 +    UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_OFFSET_4_S1_EA_INDIRECT, "lea.4-d-indirect-with-offset-4-s1-ea-indirect", "lea.4", 32,
16813 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
16814 +  },
16815 +/* lea.4 (${d-An}),(${s1-An}) */
16816 +  {
16817 +    UBICOM32_INSN_LEA_4_D_INDIRECT_4_S1_EA_INDIRECT, "lea.4-d-indirect-4-s1-ea-indirect", "lea.4", 32,
16818 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
16819 +  },
16820 +/* lea.4 (${d-An})${d-i4-4}++,(${s1-An}) */
16821 +  {
16822 +    UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_EA_INDIRECT, "lea.4-d-indirect-with-post-increment-4-s1-ea-indirect", "lea.4", 32,
16823 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
16824 +  },
16825 +/* lea.4 ${d-i4-4}(${d-An})++,(${s1-An}) */
16826 +  {
16827 +    UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_EA_INDIRECT, "lea.4-d-indirect-with-pre-increment-4-s1-ea-indirect", "lea.4", 32,
16828 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
16829 +  },
16830 +/* lea.4 ${d-direct-addr},${s1-imm7-4}(${s1-An}) */
16831 +  {
16832 +    UBICOM32_INSN_LEA_4_D_DIRECT_S1_EA_INDIRECT_WITH_OFFSET_4, "lea.4-d-direct-s1-ea-indirect-with-offset-4", "lea.4", 32,
16833 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
16834 +  },
16835 +/* lea.4 #${d-imm8},${s1-imm7-4}(${s1-An}) */
16836 +  {
16837 +    UBICOM32_INSN_LEA_4_D_IMMEDIATE_4_S1_EA_INDIRECT_WITH_OFFSET_4, "lea.4-d-immediate-4-s1-ea-indirect-with-offset-4", "lea.4", 32,
16838 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
16839 +  },
16840 +/* lea.4 (${d-An},${d-r}),${s1-imm7-4}(${s1-An}) */
16841 +  {
16842 +    UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_INDEX_4_S1_EA_INDIRECT_WITH_OFFSET_4, "lea.4-d-indirect-with-index-4-s1-ea-indirect-with-offset-4", "lea.4", 32,
16843 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
16844 +  },
16845 +/* lea.4 ${d-imm7-4}(${d-An}),${s1-imm7-4}(${s1-An}) */
16846 +  {
16847 +    UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_OFFSET_4_S1_EA_INDIRECT_WITH_OFFSET_4, "lea.4-d-indirect-with-offset-4-s1-ea-indirect-with-offset-4", "lea.4", 32,
16848 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
16849 +  },
16850 +/* lea.4 (${d-An}),${s1-imm7-4}(${s1-An}) */
16851 +  {
16852 +    UBICOM32_INSN_LEA_4_D_INDIRECT_4_S1_EA_INDIRECT_WITH_OFFSET_4, "lea.4-d-indirect-4-s1-ea-indirect-with-offset-4", "lea.4", 32,
16853 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
16854 +  },
16855 +/* lea.4 (${d-An})${d-i4-4}++,${s1-imm7-4}(${s1-An}) */
16856 +  {
16857 +    UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_EA_INDIRECT_WITH_OFFSET_4, "lea.4-d-indirect-with-post-increment-4-s1-ea-indirect-with-offset-4", "lea.4", 32,
16858 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
16859 +  },
16860 +/* lea.4 ${d-i4-4}(${d-An})++,${s1-imm7-4}(${s1-An}) */
16861 +  {
16862 +    UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_EA_INDIRECT_WITH_OFFSET_4, "lea.4-d-indirect-with-pre-increment-4-s1-ea-indirect-with-offset-4", "lea.4", 32,
16863 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
16864 +  },
16865 +/* lea.4 ${d-direct-addr},(${s1-An},${s1-r}) */
16866 +  {
16867 +    UBICOM32_INSN_LEA_4_D_DIRECT_S1_EA_INDIRECT_WITH_INDEX_4, "lea.4-d-direct-s1-ea-indirect-with-index-4", "lea.4", 32,
16868 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
16869 +  },
16870 +/* lea.4 #${d-imm8},(${s1-An},${s1-r}) */
16871 +  {
16872 +    UBICOM32_INSN_LEA_4_D_IMMEDIATE_4_S1_EA_INDIRECT_WITH_INDEX_4, "lea.4-d-immediate-4-s1-ea-indirect-with-index-4", "lea.4", 32,
16873 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
16874 +  },
16875 +/* lea.4 (${d-An},${d-r}),(${s1-An},${s1-r}) */
16876 +  {
16877 +    UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_INDEX_4_S1_EA_INDIRECT_WITH_INDEX_4, "lea.4-d-indirect-with-index-4-s1-ea-indirect-with-index-4", "lea.4", 32,
16878 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
16879 +  },
16880 +/* lea.4 ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}) */
16881 +  {
16882 +    UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_OFFSET_4_S1_EA_INDIRECT_WITH_INDEX_4, "lea.4-d-indirect-with-offset-4-s1-ea-indirect-with-index-4", "lea.4", 32,
16883 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
16884 +  },
16885 +/* lea.4 (${d-An}),(${s1-An},${s1-r}) */
16886 +  {
16887 +    UBICOM32_INSN_LEA_4_D_INDIRECT_4_S1_EA_INDIRECT_WITH_INDEX_4, "lea.4-d-indirect-4-s1-ea-indirect-with-index-4", "lea.4", 32,
16888 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
16889 +  },
16890 +/* lea.4 (${d-An})${d-i4-4}++,(${s1-An},${s1-r}) */
16891 +  {
16892 +    UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_EA_INDIRECT_WITH_INDEX_4, "lea.4-d-indirect-with-post-increment-4-s1-ea-indirect-with-index-4", "lea.4", 32,
16893 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
16894 +  },
16895 +/* lea.4 ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}) */
16896 +  {
16897 +    UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_EA_INDIRECT_WITH_INDEX_4, "lea.4-d-indirect-with-pre-increment-4-s1-ea-indirect-with-index-4", "lea.4", 32,
16898 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
16899 +  },
16900 +/* lea.4 ${d-direct-addr},(${s1-An})${s1-i4-4}++ */
16901 +  {
16902 +    UBICOM32_INSN_LEA_4_D_DIRECT_S1_EA_INDIRECT_WITH_POST_INCREMENT_4, "lea.4-d-direct-s1-ea-indirect-with-post-increment-4", "lea.4", 32,
16903 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
16904 +  },
16905 +/* lea.4 #${d-imm8},(${s1-An})${s1-i4-4}++ */
16906 +  {
16907 +    UBICOM32_INSN_LEA_4_D_IMMEDIATE_4_S1_EA_INDIRECT_WITH_POST_INCREMENT_4, "lea.4-d-immediate-4-s1-ea-indirect-with-post-increment-4", "lea.4", 32,
16908 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
16909 +  },
16910 +/* lea.4 (${d-An},${d-r}),(${s1-An})${s1-i4-4}++ */
16911 +  {
16912 +    UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_INDEX_4_S1_EA_INDIRECT_WITH_POST_INCREMENT_4, "lea.4-d-indirect-with-index-4-s1-ea-indirect-with-post-increment-4", "lea.4", 32,
16913 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
16914 +  },
16915 +/* lea.4 ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-4}++ */
16916 +  {
16917 +    UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_OFFSET_4_S1_EA_INDIRECT_WITH_POST_INCREMENT_4, "lea.4-d-indirect-with-offset-4-s1-ea-indirect-with-post-increment-4", "lea.4", 32,
16918 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
16919 +  },
16920 +/* lea.4 (${d-An}),(${s1-An})${s1-i4-4}++ */
16921 +  {
16922 +    UBICOM32_INSN_LEA_4_D_INDIRECT_4_S1_EA_INDIRECT_WITH_POST_INCREMENT_4, "lea.4-d-indirect-4-s1-ea-indirect-with-post-increment-4", "lea.4", 32,
16923 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
16924 +  },
16925 +/* lea.4 (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-4}++ */
16926 +  {
16927 +    UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_EA_INDIRECT_WITH_POST_INCREMENT_4, "lea.4-d-indirect-with-post-increment-4-s1-ea-indirect-with-post-increment-4", "lea.4", 32,
16928 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
16929 +  },
16930 +/* lea.4 ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-4}++ */
16931 +  {
16932 +    UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_EA_INDIRECT_WITH_POST_INCREMENT_4, "lea.4-d-indirect-with-pre-increment-4-s1-ea-indirect-with-post-increment-4", "lea.4", 32,
16933 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
16934 +  },
16935 +/* lea.4 ${d-direct-addr},${s1-i4-4}(${s1-An})++ */
16936 +  {
16937 +    UBICOM32_INSN_LEA_4_D_DIRECT_S1_EA_INDIRECT_WITH_PRE_INCREMENT_4, "lea.4-d-direct-s1-ea-indirect-with-pre-increment-4", "lea.4", 32,
16938 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
16939 +  },
16940 +/* lea.4 #${d-imm8},${s1-i4-4}(${s1-An})++ */
16941 +  {
16942 +    UBICOM32_INSN_LEA_4_D_IMMEDIATE_4_S1_EA_INDIRECT_WITH_PRE_INCREMENT_4, "lea.4-d-immediate-4-s1-ea-indirect-with-pre-increment-4", "lea.4", 32,
16943 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
16944 +  },
16945 +/* lea.4 (${d-An},${d-r}),${s1-i4-4}(${s1-An})++ */
16946 +  {
16947 +    UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_INDEX_4_S1_EA_INDIRECT_WITH_PRE_INCREMENT_4, "lea.4-d-indirect-with-index-4-s1-ea-indirect-with-pre-increment-4", "lea.4", 32,
16948 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
16949 +  },
16950 +/* lea.4 ${d-imm7-4}(${d-An}),${s1-i4-4}(${s1-An})++ */
16951 +  {
16952 +    UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_OFFSET_4_S1_EA_INDIRECT_WITH_PRE_INCREMENT_4, "lea.4-d-indirect-with-offset-4-s1-ea-indirect-with-pre-increment-4", "lea.4", 32,
16953 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
16954 +  },
16955 +/* lea.4 (${d-An}),${s1-i4-4}(${s1-An})++ */
16956 +  {
16957 +    UBICOM32_INSN_LEA_4_D_INDIRECT_4_S1_EA_INDIRECT_WITH_PRE_INCREMENT_4, "lea.4-d-indirect-4-s1-ea-indirect-with-pre-increment-4", "lea.4", 32,
16958 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
16959 +  },
16960 +/* lea.4 (${d-An})${d-i4-4}++,${s1-i4-4}(${s1-An})++ */
16961 +  {
16962 +    UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_EA_INDIRECT_WITH_PRE_INCREMENT_4, "lea.4-d-indirect-with-post-increment-4-s1-ea-indirect-with-pre-increment-4", "lea.4", 32,
16963 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
16964 +  },
16965 +/* lea.4 ${d-i4-4}(${d-An})++,${s1-i4-4}(${s1-An})++ */
16966 +  {
16967 +    UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_EA_INDIRECT_WITH_PRE_INCREMENT_4, "lea.4-d-indirect-with-pre-increment-4-s1-ea-indirect-with-pre-increment-4", "lea.4", 32,
16968 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
16969 +  },
16970 +/* lea.4 ${d-direct-addr},#${s1-imm8} */
16971 +  {
16972 +    UBICOM32_INSN_LEA_4_D_DIRECT_S1_EA_IMMEDIATE, "lea.4-d-direct-s1-ea-immediate", "lea.4", 32,
16973 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
16974 +  },
16975 +/* lea.4 #${d-imm8},#${s1-imm8} */
16976 +  {
16977 +    UBICOM32_INSN_LEA_4_D_IMMEDIATE_4_S1_EA_IMMEDIATE, "lea.4-d-immediate-4-s1-ea-immediate", "lea.4", 32,
16978 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
16979 +  },
16980 +/* lea.4 (${d-An},${d-r}),#${s1-imm8} */
16981 +  {
16982 +    UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_INDEX_4_S1_EA_IMMEDIATE, "lea.4-d-indirect-with-index-4-s1-ea-immediate", "lea.4", 32,
16983 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
16984 +  },
16985 +/* lea.4 ${d-imm7-4}(${d-An}),#${s1-imm8} */
16986 +  {
16987 +    UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_OFFSET_4_S1_EA_IMMEDIATE, "lea.4-d-indirect-with-offset-4-s1-ea-immediate", "lea.4", 32,
16988 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
16989 +  },
16990 +/* lea.4 (${d-An}),#${s1-imm8} */
16991 +  {
16992 +    UBICOM32_INSN_LEA_4_D_INDIRECT_4_S1_EA_IMMEDIATE, "lea.4-d-indirect-4-s1-ea-immediate", "lea.4", 32,
16993 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
16994 +  },
16995 +/* lea.4 (${d-An})${d-i4-4}++,#${s1-imm8} */
16996 +  {
16997 +    UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_EA_IMMEDIATE, "lea.4-d-indirect-with-post-increment-4-s1-ea-immediate", "lea.4", 32,
16998 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
16999 +  },
17000 +/* lea.4 ${d-i4-4}(${d-An})++,#${s1-imm8} */
17001 +  {
17002 +    UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_EA_IMMEDIATE, "lea.4-d-indirect-with-pre-increment-4-s1-ea-immediate", "lea.4", 32,
17003 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17004 +  },
17005 +/* lea.2 ${d-direct-addr},(${s1-An}) */
17006 +  {
17007 +    UBICOM32_INSN_LEA_2_D_DIRECT_S1_EA_INDIRECT, "lea.2-d-direct-s1-ea-indirect", "lea.2", 32,
17008 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17009 +  },
17010 +/* lea.2 #${d-imm8},(${s1-An}) */
17011 +  {
17012 +    UBICOM32_INSN_LEA_2_D_IMMEDIATE_4_S1_EA_INDIRECT, "lea.2-d-immediate-4-s1-ea-indirect", "lea.2", 32,
17013 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17014 +  },
17015 +/* lea.2 (${d-An},${d-r}),(${s1-An}) */
17016 +  {
17017 +    UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_INDEX_4_S1_EA_INDIRECT, "lea.2-d-indirect-with-index-4-s1-ea-indirect", "lea.2", 32,
17018 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17019 +  },
17020 +/* lea.2 ${d-imm7-4}(${d-An}),(${s1-An}) */
17021 +  {
17022 +    UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_OFFSET_4_S1_EA_INDIRECT, "lea.2-d-indirect-with-offset-4-s1-ea-indirect", "lea.2", 32,
17023 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17024 +  },
17025 +/* lea.2 (${d-An}),(${s1-An}) */
17026 +  {
17027 +    UBICOM32_INSN_LEA_2_D_INDIRECT_4_S1_EA_INDIRECT, "lea.2-d-indirect-4-s1-ea-indirect", "lea.2", 32,
17028 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17029 +  },
17030 +/* lea.2 (${d-An})${d-i4-4}++,(${s1-An}) */
17031 +  {
17032 +    UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_POST_INCREMENT_4_S1_EA_INDIRECT, "lea.2-d-indirect-with-post-increment-4-s1-ea-indirect", "lea.2", 32,
17033 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17034 +  },
17035 +/* lea.2 ${d-i4-4}(${d-An})++,(${s1-An}) */
17036 +  {
17037 +    UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_EA_INDIRECT, "lea.2-d-indirect-with-pre-increment-4-s1-ea-indirect", "lea.2", 32,
17038 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17039 +  },
17040 +/* lea.2 ${d-direct-addr},${s1-imm7-2}(${s1-An}) */
17041 +  {
17042 +    UBICOM32_INSN_LEA_2_D_DIRECT_S1_EA_INDIRECT_WITH_OFFSET_2, "lea.2-d-direct-s1-ea-indirect-with-offset-2", "lea.2", 32,
17043 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17044 +  },
17045 +/* lea.2 #${d-imm8},${s1-imm7-2}(${s1-An}) */
17046 +  {
17047 +    UBICOM32_INSN_LEA_2_D_IMMEDIATE_4_S1_EA_INDIRECT_WITH_OFFSET_2, "lea.2-d-immediate-4-s1-ea-indirect-with-offset-2", "lea.2", 32,
17048 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17049 +  },
17050 +/* lea.2 (${d-An},${d-r}),${s1-imm7-2}(${s1-An}) */
17051 +  {
17052 +    UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_INDEX_4_S1_EA_INDIRECT_WITH_OFFSET_2, "lea.2-d-indirect-with-index-4-s1-ea-indirect-with-offset-2", "lea.2", 32,
17053 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17054 +  },
17055 +/* lea.2 ${d-imm7-4}(${d-An}),${s1-imm7-2}(${s1-An}) */
17056 +  {
17057 +    UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_OFFSET_4_S1_EA_INDIRECT_WITH_OFFSET_2, "lea.2-d-indirect-with-offset-4-s1-ea-indirect-with-offset-2", "lea.2", 32,
17058 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17059 +  },
17060 +/* lea.2 (${d-An}),${s1-imm7-2}(${s1-An}) */
17061 +  {
17062 +    UBICOM32_INSN_LEA_2_D_INDIRECT_4_S1_EA_INDIRECT_WITH_OFFSET_2, "lea.2-d-indirect-4-s1-ea-indirect-with-offset-2", "lea.2", 32,
17063 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17064 +  },
17065 +/* lea.2 (${d-An})${d-i4-4}++,${s1-imm7-2}(${s1-An}) */
17066 +  {
17067 +    UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_POST_INCREMENT_4_S1_EA_INDIRECT_WITH_OFFSET_2, "lea.2-d-indirect-with-post-increment-4-s1-ea-indirect-with-offset-2", "lea.2", 32,
17068 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17069 +  },
17070 +/* lea.2 ${d-i4-4}(${d-An})++,${s1-imm7-2}(${s1-An}) */
17071 +  {
17072 +    UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_EA_INDIRECT_WITH_OFFSET_2, "lea.2-d-indirect-with-pre-increment-4-s1-ea-indirect-with-offset-2", "lea.2", 32,
17073 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17074 +  },
17075 +/* lea.2 ${d-direct-addr},(${s1-An},${s1-r}) */
17076 +  {
17077 +    UBICOM32_INSN_LEA_2_D_DIRECT_S1_EA_INDIRECT_WITH_INDEX_2, "lea.2-d-direct-s1-ea-indirect-with-index-2", "lea.2", 32,
17078 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17079 +  },
17080 +/* lea.2 #${d-imm8},(${s1-An},${s1-r}) */
17081 +  {
17082 +    UBICOM32_INSN_LEA_2_D_IMMEDIATE_4_S1_EA_INDIRECT_WITH_INDEX_2, "lea.2-d-immediate-4-s1-ea-indirect-with-index-2", "lea.2", 32,
17083 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17084 +  },
17085 +/* lea.2 (${d-An},${d-r}),(${s1-An},${s1-r}) */
17086 +  {
17087 +    UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_INDEX_4_S1_EA_INDIRECT_WITH_INDEX_2, "lea.2-d-indirect-with-index-4-s1-ea-indirect-with-index-2", "lea.2", 32,
17088 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17089 +  },
17090 +/* lea.2 ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}) */
17091 +  {
17092 +    UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_OFFSET_4_S1_EA_INDIRECT_WITH_INDEX_2, "lea.2-d-indirect-with-offset-4-s1-ea-indirect-with-index-2", "lea.2", 32,
17093 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17094 +  },
17095 +/* lea.2 (${d-An}),(${s1-An},${s1-r}) */
17096 +  {
17097 +    UBICOM32_INSN_LEA_2_D_INDIRECT_4_S1_EA_INDIRECT_WITH_INDEX_2, "lea.2-d-indirect-4-s1-ea-indirect-with-index-2", "lea.2", 32,
17098 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17099 +  },
17100 +/* lea.2 (${d-An})${d-i4-4}++,(${s1-An},${s1-r}) */
17101 +  {
17102 +    UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_POST_INCREMENT_4_S1_EA_INDIRECT_WITH_INDEX_2, "lea.2-d-indirect-with-post-increment-4-s1-ea-indirect-with-index-2", "lea.2", 32,
17103 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17104 +  },
17105 +/* lea.2 ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}) */
17106 +  {
17107 +    UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_EA_INDIRECT_WITH_INDEX_2, "lea.2-d-indirect-with-pre-increment-4-s1-ea-indirect-with-index-2", "lea.2", 32,
17108 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17109 +  },
17110 +/* lea.2 ${d-direct-addr},(${s1-An})${s1-i4-2}++ */
17111 +  {
17112 +    UBICOM32_INSN_LEA_2_D_DIRECT_S1_EA_INDIRECT_WITH_POST_INCREMENT_2, "lea.2-d-direct-s1-ea-indirect-with-post-increment-2", "lea.2", 32,
17113 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17114 +  },
17115 +/* lea.2 #${d-imm8},(${s1-An})${s1-i4-2}++ */
17116 +  {
17117 +    UBICOM32_INSN_LEA_2_D_IMMEDIATE_4_S1_EA_INDIRECT_WITH_POST_INCREMENT_2, "lea.2-d-immediate-4-s1-ea-indirect-with-post-increment-2", "lea.2", 32,
17118 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17119 +  },
17120 +/* lea.2 (${d-An},${d-r}),(${s1-An})${s1-i4-2}++ */
17121 +  {
17122 +    UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_INDEX_4_S1_EA_INDIRECT_WITH_POST_INCREMENT_2, "lea.2-d-indirect-with-index-4-s1-ea-indirect-with-post-increment-2", "lea.2", 32,
17123 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17124 +  },
17125 +/* lea.2 ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-2}++ */
17126 +  {
17127 +    UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_OFFSET_4_S1_EA_INDIRECT_WITH_POST_INCREMENT_2, "lea.2-d-indirect-with-offset-4-s1-ea-indirect-with-post-increment-2", "lea.2", 32,
17128 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17129 +  },
17130 +/* lea.2 (${d-An}),(${s1-An})${s1-i4-2}++ */
17131 +  {
17132 +    UBICOM32_INSN_LEA_2_D_INDIRECT_4_S1_EA_INDIRECT_WITH_POST_INCREMENT_2, "lea.2-d-indirect-4-s1-ea-indirect-with-post-increment-2", "lea.2", 32,
17133 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17134 +  },
17135 +/* lea.2 (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-2}++ */
17136 +  {
17137 +    UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_POST_INCREMENT_4_S1_EA_INDIRECT_WITH_POST_INCREMENT_2, "lea.2-d-indirect-with-post-increment-4-s1-ea-indirect-with-post-increment-2", "lea.2", 32,
17138 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17139 +  },
17140 +/* lea.2 ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-2}++ */
17141 +  {
17142 +    UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_EA_INDIRECT_WITH_POST_INCREMENT_2, "lea.2-d-indirect-with-pre-increment-4-s1-ea-indirect-with-post-increment-2", "lea.2", 32,
17143 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17144 +  },
17145 +/* lea.2 ${d-direct-addr},${s1-i4-2}(${s1-An})++ */
17146 +  {
17147 +    UBICOM32_INSN_LEA_2_D_DIRECT_S1_EA_INDIRECT_WITH_PRE_INCREMENT_2, "lea.2-d-direct-s1-ea-indirect-with-pre-increment-2", "lea.2", 32,
17148 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17149 +  },
17150 +/* lea.2 #${d-imm8},${s1-i4-2}(${s1-An})++ */
17151 +  {
17152 +    UBICOM32_INSN_LEA_2_D_IMMEDIATE_4_S1_EA_INDIRECT_WITH_PRE_INCREMENT_2, "lea.2-d-immediate-4-s1-ea-indirect-with-pre-increment-2", "lea.2", 32,
17153 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17154 +  },
17155 +/* lea.2 (${d-An},${d-r}),${s1-i4-2}(${s1-An})++ */
17156 +  {
17157 +    UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_INDEX_4_S1_EA_INDIRECT_WITH_PRE_INCREMENT_2, "lea.2-d-indirect-with-index-4-s1-ea-indirect-with-pre-increment-2", "lea.2", 32,
17158 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17159 +  },
17160 +/* lea.2 ${d-imm7-4}(${d-An}),${s1-i4-2}(${s1-An})++ */
17161 +  {
17162 +    UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_OFFSET_4_S1_EA_INDIRECT_WITH_PRE_INCREMENT_2, "lea.2-d-indirect-with-offset-4-s1-ea-indirect-with-pre-increment-2", "lea.2", 32,
17163 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17164 +  },
17165 +/* lea.2 (${d-An}),${s1-i4-2}(${s1-An})++ */
17166 +  {
17167 +    UBICOM32_INSN_LEA_2_D_INDIRECT_4_S1_EA_INDIRECT_WITH_PRE_INCREMENT_2, "lea.2-d-indirect-4-s1-ea-indirect-with-pre-increment-2", "lea.2", 32,
17168 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17169 +  },
17170 +/* lea.2 (${d-An})${d-i4-4}++,${s1-i4-2}(${s1-An})++ */
17171 +  {
17172 +    UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_POST_INCREMENT_4_S1_EA_INDIRECT_WITH_PRE_INCREMENT_2, "lea.2-d-indirect-with-post-increment-4-s1-ea-indirect-with-pre-increment-2", "lea.2", 32,
17173 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17174 +  },
17175 +/* lea.2 ${d-i4-4}(${d-An})++,${s1-i4-2}(${s1-An})++ */
17176 +  {
17177 +    UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_EA_INDIRECT_WITH_PRE_INCREMENT_2, "lea.2-d-indirect-with-pre-increment-4-s1-ea-indirect-with-pre-increment-2", "lea.2", 32,
17178 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17179 +  },
17180 +/* lea.2 ${d-direct-addr},#${s1-imm8} */
17181 +  {
17182 +    UBICOM32_INSN_LEA_2_D_DIRECT_S1_EA_IMMEDIATE, "lea.2-d-direct-s1-ea-immediate", "lea.2", 32,
17183 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17184 +  },
17185 +/* lea.2 #${d-imm8},#${s1-imm8} */
17186 +  {
17187 +    UBICOM32_INSN_LEA_2_D_IMMEDIATE_4_S1_EA_IMMEDIATE, "lea.2-d-immediate-4-s1-ea-immediate", "lea.2", 32,
17188 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17189 +  },
17190 +/* lea.2 (${d-An},${d-r}),#${s1-imm8} */
17191 +  {
17192 +    UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_INDEX_4_S1_EA_IMMEDIATE, "lea.2-d-indirect-with-index-4-s1-ea-immediate", "lea.2", 32,
17193 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17194 +  },
17195 +/* lea.2 ${d-imm7-4}(${d-An}),#${s1-imm8} */
17196 +  {
17197 +    UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_OFFSET_4_S1_EA_IMMEDIATE, "lea.2-d-indirect-with-offset-4-s1-ea-immediate", "lea.2", 32,
17198 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17199 +  },
17200 +/* lea.2 (${d-An}),#${s1-imm8} */
17201 +  {
17202 +    UBICOM32_INSN_LEA_2_D_INDIRECT_4_S1_EA_IMMEDIATE, "lea.2-d-indirect-4-s1-ea-immediate", "lea.2", 32,
17203 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17204 +  },
17205 +/* lea.2 (${d-An})${d-i4-4}++,#${s1-imm8} */
17206 +  {
17207 +    UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_POST_INCREMENT_4_S1_EA_IMMEDIATE, "lea.2-d-indirect-with-post-increment-4-s1-ea-immediate", "lea.2", 32,
17208 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17209 +  },
17210 +/* lea.2 ${d-i4-4}(${d-An})++,#${s1-imm8} */
17211 +  {
17212 +    UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_EA_IMMEDIATE, "lea.2-d-indirect-with-pre-increment-4-s1-ea-immediate", "lea.2", 32,
17213 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17214 +  },
17215 +/* lea.1 ${d-direct-addr},(${s1-An}) */
17216 +  {
17217 +    UBICOM32_INSN_LEA_1_D_DIRECT_S1_EA_INDIRECT, "lea.1-d-direct-s1-ea-indirect", "lea.1", 32,
17218 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17219 +  },
17220 +/* lea.1 #${d-imm8},(${s1-An}) */
17221 +  {
17222 +    UBICOM32_INSN_LEA_1_D_IMMEDIATE_4_S1_EA_INDIRECT, "lea.1-d-immediate-4-s1-ea-indirect", "lea.1", 32,
17223 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17224 +  },
17225 +/* lea.1 (${d-An},${d-r}),(${s1-An}) */
17226 +  {
17227 +    UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_INDEX_4_S1_EA_INDIRECT, "lea.1-d-indirect-with-index-4-s1-ea-indirect", "lea.1", 32,
17228 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17229 +  },
17230 +/* lea.1 ${d-imm7-4}(${d-An}),(${s1-An}) */
17231 +  {
17232 +    UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_OFFSET_4_S1_EA_INDIRECT, "lea.1-d-indirect-with-offset-4-s1-ea-indirect", "lea.1", 32,
17233 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17234 +  },
17235 +/* lea.1 (${d-An}),(${s1-An}) */
17236 +  {
17237 +    UBICOM32_INSN_LEA_1_D_INDIRECT_4_S1_EA_INDIRECT, "lea.1-d-indirect-4-s1-ea-indirect", "lea.1", 32,
17238 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17239 +  },
17240 +/* lea.1 (${d-An})${d-i4-4}++,(${s1-An}) */
17241 +  {
17242 +    UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_POST_INCREMENT_4_S1_EA_INDIRECT, "lea.1-d-indirect-with-post-increment-4-s1-ea-indirect", "lea.1", 32,
17243 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17244 +  },
17245 +/* lea.1 ${d-i4-4}(${d-An})++,(${s1-An}) */
17246 +  {
17247 +    UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_EA_INDIRECT, "lea.1-d-indirect-with-pre-increment-4-s1-ea-indirect", "lea.1", 32,
17248 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17249 +  },
17250 +/* lea.1 ${d-direct-addr},${s1-imm7-1}(${s1-An}) */
17251 +  {
17252 +    UBICOM32_INSN_LEA_1_D_DIRECT_S1_EA_INDIRECT_WITH_OFFSET_1, "lea.1-d-direct-s1-ea-indirect-with-offset-1", "lea.1", 32,
17253 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17254 +  },
17255 +/* lea.1 #${d-imm8},${s1-imm7-1}(${s1-An}) */
17256 +  {
17257 +    UBICOM32_INSN_LEA_1_D_IMMEDIATE_4_S1_EA_INDIRECT_WITH_OFFSET_1, "lea.1-d-immediate-4-s1-ea-indirect-with-offset-1", "lea.1", 32,
17258 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17259 +  },
17260 +/* lea.1 (${d-An},${d-r}),${s1-imm7-1}(${s1-An}) */
17261 +  {
17262 +    UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_INDEX_4_S1_EA_INDIRECT_WITH_OFFSET_1, "lea.1-d-indirect-with-index-4-s1-ea-indirect-with-offset-1", "lea.1", 32,
17263 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17264 +  },
17265 +/* lea.1 ${d-imm7-4}(${d-An}),${s1-imm7-1}(${s1-An}) */
17266 +  {
17267 +    UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_OFFSET_4_S1_EA_INDIRECT_WITH_OFFSET_1, "lea.1-d-indirect-with-offset-4-s1-ea-indirect-with-offset-1", "lea.1", 32,
17268 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17269 +  },
17270 +/* lea.1 (${d-An}),${s1-imm7-1}(${s1-An}) */
17271 +  {
17272 +    UBICOM32_INSN_LEA_1_D_INDIRECT_4_S1_EA_INDIRECT_WITH_OFFSET_1, "lea.1-d-indirect-4-s1-ea-indirect-with-offset-1", "lea.1", 32,
17273 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17274 +  },
17275 +/* lea.1 (${d-An})${d-i4-4}++,${s1-imm7-1}(${s1-An}) */
17276 +  {
17277 +    UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_POST_INCREMENT_4_S1_EA_INDIRECT_WITH_OFFSET_1, "lea.1-d-indirect-with-post-increment-4-s1-ea-indirect-with-offset-1", "lea.1", 32,
17278 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17279 +  },
17280 +/* lea.1 ${d-i4-4}(${d-An})++,${s1-imm7-1}(${s1-An}) */
17281 +  {
17282 +    UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_EA_INDIRECT_WITH_OFFSET_1, "lea.1-d-indirect-with-pre-increment-4-s1-ea-indirect-with-offset-1", "lea.1", 32,
17283 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17284 +  },
17285 +/* lea.1 ${d-direct-addr},(${s1-An},${s1-r}) */
17286 +  {
17287 +    UBICOM32_INSN_LEA_1_D_DIRECT_S1_EA_INDIRECT_WITH_INDEX_1, "lea.1-d-direct-s1-ea-indirect-with-index-1", "lea.1", 32,
17288 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17289 +  },
17290 +/* lea.1 #${d-imm8},(${s1-An},${s1-r}) */
17291 +  {
17292 +    UBICOM32_INSN_LEA_1_D_IMMEDIATE_4_S1_EA_INDIRECT_WITH_INDEX_1, "lea.1-d-immediate-4-s1-ea-indirect-with-index-1", "lea.1", 32,
17293 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17294 +  },
17295 +/* lea.1 (${d-An},${d-r}),(${s1-An},${s1-r}) */
17296 +  {
17297 +    UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_INDEX_4_S1_EA_INDIRECT_WITH_INDEX_1, "lea.1-d-indirect-with-index-4-s1-ea-indirect-with-index-1", "lea.1", 32,
17298 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17299 +  },
17300 +/* lea.1 ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}) */
17301 +  {
17302 +    UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_OFFSET_4_S1_EA_INDIRECT_WITH_INDEX_1, "lea.1-d-indirect-with-offset-4-s1-ea-indirect-with-index-1", "lea.1", 32,
17303 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17304 +  },
17305 +/* lea.1 (${d-An}),(${s1-An},${s1-r}) */
17306 +  {
17307 +    UBICOM32_INSN_LEA_1_D_INDIRECT_4_S1_EA_INDIRECT_WITH_INDEX_1, "lea.1-d-indirect-4-s1-ea-indirect-with-index-1", "lea.1", 32,
17308 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17309 +  },
17310 +/* lea.1 (${d-An})${d-i4-4}++,(${s1-An},${s1-r}) */
17311 +  {
17312 +    UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_POST_INCREMENT_4_S1_EA_INDIRECT_WITH_INDEX_1, "lea.1-d-indirect-with-post-increment-4-s1-ea-indirect-with-index-1", "lea.1", 32,
17313 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17314 +  },
17315 +/* lea.1 ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}) */
17316 +  {
17317 +    UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_EA_INDIRECT_WITH_INDEX_1, "lea.1-d-indirect-with-pre-increment-4-s1-ea-indirect-with-index-1", "lea.1", 32,
17318 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17319 +  },
17320 +/* lea.1 ${d-direct-addr},(${s1-An})${s1-i4-1}++ */
17321 +  {
17322 +    UBICOM32_INSN_LEA_1_D_DIRECT_S1_EA_INDIRECT_WITH_POST_INCREMENT_1, "lea.1-d-direct-s1-ea-indirect-with-post-increment-1", "lea.1", 32,
17323 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17324 +  },
17325 +/* lea.1 #${d-imm8},(${s1-An})${s1-i4-1}++ */
17326 +  {
17327 +    UBICOM32_INSN_LEA_1_D_IMMEDIATE_4_S1_EA_INDIRECT_WITH_POST_INCREMENT_1, "lea.1-d-immediate-4-s1-ea-indirect-with-post-increment-1", "lea.1", 32,
17328 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17329 +  },
17330 +/* lea.1 (${d-An},${d-r}),(${s1-An})${s1-i4-1}++ */
17331 +  {
17332 +    UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_INDEX_4_S1_EA_INDIRECT_WITH_POST_INCREMENT_1, "lea.1-d-indirect-with-index-4-s1-ea-indirect-with-post-increment-1", "lea.1", 32,
17333 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17334 +  },
17335 +/* lea.1 ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-1}++ */
17336 +  {
17337 +    UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_OFFSET_4_S1_EA_INDIRECT_WITH_POST_INCREMENT_1, "lea.1-d-indirect-with-offset-4-s1-ea-indirect-with-post-increment-1", "lea.1", 32,
17338 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17339 +  },
17340 +/* lea.1 (${d-An}),(${s1-An})${s1-i4-1}++ */
17341 +  {
17342 +    UBICOM32_INSN_LEA_1_D_INDIRECT_4_S1_EA_INDIRECT_WITH_POST_INCREMENT_1, "lea.1-d-indirect-4-s1-ea-indirect-with-post-increment-1", "lea.1", 32,
17343 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17344 +  },
17345 +/* lea.1 (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-1}++ */
17346 +  {
17347 +    UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_POST_INCREMENT_4_S1_EA_INDIRECT_WITH_POST_INCREMENT_1, "lea.1-d-indirect-with-post-increment-4-s1-ea-indirect-with-post-increment-1", "lea.1", 32,
17348 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17349 +  },
17350 +/* lea.1 ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-1}++ */
17351 +  {
17352 +    UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_EA_INDIRECT_WITH_POST_INCREMENT_1, "lea.1-d-indirect-with-pre-increment-4-s1-ea-indirect-with-post-increment-1", "lea.1", 32,
17353 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17354 +  },
17355 +/* lea.1 ${d-direct-addr},${s1-i4-1}(${s1-An})++ */
17356 +  {
17357 +    UBICOM32_INSN_LEA_1_D_DIRECT_S1_EA_INDIRECT_WITH_PRE_INCREMENT_1, "lea.1-d-direct-s1-ea-indirect-with-pre-increment-1", "lea.1", 32,
17358 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17359 +  },
17360 +/* lea.1 #${d-imm8},${s1-i4-1}(${s1-An})++ */
17361 +  {
17362 +    UBICOM32_INSN_LEA_1_D_IMMEDIATE_4_S1_EA_INDIRECT_WITH_PRE_INCREMENT_1, "lea.1-d-immediate-4-s1-ea-indirect-with-pre-increment-1", "lea.1", 32,
17363 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17364 +  },
17365 +/* lea.1 (${d-An},${d-r}),${s1-i4-1}(${s1-An})++ */
17366 +  {
17367 +    UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_INDEX_4_S1_EA_INDIRECT_WITH_PRE_INCREMENT_1, "lea.1-d-indirect-with-index-4-s1-ea-indirect-with-pre-increment-1", "lea.1", 32,
17368 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17369 +  },
17370 +/* lea.1 ${d-imm7-4}(${d-An}),${s1-i4-1}(${s1-An})++ */
17371 +  {
17372 +    UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_OFFSET_4_S1_EA_INDIRECT_WITH_PRE_INCREMENT_1, "lea.1-d-indirect-with-offset-4-s1-ea-indirect-with-pre-increment-1", "lea.1", 32,
17373 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17374 +  },
17375 +/* lea.1 (${d-An}),${s1-i4-1}(${s1-An})++ */
17376 +  {
17377 +    UBICOM32_INSN_LEA_1_D_INDIRECT_4_S1_EA_INDIRECT_WITH_PRE_INCREMENT_1, "lea.1-d-indirect-4-s1-ea-indirect-with-pre-increment-1", "lea.1", 32,
17378 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17379 +  },
17380 +/* lea.1 (${d-An})${d-i4-4}++,${s1-i4-1}(${s1-An})++ */
17381 +  {
17382 +    UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_POST_INCREMENT_4_S1_EA_INDIRECT_WITH_PRE_INCREMENT_1, "lea.1-d-indirect-with-post-increment-4-s1-ea-indirect-with-pre-increment-1", "lea.1", 32,
17383 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17384 +  },
17385 +/* lea.1 ${d-i4-4}(${d-An})++,${s1-i4-1}(${s1-An})++ */
17386 +  {
17387 +    UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_EA_INDIRECT_WITH_PRE_INCREMENT_1, "lea.1-d-indirect-with-pre-increment-4-s1-ea-indirect-with-pre-increment-1", "lea.1", 32,
17388 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17389 +  },
17390 +/* lea.1 ${d-direct-addr},#${s1-imm8} */
17391 +  {
17392 +    UBICOM32_INSN_LEA_1_D_DIRECT_S1_EA_IMMEDIATE, "lea.1-d-direct-s1-ea-immediate", "lea.1", 32,
17393 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17394 +  },
17395 +/* lea.1 #${d-imm8},#${s1-imm8} */
17396 +  {
17397 +    UBICOM32_INSN_LEA_1_D_IMMEDIATE_4_S1_EA_IMMEDIATE, "lea.1-d-immediate-4-s1-ea-immediate", "lea.1", 32,
17398 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17399 +  },
17400 +/* lea.1 (${d-An},${d-r}),#${s1-imm8} */
17401 +  {
17402 +    UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_INDEX_4_S1_EA_IMMEDIATE, "lea.1-d-indirect-with-index-4-s1-ea-immediate", "lea.1", 32,
17403 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17404 +  },
17405 +/* lea.1 ${d-imm7-4}(${d-An}),#${s1-imm8} */
17406 +  {
17407 +    UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_OFFSET_4_S1_EA_IMMEDIATE, "lea.1-d-indirect-with-offset-4-s1-ea-immediate", "lea.1", 32,
17408 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17409 +  },
17410 +/* lea.1 (${d-An}),#${s1-imm8} */
17411 +  {
17412 +    UBICOM32_INSN_LEA_1_D_INDIRECT_4_S1_EA_IMMEDIATE, "lea.1-d-indirect-4-s1-ea-immediate", "lea.1", 32,
17413 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17414 +  },
17415 +/* lea.1 (${d-An})${d-i4-4}++,#${s1-imm8} */
17416 +  {
17417 +    UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_POST_INCREMENT_4_S1_EA_IMMEDIATE, "lea.1-d-indirect-with-post-increment-4-s1-ea-immediate", "lea.1", 32,
17418 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17419 +  },
17420 +/* lea.1 ${d-i4-4}(${d-An})++,#${s1-imm8} */
17421 +  {
17422 +    UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_EA_IMMEDIATE, "lea.1-d-indirect-with-pre-increment-4-s1-ea-immediate", "lea.1", 32,
17423 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17424 +  },
17425 +/* cmpi ${s1-direct-addr},#${imm16-1} */
17426 +  {
17427 +    UBICOM32_INSN_CMPI_S1_DIRECT, "cmpi-s1-direct", "cmpi", 32,
17428 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17429 +  },
17430 +/* cmpi #${s1-imm8},#${imm16-1} */
17431 +  {
17432 +    UBICOM32_INSN_CMPI_S1_IMMEDIATE, "cmpi-s1-immediate", "cmpi", 32,
17433 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17434 +  },
17435 +/* cmpi (${s1-An},${s1-r}),#${imm16-1} */
17436 +  {
17437 +    UBICOM32_INSN_CMPI_S1_INDIRECT_WITH_INDEX_2, "cmpi-s1-indirect-with-index-2", "cmpi", 32,
17438 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17439 +  },
17440 +/* cmpi ${s1-imm7-2}(${s1-An}),#${imm16-1} */
17441 +  {
17442 +    UBICOM32_INSN_CMPI_S1_INDIRECT_WITH_OFFSET_2, "cmpi-s1-indirect-with-offset-2", "cmpi", 32,
17443 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17444 +  },
17445 +/* cmpi (${s1-An}),#${imm16-1} */
17446 +  {
17447 +    UBICOM32_INSN_CMPI_S1_INDIRECT_2, "cmpi-s1-indirect-2", "cmpi", 32,
17448 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17449 +  },
17450 +/* cmpi (${s1-An})${s1-i4-2}++,#${imm16-1} */
17451 +  {
17452 +    UBICOM32_INSN_CMPI_S1_INDIRECT_WITH_POST_INCREMENT_2, "cmpi-s1-indirect-with-post-increment-2", "cmpi", 32,
17453 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17454 +  },
17455 +/* cmpi ${s1-i4-2}(${s1-An})++,#${imm16-1} */
17456 +  {
17457 +    UBICOM32_INSN_CMPI_S1_INDIRECT_WITH_PRE_INCREMENT_2, "cmpi-s1-indirect-with-pre-increment-2", "cmpi", 32,
17458 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
17459 +  },
17460 +/* pxadds.u ${d-direct-addr},${s1-direct-addr},${s2} */
17461 +  {
17462 +    UBICOM32_INSN_PXADDS_U_D_DIRECT_S1_DIRECT, "pxadds.u-d-direct-s1-direct", "pxadds.u", 32,
17463 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17464 +  },
17465 +/* pxadds.u #${d-imm8},${s1-direct-addr},${s2} */
17466 +  {
17467 +    UBICOM32_INSN_PXADDS_U_D_IMMEDIATE_2_S1_DIRECT, "pxadds.u-d-immediate-2-s1-direct", "pxadds.u", 32,
17468 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17469 +  },
17470 +/* pxadds.u (${d-An},${d-r}),${s1-direct-addr},${s2} */
17471 +  {
17472 +    UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_INDEX_2_S1_DIRECT, "pxadds.u-d-indirect-with-index-2-s1-direct", "pxadds.u", 32,
17473 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17474 +  },
17475 +/* pxadds.u ${d-imm7-2}(${d-An}),${s1-direct-addr},${s2} */
17476 +  {
17477 +    UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_OFFSET_2_S1_DIRECT, "pxadds.u-d-indirect-with-offset-2-s1-direct", "pxadds.u", 32,
17478 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17479 +  },
17480 +/* pxadds.u (${d-An}),${s1-direct-addr},${s2} */
17481 +  {
17482 +    UBICOM32_INSN_PXADDS_U_D_INDIRECT_2_S1_DIRECT, "pxadds.u-d-indirect-2-s1-direct", "pxadds.u", 32,
17483 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17484 +  },
17485 +/* pxadds.u (${d-An})${d-i4-2}++,${s1-direct-addr},${s2} */
17486 +  {
17487 +    UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_POST_INCREMENT_2_S1_DIRECT, "pxadds.u-d-indirect-with-post-increment-2-s1-direct", "pxadds.u", 32,
17488 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17489 +  },
17490 +/* pxadds.u ${d-i4-2}(${d-An})++,${s1-direct-addr},${s2} */
17491 +  {
17492 +    UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_DIRECT, "pxadds.u-d-indirect-with-pre-increment-2-s1-direct", "pxadds.u", 32,
17493 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17494 +  },
17495 +/* pxadds.u ${d-direct-addr},#${s1-imm8},${s2} */
17496 +  {
17497 +    UBICOM32_INSN_PXADDS_U_D_DIRECT_S1_IMMEDIATE, "pxadds.u-d-direct-s1-immediate", "pxadds.u", 32,
17498 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17499 +  },
17500 +/* pxadds.u #${d-imm8},#${s1-imm8},${s2} */
17501 +  {
17502 +    UBICOM32_INSN_PXADDS_U_D_IMMEDIATE_2_S1_IMMEDIATE, "pxadds.u-d-immediate-2-s1-immediate", "pxadds.u", 32,
17503 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17504 +  },
17505 +/* pxadds.u (${d-An},${d-r}),#${s1-imm8},${s2} */
17506 +  {
17507 +    UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_INDEX_2_S1_IMMEDIATE, "pxadds.u-d-indirect-with-index-2-s1-immediate", "pxadds.u", 32,
17508 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17509 +  },
17510 +/* pxadds.u ${d-imm7-2}(${d-An}),#${s1-imm8},${s2} */
17511 +  {
17512 +    UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_OFFSET_2_S1_IMMEDIATE, "pxadds.u-d-indirect-with-offset-2-s1-immediate", "pxadds.u", 32,
17513 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17514 +  },
17515 +/* pxadds.u (${d-An}),#${s1-imm8},${s2} */
17516 +  {
17517 +    UBICOM32_INSN_PXADDS_U_D_INDIRECT_2_S1_IMMEDIATE, "pxadds.u-d-indirect-2-s1-immediate", "pxadds.u", 32,
17518 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17519 +  },
17520 +/* pxadds.u (${d-An})${d-i4-2}++,#${s1-imm8},${s2} */
17521 +  {
17522 +    UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_POST_INCREMENT_2_S1_IMMEDIATE, "pxadds.u-d-indirect-with-post-increment-2-s1-immediate", "pxadds.u", 32,
17523 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17524 +  },
17525 +/* pxadds.u ${d-i4-2}(${d-An})++,#${s1-imm8},${s2} */
17526 +  {
17527 +    UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_IMMEDIATE, "pxadds.u-d-indirect-with-pre-increment-2-s1-immediate", "pxadds.u", 32,
17528 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17529 +  },
17530 +/* pxadds.u ${d-direct-addr},(${s1-An},${s1-r}),${s2} */
17531 +  {
17532 +    UBICOM32_INSN_PXADDS_U_D_DIRECT_S1_INDIRECT_WITH_INDEX_4, "pxadds.u-d-direct-s1-indirect-with-index-4", "pxadds.u", 32,
17533 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17534 +  },
17535 +/* pxadds.u #${d-imm8},(${s1-An},${s1-r}),${s2} */
17536 +  {
17537 +    UBICOM32_INSN_PXADDS_U_D_IMMEDIATE_2_S1_INDIRECT_WITH_INDEX_4, "pxadds.u-d-immediate-2-s1-indirect-with-index-4", "pxadds.u", 32,
17538 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17539 +  },
17540 +/* pxadds.u (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */
17541 +  {
17542 +    UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_INDEX_4, "pxadds.u-d-indirect-with-index-2-s1-indirect-with-index-4", "pxadds.u", 32,
17543 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17544 +  },
17545 +/* pxadds.u ${d-imm7-2}(${d-An}),(${s1-An},${s1-r}),${s2} */
17546 +  {
17547 +    UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_INDEX_4, "pxadds.u-d-indirect-with-offset-2-s1-indirect-with-index-4", "pxadds.u", 32,
17548 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17549 +  },
17550 +/* pxadds.u (${d-An}),(${s1-An},${s1-r}),${s2} */
17551 +  {
17552 +    UBICOM32_INSN_PXADDS_U_D_INDIRECT_2_S1_INDIRECT_WITH_INDEX_4, "pxadds.u-d-indirect-2-s1-indirect-with-index-4", "pxadds.u", 32,
17553 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17554 +  },
17555 +/* pxadds.u (${d-An})${d-i4-2}++,(${s1-An},${s1-r}),${s2} */
17556 +  {
17557 +    UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_INDEX_4, "pxadds.u-d-indirect-with-post-increment-2-s1-indirect-with-index-4", "pxadds.u", 32,
17558 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17559 +  },
17560 +/* pxadds.u ${d-i4-2}(${d-An})++,(${s1-An},${s1-r}),${s2} */
17561 +  {
17562 +    UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_INDEX_4, "pxadds.u-d-indirect-with-pre-increment-2-s1-indirect-with-index-4", "pxadds.u", 32,
17563 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17564 +  },
17565 +/* pxadds.u ${d-direct-addr},${s1-imm7-4}(${s1-An}),${s2} */
17566 +  {
17567 +    UBICOM32_INSN_PXADDS_U_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4, "pxadds.u-d-direct-s1-indirect-with-offset-4", "pxadds.u", 32,
17568 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17569 +  },
17570 +/* pxadds.u #${d-imm8},${s1-imm7-4}(${s1-An}),${s2} */
17571 +  {
17572 +    UBICOM32_INSN_PXADDS_U_D_IMMEDIATE_2_S1_INDIRECT_WITH_OFFSET_4, "pxadds.u-d-immediate-2-s1-indirect-with-offset-4", "pxadds.u", 32,
17573 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17574 +  },
17575 +/* pxadds.u (${d-An},${d-r}),${s1-imm7-4}(${s1-An}),${s2} */
17576 +  {
17577 +    UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_OFFSET_4, "pxadds.u-d-indirect-with-index-2-s1-indirect-with-offset-4", "pxadds.u", 32,
17578 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17579 +  },
17580 +/* pxadds.u ${d-imm7-2}(${d-An}),${s1-imm7-4}(${s1-An}),${s2} */
17581 +  {
17582 +    UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_OFFSET_4, "pxadds.u-d-indirect-with-offset-2-s1-indirect-with-offset-4", "pxadds.u", 32,
17583 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17584 +  },
17585 +/* pxadds.u (${d-An}),${s1-imm7-4}(${s1-An}),${s2} */
17586 +  {
17587 +    UBICOM32_INSN_PXADDS_U_D_INDIRECT_2_S1_INDIRECT_WITH_OFFSET_4, "pxadds.u-d-indirect-2-s1-indirect-with-offset-4", "pxadds.u", 32,
17588 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17589 +  },
17590 +/* pxadds.u (${d-An})${d-i4-2}++,${s1-imm7-4}(${s1-An}),${s2} */
17591 +  {
17592 +    UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_4, "pxadds.u-d-indirect-with-post-increment-2-s1-indirect-with-offset-4", "pxadds.u", 32,
17593 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17594 +  },
17595 +/* pxadds.u ${d-i4-2}(${d-An})++,${s1-imm7-4}(${s1-An}),${s2} */
17596 +  {
17597 +    UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_4, "pxadds.u-d-indirect-with-pre-increment-2-s1-indirect-with-offset-4", "pxadds.u", 32,
17598 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17599 +  },
17600 +/* pxadds.u ${d-direct-addr},(${s1-An}),${s2} */
17601 +  {
17602 +    UBICOM32_INSN_PXADDS_U_D_DIRECT_S1_INDIRECT_4, "pxadds.u-d-direct-s1-indirect-4", "pxadds.u", 32,
17603 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17604 +  },
17605 +/* pxadds.u #${d-imm8},(${s1-An}),${s2} */
17606 +  {
17607 +    UBICOM32_INSN_PXADDS_U_D_IMMEDIATE_2_S1_INDIRECT_4, "pxadds.u-d-immediate-2-s1-indirect-4", "pxadds.u", 32,
17608 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17609 +  },
17610 +/* pxadds.u (${d-An},${d-r}),(${s1-An}),${s2} */
17611 +  {
17612 +    UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_4, "pxadds.u-d-indirect-with-index-2-s1-indirect-4", "pxadds.u", 32,
17613 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17614 +  },
17615 +/* pxadds.u ${d-imm7-2}(${d-An}),(${s1-An}),${s2} */
17616 +  {
17617 +    UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_4, "pxadds.u-d-indirect-with-offset-2-s1-indirect-4", "pxadds.u", 32,
17618 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17619 +  },
17620 +/* pxadds.u (${d-An}),(${s1-An}),${s2} */
17621 +  {
17622 +    UBICOM32_INSN_PXADDS_U_D_INDIRECT_2_S1_INDIRECT_4, "pxadds.u-d-indirect-2-s1-indirect-4", "pxadds.u", 32,
17623 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17624 +  },
17625 +/* pxadds.u (${d-An})${d-i4-2}++,(${s1-An}),${s2} */
17626 +  {
17627 +    UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_4, "pxadds.u-d-indirect-with-post-increment-2-s1-indirect-4", "pxadds.u", 32,
17628 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17629 +  },
17630 +/* pxadds.u ${d-i4-2}(${d-An})++,(${s1-An}),${s2} */
17631 +  {
17632 +    UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_4, "pxadds.u-d-indirect-with-pre-increment-2-s1-indirect-4", "pxadds.u", 32,
17633 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17634 +  },
17635 +/* pxadds.u ${d-direct-addr},(${s1-An})${s1-i4-4}++,${s2} */
17636 +  {
17637 +    UBICOM32_INSN_PXADDS_U_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4, "pxadds.u-d-direct-s1-indirect-with-post-increment-4", "pxadds.u", 32,
17638 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17639 +  },
17640 +/* pxadds.u #${d-imm8},(${s1-An})${s1-i4-4}++,${s2} */
17641 +  {
17642 +    UBICOM32_INSN_PXADDS_U_D_IMMEDIATE_2_S1_INDIRECT_WITH_POST_INCREMENT_4, "pxadds.u-d-immediate-2-s1-indirect-with-post-increment-4", "pxadds.u", 32,
17643 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17644 +  },
17645 +/* pxadds.u (${d-An},${d-r}),(${s1-An})${s1-i4-4}++,${s2} */
17646 +  {
17647 +    UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_POST_INCREMENT_4, "pxadds.u-d-indirect-with-index-2-s1-indirect-with-post-increment-4", "pxadds.u", 32,
17648 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17649 +  },
17650 +/* pxadds.u ${d-imm7-2}(${d-An}),(${s1-An})${s1-i4-4}++,${s2} */
17651 +  {
17652 +    UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_POST_INCREMENT_4, "pxadds.u-d-indirect-with-offset-2-s1-indirect-with-post-increment-4", "pxadds.u", 32,
17653 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17654 +  },
17655 +/* pxadds.u (${d-An}),(${s1-An})${s1-i4-4}++,${s2} */
17656 +  {
17657 +    UBICOM32_INSN_PXADDS_U_D_INDIRECT_2_S1_INDIRECT_WITH_POST_INCREMENT_4, "pxadds.u-d-indirect-2-s1-indirect-with-post-increment-4", "pxadds.u", 32,
17658 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17659 +  },
17660 +/* pxadds.u (${d-An})${d-i4-2}++,(${s1-An})${s1-i4-4}++,${s2} */
17661 +  {
17662 +    UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_4, "pxadds.u-d-indirect-with-post-increment-2-s1-indirect-with-post-increment-4", "pxadds.u", 32,
17663 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17664 +  },
17665 +/* pxadds.u ${d-i4-2}(${d-An})++,(${s1-An})${s1-i4-4}++,${s2} */
17666 +  {
17667 +    UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_4, "pxadds.u-d-indirect-with-pre-increment-2-s1-indirect-with-post-increment-4", "pxadds.u", 32,
17668 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17669 +  },
17670 +/* pxadds.u ${d-direct-addr},${s1-i4-4}(${s1-An})++,${s2} */
17671 +  {
17672 +    UBICOM32_INSN_PXADDS_U_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4, "pxadds.u-d-direct-s1-indirect-with-pre-increment-4", "pxadds.u", 32,
17673 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17674 +  },
17675 +/* pxadds.u #${d-imm8},${s1-i4-4}(${s1-An})++,${s2} */
17676 +  {
17677 +    UBICOM32_INSN_PXADDS_U_D_IMMEDIATE_2_S1_INDIRECT_WITH_PRE_INCREMENT_4, "pxadds.u-d-immediate-2-s1-indirect-with-pre-increment-4", "pxadds.u", 32,
17678 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17679 +  },
17680 +/* pxadds.u (${d-An},${d-r}),${s1-i4-4}(${s1-An})++,${s2} */
17681 +  {
17682 +    UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_PRE_INCREMENT_4, "pxadds.u-d-indirect-with-index-2-s1-indirect-with-pre-increment-4", "pxadds.u", 32,
17683 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17684 +  },
17685 +/* pxadds.u ${d-imm7-2}(${d-An}),${s1-i4-4}(${s1-An})++,${s2} */
17686 +  {
17687 +    UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_PRE_INCREMENT_4, "pxadds.u-d-indirect-with-offset-2-s1-indirect-with-pre-increment-4", "pxadds.u", 32,
17688 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17689 +  },
17690 +/* pxadds.u (${d-An}),${s1-i4-4}(${s1-An})++,${s2} */
17691 +  {
17692 +    UBICOM32_INSN_PXADDS_U_D_INDIRECT_2_S1_INDIRECT_WITH_PRE_INCREMENT_4, "pxadds.u-d-indirect-2-s1-indirect-with-pre-increment-4", "pxadds.u", 32,
17693 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17694 +  },
17695 +/* pxadds.u (${d-An})${d-i4-2}++,${s1-i4-4}(${s1-An})++,${s2} */
17696 +  {
17697 +    UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_4, "pxadds.u-d-indirect-with-post-increment-2-s1-indirect-with-pre-increment-4", "pxadds.u", 32,
17698 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17699 +  },
17700 +/* pxadds.u ${d-i4-2}(${d-An})++,${s1-i4-4}(${s1-An})++,${s2} */
17701 +  {
17702 +    UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_4, "pxadds.u-d-indirect-with-pre-increment-2-s1-indirect-with-pre-increment-4", "pxadds.u", 32,
17703 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17704 +  },
17705 +/* pxadds ${d-direct-addr},${s1-direct-addr},${s2} */
17706 +  {
17707 +    UBICOM32_INSN_PXADDS_D_DIRECT_S1_DIRECT, "pxadds-d-direct-s1-direct", "pxadds", 32,
17708 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17709 +  },
17710 +/* pxadds #${d-imm8},${s1-direct-addr},${s2} */
17711 +  {
17712 +    UBICOM32_INSN_PXADDS_D_IMMEDIATE_2_S1_DIRECT, "pxadds-d-immediate-2-s1-direct", "pxadds", 32,
17713 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17714 +  },
17715 +/* pxadds (${d-An},${d-r}),${s1-direct-addr},${s2} */
17716 +  {
17717 +    UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_INDEX_2_S1_DIRECT, "pxadds-d-indirect-with-index-2-s1-direct", "pxadds", 32,
17718 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17719 +  },
17720 +/* pxadds ${d-imm7-2}(${d-An}),${s1-direct-addr},${s2} */
17721 +  {
17722 +    UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_OFFSET_2_S1_DIRECT, "pxadds-d-indirect-with-offset-2-s1-direct", "pxadds", 32,
17723 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17724 +  },
17725 +/* pxadds (${d-An}),${s1-direct-addr},${s2} */
17726 +  {
17727 +    UBICOM32_INSN_PXADDS_D_INDIRECT_2_S1_DIRECT, "pxadds-d-indirect-2-s1-direct", "pxadds", 32,
17728 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17729 +  },
17730 +/* pxadds (${d-An})${d-i4-2}++,${s1-direct-addr},${s2} */
17731 +  {
17732 +    UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_POST_INCREMENT_2_S1_DIRECT, "pxadds-d-indirect-with-post-increment-2-s1-direct", "pxadds", 32,
17733 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17734 +  },
17735 +/* pxadds ${d-i4-2}(${d-An})++,${s1-direct-addr},${s2} */
17736 +  {
17737 +    UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_DIRECT, "pxadds-d-indirect-with-pre-increment-2-s1-direct", "pxadds", 32,
17738 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17739 +  },
17740 +/* pxadds ${d-direct-addr},#${s1-imm8},${s2} */
17741 +  {
17742 +    UBICOM32_INSN_PXADDS_D_DIRECT_S1_IMMEDIATE, "pxadds-d-direct-s1-immediate", "pxadds", 32,
17743 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17744 +  },
17745 +/* pxadds #${d-imm8},#${s1-imm8},${s2} */
17746 +  {
17747 +    UBICOM32_INSN_PXADDS_D_IMMEDIATE_2_S1_IMMEDIATE, "pxadds-d-immediate-2-s1-immediate", "pxadds", 32,
17748 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17749 +  },
17750 +/* pxadds (${d-An},${d-r}),#${s1-imm8},${s2} */
17751 +  {
17752 +    UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_INDEX_2_S1_IMMEDIATE, "pxadds-d-indirect-with-index-2-s1-immediate", "pxadds", 32,
17753 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17754 +  },
17755 +/* pxadds ${d-imm7-2}(${d-An}),#${s1-imm8},${s2} */
17756 +  {
17757 +    UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_OFFSET_2_S1_IMMEDIATE, "pxadds-d-indirect-with-offset-2-s1-immediate", "pxadds", 32,
17758 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17759 +  },
17760 +/* pxadds (${d-An}),#${s1-imm8},${s2} */
17761 +  {
17762 +    UBICOM32_INSN_PXADDS_D_INDIRECT_2_S1_IMMEDIATE, "pxadds-d-indirect-2-s1-immediate", "pxadds", 32,
17763 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17764 +  },
17765 +/* pxadds (${d-An})${d-i4-2}++,#${s1-imm8},${s2} */
17766 +  {
17767 +    UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_POST_INCREMENT_2_S1_IMMEDIATE, "pxadds-d-indirect-with-post-increment-2-s1-immediate", "pxadds", 32,
17768 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17769 +  },
17770 +/* pxadds ${d-i4-2}(${d-An})++,#${s1-imm8},${s2} */
17771 +  {
17772 +    UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_IMMEDIATE, "pxadds-d-indirect-with-pre-increment-2-s1-immediate", "pxadds", 32,
17773 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17774 +  },
17775 +/* pxadds ${d-direct-addr},(${s1-An},${s1-r}),${s2} */
17776 +  {
17777 +    UBICOM32_INSN_PXADDS_D_DIRECT_S1_INDIRECT_WITH_INDEX_4, "pxadds-d-direct-s1-indirect-with-index-4", "pxadds", 32,
17778 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17779 +  },
17780 +/* pxadds #${d-imm8},(${s1-An},${s1-r}),${s2} */
17781 +  {
17782 +    UBICOM32_INSN_PXADDS_D_IMMEDIATE_2_S1_INDIRECT_WITH_INDEX_4, "pxadds-d-immediate-2-s1-indirect-with-index-4", "pxadds", 32,
17783 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17784 +  },
17785 +/* pxadds (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */
17786 +  {
17787 +    UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_INDEX_4, "pxadds-d-indirect-with-index-2-s1-indirect-with-index-4", "pxadds", 32,
17788 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17789 +  },
17790 +/* pxadds ${d-imm7-2}(${d-An}),(${s1-An},${s1-r}),${s2} */
17791 +  {
17792 +    UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_INDEX_4, "pxadds-d-indirect-with-offset-2-s1-indirect-with-index-4", "pxadds", 32,
17793 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17794 +  },
17795 +/* pxadds (${d-An}),(${s1-An},${s1-r}),${s2} */
17796 +  {
17797 +    UBICOM32_INSN_PXADDS_D_INDIRECT_2_S1_INDIRECT_WITH_INDEX_4, "pxadds-d-indirect-2-s1-indirect-with-index-4", "pxadds", 32,
17798 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17799 +  },
17800 +/* pxadds (${d-An})${d-i4-2}++,(${s1-An},${s1-r}),${s2} */
17801 +  {
17802 +    UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_INDEX_4, "pxadds-d-indirect-with-post-increment-2-s1-indirect-with-index-4", "pxadds", 32,
17803 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17804 +  },
17805 +/* pxadds ${d-i4-2}(${d-An})++,(${s1-An},${s1-r}),${s2} */
17806 +  {
17807 +    UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_INDEX_4, "pxadds-d-indirect-with-pre-increment-2-s1-indirect-with-index-4", "pxadds", 32,
17808 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17809 +  },
17810 +/* pxadds ${d-direct-addr},${s1-imm7-4}(${s1-An}),${s2} */
17811 +  {
17812 +    UBICOM32_INSN_PXADDS_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4, "pxadds-d-direct-s1-indirect-with-offset-4", "pxadds", 32,
17813 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17814 +  },
17815 +/* pxadds #${d-imm8},${s1-imm7-4}(${s1-An}),${s2} */
17816 +  {
17817 +    UBICOM32_INSN_PXADDS_D_IMMEDIATE_2_S1_INDIRECT_WITH_OFFSET_4, "pxadds-d-immediate-2-s1-indirect-with-offset-4", "pxadds", 32,
17818 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17819 +  },
17820 +/* pxadds (${d-An},${d-r}),${s1-imm7-4}(${s1-An}),${s2} */
17821 +  {
17822 +    UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_OFFSET_4, "pxadds-d-indirect-with-index-2-s1-indirect-with-offset-4", "pxadds", 32,
17823 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17824 +  },
17825 +/* pxadds ${d-imm7-2}(${d-An}),${s1-imm7-4}(${s1-An}),${s2} */
17826 +  {
17827 +    UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_OFFSET_4, "pxadds-d-indirect-with-offset-2-s1-indirect-with-offset-4", "pxadds", 32,
17828 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17829 +  },
17830 +/* pxadds (${d-An}),${s1-imm7-4}(${s1-An}),${s2} */
17831 +  {
17832 +    UBICOM32_INSN_PXADDS_D_INDIRECT_2_S1_INDIRECT_WITH_OFFSET_4, "pxadds-d-indirect-2-s1-indirect-with-offset-4", "pxadds", 32,
17833 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17834 +  },
17835 +/* pxadds (${d-An})${d-i4-2}++,${s1-imm7-4}(${s1-An}),${s2} */
17836 +  {
17837 +    UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_4, "pxadds-d-indirect-with-post-increment-2-s1-indirect-with-offset-4", "pxadds", 32,
17838 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17839 +  },
17840 +/* pxadds ${d-i4-2}(${d-An})++,${s1-imm7-4}(${s1-An}),${s2} */
17841 +  {
17842 +    UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_4, "pxadds-d-indirect-with-pre-increment-2-s1-indirect-with-offset-4", "pxadds", 32,
17843 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17844 +  },
17845 +/* pxadds ${d-direct-addr},(${s1-An}),${s2} */
17846 +  {
17847 +    UBICOM32_INSN_PXADDS_D_DIRECT_S1_INDIRECT_4, "pxadds-d-direct-s1-indirect-4", "pxadds", 32,
17848 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17849 +  },
17850 +/* pxadds #${d-imm8},(${s1-An}),${s2} */
17851 +  {
17852 +    UBICOM32_INSN_PXADDS_D_IMMEDIATE_2_S1_INDIRECT_4, "pxadds-d-immediate-2-s1-indirect-4", "pxadds", 32,
17853 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17854 +  },
17855 +/* pxadds (${d-An},${d-r}),(${s1-An}),${s2} */
17856 +  {
17857 +    UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_4, "pxadds-d-indirect-with-index-2-s1-indirect-4", "pxadds", 32,
17858 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17859 +  },
17860 +/* pxadds ${d-imm7-2}(${d-An}),(${s1-An}),${s2} */
17861 +  {
17862 +    UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_4, "pxadds-d-indirect-with-offset-2-s1-indirect-4", "pxadds", 32,
17863 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17864 +  },
17865 +/* pxadds (${d-An}),(${s1-An}),${s2} */
17866 +  {
17867 +    UBICOM32_INSN_PXADDS_D_INDIRECT_2_S1_INDIRECT_4, "pxadds-d-indirect-2-s1-indirect-4", "pxadds", 32,
17868 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17869 +  },
17870 +/* pxadds (${d-An})${d-i4-2}++,(${s1-An}),${s2} */
17871 +  {
17872 +    UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_4, "pxadds-d-indirect-with-post-increment-2-s1-indirect-4", "pxadds", 32,
17873 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17874 +  },
17875 +/* pxadds ${d-i4-2}(${d-An})++,(${s1-An}),${s2} */
17876 +  {
17877 +    UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_4, "pxadds-d-indirect-with-pre-increment-2-s1-indirect-4", "pxadds", 32,
17878 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17879 +  },
17880 +/* pxadds ${d-direct-addr},(${s1-An})${s1-i4-4}++,${s2} */
17881 +  {
17882 +    UBICOM32_INSN_PXADDS_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4, "pxadds-d-direct-s1-indirect-with-post-increment-4", "pxadds", 32,
17883 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17884 +  },
17885 +/* pxadds #${d-imm8},(${s1-An})${s1-i4-4}++,${s2} */
17886 +  {
17887 +    UBICOM32_INSN_PXADDS_D_IMMEDIATE_2_S1_INDIRECT_WITH_POST_INCREMENT_4, "pxadds-d-immediate-2-s1-indirect-with-post-increment-4", "pxadds", 32,
17888 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17889 +  },
17890 +/* pxadds (${d-An},${d-r}),(${s1-An})${s1-i4-4}++,${s2} */
17891 +  {
17892 +    UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_POST_INCREMENT_4, "pxadds-d-indirect-with-index-2-s1-indirect-with-post-increment-4", "pxadds", 32,
17893 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17894 +  },
17895 +/* pxadds ${d-imm7-2}(${d-An}),(${s1-An})${s1-i4-4}++,${s2} */
17896 +  {
17897 +    UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_POST_INCREMENT_4, "pxadds-d-indirect-with-offset-2-s1-indirect-with-post-increment-4", "pxadds", 32,
17898 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17899 +  },
17900 +/* pxadds (${d-An}),(${s1-An})${s1-i4-4}++,${s2} */
17901 +  {
17902 +    UBICOM32_INSN_PXADDS_D_INDIRECT_2_S1_INDIRECT_WITH_POST_INCREMENT_4, "pxadds-d-indirect-2-s1-indirect-with-post-increment-4", "pxadds", 32,
17903 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17904 +  },
17905 +/* pxadds (${d-An})${d-i4-2}++,(${s1-An})${s1-i4-4}++,${s2} */
17906 +  {
17907 +    UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_4, "pxadds-d-indirect-with-post-increment-2-s1-indirect-with-post-increment-4", "pxadds", 32,
17908 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17909 +  },
17910 +/* pxadds ${d-i4-2}(${d-An})++,(${s1-An})${s1-i4-4}++,${s2} */
17911 +  {
17912 +    UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_4, "pxadds-d-indirect-with-pre-increment-2-s1-indirect-with-post-increment-4", "pxadds", 32,
17913 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17914 +  },
17915 +/* pxadds ${d-direct-addr},${s1-i4-4}(${s1-An})++,${s2} */
17916 +  {
17917 +    UBICOM32_INSN_PXADDS_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4, "pxadds-d-direct-s1-indirect-with-pre-increment-4", "pxadds", 32,
17918 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17919 +  },
17920 +/* pxadds #${d-imm8},${s1-i4-4}(${s1-An})++,${s2} */
17921 +  {
17922 +    UBICOM32_INSN_PXADDS_D_IMMEDIATE_2_S1_INDIRECT_WITH_PRE_INCREMENT_4, "pxadds-d-immediate-2-s1-indirect-with-pre-increment-4", "pxadds", 32,
17923 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17924 +  },
17925 +/* pxadds (${d-An},${d-r}),${s1-i4-4}(${s1-An})++,${s2} */
17926 +  {
17927 +    UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_PRE_INCREMENT_4, "pxadds-d-indirect-with-index-2-s1-indirect-with-pre-increment-4", "pxadds", 32,
17928 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17929 +  },
17930 +/* pxadds ${d-imm7-2}(${d-An}),${s1-i4-4}(${s1-An})++,${s2} */
17931 +  {
17932 +    UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_PRE_INCREMENT_4, "pxadds-d-indirect-with-offset-2-s1-indirect-with-pre-increment-4", "pxadds", 32,
17933 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17934 +  },
17935 +/* pxadds (${d-An}),${s1-i4-4}(${s1-An})++,${s2} */
17936 +  {
17937 +    UBICOM32_INSN_PXADDS_D_INDIRECT_2_S1_INDIRECT_WITH_PRE_INCREMENT_4, "pxadds-d-indirect-2-s1-indirect-with-pre-increment-4", "pxadds", 32,
17938 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17939 +  },
17940 +/* pxadds (${d-An})${d-i4-2}++,${s1-i4-4}(${s1-An})++,${s2} */
17941 +  {
17942 +    UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_4, "pxadds-d-indirect-with-post-increment-2-s1-indirect-with-pre-increment-4", "pxadds", 32,
17943 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17944 +  },
17945 +/* pxadds ${d-i4-2}(${d-An})++,${s1-i4-4}(${s1-An})++,${s2} */
17946 +  {
17947 +    UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_4, "pxadds-d-indirect-with-pre-increment-2-s1-indirect-with-pre-increment-4", "pxadds", 32,
17948 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17949 +  },
17950 +/* pxhi.s ${Dn},${s1-direct-addr},${s2} */
17951 +  {
17952 +    UBICOM32_INSN_PXHI_S_S1_DIRECT, "pxhi.s-s1-direct", "pxhi.s", 32,
17953 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17954 +  },
17955 +/* pxhi.s ${Dn},#${s1-imm8},${s2} */
17956 +  {
17957 +    UBICOM32_INSN_PXHI_S_S1_IMMEDIATE, "pxhi.s-s1-immediate", "pxhi.s", 32,
17958 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17959 +  },
17960 +/* pxhi.s ${Dn},(${s1-An},${s1-r}),${s2} */
17961 +  {
17962 +    UBICOM32_INSN_PXHI_S_S1_INDIRECT_WITH_INDEX_4, "pxhi.s-s1-indirect-with-index-4", "pxhi.s", 32,
17963 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17964 +  },
17965 +/* pxhi.s ${Dn},${s1-imm7-4}(${s1-An}),${s2} */
17966 +  {
17967 +    UBICOM32_INSN_PXHI_S_S1_INDIRECT_WITH_OFFSET_4, "pxhi.s-s1-indirect-with-offset-4", "pxhi.s", 32,
17968 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17969 +  },
17970 +/* pxhi.s ${Dn},(${s1-An}),${s2} */
17971 +  {
17972 +    UBICOM32_INSN_PXHI_S_S1_INDIRECT_4, "pxhi.s-s1-indirect-4", "pxhi.s", 32,
17973 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17974 +  },
17975 +/* pxhi.s ${Dn},(${s1-An})${s1-i4-4}++,${s2} */
17976 +  {
17977 +    UBICOM32_INSN_PXHI_S_S1_INDIRECT_WITH_POST_INCREMENT_4, "pxhi.s-s1-indirect-with-post-increment-4", "pxhi.s", 32,
17978 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17979 +  },
17980 +/* pxhi.s ${Dn},${s1-i4-4}(${s1-An})++,${s2} */
17981 +  {
17982 +    UBICOM32_INSN_PXHI_S_S1_INDIRECT_WITH_PRE_INCREMENT_4, "pxhi.s-s1-indirect-with-pre-increment-4", "pxhi.s", 32,
17983 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17984 +  },
17985 +/* pxhi ${Dn},${s1-direct-addr},${s2} */
17986 +  {
17987 +    UBICOM32_INSN_PXHI_S1_DIRECT, "pxhi-s1-direct", "pxhi", 32,
17988 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17989 +  },
17990 +/* pxhi ${Dn},#${s1-imm8},${s2} */
17991 +  {
17992 +    UBICOM32_INSN_PXHI_S1_IMMEDIATE, "pxhi-s1-immediate", "pxhi", 32,
17993 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17994 +  },
17995 +/* pxhi ${Dn},(${s1-An},${s1-r}),${s2} */
17996 +  {
17997 +    UBICOM32_INSN_PXHI_S1_INDIRECT_WITH_INDEX_4, "pxhi-s1-indirect-with-index-4", "pxhi", 32,
17998 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
17999 +  },
18000 +/* pxhi ${Dn},${s1-imm7-4}(${s1-An}),${s2} */
18001 +  {
18002 +    UBICOM32_INSN_PXHI_S1_INDIRECT_WITH_OFFSET_4, "pxhi-s1-indirect-with-offset-4", "pxhi", 32,
18003 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18004 +  },
18005 +/* pxhi ${Dn},(${s1-An}),${s2} */
18006 +  {
18007 +    UBICOM32_INSN_PXHI_S1_INDIRECT_4, "pxhi-s1-indirect-4", "pxhi", 32,
18008 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18009 +  },
18010 +/* pxhi ${Dn},(${s1-An})${s1-i4-4}++,${s2} */
18011 +  {
18012 +    UBICOM32_INSN_PXHI_S1_INDIRECT_WITH_POST_INCREMENT_4, "pxhi-s1-indirect-with-post-increment-4", "pxhi", 32,
18013 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18014 +  },
18015 +/* pxhi ${Dn},${s1-i4-4}(${s1-An})++,${s2} */
18016 +  {
18017 +    UBICOM32_INSN_PXHI_S1_INDIRECT_WITH_PRE_INCREMENT_4, "pxhi-s1-indirect-with-pre-increment-4", "pxhi", 32,
18018 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18019 +  },
18020 +/* pxvi.s ${d-direct-addr},${s1-direct-addr},${s2} */
18021 +  {
18022 +    UBICOM32_INSN_PXVI_S_D_DIRECT_S1_DIRECT, "pxvi.s-d-direct-s1-direct", "pxvi.s", 32,
18023 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18024 +  },
18025 +/* pxvi.s #${d-imm8},${s1-direct-addr},${s2} */
18026 +  {
18027 +    UBICOM32_INSN_PXVI_S_D_IMMEDIATE_4_S1_DIRECT, "pxvi.s-d-immediate-4-s1-direct", "pxvi.s", 32,
18028 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18029 +  },
18030 +/* pxvi.s (${d-An},${d-r}),${s1-direct-addr},${s2} */
18031 +  {
18032 +    UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_INDEX_4_S1_DIRECT, "pxvi.s-d-indirect-with-index-4-s1-direct", "pxvi.s", 32,
18033 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18034 +  },
18035 +/* pxvi.s ${d-imm7-4}(${d-An}),${s1-direct-addr},${s2} */
18036 +  {
18037 +    UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_OFFSET_4_S1_DIRECT, "pxvi.s-d-indirect-with-offset-4-s1-direct", "pxvi.s", 32,
18038 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18039 +  },
18040 +/* pxvi.s (${d-An}),${s1-direct-addr},${s2} */
18041 +  {
18042 +    UBICOM32_INSN_PXVI_S_D_INDIRECT_4_S1_DIRECT, "pxvi.s-d-indirect-4-s1-direct", "pxvi.s", 32,
18043 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18044 +  },
18045 +/* pxvi.s (${d-An})${d-i4-4}++,${s1-direct-addr},${s2} */
18046 +  {
18047 +    UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_POST_INCREMENT_4_S1_DIRECT, "pxvi.s-d-indirect-with-post-increment-4-s1-direct", "pxvi.s", 32,
18048 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18049 +  },
18050 +/* pxvi.s ${d-i4-4}(${d-An})++,${s1-direct-addr},${s2} */
18051 +  {
18052 +    UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_DIRECT, "pxvi.s-d-indirect-with-pre-increment-4-s1-direct", "pxvi.s", 32,
18053 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18054 +  },
18055 +/* pxvi.s ${d-direct-addr},#${s1-imm8},${s2} */
18056 +  {
18057 +    UBICOM32_INSN_PXVI_S_D_DIRECT_S1_IMMEDIATE, "pxvi.s-d-direct-s1-immediate", "pxvi.s", 32,
18058 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18059 +  },
18060 +/* pxvi.s #${d-imm8},#${s1-imm8},${s2} */
18061 +  {
18062 +    UBICOM32_INSN_PXVI_S_D_IMMEDIATE_4_S1_IMMEDIATE, "pxvi.s-d-immediate-4-s1-immediate", "pxvi.s", 32,
18063 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18064 +  },
18065 +/* pxvi.s (${d-An},${d-r}),#${s1-imm8},${s2} */
18066 +  {
18067 +    UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_INDEX_4_S1_IMMEDIATE, "pxvi.s-d-indirect-with-index-4-s1-immediate", "pxvi.s", 32,
18068 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18069 +  },
18070 +/* pxvi.s ${d-imm7-4}(${d-An}),#${s1-imm8},${s2} */
18071 +  {
18072 +    UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_OFFSET_4_S1_IMMEDIATE, "pxvi.s-d-indirect-with-offset-4-s1-immediate", "pxvi.s", 32,
18073 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18074 +  },
18075 +/* pxvi.s (${d-An}),#${s1-imm8},${s2} */
18076 +  {
18077 +    UBICOM32_INSN_PXVI_S_D_INDIRECT_4_S1_IMMEDIATE, "pxvi.s-d-indirect-4-s1-immediate", "pxvi.s", 32,
18078 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18079 +  },
18080 +/* pxvi.s (${d-An})${d-i4-4}++,#${s1-imm8},${s2} */
18081 +  {
18082 +    UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_POST_INCREMENT_4_S1_IMMEDIATE, "pxvi.s-d-indirect-with-post-increment-4-s1-immediate", "pxvi.s", 32,
18083 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18084 +  },
18085 +/* pxvi.s ${d-i4-4}(${d-An})++,#${s1-imm8},${s2} */
18086 +  {
18087 +    UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_IMMEDIATE, "pxvi.s-d-indirect-with-pre-increment-4-s1-immediate", "pxvi.s", 32,
18088 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18089 +  },
18090 +/* pxvi.s ${d-direct-addr},(${s1-An},${s1-r}),${s2} */
18091 +  {
18092 +    UBICOM32_INSN_PXVI_S_D_DIRECT_S1_INDIRECT_WITH_INDEX_4, "pxvi.s-d-direct-s1-indirect-with-index-4", "pxvi.s", 32,
18093 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18094 +  },
18095 +/* pxvi.s #${d-imm8},(${s1-An},${s1-r}),${s2} */
18096 +  {
18097 +    UBICOM32_INSN_PXVI_S_D_IMMEDIATE_4_S1_INDIRECT_WITH_INDEX_4, "pxvi.s-d-immediate-4-s1-indirect-with-index-4", "pxvi.s", 32,
18098 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18099 +  },
18100 +/* pxvi.s (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */
18101 +  {
18102 +    UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_INDEX_4, "pxvi.s-d-indirect-with-index-4-s1-indirect-with-index-4", "pxvi.s", 32,
18103 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18104 +  },
18105 +/* pxvi.s ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}),${s2} */
18106 +  {
18107 +    UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_INDEX_4, "pxvi.s-d-indirect-with-offset-4-s1-indirect-with-index-4", "pxvi.s", 32,
18108 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18109 +  },
18110 +/* pxvi.s (${d-An}),(${s1-An},${s1-r}),${s2} */
18111 +  {
18112 +    UBICOM32_INSN_PXVI_S_D_INDIRECT_4_S1_INDIRECT_WITH_INDEX_4, "pxvi.s-d-indirect-4-s1-indirect-with-index-4", "pxvi.s", 32,
18113 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18114 +  },
18115 +/* pxvi.s (${d-An})${d-i4-4}++,(${s1-An},${s1-r}),${s2} */
18116 +  {
18117 +    UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, "pxvi.s-d-indirect-with-post-increment-4-s1-indirect-with-index-4", "pxvi.s", 32,
18118 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18119 +  },
18120 +/* pxvi.s ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}),${s2} */
18121 +  {
18122 +    UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, "pxvi.s-d-indirect-with-pre-increment-4-s1-indirect-with-index-4", "pxvi.s", 32,
18123 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18124 +  },
18125 +/* pxvi.s ${d-direct-addr},${s1-imm7-4}(${s1-An}),${s2} */
18126 +  {
18127 +    UBICOM32_INSN_PXVI_S_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4, "pxvi.s-d-direct-s1-indirect-with-offset-4", "pxvi.s", 32,
18128 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18129 +  },
18130 +/* pxvi.s #${d-imm8},${s1-imm7-4}(${s1-An}),${s2} */
18131 +  {
18132 +    UBICOM32_INSN_PXVI_S_D_IMMEDIATE_4_S1_INDIRECT_WITH_OFFSET_4, "pxvi.s-d-immediate-4-s1-indirect-with-offset-4", "pxvi.s", 32,
18133 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18134 +  },
18135 +/* pxvi.s (${d-An},${d-r}),${s1-imm7-4}(${s1-An}),${s2} */
18136 +  {
18137 +    UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_OFFSET_4, "pxvi.s-d-indirect-with-index-4-s1-indirect-with-offset-4", "pxvi.s", 32,
18138 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18139 +  },
18140 +/* pxvi.s ${d-imm7-4}(${d-An}),${s1-imm7-4}(${s1-An}),${s2} */
18141 +  {
18142 +    UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_OFFSET_4, "pxvi.s-d-indirect-with-offset-4-s1-indirect-with-offset-4", "pxvi.s", 32,
18143 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18144 +  },
18145 +/* pxvi.s (${d-An}),${s1-imm7-4}(${s1-An}),${s2} */
18146 +  {
18147 +    UBICOM32_INSN_PXVI_S_D_INDIRECT_4_S1_INDIRECT_WITH_OFFSET_4, "pxvi.s-d-indirect-4-s1-indirect-with-offset-4", "pxvi.s", 32,
18148 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18149 +  },
18150 +/* pxvi.s (${d-An})${d-i4-4}++,${s1-imm7-4}(${s1-An}),${s2} */
18151 +  {
18152 +    UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, "pxvi.s-d-indirect-with-post-increment-4-s1-indirect-with-offset-4", "pxvi.s", 32,
18153 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18154 +  },
18155 +/* pxvi.s ${d-i4-4}(${d-An})++,${s1-imm7-4}(${s1-An}),${s2} */
18156 +  {
18157 +    UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, "pxvi.s-d-indirect-with-pre-increment-4-s1-indirect-with-offset-4", "pxvi.s", 32,
18158 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18159 +  },
18160 +/* pxvi.s ${d-direct-addr},(${s1-An}),${s2} */
18161 +  {
18162 +    UBICOM32_INSN_PXVI_S_D_DIRECT_S1_INDIRECT_4, "pxvi.s-d-direct-s1-indirect-4", "pxvi.s", 32,
18163 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18164 +  },
18165 +/* pxvi.s #${d-imm8},(${s1-An}),${s2} */
18166 +  {
18167 +    UBICOM32_INSN_PXVI_S_D_IMMEDIATE_4_S1_INDIRECT_4, "pxvi.s-d-immediate-4-s1-indirect-4", "pxvi.s", 32,
18168 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18169 +  },
18170 +/* pxvi.s (${d-An},${d-r}),(${s1-An}),${s2} */
18171 +  {
18172 +    UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_4, "pxvi.s-d-indirect-with-index-4-s1-indirect-4", "pxvi.s", 32,
18173 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18174 +  },
18175 +/* pxvi.s ${d-imm7-4}(${d-An}),(${s1-An}),${s2} */
18176 +  {
18177 +    UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_4, "pxvi.s-d-indirect-with-offset-4-s1-indirect-4", "pxvi.s", 32,
18178 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18179 +  },
18180 +/* pxvi.s (${d-An}),(${s1-An}),${s2} */
18181 +  {
18182 +    UBICOM32_INSN_PXVI_S_D_INDIRECT_4_S1_INDIRECT_4, "pxvi.s-d-indirect-4-s1-indirect-4", "pxvi.s", 32,
18183 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18184 +  },
18185 +/* pxvi.s (${d-An})${d-i4-4}++,(${s1-An}),${s2} */
18186 +  {
18187 +    UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_4, "pxvi.s-d-indirect-with-post-increment-4-s1-indirect-4", "pxvi.s", 32,
18188 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18189 +  },
18190 +/* pxvi.s ${d-i4-4}(${d-An})++,(${s1-An}),${s2} */
18191 +  {
18192 +    UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_4, "pxvi.s-d-indirect-with-pre-increment-4-s1-indirect-4", "pxvi.s", 32,
18193 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18194 +  },
18195 +/* pxvi.s ${d-direct-addr},(${s1-An})${s1-i4-4}++,${s2} */
18196 +  {
18197 +    UBICOM32_INSN_PXVI_S_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4, "pxvi.s-d-direct-s1-indirect-with-post-increment-4", "pxvi.s", 32,
18198 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18199 +  },
18200 +/* pxvi.s #${d-imm8},(${s1-An})${s1-i4-4}++,${s2} */
18201 +  {
18202 +    UBICOM32_INSN_PXVI_S_D_IMMEDIATE_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "pxvi.s-d-immediate-4-s1-indirect-with-post-increment-4", "pxvi.s", 32,
18203 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18204 +  },
18205 +/* pxvi.s (${d-An},${d-r}),(${s1-An})${s1-i4-4}++,${s2} */
18206 +  {
18207 +    UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "pxvi.s-d-indirect-with-index-4-s1-indirect-with-post-increment-4", "pxvi.s", 32,
18208 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18209 +  },
18210 +/* pxvi.s ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-4}++,${s2} */
18211 +  {
18212 +    UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "pxvi.s-d-indirect-with-offset-4-s1-indirect-with-post-increment-4", "pxvi.s", 32,
18213 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18214 +  },
18215 +/* pxvi.s (${d-An}),(${s1-An})${s1-i4-4}++,${s2} */
18216 +  {
18217 +    UBICOM32_INSN_PXVI_S_D_INDIRECT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "pxvi.s-d-indirect-4-s1-indirect-with-post-increment-4", "pxvi.s", 32,
18218 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18219 +  },
18220 +/* pxvi.s (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-4}++,${s2} */
18221 +  {
18222 +    UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "pxvi.s-d-indirect-with-post-increment-4-s1-indirect-with-post-increment-4", "pxvi.s", 32,
18223 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18224 +  },
18225 +/* pxvi.s ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-4}++,${s2} */
18226 +  {
18227 +    UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "pxvi.s-d-indirect-with-pre-increment-4-s1-indirect-with-post-increment-4", "pxvi.s", 32,
18228 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18229 +  },
18230 +/* pxvi.s ${d-direct-addr},${s1-i4-4}(${s1-An})++,${s2} */
18231 +  {
18232 +    UBICOM32_INSN_PXVI_S_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4, "pxvi.s-d-direct-s1-indirect-with-pre-increment-4", "pxvi.s", 32,
18233 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18234 +  },
18235 +/* pxvi.s #${d-imm8},${s1-i4-4}(${s1-An})++,${s2} */
18236 +  {
18237 +    UBICOM32_INSN_PXVI_S_D_IMMEDIATE_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "pxvi.s-d-immediate-4-s1-indirect-with-pre-increment-4", "pxvi.s", 32,
18238 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18239 +  },
18240 +/* pxvi.s (${d-An},${d-r}),${s1-i4-4}(${s1-An})++,${s2} */
18241 +  {
18242 +    UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "pxvi.s-d-indirect-with-index-4-s1-indirect-with-pre-increment-4", "pxvi.s", 32,
18243 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18244 +  },
18245 +/* pxvi.s ${d-imm7-4}(${d-An}),${s1-i4-4}(${s1-An})++,${s2} */
18246 +  {
18247 +    UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "pxvi.s-d-indirect-with-offset-4-s1-indirect-with-pre-increment-4", "pxvi.s", 32,
18248 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18249 +  },
18250 +/* pxvi.s (${d-An}),${s1-i4-4}(${s1-An})++,${s2} */
18251 +  {
18252 +    UBICOM32_INSN_PXVI_S_D_INDIRECT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "pxvi.s-d-indirect-4-s1-indirect-with-pre-increment-4", "pxvi.s", 32,
18253 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18254 +  },
18255 +/* pxvi.s (${d-An})${d-i4-4}++,${s1-i4-4}(${s1-An})++,${s2} */
18256 +  {
18257 +    UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "pxvi.s-d-indirect-with-post-increment-4-s1-indirect-with-pre-increment-4", "pxvi.s", 32,
18258 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18259 +  },
18260 +/* pxvi.s ${d-i4-4}(${d-An})++,${s1-i4-4}(${s1-An})++,${s2} */
18261 +  {
18262 +    UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "pxvi.s-d-indirect-with-pre-increment-4-s1-indirect-with-pre-increment-4", "pxvi.s", 32,
18263 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18264 +  },
18265 +/* pxvi ${d-direct-addr},${s1-direct-addr},${s2} */
18266 +  {
18267 +    UBICOM32_INSN_PXVI_D_DIRECT_S1_DIRECT, "pxvi-d-direct-s1-direct", "pxvi", 32,
18268 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18269 +  },
18270 +/* pxvi #${d-imm8},${s1-direct-addr},${s2} */
18271 +  {
18272 +    UBICOM32_INSN_PXVI_D_IMMEDIATE_4_S1_DIRECT, "pxvi-d-immediate-4-s1-direct", "pxvi", 32,
18273 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18274 +  },
18275 +/* pxvi (${d-An},${d-r}),${s1-direct-addr},${s2} */
18276 +  {
18277 +    UBICOM32_INSN_PXVI_D_INDIRECT_WITH_INDEX_4_S1_DIRECT, "pxvi-d-indirect-with-index-4-s1-direct", "pxvi", 32,
18278 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18279 +  },
18280 +/* pxvi ${d-imm7-4}(${d-An}),${s1-direct-addr},${s2} */
18281 +  {
18282 +    UBICOM32_INSN_PXVI_D_INDIRECT_WITH_OFFSET_4_S1_DIRECT, "pxvi-d-indirect-with-offset-4-s1-direct", "pxvi", 32,
18283 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18284 +  },
18285 +/* pxvi (${d-An}),${s1-direct-addr},${s2} */
18286 +  {
18287 +    UBICOM32_INSN_PXVI_D_INDIRECT_4_S1_DIRECT, "pxvi-d-indirect-4-s1-direct", "pxvi", 32,
18288 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18289 +  },
18290 +/* pxvi (${d-An})${d-i4-4}++,${s1-direct-addr},${s2} */
18291 +  {
18292 +    UBICOM32_INSN_PXVI_D_INDIRECT_WITH_POST_INCREMENT_4_S1_DIRECT, "pxvi-d-indirect-with-post-increment-4-s1-direct", "pxvi", 32,
18293 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18294 +  },
18295 +/* pxvi ${d-i4-4}(${d-An})++,${s1-direct-addr},${s2} */
18296 +  {
18297 +    UBICOM32_INSN_PXVI_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_DIRECT, "pxvi-d-indirect-with-pre-increment-4-s1-direct", "pxvi", 32,
18298 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18299 +  },
18300 +/* pxvi ${d-direct-addr},#${s1-imm8},${s2} */
18301 +  {
18302 +    UBICOM32_INSN_PXVI_D_DIRECT_S1_IMMEDIATE, "pxvi-d-direct-s1-immediate", "pxvi", 32,
18303 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18304 +  },
18305 +/* pxvi #${d-imm8},#${s1-imm8},${s2} */
18306 +  {
18307 +    UBICOM32_INSN_PXVI_D_IMMEDIATE_4_S1_IMMEDIATE, "pxvi-d-immediate-4-s1-immediate", "pxvi", 32,
18308 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18309 +  },
18310 +/* pxvi (${d-An},${d-r}),#${s1-imm8},${s2} */
18311 +  {
18312 +    UBICOM32_INSN_PXVI_D_INDIRECT_WITH_INDEX_4_S1_IMMEDIATE, "pxvi-d-indirect-with-index-4-s1-immediate", "pxvi", 32,
18313 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18314 +  },
18315 +/* pxvi ${d-imm7-4}(${d-An}),#${s1-imm8},${s2} */
18316 +  {
18317 +    UBICOM32_INSN_PXVI_D_INDIRECT_WITH_OFFSET_4_S1_IMMEDIATE, "pxvi-d-indirect-with-offset-4-s1-immediate", "pxvi", 32,
18318 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18319 +  },
18320 +/* pxvi (${d-An}),#${s1-imm8},${s2} */
18321 +  {
18322 +    UBICOM32_INSN_PXVI_D_INDIRECT_4_S1_IMMEDIATE, "pxvi-d-indirect-4-s1-immediate", "pxvi", 32,
18323 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18324 +  },
18325 +/* pxvi (${d-An})${d-i4-4}++,#${s1-imm8},${s2} */
18326 +  {
18327 +    UBICOM32_INSN_PXVI_D_INDIRECT_WITH_POST_INCREMENT_4_S1_IMMEDIATE, "pxvi-d-indirect-with-post-increment-4-s1-immediate", "pxvi", 32,
18328 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18329 +  },
18330 +/* pxvi ${d-i4-4}(${d-An})++,#${s1-imm8},${s2} */
18331 +  {
18332 +    UBICOM32_INSN_PXVI_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_IMMEDIATE, "pxvi-d-indirect-with-pre-increment-4-s1-immediate", "pxvi", 32,
18333 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18334 +  },
18335 +/* pxvi ${d-direct-addr},(${s1-An},${s1-r}),${s2} */
18336 +  {
18337 +    UBICOM32_INSN_PXVI_D_DIRECT_S1_INDIRECT_WITH_INDEX_4, "pxvi-d-direct-s1-indirect-with-index-4", "pxvi", 32,
18338 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18339 +  },
18340 +/* pxvi #${d-imm8},(${s1-An},${s1-r}),${s2} */
18341 +  {
18342 +    UBICOM32_INSN_PXVI_D_IMMEDIATE_4_S1_INDIRECT_WITH_INDEX_4, "pxvi-d-immediate-4-s1-indirect-with-index-4", "pxvi", 32,
18343 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18344 +  },
18345 +/* pxvi (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */
18346 +  {
18347 +    UBICOM32_INSN_PXVI_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_INDEX_4, "pxvi-d-indirect-with-index-4-s1-indirect-with-index-4", "pxvi", 32,
18348 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18349 +  },
18350 +/* pxvi ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}),${s2} */
18351 +  {
18352 +    UBICOM32_INSN_PXVI_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_INDEX_4, "pxvi-d-indirect-with-offset-4-s1-indirect-with-index-4", "pxvi", 32,
18353 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18354 +  },
18355 +/* pxvi (${d-An}),(${s1-An},${s1-r}),${s2} */
18356 +  {
18357 +    UBICOM32_INSN_PXVI_D_INDIRECT_4_S1_INDIRECT_WITH_INDEX_4, "pxvi-d-indirect-4-s1-indirect-with-index-4", "pxvi", 32,
18358 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18359 +  },
18360 +/* pxvi (${d-An})${d-i4-4}++,(${s1-An},${s1-r}),${s2} */
18361 +  {
18362 +    UBICOM32_INSN_PXVI_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, "pxvi-d-indirect-with-post-increment-4-s1-indirect-with-index-4", "pxvi", 32,
18363 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18364 +  },
18365 +/* pxvi ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}),${s2} */
18366 +  {
18367 +    UBICOM32_INSN_PXVI_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, "pxvi-d-indirect-with-pre-increment-4-s1-indirect-with-index-4", "pxvi", 32,
18368 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18369 +  },
18370 +/* pxvi ${d-direct-addr},${s1-imm7-4}(${s1-An}),${s2} */
18371 +  {
18372 +    UBICOM32_INSN_PXVI_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4, "pxvi-d-direct-s1-indirect-with-offset-4", "pxvi", 32,
18373 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18374 +  },
18375 +/* pxvi #${d-imm8},${s1-imm7-4}(${s1-An}),${s2} */
18376 +  {
18377 +    UBICOM32_INSN_PXVI_D_IMMEDIATE_4_S1_INDIRECT_WITH_OFFSET_4, "pxvi-d-immediate-4-s1-indirect-with-offset-4", "pxvi", 32,
18378 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18379 +  },
18380 +/* pxvi (${d-An},${d-r}),${s1-imm7-4}(${s1-An}),${s2} */
18381 +  {
18382 +    UBICOM32_INSN_PXVI_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_OFFSET_4, "pxvi-d-indirect-with-index-4-s1-indirect-with-offset-4", "pxvi", 32,
18383 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18384 +  },
18385 +/* pxvi ${d-imm7-4}(${d-An}),${s1-imm7-4}(${s1-An}),${s2} */
18386 +  {
18387 +    UBICOM32_INSN_PXVI_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_OFFSET_4, "pxvi-d-indirect-with-offset-4-s1-indirect-with-offset-4", "pxvi", 32,
18388 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18389 +  },
18390 +/* pxvi (${d-An}),${s1-imm7-4}(${s1-An}),${s2} */
18391 +  {
18392 +    UBICOM32_INSN_PXVI_D_INDIRECT_4_S1_INDIRECT_WITH_OFFSET_4, "pxvi-d-indirect-4-s1-indirect-with-offset-4", "pxvi", 32,
18393 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18394 +  },
18395 +/* pxvi (${d-An})${d-i4-4}++,${s1-imm7-4}(${s1-An}),${s2} */
18396 +  {
18397 +    UBICOM32_INSN_PXVI_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, "pxvi-d-indirect-with-post-increment-4-s1-indirect-with-offset-4", "pxvi", 32,
18398 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18399 +  },
18400 +/* pxvi ${d-i4-4}(${d-An})++,${s1-imm7-4}(${s1-An}),${s2} */
18401 +  {
18402 +    UBICOM32_INSN_PXVI_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, "pxvi-d-indirect-with-pre-increment-4-s1-indirect-with-offset-4", "pxvi", 32,
18403 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18404 +  },
18405 +/* pxvi ${d-direct-addr},(${s1-An}),${s2} */
18406 +  {
18407 +    UBICOM32_INSN_PXVI_D_DIRECT_S1_INDIRECT_4, "pxvi-d-direct-s1-indirect-4", "pxvi", 32,
18408 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18409 +  },
18410 +/* pxvi #${d-imm8},(${s1-An}),${s2} */
18411 +  {
18412 +    UBICOM32_INSN_PXVI_D_IMMEDIATE_4_S1_INDIRECT_4, "pxvi-d-immediate-4-s1-indirect-4", "pxvi", 32,
18413 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18414 +  },
18415 +/* pxvi (${d-An},${d-r}),(${s1-An}),${s2} */
18416 +  {
18417 +    UBICOM32_INSN_PXVI_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_4, "pxvi-d-indirect-with-index-4-s1-indirect-4", "pxvi", 32,
18418 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18419 +  },
18420 +/* pxvi ${d-imm7-4}(${d-An}),(${s1-An}),${s2} */
18421 +  {
18422 +    UBICOM32_INSN_PXVI_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_4, "pxvi-d-indirect-with-offset-4-s1-indirect-4", "pxvi", 32,
18423 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18424 +  },
18425 +/* pxvi (${d-An}),(${s1-An}),${s2} */
18426 +  {
18427 +    UBICOM32_INSN_PXVI_D_INDIRECT_4_S1_INDIRECT_4, "pxvi-d-indirect-4-s1-indirect-4", "pxvi", 32,
18428 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18429 +  },
18430 +/* pxvi (${d-An})${d-i4-4}++,(${s1-An}),${s2} */
18431 +  {
18432 +    UBICOM32_INSN_PXVI_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_4, "pxvi-d-indirect-with-post-increment-4-s1-indirect-4", "pxvi", 32,
18433 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18434 +  },
18435 +/* pxvi ${d-i4-4}(${d-An})++,(${s1-An}),${s2} */
18436 +  {
18437 +    UBICOM32_INSN_PXVI_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_4, "pxvi-d-indirect-with-pre-increment-4-s1-indirect-4", "pxvi", 32,
18438 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18439 +  },
18440 +/* pxvi ${d-direct-addr},(${s1-An})${s1-i4-4}++,${s2} */
18441 +  {
18442 +    UBICOM32_INSN_PXVI_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4, "pxvi-d-direct-s1-indirect-with-post-increment-4", "pxvi", 32,
18443 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18444 +  },
18445 +/* pxvi #${d-imm8},(${s1-An})${s1-i4-4}++,${s2} */
18446 +  {
18447 +    UBICOM32_INSN_PXVI_D_IMMEDIATE_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "pxvi-d-immediate-4-s1-indirect-with-post-increment-4", "pxvi", 32,
18448 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18449 +  },
18450 +/* pxvi (${d-An},${d-r}),(${s1-An})${s1-i4-4}++,${s2} */
18451 +  {
18452 +    UBICOM32_INSN_PXVI_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "pxvi-d-indirect-with-index-4-s1-indirect-with-post-increment-4", "pxvi", 32,
18453 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18454 +  },
18455 +/* pxvi ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-4}++,${s2} */
18456 +  {
18457 +    UBICOM32_INSN_PXVI_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "pxvi-d-indirect-with-offset-4-s1-indirect-with-post-increment-4", "pxvi", 32,
18458 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18459 +  },
18460 +/* pxvi (${d-An}),(${s1-An})${s1-i4-4}++,${s2} */
18461 +  {
18462 +    UBICOM32_INSN_PXVI_D_INDIRECT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "pxvi-d-indirect-4-s1-indirect-with-post-increment-4", "pxvi", 32,
18463 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18464 +  },
18465 +/* pxvi (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-4}++,${s2} */
18466 +  {
18467 +    UBICOM32_INSN_PXVI_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "pxvi-d-indirect-with-post-increment-4-s1-indirect-with-post-increment-4", "pxvi", 32,
18468 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18469 +  },
18470 +/* pxvi ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-4}++,${s2} */
18471 +  {
18472 +    UBICOM32_INSN_PXVI_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "pxvi-d-indirect-with-pre-increment-4-s1-indirect-with-post-increment-4", "pxvi", 32,
18473 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18474 +  },
18475 +/* pxvi ${d-direct-addr},${s1-i4-4}(${s1-An})++,${s2} */
18476 +  {
18477 +    UBICOM32_INSN_PXVI_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4, "pxvi-d-direct-s1-indirect-with-pre-increment-4", "pxvi", 32,
18478 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18479 +  },
18480 +/* pxvi #${d-imm8},${s1-i4-4}(${s1-An})++,${s2} */
18481 +  {
18482 +    UBICOM32_INSN_PXVI_D_IMMEDIATE_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "pxvi-d-immediate-4-s1-indirect-with-pre-increment-4", "pxvi", 32,
18483 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18484 +  },
18485 +/* pxvi (${d-An},${d-r}),${s1-i4-4}(${s1-An})++,${s2} */
18486 +  {
18487 +    UBICOM32_INSN_PXVI_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "pxvi-d-indirect-with-index-4-s1-indirect-with-pre-increment-4", "pxvi", 32,
18488 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18489 +  },
18490 +/* pxvi ${d-imm7-4}(${d-An}),${s1-i4-4}(${s1-An})++,${s2} */
18491 +  {
18492 +    UBICOM32_INSN_PXVI_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "pxvi-d-indirect-with-offset-4-s1-indirect-with-pre-increment-4", "pxvi", 32,
18493 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18494 +  },
18495 +/* pxvi (${d-An}),${s1-i4-4}(${s1-An})++,${s2} */
18496 +  {
18497 +    UBICOM32_INSN_PXVI_D_INDIRECT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "pxvi-d-indirect-4-s1-indirect-with-pre-increment-4", "pxvi", 32,
18498 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18499 +  },
18500 +/* pxvi (${d-An})${d-i4-4}++,${s1-i4-4}(${s1-An})++,${s2} */
18501 +  {
18502 +    UBICOM32_INSN_PXVI_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "pxvi-d-indirect-with-post-increment-4-s1-indirect-with-pre-increment-4", "pxvi", 32,
18503 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18504 +  },
18505 +/* pxvi ${d-i4-4}(${d-An})++,${s1-i4-4}(${s1-An})++,${s2} */
18506 +  {
18507 +    UBICOM32_INSN_PXVI_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "pxvi-d-indirect-with-pre-increment-4-s1-indirect-with-pre-increment-4", "pxvi", 32,
18508 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18509 +  },
18510 +/* pxblend.t ${d-direct-addr},${s1-direct-addr},${s2} */
18511 +  {
18512 +    UBICOM32_INSN_PXBLEND_T_D_DIRECT_S1_DIRECT, "pxblend.t-d-direct-s1-direct", "pxblend.t", 32,
18513 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18514 +  },
18515 +/* pxblend.t #${d-imm8},${s1-direct-addr},${s2} */
18516 +  {
18517 +    UBICOM32_INSN_PXBLEND_T_D_IMMEDIATE_4_S1_DIRECT, "pxblend.t-d-immediate-4-s1-direct", "pxblend.t", 32,
18518 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18519 +  },
18520 +/* pxblend.t (${d-An},${d-r}),${s1-direct-addr},${s2} */
18521 +  {
18522 +    UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_INDEX_4_S1_DIRECT, "pxblend.t-d-indirect-with-index-4-s1-direct", "pxblend.t", 32,
18523 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18524 +  },
18525 +/* pxblend.t ${d-imm7-4}(${d-An}),${s1-direct-addr},${s2} */
18526 +  {
18527 +    UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_OFFSET_4_S1_DIRECT, "pxblend.t-d-indirect-with-offset-4-s1-direct", "pxblend.t", 32,
18528 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18529 +  },
18530 +/* pxblend.t (${d-An}),${s1-direct-addr},${s2} */
18531 +  {
18532 +    UBICOM32_INSN_PXBLEND_T_D_INDIRECT_4_S1_DIRECT, "pxblend.t-d-indirect-4-s1-direct", "pxblend.t", 32,
18533 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18534 +  },
18535 +/* pxblend.t (${d-An})${d-i4-4}++,${s1-direct-addr},${s2} */
18536 +  {
18537 +    UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_POST_INCREMENT_4_S1_DIRECT, "pxblend.t-d-indirect-with-post-increment-4-s1-direct", "pxblend.t", 32,
18538 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18539 +  },
18540 +/* pxblend.t ${d-i4-4}(${d-An})++,${s1-direct-addr},${s2} */
18541 +  {
18542 +    UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_DIRECT, "pxblend.t-d-indirect-with-pre-increment-4-s1-direct", "pxblend.t", 32,
18543 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18544 +  },
18545 +/* pxblend.t ${d-direct-addr},#${s1-imm8},${s2} */
18546 +  {
18547 +    UBICOM32_INSN_PXBLEND_T_D_DIRECT_S1_IMMEDIATE, "pxblend.t-d-direct-s1-immediate", "pxblend.t", 32,
18548 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18549 +  },
18550 +/* pxblend.t #${d-imm8},#${s1-imm8},${s2} */
18551 +  {
18552 +    UBICOM32_INSN_PXBLEND_T_D_IMMEDIATE_4_S1_IMMEDIATE, "pxblend.t-d-immediate-4-s1-immediate", "pxblend.t", 32,
18553 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18554 +  },
18555 +/* pxblend.t (${d-An},${d-r}),#${s1-imm8},${s2} */
18556 +  {
18557 +    UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_INDEX_4_S1_IMMEDIATE, "pxblend.t-d-indirect-with-index-4-s1-immediate", "pxblend.t", 32,
18558 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18559 +  },
18560 +/* pxblend.t ${d-imm7-4}(${d-An}),#${s1-imm8},${s2} */
18561 +  {
18562 +    UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_OFFSET_4_S1_IMMEDIATE, "pxblend.t-d-indirect-with-offset-4-s1-immediate", "pxblend.t", 32,
18563 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18564 +  },
18565 +/* pxblend.t (${d-An}),#${s1-imm8},${s2} */
18566 +  {
18567 +    UBICOM32_INSN_PXBLEND_T_D_INDIRECT_4_S1_IMMEDIATE, "pxblend.t-d-indirect-4-s1-immediate", "pxblend.t", 32,
18568 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18569 +  },
18570 +/* pxblend.t (${d-An})${d-i4-4}++,#${s1-imm8},${s2} */
18571 +  {
18572 +    UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_POST_INCREMENT_4_S1_IMMEDIATE, "pxblend.t-d-indirect-with-post-increment-4-s1-immediate", "pxblend.t", 32,
18573 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18574 +  },
18575 +/* pxblend.t ${d-i4-4}(${d-An})++,#${s1-imm8},${s2} */
18576 +  {
18577 +    UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_IMMEDIATE, "pxblend.t-d-indirect-with-pre-increment-4-s1-immediate", "pxblend.t", 32,
18578 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18579 +  },
18580 +/* pxblend.t ${d-direct-addr},(${s1-An},${s1-r}),${s2} */
18581 +  {
18582 +    UBICOM32_INSN_PXBLEND_T_D_DIRECT_S1_INDIRECT_WITH_INDEX_4, "pxblend.t-d-direct-s1-indirect-with-index-4", "pxblend.t", 32,
18583 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18584 +  },
18585 +/* pxblend.t #${d-imm8},(${s1-An},${s1-r}),${s2} */
18586 +  {
18587 +    UBICOM32_INSN_PXBLEND_T_D_IMMEDIATE_4_S1_INDIRECT_WITH_INDEX_4, "pxblend.t-d-immediate-4-s1-indirect-with-index-4", "pxblend.t", 32,
18588 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18589 +  },
18590 +/* pxblend.t (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */
18591 +  {
18592 +    UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_INDEX_4, "pxblend.t-d-indirect-with-index-4-s1-indirect-with-index-4", "pxblend.t", 32,
18593 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18594 +  },
18595 +/* pxblend.t ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}),${s2} */
18596 +  {
18597 +    UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_INDEX_4, "pxblend.t-d-indirect-with-offset-4-s1-indirect-with-index-4", "pxblend.t", 32,
18598 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18599 +  },
18600 +/* pxblend.t (${d-An}),(${s1-An},${s1-r}),${s2} */
18601 +  {
18602 +    UBICOM32_INSN_PXBLEND_T_D_INDIRECT_4_S1_INDIRECT_WITH_INDEX_4, "pxblend.t-d-indirect-4-s1-indirect-with-index-4", "pxblend.t", 32,
18603 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18604 +  },
18605 +/* pxblend.t (${d-An})${d-i4-4}++,(${s1-An},${s1-r}),${s2} */
18606 +  {
18607 +    UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, "pxblend.t-d-indirect-with-post-increment-4-s1-indirect-with-index-4", "pxblend.t", 32,
18608 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18609 +  },
18610 +/* pxblend.t ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}),${s2} */
18611 +  {
18612 +    UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, "pxblend.t-d-indirect-with-pre-increment-4-s1-indirect-with-index-4", "pxblend.t", 32,
18613 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18614 +  },
18615 +/* pxblend.t ${d-direct-addr},${s1-imm7-4}(${s1-An}),${s2} */
18616 +  {
18617 +    UBICOM32_INSN_PXBLEND_T_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4, "pxblend.t-d-direct-s1-indirect-with-offset-4", "pxblend.t", 32,
18618 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18619 +  },
18620 +/* pxblend.t #${d-imm8},${s1-imm7-4}(${s1-An}),${s2} */
18621 +  {
18622 +    UBICOM32_INSN_PXBLEND_T_D_IMMEDIATE_4_S1_INDIRECT_WITH_OFFSET_4, "pxblend.t-d-immediate-4-s1-indirect-with-offset-4", "pxblend.t", 32,
18623 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18624 +  },
18625 +/* pxblend.t (${d-An},${d-r}),${s1-imm7-4}(${s1-An}),${s2} */
18626 +  {
18627 +    UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_OFFSET_4, "pxblend.t-d-indirect-with-index-4-s1-indirect-with-offset-4", "pxblend.t", 32,
18628 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18629 +  },
18630 +/* pxblend.t ${d-imm7-4}(${d-An}),${s1-imm7-4}(${s1-An}),${s2} */
18631 +  {
18632 +    UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_OFFSET_4, "pxblend.t-d-indirect-with-offset-4-s1-indirect-with-offset-4", "pxblend.t", 32,
18633 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18634 +  },
18635 +/* pxblend.t (${d-An}),${s1-imm7-4}(${s1-An}),${s2} */
18636 +  {
18637 +    UBICOM32_INSN_PXBLEND_T_D_INDIRECT_4_S1_INDIRECT_WITH_OFFSET_4, "pxblend.t-d-indirect-4-s1-indirect-with-offset-4", "pxblend.t", 32,
18638 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18639 +  },
18640 +/* pxblend.t (${d-An})${d-i4-4}++,${s1-imm7-4}(${s1-An}),${s2} */
18641 +  {
18642 +    UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, "pxblend.t-d-indirect-with-post-increment-4-s1-indirect-with-offset-4", "pxblend.t", 32,
18643 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18644 +  },
18645 +/* pxblend.t ${d-i4-4}(${d-An})++,${s1-imm7-4}(${s1-An}),${s2} */
18646 +  {
18647 +    UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, "pxblend.t-d-indirect-with-pre-increment-4-s1-indirect-with-offset-4", "pxblend.t", 32,
18648 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18649 +  },
18650 +/* pxblend.t ${d-direct-addr},(${s1-An}),${s2} */
18651 +  {
18652 +    UBICOM32_INSN_PXBLEND_T_D_DIRECT_S1_INDIRECT_4, "pxblend.t-d-direct-s1-indirect-4", "pxblend.t", 32,
18653 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18654 +  },
18655 +/* pxblend.t #${d-imm8},(${s1-An}),${s2} */
18656 +  {
18657 +    UBICOM32_INSN_PXBLEND_T_D_IMMEDIATE_4_S1_INDIRECT_4, "pxblend.t-d-immediate-4-s1-indirect-4", "pxblend.t", 32,
18658 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18659 +  },
18660 +/* pxblend.t (${d-An},${d-r}),(${s1-An}),${s2} */
18661 +  {
18662 +    UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_4, "pxblend.t-d-indirect-with-index-4-s1-indirect-4", "pxblend.t", 32,
18663 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18664 +  },
18665 +/* pxblend.t ${d-imm7-4}(${d-An}),(${s1-An}),${s2} */
18666 +  {
18667 +    UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_4, "pxblend.t-d-indirect-with-offset-4-s1-indirect-4", "pxblend.t", 32,
18668 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18669 +  },
18670 +/* pxblend.t (${d-An}),(${s1-An}),${s2} */
18671 +  {
18672 +    UBICOM32_INSN_PXBLEND_T_D_INDIRECT_4_S1_INDIRECT_4, "pxblend.t-d-indirect-4-s1-indirect-4", "pxblend.t", 32,
18673 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18674 +  },
18675 +/* pxblend.t (${d-An})${d-i4-4}++,(${s1-An}),${s2} */
18676 +  {
18677 +    UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_4, "pxblend.t-d-indirect-with-post-increment-4-s1-indirect-4", "pxblend.t", 32,
18678 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18679 +  },
18680 +/* pxblend.t ${d-i4-4}(${d-An})++,(${s1-An}),${s2} */
18681 +  {
18682 +    UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_4, "pxblend.t-d-indirect-with-pre-increment-4-s1-indirect-4", "pxblend.t", 32,
18683 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18684 +  },
18685 +/* pxblend.t ${d-direct-addr},(${s1-An})${s1-i4-4}++,${s2} */
18686 +  {
18687 +    UBICOM32_INSN_PXBLEND_T_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4, "pxblend.t-d-direct-s1-indirect-with-post-increment-4", "pxblend.t", 32,
18688 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18689 +  },
18690 +/* pxblend.t #${d-imm8},(${s1-An})${s1-i4-4}++,${s2} */
18691 +  {
18692 +    UBICOM32_INSN_PXBLEND_T_D_IMMEDIATE_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "pxblend.t-d-immediate-4-s1-indirect-with-post-increment-4", "pxblend.t", 32,
18693 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18694 +  },
18695 +/* pxblend.t (${d-An},${d-r}),(${s1-An})${s1-i4-4}++,${s2} */
18696 +  {
18697 +    UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "pxblend.t-d-indirect-with-index-4-s1-indirect-with-post-increment-4", "pxblend.t", 32,
18698 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18699 +  },
18700 +/* pxblend.t ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-4}++,${s2} */
18701 +  {
18702 +    UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "pxblend.t-d-indirect-with-offset-4-s1-indirect-with-post-increment-4", "pxblend.t", 32,
18703 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18704 +  },
18705 +/* pxblend.t (${d-An}),(${s1-An})${s1-i4-4}++,${s2} */
18706 +  {
18707 +    UBICOM32_INSN_PXBLEND_T_D_INDIRECT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "pxblend.t-d-indirect-4-s1-indirect-with-post-increment-4", "pxblend.t", 32,
18708 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18709 +  },
18710 +/* pxblend.t (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-4}++,${s2} */
18711 +  {
18712 +    UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "pxblend.t-d-indirect-with-post-increment-4-s1-indirect-with-post-increment-4", "pxblend.t", 32,
18713 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18714 +  },
18715 +/* pxblend.t ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-4}++,${s2} */
18716 +  {
18717 +    UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "pxblend.t-d-indirect-with-pre-increment-4-s1-indirect-with-post-increment-4", "pxblend.t", 32,
18718 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18719 +  },
18720 +/* pxblend.t ${d-direct-addr},${s1-i4-4}(${s1-An})++,${s2} */
18721 +  {
18722 +    UBICOM32_INSN_PXBLEND_T_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4, "pxblend.t-d-direct-s1-indirect-with-pre-increment-4", "pxblend.t", 32,
18723 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18724 +  },
18725 +/* pxblend.t #${d-imm8},${s1-i4-4}(${s1-An})++,${s2} */
18726 +  {
18727 +    UBICOM32_INSN_PXBLEND_T_D_IMMEDIATE_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "pxblend.t-d-immediate-4-s1-indirect-with-pre-increment-4", "pxblend.t", 32,
18728 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18729 +  },
18730 +/* pxblend.t (${d-An},${d-r}),${s1-i4-4}(${s1-An})++,${s2} */
18731 +  {
18732 +    UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "pxblend.t-d-indirect-with-index-4-s1-indirect-with-pre-increment-4", "pxblend.t", 32,
18733 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18734 +  },
18735 +/* pxblend.t ${d-imm7-4}(${d-An}),${s1-i4-4}(${s1-An})++,${s2} */
18736 +  {
18737 +    UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "pxblend.t-d-indirect-with-offset-4-s1-indirect-with-pre-increment-4", "pxblend.t", 32,
18738 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18739 +  },
18740 +/* pxblend.t (${d-An}),${s1-i4-4}(${s1-An})++,${s2} */
18741 +  {
18742 +    UBICOM32_INSN_PXBLEND_T_D_INDIRECT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "pxblend.t-d-indirect-4-s1-indirect-with-pre-increment-4", "pxblend.t", 32,
18743 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18744 +  },
18745 +/* pxblend.t (${d-An})${d-i4-4}++,${s1-i4-4}(${s1-An})++,${s2} */
18746 +  {
18747 +    UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "pxblend.t-d-indirect-with-post-increment-4-s1-indirect-with-pre-increment-4", "pxblend.t", 32,
18748 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18749 +  },
18750 +/* pxblend.t ${d-i4-4}(${d-An})++,${s1-i4-4}(${s1-An})++,${s2} */
18751 +  {
18752 +    UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "pxblend.t-d-indirect-with-pre-increment-4-s1-indirect-with-pre-increment-4", "pxblend.t", 32,
18753 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18754 +  },
18755 +/* pxblend ${d-direct-addr},${s1-direct-addr},${s2} */
18756 +  {
18757 +    UBICOM32_INSN_PXBLEND_D_DIRECT_S1_DIRECT, "pxblend-d-direct-s1-direct", "pxblend", 32,
18758 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18759 +  },
18760 +/* pxblend #${d-imm8},${s1-direct-addr},${s2} */
18761 +  {
18762 +    UBICOM32_INSN_PXBLEND_D_IMMEDIATE_4_S1_DIRECT, "pxblend-d-immediate-4-s1-direct", "pxblend", 32,
18763 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18764 +  },
18765 +/* pxblend (${d-An},${d-r}),${s1-direct-addr},${s2} */
18766 +  {
18767 +    UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_INDEX_4_S1_DIRECT, "pxblend-d-indirect-with-index-4-s1-direct", "pxblend", 32,
18768 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18769 +  },
18770 +/* pxblend ${d-imm7-4}(${d-An}),${s1-direct-addr},${s2} */
18771 +  {
18772 +    UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_OFFSET_4_S1_DIRECT, "pxblend-d-indirect-with-offset-4-s1-direct", "pxblend", 32,
18773 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18774 +  },
18775 +/* pxblend (${d-An}),${s1-direct-addr},${s2} */
18776 +  {
18777 +    UBICOM32_INSN_PXBLEND_D_INDIRECT_4_S1_DIRECT, "pxblend-d-indirect-4-s1-direct", "pxblend", 32,
18778 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18779 +  },
18780 +/* pxblend (${d-An})${d-i4-4}++,${s1-direct-addr},${s2} */
18781 +  {
18782 +    UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_POST_INCREMENT_4_S1_DIRECT, "pxblend-d-indirect-with-post-increment-4-s1-direct", "pxblend", 32,
18783 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18784 +  },
18785 +/* pxblend ${d-i4-4}(${d-An})++,${s1-direct-addr},${s2} */
18786 +  {
18787 +    UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_DIRECT, "pxblend-d-indirect-with-pre-increment-4-s1-direct", "pxblend", 32,
18788 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18789 +  },
18790 +/* pxblend ${d-direct-addr},#${s1-imm8},${s2} */
18791 +  {
18792 +    UBICOM32_INSN_PXBLEND_D_DIRECT_S1_IMMEDIATE, "pxblend-d-direct-s1-immediate", "pxblend", 32,
18793 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18794 +  },
18795 +/* pxblend #${d-imm8},#${s1-imm8},${s2} */
18796 +  {
18797 +    UBICOM32_INSN_PXBLEND_D_IMMEDIATE_4_S1_IMMEDIATE, "pxblend-d-immediate-4-s1-immediate", "pxblend", 32,
18798 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18799 +  },
18800 +/* pxblend (${d-An},${d-r}),#${s1-imm8},${s2} */
18801 +  {
18802 +    UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_INDEX_4_S1_IMMEDIATE, "pxblend-d-indirect-with-index-4-s1-immediate", "pxblend", 32,
18803 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18804 +  },
18805 +/* pxblend ${d-imm7-4}(${d-An}),#${s1-imm8},${s2} */
18806 +  {
18807 +    UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_OFFSET_4_S1_IMMEDIATE, "pxblend-d-indirect-with-offset-4-s1-immediate", "pxblend", 32,
18808 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18809 +  },
18810 +/* pxblend (${d-An}),#${s1-imm8},${s2} */
18811 +  {
18812 +    UBICOM32_INSN_PXBLEND_D_INDIRECT_4_S1_IMMEDIATE, "pxblend-d-indirect-4-s1-immediate", "pxblend", 32,
18813 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18814 +  },
18815 +/* pxblend (${d-An})${d-i4-4}++,#${s1-imm8},${s2} */
18816 +  {
18817 +    UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_POST_INCREMENT_4_S1_IMMEDIATE, "pxblend-d-indirect-with-post-increment-4-s1-immediate", "pxblend", 32,
18818 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18819 +  },
18820 +/* pxblend ${d-i4-4}(${d-An})++,#${s1-imm8},${s2} */
18821 +  {
18822 +    UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_IMMEDIATE, "pxblend-d-indirect-with-pre-increment-4-s1-immediate", "pxblend", 32,
18823 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18824 +  },
18825 +/* pxblend ${d-direct-addr},(${s1-An},${s1-r}),${s2} */
18826 +  {
18827 +    UBICOM32_INSN_PXBLEND_D_DIRECT_S1_INDIRECT_WITH_INDEX_4, "pxblend-d-direct-s1-indirect-with-index-4", "pxblend", 32,
18828 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18829 +  },
18830 +/* pxblend #${d-imm8},(${s1-An},${s1-r}),${s2} */
18831 +  {
18832 +    UBICOM32_INSN_PXBLEND_D_IMMEDIATE_4_S1_INDIRECT_WITH_INDEX_4, "pxblend-d-immediate-4-s1-indirect-with-index-4", "pxblend", 32,
18833 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18834 +  },
18835 +/* pxblend (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */
18836 +  {
18837 +    UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_INDEX_4, "pxblend-d-indirect-with-index-4-s1-indirect-with-index-4", "pxblend", 32,
18838 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18839 +  },
18840 +/* pxblend ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}),${s2} */
18841 +  {
18842 +    UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_INDEX_4, "pxblend-d-indirect-with-offset-4-s1-indirect-with-index-4", "pxblend", 32,
18843 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18844 +  },
18845 +/* pxblend (${d-An}),(${s1-An},${s1-r}),${s2} */
18846 +  {
18847 +    UBICOM32_INSN_PXBLEND_D_INDIRECT_4_S1_INDIRECT_WITH_INDEX_4, "pxblend-d-indirect-4-s1-indirect-with-index-4", "pxblend", 32,
18848 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18849 +  },
18850 +/* pxblend (${d-An})${d-i4-4}++,(${s1-An},${s1-r}),${s2} */
18851 +  {
18852 +    UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, "pxblend-d-indirect-with-post-increment-4-s1-indirect-with-index-4", "pxblend", 32,
18853 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18854 +  },
18855 +/* pxblend ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}),${s2} */
18856 +  {
18857 +    UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, "pxblend-d-indirect-with-pre-increment-4-s1-indirect-with-index-4", "pxblend", 32,
18858 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18859 +  },
18860 +/* pxblend ${d-direct-addr},${s1-imm7-4}(${s1-An}),${s2} */
18861 +  {
18862 +    UBICOM32_INSN_PXBLEND_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4, "pxblend-d-direct-s1-indirect-with-offset-4", "pxblend", 32,
18863 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18864 +  },
18865 +/* pxblend #${d-imm8},${s1-imm7-4}(${s1-An}),${s2} */
18866 +  {
18867 +    UBICOM32_INSN_PXBLEND_D_IMMEDIATE_4_S1_INDIRECT_WITH_OFFSET_4, "pxblend-d-immediate-4-s1-indirect-with-offset-4", "pxblend", 32,
18868 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18869 +  },
18870 +/* pxblend (${d-An},${d-r}),${s1-imm7-4}(${s1-An}),${s2} */
18871 +  {
18872 +    UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_OFFSET_4, "pxblend-d-indirect-with-index-4-s1-indirect-with-offset-4", "pxblend", 32,
18873 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18874 +  },
18875 +/* pxblend ${d-imm7-4}(${d-An}),${s1-imm7-4}(${s1-An}),${s2} */
18876 +  {
18877 +    UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_OFFSET_4, "pxblend-d-indirect-with-offset-4-s1-indirect-with-offset-4", "pxblend", 32,
18878 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18879 +  },
18880 +/* pxblend (${d-An}),${s1-imm7-4}(${s1-An}),${s2} */
18881 +  {
18882 +    UBICOM32_INSN_PXBLEND_D_INDIRECT_4_S1_INDIRECT_WITH_OFFSET_4, "pxblend-d-indirect-4-s1-indirect-with-offset-4", "pxblend", 32,
18883 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18884 +  },
18885 +/* pxblend (${d-An})${d-i4-4}++,${s1-imm7-4}(${s1-An}),${s2} */
18886 +  {
18887 +    UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, "pxblend-d-indirect-with-post-increment-4-s1-indirect-with-offset-4", "pxblend", 32,
18888 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18889 +  },
18890 +/* pxblend ${d-i4-4}(${d-An})++,${s1-imm7-4}(${s1-An}),${s2} */
18891 +  {
18892 +    UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, "pxblend-d-indirect-with-pre-increment-4-s1-indirect-with-offset-4", "pxblend", 32,
18893 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18894 +  },
18895 +/* pxblend ${d-direct-addr},(${s1-An}),${s2} */
18896 +  {
18897 +    UBICOM32_INSN_PXBLEND_D_DIRECT_S1_INDIRECT_4, "pxblend-d-direct-s1-indirect-4", "pxblend", 32,
18898 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18899 +  },
18900 +/* pxblend #${d-imm8},(${s1-An}),${s2} */
18901 +  {
18902 +    UBICOM32_INSN_PXBLEND_D_IMMEDIATE_4_S1_INDIRECT_4, "pxblend-d-immediate-4-s1-indirect-4", "pxblend", 32,
18903 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18904 +  },
18905 +/* pxblend (${d-An},${d-r}),(${s1-An}),${s2} */
18906 +  {
18907 +    UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_4, "pxblend-d-indirect-with-index-4-s1-indirect-4", "pxblend", 32,
18908 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18909 +  },
18910 +/* pxblend ${d-imm7-4}(${d-An}),(${s1-An}),${s2} */
18911 +  {
18912 +    UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_4, "pxblend-d-indirect-with-offset-4-s1-indirect-4", "pxblend", 32,
18913 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18914 +  },
18915 +/* pxblend (${d-An}),(${s1-An}),${s2} */
18916 +  {
18917 +    UBICOM32_INSN_PXBLEND_D_INDIRECT_4_S1_INDIRECT_4, "pxblend-d-indirect-4-s1-indirect-4", "pxblend", 32,
18918 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18919 +  },
18920 +/* pxblend (${d-An})${d-i4-4}++,(${s1-An}),${s2} */
18921 +  {
18922 +    UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_4, "pxblend-d-indirect-with-post-increment-4-s1-indirect-4", "pxblend", 32,
18923 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18924 +  },
18925 +/* pxblend ${d-i4-4}(${d-An})++,(${s1-An}),${s2} */
18926 +  {
18927 +    UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_4, "pxblend-d-indirect-with-pre-increment-4-s1-indirect-4", "pxblend", 32,
18928 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18929 +  },
18930 +/* pxblend ${d-direct-addr},(${s1-An})${s1-i4-4}++,${s2} */
18931 +  {
18932 +    UBICOM32_INSN_PXBLEND_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4, "pxblend-d-direct-s1-indirect-with-post-increment-4", "pxblend", 32,
18933 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18934 +  },
18935 +/* pxblend #${d-imm8},(${s1-An})${s1-i4-4}++,${s2} */
18936 +  {
18937 +    UBICOM32_INSN_PXBLEND_D_IMMEDIATE_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "pxblend-d-immediate-4-s1-indirect-with-post-increment-4", "pxblend", 32,
18938 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18939 +  },
18940 +/* pxblend (${d-An},${d-r}),(${s1-An})${s1-i4-4}++,${s2} */
18941 +  {
18942 +    UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "pxblend-d-indirect-with-index-4-s1-indirect-with-post-increment-4", "pxblend", 32,
18943 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18944 +  },
18945 +/* pxblend ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-4}++,${s2} */
18946 +  {
18947 +    UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "pxblend-d-indirect-with-offset-4-s1-indirect-with-post-increment-4", "pxblend", 32,
18948 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18949 +  },
18950 +/* pxblend (${d-An}),(${s1-An})${s1-i4-4}++,${s2} */
18951 +  {
18952 +    UBICOM32_INSN_PXBLEND_D_INDIRECT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "pxblend-d-indirect-4-s1-indirect-with-post-increment-4", "pxblend", 32,
18953 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18954 +  },
18955 +/* pxblend (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-4}++,${s2} */
18956 +  {
18957 +    UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "pxblend-d-indirect-with-post-increment-4-s1-indirect-with-post-increment-4", "pxblend", 32,
18958 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18959 +  },
18960 +/* pxblend ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-4}++,${s2} */
18961 +  {
18962 +    UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "pxblend-d-indirect-with-pre-increment-4-s1-indirect-with-post-increment-4", "pxblend", 32,
18963 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18964 +  },
18965 +/* pxblend ${d-direct-addr},${s1-i4-4}(${s1-An})++,${s2} */
18966 +  {
18967 +    UBICOM32_INSN_PXBLEND_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4, "pxblend-d-direct-s1-indirect-with-pre-increment-4", "pxblend", 32,
18968 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18969 +  },
18970 +/* pxblend #${d-imm8},${s1-i4-4}(${s1-An})++,${s2} */
18971 +  {
18972 +    UBICOM32_INSN_PXBLEND_D_IMMEDIATE_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "pxblend-d-immediate-4-s1-indirect-with-pre-increment-4", "pxblend", 32,
18973 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18974 +  },
18975 +/* pxblend (${d-An},${d-r}),${s1-i4-4}(${s1-An})++,${s2} */
18976 +  {
18977 +    UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "pxblend-d-indirect-with-index-4-s1-indirect-with-pre-increment-4", "pxblend", 32,
18978 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18979 +  },
18980 +/* pxblend ${d-imm7-4}(${d-An}),${s1-i4-4}(${s1-An})++,${s2} */
18981 +  {
18982 +    UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "pxblend-d-indirect-with-offset-4-s1-indirect-with-pre-increment-4", "pxblend", 32,
18983 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18984 +  },
18985 +/* pxblend (${d-An}),${s1-i4-4}(${s1-An})++,${s2} */
18986 +  {
18987 +    UBICOM32_INSN_PXBLEND_D_INDIRECT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "pxblend-d-indirect-4-s1-indirect-with-pre-increment-4", "pxblend", 32,
18988 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18989 +  },
18990 +/* pxblend (${d-An})${d-i4-4}++,${s1-i4-4}(${s1-An})++,${s2} */
18991 +  {
18992 +    UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "pxblend-d-indirect-with-post-increment-4-s1-indirect-with-pre-increment-4", "pxblend", 32,
18993 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18994 +  },
18995 +/* pxblend ${d-i4-4}(${d-An})++,${s1-i4-4}(${s1-An})++,${s2} */
18996 +  {
18997 +    UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "pxblend-d-indirect-with-pre-increment-4-s1-indirect-with-pre-increment-4", "pxblend", 32,
18998 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
18999 +  },
19000 +/* pxcnv.t ${d-direct-addr},${s1-direct-addr} */
19001 +  {
19002 +    UBICOM32_INSN_PXCNV_T_D_DIRECT_S1_DIRECT, "pxcnv.t-d-direct-s1-direct", "pxcnv.t", 32,
19003 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19004 +  },
19005 +/* pxcnv.t #${d-imm8},${s1-direct-addr} */
19006 +  {
19007 +    UBICOM32_INSN_PXCNV_T_D_IMMEDIATE_2_S1_DIRECT, "pxcnv.t-d-immediate-2-s1-direct", "pxcnv.t", 32,
19008 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19009 +  },
19010 +/* pxcnv.t (${d-An},${d-r}),${s1-direct-addr} */
19011 +  {
19012 +    UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_INDEX_2_S1_DIRECT, "pxcnv.t-d-indirect-with-index-2-s1-direct", "pxcnv.t", 32,
19013 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19014 +  },
19015 +/* pxcnv.t ${d-imm7-2}(${d-An}),${s1-direct-addr} */
19016 +  {
19017 +    UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_OFFSET_2_S1_DIRECT, "pxcnv.t-d-indirect-with-offset-2-s1-direct", "pxcnv.t", 32,
19018 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19019 +  },
19020 +/* pxcnv.t (${d-An}),${s1-direct-addr} */
19021 +  {
19022 +    UBICOM32_INSN_PXCNV_T_D_INDIRECT_2_S1_DIRECT, "pxcnv.t-d-indirect-2-s1-direct", "pxcnv.t", 32,
19023 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19024 +  },
19025 +/* pxcnv.t (${d-An})${d-i4-2}++,${s1-direct-addr} */
19026 +  {
19027 +    UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_POST_INCREMENT_2_S1_DIRECT, "pxcnv.t-d-indirect-with-post-increment-2-s1-direct", "pxcnv.t", 32,
19028 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19029 +  },
19030 +/* pxcnv.t ${d-i4-2}(${d-An})++,${s1-direct-addr} */
19031 +  {
19032 +    UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_DIRECT, "pxcnv.t-d-indirect-with-pre-increment-2-s1-direct", "pxcnv.t", 32,
19033 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19034 +  },
19035 +/* pxcnv.t ${d-direct-addr},#${s1-imm8} */
19036 +  {
19037 +    UBICOM32_INSN_PXCNV_T_D_DIRECT_S1_IMMEDIATE, "pxcnv.t-d-direct-s1-immediate", "pxcnv.t", 32,
19038 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19039 +  },
19040 +/* pxcnv.t #${d-imm8},#${s1-imm8} */
19041 +  {
19042 +    UBICOM32_INSN_PXCNV_T_D_IMMEDIATE_2_S1_IMMEDIATE, "pxcnv.t-d-immediate-2-s1-immediate", "pxcnv.t", 32,
19043 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19044 +  },
19045 +/* pxcnv.t (${d-An},${d-r}),#${s1-imm8} */
19046 +  {
19047 +    UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_INDEX_2_S1_IMMEDIATE, "pxcnv.t-d-indirect-with-index-2-s1-immediate", "pxcnv.t", 32,
19048 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19049 +  },
19050 +/* pxcnv.t ${d-imm7-2}(${d-An}),#${s1-imm8} */
19051 +  {
19052 +    UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_OFFSET_2_S1_IMMEDIATE, "pxcnv.t-d-indirect-with-offset-2-s1-immediate", "pxcnv.t", 32,
19053 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19054 +  },
19055 +/* pxcnv.t (${d-An}),#${s1-imm8} */
19056 +  {
19057 +    UBICOM32_INSN_PXCNV_T_D_INDIRECT_2_S1_IMMEDIATE, "pxcnv.t-d-indirect-2-s1-immediate", "pxcnv.t", 32,
19058 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19059 +  },
19060 +/* pxcnv.t (${d-An})${d-i4-2}++,#${s1-imm8} */
19061 +  {
19062 +    UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_POST_INCREMENT_2_S1_IMMEDIATE, "pxcnv.t-d-indirect-with-post-increment-2-s1-immediate", "pxcnv.t", 32,
19063 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19064 +  },
19065 +/* pxcnv.t ${d-i4-2}(${d-An})++,#${s1-imm8} */
19066 +  {
19067 +    UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_IMMEDIATE, "pxcnv.t-d-indirect-with-pre-increment-2-s1-immediate", "pxcnv.t", 32,
19068 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19069 +  },
19070 +/* pxcnv.t ${d-direct-addr},(${s1-An},${s1-r}) */
19071 +  {
19072 +    UBICOM32_INSN_PXCNV_T_D_DIRECT_S1_INDIRECT_WITH_INDEX_4, "pxcnv.t-d-direct-s1-indirect-with-index-4", "pxcnv.t", 32,
19073 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19074 +  },
19075 +/* pxcnv.t #${d-imm8},(${s1-An},${s1-r}) */
19076 +  {
19077 +    UBICOM32_INSN_PXCNV_T_D_IMMEDIATE_2_S1_INDIRECT_WITH_INDEX_4, "pxcnv.t-d-immediate-2-s1-indirect-with-index-4", "pxcnv.t", 32,
19078 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19079 +  },
19080 +/* pxcnv.t (${d-An},${d-r}),(${s1-An},${s1-r}) */
19081 +  {
19082 +    UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_INDEX_4, "pxcnv.t-d-indirect-with-index-2-s1-indirect-with-index-4", "pxcnv.t", 32,
19083 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19084 +  },
19085 +/* pxcnv.t ${d-imm7-2}(${d-An}),(${s1-An},${s1-r}) */
19086 +  {
19087 +    UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_INDEX_4, "pxcnv.t-d-indirect-with-offset-2-s1-indirect-with-index-4", "pxcnv.t", 32,
19088 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19089 +  },
19090 +/* pxcnv.t (${d-An}),(${s1-An},${s1-r}) */
19091 +  {
19092 +    UBICOM32_INSN_PXCNV_T_D_INDIRECT_2_S1_INDIRECT_WITH_INDEX_4, "pxcnv.t-d-indirect-2-s1-indirect-with-index-4", "pxcnv.t", 32,
19093 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19094 +  },
19095 +/* pxcnv.t (${d-An})${d-i4-2}++,(${s1-An},${s1-r}) */
19096 +  {
19097 +    UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_INDEX_4, "pxcnv.t-d-indirect-with-post-increment-2-s1-indirect-with-index-4", "pxcnv.t", 32,
19098 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19099 +  },
19100 +/* pxcnv.t ${d-i4-2}(${d-An})++,(${s1-An},${s1-r}) */
19101 +  {
19102 +    UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_INDEX_4, "pxcnv.t-d-indirect-with-pre-increment-2-s1-indirect-with-index-4", "pxcnv.t", 32,
19103 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19104 +  },
19105 +/* pxcnv.t ${d-direct-addr},${s1-imm7-4}(${s1-An}) */
19106 +  {
19107 +    UBICOM32_INSN_PXCNV_T_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4, "pxcnv.t-d-direct-s1-indirect-with-offset-4", "pxcnv.t", 32,
19108 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19109 +  },
19110 +/* pxcnv.t #${d-imm8},${s1-imm7-4}(${s1-An}) */
19111 +  {
19112 +    UBICOM32_INSN_PXCNV_T_D_IMMEDIATE_2_S1_INDIRECT_WITH_OFFSET_4, "pxcnv.t-d-immediate-2-s1-indirect-with-offset-4", "pxcnv.t", 32,
19113 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19114 +  },
19115 +/* pxcnv.t (${d-An},${d-r}),${s1-imm7-4}(${s1-An}) */
19116 +  {
19117 +    UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_OFFSET_4, "pxcnv.t-d-indirect-with-index-2-s1-indirect-with-offset-4", "pxcnv.t", 32,
19118 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19119 +  },
19120 +/* pxcnv.t ${d-imm7-2}(${d-An}),${s1-imm7-4}(${s1-An}) */
19121 +  {
19122 +    UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_OFFSET_4, "pxcnv.t-d-indirect-with-offset-2-s1-indirect-with-offset-4", "pxcnv.t", 32,
19123 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19124 +  },
19125 +/* pxcnv.t (${d-An}),${s1-imm7-4}(${s1-An}) */
19126 +  {
19127 +    UBICOM32_INSN_PXCNV_T_D_INDIRECT_2_S1_INDIRECT_WITH_OFFSET_4, "pxcnv.t-d-indirect-2-s1-indirect-with-offset-4", "pxcnv.t", 32,
19128 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19129 +  },
19130 +/* pxcnv.t (${d-An})${d-i4-2}++,${s1-imm7-4}(${s1-An}) */
19131 +  {
19132 +    UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_4, "pxcnv.t-d-indirect-with-post-increment-2-s1-indirect-with-offset-4", "pxcnv.t", 32,
19133 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19134 +  },
19135 +/* pxcnv.t ${d-i4-2}(${d-An})++,${s1-imm7-4}(${s1-An}) */
19136 +  {
19137 +    UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_4, "pxcnv.t-d-indirect-with-pre-increment-2-s1-indirect-with-offset-4", "pxcnv.t", 32,
19138 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19139 +  },
19140 +/* pxcnv.t ${d-direct-addr},(${s1-An}) */
19141 +  {
19142 +    UBICOM32_INSN_PXCNV_T_D_DIRECT_S1_INDIRECT_4, "pxcnv.t-d-direct-s1-indirect-4", "pxcnv.t", 32,
19143 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19144 +  },
19145 +/* pxcnv.t #${d-imm8},(${s1-An}) */
19146 +  {
19147 +    UBICOM32_INSN_PXCNV_T_D_IMMEDIATE_2_S1_INDIRECT_4, "pxcnv.t-d-immediate-2-s1-indirect-4", "pxcnv.t", 32,
19148 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19149 +  },
19150 +/* pxcnv.t (${d-An},${d-r}),(${s1-An}) */
19151 +  {
19152 +    UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_4, "pxcnv.t-d-indirect-with-index-2-s1-indirect-4", "pxcnv.t", 32,
19153 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19154 +  },
19155 +/* pxcnv.t ${d-imm7-2}(${d-An}),(${s1-An}) */
19156 +  {
19157 +    UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_4, "pxcnv.t-d-indirect-with-offset-2-s1-indirect-4", "pxcnv.t", 32,
19158 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19159 +  },
19160 +/* pxcnv.t (${d-An}),(${s1-An}) */
19161 +  {
19162 +    UBICOM32_INSN_PXCNV_T_D_INDIRECT_2_S1_INDIRECT_4, "pxcnv.t-d-indirect-2-s1-indirect-4", "pxcnv.t", 32,
19163 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19164 +  },
19165 +/* pxcnv.t (${d-An})${d-i4-2}++,(${s1-An}) */
19166 +  {
19167 +    UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_4, "pxcnv.t-d-indirect-with-post-increment-2-s1-indirect-4", "pxcnv.t", 32,
19168 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19169 +  },
19170 +/* pxcnv.t ${d-i4-2}(${d-An})++,(${s1-An}) */
19171 +  {
19172 +    UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_4, "pxcnv.t-d-indirect-with-pre-increment-2-s1-indirect-4", "pxcnv.t", 32,
19173 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19174 +  },
19175 +/* pxcnv.t ${d-direct-addr},(${s1-An})${s1-i4-4}++ */
19176 +  {
19177 +    UBICOM32_INSN_PXCNV_T_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4, "pxcnv.t-d-direct-s1-indirect-with-post-increment-4", "pxcnv.t", 32,
19178 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19179 +  },
19180 +/* pxcnv.t #${d-imm8},(${s1-An})${s1-i4-4}++ */
19181 +  {
19182 +    UBICOM32_INSN_PXCNV_T_D_IMMEDIATE_2_S1_INDIRECT_WITH_POST_INCREMENT_4, "pxcnv.t-d-immediate-2-s1-indirect-with-post-increment-4", "pxcnv.t", 32,
19183 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19184 +  },
19185 +/* pxcnv.t (${d-An},${d-r}),(${s1-An})${s1-i4-4}++ */
19186 +  {
19187 +    UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_POST_INCREMENT_4, "pxcnv.t-d-indirect-with-index-2-s1-indirect-with-post-increment-4", "pxcnv.t", 32,
19188 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19189 +  },
19190 +/* pxcnv.t ${d-imm7-2}(${d-An}),(${s1-An})${s1-i4-4}++ */
19191 +  {
19192 +    UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_POST_INCREMENT_4, "pxcnv.t-d-indirect-with-offset-2-s1-indirect-with-post-increment-4", "pxcnv.t", 32,
19193 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19194 +  },
19195 +/* pxcnv.t (${d-An}),(${s1-An})${s1-i4-4}++ */
19196 +  {
19197 +    UBICOM32_INSN_PXCNV_T_D_INDIRECT_2_S1_INDIRECT_WITH_POST_INCREMENT_4, "pxcnv.t-d-indirect-2-s1-indirect-with-post-increment-4", "pxcnv.t", 32,
19198 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19199 +  },
19200 +/* pxcnv.t (${d-An})${d-i4-2}++,(${s1-An})${s1-i4-4}++ */
19201 +  {
19202 +    UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_4, "pxcnv.t-d-indirect-with-post-increment-2-s1-indirect-with-post-increment-4", "pxcnv.t", 32,
19203 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19204 +  },
19205 +/* pxcnv.t ${d-i4-2}(${d-An})++,(${s1-An})${s1-i4-4}++ */
19206 +  {
19207 +    UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_4, "pxcnv.t-d-indirect-with-pre-increment-2-s1-indirect-with-post-increment-4", "pxcnv.t", 32,
19208 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19209 +  },
19210 +/* pxcnv.t ${d-direct-addr},${s1-i4-4}(${s1-An})++ */
19211 +  {
19212 +    UBICOM32_INSN_PXCNV_T_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4, "pxcnv.t-d-direct-s1-indirect-with-pre-increment-4", "pxcnv.t", 32,
19213 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19214 +  },
19215 +/* pxcnv.t #${d-imm8},${s1-i4-4}(${s1-An})++ */
19216 +  {
19217 +    UBICOM32_INSN_PXCNV_T_D_IMMEDIATE_2_S1_INDIRECT_WITH_PRE_INCREMENT_4, "pxcnv.t-d-immediate-2-s1-indirect-with-pre-increment-4", "pxcnv.t", 32,
19218 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19219 +  },
19220 +/* pxcnv.t (${d-An},${d-r}),${s1-i4-4}(${s1-An})++ */
19221 +  {
19222 +    UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_PRE_INCREMENT_4, "pxcnv.t-d-indirect-with-index-2-s1-indirect-with-pre-increment-4", "pxcnv.t", 32,
19223 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19224 +  },
19225 +/* pxcnv.t ${d-imm7-2}(${d-An}),${s1-i4-4}(${s1-An})++ */
19226 +  {
19227 +    UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_PRE_INCREMENT_4, "pxcnv.t-d-indirect-with-offset-2-s1-indirect-with-pre-increment-4", "pxcnv.t", 32,
19228 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19229 +  },
19230 +/* pxcnv.t (${d-An}),${s1-i4-4}(${s1-An})++ */
19231 +  {
19232 +    UBICOM32_INSN_PXCNV_T_D_INDIRECT_2_S1_INDIRECT_WITH_PRE_INCREMENT_4, "pxcnv.t-d-indirect-2-s1-indirect-with-pre-increment-4", "pxcnv.t", 32,
19233 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19234 +  },
19235 +/* pxcnv.t (${d-An})${d-i4-2}++,${s1-i4-4}(${s1-An})++ */
19236 +  {
19237 +    UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_4, "pxcnv.t-d-indirect-with-post-increment-2-s1-indirect-with-pre-increment-4", "pxcnv.t", 32,
19238 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19239 +  },
19240 +/* pxcnv.t ${d-i4-2}(${d-An})++,${s1-i4-4}(${s1-An})++ */
19241 +  {
19242 +    UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_4, "pxcnv.t-d-indirect-with-pre-increment-2-s1-indirect-with-pre-increment-4", "pxcnv.t", 32,
19243 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19244 +  },
19245 +/* pxcnv ${d-direct-addr},${s1-direct-addr} */
19246 +  {
19247 +    UBICOM32_INSN_PXCNV_D_DIRECT_S1_DIRECT, "pxcnv-d-direct-s1-direct", "pxcnv", 32,
19248 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19249 +  },
19250 +/* pxcnv #${d-imm8},${s1-direct-addr} */
19251 +  {
19252 +    UBICOM32_INSN_PXCNV_D_IMMEDIATE_2_S1_DIRECT, "pxcnv-d-immediate-2-s1-direct", "pxcnv", 32,
19253 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19254 +  },
19255 +/* pxcnv (${d-An},${d-r}),${s1-direct-addr} */
19256 +  {
19257 +    UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_INDEX_2_S1_DIRECT, "pxcnv-d-indirect-with-index-2-s1-direct", "pxcnv", 32,
19258 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19259 +  },
19260 +/* pxcnv ${d-imm7-2}(${d-An}),${s1-direct-addr} */
19261 +  {
19262 +    UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_OFFSET_2_S1_DIRECT, "pxcnv-d-indirect-with-offset-2-s1-direct", "pxcnv", 32,
19263 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19264 +  },
19265 +/* pxcnv (${d-An}),${s1-direct-addr} */
19266 +  {
19267 +    UBICOM32_INSN_PXCNV_D_INDIRECT_2_S1_DIRECT, "pxcnv-d-indirect-2-s1-direct", "pxcnv", 32,
19268 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19269 +  },
19270 +/* pxcnv (${d-An})${d-i4-2}++,${s1-direct-addr} */
19271 +  {
19272 +    UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_POST_INCREMENT_2_S1_DIRECT, "pxcnv-d-indirect-with-post-increment-2-s1-direct", "pxcnv", 32,
19273 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19274 +  },
19275 +/* pxcnv ${d-i4-2}(${d-An})++,${s1-direct-addr} */
19276 +  {
19277 +    UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_DIRECT, "pxcnv-d-indirect-with-pre-increment-2-s1-direct", "pxcnv", 32,
19278 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19279 +  },
19280 +/* pxcnv ${d-direct-addr},#${s1-imm8} */
19281 +  {
19282 +    UBICOM32_INSN_PXCNV_D_DIRECT_S1_IMMEDIATE, "pxcnv-d-direct-s1-immediate", "pxcnv", 32,
19283 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19284 +  },
19285 +/* pxcnv #${d-imm8},#${s1-imm8} */
19286 +  {
19287 +    UBICOM32_INSN_PXCNV_D_IMMEDIATE_2_S1_IMMEDIATE, "pxcnv-d-immediate-2-s1-immediate", "pxcnv", 32,
19288 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19289 +  },
19290 +/* pxcnv (${d-An},${d-r}),#${s1-imm8} */
19291 +  {
19292 +    UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_INDEX_2_S1_IMMEDIATE, "pxcnv-d-indirect-with-index-2-s1-immediate", "pxcnv", 32,
19293 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19294 +  },
19295 +/* pxcnv ${d-imm7-2}(${d-An}),#${s1-imm8} */
19296 +  {
19297 +    UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_OFFSET_2_S1_IMMEDIATE, "pxcnv-d-indirect-with-offset-2-s1-immediate", "pxcnv", 32,
19298 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19299 +  },
19300 +/* pxcnv (${d-An}),#${s1-imm8} */
19301 +  {
19302 +    UBICOM32_INSN_PXCNV_D_INDIRECT_2_S1_IMMEDIATE, "pxcnv-d-indirect-2-s1-immediate", "pxcnv", 32,
19303 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19304 +  },
19305 +/* pxcnv (${d-An})${d-i4-2}++,#${s1-imm8} */
19306 +  {
19307 +    UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_POST_INCREMENT_2_S1_IMMEDIATE, "pxcnv-d-indirect-with-post-increment-2-s1-immediate", "pxcnv", 32,
19308 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19309 +  },
19310 +/* pxcnv ${d-i4-2}(${d-An})++,#${s1-imm8} */
19311 +  {
19312 +    UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_IMMEDIATE, "pxcnv-d-indirect-with-pre-increment-2-s1-immediate", "pxcnv", 32,
19313 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19314 +  },
19315 +/* pxcnv ${d-direct-addr},(${s1-An},${s1-r}) */
19316 +  {
19317 +    UBICOM32_INSN_PXCNV_D_DIRECT_S1_INDIRECT_WITH_INDEX_4, "pxcnv-d-direct-s1-indirect-with-index-4", "pxcnv", 32,
19318 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19319 +  },
19320 +/* pxcnv #${d-imm8},(${s1-An},${s1-r}) */
19321 +  {
19322 +    UBICOM32_INSN_PXCNV_D_IMMEDIATE_2_S1_INDIRECT_WITH_INDEX_4, "pxcnv-d-immediate-2-s1-indirect-with-index-4", "pxcnv", 32,
19323 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19324 +  },
19325 +/* pxcnv (${d-An},${d-r}),(${s1-An},${s1-r}) */
19326 +  {
19327 +    UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_INDEX_4, "pxcnv-d-indirect-with-index-2-s1-indirect-with-index-4", "pxcnv", 32,
19328 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19329 +  },
19330 +/* pxcnv ${d-imm7-2}(${d-An}),(${s1-An},${s1-r}) */
19331 +  {
19332 +    UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_INDEX_4, "pxcnv-d-indirect-with-offset-2-s1-indirect-with-index-4", "pxcnv", 32,
19333 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19334 +  },
19335 +/* pxcnv (${d-An}),(${s1-An},${s1-r}) */
19336 +  {
19337 +    UBICOM32_INSN_PXCNV_D_INDIRECT_2_S1_INDIRECT_WITH_INDEX_4, "pxcnv-d-indirect-2-s1-indirect-with-index-4", "pxcnv", 32,
19338 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19339 +  },
19340 +/* pxcnv (${d-An})${d-i4-2}++,(${s1-An},${s1-r}) */
19341 +  {
19342 +    UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_INDEX_4, "pxcnv-d-indirect-with-post-increment-2-s1-indirect-with-index-4", "pxcnv", 32,
19343 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19344 +  },
19345 +/* pxcnv ${d-i4-2}(${d-An})++,(${s1-An},${s1-r}) */
19346 +  {
19347 +    UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_INDEX_4, "pxcnv-d-indirect-with-pre-increment-2-s1-indirect-with-index-4", "pxcnv", 32,
19348 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19349 +  },
19350 +/* pxcnv ${d-direct-addr},${s1-imm7-4}(${s1-An}) */
19351 +  {
19352 +    UBICOM32_INSN_PXCNV_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4, "pxcnv-d-direct-s1-indirect-with-offset-4", "pxcnv", 32,
19353 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19354 +  },
19355 +/* pxcnv #${d-imm8},${s1-imm7-4}(${s1-An}) */
19356 +  {
19357 +    UBICOM32_INSN_PXCNV_D_IMMEDIATE_2_S1_INDIRECT_WITH_OFFSET_4, "pxcnv-d-immediate-2-s1-indirect-with-offset-4", "pxcnv", 32,
19358 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19359 +  },
19360 +/* pxcnv (${d-An},${d-r}),${s1-imm7-4}(${s1-An}) */
19361 +  {
19362 +    UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_OFFSET_4, "pxcnv-d-indirect-with-index-2-s1-indirect-with-offset-4", "pxcnv", 32,
19363 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19364 +  },
19365 +/* pxcnv ${d-imm7-2}(${d-An}),${s1-imm7-4}(${s1-An}) */
19366 +  {
19367 +    UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_OFFSET_4, "pxcnv-d-indirect-with-offset-2-s1-indirect-with-offset-4", "pxcnv", 32,
19368 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19369 +  },
19370 +/* pxcnv (${d-An}),${s1-imm7-4}(${s1-An}) */
19371 +  {
19372 +    UBICOM32_INSN_PXCNV_D_INDIRECT_2_S1_INDIRECT_WITH_OFFSET_4, "pxcnv-d-indirect-2-s1-indirect-with-offset-4", "pxcnv", 32,
19373 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19374 +  },
19375 +/* pxcnv (${d-An})${d-i4-2}++,${s1-imm7-4}(${s1-An}) */
19376 +  {
19377 +    UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_4, "pxcnv-d-indirect-with-post-increment-2-s1-indirect-with-offset-4", "pxcnv", 32,
19378 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19379 +  },
19380 +/* pxcnv ${d-i4-2}(${d-An})++,${s1-imm7-4}(${s1-An}) */
19381 +  {
19382 +    UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_4, "pxcnv-d-indirect-with-pre-increment-2-s1-indirect-with-offset-4", "pxcnv", 32,
19383 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19384 +  },
19385 +/* pxcnv ${d-direct-addr},(${s1-An}) */
19386 +  {
19387 +    UBICOM32_INSN_PXCNV_D_DIRECT_S1_INDIRECT_4, "pxcnv-d-direct-s1-indirect-4", "pxcnv", 32,
19388 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19389 +  },
19390 +/* pxcnv #${d-imm8},(${s1-An}) */
19391 +  {
19392 +    UBICOM32_INSN_PXCNV_D_IMMEDIATE_2_S1_INDIRECT_4, "pxcnv-d-immediate-2-s1-indirect-4", "pxcnv", 32,
19393 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19394 +  },
19395 +/* pxcnv (${d-An},${d-r}),(${s1-An}) */
19396 +  {
19397 +    UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_4, "pxcnv-d-indirect-with-index-2-s1-indirect-4", "pxcnv", 32,
19398 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19399 +  },
19400 +/* pxcnv ${d-imm7-2}(${d-An}),(${s1-An}) */
19401 +  {
19402 +    UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_4, "pxcnv-d-indirect-with-offset-2-s1-indirect-4", "pxcnv", 32,
19403 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19404 +  },
19405 +/* pxcnv (${d-An}),(${s1-An}) */
19406 +  {
19407 +    UBICOM32_INSN_PXCNV_D_INDIRECT_2_S1_INDIRECT_4, "pxcnv-d-indirect-2-s1-indirect-4", "pxcnv", 32,
19408 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19409 +  },
19410 +/* pxcnv (${d-An})${d-i4-2}++,(${s1-An}) */
19411 +  {
19412 +    UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_4, "pxcnv-d-indirect-with-post-increment-2-s1-indirect-4", "pxcnv", 32,
19413 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19414 +  },
19415 +/* pxcnv ${d-i4-2}(${d-An})++,(${s1-An}) */
19416 +  {
19417 +    UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_4, "pxcnv-d-indirect-with-pre-increment-2-s1-indirect-4", "pxcnv", 32,
19418 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19419 +  },
19420 +/* pxcnv ${d-direct-addr},(${s1-An})${s1-i4-4}++ */
19421 +  {
19422 +    UBICOM32_INSN_PXCNV_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4, "pxcnv-d-direct-s1-indirect-with-post-increment-4", "pxcnv", 32,
19423 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19424 +  },
19425 +/* pxcnv #${d-imm8},(${s1-An})${s1-i4-4}++ */
19426 +  {
19427 +    UBICOM32_INSN_PXCNV_D_IMMEDIATE_2_S1_INDIRECT_WITH_POST_INCREMENT_4, "pxcnv-d-immediate-2-s1-indirect-with-post-increment-4", "pxcnv", 32,
19428 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19429 +  },
19430 +/* pxcnv (${d-An},${d-r}),(${s1-An})${s1-i4-4}++ */
19431 +  {
19432 +    UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_POST_INCREMENT_4, "pxcnv-d-indirect-with-index-2-s1-indirect-with-post-increment-4", "pxcnv", 32,
19433 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19434 +  },
19435 +/* pxcnv ${d-imm7-2}(${d-An}),(${s1-An})${s1-i4-4}++ */
19436 +  {
19437 +    UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_POST_INCREMENT_4, "pxcnv-d-indirect-with-offset-2-s1-indirect-with-post-increment-4", "pxcnv", 32,
19438 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19439 +  },
19440 +/* pxcnv (${d-An}),(${s1-An})${s1-i4-4}++ */
19441 +  {
19442 +    UBICOM32_INSN_PXCNV_D_INDIRECT_2_S1_INDIRECT_WITH_POST_INCREMENT_4, "pxcnv-d-indirect-2-s1-indirect-with-post-increment-4", "pxcnv", 32,
19443 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19444 +  },
19445 +/* pxcnv (${d-An})${d-i4-2}++,(${s1-An})${s1-i4-4}++ */
19446 +  {
19447 +    UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_4, "pxcnv-d-indirect-with-post-increment-2-s1-indirect-with-post-increment-4", "pxcnv", 32,
19448 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19449 +  },
19450 +/* pxcnv ${d-i4-2}(${d-An})++,(${s1-An})${s1-i4-4}++ */
19451 +  {
19452 +    UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_4, "pxcnv-d-indirect-with-pre-increment-2-s1-indirect-with-post-increment-4", "pxcnv", 32,
19453 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19454 +  },
19455 +/* pxcnv ${d-direct-addr},${s1-i4-4}(${s1-An})++ */
19456 +  {
19457 +    UBICOM32_INSN_PXCNV_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4, "pxcnv-d-direct-s1-indirect-with-pre-increment-4", "pxcnv", 32,
19458 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19459 +  },
19460 +/* pxcnv #${d-imm8},${s1-i4-4}(${s1-An})++ */
19461 +  {
19462 +    UBICOM32_INSN_PXCNV_D_IMMEDIATE_2_S1_INDIRECT_WITH_PRE_INCREMENT_4, "pxcnv-d-immediate-2-s1-indirect-with-pre-increment-4", "pxcnv", 32,
19463 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19464 +  },
19465 +/* pxcnv (${d-An},${d-r}),${s1-i4-4}(${s1-An})++ */
19466 +  {
19467 +    UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_PRE_INCREMENT_4, "pxcnv-d-indirect-with-index-2-s1-indirect-with-pre-increment-4", "pxcnv", 32,
19468 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19469 +  },
19470 +/* pxcnv ${d-imm7-2}(${d-An}),${s1-i4-4}(${s1-An})++ */
19471 +  {
19472 +    UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_PRE_INCREMENT_4, "pxcnv-d-indirect-with-offset-2-s1-indirect-with-pre-increment-4", "pxcnv", 32,
19473 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19474 +  },
19475 +/* pxcnv (${d-An}),${s1-i4-4}(${s1-An})++ */
19476 +  {
19477 +    UBICOM32_INSN_PXCNV_D_INDIRECT_2_S1_INDIRECT_WITH_PRE_INCREMENT_4, "pxcnv-d-indirect-2-s1-indirect-with-pre-increment-4", "pxcnv", 32,
19478 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19479 +  },
19480 +/* pxcnv (${d-An})${d-i4-2}++,${s1-i4-4}(${s1-An})++ */
19481 +  {
19482 +    UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_4, "pxcnv-d-indirect-with-post-increment-2-s1-indirect-with-pre-increment-4", "pxcnv", 32,
19483 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19484 +  },
19485 +/* pxcnv ${d-i4-2}(${d-An})++,${s1-i4-4}(${s1-An})++ */
19486 +  {
19487 +    UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_4, "pxcnv-d-indirect-with-pre-increment-2-s1-indirect-with-pre-increment-4", "pxcnv", 32,
19488 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19489 +  },
19490 +/* subc ${d-direct-addr},${s1-direct-addr},${s2} */
19491 +  {
19492 +    UBICOM32_INSN_SUBC_D_DIRECT_S1_DIRECT, "subc-d-direct-s1-direct", "subc", 32,
19493 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19494 +  },
19495 +/* subc #${d-imm8},${s1-direct-addr},${s2} */
19496 +  {
19497 +    UBICOM32_INSN_SUBC_D_IMMEDIATE_4_S1_DIRECT, "subc-d-immediate-4-s1-direct", "subc", 32,
19498 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19499 +  },
19500 +/* subc (${d-An},${d-r}),${s1-direct-addr},${s2} */
19501 +  {
19502 +    UBICOM32_INSN_SUBC_D_INDIRECT_WITH_INDEX_4_S1_DIRECT, "subc-d-indirect-with-index-4-s1-direct", "subc", 32,
19503 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19504 +  },
19505 +/* subc ${d-imm7-4}(${d-An}),${s1-direct-addr},${s2} */
19506 +  {
19507 +    UBICOM32_INSN_SUBC_D_INDIRECT_WITH_OFFSET_4_S1_DIRECT, "subc-d-indirect-with-offset-4-s1-direct", "subc", 32,
19508 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19509 +  },
19510 +/* subc (${d-An}),${s1-direct-addr},${s2} */
19511 +  {
19512 +    UBICOM32_INSN_SUBC_D_INDIRECT_4_S1_DIRECT, "subc-d-indirect-4-s1-direct", "subc", 32,
19513 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19514 +  },
19515 +/* subc (${d-An})${d-i4-4}++,${s1-direct-addr},${s2} */
19516 +  {
19517 +    UBICOM32_INSN_SUBC_D_INDIRECT_WITH_POST_INCREMENT_4_S1_DIRECT, "subc-d-indirect-with-post-increment-4-s1-direct", "subc", 32,
19518 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19519 +  },
19520 +/* subc ${d-i4-4}(${d-An})++,${s1-direct-addr},${s2} */
19521 +  {
19522 +    UBICOM32_INSN_SUBC_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_DIRECT, "subc-d-indirect-with-pre-increment-4-s1-direct", "subc", 32,
19523 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19524 +  },
19525 +/* subc ${d-direct-addr},#${s1-imm8},${s2} */
19526 +  {
19527 +    UBICOM32_INSN_SUBC_D_DIRECT_S1_IMMEDIATE, "subc-d-direct-s1-immediate", "subc", 32,
19528 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19529 +  },
19530 +/* subc #${d-imm8},#${s1-imm8},${s2} */
19531 +  {
19532 +    UBICOM32_INSN_SUBC_D_IMMEDIATE_4_S1_IMMEDIATE, "subc-d-immediate-4-s1-immediate", "subc", 32,
19533 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19534 +  },
19535 +/* subc (${d-An},${d-r}),#${s1-imm8},${s2} */
19536 +  {
19537 +    UBICOM32_INSN_SUBC_D_INDIRECT_WITH_INDEX_4_S1_IMMEDIATE, "subc-d-indirect-with-index-4-s1-immediate", "subc", 32,
19538 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19539 +  },
19540 +/* subc ${d-imm7-4}(${d-An}),#${s1-imm8},${s2} */
19541 +  {
19542 +    UBICOM32_INSN_SUBC_D_INDIRECT_WITH_OFFSET_4_S1_IMMEDIATE, "subc-d-indirect-with-offset-4-s1-immediate", "subc", 32,
19543 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19544 +  },
19545 +/* subc (${d-An}),#${s1-imm8},${s2} */
19546 +  {
19547 +    UBICOM32_INSN_SUBC_D_INDIRECT_4_S1_IMMEDIATE, "subc-d-indirect-4-s1-immediate", "subc", 32,
19548 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19549 +  },
19550 +/* subc (${d-An})${d-i4-4}++,#${s1-imm8},${s2} */
19551 +  {
19552 +    UBICOM32_INSN_SUBC_D_INDIRECT_WITH_POST_INCREMENT_4_S1_IMMEDIATE, "subc-d-indirect-with-post-increment-4-s1-immediate", "subc", 32,
19553 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19554 +  },
19555 +/* subc ${d-i4-4}(${d-An})++,#${s1-imm8},${s2} */
19556 +  {
19557 +    UBICOM32_INSN_SUBC_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_IMMEDIATE, "subc-d-indirect-with-pre-increment-4-s1-immediate", "subc", 32,
19558 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19559 +  },
19560 +/* subc ${d-direct-addr},(${s1-An},${s1-r}),${s2} */
19561 +  {
19562 +    UBICOM32_INSN_SUBC_D_DIRECT_S1_INDIRECT_WITH_INDEX_4, "subc-d-direct-s1-indirect-with-index-4", "subc", 32,
19563 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19564 +  },
19565 +/* subc #${d-imm8},(${s1-An},${s1-r}),${s2} */
19566 +  {
19567 +    UBICOM32_INSN_SUBC_D_IMMEDIATE_4_S1_INDIRECT_WITH_INDEX_4, "subc-d-immediate-4-s1-indirect-with-index-4", "subc", 32,
19568 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19569 +  },
19570 +/* subc (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */
19571 +  {
19572 +    UBICOM32_INSN_SUBC_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_INDEX_4, "subc-d-indirect-with-index-4-s1-indirect-with-index-4", "subc", 32,
19573 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19574 +  },
19575 +/* subc ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}),${s2} */
19576 +  {
19577 +    UBICOM32_INSN_SUBC_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_INDEX_4, "subc-d-indirect-with-offset-4-s1-indirect-with-index-4", "subc", 32,
19578 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19579 +  },
19580 +/* subc (${d-An}),(${s1-An},${s1-r}),${s2} */
19581 +  {
19582 +    UBICOM32_INSN_SUBC_D_INDIRECT_4_S1_INDIRECT_WITH_INDEX_4, "subc-d-indirect-4-s1-indirect-with-index-4", "subc", 32,
19583 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19584 +  },
19585 +/* subc (${d-An})${d-i4-4}++,(${s1-An},${s1-r}),${s2} */
19586 +  {
19587 +    UBICOM32_INSN_SUBC_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, "subc-d-indirect-with-post-increment-4-s1-indirect-with-index-4", "subc", 32,
19588 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19589 +  },
19590 +/* subc ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}),${s2} */
19591 +  {
19592 +    UBICOM32_INSN_SUBC_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, "subc-d-indirect-with-pre-increment-4-s1-indirect-with-index-4", "subc", 32,
19593 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19594 +  },
19595 +/* subc ${d-direct-addr},${s1-imm7-4}(${s1-An}),${s2} */
19596 +  {
19597 +    UBICOM32_INSN_SUBC_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4, "subc-d-direct-s1-indirect-with-offset-4", "subc", 32,
19598 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19599 +  },
19600 +/* subc #${d-imm8},${s1-imm7-4}(${s1-An}),${s2} */
19601 +  {
19602 +    UBICOM32_INSN_SUBC_D_IMMEDIATE_4_S1_INDIRECT_WITH_OFFSET_4, "subc-d-immediate-4-s1-indirect-with-offset-4", "subc", 32,
19603 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19604 +  },
19605 +/* subc (${d-An},${d-r}),${s1-imm7-4}(${s1-An}),${s2} */
19606 +  {
19607 +    UBICOM32_INSN_SUBC_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_OFFSET_4, "subc-d-indirect-with-index-4-s1-indirect-with-offset-4", "subc", 32,
19608 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19609 +  },
19610 +/* subc ${d-imm7-4}(${d-An}),${s1-imm7-4}(${s1-An}),${s2} */
19611 +  {
19612 +    UBICOM32_INSN_SUBC_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_OFFSET_4, "subc-d-indirect-with-offset-4-s1-indirect-with-offset-4", "subc", 32,
19613 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19614 +  },
19615 +/* subc (${d-An}),${s1-imm7-4}(${s1-An}),${s2} */
19616 +  {
19617 +    UBICOM32_INSN_SUBC_D_INDIRECT_4_S1_INDIRECT_WITH_OFFSET_4, "subc-d-indirect-4-s1-indirect-with-offset-4", "subc", 32,
19618 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19619 +  },
19620 +/* subc (${d-An})${d-i4-4}++,${s1-imm7-4}(${s1-An}),${s2} */
19621 +  {
19622 +    UBICOM32_INSN_SUBC_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, "subc-d-indirect-with-post-increment-4-s1-indirect-with-offset-4", "subc", 32,
19623 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19624 +  },
19625 +/* subc ${d-i4-4}(${d-An})++,${s1-imm7-4}(${s1-An}),${s2} */
19626 +  {
19627 +    UBICOM32_INSN_SUBC_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, "subc-d-indirect-with-pre-increment-4-s1-indirect-with-offset-4", "subc", 32,
19628 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19629 +  },
19630 +/* subc ${d-direct-addr},(${s1-An}),${s2} */
19631 +  {
19632 +    UBICOM32_INSN_SUBC_D_DIRECT_S1_INDIRECT_4, "subc-d-direct-s1-indirect-4", "subc", 32,
19633 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19634 +  },
19635 +/* subc #${d-imm8},(${s1-An}),${s2} */
19636 +  {
19637 +    UBICOM32_INSN_SUBC_D_IMMEDIATE_4_S1_INDIRECT_4, "subc-d-immediate-4-s1-indirect-4", "subc", 32,
19638 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19639 +  },
19640 +/* subc (${d-An},${d-r}),(${s1-An}),${s2} */
19641 +  {
19642 +    UBICOM32_INSN_SUBC_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_4, "subc-d-indirect-with-index-4-s1-indirect-4", "subc", 32,
19643 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19644 +  },
19645 +/* subc ${d-imm7-4}(${d-An}),(${s1-An}),${s2} */
19646 +  {
19647 +    UBICOM32_INSN_SUBC_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_4, "subc-d-indirect-with-offset-4-s1-indirect-4", "subc", 32,
19648 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19649 +  },
19650 +/* subc (${d-An}),(${s1-An}),${s2} */
19651 +  {
19652 +    UBICOM32_INSN_SUBC_D_INDIRECT_4_S1_INDIRECT_4, "subc-d-indirect-4-s1-indirect-4", "subc", 32,
19653 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19654 +  },
19655 +/* subc (${d-An})${d-i4-4}++,(${s1-An}),${s2} */
19656 +  {
19657 +    UBICOM32_INSN_SUBC_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_4, "subc-d-indirect-with-post-increment-4-s1-indirect-4", "subc", 32,
19658 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19659 +  },
19660 +/* subc ${d-i4-4}(${d-An})++,(${s1-An}),${s2} */
19661 +  {
19662 +    UBICOM32_INSN_SUBC_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_4, "subc-d-indirect-with-pre-increment-4-s1-indirect-4", "subc", 32,
19663 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19664 +  },
19665 +/* subc ${d-direct-addr},(${s1-An})${s1-i4-4}++,${s2} */
19666 +  {
19667 +    UBICOM32_INSN_SUBC_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4, "subc-d-direct-s1-indirect-with-post-increment-4", "subc", 32,
19668 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19669 +  },
19670 +/* subc #${d-imm8},(${s1-An})${s1-i4-4}++,${s2} */
19671 +  {
19672 +    UBICOM32_INSN_SUBC_D_IMMEDIATE_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "subc-d-immediate-4-s1-indirect-with-post-increment-4", "subc", 32,
19673 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19674 +  },
19675 +/* subc (${d-An},${d-r}),(${s1-An})${s1-i4-4}++,${s2} */
19676 +  {
19677 +    UBICOM32_INSN_SUBC_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "subc-d-indirect-with-index-4-s1-indirect-with-post-increment-4", "subc", 32,
19678 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19679 +  },
19680 +/* subc ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-4}++,${s2} */
19681 +  {
19682 +    UBICOM32_INSN_SUBC_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "subc-d-indirect-with-offset-4-s1-indirect-with-post-increment-4", "subc", 32,
19683 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19684 +  },
19685 +/* subc (${d-An}),(${s1-An})${s1-i4-4}++,${s2} */
19686 +  {
19687 +    UBICOM32_INSN_SUBC_D_INDIRECT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "subc-d-indirect-4-s1-indirect-with-post-increment-4", "subc", 32,
19688 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19689 +  },
19690 +/* subc (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-4}++,${s2} */
19691 +  {
19692 +    UBICOM32_INSN_SUBC_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "subc-d-indirect-with-post-increment-4-s1-indirect-with-post-increment-4", "subc", 32,
19693 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19694 +  },
19695 +/* subc ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-4}++,${s2} */
19696 +  {
19697 +    UBICOM32_INSN_SUBC_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "subc-d-indirect-with-pre-increment-4-s1-indirect-with-post-increment-4", "subc", 32,
19698 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19699 +  },
19700 +/* subc ${d-direct-addr},${s1-i4-4}(${s1-An})++,${s2} */
19701 +  {
19702 +    UBICOM32_INSN_SUBC_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4, "subc-d-direct-s1-indirect-with-pre-increment-4", "subc", 32,
19703 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19704 +  },
19705 +/* subc #${d-imm8},${s1-i4-4}(${s1-An})++,${s2} */
19706 +  {
19707 +    UBICOM32_INSN_SUBC_D_IMMEDIATE_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "subc-d-immediate-4-s1-indirect-with-pre-increment-4", "subc", 32,
19708 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19709 +  },
19710 +/* subc (${d-An},${d-r}),${s1-i4-4}(${s1-An})++,${s2} */
19711 +  {
19712 +    UBICOM32_INSN_SUBC_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "subc-d-indirect-with-index-4-s1-indirect-with-pre-increment-4", "subc", 32,
19713 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19714 +  },
19715 +/* subc ${d-imm7-4}(${d-An}),${s1-i4-4}(${s1-An})++,${s2} */
19716 +  {
19717 +    UBICOM32_INSN_SUBC_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "subc-d-indirect-with-offset-4-s1-indirect-with-pre-increment-4", "subc", 32,
19718 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19719 +  },
19720 +/* subc (${d-An}),${s1-i4-4}(${s1-An})++,${s2} */
19721 +  {
19722 +    UBICOM32_INSN_SUBC_D_INDIRECT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "subc-d-indirect-4-s1-indirect-with-pre-increment-4", "subc", 32,
19723 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19724 +  },
19725 +/* subc (${d-An})${d-i4-4}++,${s1-i4-4}(${s1-An})++,${s2} */
19726 +  {
19727 +    UBICOM32_INSN_SUBC_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "subc-d-indirect-with-post-increment-4-s1-indirect-with-pre-increment-4", "subc", 32,
19728 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19729 +  },
19730 +/* subc ${d-i4-4}(${d-An})++,${s1-i4-4}(${s1-An})++,${s2} */
19731 +  {
19732 +    UBICOM32_INSN_SUBC_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "subc-d-indirect-with-pre-increment-4-s1-indirect-with-pre-increment-4", "subc", 32,
19733 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19734 +  },
19735 +/* addc ${d-direct-addr},${s1-direct-addr},${s2} */
19736 +  {
19737 +    UBICOM32_INSN_ADDC_D_DIRECT_S1_DIRECT, "addc-d-direct-s1-direct", "addc", 32,
19738 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19739 +  },
19740 +/* addc #${d-imm8},${s1-direct-addr},${s2} */
19741 +  {
19742 +    UBICOM32_INSN_ADDC_D_IMMEDIATE_4_S1_DIRECT, "addc-d-immediate-4-s1-direct", "addc", 32,
19743 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19744 +  },
19745 +/* addc (${d-An},${d-r}),${s1-direct-addr},${s2} */
19746 +  {
19747 +    UBICOM32_INSN_ADDC_D_INDIRECT_WITH_INDEX_4_S1_DIRECT, "addc-d-indirect-with-index-4-s1-direct", "addc", 32,
19748 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19749 +  },
19750 +/* addc ${d-imm7-4}(${d-An}),${s1-direct-addr},${s2} */
19751 +  {
19752 +    UBICOM32_INSN_ADDC_D_INDIRECT_WITH_OFFSET_4_S1_DIRECT, "addc-d-indirect-with-offset-4-s1-direct", "addc", 32,
19753 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19754 +  },
19755 +/* addc (${d-An}),${s1-direct-addr},${s2} */
19756 +  {
19757 +    UBICOM32_INSN_ADDC_D_INDIRECT_4_S1_DIRECT, "addc-d-indirect-4-s1-direct", "addc", 32,
19758 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19759 +  },
19760 +/* addc (${d-An})${d-i4-4}++,${s1-direct-addr},${s2} */
19761 +  {
19762 +    UBICOM32_INSN_ADDC_D_INDIRECT_WITH_POST_INCREMENT_4_S1_DIRECT, "addc-d-indirect-with-post-increment-4-s1-direct", "addc", 32,
19763 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19764 +  },
19765 +/* addc ${d-i4-4}(${d-An})++,${s1-direct-addr},${s2} */
19766 +  {
19767 +    UBICOM32_INSN_ADDC_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_DIRECT, "addc-d-indirect-with-pre-increment-4-s1-direct", "addc", 32,
19768 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19769 +  },
19770 +/* addc ${d-direct-addr},#${s1-imm8},${s2} */
19771 +  {
19772 +    UBICOM32_INSN_ADDC_D_DIRECT_S1_IMMEDIATE, "addc-d-direct-s1-immediate", "addc", 32,
19773 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19774 +  },
19775 +/* addc #${d-imm8},#${s1-imm8},${s2} */
19776 +  {
19777 +    UBICOM32_INSN_ADDC_D_IMMEDIATE_4_S1_IMMEDIATE, "addc-d-immediate-4-s1-immediate", "addc", 32,
19778 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19779 +  },
19780 +/* addc (${d-An},${d-r}),#${s1-imm8},${s2} */
19781 +  {
19782 +    UBICOM32_INSN_ADDC_D_INDIRECT_WITH_INDEX_4_S1_IMMEDIATE, "addc-d-indirect-with-index-4-s1-immediate", "addc", 32,
19783 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19784 +  },
19785 +/* addc ${d-imm7-4}(${d-An}),#${s1-imm8},${s2} */
19786 +  {
19787 +    UBICOM32_INSN_ADDC_D_INDIRECT_WITH_OFFSET_4_S1_IMMEDIATE, "addc-d-indirect-with-offset-4-s1-immediate", "addc", 32,
19788 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19789 +  },
19790 +/* addc (${d-An}),#${s1-imm8},${s2} */
19791 +  {
19792 +    UBICOM32_INSN_ADDC_D_INDIRECT_4_S1_IMMEDIATE, "addc-d-indirect-4-s1-immediate", "addc", 32,
19793 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19794 +  },
19795 +/* addc (${d-An})${d-i4-4}++,#${s1-imm8},${s2} */
19796 +  {
19797 +    UBICOM32_INSN_ADDC_D_INDIRECT_WITH_POST_INCREMENT_4_S1_IMMEDIATE, "addc-d-indirect-with-post-increment-4-s1-immediate", "addc", 32,
19798 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19799 +  },
19800 +/* addc ${d-i4-4}(${d-An})++,#${s1-imm8},${s2} */
19801 +  {
19802 +    UBICOM32_INSN_ADDC_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_IMMEDIATE, "addc-d-indirect-with-pre-increment-4-s1-immediate", "addc", 32,
19803 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19804 +  },
19805 +/* addc ${d-direct-addr},(${s1-An},${s1-r}),${s2} */
19806 +  {
19807 +    UBICOM32_INSN_ADDC_D_DIRECT_S1_INDIRECT_WITH_INDEX_4, "addc-d-direct-s1-indirect-with-index-4", "addc", 32,
19808 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19809 +  },
19810 +/* addc #${d-imm8},(${s1-An},${s1-r}),${s2} */
19811 +  {
19812 +    UBICOM32_INSN_ADDC_D_IMMEDIATE_4_S1_INDIRECT_WITH_INDEX_4, "addc-d-immediate-4-s1-indirect-with-index-4", "addc", 32,
19813 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19814 +  },
19815 +/* addc (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */
19816 +  {
19817 +    UBICOM32_INSN_ADDC_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_INDEX_4, "addc-d-indirect-with-index-4-s1-indirect-with-index-4", "addc", 32,
19818 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19819 +  },
19820 +/* addc ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}),${s2} */
19821 +  {
19822 +    UBICOM32_INSN_ADDC_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_INDEX_4, "addc-d-indirect-with-offset-4-s1-indirect-with-index-4", "addc", 32,
19823 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19824 +  },
19825 +/* addc (${d-An}),(${s1-An},${s1-r}),${s2} */
19826 +  {
19827 +    UBICOM32_INSN_ADDC_D_INDIRECT_4_S1_INDIRECT_WITH_INDEX_4, "addc-d-indirect-4-s1-indirect-with-index-4", "addc", 32,
19828 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19829 +  },
19830 +/* addc (${d-An})${d-i4-4}++,(${s1-An},${s1-r}),${s2} */
19831 +  {
19832 +    UBICOM32_INSN_ADDC_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, "addc-d-indirect-with-post-increment-4-s1-indirect-with-index-4", "addc", 32,
19833 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19834 +  },
19835 +/* addc ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}),${s2} */
19836 +  {
19837 +    UBICOM32_INSN_ADDC_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, "addc-d-indirect-with-pre-increment-4-s1-indirect-with-index-4", "addc", 32,
19838 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19839 +  },
19840 +/* addc ${d-direct-addr},${s1-imm7-4}(${s1-An}),${s2} */
19841 +  {
19842 +    UBICOM32_INSN_ADDC_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4, "addc-d-direct-s1-indirect-with-offset-4", "addc", 32,
19843 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19844 +  },
19845 +/* addc #${d-imm8},${s1-imm7-4}(${s1-An}),${s2} */
19846 +  {
19847 +    UBICOM32_INSN_ADDC_D_IMMEDIATE_4_S1_INDIRECT_WITH_OFFSET_4, "addc-d-immediate-4-s1-indirect-with-offset-4", "addc", 32,
19848 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19849 +  },
19850 +/* addc (${d-An},${d-r}),${s1-imm7-4}(${s1-An}),${s2} */
19851 +  {
19852 +    UBICOM32_INSN_ADDC_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_OFFSET_4, "addc-d-indirect-with-index-4-s1-indirect-with-offset-4", "addc", 32,
19853 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19854 +  },
19855 +/* addc ${d-imm7-4}(${d-An}),${s1-imm7-4}(${s1-An}),${s2} */
19856 +  {
19857 +    UBICOM32_INSN_ADDC_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_OFFSET_4, "addc-d-indirect-with-offset-4-s1-indirect-with-offset-4", "addc", 32,
19858 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19859 +  },
19860 +/* addc (${d-An}),${s1-imm7-4}(${s1-An}),${s2} */
19861 +  {
19862 +    UBICOM32_INSN_ADDC_D_INDIRECT_4_S1_INDIRECT_WITH_OFFSET_4, "addc-d-indirect-4-s1-indirect-with-offset-4", "addc", 32,
19863 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19864 +  },
19865 +/* addc (${d-An})${d-i4-4}++,${s1-imm7-4}(${s1-An}),${s2} */
19866 +  {
19867 +    UBICOM32_INSN_ADDC_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, "addc-d-indirect-with-post-increment-4-s1-indirect-with-offset-4", "addc", 32,
19868 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19869 +  },
19870 +/* addc ${d-i4-4}(${d-An})++,${s1-imm7-4}(${s1-An}),${s2} */
19871 +  {
19872 +    UBICOM32_INSN_ADDC_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, "addc-d-indirect-with-pre-increment-4-s1-indirect-with-offset-4", "addc", 32,
19873 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19874 +  },
19875 +/* addc ${d-direct-addr},(${s1-An}),${s2} */
19876 +  {
19877 +    UBICOM32_INSN_ADDC_D_DIRECT_S1_INDIRECT_4, "addc-d-direct-s1-indirect-4", "addc", 32,
19878 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19879 +  },
19880 +/* addc #${d-imm8},(${s1-An}),${s2} */
19881 +  {
19882 +    UBICOM32_INSN_ADDC_D_IMMEDIATE_4_S1_INDIRECT_4, "addc-d-immediate-4-s1-indirect-4", "addc", 32,
19883 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19884 +  },
19885 +/* addc (${d-An},${d-r}),(${s1-An}),${s2} */
19886 +  {
19887 +    UBICOM32_INSN_ADDC_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_4, "addc-d-indirect-with-index-4-s1-indirect-4", "addc", 32,
19888 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19889 +  },
19890 +/* addc ${d-imm7-4}(${d-An}),(${s1-An}),${s2} */
19891 +  {
19892 +    UBICOM32_INSN_ADDC_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_4, "addc-d-indirect-with-offset-4-s1-indirect-4", "addc", 32,
19893 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19894 +  },
19895 +/* addc (${d-An}),(${s1-An}),${s2} */
19896 +  {
19897 +    UBICOM32_INSN_ADDC_D_INDIRECT_4_S1_INDIRECT_4, "addc-d-indirect-4-s1-indirect-4", "addc", 32,
19898 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19899 +  },
19900 +/* addc (${d-An})${d-i4-4}++,(${s1-An}),${s2} */
19901 +  {
19902 +    UBICOM32_INSN_ADDC_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_4, "addc-d-indirect-with-post-increment-4-s1-indirect-4", "addc", 32,
19903 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19904 +  },
19905 +/* addc ${d-i4-4}(${d-An})++,(${s1-An}),${s2} */
19906 +  {
19907 +    UBICOM32_INSN_ADDC_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_4, "addc-d-indirect-with-pre-increment-4-s1-indirect-4", "addc", 32,
19908 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19909 +  },
19910 +/* addc ${d-direct-addr},(${s1-An})${s1-i4-4}++,${s2} */
19911 +  {
19912 +    UBICOM32_INSN_ADDC_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4, "addc-d-direct-s1-indirect-with-post-increment-4", "addc", 32,
19913 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19914 +  },
19915 +/* addc #${d-imm8},(${s1-An})${s1-i4-4}++,${s2} */
19916 +  {
19917 +    UBICOM32_INSN_ADDC_D_IMMEDIATE_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "addc-d-immediate-4-s1-indirect-with-post-increment-4", "addc", 32,
19918 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19919 +  },
19920 +/* addc (${d-An},${d-r}),(${s1-An})${s1-i4-4}++,${s2} */
19921 +  {
19922 +    UBICOM32_INSN_ADDC_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "addc-d-indirect-with-index-4-s1-indirect-with-post-increment-4", "addc", 32,
19923 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19924 +  },
19925 +/* addc ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-4}++,${s2} */
19926 +  {
19927 +    UBICOM32_INSN_ADDC_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "addc-d-indirect-with-offset-4-s1-indirect-with-post-increment-4", "addc", 32,
19928 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19929 +  },
19930 +/* addc (${d-An}),(${s1-An})${s1-i4-4}++,${s2} */
19931 +  {
19932 +    UBICOM32_INSN_ADDC_D_INDIRECT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "addc-d-indirect-4-s1-indirect-with-post-increment-4", "addc", 32,
19933 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19934 +  },
19935 +/* addc (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-4}++,${s2} */
19936 +  {
19937 +    UBICOM32_INSN_ADDC_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "addc-d-indirect-with-post-increment-4-s1-indirect-with-post-increment-4", "addc", 32,
19938 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19939 +  },
19940 +/* addc ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-4}++,${s2} */
19941 +  {
19942 +    UBICOM32_INSN_ADDC_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "addc-d-indirect-with-pre-increment-4-s1-indirect-with-post-increment-4", "addc", 32,
19943 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19944 +  },
19945 +/* addc ${d-direct-addr},${s1-i4-4}(${s1-An})++,${s2} */
19946 +  {
19947 +    UBICOM32_INSN_ADDC_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4, "addc-d-direct-s1-indirect-with-pre-increment-4", "addc", 32,
19948 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19949 +  },
19950 +/* addc #${d-imm8},${s1-i4-4}(${s1-An})++,${s2} */
19951 +  {
19952 +    UBICOM32_INSN_ADDC_D_IMMEDIATE_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "addc-d-immediate-4-s1-indirect-with-pre-increment-4", "addc", 32,
19953 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19954 +  },
19955 +/* addc (${d-An},${d-r}),${s1-i4-4}(${s1-An})++,${s2} */
19956 +  {
19957 +    UBICOM32_INSN_ADDC_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "addc-d-indirect-with-index-4-s1-indirect-with-pre-increment-4", "addc", 32,
19958 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19959 +  },
19960 +/* addc ${d-imm7-4}(${d-An}),${s1-i4-4}(${s1-An})++,${s2} */
19961 +  {
19962 +    UBICOM32_INSN_ADDC_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "addc-d-indirect-with-offset-4-s1-indirect-with-pre-increment-4", "addc", 32,
19963 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19964 +  },
19965 +/* addc (${d-An}),${s1-i4-4}(${s1-An})++,${s2} */
19966 +  {
19967 +    UBICOM32_INSN_ADDC_D_INDIRECT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "addc-d-indirect-4-s1-indirect-with-pre-increment-4", "addc", 32,
19968 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19969 +  },
19970 +/* addc (${d-An})${d-i4-4}++,${s1-i4-4}(${s1-An})++,${s2} */
19971 +  {
19972 +    UBICOM32_INSN_ADDC_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "addc-d-indirect-with-post-increment-4-s1-indirect-with-pre-increment-4", "addc", 32,
19973 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19974 +  },
19975 +/* addc ${d-i4-4}(${d-An})++,${s1-i4-4}(${s1-An})++,${s2} */
19976 +  {
19977 +    UBICOM32_INSN_ADDC_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "addc-d-indirect-with-pre-increment-4-s1-indirect-with-pre-increment-4", "addc", 32,
19978 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
19979 +  },
19980 +/* sub.1 ${d-direct-addr},${s1-direct-addr},${s2} */
19981 +  {
19982 +    UBICOM32_INSN_SUB_1_D_DIRECT_S1_DIRECT, "sub.1-d-direct-s1-direct", "sub.1", 32,
19983 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19984 +  },
19985 +/* sub.1 #${d-imm8},${s1-direct-addr},${s2} */
19986 +  {
19987 +    UBICOM32_INSN_SUB_1_D_IMMEDIATE_1_S1_DIRECT, "sub.1-d-immediate-1-s1-direct", "sub.1", 32,
19988 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19989 +  },
19990 +/* sub.1 (${d-An},${d-r}),${s1-direct-addr},${s2} */
19991 +  {
19992 +    UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_INDEX_1_S1_DIRECT, "sub.1-d-indirect-with-index-1-s1-direct", "sub.1", 32,
19993 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19994 +  },
19995 +/* sub.1 ${d-imm7-1}(${d-An}),${s1-direct-addr},${s2} */
19996 +  {
19997 +    UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_OFFSET_1_S1_DIRECT, "sub.1-d-indirect-with-offset-1-s1-direct", "sub.1", 32,
19998 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
19999 +  },
20000 +/* sub.1 (${d-An}),${s1-direct-addr},${s2} */
20001 +  {
20002 +    UBICOM32_INSN_SUB_1_D_INDIRECT_1_S1_DIRECT, "sub.1-d-indirect-1-s1-direct", "sub.1", 32,
20003 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20004 +  },
20005 +/* sub.1 (${d-An})${d-i4-1}++,${s1-direct-addr},${s2} */
20006 +  {
20007 +    UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_DIRECT, "sub.1-d-indirect-with-post-increment-1-s1-direct", "sub.1", 32,
20008 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20009 +  },
20010 +/* sub.1 ${d-i4-1}(${d-An})++,${s1-direct-addr},${s2} */
20011 +  {
20012 +    UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_DIRECT, "sub.1-d-indirect-with-pre-increment-1-s1-direct", "sub.1", 32,
20013 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20014 +  },
20015 +/* sub.1 ${d-direct-addr},#${s1-imm8},${s2} */
20016 +  {
20017 +    UBICOM32_INSN_SUB_1_D_DIRECT_S1_IMMEDIATE, "sub.1-d-direct-s1-immediate", "sub.1", 32,
20018 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20019 +  },
20020 +/* sub.1 #${d-imm8},#${s1-imm8},${s2} */
20021 +  {
20022 +    UBICOM32_INSN_SUB_1_D_IMMEDIATE_1_S1_IMMEDIATE, "sub.1-d-immediate-1-s1-immediate", "sub.1", 32,
20023 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20024 +  },
20025 +/* sub.1 (${d-An},${d-r}),#${s1-imm8},${s2} */
20026 +  {
20027 +    UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_INDEX_1_S1_IMMEDIATE, "sub.1-d-indirect-with-index-1-s1-immediate", "sub.1", 32,
20028 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20029 +  },
20030 +/* sub.1 ${d-imm7-1}(${d-An}),#${s1-imm8},${s2} */
20031 +  {
20032 +    UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_OFFSET_1_S1_IMMEDIATE, "sub.1-d-indirect-with-offset-1-s1-immediate", "sub.1", 32,
20033 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20034 +  },
20035 +/* sub.1 (${d-An}),#${s1-imm8},${s2} */
20036 +  {
20037 +    UBICOM32_INSN_SUB_1_D_INDIRECT_1_S1_IMMEDIATE, "sub.1-d-indirect-1-s1-immediate", "sub.1", 32,
20038 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20039 +  },
20040 +/* sub.1 (${d-An})${d-i4-1}++,#${s1-imm8},${s2} */
20041 +  {
20042 +    UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_IMMEDIATE, "sub.1-d-indirect-with-post-increment-1-s1-immediate", "sub.1", 32,
20043 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20044 +  },
20045 +/* sub.1 ${d-i4-1}(${d-An})++,#${s1-imm8},${s2} */
20046 +  {
20047 +    UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_IMMEDIATE, "sub.1-d-indirect-with-pre-increment-1-s1-immediate", "sub.1", 32,
20048 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20049 +  },
20050 +/* sub.1 ${d-direct-addr},(${s1-An},${s1-r}),${s2} */
20051 +  {
20052 +    UBICOM32_INSN_SUB_1_D_DIRECT_S1_INDIRECT_WITH_INDEX_1, "sub.1-d-direct-s1-indirect-with-index-1", "sub.1", 32,
20053 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20054 +  },
20055 +/* sub.1 #${d-imm8},(${s1-An},${s1-r}),${s2} */
20056 +  {
20057 +    UBICOM32_INSN_SUB_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_INDEX_1, "sub.1-d-immediate-1-s1-indirect-with-index-1", "sub.1", 32,
20058 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20059 +  },
20060 +/* sub.1 (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */
20061 +  {
20062 +    UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_INDEX_1, "sub.1-d-indirect-with-index-1-s1-indirect-with-index-1", "sub.1", 32,
20063 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20064 +  },
20065 +/* sub.1 ${d-imm7-1}(${d-An}),(${s1-An},${s1-r}),${s2} */
20066 +  {
20067 +    UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_INDEX_1, "sub.1-d-indirect-with-offset-1-s1-indirect-with-index-1", "sub.1", 32,
20068 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20069 +  },
20070 +/* sub.1 (${d-An}),(${s1-An},${s1-r}),${s2} */
20071 +  {
20072 +    UBICOM32_INSN_SUB_1_D_INDIRECT_1_S1_INDIRECT_WITH_INDEX_1, "sub.1-d-indirect-1-s1-indirect-with-index-1", "sub.1", 32,
20073 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20074 +  },
20075 +/* sub.1 (${d-An})${d-i4-1}++,(${s1-An},${s1-r}),${s2} */
20076 +  {
20077 +    UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_INDEX_1, "sub.1-d-indirect-with-post-increment-1-s1-indirect-with-index-1", "sub.1", 32,
20078 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20079 +  },
20080 +/* sub.1 ${d-i4-1}(${d-An})++,(${s1-An},${s1-r}),${s2} */
20081 +  {
20082 +    UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_INDEX_1, "sub.1-d-indirect-with-pre-increment-1-s1-indirect-with-index-1", "sub.1", 32,
20083 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20084 +  },
20085 +/* sub.1 ${d-direct-addr},${s1-imm7-1}(${s1-An}),${s2} */
20086 +  {
20087 +    UBICOM32_INSN_SUB_1_D_DIRECT_S1_INDIRECT_WITH_OFFSET_1, "sub.1-d-direct-s1-indirect-with-offset-1", "sub.1", 32,
20088 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20089 +  },
20090 +/* sub.1 #${d-imm8},${s1-imm7-1}(${s1-An}),${s2} */
20091 +  {
20092 +    UBICOM32_INSN_SUB_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_OFFSET_1, "sub.1-d-immediate-1-s1-indirect-with-offset-1", "sub.1", 32,
20093 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20094 +  },
20095 +/* sub.1 (${d-An},${d-r}),${s1-imm7-1}(${s1-An}),${s2} */
20096 +  {
20097 +    UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_OFFSET_1, "sub.1-d-indirect-with-index-1-s1-indirect-with-offset-1", "sub.1", 32,
20098 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20099 +  },
20100 +/* sub.1 ${d-imm7-1}(${d-An}),${s1-imm7-1}(${s1-An}),${s2} */
20101 +  {
20102 +    UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_OFFSET_1, "sub.1-d-indirect-with-offset-1-s1-indirect-with-offset-1", "sub.1", 32,
20103 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20104 +  },
20105 +/* sub.1 (${d-An}),${s1-imm7-1}(${s1-An}),${s2} */
20106 +  {
20107 +    UBICOM32_INSN_SUB_1_D_INDIRECT_1_S1_INDIRECT_WITH_OFFSET_1, "sub.1-d-indirect-1-s1-indirect-with-offset-1", "sub.1", 32,
20108 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20109 +  },
20110 +/* sub.1 (${d-An})${d-i4-1}++,${s1-imm7-1}(${s1-An}),${s2} */
20111 +  {
20112 +    UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_OFFSET_1, "sub.1-d-indirect-with-post-increment-1-s1-indirect-with-offset-1", "sub.1", 32,
20113 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20114 +  },
20115 +/* sub.1 ${d-i4-1}(${d-An})++,${s1-imm7-1}(${s1-An}),${s2} */
20116 +  {
20117 +    UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_OFFSET_1, "sub.1-d-indirect-with-pre-increment-1-s1-indirect-with-offset-1", "sub.1", 32,
20118 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20119 +  },
20120 +/* sub.1 ${d-direct-addr},(${s1-An}),${s2} */
20121 +  {
20122 +    UBICOM32_INSN_SUB_1_D_DIRECT_S1_INDIRECT_1, "sub.1-d-direct-s1-indirect-1", "sub.1", 32,
20123 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20124 +  },
20125 +/* sub.1 #${d-imm8},(${s1-An}),${s2} */
20126 +  {
20127 +    UBICOM32_INSN_SUB_1_D_IMMEDIATE_1_S1_INDIRECT_1, "sub.1-d-immediate-1-s1-indirect-1", "sub.1", 32,
20128 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20129 +  },
20130 +/* sub.1 (${d-An},${d-r}),(${s1-An}),${s2} */
20131 +  {
20132 +    UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_1, "sub.1-d-indirect-with-index-1-s1-indirect-1", "sub.1", 32,
20133 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20134 +  },
20135 +/* sub.1 ${d-imm7-1}(${d-An}),(${s1-An}),${s2} */
20136 +  {
20137 +    UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_1, "sub.1-d-indirect-with-offset-1-s1-indirect-1", "sub.1", 32,
20138 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20139 +  },
20140 +/* sub.1 (${d-An}),(${s1-An}),${s2} */
20141 +  {
20142 +    UBICOM32_INSN_SUB_1_D_INDIRECT_1_S1_INDIRECT_1, "sub.1-d-indirect-1-s1-indirect-1", "sub.1", 32,
20143 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20144 +  },
20145 +/* sub.1 (${d-An})${d-i4-1}++,(${s1-An}),${s2} */
20146 +  {
20147 +    UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_1, "sub.1-d-indirect-with-post-increment-1-s1-indirect-1", "sub.1", 32,
20148 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20149 +  },
20150 +/* sub.1 ${d-i4-1}(${d-An})++,(${s1-An}),${s2} */
20151 +  {
20152 +    UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_1, "sub.1-d-indirect-with-pre-increment-1-s1-indirect-1", "sub.1", 32,
20153 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20154 +  },
20155 +/* sub.1 ${d-direct-addr},(${s1-An})${s1-i4-1}++,${s2} */
20156 +  {
20157 +    UBICOM32_INSN_SUB_1_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_1, "sub.1-d-direct-s1-indirect-with-post-increment-1", "sub.1", 32,
20158 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20159 +  },
20160 +/* sub.1 #${d-imm8},(${s1-An})${s1-i4-1}++,${s2} */
20161 +  {
20162 +    UBICOM32_INSN_SUB_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_POST_INCREMENT_1, "sub.1-d-immediate-1-s1-indirect-with-post-increment-1", "sub.1", 32,
20163 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20164 +  },
20165 +/* sub.1 (${d-An},${d-r}),(${s1-An})${s1-i4-1}++,${s2} */
20166 +  {
20167 +    UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_POST_INCREMENT_1, "sub.1-d-indirect-with-index-1-s1-indirect-with-post-increment-1", "sub.1", 32,
20168 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20169 +  },
20170 +/* sub.1 ${d-imm7-1}(${d-An}),(${s1-An})${s1-i4-1}++,${s2} */
20171 +  {
20172 +    UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_POST_INCREMENT_1, "sub.1-d-indirect-with-offset-1-s1-indirect-with-post-increment-1", "sub.1", 32,
20173 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20174 +  },
20175 +/* sub.1 (${d-An}),(${s1-An})${s1-i4-1}++,${s2} */
20176 +  {
20177 +    UBICOM32_INSN_SUB_1_D_INDIRECT_1_S1_INDIRECT_WITH_POST_INCREMENT_1, "sub.1-d-indirect-1-s1-indirect-with-post-increment-1", "sub.1", 32,
20178 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20179 +  },
20180 +/* sub.1 (${d-An})${d-i4-1}++,(${s1-An})${s1-i4-1}++,${s2} */
20181 +  {
20182 +    UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_POST_INCREMENT_1, "sub.1-d-indirect-with-post-increment-1-s1-indirect-with-post-increment-1", "sub.1", 32,
20183 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20184 +  },
20185 +/* sub.1 ${d-i4-1}(${d-An})++,(${s1-An})${s1-i4-1}++,${s2} */
20186 +  {
20187 +    UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_POST_INCREMENT_1, "sub.1-d-indirect-with-pre-increment-1-s1-indirect-with-post-increment-1", "sub.1", 32,
20188 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20189 +  },
20190 +/* sub.1 ${d-direct-addr},${s1-i4-1}(${s1-An})++,${s2} */
20191 +  {
20192 +    UBICOM32_INSN_SUB_1_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_1, "sub.1-d-direct-s1-indirect-with-pre-increment-1", "sub.1", 32,
20193 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20194 +  },
20195 +/* sub.1 #${d-imm8},${s1-i4-1}(${s1-An})++,${s2} */
20196 +  {
20197 +    UBICOM32_INSN_SUB_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, "sub.1-d-immediate-1-s1-indirect-with-pre-increment-1", "sub.1", 32,
20198 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20199 +  },
20200 +/* sub.1 (${d-An},${d-r}),${s1-i4-1}(${s1-An})++,${s2} */
20201 +  {
20202 +    UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, "sub.1-d-indirect-with-index-1-s1-indirect-with-pre-increment-1", "sub.1", 32,
20203 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20204 +  },
20205 +/* sub.1 ${d-imm7-1}(${d-An}),${s1-i4-1}(${s1-An})++,${s2} */
20206 +  {
20207 +    UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, "sub.1-d-indirect-with-offset-1-s1-indirect-with-pre-increment-1", "sub.1", 32,
20208 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20209 +  },
20210 +/* sub.1 (${d-An}),${s1-i4-1}(${s1-An})++,${s2} */
20211 +  {
20212 +    UBICOM32_INSN_SUB_1_D_INDIRECT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, "sub.1-d-indirect-1-s1-indirect-with-pre-increment-1", "sub.1", 32,
20213 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20214 +  },
20215 +/* sub.1 (${d-An})${d-i4-1}++,${s1-i4-1}(${s1-An})++,${s2} */
20216 +  {
20217 +    UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, "sub.1-d-indirect-with-post-increment-1-s1-indirect-with-pre-increment-1", "sub.1", 32,
20218 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20219 +  },
20220 +/* sub.1 ${d-i4-1}(${d-An})++,${s1-i4-1}(${s1-An})++,${s2} */
20221 +  {
20222 +    UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, "sub.1-d-indirect-with-pre-increment-1-s1-indirect-with-pre-increment-1", "sub.1", 32,
20223 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20224 +  },
20225 +/* sub.4 ${d-direct-addr},${s1-direct-addr},${s2} */
20226 +  {
20227 +    UBICOM32_INSN_SUB_4_D_DIRECT_S1_DIRECT, "sub.4-d-direct-s1-direct", "sub.4", 32,
20228 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20229 +  },
20230 +/* sub.4 #${d-imm8},${s1-direct-addr},${s2} */
20231 +  {
20232 +    UBICOM32_INSN_SUB_4_D_IMMEDIATE_4_S1_DIRECT, "sub.4-d-immediate-4-s1-direct", "sub.4", 32,
20233 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20234 +  },
20235 +/* sub.4 (${d-An},${d-r}),${s1-direct-addr},${s2} */
20236 +  {
20237 +    UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_INDEX_4_S1_DIRECT, "sub.4-d-indirect-with-index-4-s1-direct", "sub.4", 32,
20238 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20239 +  },
20240 +/* sub.4 ${d-imm7-4}(${d-An}),${s1-direct-addr},${s2} */
20241 +  {
20242 +    UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_OFFSET_4_S1_DIRECT, "sub.4-d-indirect-with-offset-4-s1-direct", "sub.4", 32,
20243 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20244 +  },
20245 +/* sub.4 (${d-An}),${s1-direct-addr},${s2} */
20246 +  {
20247 +    UBICOM32_INSN_SUB_4_D_INDIRECT_4_S1_DIRECT, "sub.4-d-indirect-4-s1-direct", "sub.4", 32,
20248 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20249 +  },
20250 +/* sub.4 (${d-An})${d-i4-4}++,${s1-direct-addr},${s2} */
20251 +  {
20252 +    UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_DIRECT, "sub.4-d-indirect-with-post-increment-4-s1-direct", "sub.4", 32,
20253 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20254 +  },
20255 +/* sub.4 ${d-i4-4}(${d-An})++,${s1-direct-addr},${s2} */
20256 +  {
20257 +    UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_DIRECT, "sub.4-d-indirect-with-pre-increment-4-s1-direct", "sub.4", 32,
20258 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20259 +  },
20260 +/* sub.4 ${d-direct-addr},#${s1-imm8},${s2} */
20261 +  {
20262 +    UBICOM32_INSN_SUB_4_D_DIRECT_S1_IMMEDIATE, "sub.4-d-direct-s1-immediate", "sub.4", 32,
20263 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20264 +  },
20265 +/* sub.4 #${d-imm8},#${s1-imm8},${s2} */
20266 +  {
20267 +    UBICOM32_INSN_SUB_4_D_IMMEDIATE_4_S1_IMMEDIATE, "sub.4-d-immediate-4-s1-immediate", "sub.4", 32,
20268 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20269 +  },
20270 +/* sub.4 (${d-An},${d-r}),#${s1-imm8},${s2} */
20271 +  {
20272 +    UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_INDEX_4_S1_IMMEDIATE, "sub.4-d-indirect-with-index-4-s1-immediate", "sub.4", 32,
20273 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20274 +  },
20275 +/* sub.4 ${d-imm7-4}(${d-An}),#${s1-imm8},${s2} */
20276 +  {
20277 +    UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_OFFSET_4_S1_IMMEDIATE, "sub.4-d-indirect-with-offset-4-s1-immediate", "sub.4", 32,
20278 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20279 +  },
20280 +/* sub.4 (${d-An}),#${s1-imm8},${s2} */
20281 +  {
20282 +    UBICOM32_INSN_SUB_4_D_INDIRECT_4_S1_IMMEDIATE, "sub.4-d-indirect-4-s1-immediate", "sub.4", 32,
20283 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20284 +  },
20285 +/* sub.4 (${d-An})${d-i4-4}++,#${s1-imm8},${s2} */
20286 +  {
20287 +    UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_IMMEDIATE, "sub.4-d-indirect-with-post-increment-4-s1-immediate", "sub.4", 32,
20288 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20289 +  },
20290 +/* sub.4 ${d-i4-4}(${d-An})++,#${s1-imm8},${s2} */
20291 +  {
20292 +    UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_IMMEDIATE, "sub.4-d-indirect-with-pre-increment-4-s1-immediate", "sub.4", 32,
20293 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20294 +  },
20295 +/* sub.4 ${d-direct-addr},(${s1-An},${s1-r}),${s2} */
20296 +  {
20297 +    UBICOM32_INSN_SUB_4_D_DIRECT_S1_INDIRECT_WITH_INDEX_4, "sub.4-d-direct-s1-indirect-with-index-4", "sub.4", 32,
20298 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20299 +  },
20300 +/* sub.4 #${d-imm8},(${s1-An},${s1-r}),${s2} */
20301 +  {
20302 +    UBICOM32_INSN_SUB_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_INDEX_4, "sub.4-d-immediate-4-s1-indirect-with-index-4", "sub.4", 32,
20303 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20304 +  },
20305 +/* sub.4 (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */
20306 +  {
20307 +    UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_INDEX_4, "sub.4-d-indirect-with-index-4-s1-indirect-with-index-4", "sub.4", 32,
20308 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20309 +  },
20310 +/* sub.4 ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}),${s2} */
20311 +  {
20312 +    UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_INDEX_4, "sub.4-d-indirect-with-offset-4-s1-indirect-with-index-4", "sub.4", 32,
20313 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20314 +  },
20315 +/* sub.4 (${d-An}),(${s1-An},${s1-r}),${s2} */
20316 +  {
20317 +    UBICOM32_INSN_SUB_4_D_INDIRECT_4_S1_INDIRECT_WITH_INDEX_4, "sub.4-d-indirect-4-s1-indirect-with-index-4", "sub.4", 32,
20318 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20319 +  },
20320 +/* sub.4 (${d-An})${d-i4-4}++,(${s1-An},${s1-r}),${s2} */
20321 +  {
20322 +    UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, "sub.4-d-indirect-with-post-increment-4-s1-indirect-with-index-4", "sub.4", 32,
20323 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20324 +  },
20325 +/* sub.4 ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}),${s2} */
20326 +  {
20327 +    UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, "sub.4-d-indirect-with-pre-increment-4-s1-indirect-with-index-4", "sub.4", 32,
20328 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20329 +  },
20330 +/* sub.4 ${d-direct-addr},${s1-imm7-4}(${s1-An}),${s2} */
20331 +  {
20332 +    UBICOM32_INSN_SUB_4_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4, "sub.4-d-direct-s1-indirect-with-offset-4", "sub.4", 32,
20333 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20334 +  },
20335 +/* sub.4 #${d-imm8},${s1-imm7-4}(${s1-An}),${s2} */
20336 +  {
20337 +    UBICOM32_INSN_SUB_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_OFFSET_4, "sub.4-d-immediate-4-s1-indirect-with-offset-4", "sub.4", 32,
20338 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20339 +  },
20340 +/* sub.4 (${d-An},${d-r}),${s1-imm7-4}(${s1-An}),${s2} */
20341 +  {
20342 +    UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_OFFSET_4, "sub.4-d-indirect-with-index-4-s1-indirect-with-offset-4", "sub.4", 32,
20343 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20344 +  },
20345 +/* sub.4 ${d-imm7-4}(${d-An}),${s1-imm7-4}(${s1-An}),${s2} */
20346 +  {
20347 +    UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_OFFSET_4, "sub.4-d-indirect-with-offset-4-s1-indirect-with-offset-4", "sub.4", 32,
20348 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20349 +  },
20350 +/* sub.4 (${d-An}),${s1-imm7-4}(${s1-An}),${s2} */
20351 +  {
20352 +    UBICOM32_INSN_SUB_4_D_INDIRECT_4_S1_INDIRECT_WITH_OFFSET_4, "sub.4-d-indirect-4-s1-indirect-with-offset-4", "sub.4", 32,
20353 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20354 +  },
20355 +/* sub.4 (${d-An})${d-i4-4}++,${s1-imm7-4}(${s1-An}),${s2} */
20356 +  {
20357 +    UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, "sub.4-d-indirect-with-post-increment-4-s1-indirect-with-offset-4", "sub.4", 32,
20358 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20359 +  },
20360 +/* sub.4 ${d-i4-4}(${d-An})++,${s1-imm7-4}(${s1-An}),${s2} */
20361 +  {
20362 +    UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, "sub.4-d-indirect-with-pre-increment-4-s1-indirect-with-offset-4", "sub.4", 32,
20363 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20364 +  },
20365 +/* sub.4 ${d-direct-addr},(${s1-An}),${s2} */
20366 +  {
20367 +    UBICOM32_INSN_SUB_4_D_DIRECT_S1_INDIRECT_4, "sub.4-d-direct-s1-indirect-4", "sub.4", 32,
20368 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20369 +  },
20370 +/* sub.4 #${d-imm8},(${s1-An}),${s2} */
20371 +  {
20372 +    UBICOM32_INSN_SUB_4_D_IMMEDIATE_4_S1_INDIRECT_4, "sub.4-d-immediate-4-s1-indirect-4", "sub.4", 32,
20373 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20374 +  },
20375 +/* sub.4 (${d-An},${d-r}),(${s1-An}),${s2} */
20376 +  {
20377 +    UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_4, "sub.4-d-indirect-with-index-4-s1-indirect-4", "sub.4", 32,
20378 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20379 +  },
20380 +/* sub.4 ${d-imm7-4}(${d-An}),(${s1-An}),${s2} */
20381 +  {
20382 +    UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_4, "sub.4-d-indirect-with-offset-4-s1-indirect-4", "sub.4", 32,
20383 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20384 +  },
20385 +/* sub.4 (${d-An}),(${s1-An}),${s2} */
20386 +  {
20387 +    UBICOM32_INSN_SUB_4_D_INDIRECT_4_S1_INDIRECT_4, "sub.4-d-indirect-4-s1-indirect-4", "sub.4", 32,
20388 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20389 +  },
20390 +/* sub.4 (${d-An})${d-i4-4}++,(${s1-An}),${s2} */
20391 +  {
20392 +    UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_4, "sub.4-d-indirect-with-post-increment-4-s1-indirect-4", "sub.4", 32,
20393 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20394 +  },
20395 +/* sub.4 ${d-i4-4}(${d-An})++,(${s1-An}),${s2} */
20396 +  {
20397 +    UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_4, "sub.4-d-indirect-with-pre-increment-4-s1-indirect-4", "sub.4", 32,
20398 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20399 +  },
20400 +/* sub.4 ${d-direct-addr},(${s1-An})${s1-i4-4}++,${s2} */
20401 +  {
20402 +    UBICOM32_INSN_SUB_4_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4, "sub.4-d-direct-s1-indirect-with-post-increment-4", "sub.4", 32,
20403 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20404 +  },
20405 +/* sub.4 #${d-imm8},(${s1-An})${s1-i4-4}++,${s2} */
20406 +  {
20407 +    UBICOM32_INSN_SUB_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "sub.4-d-immediate-4-s1-indirect-with-post-increment-4", "sub.4", 32,
20408 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20409 +  },
20410 +/* sub.4 (${d-An},${d-r}),(${s1-An})${s1-i4-4}++,${s2} */
20411 +  {
20412 +    UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "sub.4-d-indirect-with-index-4-s1-indirect-with-post-increment-4", "sub.4", 32,
20413 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20414 +  },
20415 +/* sub.4 ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-4}++,${s2} */
20416 +  {
20417 +    UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "sub.4-d-indirect-with-offset-4-s1-indirect-with-post-increment-4", "sub.4", 32,
20418 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20419 +  },
20420 +/* sub.4 (${d-An}),(${s1-An})${s1-i4-4}++,${s2} */
20421 +  {
20422 +    UBICOM32_INSN_SUB_4_D_INDIRECT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "sub.4-d-indirect-4-s1-indirect-with-post-increment-4", "sub.4", 32,
20423 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20424 +  },
20425 +/* sub.4 (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-4}++,${s2} */
20426 +  {
20427 +    UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "sub.4-d-indirect-with-post-increment-4-s1-indirect-with-post-increment-4", "sub.4", 32,
20428 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20429 +  },
20430 +/* sub.4 ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-4}++,${s2} */
20431 +  {
20432 +    UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "sub.4-d-indirect-with-pre-increment-4-s1-indirect-with-post-increment-4", "sub.4", 32,
20433 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20434 +  },
20435 +/* sub.4 ${d-direct-addr},${s1-i4-4}(${s1-An})++,${s2} */
20436 +  {
20437 +    UBICOM32_INSN_SUB_4_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4, "sub.4-d-direct-s1-indirect-with-pre-increment-4", "sub.4", 32,
20438 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20439 +  },
20440 +/* sub.4 #${d-imm8},${s1-i4-4}(${s1-An})++,${s2} */
20441 +  {
20442 +    UBICOM32_INSN_SUB_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "sub.4-d-immediate-4-s1-indirect-with-pre-increment-4", "sub.4", 32,
20443 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20444 +  },
20445 +/* sub.4 (${d-An},${d-r}),${s1-i4-4}(${s1-An})++,${s2} */
20446 +  {
20447 +    UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "sub.4-d-indirect-with-index-4-s1-indirect-with-pre-increment-4", "sub.4", 32,
20448 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20449 +  },
20450 +/* sub.4 ${d-imm7-4}(${d-An}),${s1-i4-4}(${s1-An})++,${s2} */
20451 +  {
20452 +    UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "sub.4-d-indirect-with-offset-4-s1-indirect-with-pre-increment-4", "sub.4", 32,
20453 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20454 +  },
20455 +/* sub.4 (${d-An}),${s1-i4-4}(${s1-An})++,${s2} */
20456 +  {
20457 +    UBICOM32_INSN_SUB_4_D_INDIRECT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "sub.4-d-indirect-4-s1-indirect-with-pre-increment-4", "sub.4", 32,
20458 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20459 +  },
20460 +/* sub.4 (${d-An})${d-i4-4}++,${s1-i4-4}(${s1-An})++,${s2} */
20461 +  {
20462 +    UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "sub.4-d-indirect-with-post-increment-4-s1-indirect-with-pre-increment-4", "sub.4", 32,
20463 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20464 +  },
20465 +/* sub.4 ${d-i4-4}(${d-An})++,${s1-i4-4}(${s1-An})++,${s2} */
20466 +  {
20467 +    UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "sub.4-d-indirect-with-pre-increment-4-s1-indirect-with-pre-increment-4", "sub.4", 32,
20468 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20469 +  },
20470 +/* sub.2 ${d-direct-addr},${s1-direct-addr},${s2} */
20471 +  {
20472 +    UBICOM32_INSN_SUB_2_D_DIRECT_S1_DIRECT, "sub.2-d-direct-s1-direct", "sub.2", 32,
20473 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20474 +  },
20475 +/* sub.2 #${d-imm8},${s1-direct-addr},${s2} */
20476 +  {
20477 +    UBICOM32_INSN_SUB_2_D_IMMEDIATE_2_S1_DIRECT, "sub.2-d-immediate-2-s1-direct", "sub.2", 32,
20478 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20479 +  },
20480 +/* sub.2 (${d-An},${d-r}),${s1-direct-addr},${s2} */
20481 +  {
20482 +    UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_INDEX_2_S1_DIRECT, "sub.2-d-indirect-with-index-2-s1-direct", "sub.2", 32,
20483 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20484 +  },
20485 +/* sub.2 ${d-imm7-2}(${d-An}),${s1-direct-addr},${s2} */
20486 +  {
20487 +    UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_OFFSET_2_S1_DIRECT, "sub.2-d-indirect-with-offset-2-s1-direct", "sub.2", 32,
20488 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20489 +  },
20490 +/* sub.2 (${d-An}),${s1-direct-addr},${s2} */
20491 +  {
20492 +    UBICOM32_INSN_SUB_2_D_INDIRECT_2_S1_DIRECT, "sub.2-d-indirect-2-s1-direct", "sub.2", 32,
20493 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20494 +  },
20495 +/* sub.2 (${d-An})${d-i4-2}++,${s1-direct-addr},${s2} */
20496 +  {
20497 +    UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_DIRECT, "sub.2-d-indirect-with-post-increment-2-s1-direct", "sub.2", 32,
20498 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20499 +  },
20500 +/* sub.2 ${d-i4-2}(${d-An})++,${s1-direct-addr},${s2} */
20501 +  {
20502 +    UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_DIRECT, "sub.2-d-indirect-with-pre-increment-2-s1-direct", "sub.2", 32,
20503 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20504 +  },
20505 +/* sub.2 ${d-direct-addr},#${s1-imm8},${s2} */
20506 +  {
20507 +    UBICOM32_INSN_SUB_2_D_DIRECT_S1_IMMEDIATE, "sub.2-d-direct-s1-immediate", "sub.2", 32,
20508 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20509 +  },
20510 +/* sub.2 #${d-imm8},#${s1-imm8},${s2} */
20511 +  {
20512 +    UBICOM32_INSN_SUB_2_D_IMMEDIATE_2_S1_IMMEDIATE, "sub.2-d-immediate-2-s1-immediate", "sub.2", 32,
20513 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20514 +  },
20515 +/* sub.2 (${d-An},${d-r}),#${s1-imm8},${s2} */
20516 +  {
20517 +    UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_INDEX_2_S1_IMMEDIATE, "sub.2-d-indirect-with-index-2-s1-immediate", "sub.2", 32,
20518 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20519 +  },
20520 +/* sub.2 ${d-imm7-2}(${d-An}),#${s1-imm8},${s2} */
20521 +  {
20522 +    UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_OFFSET_2_S1_IMMEDIATE, "sub.2-d-indirect-with-offset-2-s1-immediate", "sub.2", 32,
20523 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20524 +  },
20525 +/* sub.2 (${d-An}),#${s1-imm8},${s2} */
20526 +  {
20527 +    UBICOM32_INSN_SUB_2_D_INDIRECT_2_S1_IMMEDIATE, "sub.2-d-indirect-2-s1-immediate", "sub.2", 32,
20528 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20529 +  },
20530 +/* sub.2 (${d-An})${d-i4-2}++,#${s1-imm8},${s2} */
20531 +  {
20532 +    UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_IMMEDIATE, "sub.2-d-indirect-with-post-increment-2-s1-immediate", "sub.2", 32,
20533 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20534 +  },
20535 +/* sub.2 ${d-i4-2}(${d-An})++,#${s1-imm8},${s2} */
20536 +  {
20537 +    UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_IMMEDIATE, "sub.2-d-indirect-with-pre-increment-2-s1-immediate", "sub.2", 32,
20538 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20539 +  },
20540 +/* sub.2 ${d-direct-addr},(${s1-An},${s1-r}),${s2} */
20541 +  {
20542 +    UBICOM32_INSN_SUB_2_D_DIRECT_S1_INDIRECT_WITH_INDEX_2, "sub.2-d-direct-s1-indirect-with-index-2", "sub.2", 32,
20543 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20544 +  },
20545 +/* sub.2 #${d-imm8},(${s1-An},${s1-r}),${s2} */
20546 +  {
20547 +    UBICOM32_INSN_SUB_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_INDEX_2, "sub.2-d-immediate-2-s1-indirect-with-index-2", "sub.2", 32,
20548 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20549 +  },
20550 +/* sub.2 (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */
20551 +  {
20552 +    UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_INDEX_2, "sub.2-d-indirect-with-index-2-s1-indirect-with-index-2", "sub.2", 32,
20553 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20554 +  },
20555 +/* sub.2 ${d-imm7-2}(${d-An}),(${s1-An},${s1-r}),${s2} */
20556 +  {
20557 +    UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_INDEX_2, "sub.2-d-indirect-with-offset-2-s1-indirect-with-index-2", "sub.2", 32,
20558 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20559 +  },
20560 +/* sub.2 (${d-An}),(${s1-An},${s1-r}),${s2} */
20561 +  {
20562 +    UBICOM32_INSN_SUB_2_D_INDIRECT_2_S1_INDIRECT_WITH_INDEX_2, "sub.2-d-indirect-2-s1-indirect-with-index-2", "sub.2", 32,
20563 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20564 +  },
20565 +/* sub.2 (${d-An})${d-i4-2}++,(${s1-An},${s1-r}),${s2} */
20566 +  {
20567 +    UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_INDEX_2, "sub.2-d-indirect-with-post-increment-2-s1-indirect-with-index-2", "sub.2", 32,
20568 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20569 +  },
20570 +/* sub.2 ${d-i4-2}(${d-An})++,(${s1-An},${s1-r}),${s2} */
20571 +  {
20572 +    UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_INDEX_2, "sub.2-d-indirect-with-pre-increment-2-s1-indirect-with-index-2", "sub.2", 32,
20573 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20574 +  },
20575 +/* sub.2 ${d-direct-addr},${s1-imm7-2}(${s1-An}),${s2} */
20576 +  {
20577 +    UBICOM32_INSN_SUB_2_D_DIRECT_S1_INDIRECT_WITH_OFFSET_2, "sub.2-d-direct-s1-indirect-with-offset-2", "sub.2", 32,
20578 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20579 +  },
20580 +/* sub.2 #${d-imm8},${s1-imm7-2}(${s1-An}),${s2} */
20581 +  {
20582 +    UBICOM32_INSN_SUB_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_OFFSET_2, "sub.2-d-immediate-2-s1-indirect-with-offset-2", "sub.2", 32,
20583 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20584 +  },
20585 +/* sub.2 (${d-An},${d-r}),${s1-imm7-2}(${s1-An}),${s2} */
20586 +  {
20587 +    UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_OFFSET_2, "sub.2-d-indirect-with-index-2-s1-indirect-with-offset-2", "sub.2", 32,
20588 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20589 +  },
20590 +/* sub.2 ${d-imm7-2}(${d-An}),${s1-imm7-2}(${s1-An}),${s2} */
20591 +  {
20592 +    UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_OFFSET_2, "sub.2-d-indirect-with-offset-2-s1-indirect-with-offset-2", "sub.2", 32,
20593 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20594 +  },
20595 +/* sub.2 (${d-An}),${s1-imm7-2}(${s1-An}),${s2} */
20596 +  {
20597 +    UBICOM32_INSN_SUB_2_D_INDIRECT_2_S1_INDIRECT_WITH_OFFSET_2, "sub.2-d-indirect-2-s1-indirect-with-offset-2", "sub.2", 32,
20598 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20599 +  },
20600 +/* sub.2 (${d-An})${d-i4-2}++,${s1-imm7-2}(${s1-An}),${s2} */
20601 +  {
20602 +    UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_2, "sub.2-d-indirect-with-post-increment-2-s1-indirect-with-offset-2", "sub.2", 32,
20603 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20604 +  },
20605 +/* sub.2 ${d-i4-2}(${d-An})++,${s1-imm7-2}(${s1-An}),${s2} */
20606 +  {
20607 +    UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_2, "sub.2-d-indirect-with-pre-increment-2-s1-indirect-with-offset-2", "sub.2", 32,
20608 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20609 +  },
20610 +/* sub.2 ${d-direct-addr},(${s1-An}),${s2} */
20611 +  {
20612 +    UBICOM32_INSN_SUB_2_D_DIRECT_S1_INDIRECT_2, "sub.2-d-direct-s1-indirect-2", "sub.2", 32,
20613 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20614 +  },
20615 +/* sub.2 #${d-imm8},(${s1-An}),${s2} */
20616 +  {
20617 +    UBICOM32_INSN_SUB_2_D_IMMEDIATE_2_S1_INDIRECT_2, "sub.2-d-immediate-2-s1-indirect-2", "sub.2", 32,
20618 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20619 +  },
20620 +/* sub.2 (${d-An},${d-r}),(${s1-An}),${s2} */
20621 +  {
20622 +    UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_2, "sub.2-d-indirect-with-index-2-s1-indirect-2", "sub.2", 32,
20623 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20624 +  },
20625 +/* sub.2 ${d-imm7-2}(${d-An}),(${s1-An}),${s2} */
20626 +  {
20627 +    UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_2, "sub.2-d-indirect-with-offset-2-s1-indirect-2", "sub.2", 32,
20628 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20629 +  },
20630 +/* sub.2 (${d-An}),(${s1-An}),${s2} */
20631 +  {
20632 +    UBICOM32_INSN_SUB_2_D_INDIRECT_2_S1_INDIRECT_2, "sub.2-d-indirect-2-s1-indirect-2", "sub.2", 32,
20633 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20634 +  },
20635 +/* sub.2 (${d-An})${d-i4-2}++,(${s1-An}),${s2} */
20636 +  {
20637 +    UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_2, "sub.2-d-indirect-with-post-increment-2-s1-indirect-2", "sub.2", 32,
20638 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20639 +  },
20640 +/* sub.2 ${d-i4-2}(${d-An})++,(${s1-An}),${s2} */
20641 +  {
20642 +    UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_2, "sub.2-d-indirect-with-pre-increment-2-s1-indirect-2", "sub.2", 32,
20643 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20644 +  },
20645 +/* sub.2 ${d-direct-addr},(${s1-An})${s1-i4-2}++,${s2} */
20646 +  {
20647 +    UBICOM32_INSN_SUB_2_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_2, "sub.2-d-direct-s1-indirect-with-post-increment-2", "sub.2", 32,
20648 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20649 +  },
20650 +/* sub.2 #${d-imm8},(${s1-An})${s1-i4-2}++,${s2} */
20651 +  {
20652 +    UBICOM32_INSN_SUB_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_POST_INCREMENT_2, "sub.2-d-immediate-2-s1-indirect-with-post-increment-2", "sub.2", 32,
20653 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20654 +  },
20655 +/* sub.2 (${d-An},${d-r}),(${s1-An})${s1-i4-2}++,${s2} */
20656 +  {
20657 +    UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_POST_INCREMENT_2, "sub.2-d-indirect-with-index-2-s1-indirect-with-post-increment-2", "sub.2", 32,
20658 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20659 +  },
20660 +/* sub.2 ${d-imm7-2}(${d-An}),(${s1-An})${s1-i4-2}++,${s2} */
20661 +  {
20662 +    UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_POST_INCREMENT_2, "sub.2-d-indirect-with-offset-2-s1-indirect-with-post-increment-2", "sub.2", 32,
20663 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20664 +  },
20665 +/* sub.2 (${d-An}),(${s1-An})${s1-i4-2}++,${s2} */
20666 +  {
20667 +    UBICOM32_INSN_SUB_2_D_INDIRECT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, "sub.2-d-indirect-2-s1-indirect-with-post-increment-2", "sub.2", 32,
20668 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20669 +  },
20670 +/* sub.2 (${d-An})${d-i4-2}++,(${s1-An})${s1-i4-2}++,${s2} */
20671 +  {
20672 +    UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, "sub.2-d-indirect-with-post-increment-2-s1-indirect-with-post-increment-2", "sub.2", 32,
20673 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20674 +  },
20675 +/* sub.2 ${d-i4-2}(${d-An})++,(${s1-An})${s1-i4-2}++,${s2} */
20676 +  {
20677 +    UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, "sub.2-d-indirect-with-pre-increment-2-s1-indirect-with-post-increment-2", "sub.2", 32,
20678 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20679 +  },
20680 +/* sub.2 ${d-direct-addr},${s1-i4-2}(${s1-An})++,${s2} */
20681 +  {
20682 +    UBICOM32_INSN_SUB_2_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_2, "sub.2-d-direct-s1-indirect-with-pre-increment-2", "sub.2", 32,
20683 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20684 +  },
20685 +/* sub.2 #${d-imm8},${s1-i4-2}(${s1-An})++,${s2} */
20686 +  {
20687 +    UBICOM32_INSN_SUB_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, "sub.2-d-immediate-2-s1-indirect-with-pre-increment-2", "sub.2", 32,
20688 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20689 +  },
20690 +/* sub.2 (${d-An},${d-r}),${s1-i4-2}(${s1-An})++,${s2} */
20691 +  {
20692 +    UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, "sub.2-d-indirect-with-index-2-s1-indirect-with-pre-increment-2", "sub.2", 32,
20693 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20694 +  },
20695 +/* sub.2 ${d-imm7-2}(${d-An}),${s1-i4-2}(${s1-An})++,${s2} */
20696 +  {
20697 +    UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, "sub.2-d-indirect-with-offset-2-s1-indirect-with-pre-increment-2", "sub.2", 32,
20698 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20699 +  },
20700 +/* sub.2 (${d-An}),${s1-i4-2}(${s1-An})++,${s2} */
20701 +  {
20702 +    UBICOM32_INSN_SUB_2_D_INDIRECT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, "sub.2-d-indirect-2-s1-indirect-with-pre-increment-2", "sub.2", 32,
20703 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20704 +  },
20705 +/* sub.2 (${d-An})${d-i4-2}++,${s1-i4-2}(${s1-An})++,${s2} */
20706 +  {
20707 +    UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, "sub.2-d-indirect-with-post-increment-2-s1-indirect-with-pre-increment-2", "sub.2", 32,
20708 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20709 +  },
20710 +/* sub.2 ${d-i4-2}(${d-An})++,${s1-i4-2}(${s1-An})++,${s2} */
20711 +  {
20712 +    UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, "sub.2-d-indirect-with-pre-increment-2-s1-indirect-with-pre-increment-2", "sub.2", 32,
20713 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20714 +  },
20715 +/* add.1 ${d-direct-addr},${s1-direct-addr},${s2} */
20716 +  {
20717 +    UBICOM32_INSN_ADD_1_D_DIRECT_S1_DIRECT, "add.1-d-direct-s1-direct", "add.1", 32,
20718 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20719 +  },
20720 +/* add.1 #${d-imm8},${s1-direct-addr},${s2} */
20721 +  {
20722 +    UBICOM32_INSN_ADD_1_D_IMMEDIATE_1_S1_DIRECT, "add.1-d-immediate-1-s1-direct", "add.1", 32,
20723 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20724 +  },
20725 +/* add.1 (${d-An},${d-r}),${s1-direct-addr},${s2} */
20726 +  {
20727 +    UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_INDEX_1_S1_DIRECT, "add.1-d-indirect-with-index-1-s1-direct", "add.1", 32,
20728 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20729 +  },
20730 +/* add.1 ${d-imm7-1}(${d-An}),${s1-direct-addr},${s2} */
20731 +  {
20732 +    UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_OFFSET_1_S1_DIRECT, "add.1-d-indirect-with-offset-1-s1-direct", "add.1", 32,
20733 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20734 +  },
20735 +/* add.1 (${d-An}),${s1-direct-addr},${s2} */
20736 +  {
20737 +    UBICOM32_INSN_ADD_1_D_INDIRECT_1_S1_DIRECT, "add.1-d-indirect-1-s1-direct", "add.1", 32,
20738 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20739 +  },
20740 +/* add.1 (${d-An})${d-i4-1}++,${s1-direct-addr},${s2} */
20741 +  {
20742 +    UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_DIRECT, "add.1-d-indirect-with-post-increment-1-s1-direct", "add.1", 32,
20743 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20744 +  },
20745 +/* add.1 ${d-i4-1}(${d-An})++,${s1-direct-addr},${s2} */
20746 +  {
20747 +    UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_DIRECT, "add.1-d-indirect-with-pre-increment-1-s1-direct", "add.1", 32,
20748 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20749 +  },
20750 +/* add.1 ${d-direct-addr},#${s1-imm8},${s2} */
20751 +  {
20752 +    UBICOM32_INSN_ADD_1_D_DIRECT_S1_IMMEDIATE, "add.1-d-direct-s1-immediate", "add.1", 32,
20753 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20754 +  },
20755 +/* add.1 #${d-imm8},#${s1-imm8},${s2} */
20756 +  {
20757 +    UBICOM32_INSN_ADD_1_D_IMMEDIATE_1_S1_IMMEDIATE, "add.1-d-immediate-1-s1-immediate", "add.1", 32,
20758 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20759 +  },
20760 +/* add.1 (${d-An},${d-r}),#${s1-imm8},${s2} */
20761 +  {
20762 +    UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_INDEX_1_S1_IMMEDIATE, "add.1-d-indirect-with-index-1-s1-immediate", "add.1", 32,
20763 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20764 +  },
20765 +/* add.1 ${d-imm7-1}(${d-An}),#${s1-imm8},${s2} */
20766 +  {
20767 +    UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_OFFSET_1_S1_IMMEDIATE, "add.1-d-indirect-with-offset-1-s1-immediate", "add.1", 32,
20768 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20769 +  },
20770 +/* add.1 (${d-An}),#${s1-imm8},${s2} */
20771 +  {
20772 +    UBICOM32_INSN_ADD_1_D_INDIRECT_1_S1_IMMEDIATE, "add.1-d-indirect-1-s1-immediate", "add.1", 32,
20773 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20774 +  },
20775 +/* add.1 (${d-An})${d-i4-1}++,#${s1-imm8},${s2} */
20776 +  {
20777 +    UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_IMMEDIATE, "add.1-d-indirect-with-post-increment-1-s1-immediate", "add.1", 32,
20778 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20779 +  },
20780 +/* add.1 ${d-i4-1}(${d-An})++,#${s1-imm8},${s2} */
20781 +  {
20782 +    UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_IMMEDIATE, "add.1-d-indirect-with-pre-increment-1-s1-immediate", "add.1", 32,
20783 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20784 +  },
20785 +/* add.1 ${d-direct-addr},(${s1-An},${s1-r}),${s2} */
20786 +  {
20787 +    UBICOM32_INSN_ADD_1_D_DIRECT_S1_INDIRECT_WITH_INDEX_1, "add.1-d-direct-s1-indirect-with-index-1", "add.1", 32,
20788 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20789 +  },
20790 +/* add.1 #${d-imm8},(${s1-An},${s1-r}),${s2} */
20791 +  {
20792 +    UBICOM32_INSN_ADD_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_INDEX_1, "add.1-d-immediate-1-s1-indirect-with-index-1", "add.1", 32,
20793 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20794 +  },
20795 +/* add.1 (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */
20796 +  {
20797 +    UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_INDEX_1, "add.1-d-indirect-with-index-1-s1-indirect-with-index-1", "add.1", 32,
20798 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20799 +  },
20800 +/* add.1 ${d-imm7-1}(${d-An}),(${s1-An},${s1-r}),${s2} */
20801 +  {
20802 +    UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_INDEX_1, "add.1-d-indirect-with-offset-1-s1-indirect-with-index-1", "add.1", 32,
20803 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20804 +  },
20805 +/* add.1 (${d-An}),(${s1-An},${s1-r}),${s2} */
20806 +  {
20807 +    UBICOM32_INSN_ADD_1_D_INDIRECT_1_S1_INDIRECT_WITH_INDEX_1, "add.1-d-indirect-1-s1-indirect-with-index-1", "add.1", 32,
20808 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20809 +  },
20810 +/* add.1 (${d-An})${d-i4-1}++,(${s1-An},${s1-r}),${s2} */
20811 +  {
20812 +    UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_INDEX_1, "add.1-d-indirect-with-post-increment-1-s1-indirect-with-index-1", "add.1", 32,
20813 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20814 +  },
20815 +/* add.1 ${d-i4-1}(${d-An})++,(${s1-An},${s1-r}),${s2} */
20816 +  {
20817 +    UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_INDEX_1, "add.1-d-indirect-with-pre-increment-1-s1-indirect-with-index-1", "add.1", 32,
20818 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20819 +  },
20820 +/* add.1 ${d-direct-addr},${s1-imm7-1}(${s1-An}),${s2} */
20821 +  {
20822 +    UBICOM32_INSN_ADD_1_D_DIRECT_S1_INDIRECT_WITH_OFFSET_1, "add.1-d-direct-s1-indirect-with-offset-1", "add.1", 32,
20823 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20824 +  },
20825 +/* add.1 #${d-imm8},${s1-imm7-1}(${s1-An}),${s2} */
20826 +  {
20827 +    UBICOM32_INSN_ADD_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_OFFSET_1, "add.1-d-immediate-1-s1-indirect-with-offset-1", "add.1", 32,
20828 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20829 +  },
20830 +/* add.1 (${d-An},${d-r}),${s1-imm7-1}(${s1-An}),${s2} */
20831 +  {
20832 +    UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_OFFSET_1, "add.1-d-indirect-with-index-1-s1-indirect-with-offset-1", "add.1", 32,
20833 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20834 +  },
20835 +/* add.1 ${d-imm7-1}(${d-An}),${s1-imm7-1}(${s1-An}),${s2} */
20836 +  {
20837 +    UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_OFFSET_1, "add.1-d-indirect-with-offset-1-s1-indirect-with-offset-1", "add.1", 32,
20838 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20839 +  },
20840 +/* add.1 (${d-An}),${s1-imm7-1}(${s1-An}),${s2} */
20841 +  {
20842 +    UBICOM32_INSN_ADD_1_D_INDIRECT_1_S1_INDIRECT_WITH_OFFSET_1, "add.1-d-indirect-1-s1-indirect-with-offset-1", "add.1", 32,
20843 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20844 +  },
20845 +/* add.1 (${d-An})${d-i4-1}++,${s1-imm7-1}(${s1-An}),${s2} */
20846 +  {
20847 +    UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_OFFSET_1, "add.1-d-indirect-with-post-increment-1-s1-indirect-with-offset-1", "add.1", 32,
20848 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20849 +  },
20850 +/* add.1 ${d-i4-1}(${d-An})++,${s1-imm7-1}(${s1-An}),${s2} */
20851 +  {
20852 +    UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_OFFSET_1, "add.1-d-indirect-with-pre-increment-1-s1-indirect-with-offset-1", "add.1", 32,
20853 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20854 +  },
20855 +/* add.1 ${d-direct-addr},(${s1-An}),${s2} */
20856 +  {
20857 +    UBICOM32_INSN_ADD_1_D_DIRECT_S1_INDIRECT_1, "add.1-d-direct-s1-indirect-1", "add.1", 32,
20858 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20859 +  },
20860 +/* add.1 #${d-imm8},(${s1-An}),${s2} */
20861 +  {
20862 +    UBICOM32_INSN_ADD_1_D_IMMEDIATE_1_S1_INDIRECT_1, "add.1-d-immediate-1-s1-indirect-1", "add.1", 32,
20863 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20864 +  },
20865 +/* add.1 (${d-An},${d-r}),(${s1-An}),${s2} */
20866 +  {
20867 +    UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_1, "add.1-d-indirect-with-index-1-s1-indirect-1", "add.1", 32,
20868 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20869 +  },
20870 +/* add.1 ${d-imm7-1}(${d-An}),(${s1-An}),${s2} */
20871 +  {
20872 +    UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_1, "add.1-d-indirect-with-offset-1-s1-indirect-1", "add.1", 32,
20873 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20874 +  },
20875 +/* add.1 (${d-An}),(${s1-An}),${s2} */
20876 +  {
20877 +    UBICOM32_INSN_ADD_1_D_INDIRECT_1_S1_INDIRECT_1, "add.1-d-indirect-1-s1-indirect-1", "add.1", 32,
20878 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20879 +  },
20880 +/* add.1 (${d-An})${d-i4-1}++,(${s1-An}),${s2} */
20881 +  {
20882 +    UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_1, "add.1-d-indirect-with-post-increment-1-s1-indirect-1", "add.1", 32,
20883 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20884 +  },
20885 +/* add.1 ${d-i4-1}(${d-An})++,(${s1-An}),${s2} */
20886 +  {
20887 +    UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_1, "add.1-d-indirect-with-pre-increment-1-s1-indirect-1", "add.1", 32,
20888 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20889 +  },
20890 +/* add.1 ${d-direct-addr},(${s1-An})${s1-i4-1}++,${s2} */
20891 +  {
20892 +    UBICOM32_INSN_ADD_1_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_1, "add.1-d-direct-s1-indirect-with-post-increment-1", "add.1", 32,
20893 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20894 +  },
20895 +/* add.1 #${d-imm8},(${s1-An})${s1-i4-1}++,${s2} */
20896 +  {
20897 +    UBICOM32_INSN_ADD_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_POST_INCREMENT_1, "add.1-d-immediate-1-s1-indirect-with-post-increment-1", "add.1", 32,
20898 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20899 +  },
20900 +/* add.1 (${d-An},${d-r}),(${s1-An})${s1-i4-1}++,${s2} */
20901 +  {
20902 +    UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_POST_INCREMENT_1, "add.1-d-indirect-with-index-1-s1-indirect-with-post-increment-1", "add.1", 32,
20903 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20904 +  },
20905 +/* add.1 ${d-imm7-1}(${d-An}),(${s1-An})${s1-i4-1}++,${s2} */
20906 +  {
20907 +    UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_POST_INCREMENT_1, "add.1-d-indirect-with-offset-1-s1-indirect-with-post-increment-1", "add.1", 32,
20908 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20909 +  },
20910 +/* add.1 (${d-An}),(${s1-An})${s1-i4-1}++,${s2} */
20911 +  {
20912 +    UBICOM32_INSN_ADD_1_D_INDIRECT_1_S1_INDIRECT_WITH_POST_INCREMENT_1, "add.1-d-indirect-1-s1-indirect-with-post-increment-1", "add.1", 32,
20913 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20914 +  },
20915 +/* add.1 (${d-An})${d-i4-1}++,(${s1-An})${s1-i4-1}++,${s2} */
20916 +  {
20917 +    UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_POST_INCREMENT_1, "add.1-d-indirect-with-post-increment-1-s1-indirect-with-post-increment-1", "add.1", 32,
20918 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20919 +  },
20920 +/* add.1 ${d-i4-1}(${d-An})++,(${s1-An})${s1-i4-1}++,${s2} */
20921 +  {
20922 +    UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_POST_INCREMENT_1, "add.1-d-indirect-with-pre-increment-1-s1-indirect-with-post-increment-1", "add.1", 32,
20923 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20924 +  },
20925 +/* add.1 ${d-direct-addr},${s1-i4-1}(${s1-An})++,${s2} */
20926 +  {
20927 +    UBICOM32_INSN_ADD_1_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_1, "add.1-d-direct-s1-indirect-with-pre-increment-1", "add.1", 32,
20928 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20929 +  },
20930 +/* add.1 #${d-imm8},${s1-i4-1}(${s1-An})++,${s2} */
20931 +  {
20932 +    UBICOM32_INSN_ADD_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, "add.1-d-immediate-1-s1-indirect-with-pre-increment-1", "add.1", 32,
20933 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20934 +  },
20935 +/* add.1 (${d-An},${d-r}),${s1-i4-1}(${s1-An})++,${s2} */
20936 +  {
20937 +    UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, "add.1-d-indirect-with-index-1-s1-indirect-with-pre-increment-1", "add.1", 32,
20938 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20939 +  },
20940 +/* add.1 ${d-imm7-1}(${d-An}),${s1-i4-1}(${s1-An})++,${s2} */
20941 +  {
20942 +    UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, "add.1-d-indirect-with-offset-1-s1-indirect-with-pre-increment-1", "add.1", 32,
20943 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20944 +  },
20945 +/* add.1 (${d-An}),${s1-i4-1}(${s1-An})++,${s2} */
20946 +  {
20947 +    UBICOM32_INSN_ADD_1_D_INDIRECT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, "add.1-d-indirect-1-s1-indirect-with-pre-increment-1", "add.1", 32,
20948 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20949 +  },
20950 +/* add.1 (${d-An})${d-i4-1}++,${s1-i4-1}(${s1-An})++,${s2} */
20951 +  {
20952 +    UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, "add.1-d-indirect-with-post-increment-1-s1-indirect-with-pre-increment-1", "add.1", 32,
20953 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20954 +  },
20955 +/* add.1 ${d-i4-1}(${d-An})++,${s1-i4-1}(${s1-An})++,${s2} */
20956 +  {
20957 +    UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, "add.1-d-indirect-with-pre-increment-1-s1-indirect-with-pre-increment-1", "add.1", 32,
20958 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
20959 +  },
20960 +/* add.4 ${d-direct-addr},${s1-direct-addr},${s2} */
20961 +  {
20962 +    UBICOM32_INSN_ADD_4_D_DIRECT_S1_DIRECT, "add.4-d-direct-s1-direct", "add.4", 32,
20963 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20964 +  },
20965 +/* add.4 #${d-imm8},${s1-direct-addr},${s2} */
20966 +  {
20967 +    UBICOM32_INSN_ADD_4_D_IMMEDIATE_4_S1_DIRECT, "add.4-d-immediate-4-s1-direct", "add.4", 32,
20968 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20969 +  },
20970 +/* add.4 (${d-An},${d-r}),${s1-direct-addr},${s2} */
20971 +  {
20972 +    UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_INDEX_4_S1_DIRECT, "add.4-d-indirect-with-index-4-s1-direct", "add.4", 32,
20973 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20974 +  },
20975 +/* add.4 ${d-imm7-4}(${d-An}),${s1-direct-addr},${s2} */
20976 +  {
20977 +    UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_OFFSET_4_S1_DIRECT, "add.4-d-indirect-with-offset-4-s1-direct", "add.4", 32,
20978 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20979 +  },
20980 +/* add.4 (${d-An}),${s1-direct-addr},${s2} */
20981 +  {
20982 +    UBICOM32_INSN_ADD_4_D_INDIRECT_4_S1_DIRECT, "add.4-d-indirect-4-s1-direct", "add.4", 32,
20983 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20984 +  },
20985 +/* add.4 (${d-An})${d-i4-4}++,${s1-direct-addr},${s2} */
20986 +  {
20987 +    UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_DIRECT, "add.4-d-indirect-with-post-increment-4-s1-direct", "add.4", 32,
20988 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20989 +  },
20990 +/* add.4 ${d-i4-4}(${d-An})++,${s1-direct-addr},${s2} */
20991 +  {
20992 +    UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_DIRECT, "add.4-d-indirect-with-pre-increment-4-s1-direct", "add.4", 32,
20993 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20994 +  },
20995 +/* add.4 ${d-direct-addr},#${s1-imm8},${s2} */
20996 +  {
20997 +    UBICOM32_INSN_ADD_4_D_DIRECT_S1_IMMEDIATE, "add.4-d-direct-s1-immediate", "add.4", 32,
20998 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
20999 +  },
21000 +/* add.4 #${d-imm8},#${s1-imm8},${s2} */
21001 +  {
21002 +    UBICOM32_INSN_ADD_4_D_IMMEDIATE_4_S1_IMMEDIATE, "add.4-d-immediate-4-s1-immediate", "add.4", 32,
21003 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21004 +  },
21005 +/* add.4 (${d-An},${d-r}),#${s1-imm8},${s2} */
21006 +  {
21007 +    UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_INDEX_4_S1_IMMEDIATE, "add.4-d-indirect-with-index-4-s1-immediate", "add.4", 32,
21008 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21009 +  },
21010 +/* add.4 ${d-imm7-4}(${d-An}),#${s1-imm8},${s2} */
21011 +  {
21012 +    UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_OFFSET_4_S1_IMMEDIATE, "add.4-d-indirect-with-offset-4-s1-immediate", "add.4", 32,
21013 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21014 +  },
21015 +/* add.4 (${d-An}),#${s1-imm8},${s2} */
21016 +  {
21017 +    UBICOM32_INSN_ADD_4_D_INDIRECT_4_S1_IMMEDIATE, "add.4-d-indirect-4-s1-immediate", "add.4", 32,
21018 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21019 +  },
21020 +/* add.4 (${d-An})${d-i4-4}++,#${s1-imm8},${s2} */
21021 +  {
21022 +    UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_IMMEDIATE, "add.4-d-indirect-with-post-increment-4-s1-immediate", "add.4", 32,
21023 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21024 +  },
21025 +/* add.4 ${d-i4-4}(${d-An})++,#${s1-imm8},${s2} */
21026 +  {
21027 +    UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_IMMEDIATE, "add.4-d-indirect-with-pre-increment-4-s1-immediate", "add.4", 32,
21028 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21029 +  },
21030 +/* add.4 ${d-direct-addr},(${s1-An},${s1-r}),${s2} */
21031 +  {
21032 +    UBICOM32_INSN_ADD_4_D_DIRECT_S1_INDIRECT_WITH_INDEX_4, "add.4-d-direct-s1-indirect-with-index-4", "add.4", 32,
21033 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21034 +  },
21035 +/* add.4 #${d-imm8},(${s1-An},${s1-r}),${s2} */
21036 +  {
21037 +    UBICOM32_INSN_ADD_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_INDEX_4, "add.4-d-immediate-4-s1-indirect-with-index-4", "add.4", 32,
21038 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21039 +  },
21040 +/* add.4 (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */
21041 +  {
21042 +    UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_INDEX_4, "add.4-d-indirect-with-index-4-s1-indirect-with-index-4", "add.4", 32,
21043 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21044 +  },
21045 +/* add.4 ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}),${s2} */
21046 +  {
21047 +    UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_INDEX_4, "add.4-d-indirect-with-offset-4-s1-indirect-with-index-4", "add.4", 32,
21048 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21049 +  },
21050 +/* add.4 (${d-An}),(${s1-An},${s1-r}),${s2} */
21051 +  {
21052 +    UBICOM32_INSN_ADD_4_D_INDIRECT_4_S1_INDIRECT_WITH_INDEX_4, "add.4-d-indirect-4-s1-indirect-with-index-4", "add.4", 32,
21053 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21054 +  },
21055 +/* add.4 (${d-An})${d-i4-4}++,(${s1-An},${s1-r}),${s2} */
21056 +  {
21057 +    UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, "add.4-d-indirect-with-post-increment-4-s1-indirect-with-index-4", "add.4", 32,
21058 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21059 +  },
21060 +/* add.4 ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}),${s2} */
21061 +  {
21062 +    UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, "add.4-d-indirect-with-pre-increment-4-s1-indirect-with-index-4", "add.4", 32,
21063 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21064 +  },
21065 +/* add.4 ${d-direct-addr},${s1-imm7-4}(${s1-An}),${s2} */
21066 +  {
21067 +    UBICOM32_INSN_ADD_4_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4, "add.4-d-direct-s1-indirect-with-offset-4", "add.4", 32,
21068 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21069 +  },
21070 +/* add.4 #${d-imm8},${s1-imm7-4}(${s1-An}),${s2} */
21071 +  {
21072 +    UBICOM32_INSN_ADD_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_OFFSET_4, "add.4-d-immediate-4-s1-indirect-with-offset-4", "add.4", 32,
21073 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21074 +  },
21075 +/* add.4 (${d-An},${d-r}),${s1-imm7-4}(${s1-An}),${s2} */
21076 +  {
21077 +    UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_OFFSET_4, "add.4-d-indirect-with-index-4-s1-indirect-with-offset-4", "add.4", 32,
21078 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21079 +  },
21080 +/* add.4 ${d-imm7-4}(${d-An}),${s1-imm7-4}(${s1-An}),${s2} */
21081 +  {
21082 +    UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_OFFSET_4, "add.4-d-indirect-with-offset-4-s1-indirect-with-offset-4", "add.4", 32,
21083 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21084 +  },
21085 +/* add.4 (${d-An}),${s1-imm7-4}(${s1-An}),${s2} */
21086 +  {
21087 +    UBICOM32_INSN_ADD_4_D_INDIRECT_4_S1_INDIRECT_WITH_OFFSET_4, "add.4-d-indirect-4-s1-indirect-with-offset-4", "add.4", 32,
21088 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21089 +  },
21090 +/* add.4 (${d-An})${d-i4-4}++,${s1-imm7-4}(${s1-An}),${s2} */
21091 +  {
21092 +    UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, "add.4-d-indirect-with-post-increment-4-s1-indirect-with-offset-4", "add.4", 32,
21093 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21094 +  },
21095 +/* add.4 ${d-i4-4}(${d-An})++,${s1-imm7-4}(${s1-An}),${s2} */
21096 +  {
21097 +    UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, "add.4-d-indirect-with-pre-increment-4-s1-indirect-with-offset-4", "add.4", 32,
21098 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21099 +  },
21100 +/* add.4 ${d-direct-addr},(${s1-An}),${s2} */
21101 +  {
21102 +    UBICOM32_INSN_ADD_4_D_DIRECT_S1_INDIRECT_4, "add.4-d-direct-s1-indirect-4", "add.4", 32,
21103 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21104 +  },
21105 +/* add.4 #${d-imm8},(${s1-An}),${s2} */
21106 +  {
21107 +    UBICOM32_INSN_ADD_4_D_IMMEDIATE_4_S1_INDIRECT_4, "add.4-d-immediate-4-s1-indirect-4", "add.4", 32,
21108 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21109 +  },
21110 +/* add.4 (${d-An},${d-r}),(${s1-An}),${s2} */
21111 +  {
21112 +    UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_4, "add.4-d-indirect-with-index-4-s1-indirect-4", "add.4", 32,
21113 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21114 +  },
21115 +/* add.4 ${d-imm7-4}(${d-An}),(${s1-An}),${s2} */
21116 +  {
21117 +    UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_4, "add.4-d-indirect-with-offset-4-s1-indirect-4", "add.4", 32,
21118 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21119 +  },
21120 +/* add.4 (${d-An}),(${s1-An}),${s2} */
21121 +  {
21122 +    UBICOM32_INSN_ADD_4_D_INDIRECT_4_S1_INDIRECT_4, "add.4-d-indirect-4-s1-indirect-4", "add.4", 32,
21123 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21124 +  },
21125 +/* add.4 (${d-An})${d-i4-4}++,(${s1-An}),${s2} */
21126 +  {
21127 +    UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_4, "add.4-d-indirect-with-post-increment-4-s1-indirect-4", "add.4", 32,
21128 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21129 +  },
21130 +/* add.4 ${d-i4-4}(${d-An})++,(${s1-An}),${s2} */
21131 +  {
21132 +    UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_4, "add.4-d-indirect-with-pre-increment-4-s1-indirect-4", "add.4", 32,
21133 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21134 +  },
21135 +/* add.4 ${d-direct-addr},(${s1-An})${s1-i4-4}++,${s2} */
21136 +  {
21137 +    UBICOM32_INSN_ADD_4_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4, "add.4-d-direct-s1-indirect-with-post-increment-4", "add.4", 32,
21138 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21139 +  },
21140 +/* add.4 #${d-imm8},(${s1-An})${s1-i4-4}++,${s2} */
21141 +  {
21142 +    UBICOM32_INSN_ADD_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "add.4-d-immediate-4-s1-indirect-with-post-increment-4", "add.4", 32,
21143 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21144 +  },
21145 +/* add.4 (${d-An},${d-r}),(${s1-An})${s1-i4-4}++,${s2} */
21146 +  {
21147 +    UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "add.4-d-indirect-with-index-4-s1-indirect-with-post-increment-4", "add.4", 32,
21148 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21149 +  },
21150 +/* add.4 ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-4}++,${s2} */
21151 +  {
21152 +    UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "add.4-d-indirect-with-offset-4-s1-indirect-with-post-increment-4", "add.4", 32,
21153 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21154 +  },
21155 +/* add.4 (${d-An}),(${s1-An})${s1-i4-4}++,${s2} */
21156 +  {
21157 +    UBICOM32_INSN_ADD_4_D_INDIRECT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "add.4-d-indirect-4-s1-indirect-with-post-increment-4", "add.4", 32,
21158 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21159 +  },
21160 +/* add.4 (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-4}++,${s2} */
21161 +  {
21162 +    UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "add.4-d-indirect-with-post-increment-4-s1-indirect-with-post-increment-4", "add.4", 32,
21163 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21164 +  },
21165 +/* add.4 ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-4}++,${s2} */
21166 +  {
21167 +    UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "add.4-d-indirect-with-pre-increment-4-s1-indirect-with-post-increment-4", "add.4", 32,
21168 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21169 +  },
21170 +/* add.4 ${d-direct-addr},${s1-i4-4}(${s1-An})++,${s2} */
21171 +  {
21172 +    UBICOM32_INSN_ADD_4_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4, "add.4-d-direct-s1-indirect-with-pre-increment-4", "add.4", 32,
21173 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21174 +  },
21175 +/* add.4 #${d-imm8},${s1-i4-4}(${s1-An})++,${s2} */
21176 +  {
21177 +    UBICOM32_INSN_ADD_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "add.4-d-immediate-4-s1-indirect-with-pre-increment-4", "add.4", 32,
21178 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21179 +  },
21180 +/* add.4 (${d-An},${d-r}),${s1-i4-4}(${s1-An})++,${s2} */
21181 +  {
21182 +    UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "add.4-d-indirect-with-index-4-s1-indirect-with-pre-increment-4", "add.4", 32,
21183 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21184 +  },
21185 +/* add.4 ${d-imm7-4}(${d-An}),${s1-i4-4}(${s1-An})++,${s2} */
21186 +  {
21187 +    UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "add.4-d-indirect-with-offset-4-s1-indirect-with-pre-increment-4", "add.4", 32,
21188 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21189 +  },
21190 +/* add.4 (${d-An}),${s1-i4-4}(${s1-An})++,${s2} */
21191 +  {
21192 +    UBICOM32_INSN_ADD_4_D_INDIRECT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "add.4-d-indirect-4-s1-indirect-with-pre-increment-4", "add.4", 32,
21193 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21194 +  },
21195 +/* add.4 (${d-An})${d-i4-4}++,${s1-i4-4}(${s1-An})++,${s2} */
21196 +  {
21197 +    UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "add.4-d-indirect-with-post-increment-4-s1-indirect-with-pre-increment-4", "add.4", 32,
21198 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21199 +  },
21200 +/* add.4 ${d-i4-4}(${d-An})++,${s1-i4-4}(${s1-An})++,${s2} */
21201 +  {
21202 +    UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "add.4-d-indirect-with-pre-increment-4-s1-indirect-with-pre-increment-4", "add.4", 32,
21203 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21204 +  },
21205 +/* add.2 ${d-direct-addr},${s1-direct-addr},${s2} */
21206 +  {
21207 +    UBICOM32_INSN_ADD_2_D_DIRECT_S1_DIRECT, "add.2-d-direct-s1-direct", "add.2", 32,
21208 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21209 +  },
21210 +/* add.2 #${d-imm8},${s1-direct-addr},${s2} */
21211 +  {
21212 +    UBICOM32_INSN_ADD_2_D_IMMEDIATE_2_S1_DIRECT, "add.2-d-immediate-2-s1-direct", "add.2", 32,
21213 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21214 +  },
21215 +/* add.2 (${d-An},${d-r}),${s1-direct-addr},${s2} */
21216 +  {
21217 +    UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_INDEX_2_S1_DIRECT, "add.2-d-indirect-with-index-2-s1-direct", "add.2", 32,
21218 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21219 +  },
21220 +/* add.2 ${d-imm7-2}(${d-An}),${s1-direct-addr},${s2} */
21221 +  {
21222 +    UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_OFFSET_2_S1_DIRECT, "add.2-d-indirect-with-offset-2-s1-direct", "add.2", 32,
21223 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21224 +  },
21225 +/* add.2 (${d-An}),${s1-direct-addr},${s2} */
21226 +  {
21227 +    UBICOM32_INSN_ADD_2_D_INDIRECT_2_S1_DIRECT, "add.2-d-indirect-2-s1-direct", "add.2", 32,
21228 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21229 +  },
21230 +/* add.2 (${d-An})${d-i4-2}++,${s1-direct-addr},${s2} */
21231 +  {
21232 +    UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_DIRECT, "add.2-d-indirect-with-post-increment-2-s1-direct", "add.2", 32,
21233 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21234 +  },
21235 +/* add.2 ${d-i4-2}(${d-An})++,${s1-direct-addr},${s2} */
21236 +  {
21237 +    UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_DIRECT, "add.2-d-indirect-with-pre-increment-2-s1-direct", "add.2", 32,
21238 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21239 +  },
21240 +/* add.2 ${d-direct-addr},#${s1-imm8},${s2} */
21241 +  {
21242 +    UBICOM32_INSN_ADD_2_D_DIRECT_S1_IMMEDIATE, "add.2-d-direct-s1-immediate", "add.2", 32,
21243 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21244 +  },
21245 +/* add.2 #${d-imm8},#${s1-imm8},${s2} */
21246 +  {
21247 +    UBICOM32_INSN_ADD_2_D_IMMEDIATE_2_S1_IMMEDIATE, "add.2-d-immediate-2-s1-immediate", "add.2", 32,
21248 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21249 +  },
21250 +/* add.2 (${d-An},${d-r}),#${s1-imm8},${s2} */
21251 +  {
21252 +    UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_INDEX_2_S1_IMMEDIATE, "add.2-d-indirect-with-index-2-s1-immediate", "add.2", 32,
21253 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21254 +  },
21255 +/* add.2 ${d-imm7-2}(${d-An}),#${s1-imm8},${s2} */
21256 +  {
21257 +    UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_OFFSET_2_S1_IMMEDIATE, "add.2-d-indirect-with-offset-2-s1-immediate", "add.2", 32,
21258 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21259 +  },
21260 +/* add.2 (${d-An}),#${s1-imm8},${s2} */
21261 +  {
21262 +    UBICOM32_INSN_ADD_2_D_INDIRECT_2_S1_IMMEDIATE, "add.2-d-indirect-2-s1-immediate", "add.2", 32,
21263 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21264 +  },
21265 +/* add.2 (${d-An})${d-i4-2}++,#${s1-imm8},${s2} */
21266 +  {
21267 +    UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_IMMEDIATE, "add.2-d-indirect-with-post-increment-2-s1-immediate", "add.2", 32,
21268 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21269 +  },
21270 +/* add.2 ${d-i4-2}(${d-An})++,#${s1-imm8},${s2} */
21271 +  {
21272 +    UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_IMMEDIATE, "add.2-d-indirect-with-pre-increment-2-s1-immediate", "add.2", 32,
21273 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21274 +  },
21275 +/* add.2 ${d-direct-addr},(${s1-An},${s1-r}),${s2} */
21276 +  {
21277 +    UBICOM32_INSN_ADD_2_D_DIRECT_S1_INDIRECT_WITH_INDEX_2, "add.2-d-direct-s1-indirect-with-index-2", "add.2", 32,
21278 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21279 +  },
21280 +/* add.2 #${d-imm8},(${s1-An},${s1-r}),${s2} */
21281 +  {
21282 +    UBICOM32_INSN_ADD_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_INDEX_2, "add.2-d-immediate-2-s1-indirect-with-index-2", "add.2", 32,
21283 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21284 +  },
21285 +/* add.2 (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */
21286 +  {
21287 +    UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_INDEX_2, "add.2-d-indirect-with-index-2-s1-indirect-with-index-2", "add.2", 32,
21288 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21289 +  },
21290 +/* add.2 ${d-imm7-2}(${d-An}),(${s1-An},${s1-r}),${s2} */
21291 +  {
21292 +    UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_INDEX_2, "add.2-d-indirect-with-offset-2-s1-indirect-with-index-2", "add.2", 32,
21293 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21294 +  },
21295 +/* add.2 (${d-An}),(${s1-An},${s1-r}),${s2} */
21296 +  {
21297 +    UBICOM32_INSN_ADD_2_D_INDIRECT_2_S1_INDIRECT_WITH_INDEX_2, "add.2-d-indirect-2-s1-indirect-with-index-2", "add.2", 32,
21298 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21299 +  },
21300 +/* add.2 (${d-An})${d-i4-2}++,(${s1-An},${s1-r}),${s2} */
21301 +  {
21302 +    UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_INDEX_2, "add.2-d-indirect-with-post-increment-2-s1-indirect-with-index-2", "add.2", 32,
21303 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21304 +  },
21305 +/* add.2 ${d-i4-2}(${d-An})++,(${s1-An},${s1-r}),${s2} */
21306 +  {
21307 +    UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_INDEX_2, "add.2-d-indirect-with-pre-increment-2-s1-indirect-with-index-2", "add.2", 32,
21308 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21309 +  },
21310 +/* add.2 ${d-direct-addr},${s1-imm7-2}(${s1-An}),${s2} */
21311 +  {
21312 +    UBICOM32_INSN_ADD_2_D_DIRECT_S1_INDIRECT_WITH_OFFSET_2, "add.2-d-direct-s1-indirect-with-offset-2", "add.2", 32,
21313 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21314 +  },
21315 +/* add.2 #${d-imm8},${s1-imm7-2}(${s1-An}),${s2} */
21316 +  {
21317 +    UBICOM32_INSN_ADD_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_OFFSET_2, "add.2-d-immediate-2-s1-indirect-with-offset-2", "add.2", 32,
21318 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21319 +  },
21320 +/* add.2 (${d-An},${d-r}),${s1-imm7-2}(${s1-An}),${s2} */
21321 +  {
21322 +    UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_OFFSET_2, "add.2-d-indirect-with-index-2-s1-indirect-with-offset-2", "add.2", 32,
21323 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21324 +  },
21325 +/* add.2 ${d-imm7-2}(${d-An}),${s1-imm7-2}(${s1-An}),${s2} */
21326 +  {
21327 +    UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_OFFSET_2, "add.2-d-indirect-with-offset-2-s1-indirect-with-offset-2", "add.2", 32,
21328 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21329 +  },
21330 +/* add.2 (${d-An}),${s1-imm7-2}(${s1-An}),${s2} */
21331 +  {
21332 +    UBICOM32_INSN_ADD_2_D_INDIRECT_2_S1_INDIRECT_WITH_OFFSET_2, "add.2-d-indirect-2-s1-indirect-with-offset-2", "add.2", 32,
21333 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21334 +  },
21335 +/* add.2 (${d-An})${d-i4-2}++,${s1-imm7-2}(${s1-An}),${s2} */
21336 +  {
21337 +    UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_2, "add.2-d-indirect-with-post-increment-2-s1-indirect-with-offset-2", "add.2", 32,
21338 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21339 +  },
21340 +/* add.2 ${d-i4-2}(${d-An})++,${s1-imm7-2}(${s1-An}),${s2} */
21341 +  {
21342 +    UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_2, "add.2-d-indirect-with-pre-increment-2-s1-indirect-with-offset-2", "add.2", 32,
21343 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21344 +  },
21345 +/* add.2 ${d-direct-addr},(${s1-An}),${s2} */
21346 +  {
21347 +    UBICOM32_INSN_ADD_2_D_DIRECT_S1_INDIRECT_2, "add.2-d-direct-s1-indirect-2", "add.2", 32,
21348 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21349 +  },
21350 +/* add.2 #${d-imm8},(${s1-An}),${s2} */
21351 +  {
21352 +    UBICOM32_INSN_ADD_2_D_IMMEDIATE_2_S1_INDIRECT_2, "add.2-d-immediate-2-s1-indirect-2", "add.2", 32,
21353 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21354 +  },
21355 +/* add.2 (${d-An},${d-r}),(${s1-An}),${s2} */
21356 +  {
21357 +    UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_2, "add.2-d-indirect-with-index-2-s1-indirect-2", "add.2", 32,
21358 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21359 +  },
21360 +/* add.2 ${d-imm7-2}(${d-An}),(${s1-An}),${s2} */
21361 +  {
21362 +    UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_2, "add.2-d-indirect-with-offset-2-s1-indirect-2", "add.2", 32,
21363 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21364 +  },
21365 +/* add.2 (${d-An}),(${s1-An}),${s2} */
21366 +  {
21367 +    UBICOM32_INSN_ADD_2_D_INDIRECT_2_S1_INDIRECT_2, "add.2-d-indirect-2-s1-indirect-2", "add.2", 32,
21368 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21369 +  },
21370 +/* add.2 (${d-An})${d-i4-2}++,(${s1-An}),${s2} */
21371 +  {
21372 +    UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_2, "add.2-d-indirect-with-post-increment-2-s1-indirect-2", "add.2", 32,
21373 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21374 +  },
21375 +/* add.2 ${d-i4-2}(${d-An})++,(${s1-An}),${s2} */
21376 +  {
21377 +    UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_2, "add.2-d-indirect-with-pre-increment-2-s1-indirect-2", "add.2", 32,
21378 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21379 +  },
21380 +/* add.2 ${d-direct-addr},(${s1-An})${s1-i4-2}++,${s2} */
21381 +  {
21382 +    UBICOM32_INSN_ADD_2_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_2, "add.2-d-direct-s1-indirect-with-post-increment-2", "add.2", 32,
21383 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21384 +  },
21385 +/* add.2 #${d-imm8},(${s1-An})${s1-i4-2}++,${s2} */
21386 +  {
21387 +    UBICOM32_INSN_ADD_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_POST_INCREMENT_2, "add.2-d-immediate-2-s1-indirect-with-post-increment-2", "add.2", 32,
21388 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21389 +  },
21390 +/* add.2 (${d-An},${d-r}),(${s1-An})${s1-i4-2}++,${s2} */
21391 +  {
21392 +    UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_POST_INCREMENT_2, "add.2-d-indirect-with-index-2-s1-indirect-with-post-increment-2", "add.2", 32,
21393 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21394 +  },
21395 +/* add.2 ${d-imm7-2}(${d-An}),(${s1-An})${s1-i4-2}++,${s2} */
21396 +  {
21397 +    UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_POST_INCREMENT_2, "add.2-d-indirect-with-offset-2-s1-indirect-with-post-increment-2", "add.2", 32,
21398 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21399 +  },
21400 +/* add.2 (${d-An}),(${s1-An})${s1-i4-2}++,${s2} */
21401 +  {
21402 +    UBICOM32_INSN_ADD_2_D_INDIRECT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, "add.2-d-indirect-2-s1-indirect-with-post-increment-2", "add.2", 32,
21403 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21404 +  },
21405 +/* add.2 (${d-An})${d-i4-2}++,(${s1-An})${s1-i4-2}++,${s2} */
21406 +  {
21407 +    UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, "add.2-d-indirect-with-post-increment-2-s1-indirect-with-post-increment-2", "add.2", 32,
21408 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21409 +  },
21410 +/* add.2 ${d-i4-2}(${d-An})++,(${s1-An})${s1-i4-2}++,${s2} */
21411 +  {
21412 +    UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, "add.2-d-indirect-with-pre-increment-2-s1-indirect-with-post-increment-2", "add.2", 32,
21413 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21414 +  },
21415 +/* add.2 ${d-direct-addr},${s1-i4-2}(${s1-An})++,${s2} */
21416 +  {
21417 +    UBICOM32_INSN_ADD_2_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_2, "add.2-d-direct-s1-indirect-with-pre-increment-2", "add.2", 32,
21418 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21419 +  },
21420 +/* add.2 #${d-imm8},${s1-i4-2}(${s1-An})++,${s2} */
21421 +  {
21422 +    UBICOM32_INSN_ADD_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, "add.2-d-immediate-2-s1-indirect-with-pre-increment-2", "add.2", 32,
21423 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21424 +  },
21425 +/* add.2 (${d-An},${d-r}),${s1-i4-2}(${s1-An})++,${s2} */
21426 +  {
21427 +    UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, "add.2-d-indirect-with-index-2-s1-indirect-with-pre-increment-2", "add.2", 32,
21428 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21429 +  },
21430 +/* add.2 ${d-imm7-2}(${d-An}),${s1-i4-2}(${s1-An})++,${s2} */
21431 +  {
21432 +    UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, "add.2-d-indirect-with-offset-2-s1-indirect-with-pre-increment-2", "add.2", 32,
21433 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21434 +  },
21435 +/* add.2 (${d-An}),${s1-i4-2}(${s1-An})++,${s2} */
21436 +  {
21437 +    UBICOM32_INSN_ADD_2_D_INDIRECT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, "add.2-d-indirect-2-s1-indirect-with-pre-increment-2", "add.2", 32,
21438 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21439 +  },
21440 +/* add.2 (${d-An})${d-i4-2}++,${s1-i4-2}(${s1-An})++,${s2} */
21441 +  {
21442 +    UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, "add.2-d-indirect-with-post-increment-2-s1-indirect-with-pre-increment-2", "add.2", 32,
21443 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21444 +  },
21445 +/* add.2 ${d-i4-2}(${d-An})++,${s1-i4-2}(${s1-An})++,${s2} */
21446 +  {
21447 +    UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, "add.2-d-indirect-with-pre-increment-2-s1-indirect-with-pre-increment-2", "add.2", 32,
21448 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21449 +  },
21450 +/* not.4 ${d-direct-addr},${s1-direct-addr} */
21451 +  {
21452 +    UBICOM32_INSN_NOT_4_D_DIRECT_S1_DIRECT, "not.4-d-direct-s1-direct", "not.4", 32,
21453 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21454 +  },
21455 +/* not.4 #${d-imm8},${s1-direct-addr} */
21456 +  {
21457 +    UBICOM32_INSN_NOT_4_D_IMMEDIATE_4_S1_DIRECT, "not.4-d-immediate-4-s1-direct", "not.4", 32,
21458 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21459 +  },
21460 +/* not.4 (${d-An},${d-r}),${s1-direct-addr} */
21461 +  {
21462 +    UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_INDEX_4_S1_DIRECT, "not.4-d-indirect-with-index-4-s1-direct", "not.4", 32,
21463 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21464 +  },
21465 +/* not.4 ${d-imm7-4}(${d-An}),${s1-direct-addr} */
21466 +  {
21467 +    UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_OFFSET_4_S1_DIRECT, "not.4-d-indirect-with-offset-4-s1-direct", "not.4", 32,
21468 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21469 +  },
21470 +/* not.4 (${d-An}),${s1-direct-addr} */
21471 +  {
21472 +    UBICOM32_INSN_NOT_4_D_INDIRECT_4_S1_DIRECT, "not.4-d-indirect-4-s1-direct", "not.4", 32,
21473 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21474 +  },
21475 +/* not.4 (${d-An})${d-i4-4}++,${s1-direct-addr} */
21476 +  {
21477 +    UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_DIRECT, "not.4-d-indirect-with-post-increment-4-s1-direct", "not.4", 32,
21478 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21479 +  },
21480 +/* not.4 ${d-i4-4}(${d-An})++,${s1-direct-addr} */
21481 +  {
21482 +    UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_DIRECT, "not.4-d-indirect-with-pre-increment-4-s1-direct", "not.4", 32,
21483 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21484 +  },
21485 +/* not.4 ${d-direct-addr},#${s1-imm8} */
21486 +  {
21487 +    UBICOM32_INSN_NOT_4_D_DIRECT_S1_IMMEDIATE, "not.4-d-direct-s1-immediate", "not.4", 32,
21488 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21489 +  },
21490 +/* not.4 #${d-imm8},#${s1-imm8} */
21491 +  {
21492 +    UBICOM32_INSN_NOT_4_D_IMMEDIATE_4_S1_IMMEDIATE, "not.4-d-immediate-4-s1-immediate", "not.4", 32,
21493 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21494 +  },
21495 +/* not.4 (${d-An},${d-r}),#${s1-imm8} */
21496 +  {
21497 +    UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_INDEX_4_S1_IMMEDIATE, "not.4-d-indirect-with-index-4-s1-immediate", "not.4", 32,
21498 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21499 +  },
21500 +/* not.4 ${d-imm7-4}(${d-An}),#${s1-imm8} */
21501 +  {
21502 +    UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_OFFSET_4_S1_IMMEDIATE, "not.4-d-indirect-with-offset-4-s1-immediate", "not.4", 32,
21503 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21504 +  },
21505 +/* not.4 (${d-An}),#${s1-imm8} */
21506 +  {
21507 +    UBICOM32_INSN_NOT_4_D_INDIRECT_4_S1_IMMEDIATE, "not.4-d-indirect-4-s1-immediate", "not.4", 32,
21508 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21509 +  },
21510 +/* not.4 (${d-An})${d-i4-4}++,#${s1-imm8} */
21511 +  {
21512 +    UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_IMMEDIATE, "not.4-d-indirect-with-post-increment-4-s1-immediate", "not.4", 32,
21513 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21514 +  },
21515 +/* not.4 ${d-i4-4}(${d-An})++,#${s1-imm8} */
21516 +  {
21517 +    UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_IMMEDIATE, "not.4-d-indirect-with-pre-increment-4-s1-immediate", "not.4", 32,
21518 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21519 +  },
21520 +/* not.4 ${d-direct-addr},(${s1-An},${s1-r}) */
21521 +  {
21522 +    UBICOM32_INSN_NOT_4_D_DIRECT_S1_INDIRECT_WITH_INDEX_4, "not.4-d-direct-s1-indirect-with-index-4", "not.4", 32,
21523 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21524 +  },
21525 +/* not.4 #${d-imm8},(${s1-An},${s1-r}) */
21526 +  {
21527 +    UBICOM32_INSN_NOT_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_INDEX_4, "not.4-d-immediate-4-s1-indirect-with-index-4", "not.4", 32,
21528 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21529 +  },
21530 +/* not.4 (${d-An},${d-r}),(${s1-An},${s1-r}) */
21531 +  {
21532 +    UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_INDEX_4, "not.4-d-indirect-with-index-4-s1-indirect-with-index-4", "not.4", 32,
21533 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21534 +  },
21535 +/* not.4 ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}) */
21536 +  {
21537 +    UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_INDEX_4, "not.4-d-indirect-with-offset-4-s1-indirect-with-index-4", "not.4", 32,
21538 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21539 +  },
21540 +/* not.4 (${d-An}),(${s1-An},${s1-r}) */
21541 +  {
21542 +    UBICOM32_INSN_NOT_4_D_INDIRECT_4_S1_INDIRECT_WITH_INDEX_4, "not.4-d-indirect-4-s1-indirect-with-index-4", "not.4", 32,
21543 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21544 +  },
21545 +/* not.4 (${d-An})${d-i4-4}++,(${s1-An},${s1-r}) */
21546 +  {
21547 +    UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, "not.4-d-indirect-with-post-increment-4-s1-indirect-with-index-4", "not.4", 32,
21548 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21549 +  },
21550 +/* not.4 ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}) */
21551 +  {
21552 +    UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, "not.4-d-indirect-with-pre-increment-4-s1-indirect-with-index-4", "not.4", 32,
21553 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21554 +  },
21555 +/* not.4 ${d-direct-addr},${s1-imm7-4}(${s1-An}) */
21556 +  {
21557 +    UBICOM32_INSN_NOT_4_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4, "not.4-d-direct-s1-indirect-with-offset-4", "not.4", 32,
21558 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21559 +  },
21560 +/* not.4 #${d-imm8},${s1-imm7-4}(${s1-An}) */
21561 +  {
21562 +    UBICOM32_INSN_NOT_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_OFFSET_4, "not.4-d-immediate-4-s1-indirect-with-offset-4", "not.4", 32,
21563 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21564 +  },
21565 +/* not.4 (${d-An},${d-r}),${s1-imm7-4}(${s1-An}) */
21566 +  {
21567 +    UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_OFFSET_4, "not.4-d-indirect-with-index-4-s1-indirect-with-offset-4", "not.4", 32,
21568 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21569 +  },
21570 +/* not.4 ${d-imm7-4}(${d-An}),${s1-imm7-4}(${s1-An}) */
21571 +  {
21572 +    UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_OFFSET_4, "not.4-d-indirect-with-offset-4-s1-indirect-with-offset-4", "not.4", 32,
21573 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21574 +  },
21575 +/* not.4 (${d-An}),${s1-imm7-4}(${s1-An}) */
21576 +  {
21577 +    UBICOM32_INSN_NOT_4_D_INDIRECT_4_S1_INDIRECT_WITH_OFFSET_4, "not.4-d-indirect-4-s1-indirect-with-offset-4", "not.4", 32,
21578 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21579 +  },
21580 +/* not.4 (${d-An})${d-i4-4}++,${s1-imm7-4}(${s1-An}) */
21581 +  {
21582 +    UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, "not.4-d-indirect-with-post-increment-4-s1-indirect-with-offset-4", "not.4", 32,
21583 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21584 +  },
21585 +/* not.4 ${d-i4-4}(${d-An})++,${s1-imm7-4}(${s1-An}) */
21586 +  {
21587 +    UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, "not.4-d-indirect-with-pre-increment-4-s1-indirect-with-offset-4", "not.4", 32,
21588 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21589 +  },
21590 +/* not.4 ${d-direct-addr},(${s1-An}) */
21591 +  {
21592 +    UBICOM32_INSN_NOT_4_D_DIRECT_S1_INDIRECT_4, "not.4-d-direct-s1-indirect-4", "not.4", 32,
21593 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21594 +  },
21595 +/* not.4 #${d-imm8},(${s1-An}) */
21596 +  {
21597 +    UBICOM32_INSN_NOT_4_D_IMMEDIATE_4_S1_INDIRECT_4, "not.4-d-immediate-4-s1-indirect-4", "not.4", 32,
21598 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21599 +  },
21600 +/* not.4 (${d-An},${d-r}),(${s1-An}) */
21601 +  {
21602 +    UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_4, "not.4-d-indirect-with-index-4-s1-indirect-4", "not.4", 32,
21603 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21604 +  },
21605 +/* not.4 ${d-imm7-4}(${d-An}),(${s1-An}) */
21606 +  {
21607 +    UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_4, "not.4-d-indirect-with-offset-4-s1-indirect-4", "not.4", 32,
21608 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21609 +  },
21610 +/* not.4 (${d-An}),(${s1-An}) */
21611 +  {
21612 +    UBICOM32_INSN_NOT_4_D_INDIRECT_4_S1_INDIRECT_4, "not.4-d-indirect-4-s1-indirect-4", "not.4", 32,
21613 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21614 +  },
21615 +/* not.4 (${d-An})${d-i4-4}++,(${s1-An}) */
21616 +  {
21617 +    UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_4, "not.4-d-indirect-with-post-increment-4-s1-indirect-4", "not.4", 32,
21618 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21619 +  },
21620 +/* not.4 ${d-i4-4}(${d-An})++,(${s1-An}) */
21621 +  {
21622 +    UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_4, "not.4-d-indirect-with-pre-increment-4-s1-indirect-4", "not.4", 32,
21623 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21624 +  },
21625 +/* not.4 ${d-direct-addr},(${s1-An})${s1-i4-4}++ */
21626 +  {
21627 +    UBICOM32_INSN_NOT_4_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4, "not.4-d-direct-s1-indirect-with-post-increment-4", "not.4", 32,
21628 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21629 +  },
21630 +/* not.4 #${d-imm8},(${s1-An})${s1-i4-4}++ */
21631 +  {
21632 +    UBICOM32_INSN_NOT_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "not.4-d-immediate-4-s1-indirect-with-post-increment-4", "not.4", 32,
21633 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21634 +  },
21635 +/* not.4 (${d-An},${d-r}),(${s1-An})${s1-i4-4}++ */
21636 +  {
21637 +    UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "not.4-d-indirect-with-index-4-s1-indirect-with-post-increment-4", "not.4", 32,
21638 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21639 +  },
21640 +/* not.4 ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-4}++ */
21641 +  {
21642 +    UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "not.4-d-indirect-with-offset-4-s1-indirect-with-post-increment-4", "not.4", 32,
21643 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21644 +  },
21645 +/* not.4 (${d-An}),(${s1-An})${s1-i4-4}++ */
21646 +  {
21647 +    UBICOM32_INSN_NOT_4_D_INDIRECT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "not.4-d-indirect-4-s1-indirect-with-post-increment-4", "not.4", 32,
21648 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21649 +  },
21650 +/* not.4 (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-4}++ */
21651 +  {
21652 +    UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "not.4-d-indirect-with-post-increment-4-s1-indirect-with-post-increment-4", "not.4", 32,
21653 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21654 +  },
21655 +/* not.4 ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-4}++ */
21656 +  {
21657 +    UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "not.4-d-indirect-with-pre-increment-4-s1-indirect-with-post-increment-4", "not.4", 32,
21658 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21659 +  },
21660 +/* not.4 ${d-direct-addr},${s1-i4-4}(${s1-An})++ */
21661 +  {
21662 +    UBICOM32_INSN_NOT_4_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4, "not.4-d-direct-s1-indirect-with-pre-increment-4", "not.4", 32,
21663 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21664 +  },
21665 +/* not.4 #${d-imm8},${s1-i4-4}(${s1-An})++ */
21666 +  {
21667 +    UBICOM32_INSN_NOT_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "not.4-d-immediate-4-s1-indirect-with-pre-increment-4", "not.4", 32,
21668 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21669 +  },
21670 +/* not.4 (${d-An},${d-r}),${s1-i4-4}(${s1-An})++ */
21671 +  {
21672 +    UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "not.4-d-indirect-with-index-4-s1-indirect-with-pre-increment-4", "not.4", 32,
21673 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21674 +  },
21675 +/* not.4 ${d-imm7-4}(${d-An}),${s1-i4-4}(${s1-An})++ */
21676 +  {
21677 +    UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "not.4-d-indirect-with-offset-4-s1-indirect-with-pre-increment-4", "not.4", 32,
21678 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21679 +  },
21680 +/* not.4 (${d-An}),${s1-i4-4}(${s1-An})++ */
21681 +  {
21682 +    UBICOM32_INSN_NOT_4_D_INDIRECT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "not.4-d-indirect-4-s1-indirect-with-pre-increment-4", "not.4", 32,
21683 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21684 +  },
21685 +/* not.4 (${d-An})${d-i4-4}++,${s1-i4-4}(${s1-An})++ */
21686 +  {
21687 +    UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "not.4-d-indirect-with-post-increment-4-s1-indirect-with-pre-increment-4", "not.4", 32,
21688 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21689 +  },
21690 +/* not.4 ${d-i4-4}(${d-An})++,${s1-i4-4}(${s1-An})++ */
21691 +  {
21692 +    UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "not.4-d-indirect-with-pre-increment-4-s1-indirect-with-pre-increment-4", "not.4", 32,
21693 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21694 +  },
21695 +/* not.2 ${d-direct-addr},${s1-direct-addr} */
21696 +  {
21697 +    UBICOM32_INSN_NOT_2_D_DIRECT_S1_DIRECT, "not.2-d-direct-s1-direct", "not.2", 32,
21698 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21699 +  },
21700 +/* not.2 #${d-imm8},${s1-direct-addr} */
21701 +  {
21702 +    UBICOM32_INSN_NOT_2_D_IMMEDIATE_2_S1_DIRECT, "not.2-d-immediate-2-s1-direct", "not.2", 32,
21703 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21704 +  },
21705 +/* not.2 (${d-An},${d-r}),${s1-direct-addr} */
21706 +  {
21707 +    UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_INDEX_2_S1_DIRECT, "not.2-d-indirect-with-index-2-s1-direct", "not.2", 32,
21708 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21709 +  },
21710 +/* not.2 ${d-imm7-2}(${d-An}),${s1-direct-addr} */
21711 +  {
21712 +    UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_OFFSET_2_S1_DIRECT, "not.2-d-indirect-with-offset-2-s1-direct", "not.2", 32,
21713 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21714 +  },
21715 +/* not.2 (${d-An}),${s1-direct-addr} */
21716 +  {
21717 +    UBICOM32_INSN_NOT_2_D_INDIRECT_2_S1_DIRECT, "not.2-d-indirect-2-s1-direct", "not.2", 32,
21718 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21719 +  },
21720 +/* not.2 (${d-An})${d-i4-2}++,${s1-direct-addr} */
21721 +  {
21722 +    UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_DIRECT, "not.2-d-indirect-with-post-increment-2-s1-direct", "not.2", 32,
21723 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21724 +  },
21725 +/* not.2 ${d-i4-2}(${d-An})++,${s1-direct-addr} */
21726 +  {
21727 +    UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_DIRECT, "not.2-d-indirect-with-pre-increment-2-s1-direct", "not.2", 32,
21728 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21729 +  },
21730 +/* not.2 ${d-direct-addr},#${s1-imm8} */
21731 +  {
21732 +    UBICOM32_INSN_NOT_2_D_DIRECT_S1_IMMEDIATE, "not.2-d-direct-s1-immediate", "not.2", 32,
21733 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21734 +  },
21735 +/* not.2 #${d-imm8},#${s1-imm8} */
21736 +  {
21737 +    UBICOM32_INSN_NOT_2_D_IMMEDIATE_2_S1_IMMEDIATE, "not.2-d-immediate-2-s1-immediate", "not.2", 32,
21738 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21739 +  },
21740 +/* not.2 (${d-An},${d-r}),#${s1-imm8} */
21741 +  {
21742 +    UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_INDEX_2_S1_IMMEDIATE, "not.2-d-indirect-with-index-2-s1-immediate", "not.2", 32,
21743 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21744 +  },
21745 +/* not.2 ${d-imm7-2}(${d-An}),#${s1-imm8} */
21746 +  {
21747 +    UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_OFFSET_2_S1_IMMEDIATE, "not.2-d-indirect-with-offset-2-s1-immediate", "not.2", 32,
21748 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21749 +  },
21750 +/* not.2 (${d-An}),#${s1-imm8} */
21751 +  {
21752 +    UBICOM32_INSN_NOT_2_D_INDIRECT_2_S1_IMMEDIATE, "not.2-d-indirect-2-s1-immediate", "not.2", 32,
21753 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21754 +  },
21755 +/* not.2 (${d-An})${d-i4-2}++,#${s1-imm8} */
21756 +  {
21757 +    UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_IMMEDIATE, "not.2-d-indirect-with-post-increment-2-s1-immediate", "not.2", 32,
21758 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21759 +  },
21760 +/* not.2 ${d-i4-2}(${d-An})++,#${s1-imm8} */
21761 +  {
21762 +    UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_IMMEDIATE, "not.2-d-indirect-with-pre-increment-2-s1-immediate", "not.2", 32,
21763 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21764 +  },
21765 +/* not.2 ${d-direct-addr},(${s1-An},${s1-r}) */
21766 +  {
21767 +    UBICOM32_INSN_NOT_2_D_DIRECT_S1_INDIRECT_WITH_INDEX_2, "not.2-d-direct-s1-indirect-with-index-2", "not.2", 32,
21768 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21769 +  },
21770 +/* not.2 #${d-imm8},(${s1-An},${s1-r}) */
21771 +  {
21772 +    UBICOM32_INSN_NOT_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_INDEX_2, "not.2-d-immediate-2-s1-indirect-with-index-2", "not.2", 32,
21773 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21774 +  },
21775 +/* not.2 (${d-An},${d-r}),(${s1-An},${s1-r}) */
21776 +  {
21777 +    UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_INDEX_2, "not.2-d-indirect-with-index-2-s1-indirect-with-index-2", "not.2", 32,
21778 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21779 +  },
21780 +/* not.2 ${d-imm7-2}(${d-An}),(${s1-An},${s1-r}) */
21781 +  {
21782 +    UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_INDEX_2, "not.2-d-indirect-with-offset-2-s1-indirect-with-index-2", "not.2", 32,
21783 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21784 +  },
21785 +/* not.2 (${d-An}),(${s1-An},${s1-r}) */
21786 +  {
21787 +    UBICOM32_INSN_NOT_2_D_INDIRECT_2_S1_INDIRECT_WITH_INDEX_2, "not.2-d-indirect-2-s1-indirect-with-index-2", "not.2", 32,
21788 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21789 +  },
21790 +/* not.2 (${d-An})${d-i4-2}++,(${s1-An},${s1-r}) */
21791 +  {
21792 +    UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_INDEX_2, "not.2-d-indirect-with-post-increment-2-s1-indirect-with-index-2", "not.2", 32,
21793 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21794 +  },
21795 +/* not.2 ${d-i4-2}(${d-An})++,(${s1-An},${s1-r}) */
21796 +  {
21797 +    UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_INDEX_2, "not.2-d-indirect-with-pre-increment-2-s1-indirect-with-index-2", "not.2", 32,
21798 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21799 +  },
21800 +/* not.2 ${d-direct-addr},${s1-imm7-2}(${s1-An}) */
21801 +  {
21802 +    UBICOM32_INSN_NOT_2_D_DIRECT_S1_INDIRECT_WITH_OFFSET_2, "not.2-d-direct-s1-indirect-with-offset-2", "not.2", 32,
21803 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21804 +  },
21805 +/* not.2 #${d-imm8},${s1-imm7-2}(${s1-An}) */
21806 +  {
21807 +    UBICOM32_INSN_NOT_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_OFFSET_2, "not.2-d-immediate-2-s1-indirect-with-offset-2", "not.2", 32,
21808 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21809 +  },
21810 +/* not.2 (${d-An},${d-r}),${s1-imm7-2}(${s1-An}) */
21811 +  {
21812 +    UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_OFFSET_2, "not.2-d-indirect-with-index-2-s1-indirect-with-offset-2", "not.2", 32,
21813 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21814 +  },
21815 +/* not.2 ${d-imm7-2}(${d-An}),${s1-imm7-2}(${s1-An}) */
21816 +  {
21817 +    UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_OFFSET_2, "not.2-d-indirect-with-offset-2-s1-indirect-with-offset-2", "not.2", 32,
21818 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21819 +  },
21820 +/* not.2 (${d-An}),${s1-imm7-2}(${s1-An}) */
21821 +  {
21822 +    UBICOM32_INSN_NOT_2_D_INDIRECT_2_S1_INDIRECT_WITH_OFFSET_2, "not.2-d-indirect-2-s1-indirect-with-offset-2", "not.2", 32,
21823 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21824 +  },
21825 +/* not.2 (${d-An})${d-i4-2}++,${s1-imm7-2}(${s1-An}) */
21826 +  {
21827 +    UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_2, "not.2-d-indirect-with-post-increment-2-s1-indirect-with-offset-2", "not.2", 32,
21828 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21829 +  },
21830 +/* not.2 ${d-i4-2}(${d-An})++,${s1-imm7-2}(${s1-An}) */
21831 +  {
21832 +    UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_2, "not.2-d-indirect-with-pre-increment-2-s1-indirect-with-offset-2", "not.2", 32,
21833 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21834 +  },
21835 +/* not.2 ${d-direct-addr},(${s1-An}) */
21836 +  {
21837 +    UBICOM32_INSN_NOT_2_D_DIRECT_S1_INDIRECT_2, "not.2-d-direct-s1-indirect-2", "not.2", 32,
21838 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21839 +  },
21840 +/* not.2 #${d-imm8},(${s1-An}) */
21841 +  {
21842 +    UBICOM32_INSN_NOT_2_D_IMMEDIATE_2_S1_INDIRECT_2, "not.2-d-immediate-2-s1-indirect-2", "not.2", 32,
21843 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21844 +  },
21845 +/* not.2 (${d-An},${d-r}),(${s1-An}) */
21846 +  {
21847 +    UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_2, "not.2-d-indirect-with-index-2-s1-indirect-2", "not.2", 32,
21848 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21849 +  },
21850 +/* not.2 ${d-imm7-2}(${d-An}),(${s1-An}) */
21851 +  {
21852 +    UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_2, "not.2-d-indirect-with-offset-2-s1-indirect-2", "not.2", 32,
21853 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21854 +  },
21855 +/* not.2 (${d-An}),(${s1-An}) */
21856 +  {
21857 +    UBICOM32_INSN_NOT_2_D_INDIRECT_2_S1_INDIRECT_2, "not.2-d-indirect-2-s1-indirect-2", "not.2", 32,
21858 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21859 +  },
21860 +/* not.2 (${d-An})${d-i4-2}++,(${s1-An}) */
21861 +  {
21862 +    UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_2, "not.2-d-indirect-with-post-increment-2-s1-indirect-2", "not.2", 32,
21863 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21864 +  },
21865 +/* not.2 ${d-i4-2}(${d-An})++,(${s1-An}) */
21866 +  {
21867 +    UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_2, "not.2-d-indirect-with-pre-increment-2-s1-indirect-2", "not.2", 32,
21868 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21869 +  },
21870 +/* not.2 ${d-direct-addr},(${s1-An})${s1-i4-2}++ */
21871 +  {
21872 +    UBICOM32_INSN_NOT_2_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_2, "not.2-d-direct-s1-indirect-with-post-increment-2", "not.2", 32,
21873 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21874 +  },
21875 +/* not.2 #${d-imm8},(${s1-An})${s1-i4-2}++ */
21876 +  {
21877 +    UBICOM32_INSN_NOT_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_POST_INCREMENT_2, "not.2-d-immediate-2-s1-indirect-with-post-increment-2", "not.2", 32,
21878 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21879 +  },
21880 +/* not.2 (${d-An},${d-r}),(${s1-An})${s1-i4-2}++ */
21881 +  {
21882 +    UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_POST_INCREMENT_2, "not.2-d-indirect-with-index-2-s1-indirect-with-post-increment-2", "not.2", 32,
21883 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21884 +  },
21885 +/* not.2 ${d-imm7-2}(${d-An}),(${s1-An})${s1-i4-2}++ */
21886 +  {
21887 +    UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_POST_INCREMENT_2, "not.2-d-indirect-with-offset-2-s1-indirect-with-post-increment-2", "not.2", 32,
21888 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21889 +  },
21890 +/* not.2 (${d-An}),(${s1-An})${s1-i4-2}++ */
21891 +  {
21892 +    UBICOM32_INSN_NOT_2_D_INDIRECT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, "not.2-d-indirect-2-s1-indirect-with-post-increment-2", "not.2", 32,
21893 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21894 +  },
21895 +/* not.2 (${d-An})${d-i4-2}++,(${s1-An})${s1-i4-2}++ */
21896 +  {
21897 +    UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, "not.2-d-indirect-with-post-increment-2-s1-indirect-with-post-increment-2", "not.2", 32,
21898 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21899 +  },
21900 +/* not.2 ${d-i4-2}(${d-An})++,(${s1-An})${s1-i4-2}++ */
21901 +  {
21902 +    UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, "not.2-d-indirect-with-pre-increment-2-s1-indirect-with-post-increment-2", "not.2", 32,
21903 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21904 +  },
21905 +/* not.2 ${d-direct-addr},${s1-i4-2}(${s1-An})++ */
21906 +  {
21907 +    UBICOM32_INSN_NOT_2_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_2, "not.2-d-direct-s1-indirect-with-pre-increment-2", "not.2", 32,
21908 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21909 +  },
21910 +/* not.2 #${d-imm8},${s1-i4-2}(${s1-An})++ */
21911 +  {
21912 +    UBICOM32_INSN_NOT_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, "not.2-d-immediate-2-s1-indirect-with-pre-increment-2", "not.2", 32,
21913 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21914 +  },
21915 +/* not.2 (${d-An},${d-r}),${s1-i4-2}(${s1-An})++ */
21916 +  {
21917 +    UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, "not.2-d-indirect-with-index-2-s1-indirect-with-pre-increment-2", "not.2", 32,
21918 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21919 +  },
21920 +/* not.2 ${d-imm7-2}(${d-An}),${s1-i4-2}(${s1-An})++ */
21921 +  {
21922 +    UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, "not.2-d-indirect-with-offset-2-s1-indirect-with-pre-increment-2", "not.2", 32,
21923 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21924 +  },
21925 +/* not.2 (${d-An}),${s1-i4-2}(${s1-An})++ */
21926 +  {
21927 +    UBICOM32_INSN_NOT_2_D_INDIRECT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, "not.2-d-indirect-2-s1-indirect-with-pre-increment-2", "not.2", 32,
21928 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21929 +  },
21930 +/* not.2 (${d-An})${d-i4-2}++,${s1-i4-2}(${s1-An})++ */
21931 +  {
21932 +    UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, "not.2-d-indirect-with-post-increment-2-s1-indirect-with-pre-increment-2", "not.2", 32,
21933 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21934 +  },
21935 +/* not.2 ${d-i4-2}(${d-An})++,${s1-i4-2}(${s1-An})++ */
21936 +  {
21937 +    UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, "not.2-d-indirect-with-pre-increment-2-s1-indirect-with-pre-increment-2", "not.2", 32,
21938 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
21939 +  },
21940 +/* xor.1 ${d-direct-addr},${s1-direct-addr},${s2} */
21941 +  {
21942 +    UBICOM32_INSN_XOR_1_D_DIRECT_S1_DIRECT, "xor.1-d-direct-s1-direct", "xor.1", 32,
21943 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
21944 +  },
21945 +/* xor.1 #${d-imm8},${s1-direct-addr},${s2} */
21946 +  {
21947 +    UBICOM32_INSN_XOR_1_D_IMMEDIATE_1_S1_DIRECT, "xor.1-d-immediate-1-s1-direct", "xor.1", 32,
21948 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
21949 +  },
21950 +/* xor.1 (${d-An},${d-r}),${s1-direct-addr},${s2} */
21951 +  {
21952 +    UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_INDEX_1_S1_DIRECT, "xor.1-d-indirect-with-index-1-s1-direct", "xor.1", 32,
21953 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
21954 +  },
21955 +/* xor.1 ${d-imm7-1}(${d-An}),${s1-direct-addr},${s2} */
21956 +  {
21957 +    UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_OFFSET_1_S1_DIRECT, "xor.1-d-indirect-with-offset-1-s1-direct", "xor.1", 32,
21958 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
21959 +  },
21960 +/* xor.1 (${d-An}),${s1-direct-addr},${s2} */
21961 +  {
21962 +    UBICOM32_INSN_XOR_1_D_INDIRECT_1_S1_DIRECT, "xor.1-d-indirect-1-s1-direct", "xor.1", 32,
21963 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
21964 +  },
21965 +/* xor.1 (${d-An})${d-i4-1}++,${s1-direct-addr},${s2} */
21966 +  {
21967 +    UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_DIRECT, "xor.1-d-indirect-with-post-increment-1-s1-direct", "xor.1", 32,
21968 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
21969 +  },
21970 +/* xor.1 ${d-i4-1}(${d-An})++,${s1-direct-addr},${s2} */
21971 +  {
21972 +    UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_DIRECT, "xor.1-d-indirect-with-pre-increment-1-s1-direct", "xor.1", 32,
21973 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
21974 +  },
21975 +/* xor.1 ${d-direct-addr},#${s1-imm8},${s2} */
21976 +  {
21977 +    UBICOM32_INSN_XOR_1_D_DIRECT_S1_IMMEDIATE, "xor.1-d-direct-s1-immediate", "xor.1", 32,
21978 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
21979 +  },
21980 +/* xor.1 #${d-imm8},#${s1-imm8},${s2} */
21981 +  {
21982 +    UBICOM32_INSN_XOR_1_D_IMMEDIATE_1_S1_IMMEDIATE, "xor.1-d-immediate-1-s1-immediate", "xor.1", 32,
21983 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
21984 +  },
21985 +/* xor.1 (${d-An},${d-r}),#${s1-imm8},${s2} */
21986 +  {
21987 +    UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_INDEX_1_S1_IMMEDIATE, "xor.1-d-indirect-with-index-1-s1-immediate", "xor.1", 32,
21988 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
21989 +  },
21990 +/* xor.1 ${d-imm7-1}(${d-An}),#${s1-imm8},${s2} */
21991 +  {
21992 +    UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_OFFSET_1_S1_IMMEDIATE, "xor.1-d-indirect-with-offset-1-s1-immediate", "xor.1", 32,
21993 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
21994 +  },
21995 +/* xor.1 (${d-An}),#${s1-imm8},${s2} */
21996 +  {
21997 +    UBICOM32_INSN_XOR_1_D_INDIRECT_1_S1_IMMEDIATE, "xor.1-d-indirect-1-s1-immediate", "xor.1", 32,
21998 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
21999 +  },
22000 +/* xor.1 (${d-An})${d-i4-1}++,#${s1-imm8},${s2} */
22001 +  {
22002 +    UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_IMMEDIATE, "xor.1-d-indirect-with-post-increment-1-s1-immediate", "xor.1", 32,
22003 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22004 +  },
22005 +/* xor.1 ${d-i4-1}(${d-An})++,#${s1-imm8},${s2} */
22006 +  {
22007 +    UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_IMMEDIATE, "xor.1-d-indirect-with-pre-increment-1-s1-immediate", "xor.1", 32,
22008 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22009 +  },
22010 +/* xor.1 ${d-direct-addr},(${s1-An},${s1-r}),${s2} */
22011 +  {
22012 +    UBICOM32_INSN_XOR_1_D_DIRECT_S1_INDIRECT_WITH_INDEX_1, "xor.1-d-direct-s1-indirect-with-index-1", "xor.1", 32,
22013 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22014 +  },
22015 +/* xor.1 #${d-imm8},(${s1-An},${s1-r}),${s2} */
22016 +  {
22017 +    UBICOM32_INSN_XOR_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_INDEX_1, "xor.1-d-immediate-1-s1-indirect-with-index-1", "xor.1", 32,
22018 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22019 +  },
22020 +/* xor.1 (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */
22021 +  {
22022 +    UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_INDEX_1, "xor.1-d-indirect-with-index-1-s1-indirect-with-index-1", "xor.1", 32,
22023 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22024 +  },
22025 +/* xor.1 ${d-imm7-1}(${d-An}),(${s1-An},${s1-r}),${s2} */
22026 +  {
22027 +    UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_INDEX_1, "xor.1-d-indirect-with-offset-1-s1-indirect-with-index-1", "xor.1", 32,
22028 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22029 +  },
22030 +/* xor.1 (${d-An}),(${s1-An},${s1-r}),${s2} */
22031 +  {
22032 +    UBICOM32_INSN_XOR_1_D_INDIRECT_1_S1_INDIRECT_WITH_INDEX_1, "xor.1-d-indirect-1-s1-indirect-with-index-1", "xor.1", 32,
22033 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22034 +  },
22035 +/* xor.1 (${d-An})${d-i4-1}++,(${s1-An},${s1-r}),${s2} */
22036 +  {
22037 +    UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_INDEX_1, "xor.1-d-indirect-with-post-increment-1-s1-indirect-with-index-1", "xor.1", 32,
22038 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22039 +  },
22040 +/* xor.1 ${d-i4-1}(${d-An})++,(${s1-An},${s1-r}),${s2} */
22041 +  {
22042 +    UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_INDEX_1, "xor.1-d-indirect-with-pre-increment-1-s1-indirect-with-index-1", "xor.1", 32,
22043 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22044 +  },
22045 +/* xor.1 ${d-direct-addr},${s1-imm7-1}(${s1-An}),${s2} */
22046 +  {
22047 +    UBICOM32_INSN_XOR_1_D_DIRECT_S1_INDIRECT_WITH_OFFSET_1, "xor.1-d-direct-s1-indirect-with-offset-1", "xor.1", 32,
22048 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22049 +  },
22050 +/* xor.1 #${d-imm8},${s1-imm7-1}(${s1-An}),${s2} */
22051 +  {
22052 +    UBICOM32_INSN_XOR_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_OFFSET_1, "xor.1-d-immediate-1-s1-indirect-with-offset-1", "xor.1", 32,
22053 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22054 +  },
22055 +/* xor.1 (${d-An},${d-r}),${s1-imm7-1}(${s1-An}),${s2} */
22056 +  {
22057 +    UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_OFFSET_1, "xor.1-d-indirect-with-index-1-s1-indirect-with-offset-1", "xor.1", 32,
22058 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22059 +  },
22060 +/* xor.1 ${d-imm7-1}(${d-An}),${s1-imm7-1}(${s1-An}),${s2} */
22061 +  {
22062 +    UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_OFFSET_1, "xor.1-d-indirect-with-offset-1-s1-indirect-with-offset-1", "xor.1", 32,
22063 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22064 +  },
22065 +/* xor.1 (${d-An}),${s1-imm7-1}(${s1-An}),${s2} */
22066 +  {
22067 +    UBICOM32_INSN_XOR_1_D_INDIRECT_1_S1_INDIRECT_WITH_OFFSET_1, "xor.1-d-indirect-1-s1-indirect-with-offset-1", "xor.1", 32,
22068 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22069 +  },
22070 +/* xor.1 (${d-An})${d-i4-1}++,${s1-imm7-1}(${s1-An}),${s2} */
22071 +  {
22072 +    UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_OFFSET_1, "xor.1-d-indirect-with-post-increment-1-s1-indirect-with-offset-1", "xor.1", 32,
22073 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22074 +  },
22075 +/* xor.1 ${d-i4-1}(${d-An})++,${s1-imm7-1}(${s1-An}),${s2} */
22076 +  {
22077 +    UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_OFFSET_1, "xor.1-d-indirect-with-pre-increment-1-s1-indirect-with-offset-1", "xor.1", 32,
22078 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22079 +  },
22080 +/* xor.1 ${d-direct-addr},(${s1-An}),${s2} */
22081 +  {
22082 +    UBICOM32_INSN_XOR_1_D_DIRECT_S1_INDIRECT_1, "xor.1-d-direct-s1-indirect-1", "xor.1", 32,
22083 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22084 +  },
22085 +/* xor.1 #${d-imm8},(${s1-An}),${s2} */
22086 +  {
22087 +    UBICOM32_INSN_XOR_1_D_IMMEDIATE_1_S1_INDIRECT_1, "xor.1-d-immediate-1-s1-indirect-1", "xor.1", 32,
22088 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22089 +  },
22090 +/* xor.1 (${d-An},${d-r}),(${s1-An}),${s2} */
22091 +  {
22092 +    UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_1, "xor.1-d-indirect-with-index-1-s1-indirect-1", "xor.1", 32,
22093 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22094 +  },
22095 +/* xor.1 ${d-imm7-1}(${d-An}),(${s1-An}),${s2} */
22096 +  {
22097 +    UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_1, "xor.1-d-indirect-with-offset-1-s1-indirect-1", "xor.1", 32,
22098 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22099 +  },
22100 +/* xor.1 (${d-An}),(${s1-An}),${s2} */
22101 +  {
22102 +    UBICOM32_INSN_XOR_1_D_INDIRECT_1_S1_INDIRECT_1, "xor.1-d-indirect-1-s1-indirect-1", "xor.1", 32,
22103 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22104 +  },
22105 +/* xor.1 (${d-An})${d-i4-1}++,(${s1-An}),${s2} */
22106 +  {
22107 +    UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_1, "xor.1-d-indirect-with-post-increment-1-s1-indirect-1", "xor.1", 32,
22108 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22109 +  },
22110 +/* xor.1 ${d-i4-1}(${d-An})++,(${s1-An}),${s2} */
22111 +  {
22112 +    UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_1, "xor.1-d-indirect-with-pre-increment-1-s1-indirect-1", "xor.1", 32,
22113 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22114 +  },
22115 +/* xor.1 ${d-direct-addr},(${s1-An})${s1-i4-1}++,${s2} */
22116 +  {
22117 +    UBICOM32_INSN_XOR_1_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_1, "xor.1-d-direct-s1-indirect-with-post-increment-1", "xor.1", 32,
22118 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22119 +  },
22120 +/* xor.1 #${d-imm8},(${s1-An})${s1-i4-1}++,${s2} */
22121 +  {
22122 +    UBICOM32_INSN_XOR_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_POST_INCREMENT_1, "xor.1-d-immediate-1-s1-indirect-with-post-increment-1", "xor.1", 32,
22123 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22124 +  },
22125 +/* xor.1 (${d-An},${d-r}),(${s1-An})${s1-i4-1}++,${s2} */
22126 +  {
22127 +    UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_POST_INCREMENT_1, "xor.1-d-indirect-with-index-1-s1-indirect-with-post-increment-1", "xor.1", 32,
22128 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22129 +  },
22130 +/* xor.1 ${d-imm7-1}(${d-An}),(${s1-An})${s1-i4-1}++,${s2} */
22131 +  {
22132 +    UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_POST_INCREMENT_1, "xor.1-d-indirect-with-offset-1-s1-indirect-with-post-increment-1", "xor.1", 32,
22133 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22134 +  },
22135 +/* xor.1 (${d-An}),(${s1-An})${s1-i4-1}++,${s2} */
22136 +  {
22137 +    UBICOM32_INSN_XOR_1_D_INDIRECT_1_S1_INDIRECT_WITH_POST_INCREMENT_1, "xor.1-d-indirect-1-s1-indirect-with-post-increment-1", "xor.1", 32,
22138 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22139 +  },
22140 +/* xor.1 (${d-An})${d-i4-1}++,(${s1-An})${s1-i4-1}++,${s2} */
22141 +  {
22142 +    UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_POST_INCREMENT_1, "xor.1-d-indirect-with-post-increment-1-s1-indirect-with-post-increment-1", "xor.1", 32,
22143 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22144 +  },
22145 +/* xor.1 ${d-i4-1}(${d-An})++,(${s1-An})${s1-i4-1}++,${s2} */
22146 +  {
22147 +    UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_POST_INCREMENT_1, "xor.1-d-indirect-with-pre-increment-1-s1-indirect-with-post-increment-1", "xor.1", 32,
22148 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22149 +  },
22150 +/* xor.1 ${d-direct-addr},${s1-i4-1}(${s1-An})++,${s2} */
22151 +  {
22152 +    UBICOM32_INSN_XOR_1_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_1, "xor.1-d-direct-s1-indirect-with-pre-increment-1", "xor.1", 32,
22153 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22154 +  },
22155 +/* xor.1 #${d-imm8},${s1-i4-1}(${s1-An})++,${s2} */
22156 +  {
22157 +    UBICOM32_INSN_XOR_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, "xor.1-d-immediate-1-s1-indirect-with-pre-increment-1", "xor.1", 32,
22158 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22159 +  },
22160 +/* xor.1 (${d-An},${d-r}),${s1-i4-1}(${s1-An})++,${s2} */
22161 +  {
22162 +    UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, "xor.1-d-indirect-with-index-1-s1-indirect-with-pre-increment-1", "xor.1", 32,
22163 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22164 +  },
22165 +/* xor.1 ${d-imm7-1}(${d-An}),${s1-i4-1}(${s1-An})++,${s2} */
22166 +  {
22167 +    UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, "xor.1-d-indirect-with-offset-1-s1-indirect-with-pre-increment-1", "xor.1", 32,
22168 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22169 +  },
22170 +/* xor.1 (${d-An}),${s1-i4-1}(${s1-An})++,${s2} */
22171 +  {
22172 +    UBICOM32_INSN_XOR_1_D_INDIRECT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, "xor.1-d-indirect-1-s1-indirect-with-pre-increment-1", "xor.1", 32,
22173 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22174 +  },
22175 +/* xor.1 (${d-An})${d-i4-1}++,${s1-i4-1}(${s1-An})++,${s2} */
22176 +  {
22177 +    UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, "xor.1-d-indirect-with-post-increment-1-s1-indirect-with-pre-increment-1", "xor.1", 32,
22178 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22179 +  },
22180 +/* xor.1 ${d-i4-1}(${d-An})++,${s1-i4-1}(${s1-An})++,${s2} */
22181 +  {
22182 +    UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, "xor.1-d-indirect-with-pre-increment-1-s1-indirect-with-pre-increment-1", "xor.1", 32,
22183 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22184 +  },
22185 +/* or.1 ${d-direct-addr},${s1-direct-addr},${s2} */
22186 +  {
22187 +    UBICOM32_INSN_OR_1_D_DIRECT_S1_DIRECT, "or.1-d-direct-s1-direct", "or.1", 32,
22188 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22189 +  },
22190 +/* or.1 #${d-imm8},${s1-direct-addr},${s2} */
22191 +  {
22192 +    UBICOM32_INSN_OR_1_D_IMMEDIATE_1_S1_DIRECT, "or.1-d-immediate-1-s1-direct", "or.1", 32,
22193 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22194 +  },
22195 +/* or.1 (${d-An},${d-r}),${s1-direct-addr},${s2} */
22196 +  {
22197 +    UBICOM32_INSN_OR_1_D_INDIRECT_WITH_INDEX_1_S1_DIRECT, "or.1-d-indirect-with-index-1-s1-direct", "or.1", 32,
22198 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22199 +  },
22200 +/* or.1 ${d-imm7-1}(${d-An}),${s1-direct-addr},${s2} */
22201 +  {
22202 +    UBICOM32_INSN_OR_1_D_INDIRECT_WITH_OFFSET_1_S1_DIRECT, "or.1-d-indirect-with-offset-1-s1-direct", "or.1", 32,
22203 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22204 +  },
22205 +/* or.1 (${d-An}),${s1-direct-addr},${s2} */
22206 +  {
22207 +    UBICOM32_INSN_OR_1_D_INDIRECT_1_S1_DIRECT, "or.1-d-indirect-1-s1-direct", "or.1", 32,
22208 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22209 +  },
22210 +/* or.1 (${d-An})${d-i4-1}++,${s1-direct-addr},${s2} */
22211 +  {
22212 +    UBICOM32_INSN_OR_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_DIRECT, "or.1-d-indirect-with-post-increment-1-s1-direct", "or.1", 32,
22213 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22214 +  },
22215 +/* or.1 ${d-i4-1}(${d-An})++,${s1-direct-addr},${s2} */
22216 +  {
22217 +    UBICOM32_INSN_OR_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_DIRECT, "or.1-d-indirect-with-pre-increment-1-s1-direct", "or.1", 32,
22218 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22219 +  },
22220 +/* or.1 ${d-direct-addr},#${s1-imm8},${s2} */
22221 +  {
22222 +    UBICOM32_INSN_OR_1_D_DIRECT_S1_IMMEDIATE, "or.1-d-direct-s1-immediate", "or.1", 32,
22223 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22224 +  },
22225 +/* or.1 #${d-imm8},#${s1-imm8},${s2} */
22226 +  {
22227 +    UBICOM32_INSN_OR_1_D_IMMEDIATE_1_S1_IMMEDIATE, "or.1-d-immediate-1-s1-immediate", "or.1", 32,
22228 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22229 +  },
22230 +/* or.1 (${d-An},${d-r}),#${s1-imm8},${s2} */
22231 +  {
22232 +    UBICOM32_INSN_OR_1_D_INDIRECT_WITH_INDEX_1_S1_IMMEDIATE, "or.1-d-indirect-with-index-1-s1-immediate", "or.1", 32,
22233 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22234 +  },
22235 +/* or.1 ${d-imm7-1}(${d-An}),#${s1-imm8},${s2} */
22236 +  {
22237 +    UBICOM32_INSN_OR_1_D_INDIRECT_WITH_OFFSET_1_S1_IMMEDIATE, "or.1-d-indirect-with-offset-1-s1-immediate", "or.1", 32,
22238 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22239 +  },
22240 +/* or.1 (${d-An}),#${s1-imm8},${s2} */
22241 +  {
22242 +    UBICOM32_INSN_OR_1_D_INDIRECT_1_S1_IMMEDIATE, "or.1-d-indirect-1-s1-immediate", "or.1", 32,
22243 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22244 +  },
22245 +/* or.1 (${d-An})${d-i4-1}++,#${s1-imm8},${s2} */
22246 +  {
22247 +    UBICOM32_INSN_OR_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_IMMEDIATE, "or.1-d-indirect-with-post-increment-1-s1-immediate", "or.1", 32,
22248 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22249 +  },
22250 +/* or.1 ${d-i4-1}(${d-An})++,#${s1-imm8},${s2} */
22251 +  {
22252 +    UBICOM32_INSN_OR_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_IMMEDIATE, "or.1-d-indirect-with-pre-increment-1-s1-immediate", "or.1", 32,
22253 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22254 +  },
22255 +/* or.1 ${d-direct-addr},(${s1-An},${s1-r}),${s2} */
22256 +  {
22257 +    UBICOM32_INSN_OR_1_D_DIRECT_S1_INDIRECT_WITH_INDEX_1, "or.1-d-direct-s1-indirect-with-index-1", "or.1", 32,
22258 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22259 +  },
22260 +/* or.1 #${d-imm8},(${s1-An},${s1-r}),${s2} */
22261 +  {
22262 +    UBICOM32_INSN_OR_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_INDEX_1, "or.1-d-immediate-1-s1-indirect-with-index-1", "or.1", 32,
22263 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22264 +  },
22265 +/* or.1 (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */
22266 +  {
22267 +    UBICOM32_INSN_OR_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_INDEX_1, "or.1-d-indirect-with-index-1-s1-indirect-with-index-1", "or.1", 32,
22268 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22269 +  },
22270 +/* or.1 ${d-imm7-1}(${d-An}),(${s1-An},${s1-r}),${s2} */
22271 +  {
22272 +    UBICOM32_INSN_OR_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_INDEX_1, "or.1-d-indirect-with-offset-1-s1-indirect-with-index-1", "or.1", 32,
22273 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22274 +  },
22275 +/* or.1 (${d-An}),(${s1-An},${s1-r}),${s2} */
22276 +  {
22277 +    UBICOM32_INSN_OR_1_D_INDIRECT_1_S1_INDIRECT_WITH_INDEX_1, "or.1-d-indirect-1-s1-indirect-with-index-1", "or.1", 32,
22278 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22279 +  },
22280 +/* or.1 (${d-An})${d-i4-1}++,(${s1-An},${s1-r}),${s2} */
22281 +  {
22282 +    UBICOM32_INSN_OR_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_INDEX_1, "or.1-d-indirect-with-post-increment-1-s1-indirect-with-index-1", "or.1", 32,
22283 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22284 +  },
22285 +/* or.1 ${d-i4-1}(${d-An})++,(${s1-An},${s1-r}),${s2} */
22286 +  {
22287 +    UBICOM32_INSN_OR_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_INDEX_1, "or.1-d-indirect-with-pre-increment-1-s1-indirect-with-index-1", "or.1", 32,
22288 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22289 +  },
22290 +/* or.1 ${d-direct-addr},${s1-imm7-1}(${s1-An}),${s2} */
22291 +  {
22292 +    UBICOM32_INSN_OR_1_D_DIRECT_S1_INDIRECT_WITH_OFFSET_1, "or.1-d-direct-s1-indirect-with-offset-1", "or.1", 32,
22293 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22294 +  },
22295 +/* or.1 #${d-imm8},${s1-imm7-1}(${s1-An}),${s2} */
22296 +  {
22297 +    UBICOM32_INSN_OR_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_OFFSET_1, "or.1-d-immediate-1-s1-indirect-with-offset-1", "or.1", 32,
22298 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22299 +  },
22300 +/* or.1 (${d-An},${d-r}),${s1-imm7-1}(${s1-An}),${s2} */
22301 +  {
22302 +    UBICOM32_INSN_OR_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_OFFSET_1, "or.1-d-indirect-with-index-1-s1-indirect-with-offset-1", "or.1", 32,
22303 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22304 +  },
22305 +/* or.1 ${d-imm7-1}(${d-An}),${s1-imm7-1}(${s1-An}),${s2} */
22306 +  {
22307 +    UBICOM32_INSN_OR_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_OFFSET_1, "or.1-d-indirect-with-offset-1-s1-indirect-with-offset-1", "or.1", 32,
22308 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22309 +  },
22310 +/* or.1 (${d-An}),${s1-imm7-1}(${s1-An}),${s2} */
22311 +  {
22312 +    UBICOM32_INSN_OR_1_D_INDIRECT_1_S1_INDIRECT_WITH_OFFSET_1, "or.1-d-indirect-1-s1-indirect-with-offset-1", "or.1", 32,
22313 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22314 +  },
22315 +/* or.1 (${d-An})${d-i4-1}++,${s1-imm7-1}(${s1-An}),${s2} */
22316 +  {
22317 +    UBICOM32_INSN_OR_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_OFFSET_1, "or.1-d-indirect-with-post-increment-1-s1-indirect-with-offset-1", "or.1", 32,
22318 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22319 +  },
22320 +/* or.1 ${d-i4-1}(${d-An})++,${s1-imm7-1}(${s1-An}),${s2} */
22321 +  {
22322 +    UBICOM32_INSN_OR_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_OFFSET_1, "or.1-d-indirect-with-pre-increment-1-s1-indirect-with-offset-1", "or.1", 32,
22323 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22324 +  },
22325 +/* or.1 ${d-direct-addr},(${s1-An}),${s2} */
22326 +  {
22327 +    UBICOM32_INSN_OR_1_D_DIRECT_S1_INDIRECT_1, "or.1-d-direct-s1-indirect-1", "or.1", 32,
22328 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22329 +  },
22330 +/* or.1 #${d-imm8},(${s1-An}),${s2} */
22331 +  {
22332 +    UBICOM32_INSN_OR_1_D_IMMEDIATE_1_S1_INDIRECT_1, "or.1-d-immediate-1-s1-indirect-1", "or.1", 32,
22333 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22334 +  },
22335 +/* or.1 (${d-An},${d-r}),(${s1-An}),${s2} */
22336 +  {
22337 +    UBICOM32_INSN_OR_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_1, "or.1-d-indirect-with-index-1-s1-indirect-1", "or.1", 32,
22338 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22339 +  },
22340 +/* or.1 ${d-imm7-1}(${d-An}),(${s1-An}),${s2} */
22341 +  {
22342 +    UBICOM32_INSN_OR_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_1, "or.1-d-indirect-with-offset-1-s1-indirect-1", "or.1", 32,
22343 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22344 +  },
22345 +/* or.1 (${d-An}),(${s1-An}),${s2} */
22346 +  {
22347 +    UBICOM32_INSN_OR_1_D_INDIRECT_1_S1_INDIRECT_1, "or.1-d-indirect-1-s1-indirect-1", "or.1", 32,
22348 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22349 +  },
22350 +/* or.1 (${d-An})${d-i4-1}++,(${s1-An}),${s2} */
22351 +  {
22352 +    UBICOM32_INSN_OR_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_1, "or.1-d-indirect-with-post-increment-1-s1-indirect-1", "or.1", 32,
22353 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22354 +  },
22355 +/* or.1 ${d-i4-1}(${d-An})++,(${s1-An}),${s2} */
22356 +  {
22357 +    UBICOM32_INSN_OR_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_1, "or.1-d-indirect-with-pre-increment-1-s1-indirect-1", "or.1", 32,
22358 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22359 +  },
22360 +/* or.1 ${d-direct-addr},(${s1-An})${s1-i4-1}++,${s2} */
22361 +  {
22362 +    UBICOM32_INSN_OR_1_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_1, "or.1-d-direct-s1-indirect-with-post-increment-1", "or.1", 32,
22363 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22364 +  },
22365 +/* or.1 #${d-imm8},(${s1-An})${s1-i4-1}++,${s2} */
22366 +  {
22367 +    UBICOM32_INSN_OR_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_POST_INCREMENT_1, "or.1-d-immediate-1-s1-indirect-with-post-increment-1", "or.1", 32,
22368 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22369 +  },
22370 +/* or.1 (${d-An},${d-r}),(${s1-An})${s1-i4-1}++,${s2} */
22371 +  {
22372 +    UBICOM32_INSN_OR_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_POST_INCREMENT_1, "or.1-d-indirect-with-index-1-s1-indirect-with-post-increment-1", "or.1", 32,
22373 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22374 +  },
22375 +/* or.1 ${d-imm7-1}(${d-An}),(${s1-An})${s1-i4-1}++,${s2} */
22376 +  {
22377 +    UBICOM32_INSN_OR_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_POST_INCREMENT_1, "or.1-d-indirect-with-offset-1-s1-indirect-with-post-increment-1", "or.1", 32,
22378 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22379 +  },
22380 +/* or.1 (${d-An}),(${s1-An})${s1-i4-1}++,${s2} */
22381 +  {
22382 +    UBICOM32_INSN_OR_1_D_INDIRECT_1_S1_INDIRECT_WITH_POST_INCREMENT_1, "or.1-d-indirect-1-s1-indirect-with-post-increment-1", "or.1", 32,
22383 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22384 +  },
22385 +/* or.1 (${d-An})${d-i4-1}++,(${s1-An})${s1-i4-1}++,${s2} */
22386 +  {
22387 +    UBICOM32_INSN_OR_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_POST_INCREMENT_1, "or.1-d-indirect-with-post-increment-1-s1-indirect-with-post-increment-1", "or.1", 32,
22388 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22389 +  },
22390 +/* or.1 ${d-i4-1}(${d-An})++,(${s1-An})${s1-i4-1}++,${s2} */
22391 +  {
22392 +    UBICOM32_INSN_OR_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_POST_INCREMENT_1, "or.1-d-indirect-with-pre-increment-1-s1-indirect-with-post-increment-1", "or.1", 32,
22393 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22394 +  },
22395 +/* or.1 ${d-direct-addr},${s1-i4-1}(${s1-An})++,${s2} */
22396 +  {
22397 +    UBICOM32_INSN_OR_1_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_1, "or.1-d-direct-s1-indirect-with-pre-increment-1", "or.1", 32,
22398 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22399 +  },
22400 +/* or.1 #${d-imm8},${s1-i4-1}(${s1-An})++,${s2} */
22401 +  {
22402 +    UBICOM32_INSN_OR_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, "or.1-d-immediate-1-s1-indirect-with-pre-increment-1", "or.1", 32,
22403 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22404 +  },
22405 +/* or.1 (${d-An},${d-r}),${s1-i4-1}(${s1-An})++,${s2} */
22406 +  {
22407 +    UBICOM32_INSN_OR_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, "or.1-d-indirect-with-index-1-s1-indirect-with-pre-increment-1", "or.1", 32,
22408 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22409 +  },
22410 +/* or.1 ${d-imm7-1}(${d-An}),${s1-i4-1}(${s1-An})++,${s2} */
22411 +  {
22412 +    UBICOM32_INSN_OR_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, "or.1-d-indirect-with-offset-1-s1-indirect-with-pre-increment-1", "or.1", 32,
22413 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22414 +  },
22415 +/* or.1 (${d-An}),${s1-i4-1}(${s1-An})++,${s2} */
22416 +  {
22417 +    UBICOM32_INSN_OR_1_D_INDIRECT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, "or.1-d-indirect-1-s1-indirect-with-pre-increment-1", "or.1", 32,
22418 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22419 +  },
22420 +/* or.1 (${d-An})${d-i4-1}++,${s1-i4-1}(${s1-An})++,${s2} */
22421 +  {
22422 +    UBICOM32_INSN_OR_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, "or.1-d-indirect-with-post-increment-1-s1-indirect-with-pre-increment-1", "or.1", 32,
22423 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22424 +  },
22425 +/* or.1 ${d-i4-1}(${d-An})++,${s1-i4-1}(${s1-An})++,${s2} */
22426 +  {
22427 +    UBICOM32_INSN_OR_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, "or.1-d-indirect-with-pre-increment-1-s1-indirect-with-pre-increment-1", "or.1", 32,
22428 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22429 +  },
22430 +/* and.1 ${d-direct-addr},${s1-direct-addr},${s2} */
22431 +  {
22432 +    UBICOM32_INSN_AND_1_D_DIRECT_S1_DIRECT, "and.1-d-direct-s1-direct", "and.1", 32,
22433 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22434 +  },
22435 +/* and.1 #${d-imm8},${s1-direct-addr},${s2} */
22436 +  {
22437 +    UBICOM32_INSN_AND_1_D_IMMEDIATE_1_S1_DIRECT, "and.1-d-immediate-1-s1-direct", "and.1", 32,
22438 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22439 +  },
22440 +/* and.1 (${d-An},${d-r}),${s1-direct-addr},${s2} */
22441 +  {
22442 +    UBICOM32_INSN_AND_1_D_INDIRECT_WITH_INDEX_1_S1_DIRECT, "and.1-d-indirect-with-index-1-s1-direct", "and.1", 32,
22443 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22444 +  },
22445 +/* and.1 ${d-imm7-1}(${d-An}),${s1-direct-addr},${s2} */
22446 +  {
22447 +    UBICOM32_INSN_AND_1_D_INDIRECT_WITH_OFFSET_1_S1_DIRECT, "and.1-d-indirect-with-offset-1-s1-direct", "and.1", 32,
22448 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22449 +  },
22450 +/* and.1 (${d-An}),${s1-direct-addr},${s2} */
22451 +  {
22452 +    UBICOM32_INSN_AND_1_D_INDIRECT_1_S1_DIRECT, "and.1-d-indirect-1-s1-direct", "and.1", 32,
22453 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22454 +  },
22455 +/* and.1 (${d-An})${d-i4-1}++,${s1-direct-addr},${s2} */
22456 +  {
22457 +    UBICOM32_INSN_AND_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_DIRECT, "and.1-d-indirect-with-post-increment-1-s1-direct", "and.1", 32,
22458 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22459 +  },
22460 +/* and.1 ${d-i4-1}(${d-An})++,${s1-direct-addr},${s2} */
22461 +  {
22462 +    UBICOM32_INSN_AND_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_DIRECT, "and.1-d-indirect-with-pre-increment-1-s1-direct", "and.1", 32,
22463 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22464 +  },
22465 +/* and.1 ${d-direct-addr},#${s1-imm8},${s2} */
22466 +  {
22467 +    UBICOM32_INSN_AND_1_D_DIRECT_S1_IMMEDIATE, "and.1-d-direct-s1-immediate", "and.1", 32,
22468 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22469 +  },
22470 +/* and.1 #${d-imm8},#${s1-imm8},${s2} */
22471 +  {
22472 +    UBICOM32_INSN_AND_1_D_IMMEDIATE_1_S1_IMMEDIATE, "and.1-d-immediate-1-s1-immediate", "and.1", 32,
22473 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22474 +  },
22475 +/* and.1 (${d-An},${d-r}),#${s1-imm8},${s2} */
22476 +  {
22477 +    UBICOM32_INSN_AND_1_D_INDIRECT_WITH_INDEX_1_S1_IMMEDIATE, "and.1-d-indirect-with-index-1-s1-immediate", "and.1", 32,
22478 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22479 +  },
22480 +/* and.1 ${d-imm7-1}(${d-An}),#${s1-imm8},${s2} */
22481 +  {
22482 +    UBICOM32_INSN_AND_1_D_INDIRECT_WITH_OFFSET_1_S1_IMMEDIATE, "and.1-d-indirect-with-offset-1-s1-immediate", "and.1", 32,
22483 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22484 +  },
22485 +/* and.1 (${d-An}),#${s1-imm8},${s2} */
22486 +  {
22487 +    UBICOM32_INSN_AND_1_D_INDIRECT_1_S1_IMMEDIATE, "and.1-d-indirect-1-s1-immediate", "and.1", 32,
22488 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22489 +  },
22490 +/* and.1 (${d-An})${d-i4-1}++,#${s1-imm8},${s2} */
22491 +  {
22492 +    UBICOM32_INSN_AND_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_IMMEDIATE, "and.1-d-indirect-with-post-increment-1-s1-immediate", "and.1", 32,
22493 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22494 +  },
22495 +/* and.1 ${d-i4-1}(${d-An})++,#${s1-imm8},${s2} */
22496 +  {
22497 +    UBICOM32_INSN_AND_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_IMMEDIATE, "and.1-d-indirect-with-pre-increment-1-s1-immediate", "and.1", 32,
22498 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22499 +  },
22500 +/* and.1 ${d-direct-addr},(${s1-An},${s1-r}),${s2} */
22501 +  {
22502 +    UBICOM32_INSN_AND_1_D_DIRECT_S1_INDIRECT_WITH_INDEX_1, "and.1-d-direct-s1-indirect-with-index-1", "and.1", 32,
22503 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22504 +  },
22505 +/* and.1 #${d-imm8},(${s1-An},${s1-r}),${s2} */
22506 +  {
22507 +    UBICOM32_INSN_AND_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_INDEX_1, "and.1-d-immediate-1-s1-indirect-with-index-1", "and.1", 32,
22508 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22509 +  },
22510 +/* and.1 (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */
22511 +  {
22512 +    UBICOM32_INSN_AND_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_INDEX_1, "and.1-d-indirect-with-index-1-s1-indirect-with-index-1", "and.1", 32,
22513 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22514 +  },
22515 +/* and.1 ${d-imm7-1}(${d-An}),(${s1-An},${s1-r}),${s2} */
22516 +  {
22517 +    UBICOM32_INSN_AND_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_INDEX_1, "and.1-d-indirect-with-offset-1-s1-indirect-with-index-1", "and.1", 32,
22518 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22519 +  },
22520 +/* and.1 (${d-An}),(${s1-An},${s1-r}),${s2} */
22521 +  {
22522 +    UBICOM32_INSN_AND_1_D_INDIRECT_1_S1_INDIRECT_WITH_INDEX_1, "and.1-d-indirect-1-s1-indirect-with-index-1", "and.1", 32,
22523 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22524 +  },
22525 +/* and.1 (${d-An})${d-i4-1}++,(${s1-An},${s1-r}),${s2} */
22526 +  {
22527 +    UBICOM32_INSN_AND_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_INDEX_1, "and.1-d-indirect-with-post-increment-1-s1-indirect-with-index-1", "and.1", 32,
22528 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22529 +  },
22530 +/* and.1 ${d-i4-1}(${d-An})++,(${s1-An},${s1-r}),${s2} */
22531 +  {
22532 +    UBICOM32_INSN_AND_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_INDEX_1, "and.1-d-indirect-with-pre-increment-1-s1-indirect-with-index-1", "and.1", 32,
22533 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22534 +  },
22535 +/* and.1 ${d-direct-addr},${s1-imm7-1}(${s1-An}),${s2} */
22536 +  {
22537 +    UBICOM32_INSN_AND_1_D_DIRECT_S1_INDIRECT_WITH_OFFSET_1, "and.1-d-direct-s1-indirect-with-offset-1", "and.1", 32,
22538 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22539 +  },
22540 +/* and.1 #${d-imm8},${s1-imm7-1}(${s1-An}),${s2} */
22541 +  {
22542 +    UBICOM32_INSN_AND_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_OFFSET_1, "and.1-d-immediate-1-s1-indirect-with-offset-1", "and.1", 32,
22543 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22544 +  },
22545 +/* and.1 (${d-An},${d-r}),${s1-imm7-1}(${s1-An}),${s2} */
22546 +  {
22547 +    UBICOM32_INSN_AND_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_OFFSET_1, "and.1-d-indirect-with-index-1-s1-indirect-with-offset-1", "and.1", 32,
22548 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22549 +  },
22550 +/* and.1 ${d-imm7-1}(${d-An}),${s1-imm7-1}(${s1-An}),${s2} */
22551 +  {
22552 +    UBICOM32_INSN_AND_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_OFFSET_1, "and.1-d-indirect-with-offset-1-s1-indirect-with-offset-1", "and.1", 32,
22553 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22554 +  },
22555 +/* and.1 (${d-An}),${s1-imm7-1}(${s1-An}),${s2} */
22556 +  {
22557 +    UBICOM32_INSN_AND_1_D_INDIRECT_1_S1_INDIRECT_WITH_OFFSET_1, "and.1-d-indirect-1-s1-indirect-with-offset-1", "and.1", 32,
22558 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22559 +  },
22560 +/* and.1 (${d-An})${d-i4-1}++,${s1-imm7-1}(${s1-An}),${s2} */
22561 +  {
22562 +    UBICOM32_INSN_AND_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_OFFSET_1, "and.1-d-indirect-with-post-increment-1-s1-indirect-with-offset-1", "and.1", 32,
22563 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22564 +  },
22565 +/* and.1 ${d-i4-1}(${d-An})++,${s1-imm7-1}(${s1-An}),${s2} */
22566 +  {
22567 +    UBICOM32_INSN_AND_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_OFFSET_1, "and.1-d-indirect-with-pre-increment-1-s1-indirect-with-offset-1", "and.1", 32,
22568 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22569 +  },
22570 +/* and.1 ${d-direct-addr},(${s1-An}),${s2} */
22571 +  {
22572 +    UBICOM32_INSN_AND_1_D_DIRECT_S1_INDIRECT_1, "and.1-d-direct-s1-indirect-1", "and.1", 32,
22573 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22574 +  },
22575 +/* and.1 #${d-imm8},(${s1-An}),${s2} */
22576 +  {
22577 +    UBICOM32_INSN_AND_1_D_IMMEDIATE_1_S1_INDIRECT_1, "and.1-d-immediate-1-s1-indirect-1", "and.1", 32,
22578 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22579 +  },
22580 +/* and.1 (${d-An},${d-r}),(${s1-An}),${s2} */
22581 +  {
22582 +    UBICOM32_INSN_AND_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_1, "and.1-d-indirect-with-index-1-s1-indirect-1", "and.1", 32,
22583 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22584 +  },
22585 +/* and.1 ${d-imm7-1}(${d-An}),(${s1-An}),${s2} */
22586 +  {
22587 +    UBICOM32_INSN_AND_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_1, "and.1-d-indirect-with-offset-1-s1-indirect-1", "and.1", 32,
22588 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22589 +  },
22590 +/* and.1 (${d-An}),(${s1-An}),${s2} */
22591 +  {
22592 +    UBICOM32_INSN_AND_1_D_INDIRECT_1_S1_INDIRECT_1, "and.1-d-indirect-1-s1-indirect-1", "and.1", 32,
22593 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22594 +  },
22595 +/* and.1 (${d-An})${d-i4-1}++,(${s1-An}),${s2} */
22596 +  {
22597 +    UBICOM32_INSN_AND_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_1, "and.1-d-indirect-with-post-increment-1-s1-indirect-1", "and.1", 32,
22598 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22599 +  },
22600 +/* and.1 ${d-i4-1}(${d-An})++,(${s1-An}),${s2} */
22601 +  {
22602 +    UBICOM32_INSN_AND_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_1, "and.1-d-indirect-with-pre-increment-1-s1-indirect-1", "and.1", 32,
22603 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22604 +  },
22605 +/* and.1 ${d-direct-addr},(${s1-An})${s1-i4-1}++,${s2} */
22606 +  {
22607 +    UBICOM32_INSN_AND_1_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_1, "and.1-d-direct-s1-indirect-with-post-increment-1", "and.1", 32,
22608 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22609 +  },
22610 +/* and.1 #${d-imm8},(${s1-An})${s1-i4-1}++,${s2} */
22611 +  {
22612 +    UBICOM32_INSN_AND_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_POST_INCREMENT_1, "and.1-d-immediate-1-s1-indirect-with-post-increment-1", "and.1", 32,
22613 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22614 +  },
22615 +/* and.1 (${d-An},${d-r}),(${s1-An})${s1-i4-1}++,${s2} */
22616 +  {
22617 +    UBICOM32_INSN_AND_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_POST_INCREMENT_1, "and.1-d-indirect-with-index-1-s1-indirect-with-post-increment-1", "and.1", 32,
22618 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22619 +  },
22620 +/* and.1 ${d-imm7-1}(${d-An}),(${s1-An})${s1-i4-1}++,${s2} */
22621 +  {
22622 +    UBICOM32_INSN_AND_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_POST_INCREMENT_1, "and.1-d-indirect-with-offset-1-s1-indirect-with-post-increment-1", "and.1", 32,
22623 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22624 +  },
22625 +/* and.1 (${d-An}),(${s1-An})${s1-i4-1}++,${s2} */
22626 +  {
22627 +    UBICOM32_INSN_AND_1_D_INDIRECT_1_S1_INDIRECT_WITH_POST_INCREMENT_1, "and.1-d-indirect-1-s1-indirect-with-post-increment-1", "and.1", 32,
22628 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22629 +  },
22630 +/* and.1 (${d-An})${d-i4-1}++,(${s1-An})${s1-i4-1}++,${s2} */
22631 +  {
22632 +    UBICOM32_INSN_AND_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_POST_INCREMENT_1, "and.1-d-indirect-with-post-increment-1-s1-indirect-with-post-increment-1", "and.1", 32,
22633 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22634 +  },
22635 +/* and.1 ${d-i4-1}(${d-An})++,(${s1-An})${s1-i4-1}++,${s2} */
22636 +  {
22637 +    UBICOM32_INSN_AND_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_POST_INCREMENT_1, "and.1-d-indirect-with-pre-increment-1-s1-indirect-with-post-increment-1", "and.1", 32,
22638 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22639 +  },
22640 +/* and.1 ${d-direct-addr},${s1-i4-1}(${s1-An})++,${s2} */
22641 +  {
22642 +    UBICOM32_INSN_AND_1_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_1, "and.1-d-direct-s1-indirect-with-pre-increment-1", "and.1", 32,
22643 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22644 +  },
22645 +/* and.1 #${d-imm8},${s1-i4-1}(${s1-An})++,${s2} */
22646 +  {
22647 +    UBICOM32_INSN_AND_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, "and.1-d-immediate-1-s1-indirect-with-pre-increment-1", "and.1", 32,
22648 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22649 +  },
22650 +/* and.1 (${d-An},${d-r}),${s1-i4-1}(${s1-An})++,${s2} */
22651 +  {
22652 +    UBICOM32_INSN_AND_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, "and.1-d-indirect-with-index-1-s1-indirect-with-pre-increment-1", "and.1", 32,
22653 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22654 +  },
22655 +/* and.1 ${d-imm7-1}(${d-An}),${s1-i4-1}(${s1-An})++,${s2} */
22656 +  {
22657 +    UBICOM32_INSN_AND_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, "and.1-d-indirect-with-offset-1-s1-indirect-with-pre-increment-1", "and.1", 32,
22658 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22659 +  },
22660 +/* and.1 (${d-An}),${s1-i4-1}(${s1-An})++,${s2} */
22661 +  {
22662 +    UBICOM32_INSN_AND_1_D_INDIRECT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, "and.1-d-indirect-1-s1-indirect-with-pre-increment-1", "and.1", 32,
22663 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22664 +  },
22665 +/* and.1 (${d-An})${d-i4-1}++,${s1-i4-1}(${s1-An})++,${s2} */
22666 +  {
22667 +    UBICOM32_INSN_AND_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, "and.1-d-indirect-with-post-increment-1-s1-indirect-with-pre-increment-1", "and.1", 32,
22668 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22669 +  },
22670 +/* and.1 ${d-i4-1}(${d-An})++,${s1-i4-1}(${s1-An})++,${s2} */
22671 +  {
22672 +    UBICOM32_INSN_AND_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, "and.1-d-indirect-with-pre-increment-1-s1-indirect-with-pre-increment-1", "and.1", 32,
22673 +    { 0, { { { (1<<MACH_UBICOM32_VER4), 0 } } } }
22674 +  },
22675 +/* xor.4 ${d-direct-addr},${s1-direct-addr},${s2} */
22676 +  {
22677 +    UBICOM32_INSN_XOR_4_D_DIRECT_S1_DIRECT, "xor.4-d-direct-s1-direct", "xor.4", 32,
22678 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22679 +  },
22680 +/* xor.4 #${d-imm8},${s1-direct-addr},${s2} */
22681 +  {
22682 +    UBICOM32_INSN_XOR_4_D_IMMEDIATE_4_S1_DIRECT, "xor.4-d-immediate-4-s1-direct", "xor.4", 32,
22683 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22684 +  },
22685 +/* xor.4 (${d-An},${d-r}),${s1-direct-addr},${s2} */
22686 +  {
22687 +    UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_INDEX_4_S1_DIRECT, "xor.4-d-indirect-with-index-4-s1-direct", "xor.4", 32,
22688 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22689 +  },
22690 +/* xor.4 ${d-imm7-4}(${d-An}),${s1-direct-addr},${s2} */
22691 +  {
22692 +    UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_OFFSET_4_S1_DIRECT, "xor.4-d-indirect-with-offset-4-s1-direct", "xor.4", 32,
22693 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22694 +  },
22695 +/* xor.4 (${d-An}),${s1-direct-addr},${s2} */
22696 +  {
22697 +    UBICOM32_INSN_XOR_4_D_INDIRECT_4_S1_DIRECT, "xor.4-d-indirect-4-s1-direct", "xor.4", 32,
22698 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22699 +  },
22700 +/* xor.4 (${d-An})${d-i4-4}++,${s1-direct-addr},${s2} */
22701 +  {
22702 +    UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_DIRECT, "xor.4-d-indirect-with-post-increment-4-s1-direct", "xor.4", 32,
22703 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22704 +  },
22705 +/* xor.4 ${d-i4-4}(${d-An})++,${s1-direct-addr},${s2} */
22706 +  {
22707 +    UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_DIRECT, "xor.4-d-indirect-with-pre-increment-4-s1-direct", "xor.4", 32,
22708 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22709 +  },
22710 +/* xor.4 ${d-direct-addr},#${s1-imm8},${s2} */
22711 +  {
22712 +    UBICOM32_INSN_XOR_4_D_DIRECT_S1_IMMEDIATE, "xor.4-d-direct-s1-immediate", "xor.4", 32,
22713 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22714 +  },
22715 +/* xor.4 #${d-imm8},#${s1-imm8},${s2} */
22716 +  {
22717 +    UBICOM32_INSN_XOR_4_D_IMMEDIATE_4_S1_IMMEDIATE, "xor.4-d-immediate-4-s1-immediate", "xor.4", 32,
22718 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22719 +  },
22720 +/* xor.4 (${d-An},${d-r}),#${s1-imm8},${s2} */
22721 +  {
22722 +    UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_INDEX_4_S1_IMMEDIATE, "xor.4-d-indirect-with-index-4-s1-immediate", "xor.4", 32,
22723 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22724 +  },
22725 +/* xor.4 ${d-imm7-4}(${d-An}),#${s1-imm8},${s2} */
22726 +  {
22727 +    UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_OFFSET_4_S1_IMMEDIATE, "xor.4-d-indirect-with-offset-4-s1-immediate", "xor.4", 32,
22728 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22729 +  },
22730 +/* xor.4 (${d-An}),#${s1-imm8},${s2} */
22731 +  {
22732 +    UBICOM32_INSN_XOR_4_D_INDIRECT_4_S1_IMMEDIATE, "xor.4-d-indirect-4-s1-immediate", "xor.4", 32,
22733 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22734 +  },
22735 +/* xor.4 (${d-An})${d-i4-4}++,#${s1-imm8},${s2} */
22736 +  {
22737 +    UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_IMMEDIATE, "xor.4-d-indirect-with-post-increment-4-s1-immediate", "xor.4", 32,
22738 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22739 +  },
22740 +/* xor.4 ${d-i4-4}(${d-An})++,#${s1-imm8},${s2} */
22741 +  {
22742 +    UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_IMMEDIATE, "xor.4-d-indirect-with-pre-increment-4-s1-immediate", "xor.4", 32,
22743 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22744 +  },
22745 +/* xor.4 ${d-direct-addr},(${s1-An},${s1-r}),${s2} */
22746 +  {
22747 +    UBICOM32_INSN_XOR_4_D_DIRECT_S1_INDIRECT_WITH_INDEX_4, "xor.4-d-direct-s1-indirect-with-index-4", "xor.4", 32,
22748 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22749 +  },
22750 +/* xor.4 #${d-imm8},(${s1-An},${s1-r}),${s2} */
22751 +  {
22752 +    UBICOM32_INSN_XOR_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_INDEX_4, "xor.4-d-immediate-4-s1-indirect-with-index-4", "xor.4", 32,
22753 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22754 +  },
22755 +/* xor.4 (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */
22756 +  {
22757 +    UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_INDEX_4, "xor.4-d-indirect-with-index-4-s1-indirect-with-index-4", "xor.4", 32,
22758 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22759 +  },
22760 +/* xor.4 ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}),${s2} */
22761 +  {
22762 +    UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_INDEX_4, "xor.4-d-indirect-with-offset-4-s1-indirect-with-index-4", "xor.4", 32,
22763 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22764 +  },
22765 +/* xor.4 (${d-An}),(${s1-An},${s1-r}),${s2} */
22766 +  {
22767 +    UBICOM32_INSN_XOR_4_D_INDIRECT_4_S1_INDIRECT_WITH_INDEX_4, "xor.4-d-indirect-4-s1-indirect-with-index-4", "xor.4", 32,
22768 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22769 +  },
22770 +/* xor.4 (${d-An})${d-i4-4}++,(${s1-An},${s1-r}),${s2} */
22771 +  {
22772 +    UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, "xor.4-d-indirect-with-post-increment-4-s1-indirect-with-index-4", "xor.4", 32,
22773 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22774 +  },
22775 +/* xor.4 ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}),${s2} */
22776 +  {
22777 +    UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, "xor.4-d-indirect-with-pre-increment-4-s1-indirect-with-index-4", "xor.4", 32,
22778 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22779 +  },
22780 +/* xor.4 ${d-direct-addr},${s1-imm7-4}(${s1-An}),${s2} */
22781 +  {
22782 +    UBICOM32_INSN_XOR_4_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4, "xor.4-d-direct-s1-indirect-with-offset-4", "xor.4", 32,
22783 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22784 +  },
22785 +/* xor.4 #${d-imm8},${s1-imm7-4}(${s1-An}),${s2} */
22786 +  {
22787 +    UBICOM32_INSN_XOR_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_OFFSET_4, "xor.4-d-immediate-4-s1-indirect-with-offset-4", "xor.4", 32,
22788 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22789 +  },
22790 +/* xor.4 (${d-An},${d-r}),${s1-imm7-4}(${s1-An}),${s2} */
22791 +  {
22792 +    UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_OFFSET_4, "xor.4-d-indirect-with-index-4-s1-indirect-with-offset-4", "xor.4", 32,
22793 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22794 +  },
22795 +/* xor.4 ${d-imm7-4}(${d-An}),${s1-imm7-4}(${s1-An}),${s2} */
22796 +  {
22797 +    UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_OFFSET_4, "xor.4-d-indirect-with-offset-4-s1-indirect-with-offset-4", "xor.4", 32,
22798 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22799 +  },
22800 +/* xor.4 (${d-An}),${s1-imm7-4}(${s1-An}),${s2} */
22801 +  {
22802 +    UBICOM32_INSN_XOR_4_D_INDIRECT_4_S1_INDIRECT_WITH_OFFSET_4, "xor.4-d-indirect-4-s1-indirect-with-offset-4", "xor.4", 32,
22803 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22804 +  },
22805 +/* xor.4 (${d-An})${d-i4-4}++,${s1-imm7-4}(${s1-An}),${s2} */
22806 +  {
22807 +    UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, "xor.4-d-indirect-with-post-increment-4-s1-indirect-with-offset-4", "xor.4", 32,
22808 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22809 +  },
22810 +/* xor.4 ${d-i4-4}(${d-An})++,${s1-imm7-4}(${s1-An}),${s2} */
22811 +  {
22812 +    UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, "xor.4-d-indirect-with-pre-increment-4-s1-indirect-with-offset-4", "xor.4", 32,
22813 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22814 +  },
22815 +/* xor.4 ${d-direct-addr},(${s1-An}),${s2} */
22816 +  {
22817 +    UBICOM32_INSN_XOR_4_D_DIRECT_S1_INDIRECT_4, "xor.4-d-direct-s1-indirect-4", "xor.4", 32,
22818 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22819 +  },
22820 +/* xor.4 #${d-imm8},(${s1-An}),${s2} */
22821 +  {
22822 +    UBICOM32_INSN_XOR_4_D_IMMEDIATE_4_S1_INDIRECT_4, "xor.4-d-immediate-4-s1-indirect-4", "xor.4", 32,
22823 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22824 +  },
22825 +/* xor.4 (${d-An},${d-r}),(${s1-An}),${s2} */
22826 +  {
22827 +    UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_4, "xor.4-d-indirect-with-index-4-s1-indirect-4", "xor.4", 32,
22828 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22829 +  },
22830 +/* xor.4 ${d-imm7-4}(${d-An}),(${s1-An}),${s2} */
22831 +  {
22832 +    UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_4, "xor.4-d-indirect-with-offset-4-s1-indirect-4", "xor.4", 32,
22833 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22834 +  },
22835 +/* xor.4 (${d-An}),(${s1-An}),${s2} */
22836 +  {
22837 +    UBICOM32_INSN_XOR_4_D_INDIRECT_4_S1_INDIRECT_4, "xor.4-d-indirect-4-s1-indirect-4", "xor.4", 32,
22838 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22839 +  },
22840 +/* xor.4 (${d-An})${d-i4-4}++,(${s1-An}),${s2} */
22841 +  {
22842 +    UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_4, "xor.4-d-indirect-with-post-increment-4-s1-indirect-4", "xor.4", 32,
22843 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22844 +  },
22845 +/* xor.4 ${d-i4-4}(${d-An})++,(${s1-An}),${s2} */
22846 +  {
22847 +    UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_4, "xor.4-d-indirect-with-pre-increment-4-s1-indirect-4", "xor.4", 32,
22848 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22849 +  },
22850 +/* xor.4 ${d-direct-addr},(${s1-An})${s1-i4-4}++,${s2} */
22851 +  {
22852 +    UBICOM32_INSN_XOR_4_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4, "xor.4-d-direct-s1-indirect-with-post-increment-4", "xor.4", 32,
22853 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22854 +  },
22855 +/* xor.4 #${d-imm8},(${s1-An})${s1-i4-4}++,${s2} */
22856 +  {
22857 +    UBICOM32_INSN_XOR_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "xor.4-d-immediate-4-s1-indirect-with-post-increment-4", "xor.4", 32,
22858 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22859 +  },
22860 +/* xor.4 (${d-An},${d-r}),(${s1-An})${s1-i4-4}++,${s2} */
22861 +  {
22862 +    UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "xor.4-d-indirect-with-index-4-s1-indirect-with-post-increment-4", "xor.4", 32,
22863 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22864 +  },
22865 +/* xor.4 ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-4}++,${s2} */
22866 +  {
22867 +    UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "xor.4-d-indirect-with-offset-4-s1-indirect-with-post-increment-4", "xor.4", 32,
22868 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22869 +  },
22870 +/* xor.4 (${d-An}),(${s1-An})${s1-i4-4}++,${s2} */
22871 +  {
22872 +    UBICOM32_INSN_XOR_4_D_INDIRECT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "xor.4-d-indirect-4-s1-indirect-with-post-increment-4", "xor.4", 32,
22873 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22874 +  },
22875 +/* xor.4 (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-4}++,${s2} */
22876 +  {
22877 +    UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "xor.4-d-indirect-with-post-increment-4-s1-indirect-with-post-increment-4", "xor.4", 32,
22878 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22879 +  },
22880 +/* xor.4 ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-4}++,${s2} */
22881 +  {
22882 +    UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "xor.4-d-indirect-with-pre-increment-4-s1-indirect-with-post-increment-4", "xor.4", 32,
22883 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22884 +  },
22885 +/* xor.4 ${d-direct-addr},${s1-i4-4}(${s1-An})++,${s2} */
22886 +  {
22887 +    UBICOM32_INSN_XOR_4_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4, "xor.4-d-direct-s1-indirect-with-pre-increment-4", "xor.4", 32,
22888 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22889 +  },
22890 +/* xor.4 #${d-imm8},${s1-i4-4}(${s1-An})++,${s2} */
22891 +  {
22892 +    UBICOM32_INSN_XOR_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "xor.4-d-immediate-4-s1-indirect-with-pre-increment-4", "xor.4", 32,
22893 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22894 +  },
22895 +/* xor.4 (${d-An},${d-r}),${s1-i4-4}(${s1-An})++,${s2} */
22896 +  {
22897 +    UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "xor.4-d-indirect-with-index-4-s1-indirect-with-pre-increment-4", "xor.4", 32,
22898 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22899 +  },
22900 +/* xor.4 ${d-imm7-4}(${d-An}),${s1-i4-4}(${s1-An})++,${s2} */
22901 +  {
22902 +    UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "xor.4-d-indirect-with-offset-4-s1-indirect-with-pre-increment-4", "xor.4", 32,
22903 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22904 +  },
22905 +/* xor.4 (${d-An}),${s1-i4-4}(${s1-An})++,${s2} */
22906 +  {
22907 +    UBICOM32_INSN_XOR_4_D_INDIRECT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "xor.4-d-indirect-4-s1-indirect-with-pre-increment-4", "xor.4", 32,
22908 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22909 +  },
22910 +/* xor.4 (${d-An})${d-i4-4}++,${s1-i4-4}(${s1-An})++,${s2} */
22911 +  {
22912 +    UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "xor.4-d-indirect-with-post-increment-4-s1-indirect-with-pre-increment-4", "xor.4", 32,
22913 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22914 +  },
22915 +/* xor.4 ${d-i4-4}(${d-An})++,${s1-i4-4}(${s1-An})++,${s2} */
22916 +  {
22917 +    UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "xor.4-d-indirect-with-pre-increment-4-s1-indirect-with-pre-increment-4", "xor.4", 32,
22918 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22919 +  },
22920 +/* xor.2 ${d-direct-addr},${s1-direct-addr},${s2} */
22921 +  {
22922 +    UBICOM32_INSN_XOR_2_D_DIRECT_S1_DIRECT, "xor.2-d-direct-s1-direct", "xor.2", 32,
22923 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22924 +  },
22925 +/* xor.2 #${d-imm8},${s1-direct-addr},${s2} */
22926 +  {
22927 +    UBICOM32_INSN_XOR_2_D_IMMEDIATE_2_S1_DIRECT, "xor.2-d-immediate-2-s1-direct", "xor.2", 32,
22928 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22929 +  },
22930 +/* xor.2 (${d-An},${d-r}),${s1-direct-addr},${s2} */
22931 +  {
22932 +    UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_INDEX_2_S1_DIRECT, "xor.2-d-indirect-with-index-2-s1-direct", "xor.2", 32,
22933 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22934 +  },
22935 +/* xor.2 ${d-imm7-2}(${d-An}),${s1-direct-addr},${s2} */
22936 +  {
22937 +    UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_OFFSET_2_S1_DIRECT, "xor.2-d-indirect-with-offset-2-s1-direct", "xor.2", 32,
22938 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22939 +  },
22940 +/* xor.2 (${d-An}),${s1-direct-addr},${s2} */
22941 +  {
22942 +    UBICOM32_INSN_XOR_2_D_INDIRECT_2_S1_DIRECT, "xor.2-d-indirect-2-s1-direct", "xor.2", 32,
22943 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22944 +  },
22945 +/* xor.2 (${d-An})${d-i4-2}++,${s1-direct-addr},${s2} */
22946 +  {
22947 +    UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_DIRECT, "xor.2-d-indirect-with-post-increment-2-s1-direct", "xor.2", 32,
22948 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22949 +  },
22950 +/* xor.2 ${d-i4-2}(${d-An})++,${s1-direct-addr},${s2} */
22951 +  {
22952 +    UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_DIRECT, "xor.2-d-indirect-with-pre-increment-2-s1-direct", "xor.2", 32,
22953 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22954 +  },
22955 +/* xor.2 ${d-direct-addr},#${s1-imm8},${s2} */
22956 +  {
22957 +    UBICOM32_INSN_XOR_2_D_DIRECT_S1_IMMEDIATE, "xor.2-d-direct-s1-immediate", "xor.2", 32,
22958 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22959 +  },
22960 +/* xor.2 #${d-imm8},#${s1-imm8},${s2} */
22961 +  {
22962 +    UBICOM32_INSN_XOR_2_D_IMMEDIATE_2_S1_IMMEDIATE, "xor.2-d-immediate-2-s1-immediate", "xor.2", 32,
22963 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22964 +  },
22965 +/* xor.2 (${d-An},${d-r}),#${s1-imm8},${s2} */
22966 +  {
22967 +    UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_INDEX_2_S1_IMMEDIATE, "xor.2-d-indirect-with-index-2-s1-immediate", "xor.2", 32,
22968 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22969 +  },
22970 +/* xor.2 ${d-imm7-2}(${d-An}),#${s1-imm8},${s2} */
22971 +  {
22972 +    UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_OFFSET_2_S1_IMMEDIATE, "xor.2-d-indirect-with-offset-2-s1-immediate", "xor.2", 32,
22973 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22974 +  },
22975 +/* xor.2 (${d-An}),#${s1-imm8},${s2} */
22976 +  {
22977 +    UBICOM32_INSN_XOR_2_D_INDIRECT_2_S1_IMMEDIATE, "xor.2-d-indirect-2-s1-immediate", "xor.2", 32,
22978 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22979 +  },
22980 +/* xor.2 (${d-An})${d-i4-2}++,#${s1-imm8},${s2} */
22981 +  {
22982 +    UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_IMMEDIATE, "xor.2-d-indirect-with-post-increment-2-s1-immediate", "xor.2", 32,
22983 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22984 +  },
22985 +/* xor.2 ${d-i4-2}(${d-An})++,#${s1-imm8},${s2} */
22986 +  {
22987 +    UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_IMMEDIATE, "xor.2-d-indirect-with-pre-increment-2-s1-immediate", "xor.2", 32,
22988 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22989 +  },
22990 +/* xor.2 ${d-direct-addr},(${s1-An},${s1-r}),${s2} */
22991 +  {
22992 +    UBICOM32_INSN_XOR_2_D_DIRECT_S1_INDIRECT_WITH_INDEX_2, "xor.2-d-direct-s1-indirect-with-index-2", "xor.2", 32,
22993 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22994 +  },
22995 +/* xor.2 #${d-imm8},(${s1-An},${s1-r}),${s2} */
22996 +  {
22997 +    UBICOM32_INSN_XOR_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_INDEX_2, "xor.2-d-immediate-2-s1-indirect-with-index-2", "xor.2", 32,
22998 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
22999 +  },
23000 +/* xor.2 (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */
23001 +  {
23002 +    UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_INDEX_2, "xor.2-d-indirect-with-index-2-s1-indirect-with-index-2", "xor.2", 32,
23003 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23004 +  },
23005 +/* xor.2 ${d-imm7-2}(${d-An}),(${s1-An},${s1-r}),${s2} */
23006 +  {
23007 +    UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_INDEX_2, "xor.2-d-indirect-with-offset-2-s1-indirect-with-index-2", "xor.2", 32,
23008 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23009 +  },
23010 +/* xor.2 (${d-An}),(${s1-An},${s1-r}),${s2} */
23011 +  {
23012 +    UBICOM32_INSN_XOR_2_D_INDIRECT_2_S1_INDIRECT_WITH_INDEX_2, "xor.2-d-indirect-2-s1-indirect-with-index-2", "xor.2", 32,
23013 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23014 +  },
23015 +/* xor.2 (${d-An})${d-i4-2}++,(${s1-An},${s1-r}),${s2} */
23016 +  {
23017 +    UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_INDEX_2, "xor.2-d-indirect-with-post-increment-2-s1-indirect-with-index-2", "xor.2", 32,
23018 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23019 +  },
23020 +/* xor.2 ${d-i4-2}(${d-An})++,(${s1-An},${s1-r}),${s2} */
23021 +  {
23022 +    UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_INDEX_2, "xor.2-d-indirect-with-pre-increment-2-s1-indirect-with-index-2", "xor.2", 32,
23023 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23024 +  },
23025 +/* xor.2 ${d-direct-addr},${s1-imm7-2}(${s1-An}),${s2} */
23026 +  {
23027 +    UBICOM32_INSN_XOR_2_D_DIRECT_S1_INDIRECT_WITH_OFFSET_2, "xor.2-d-direct-s1-indirect-with-offset-2", "xor.2", 32,
23028 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23029 +  },
23030 +/* xor.2 #${d-imm8},${s1-imm7-2}(${s1-An}),${s2} */
23031 +  {
23032 +    UBICOM32_INSN_XOR_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_OFFSET_2, "xor.2-d-immediate-2-s1-indirect-with-offset-2", "xor.2", 32,
23033 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23034 +  },
23035 +/* xor.2 (${d-An},${d-r}),${s1-imm7-2}(${s1-An}),${s2} */
23036 +  {
23037 +    UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_OFFSET_2, "xor.2-d-indirect-with-index-2-s1-indirect-with-offset-2", "xor.2", 32,
23038 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23039 +  },
23040 +/* xor.2 ${d-imm7-2}(${d-An}),${s1-imm7-2}(${s1-An}),${s2} */
23041 +  {
23042 +    UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_OFFSET_2, "xor.2-d-indirect-with-offset-2-s1-indirect-with-offset-2", "xor.2", 32,
23043 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23044 +  },
23045 +/* xor.2 (${d-An}),${s1-imm7-2}(${s1-An}),${s2} */
23046 +  {
23047 +    UBICOM32_INSN_XOR_2_D_INDIRECT_2_S1_INDIRECT_WITH_OFFSET_2, "xor.2-d-indirect-2-s1-indirect-with-offset-2", "xor.2", 32,
23048 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23049 +  },
23050 +/* xor.2 (${d-An})${d-i4-2}++,${s1-imm7-2}(${s1-An}),${s2} */
23051 +  {
23052 +    UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_2, "xor.2-d-indirect-with-post-increment-2-s1-indirect-with-offset-2", "xor.2", 32,
23053 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23054 +  },
23055 +/* xor.2 ${d-i4-2}(${d-An})++,${s1-imm7-2}(${s1-An}),${s2} */
23056 +  {
23057 +    UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_2, "xor.2-d-indirect-with-pre-increment-2-s1-indirect-with-offset-2", "xor.2", 32,
23058 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23059 +  },
23060 +/* xor.2 ${d-direct-addr},(${s1-An}),${s2} */
23061 +  {
23062 +    UBICOM32_INSN_XOR_2_D_DIRECT_S1_INDIRECT_2, "xor.2-d-direct-s1-indirect-2", "xor.2", 32,
23063 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23064 +  },
23065 +/* xor.2 #${d-imm8},(${s1-An}),${s2} */
23066 +  {
23067 +    UBICOM32_INSN_XOR_2_D_IMMEDIATE_2_S1_INDIRECT_2, "xor.2-d-immediate-2-s1-indirect-2", "xor.2", 32,
23068 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23069 +  },
23070 +/* xor.2 (${d-An},${d-r}),(${s1-An}),${s2} */
23071 +  {
23072 +    UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_2, "xor.2-d-indirect-with-index-2-s1-indirect-2", "xor.2", 32,
23073 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23074 +  },
23075 +/* xor.2 ${d-imm7-2}(${d-An}),(${s1-An}),${s2} */
23076 +  {
23077 +    UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_2, "xor.2-d-indirect-with-offset-2-s1-indirect-2", "xor.2", 32,
23078 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23079 +  },
23080 +/* xor.2 (${d-An}),(${s1-An}),${s2} */
23081 +  {
23082 +    UBICOM32_INSN_XOR_2_D_INDIRECT_2_S1_INDIRECT_2, "xor.2-d-indirect-2-s1-indirect-2", "xor.2", 32,
23083 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23084 +  },
23085 +/* xor.2 (${d-An})${d-i4-2}++,(${s1-An}),${s2} */
23086 +  {
23087 +    UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_2, "xor.2-d-indirect-with-post-increment-2-s1-indirect-2", "xor.2", 32,
23088 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23089 +  },
23090 +/* xor.2 ${d-i4-2}(${d-An})++,(${s1-An}),${s2} */
23091 +  {
23092 +    UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_2, "xor.2-d-indirect-with-pre-increment-2-s1-indirect-2", "xor.2", 32,
23093 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23094 +  },
23095 +/* xor.2 ${d-direct-addr},(${s1-An})${s1-i4-2}++,${s2} */
23096 +  {
23097 +    UBICOM32_INSN_XOR_2_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_2, "xor.2-d-direct-s1-indirect-with-post-increment-2", "xor.2", 32,
23098 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23099 +  },
23100 +/* xor.2 #${d-imm8},(${s1-An})${s1-i4-2}++,${s2} */
23101 +  {
23102 +    UBICOM32_INSN_XOR_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_POST_INCREMENT_2, "xor.2-d-immediate-2-s1-indirect-with-post-increment-2", "xor.2", 32,
23103 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23104 +  },
23105 +/* xor.2 (${d-An},${d-r}),(${s1-An})${s1-i4-2}++,${s2} */
23106 +  {
23107 +    UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_POST_INCREMENT_2, "xor.2-d-indirect-with-index-2-s1-indirect-with-post-increment-2", "xor.2", 32,
23108 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23109 +  },
23110 +/* xor.2 ${d-imm7-2}(${d-An}),(${s1-An})${s1-i4-2}++,${s2} */
23111 +  {
23112 +    UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_POST_INCREMENT_2, "xor.2-d-indirect-with-offset-2-s1-indirect-with-post-increment-2", "xor.2", 32,
23113 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23114 +  },
23115 +/* xor.2 (${d-An}),(${s1-An})${s1-i4-2}++,${s2} */
23116 +  {
23117 +    UBICOM32_INSN_XOR_2_D_INDIRECT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, "xor.2-d-indirect-2-s1-indirect-with-post-increment-2", "xor.2", 32,
23118 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23119 +  },
23120 +/* xor.2 (${d-An})${d-i4-2}++,(${s1-An})${s1-i4-2}++,${s2} */
23121 +  {
23122 +    UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, "xor.2-d-indirect-with-post-increment-2-s1-indirect-with-post-increment-2", "xor.2", 32,
23123 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23124 +  },
23125 +/* xor.2 ${d-i4-2}(${d-An})++,(${s1-An})${s1-i4-2}++,${s2} */
23126 +  {
23127 +    UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, "xor.2-d-indirect-with-pre-increment-2-s1-indirect-with-post-increment-2", "xor.2", 32,
23128 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23129 +  },
23130 +/* xor.2 ${d-direct-addr},${s1-i4-2}(${s1-An})++,${s2} */
23131 +  {
23132 +    UBICOM32_INSN_XOR_2_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_2, "xor.2-d-direct-s1-indirect-with-pre-increment-2", "xor.2", 32,
23133 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23134 +  },
23135 +/* xor.2 #${d-imm8},${s1-i4-2}(${s1-An})++,${s2} */
23136 +  {
23137 +    UBICOM32_INSN_XOR_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, "xor.2-d-immediate-2-s1-indirect-with-pre-increment-2", "xor.2", 32,
23138 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23139 +  },
23140 +/* xor.2 (${d-An},${d-r}),${s1-i4-2}(${s1-An})++,${s2} */
23141 +  {
23142 +    UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, "xor.2-d-indirect-with-index-2-s1-indirect-with-pre-increment-2", "xor.2", 32,
23143 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23144 +  },
23145 +/* xor.2 ${d-imm7-2}(${d-An}),${s1-i4-2}(${s1-An})++,${s2} */
23146 +  {
23147 +    UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, "xor.2-d-indirect-with-offset-2-s1-indirect-with-pre-increment-2", "xor.2", 32,
23148 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23149 +  },
23150 +/* xor.2 (${d-An}),${s1-i4-2}(${s1-An})++,${s2} */
23151 +  {
23152 +    UBICOM32_INSN_XOR_2_D_INDIRECT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, "xor.2-d-indirect-2-s1-indirect-with-pre-increment-2", "xor.2", 32,
23153 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23154 +  },
23155 +/* xor.2 (${d-An})${d-i4-2}++,${s1-i4-2}(${s1-An})++,${s2} */
23156 +  {
23157 +    UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, "xor.2-d-indirect-with-post-increment-2-s1-indirect-with-pre-increment-2", "xor.2", 32,
23158 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23159 +  },
23160 +/* xor.2 ${d-i4-2}(${d-An})++,${s1-i4-2}(${s1-An})++,${s2} */
23161 +  {
23162 +    UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, "xor.2-d-indirect-with-pre-increment-2-s1-indirect-with-pre-increment-2", "xor.2", 32,
23163 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23164 +  },
23165 +/* or.4 ${d-direct-addr},${s1-direct-addr},${s2} */
23166 +  {
23167 +    UBICOM32_INSN_OR_4_D_DIRECT_S1_DIRECT, "or.4-d-direct-s1-direct", "or.4", 32,
23168 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23169 +  },
23170 +/* or.4 #${d-imm8},${s1-direct-addr},${s2} */
23171 +  {
23172 +    UBICOM32_INSN_OR_4_D_IMMEDIATE_4_S1_DIRECT, "or.4-d-immediate-4-s1-direct", "or.4", 32,
23173 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23174 +  },
23175 +/* or.4 (${d-An},${d-r}),${s1-direct-addr},${s2} */
23176 +  {
23177 +    UBICOM32_INSN_OR_4_D_INDIRECT_WITH_INDEX_4_S1_DIRECT, "or.4-d-indirect-with-index-4-s1-direct", "or.4", 32,
23178 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23179 +  },
23180 +/* or.4 ${d-imm7-4}(${d-An}),${s1-direct-addr},${s2} */
23181 +  {
23182 +    UBICOM32_INSN_OR_4_D_INDIRECT_WITH_OFFSET_4_S1_DIRECT, "or.4-d-indirect-with-offset-4-s1-direct", "or.4", 32,
23183 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23184 +  },
23185 +/* or.4 (${d-An}),${s1-direct-addr},${s2} */
23186 +  {
23187 +    UBICOM32_INSN_OR_4_D_INDIRECT_4_S1_DIRECT, "or.4-d-indirect-4-s1-direct", "or.4", 32,
23188 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23189 +  },
23190 +/* or.4 (${d-An})${d-i4-4}++,${s1-direct-addr},${s2} */
23191 +  {
23192 +    UBICOM32_INSN_OR_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_DIRECT, "or.4-d-indirect-with-post-increment-4-s1-direct", "or.4", 32,
23193 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23194 +  },
23195 +/* or.4 ${d-i4-4}(${d-An})++,${s1-direct-addr},${s2} */
23196 +  {
23197 +    UBICOM32_INSN_OR_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_DIRECT, "or.4-d-indirect-with-pre-increment-4-s1-direct", "or.4", 32,
23198 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23199 +  },
23200 +/* or.4 ${d-direct-addr},#${s1-imm8},${s2} */
23201 +  {
23202 +    UBICOM32_INSN_OR_4_D_DIRECT_S1_IMMEDIATE, "or.4-d-direct-s1-immediate", "or.4", 32,
23203 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23204 +  },
23205 +/* or.4 #${d-imm8},#${s1-imm8},${s2} */
23206 +  {
23207 +    UBICOM32_INSN_OR_4_D_IMMEDIATE_4_S1_IMMEDIATE, "or.4-d-immediate-4-s1-immediate", "or.4", 32,
23208 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23209 +  },
23210 +/* or.4 (${d-An},${d-r}),#${s1-imm8},${s2} */
23211 +  {
23212 +    UBICOM32_INSN_OR_4_D_INDIRECT_WITH_INDEX_4_S1_IMMEDIATE, "or.4-d-indirect-with-index-4-s1-immediate", "or.4", 32,
23213 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23214 +  },
23215 +/* or.4 ${d-imm7-4}(${d-An}),#${s1-imm8},${s2} */
23216 +  {
23217 +    UBICOM32_INSN_OR_4_D_INDIRECT_WITH_OFFSET_4_S1_IMMEDIATE, "or.4-d-indirect-with-offset-4-s1-immediate", "or.4", 32,
23218 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23219 +  },
23220 +/* or.4 (${d-An}),#${s1-imm8},${s2} */
23221 +  {
23222 +    UBICOM32_INSN_OR_4_D_INDIRECT_4_S1_IMMEDIATE, "or.4-d-indirect-4-s1-immediate", "or.4", 32,
23223 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23224 +  },
23225 +/* or.4 (${d-An})${d-i4-4}++,#${s1-imm8},${s2} */
23226 +  {
23227 +    UBICOM32_INSN_OR_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_IMMEDIATE, "or.4-d-indirect-with-post-increment-4-s1-immediate", "or.4", 32,
23228 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23229 +  },
23230 +/* or.4 ${d-i4-4}(${d-An})++,#${s1-imm8},${s2} */
23231 +  {
23232 +    UBICOM32_INSN_OR_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_IMMEDIATE, "or.4-d-indirect-with-pre-increment-4-s1-immediate", "or.4", 32,
23233 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23234 +  },
23235 +/* or.4 ${d-direct-addr},(${s1-An},${s1-r}),${s2} */
23236 +  {
23237 +    UBICOM32_INSN_OR_4_D_DIRECT_S1_INDIRECT_WITH_INDEX_4, "or.4-d-direct-s1-indirect-with-index-4", "or.4", 32,
23238 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23239 +  },
23240 +/* or.4 #${d-imm8},(${s1-An},${s1-r}),${s2} */
23241 +  {
23242 +    UBICOM32_INSN_OR_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_INDEX_4, "or.4-d-immediate-4-s1-indirect-with-index-4", "or.4", 32,
23243 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23244 +  },
23245 +/* or.4 (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */
23246 +  {
23247 +    UBICOM32_INSN_OR_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_INDEX_4, "or.4-d-indirect-with-index-4-s1-indirect-with-index-4", "or.4", 32,
23248 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23249 +  },
23250 +/* or.4 ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}),${s2} */
23251 +  {
23252 +    UBICOM32_INSN_OR_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_INDEX_4, "or.4-d-indirect-with-offset-4-s1-indirect-with-index-4", "or.4", 32,
23253 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23254 +  },
23255 +/* or.4 (${d-An}),(${s1-An},${s1-r}),${s2} */
23256 +  {
23257 +    UBICOM32_INSN_OR_4_D_INDIRECT_4_S1_INDIRECT_WITH_INDEX_4, "or.4-d-indirect-4-s1-indirect-with-index-4", "or.4", 32,
23258 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23259 +  },
23260 +/* or.4 (${d-An})${d-i4-4}++,(${s1-An},${s1-r}),${s2} */
23261 +  {
23262 +    UBICOM32_INSN_OR_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, "or.4-d-indirect-with-post-increment-4-s1-indirect-with-index-4", "or.4", 32,
23263 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23264 +  },
23265 +/* or.4 ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}),${s2} */
23266 +  {
23267 +    UBICOM32_INSN_OR_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, "or.4-d-indirect-with-pre-increment-4-s1-indirect-with-index-4", "or.4", 32,
23268 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23269 +  },
23270 +/* or.4 ${d-direct-addr},${s1-imm7-4}(${s1-An}),${s2} */
23271 +  {
23272 +    UBICOM32_INSN_OR_4_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4, "or.4-d-direct-s1-indirect-with-offset-4", "or.4", 32,
23273 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23274 +  },
23275 +/* or.4 #${d-imm8},${s1-imm7-4}(${s1-An}),${s2} */
23276 +  {
23277 +    UBICOM32_INSN_OR_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_OFFSET_4, "or.4-d-immediate-4-s1-indirect-with-offset-4", "or.4", 32,
23278 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23279 +  },
23280 +/* or.4 (${d-An},${d-r}),${s1-imm7-4}(${s1-An}),${s2} */
23281 +  {
23282 +    UBICOM32_INSN_OR_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_OFFSET_4, "or.4-d-indirect-with-index-4-s1-indirect-with-offset-4", "or.4", 32,
23283 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23284 +  },
23285 +/* or.4 ${d-imm7-4}(${d-An}),${s1-imm7-4}(${s1-An}),${s2} */
23286 +  {
23287 +    UBICOM32_INSN_OR_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_OFFSET_4, "or.4-d-indirect-with-offset-4-s1-indirect-with-offset-4", "or.4", 32,
23288 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23289 +  },
23290 +/* or.4 (${d-An}),${s1-imm7-4}(${s1-An}),${s2} */
23291 +  {
23292 +    UBICOM32_INSN_OR_4_D_INDIRECT_4_S1_INDIRECT_WITH_OFFSET_4, "or.4-d-indirect-4-s1-indirect-with-offset-4", "or.4", 32,
23293 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23294 +  },
23295 +/* or.4 (${d-An})${d-i4-4}++,${s1-imm7-4}(${s1-An}),${s2} */
23296 +  {
23297 +    UBICOM32_INSN_OR_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, "or.4-d-indirect-with-post-increment-4-s1-indirect-with-offset-4", "or.4", 32,
23298 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23299 +  },
23300 +/* or.4 ${d-i4-4}(${d-An})++,${s1-imm7-4}(${s1-An}),${s2} */
23301 +  {
23302 +    UBICOM32_INSN_OR_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, "or.4-d-indirect-with-pre-increment-4-s1-indirect-with-offset-4", "or.4", 32,
23303 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23304 +  },
23305 +/* or.4 ${d-direct-addr},(${s1-An}),${s2} */
23306 +  {
23307 +    UBICOM32_INSN_OR_4_D_DIRECT_S1_INDIRECT_4, "or.4-d-direct-s1-indirect-4", "or.4", 32,
23308 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23309 +  },
23310 +/* or.4 #${d-imm8},(${s1-An}),${s2} */
23311 +  {
23312 +    UBICOM32_INSN_OR_4_D_IMMEDIATE_4_S1_INDIRECT_4, "or.4-d-immediate-4-s1-indirect-4", "or.4", 32,
23313 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23314 +  },
23315 +/* or.4 (${d-An},${d-r}),(${s1-An}),${s2} */
23316 +  {
23317 +    UBICOM32_INSN_OR_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_4, "or.4-d-indirect-with-index-4-s1-indirect-4", "or.4", 32,
23318 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23319 +  },
23320 +/* or.4 ${d-imm7-4}(${d-An}),(${s1-An}),${s2} */
23321 +  {
23322 +    UBICOM32_INSN_OR_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_4, "or.4-d-indirect-with-offset-4-s1-indirect-4", "or.4", 32,
23323 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23324 +  },
23325 +/* or.4 (${d-An}),(${s1-An}),${s2} */
23326 +  {
23327 +    UBICOM32_INSN_OR_4_D_INDIRECT_4_S1_INDIRECT_4, "or.4-d-indirect-4-s1-indirect-4", "or.4", 32,
23328 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23329 +  },
23330 +/* or.4 (${d-An})${d-i4-4}++,(${s1-An}),${s2} */
23331 +  {
23332 +    UBICOM32_INSN_OR_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_4, "or.4-d-indirect-with-post-increment-4-s1-indirect-4", "or.4", 32,
23333 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23334 +  },
23335 +/* or.4 ${d-i4-4}(${d-An})++,(${s1-An}),${s2} */
23336 +  {
23337 +    UBICOM32_INSN_OR_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_4, "or.4-d-indirect-with-pre-increment-4-s1-indirect-4", "or.4", 32,
23338 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23339 +  },
23340 +/* or.4 ${d-direct-addr},(${s1-An})${s1-i4-4}++,${s2} */
23341 +  {
23342 +    UBICOM32_INSN_OR_4_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4, "or.4-d-direct-s1-indirect-with-post-increment-4", "or.4", 32,
23343 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23344 +  },
23345 +/* or.4 #${d-imm8},(${s1-An})${s1-i4-4}++,${s2} */
23346 +  {
23347 +    UBICOM32_INSN_OR_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "or.4-d-immediate-4-s1-indirect-with-post-increment-4", "or.4", 32,
23348 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23349 +  },
23350 +/* or.4 (${d-An},${d-r}),(${s1-An})${s1-i4-4}++,${s2} */
23351 +  {
23352 +    UBICOM32_INSN_OR_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "or.4-d-indirect-with-index-4-s1-indirect-with-post-increment-4", "or.4", 32,
23353 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23354 +  },
23355 +/* or.4 ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-4}++,${s2} */
23356 +  {
23357 +    UBICOM32_INSN_OR_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "or.4-d-indirect-with-offset-4-s1-indirect-with-post-increment-4", "or.4", 32,
23358 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23359 +  },
23360 +/* or.4 (${d-An}),(${s1-An})${s1-i4-4}++,${s2} */
23361 +  {
23362 +    UBICOM32_INSN_OR_4_D_INDIRECT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "or.4-d-indirect-4-s1-indirect-with-post-increment-4", "or.4", 32,
23363 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23364 +  },
23365 +/* or.4 (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-4}++,${s2} */
23366 +  {
23367 +    UBICOM32_INSN_OR_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "or.4-d-indirect-with-post-increment-4-s1-indirect-with-post-increment-4", "or.4", 32,
23368 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23369 +  },
23370 +/* or.4 ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-4}++,${s2} */
23371 +  {
23372 +    UBICOM32_INSN_OR_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "or.4-d-indirect-with-pre-increment-4-s1-indirect-with-post-increment-4", "or.4", 32,
23373 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23374 +  },
23375 +/* or.4 ${d-direct-addr},${s1-i4-4}(${s1-An})++,${s2} */
23376 +  {
23377 +    UBICOM32_INSN_OR_4_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4, "or.4-d-direct-s1-indirect-with-pre-increment-4", "or.4", 32,
23378 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23379 +  },
23380 +/* or.4 #${d-imm8},${s1-i4-4}(${s1-An})++,${s2} */
23381 +  {
23382 +    UBICOM32_INSN_OR_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "or.4-d-immediate-4-s1-indirect-with-pre-increment-4", "or.4", 32,
23383 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23384 +  },
23385 +/* or.4 (${d-An},${d-r}),${s1-i4-4}(${s1-An})++,${s2} */
23386 +  {
23387 +    UBICOM32_INSN_OR_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "or.4-d-indirect-with-index-4-s1-indirect-with-pre-increment-4", "or.4", 32,
23388 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23389 +  },
23390 +/* or.4 ${d-imm7-4}(${d-An}),${s1-i4-4}(${s1-An})++,${s2} */
23391 +  {
23392 +    UBICOM32_INSN_OR_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "or.4-d-indirect-with-offset-4-s1-indirect-with-pre-increment-4", "or.4", 32,
23393 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23394 +  },
23395 +/* or.4 (${d-An}),${s1-i4-4}(${s1-An})++,${s2} */
23396 +  {
23397 +    UBICOM32_INSN_OR_4_D_INDIRECT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "or.4-d-indirect-4-s1-indirect-with-pre-increment-4", "or.4", 32,
23398 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23399 +  },
23400 +/* or.4 (${d-An})${d-i4-4}++,${s1-i4-4}(${s1-An})++,${s2} */
23401 +  {
23402 +    UBICOM32_INSN_OR_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "or.4-d-indirect-with-post-increment-4-s1-indirect-with-pre-increment-4", "or.4", 32,
23403 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23404 +  },
23405 +/* or.4 ${d-i4-4}(${d-An})++,${s1-i4-4}(${s1-An})++,${s2} */
23406 +  {
23407 +    UBICOM32_INSN_OR_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "or.4-d-indirect-with-pre-increment-4-s1-indirect-with-pre-increment-4", "or.4", 32,
23408 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23409 +  },
23410 +/* or.2 ${d-direct-addr},${s1-direct-addr},${s2} */
23411 +  {
23412 +    UBICOM32_INSN_OR_2_D_DIRECT_S1_DIRECT, "or.2-d-direct-s1-direct", "or.2", 32,
23413 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23414 +  },
23415 +/* or.2 #${d-imm8},${s1-direct-addr},${s2} */
23416 +  {
23417 +    UBICOM32_INSN_OR_2_D_IMMEDIATE_2_S1_DIRECT, "or.2-d-immediate-2-s1-direct", "or.2", 32,
23418 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23419 +  },
23420 +/* or.2 (${d-An},${d-r}),${s1-direct-addr},${s2} */
23421 +  {
23422 +    UBICOM32_INSN_OR_2_D_INDIRECT_WITH_INDEX_2_S1_DIRECT, "or.2-d-indirect-with-index-2-s1-direct", "or.2", 32,
23423 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23424 +  },
23425 +/* or.2 ${d-imm7-2}(${d-An}),${s1-direct-addr},${s2} */
23426 +  {
23427 +    UBICOM32_INSN_OR_2_D_INDIRECT_WITH_OFFSET_2_S1_DIRECT, "or.2-d-indirect-with-offset-2-s1-direct", "or.2", 32,
23428 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23429 +  },
23430 +/* or.2 (${d-An}),${s1-direct-addr},${s2} */
23431 +  {
23432 +    UBICOM32_INSN_OR_2_D_INDIRECT_2_S1_DIRECT, "or.2-d-indirect-2-s1-direct", "or.2", 32,
23433 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23434 +  },
23435 +/* or.2 (${d-An})${d-i4-2}++,${s1-direct-addr},${s2} */
23436 +  {
23437 +    UBICOM32_INSN_OR_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_DIRECT, "or.2-d-indirect-with-post-increment-2-s1-direct", "or.2", 32,
23438 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23439 +  },
23440 +/* or.2 ${d-i4-2}(${d-An})++,${s1-direct-addr},${s2} */
23441 +  {
23442 +    UBICOM32_INSN_OR_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_DIRECT, "or.2-d-indirect-with-pre-increment-2-s1-direct", "or.2", 32,
23443 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23444 +  },
23445 +/* or.2 ${d-direct-addr},#${s1-imm8},${s2} */
23446 +  {
23447 +    UBICOM32_INSN_OR_2_D_DIRECT_S1_IMMEDIATE, "or.2-d-direct-s1-immediate", "or.2", 32,
23448 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23449 +  },
23450 +/* or.2 #${d-imm8},#${s1-imm8},${s2} */
23451 +  {
23452 +    UBICOM32_INSN_OR_2_D_IMMEDIATE_2_S1_IMMEDIATE, "or.2-d-immediate-2-s1-immediate", "or.2", 32,
23453 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23454 +  },
23455 +/* or.2 (${d-An},${d-r}),#${s1-imm8},${s2} */
23456 +  {
23457 +    UBICOM32_INSN_OR_2_D_INDIRECT_WITH_INDEX_2_S1_IMMEDIATE, "or.2-d-indirect-with-index-2-s1-immediate", "or.2", 32,
23458 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23459 +  },
23460 +/* or.2 ${d-imm7-2}(${d-An}),#${s1-imm8},${s2} */
23461 +  {
23462 +    UBICOM32_INSN_OR_2_D_INDIRECT_WITH_OFFSET_2_S1_IMMEDIATE, "or.2-d-indirect-with-offset-2-s1-immediate", "or.2", 32,
23463 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23464 +  },
23465 +/* or.2 (${d-An}),#${s1-imm8},${s2} */
23466 +  {
23467 +    UBICOM32_INSN_OR_2_D_INDIRECT_2_S1_IMMEDIATE, "or.2-d-indirect-2-s1-immediate", "or.2", 32,
23468 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23469 +  },
23470 +/* or.2 (${d-An})${d-i4-2}++,#${s1-imm8},${s2} */
23471 +  {
23472 +    UBICOM32_INSN_OR_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_IMMEDIATE, "or.2-d-indirect-with-post-increment-2-s1-immediate", "or.2", 32,
23473 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23474 +  },
23475 +/* or.2 ${d-i4-2}(${d-An})++,#${s1-imm8},${s2} */
23476 +  {
23477 +    UBICOM32_INSN_OR_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_IMMEDIATE, "or.2-d-indirect-with-pre-increment-2-s1-immediate", "or.2", 32,
23478 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23479 +  },
23480 +/* or.2 ${d-direct-addr},(${s1-An},${s1-r}),${s2} */
23481 +  {
23482 +    UBICOM32_INSN_OR_2_D_DIRECT_S1_INDIRECT_WITH_INDEX_2, "or.2-d-direct-s1-indirect-with-index-2", "or.2", 32,
23483 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23484 +  },
23485 +/* or.2 #${d-imm8},(${s1-An},${s1-r}),${s2} */
23486 +  {
23487 +    UBICOM32_INSN_OR_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_INDEX_2, "or.2-d-immediate-2-s1-indirect-with-index-2", "or.2", 32,
23488 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23489 +  },
23490 +/* or.2 (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */
23491 +  {
23492 +    UBICOM32_INSN_OR_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_INDEX_2, "or.2-d-indirect-with-index-2-s1-indirect-with-index-2", "or.2", 32,
23493 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23494 +  },
23495 +/* or.2 ${d-imm7-2}(${d-An}),(${s1-An},${s1-r}),${s2} */
23496 +  {
23497 +    UBICOM32_INSN_OR_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_INDEX_2, "or.2-d-indirect-with-offset-2-s1-indirect-with-index-2", "or.2", 32,
23498 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23499 +  },
23500 +/* or.2 (${d-An}),(${s1-An},${s1-r}),${s2} */
23501 +  {
23502 +    UBICOM32_INSN_OR_2_D_INDIRECT_2_S1_INDIRECT_WITH_INDEX_2, "or.2-d-indirect-2-s1-indirect-with-index-2", "or.2", 32,
23503 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23504 +  },
23505 +/* or.2 (${d-An})${d-i4-2}++,(${s1-An},${s1-r}),${s2} */
23506 +  {
23507 +    UBICOM32_INSN_OR_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_INDEX_2, "or.2-d-indirect-with-post-increment-2-s1-indirect-with-index-2", "or.2", 32,
23508 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23509 +  },
23510 +/* or.2 ${d-i4-2}(${d-An})++,(${s1-An},${s1-r}),${s2} */
23511 +  {
23512 +    UBICOM32_INSN_OR_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_INDEX_2, "or.2-d-indirect-with-pre-increment-2-s1-indirect-with-index-2", "or.2", 32,
23513 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23514 +  },
23515 +/* or.2 ${d-direct-addr},${s1-imm7-2}(${s1-An}),${s2} */
23516 +  {
23517 +    UBICOM32_INSN_OR_2_D_DIRECT_S1_INDIRECT_WITH_OFFSET_2, "or.2-d-direct-s1-indirect-with-offset-2", "or.2", 32,
23518 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23519 +  },
23520 +/* or.2 #${d-imm8},${s1-imm7-2}(${s1-An}),${s2} */
23521 +  {
23522 +    UBICOM32_INSN_OR_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_OFFSET_2, "or.2-d-immediate-2-s1-indirect-with-offset-2", "or.2", 32,
23523 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23524 +  },
23525 +/* or.2 (${d-An},${d-r}),${s1-imm7-2}(${s1-An}),${s2} */
23526 +  {
23527 +    UBICOM32_INSN_OR_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_OFFSET_2, "or.2-d-indirect-with-index-2-s1-indirect-with-offset-2", "or.2", 32,
23528 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23529 +  },
23530 +/* or.2 ${d-imm7-2}(${d-An}),${s1-imm7-2}(${s1-An}),${s2} */
23531 +  {
23532 +    UBICOM32_INSN_OR_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_OFFSET_2, "or.2-d-indirect-with-offset-2-s1-indirect-with-offset-2", "or.2", 32,
23533 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23534 +  },
23535 +/* or.2 (${d-An}),${s1-imm7-2}(${s1-An}),${s2} */
23536 +  {
23537 +    UBICOM32_INSN_OR_2_D_INDIRECT_2_S1_INDIRECT_WITH_OFFSET_2, "or.2-d-indirect-2-s1-indirect-with-offset-2", "or.2", 32,
23538 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23539 +  },
23540 +/* or.2 (${d-An})${d-i4-2}++,${s1-imm7-2}(${s1-An}),${s2} */
23541 +  {
23542 +    UBICOM32_INSN_OR_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_2, "or.2-d-indirect-with-post-increment-2-s1-indirect-with-offset-2", "or.2", 32,
23543 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23544 +  },
23545 +/* or.2 ${d-i4-2}(${d-An})++,${s1-imm7-2}(${s1-An}),${s2} */
23546 +  {
23547 +    UBICOM32_INSN_OR_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_2, "or.2-d-indirect-with-pre-increment-2-s1-indirect-with-offset-2", "or.2", 32,
23548 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23549 +  },
23550 +/* or.2 ${d-direct-addr},(${s1-An}),${s2} */
23551 +  {
23552 +    UBICOM32_INSN_OR_2_D_DIRECT_S1_INDIRECT_2, "or.2-d-direct-s1-indirect-2", "or.2", 32,
23553 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23554 +  },
23555 +/* or.2 #${d-imm8},(${s1-An}),${s2} */
23556 +  {
23557 +    UBICOM32_INSN_OR_2_D_IMMEDIATE_2_S1_INDIRECT_2, "or.2-d-immediate-2-s1-indirect-2", "or.2", 32,
23558 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23559 +  },
23560 +/* or.2 (${d-An},${d-r}),(${s1-An}),${s2} */
23561 +  {
23562 +    UBICOM32_INSN_OR_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_2, "or.2-d-indirect-with-index-2-s1-indirect-2", "or.2", 32,
23563 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23564 +  },
23565 +/* or.2 ${d-imm7-2}(${d-An}),(${s1-An}),${s2} */
23566 +  {
23567 +    UBICOM32_INSN_OR_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_2, "or.2-d-indirect-with-offset-2-s1-indirect-2", "or.2", 32,
23568 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23569 +  },
23570 +/* or.2 (${d-An}),(${s1-An}),${s2} */
23571 +  {
23572 +    UBICOM32_INSN_OR_2_D_INDIRECT_2_S1_INDIRECT_2, "or.2-d-indirect-2-s1-indirect-2", "or.2", 32,
23573 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23574 +  },
23575 +/* or.2 (${d-An})${d-i4-2}++,(${s1-An}),${s2} */
23576 +  {
23577 +    UBICOM32_INSN_OR_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_2, "or.2-d-indirect-with-post-increment-2-s1-indirect-2", "or.2", 32,
23578 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23579 +  },
23580 +/* or.2 ${d-i4-2}(${d-An})++,(${s1-An}),${s2} */
23581 +  {
23582 +    UBICOM32_INSN_OR_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_2, "or.2-d-indirect-with-pre-increment-2-s1-indirect-2", "or.2", 32,
23583 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23584 +  },
23585 +/* or.2 ${d-direct-addr},(${s1-An})${s1-i4-2}++,${s2} */
23586 +  {
23587 +    UBICOM32_INSN_OR_2_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_2, "or.2-d-direct-s1-indirect-with-post-increment-2", "or.2", 32,
23588 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23589 +  },
23590 +/* or.2 #${d-imm8},(${s1-An})${s1-i4-2}++,${s2} */
23591 +  {
23592 +    UBICOM32_INSN_OR_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_POST_INCREMENT_2, "or.2-d-immediate-2-s1-indirect-with-post-increment-2", "or.2", 32,
23593 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23594 +  },
23595 +/* or.2 (${d-An},${d-r}),(${s1-An})${s1-i4-2}++,${s2} */
23596 +  {
23597 +    UBICOM32_INSN_OR_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_POST_INCREMENT_2, "or.2-d-indirect-with-index-2-s1-indirect-with-post-increment-2", "or.2", 32,
23598 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23599 +  },
23600 +/* or.2 ${d-imm7-2}(${d-An}),(${s1-An})${s1-i4-2}++,${s2} */
23601 +  {
23602 +    UBICOM32_INSN_OR_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_POST_INCREMENT_2, "or.2-d-indirect-with-offset-2-s1-indirect-with-post-increment-2", "or.2", 32,
23603 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23604 +  },
23605 +/* or.2 (${d-An}),(${s1-An})${s1-i4-2}++,${s2} */
23606 +  {
23607 +    UBICOM32_INSN_OR_2_D_INDIRECT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, "or.2-d-indirect-2-s1-indirect-with-post-increment-2", "or.2", 32,
23608 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23609 +  },
23610 +/* or.2 (${d-An})${d-i4-2}++,(${s1-An})${s1-i4-2}++,${s2} */
23611 +  {
23612 +    UBICOM32_INSN_OR_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, "or.2-d-indirect-with-post-increment-2-s1-indirect-with-post-increment-2", "or.2", 32,
23613 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23614 +  },
23615 +/* or.2 ${d-i4-2}(${d-An})++,(${s1-An})${s1-i4-2}++,${s2} */
23616 +  {
23617 +    UBICOM32_INSN_OR_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, "or.2-d-indirect-with-pre-increment-2-s1-indirect-with-post-increment-2", "or.2", 32,
23618 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23619 +  },
23620 +/* or.2 ${d-direct-addr},${s1-i4-2}(${s1-An})++,${s2} */
23621 +  {
23622 +    UBICOM32_INSN_OR_2_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_2, "or.2-d-direct-s1-indirect-with-pre-increment-2", "or.2", 32,
23623 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23624 +  },
23625 +/* or.2 #${d-imm8},${s1-i4-2}(${s1-An})++,${s2} */
23626 +  {
23627 +    UBICOM32_INSN_OR_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, "or.2-d-immediate-2-s1-indirect-with-pre-increment-2", "or.2", 32,
23628 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23629 +  },
23630 +/* or.2 (${d-An},${d-r}),${s1-i4-2}(${s1-An})++,${s2} */
23631 +  {
23632 +    UBICOM32_INSN_OR_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, "or.2-d-indirect-with-index-2-s1-indirect-with-pre-increment-2", "or.2", 32,
23633 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23634 +  },
23635 +/* or.2 ${d-imm7-2}(${d-An}),${s1-i4-2}(${s1-An})++,${s2} */
23636 +  {
23637 +    UBICOM32_INSN_OR_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, "or.2-d-indirect-with-offset-2-s1-indirect-with-pre-increment-2", "or.2", 32,
23638 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23639 +  },
23640 +/* or.2 (${d-An}),${s1-i4-2}(${s1-An})++,${s2} */
23641 +  {
23642 +    UBICOM32_INSN_OR_2_D_INDIRECT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, "or.2-d-indirect-2-s1-indirect-with-pre-increment-2", "or.2", 32,
23643 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23644 +  },
23645 +/* or.2 (${d-An})${d-i4-2}++,${s1-i4-2}(${s1-An})++,${s2} */
23646 +  {
23647 +    UBICOM32_INSN_OR_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, "or.2-d-indirect-with-post-increment-2-s1-indirect-with-pre-increment-2", "or.2", 32,
23648 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23649 +  },
23650 +/* or.2 ${d-i4-2}(${d-An})++,${s1-i4-2}(${s1-An})++,${s2} */
23651 +  {
23652 +    UBICOM32_INSN_OR_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, "or.2-d-indirect-with-pre-increment-2-s1-indirect-with-pre-increment-2", "or.2", 32,
23653 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23654 +  },
23655 +/* and.4 ${d-direct-addr},${s1-direct-addr},${s2} */
23656 +  {
23657 +    UBICOM32_INSN_AND_4_D_DIRECT_S1_DIRECT, "and.4-d-direct-s1-direct", "and.4", 32,
23658 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23659 +  },
23660 +/* and.4 #${d-imm8},${s1-direct-addr},${s2} */
23661 +  {
23662 +    UBICOM32_INSN_AND_4_D_IMMEDIATE_4_S1_DIRECT, "and.4-d-immediate-4-s1-direct", "and.4", 32,
23663 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23664 +  },
23665 +/* and.4 (${d-An},${d-r}),${s1-direct-addr},${s2} */
23666 +  {
23667 +    UBICOM32_INSN_AND_4_D_INDIRECT_WITH_INDEX_4_S1_DIRECT, "and.4-d-indirect-with-index-4-s1-direct", "and.4", 32,
23668 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23669 +  },
23670 +/* and.4 ${d-imm7-4}(${d-An}),${s1-direct-addr},${s2} */
23671 +  {
23672 +    UBICOM32_INSN_AND_4_D_INDIRECT_WITH_OFFSET_4_S1_DIRECT, "and.4-d-indirect-with-offset-4-s1-direct", "and.4", 32,
23673 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23674 +  },
23675 +/* and.4 (${d-An}),${s1-direct-addr},${s2} */
23676 +  {
23677 +    UBICOM32_INSN_AND_4_D_INDIRECT_4_S1_DIRECT, "and.4-d-indirect-4-s1-direct", "and.4", 32,
23678 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23679 +  },
23680 +/* and.4 (${d-An})${d-i4-4}++,${s1-direct-addr},${s2} */
23681 +  {
23682 +    UBICOM32_INSN_AND_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_DIRECT, "and.4-d-indirect-with-post-increment-4-s1-direct", "and.4", 32,
23683 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23684 +  },
23685 +/* and.4 ${d-i4-4}(${d-An})++,${s1-direct-addr},${s2} */
23686 +  {
23687 +    UBICOM32_INSN_AND_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_DIRECT, "and.4-d-indirect-with-pre-increment-4-s1-direct", "and.4", 32,
23688 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23689 +  },
23690 +/* and.4 ${d-direct-addr},#${s1-imm8},${s2} */
23691 +  {
23692 +    UBICOM32_INSN_AND_4_D_DIRECT_S1_IMMEDIATE, "and.4-d-direct-s1-immediate", "and.4", 32,
23693 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23694 +  },
23695 +/* and.4 #${d-imm8},#${s1-imm8},${s2} */
23696 +  {
23697 +    UBICOM32_INSN_AND_4_D_IMMEDIATE_4_S1_IMMEDIATE, "and.4-d-immediate-4-s1-immediate", "and.4", 32,
23698 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23699 +  },
23700 +/* and.4 (${d-An},${d-r}),#${s1-imm8},${s2} */
23701 +  {
23702 +    UBICOM32_INSN_AND_4_D_INDIRECT_WITH_INDEX_4_S1_IMMEDIATE, "and.4-d-indirect-with-index-4-s1-immediate", "and.4", 32,
23703 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23704 +  },
23705 +/* and.4 ${d-imm7-4}(${d-An}),#${s1-imm8},${s2} */
23706 +  {
23707 +    UBICOM32_INSN_AND_4_D_INDIRECT_WITH_OFFSET_4_S1_IMMEDIATE, "and.4-d-indirect-with-offset-4-s1-immediate", "and.4", 32,
23708 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23709 +  },
23710 +/* and.4 (${d-An}),#${s1-imm8},${s2} */
23711 +  {
23712 +    UBICOM32_INSN_AND_4_D_INDIRECT_4_S1_IMMEDIATE, "and.4-d-indirect-4-s1-immediate", "and.4", 32,
23713 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23714 +  },
23715 +/* and.4 (${d-An})${d-i4-4}++,#${s1-imm8},${s2} */
23716 +  {
23717 +    UBICOM32_INSN_AND_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_IMMEDIATE, "and.4-d-indirect-with-post-increment-4-s1-immediate", "and.4", 32,
23718 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23719 +  },
23720 +/* and.4 ${d-i4-4}(${d-An})++,#${s1-imm8},${s2} */
23721 +  {
23722 +    UBICOM32_INSN_AND_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_IMMEDIATE, "and.4-d-indirect-with-pre-increment-4-s1-immediate", "and.4", 32,
23723 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23724 +  },
23725 +/* and.4 ${d-direct-addr},(${s1-An},${s1-r}),${s2} */
23726 +  {
23727 +    UBICOM32_INSN_AND_4_D_DIRECT_S1_INDIRECT_WITH_INDEX_4, "and.4-d-direct-s1-indirect-with-index-4", "and.4", 32,
23728 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23729 +  },
23730 +/* and.4 #${d-imm8},(${s1-An},${s1-r}),${s2} */
23731 +  {
23732 +    UBICOM32_INSN_AND_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_INDEX_4, "and.4-d-immediate-4-s1-indirect-with-index-4", "and.4", 32,
23733 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23734 +  },
23735 +/* and.4 (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */
23736 +  {
23737 +    UBICOM32_INSN_AND_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_INDEX_4, "and.4-d-indirect-with-index-4-s1-indirect-with-index-4", "and.4", 32,
23738 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23739 +  },
23740 +/* and.4 ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}),${s2} */
23741 +  {
23742 +    UBICOM32_INSN_AND_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_INDEX_4, "and.4-d-indirect-with-offset-4-s1-indirect-with-index-4", "and.4", 32,
23743 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23744 +  },
23745 +/* and.4 (${d-An}),(${s1-An},${s1-r}),${s2} */
23746 +  {
23747 +    UBICOM32_INSN_AND_4_D_INDIRECT_4_S1_INDIRECT_WITH_INDEX_4, "and.4-d-indirect-4-s1-indirect-with-index-4", "and.4", 32,
23748 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23749 +  },
23750 +/* and.4 (${d-An})${d-i4-4}++,(${s1-An},${s1-r}),${s2} */
23751 +  {
23752 +    UBICOM32_INSN_AND_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, "and.4-d-indirect-with-post-increment-4-s1-indirect-with-index-4", "and.4", 32,
23753 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23754 +  },
23755 +/* and.4 ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}),${s2} */
23756 +  {
23757 +    UBICOM32_INSN_AND_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, "and.4-d-indirect-with-pre-increment-4-s1-indirect-with-index-4", "and.4", 32,
23758 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23759 +  },
23760 +/* and.4 ${d-direct-addr},${s1-imm7-4}(${s1-An}),${s2} */
23761 +  {
23762 +    UBICOM32_INSN_AND_4_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4, "and.4-d-direct-s1-indirect-with-offset-4", "and.4", 32,
23763 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23764 +  },
23765 +/* and.4 #${d-imm8},${s1-imm7-4}(${s1-An}),${s2} */
23766 +  {
23767 +    UBICOM32_INSN_AND_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_OFFSET_4, "and.4-d-immediate-4-s1-indirect-with-offset-4", "and.4", 32,
23768 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23769 +  },
23770 +/* and.4 (${d-An},${d-r}),${s1-imm7-4}(${s1-An}),${s2} */
23771 +  {
23772 +    UBICOM32_INSN_AND_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_OFFSET_4, "and.4-d-indirect-with-index-4-s1-indirect-with-offset-4", "and.4", 32,
23773 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23774 +  },
23775 +/* and.4 ${d-imm7-4}(${d-An}),${s1-imm7-4}(${s1-An}),${s2} */
23776 +  {
23777 +    UBICOM32_INSN_AND_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_OFFSET_4, "and.4-d-indirect-with-offset-4-s1-indirect-with-offset-4", "and.4", 32,
23778 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23779 +  },
23780 +/* and.4 (${d-An}),${s1-imm7-4}(${s1-An}),${s2} */
23781 +  {
23782 +    UBICOM32_INSN_AND_4_D_INDIRECT_4_S1_INDIRECT_WITH_OFFSET_4, "and.4-d-indirect-4-s1-indirect-with-offset-4", "and.4", 32,
23783 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23784 +  },
23785 +/* and.4 (${d-An})${d-i4-4}++,${s1-imm7-4}(${s1-An}),${s2} */
23786 +  {
23787 +    UBICOM32_INSN_AND_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, "and.4-d-indirect-with-post-increment-4-s1-indirect-with-offset-4", "and.4", 32,
23788 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23789 +  },
23790 +/* and.4 ${d-i4-4}(${d-An})++,${s1-imm7-4}(${s1-An}),${s2} */
23791 +  {
23792 +    UBICOM32_INSN_AND_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, "and.4-d-indirect-with-pre-increment-4-s1-indirect-with-offset-4", "and.4", 32,
23793 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23794 +  },
23795 +/* and.4 ${d-direct-addr},(${s1-An}),${s2} */
23796 +  {
23797 +    UBICOM32_INSN_AND_4_D_DIRECT_S1_INDIRECT_4, "and.4-d-direct-s1-indirect-4", "and.4", 32,
23798 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23799 +  },
23800 +/* and.4 #${d-imm8},(${s1-An}),${s2} */
23801 +  {
23802 +    UBICOM32_INSN_AND_4_D_IMMEDIATE_4_S1_INDIRECT_4, "and.4-d-immediate-4-s1-indirect-4", "and.4", 32,
23803 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23804 +  },
23805 +/* and.4 (${d-An},${d-r}),(${s1-An}),${s2} */
23806 +  {
23807 +    UBICOM32_INSN_AND_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_4, "and.4-d-indirect-with-index-4-s1-indirect-4", "and.4", 32,
23808 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23809 +  },
23810 +/* and.4 ${d-imm7-4}(${d-An}),(${s1-An}),${s2} */
23811 +  {
23812 +    UBICOM32_INSN_AND_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_4, "and.4-d-indirect-with-offset-4-s1-indirect-4", "and.4", 32,
23813 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23814 +  },
23815 +/* and.4 (${d-An}),(${s1-An}),${s2} */
23816 +  {
23817 +    UBICOM32_INSN_AND_4_D_INDIRECT_4_S1_INDIRECT_4, "and.4-d-indirect-4-s1-indirect-4", "and.4", 32,
23818 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23819 +  },
23820 +/* and.4 (${d-An})${d-i4-4}++,(${s1-An}),${s2} */
23821 +  {
23822 +    UBICOM32_INSN_AND_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_4, "and.4-d-indirect-with-post-increment-4-s1-indirect-4", "and.4", 32,
23823 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23824 +  },
23825 +/* and.4 ${d-i4-4}(${d-An})++,(${s1-An}),${s2} */
23826 +  {
23827 +    UBICOM32_INSN_AND_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_4, "and.4-d-indirect-with-pre-increment-4-s1-indirect-4", "and.4", 32,
23828 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23829 +  },
23830 +/* and.4 ${d-direct-addr},(${s1-An})${s1-i4-4}++,${s2} */
23831 +  {
23832 +    UBICOM32_INSN_AND_4_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4, "and.4-d-direct-s1-indirect-with-post-increment-4", "and.4", 32,
23833 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23834 +  },
23835 +/* and.4 #${d-imm8},(${s1-An})${s1-i4-4}++,${s2} */
23836 +  {
23837 +    UBICOM32_INSN_AND_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "and.4-d-immediate-4-s1-indirect-with-post-increment-4", "and.4", 32,
23838 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23839 +  },
23840 +/* and.4 (${d-An},${d-r}),(${s1-An})${s1-i4-4}++,${s2} */
23841 +  {
23842 +    UBICOM32_INSN_AND_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "and.4-d-indirect-with-index-4-s1-indirect-with-post-increment-4", "and.4", 32,
23843 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23844 +  },
23845 +/* and.4 ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-4}++,${s2} */
23846 +  {
23847 +    UBICOM32_INSN_AND_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "and.4-d-indirect-with-offset-4-s1-indirect-with-post-increment-4", "and.4", 32,
23848 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23849 +  },
23850 +/* and.4 (${d-An}),(${s1-An})${s1-i4-4}++,${s2} */
23851 +  {
23852 +    UBICOM32_INSN_AND_4_D_INDIRECT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "and.4-d-indirect-4-s1-indirect-with-post-increment-4", "and.4", 32,
23853 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23854 +  },
23855 +/* and.4 (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-4}++,${s2} */
23856 +  {
23857 +    UBICOM32_INSN_AND_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "and.4-d-indirect-with-post-increment-4-s1-indirect-with-post-increment-4", "and.4", 32,
23858 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23859 +  },
23860 +/* and.4 ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-4}++,${s2} */
23861 +  {
23862 +    UBICOM32_INSN_AND_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, "and.4-d-indirect-with-pre-increment-4-s1-indirect-with-post-increment-4", "and.4", 32,
23863 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23864 +  },
23865 +/* and.4 ${d-direct-addr},${s1-i4-4}(${s1-An})++,${s2} */
23866 +  {
23867 +    UBICOM32_INSN_AND_4_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4, "and.4-d-direct-s1-indirect-with-pre-increment-4", "and.4", 32,
23868 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23869 +  },
23870 +/* and.4 #${d-imm8},${s1-i4-4}(${s1-An})++,${s2} */
23871 +  {
23872 +    UBICOM32_INSN_AND_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "and.4-d-immediate-4-s1-indirect-with-pre-increment-4", "and.4", 32,
23873 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23874 +  },
23875 +/* and.4 (${d-An},${d-r}),${s1-i4-4}(${s1-An})++,${s2} */
23876 +  {
23877 +    UBICOM32_INSN_AND_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "and.4-d-indirect-with-index-4-s1-indirect-with-pre-increment-4", "and.4", 32,
23878 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23879 +  },
23880 +/* and.4 ${d-imm7-4}(${d-An}),${s1-i4-4}(${s1-An})++,${s2} */
23881 +  {
23882 +    UBICOM32_INSN_AND_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "and.4-d-indirect-with-offset-4-s1-indirect-with-pre-increment-4", "and.4", 32,
23883 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23884 +  },
23885 +/* and.4 (${d-An}),${s1-i4-4}(${s1-An})++,${s2} */
23886 +  {
23887 +    UBICOM32_INSN_AND_4_D_INDIRECT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "and.4-d-indirect-4-s1-indirect-with-pre-increment-4", "and.4", 32,
23888 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23889 +  },
23890 +/* and.4 (${d-An})${d-i4-4}++,${s1-i4-4}(${s1-An})++,${s2} */
23891 +  {
23892 +    UBICOM32_INSN_AND_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "and.4-d-indirect-with-post-increment-4-s1-indirect-with-pre-increment-4", "and.4", 32,
23893 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23894 +  },
23895 +/* and.4 ${d-i4-4}(${d-An})++,${s1-i4-4}(${s1-An})++,${s2} */
23896 +  {
23897 +    UBICOM32_INSN_AND_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, "and.4-d-indirect-with-pre-increment-4-s1-indirect-with-pre-increment-4", "and.4", 32,
23898 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23899 +  },
23900 +/* and.2 ${d-direct-addr},${s1-direct-addr},${s2} */
23901 +  {
23902 +    UBICOM32_INSN_AND_2_D_DIRECT_S1_DIRECT, "and.2-d-direct-s1-direct", "and.2", 32,
23903 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23904 +  },
23905 +/* and.2 #${d-imm8},${s1-direct-addr},${s2} */
23906 +  {
23907 +    UBICOM32_INSN_AND_2_D_IMMEDIATE_2_S1_DIRECT, "and.2-d-immediate-2-s1-direct", "and.2", 32,
23908 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23909 +  },
23910 +/* and.2 (${d-An},${d-r}),${s1-direct-addr},${s2} */
23911 +  {
23912 +    UBICOM32_INSN_AND_2_D_INDIRECT_WITH_INDEX_2_S1_DIRECT, "and.2-d-indirect-with-index-2-s1-direct", "and.2", 32,
23913 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23914 +  },
23915 +/* and.2 ${d-imm7-2}(${d-An}),${s1-direct-addr},${s2} */
23916 +  {
23917 +    UBICOM32_INSN_AND_2_D_INDIRECT_WITH_OFFSET_2_S1_DIRECT, "and.2-d-indirect-with-offset-2-s1-direct", "and.2", 32,
23918 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23919 +  },
23920 +/* and.2 (${d-An}),${s1-direct-addr},${s2} */
23921 +  {
23922 +    UBICOM32_INSN_AND_2_D_INDIRECT_2_S1_DIRECT, "and.2-d-indirect-2-s1-direct", "and.2", 32,
23923 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23924 +  },
23925 +/* and.2 (${d-An})${d-i4-2}++,${s1-direct-addr},${s2} */
23926 +  {
23927 +    UBICOM32_INSN_AND_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_DIRECT, "and.2-d-indirect-with-post-increment-2-s1-direct", "and.2", 32,
23928 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23929 +  },
23930 +/* and.2 ${d-i4-2}(${d-An})++,${s1-direct-addr},${s2} */
23931 +  {
23932 +    UBICOM32_INSN_AND_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_DIRECT, "and.2-d-indirect-with-pre-increment-2-s1-direct", "and.2", 32,
23933 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23934 +  },
23935 +/* and.2 ${d-direct-addr},#${s1-imm8},${s2} */
23936 +  {
23937 +    UBICOM32_INSN_AND_2_D_DIRECT_S1_IMMEDIATE, "and.2-d-direct-s1-immediate", "and.2", 32,
23938 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23939 +  },
23940 +/* and.2 #${d-imm8},#${s1-imm8},${s2} */
23941 +  {
23942 +    UBICOM32_INSN_AND_2_D_IMMEDIATE_2_S1_IMMEDIATE, "and.2-d-immediate-2-s1-immediate", "and.2", 32,
23943 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23944 +  },
23945 +/* and.2 (${d-An},${d-r}),#${s1-imm8},${s2} */
23946 +  {
23947 +    UBICOM32_INSN_AND_2_D_INDIRECT_WITH_INDEX_2_S1_IMMEDIATE, "and.2-d-indirect-with-index-2-s1-immediate", "and.2", 32,
23948 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23949 +  },
23950 +/* and.2 ${d-imm7-2}(${d-An}),#${s1-imm8},${s2} */
23951 +  {
23952 +    UBICOM32_INSN_AND_2_D_INDIRECT_WITH_OFFSET_2_S1_IMMEDIATE, "and.2-d-indirect-with-offset-2-s1-immediate", "and.2", 32,
23953 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23954 +  },
23955 +/* and.2 (${d-An}),#${s1-imm8},${s2} */
23956 +  {
23957 +    UBICOM32_INSN_AND_2_D_INDIRECT_2_S1_IMMEDIATE, "and.2-d-indirect-2-s1-immediate", "and.2", 32,
23958 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23959 +  },
23960 +/* and.2 (${d-An})${d-i4-2}++,#${s1-imm8},${s2} */
23961 +  {
23962 +    UBICOM32_INSN_AND_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_IMMEDIATE, "and.2-d-indirect-with-post-increment-2-s1-immediate", "and.2", 32,
23963 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23964 +  },
23965 +/* and.2 ${d-i4-2}(${d-An})++,#${s1-imm8},${s2} */
23966 +  {
23967 +    UBICOM32_INSN_AND_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_IMMEDIATE, "and.2-d-indirect-with-pre-increment-2-s1-immediate", "and.2", 32,
23968 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23969 +  },
23970 +/* and.2 ${d-direct-addr},(${s1-An},${s1-r}),${s2} */
23971 +  {
23972 +    UBICOM32_INSN_AND_2_D_DIRECT_S1_INDIRECT_WITH_INDEX_2, "and.2-d-direct-s1-indirect-with-index-2", "and.2", 32,
23973 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23974 +  },
23975 +/* and.2 #${d-imm8},(${s1-An},${s1-r}),${s2} */
23976 +  {
23977 +    UBICOM32_INSN_AND_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_INDEX_2, "and.2-d-immediate-2-s1-indirect-with-index-2", "and.2", 32,
23978 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23979 +  },
23980 +/* and.2 (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */
23981 +  {
23982 +    UBICOM32_INSN_AND_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_INDEX_2, "and.2-d-indirect-with-index-2-s1-indirect-with-index-2", "and.2", 32,
23983 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23984 +  },
23985 +/* and.2 ${d-imm7-2}(${d-An}),(${s1-An},${s1-r}),${s2} */
23986 +  {
23987 +    UBICOM32_INSN_AND_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_INDEX_2, "and.2-d-indirect-with-offset-2-s1-indirect-with-index-2", "and.2", 32,
23988 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23989 +  },
23990 +/* and.2 (${d-An}),(${s1-An},${s1-r}),${s2} */
23991 +  {
23992 +    UBICOM32_INSN_AND_2_D_INDIRECT_2_S1_INDIRECT_WITH_INDEX_2, "and.2-d-indirect-2-s1-indirect-with-index-2", "and.2", 32,
23993 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23994 +  },
23995 +/* and.2 (${d-An})${d-i4-2}++,(${s1-An},${s1-r}),${s2} */
23996 +  {
23997 +    UBICOM32_INSN_AND_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_INDEX_2, "and.2-d-indirect-with-post-increment-2-s1-indirect-with-index-2", "and.2", 32,
23998 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
23999 +  },
24000 +/* and.2 ${d-i4-2}(${d-An})++,(${s1-An},${s1-r}),${s2} */
24001 +  {
24002 +    UBICOM32_INSN_AND_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_INDEX_2, "and.2-d-indirect-with-pre-increment-2-s1-indirect-with-index-2", "and.2", 32,
24003 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
24004 +  },
24005 +/* and.2 ${d-direct-addr},${s1-imm7-2}(${s1-An}),${s2} */
24006 +  {
24007 +    UBICOM32_INSN_AND_2_D_DIRECT_S1_INDIRECT_WITH_OFFSET_2, "and.2-d-direct-s1-indirect-with-offset-2", "and.2", 32,
24008 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
24009 +  },
24010 +/* and.2 #${d-imm8},${s1-imm7-2}(${s1-An}),${s2} */
24011 +  {
24012 +    UBICOM32_INSN_AND_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_OFFSET_2, "and.2-d-immediate-2-s1-indirect-with-offset-2", "and.2", 32,
24013 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
24014 +  },
24015 +/* and.2 (${d-An},${d-r}),${s1-imm7-2}(${s1-An}),${s2} */
24016 +  {
24017 +    UBICOM32_INSN_AND_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_OFFSET_2, "and.2-d-indirect-with-index-2-s1-indirect-with-offset-2", "and.2", 32,
24018 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
24019 +  },
24020 +/* and.2 ${d-imm7-2}(${d-An}),${s1-imm7-2}(${s1-An}),${s2} */
24021 +  {
24022 +    UBICOM32_INSN_AND_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_OFFSET_2, "and.2-d-indirect-with-offset-2-s1-indirect-with-offset-2", "and.2", 32,
24023 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
24024 +  },
24025 +/* and.2 (${d-An}),${s1-imm7-2}(${s1-An}),${s2} */
24026 +  {
24027 +    UBICOM32_INSN_AND_2_D_INDIRECT_2_S1_INDIRECT_WITH_OFFSET_2, "and.2-d-indirect-2-s1-indirect-with-offset-2", "and.2", 32,
24028 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
24029 +  },
24030 +/* and.2 (${d-An})${d-i4-2}++,${s1-imm7-2}(${s1-An}),${s2} */
24031 +  {
24032 +    UBICOM32_INSN_AND_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_2, "and.2-d-indirect-with-post-increment-2-s1-indirect-with-offset-2", "and.2", 32,
24033 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
24034 +  },
24035 +/* and.2 ${d-i4-2}(${d-An})++,${s1-imm7-2}(${s1-An}),${s2} */
24036 +  {
24037 +    UBICOM32_INSN_AND_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_2, "and.2-d-indirect-with-pre-increment-2-s1-indirect-with-offset-2", "and.2", 32,
24038 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
24039 +  },
24040 +/* and.2 ${d-direct-addr},(${s1-An}),${s2} */
24041 +  {
24042 +    UBICOM32_INSN_AND_2_D_DIRECT_S1_INDIRECT_2, "and.2-d-direct-s1-indirect-2", "and.2", 32,
24043 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
24044 +  },
24045 +/* and.2 #${d-imm8},(${s1-An}),${s2} */
24046 +  {
24047 +    UBICOM32_INSN_AND_2_D_IMMEDIATE_2_S1_INDIRECT_2, "and.2-d-immediate-2-s1-indirect-2", "and.2", 32,
24048 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
24049 +  },
24050 +/* and.2 (${d-An},${d-r}),(${s1-An}),${s2} */
24051 +  {
24052 +    UBICOM32_INSN_AND_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_2, "and.2-d-indirect-with-index-2-s1-indirect-2", "and.2", 32,
24053 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
24054 +  },
24055 +/* and.2 ${d-imm7-2}(${d-An}),(${s1-An}),${s2} */
24056 +  {
24057 +    UBICOM32_INSN_AND_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_2, "and.2-d-indirect-with-offset-2-s1-indirect-2", "and.2", 32,
24058 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
24059 +  },
24060 +/* and.2 (${d-An}),(${s1-An}),${s2} */
24061 +  {
24062 +    UBICOM32_INSN_AND_2_D_INDIRECT_2_S1_INDIRECT_2, "and.2-d-indirect-2-s1-indirect-2", "and.2", 32,
24063 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
24064 +  },
24065 +/* and.2 (${d-An})${d-i4-2}++,(${s1-An}),${s2} */
24066 +  {
24067 +    UBICOM32_INSN_AND_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_2, "and.2-d-indirect-with-post-increment-2-s1-indirect-2", "and.2", 32,
24068 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
24069 +  },
24070 +/* and.2 ${d-i4-2}(${d-An})++,(${s1-An}),${s2} */
24071 +  {
24072 +    UBICOM32_INSN_AND_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_2, "and.2-d-indirect-with-pre-increment-2-s1-indirect-2", "and.2", 32,
24073 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
24074 +  },
24075 +/* and.2 ${d-direct-addr},(${s1-An})${s1-i4-2}++,${s2} */
24076 +  {
24077 +    UBICOM32_INSN_AND_2_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_2, "and.2-d-direct-s1-indirect-with-post-increment-2", "and.2", 32,
24078 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
24079 +  },
24080 +/* and.2 #${d-imm8},(${s1-An})${s1-i4-2}++,${s2} */
24081 +  {
24082 +    UBICOM32_INSN_AND_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_POST_INCREMENT_2, "and.2-d-immediate-2-s1-indirect-with-post-increment-2", "and.2", 32,
24083 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
24084 +  },
24085 +/* and.2 (${d-An},${d-r}),(${s1-An})${s1-i4-2}++,${s2} */
24086 +  {
24087 +    UBICOM32_INSN_AND_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_POST_INCREMENT_2, "and.2-d-indirect-with-index-2-s1-indirect-with-post-increment-2", "and.2", 32,
24088 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
24089 +  },
24090 +/* and.2 ${d-imm7-2}(${d-An}),(${s1-An})${s1-i4-2}++,${s2} */
24091 +  {
24092 +    UBICOM32_INSN_AND_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_POST_INCREMENT_2, "and.2-d-indirect-with-offset-2-s1-indirect-with-post-increment-2", "and.2", 32,
24093 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
24094 +  },
24095 +/* and.2 (${d-An}),(${s1-An})${s1-i4-2}++,${s2} */
24096 +  {
24097 +    UBICOM32_INSN_AND_2_D_INDIRECT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, "and.2-d-indirect-2-s1-indirect-with-post-increment-2", "and.2", 32,
24098 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
24099 +  },
24100 +/* and.2 (${d-An})${d-i4-2}++,(${s1-An})${s1-i4-2}++,${s2} */
24101 +  {
24102 +    UBICOM32_INSN_AND_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, "and.2-d-indirect-with-post-increment-2-s1-indirect-with-post-increment-2", "and.2", 32,
24103 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
24104 +  },
24105 +/* and.2 ${d-i4-2}(${d-An})++,(${s1-An})${s1-i4-2}++,${s2} */
24106 +  {
24107 +    UBICOM32_INSN_AND_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, "and.2-d-indirect-with-pre-increment-2-s1-indirect-with-post-increment-2", "and.2", 32,
24108 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
24109 +  },
24110 +/* and.2 ${d-direct-addr},${s1-i4-2}(${s1-An})++,${s2} */
24111 +  {
24112 +    UBICOM32_INSN_AND_2_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_2, "and.2-d-direct-s1-indirect-with-pre-increment-2", "and.2", 32,
24113 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
24114 +  },
24115 +/* and.2 #${d-imm8},${s1-i4-2}(${s1-An})++,${s2} */
24116 +  {
24117 +    UBICOM32_INSN_AND_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, "and.2-d-immediate-2-s1-indirect-with-pre-increment-2", "and.2", 32,
24118 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
24119 +  },
24120 +/* and.2 (${d-An},${d-r}),${s1-i4-2}(${s1-An})++,${s2} */
24121 +  {
24122 +    UBICOM32_INSN_AND_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, "and.2-d-indirect-with-index-2-s1-indirect-with-pre-increment-2", "and.2", 32,
24123 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
24124 +  },
24125 +/* and.2 ${d-imm7-2}(${d-An}),${s1-i4-2}(${s1-An})++,${s2} */
24126 +  {
24127 +    UBICOM32_INSN_AND_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, "and.2-d-indirect-with-offset-2-s1-indirect-with-pre-increment-2", "and.2", 32,
24128 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
24129 +  },
24130 +/* and.2 (${d-An}),${s1-i4-2}(${s1-An})++,${s2} */
24131 +  {
24132 +    UBICOM32_INSN_AND_2_D_INDIRECT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, "and.2-d-indirect-2-s1-indirect-with-pre-increment-2", "and.2", 32,
24133 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
24134 +  },
24135 +/* and.2 (${d-An})${d-i4-2}++,${s1-i4-2}(${s1-An})++,${s2} */
24136 +  {
24137 +    UBICOM32_INSN_AND_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, "and.2-d-indirect-with-post-increment-2-s1-indirect-with-pre-increment-2", "and.2", 32,
24138 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
24139 +  },
24140 +/* and.2 ${d-i4-2}(${d-An})++,${s1-i4-2}(${s1-An})++,${s2} */
24141 +  {
24142 +    UBICOM32_INSN_AND_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, "and.2-d-indirect-with-pre-increment-2-s1-indirect-with-pre-increment-2", "and.2", 32,
24143 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
24144 +  },
24145 +/* moveai ${An},#${imm24} */
24146 +  {
24147 +    UBICOM32_INSN_MOVEAI, "moveai", "moveai", 32,
24148 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
24149 +  },
24150 +/* __nop__ */
24151 +  {
24152 +    UBICOM32_INSN_NOP_INSN, "nop-insn", "__nop__", 32,
24153 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
24154 +  },
24155 +/* jmp${cc}${C}${P} $offset21 */
24156 +  {
24157 +    UBICOM32_INSN_JMPCC, "jmpcc", "jmp", 32,
24158 +    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
24159 +  },
24160 +/* call $An,$offset24 */
24161 +  {
24162 +    UBICOM32_INSN_CALL, "call", "call", 32,
24163 +    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
24164 +  },
24165 +/* calli ${An},${offset16}(${Am}) */
24166 +  {
24167 +    UBICOM32_INSN_CALLI, "calli", "calli", 32,
24168 +    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
24169 +  },
24170 +/* suspend */
24171 +  {
24172 +    UBICOM32_INSN_SUSPEND, "suspend", "suspend", 32,
24173 +    { 0, { { { (1<<MACH_BASE), 0 } } } }
24174 +  },
24175 +/* __clracc__ ${dsp-destA} */
24176 +  {
24177 +    UBICOM32_INSN_DSP_CLRACC, "dsp-clracc", "__clracc__", 32,
24178 +    { 0, { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
24179 +  },
24180 +/* __unused__00_11 */
24181 +  {
24182 +    UBICOM32_INSN_UNUSED_00_11, "unused.00_11", "__unused__00_11", 32,
24183 +    { 0|A(NO_DIS), { { { (1<<MACH_BASE), 0 } } } }
24184 +  },
24185 +/* __unused__00_13 */
24186 +  {
24187 +    UBICOM32_INSN_UNUSED_00_13, "unused.00_13", "__unused__00_13", 32,
24188 +    { 0|A(NO_DIS), { { { (1<<MACH_BASE), 0 } } } }
24189 +  },
24190 +/* __unused__00_14 */
24191 +  {
24192 +    UBICOM32_INSN_UNUSED_00_14, "unused.00_14", "__unused__00_14", 32,
24193 +    { 0|A(NO_DIS), { { { (1<<MACH_BASE), 0 } } } }
24194 +  },
24195 +/* __unused__00_16 */
24196 +  {
24197 +    UBICOM32_INSN_UNUSED_00_16, "unused.00_16", "__unused__00_16", 32,
24198 +    { 0|A(NO_DIS), { { { (1<<MACH_BASE), 0 } } } }
24199 +  },
24200 +/* __unused__02_04 */
24201 +  {
24202 +    UBICOM32_INSN_UNUSED_02_04, "unused.02_04", "__unused__02_04", 32,
24203 +    { 0|A(NO_DIS), { { { (1<<MACH_BASE), 0 } } } }
24204 +  },
24205 +/* __unused__02_07 */
24206 +  {
24207 +    UBICOM32_INSN_UNUSED_02_07, "unused.02_07", "__unused__02_07", 32,
24208 +    { 0|A(NO_DIS), { { { (1<<MACH_BASE), 0 } } } }
24209 +  },
24210 +/* __unused__02_0D */
24211 +  {
24212 +    UBICOM32_INSN_UNUSED_02_0D, "unused.02_0D", "__unused__02_0D", 32,
24213 +    { 0|A(NO_DIS), { { { (1<<MACH_BASE), 0 } } } }
24214 +  },
24215 +/* __unused__02_0E */
24216 +  {
24217 +    UBICOM32_INSN_UNUSED_02_0E, "unused.02_0E", "__unused__02_0E", 32,
24218 +    { 0|A(NO_DIS), { { { (1<<MACH_BASE), 0 } } } }
24219 +  },
24220 +/* __unused__02_0F */
24221 +  {
24222 +    UBICOM32_INSN_UNUSED_02_0F, "unused.02_0F", "__unused__02_0F", 32,
24223 +    { 0|A(NO_DIS), { { { (1<<MACH_BASE), 0 } } } }
24224 +  },
24225 +/* __unused__02_17 */
24226 +  {
24227 +    UBICOM32_INSN_UNUSED_02_17, "unused.02_17", "__unused__02_17", 32,
24228 +    { 0|A(NO_DIS), { { { (1<<MACH_BASE), 0 } } } }
24229 +  },
24230 +/* __unused__02_19 */
24231 +  {
24232 +    UBICOM32_INSN_UNUSED_02_19, "unused.02_19", "__unused__02_19", 32,
24233 +    { 0|A(NO_DIS), { { { (1<<MACH_BASE), 0 } } } }
24234 +  },
24235 +/* __unused__02_1B */
24236 +  {
24237 +    UBICOM32_INSN_UNUSED_02_1B, "unused.02_1B", "__unused__02_1B", 32,
24238 +    { 0|A(NO_DIS), { { { (1<<MACH_BASE), 0 } } } }
24239 +  },
24240 +/* __unused__02_1D */
24241 +  {
24242 +    UBICOM32_INSN_UNUSED_02_1D, "unused.02_1D", "__unused__02_1D", 32,
24243 +    { 0|A(NO_DIS), { { { (1<<MACH_BASE), 0 } } } }
24244 +  },
24245 +/* __unused__01 */
24246 +  {
24247 +    UBICOM32_INSN_UNUSED_01, "unused.01", "__unused__01", 32,
24248 +    { 0|A(NO_DIS), { { { (1<<MACH_BASE), 0 } } } }
24249 +  },
24250 +/* __unused__03 */
24251 +  {
24252 +    UBICOM32_INSN_UNUSED_03, "unused.03", "__unused__03", 32,
24253 +    { 0|A(NO_DIS), { { { (1<<MACH_BASE), 0 } } } }
24254 +  },
24255 +/* __unused__07 */
24256 +  {
24257 +    UBICOM32_INSN_UNUSED_07, "unused.07", "__unused__07", 32,
24258 +    { 0|A(NO_DIS), { { { (1<<MACH_BASE), 0 } } } }
24259 +  },
24260 +/* __unused__17 */
24261 +  {
24262 +    UBICOM32_INSN_UNUSED_17, "unused.17", "__unused__17", 32,
24263 +    { 0|A(NO_DIS), { { { (1<<MACH_BASE), 0 } } } }
24264 +  },
24265 +/* __unused__1D */
24266 +  {
24267 +    UBICOM32_INSN_UNUSED_1D, "unused.1D", "__unused__1D", 32,
24268 +    { 0|A(NO_DIS), { { { (1<<MACH_BASE), 0 } } } }
24269 +  },
24270 +/* __unused__1F */
24271 +  {
24272 +    UBICOM32_INSN_UNUSED_1F, "unused.1F", "__unused__1F", 32,
24273 +    { 0|A(NO_DIS), { { { (1<<MACH_BASE), 0 } } } }
24274 +  },
24275 +/* __unused__DSP_06 */
24276 +  {
24277 +    UBICOM32_INSN_UNUSED_DSP_06, "unused.DSP_06", "__unused__DSP_06", 32,
24278 +    { 0|A(NO_DIS), { { { (1<<MACH_BASE), 0 } } } }
24279 +  },
24280 +/* __unused__DSP_0b */
24281 +  {
24282 +    UBICOM32_INSN_UNUSED_DSP_0B, "unused.DSP_0b", "__unused__DSP_0b", 32,
24283 +    { 0|A(NO_DIS), { { { (1<<MACH_BASE), 0 } } } }
24284 +  },
24285 +/* __unused__DSP_0c */
24286 +  {
24287 +    UBICOM32_INSN_UNUSED_DSP_0C, "unused.DSP_0c", "__unused__DSP_0c", 32,
24288 +    { 0|A(NO_DIS), { { { (1<<MACH_BASE), 0 } } } }
24289 +  },
24290 +/* __unused__DSP_0d */
24291 +  {
24292 +    UBICOM32_INSN_UNUSED_DSP_0D, "unused.DSP_0d", "__unused__DSP_0d", 32,
24293 +    { 0|A(NO_DIS), { { { (1<<MACH_BASE), 0 } } } }
24294 +  },
24295 +/* __unused__DSP_0e */
24296 +  {
24297 +    UBICOM32_INSN_UNUSED_DSP_0E, "unused.DSP_0e", "__unused__DSP_0e", 32,
24298 +    { 0|A(NO_DIS), { { { (1<<MACH_BASE), 0 } } } }
24299 +  },
24300 +/* __unused__DSP_0f */
24301 +  {
24302 +    UBICOM32_INSN_UNUSED_DSP_0F, "unused.DSP_0f", "__unused__DSP_0f", 32,
24303 +    { 0|A(NO_DIS), { { { (1<<MACH_BASE), 0 } } } }
24304 +  },
24305 +/* __unused__DSP_14 */
24306 +  {
24307 +    UBICOM32_INSN_UNUSED_DSP_14, "unused.DSP_14", "__unused__DSP_14", 32,
24308 +    { 0|A(NO_DIS), { { { (1<<MACH_BASE), 0 } } } }
24309 +  },
24310 +/* __unused__DSP_15 */
24311 +  {
24312 +    UBICOM32_INSN_UNUSED_DSP_15, "unused.DSP_15", "__unused__DSP_15", 32,
24313 +    { 0|A(NO_DIS), { { { (1<<MACH_BASE), 0 } } } }
24314 +  },
24315 +/* __unused__DSP_16 */
24316 +  {
24317 +    UBICOM32_INSN_UNUSED_DSP_16, "unused.DSP_16", "__unused__DSP_16", 32,
24318 +    { 0|A(NO_DIS), { { { (1<<MACH_BASE), 0 } } } }
24319 +  },
24320 +/* __unused__DSP_17 */
24321 +  {
24322 +    UBICOM32_INSN_UNUSED_DSP_17, "unused.DSP_17", "__unused__DSP_17", 32,
24323 +    { 0|A(NO_DIS), { { { (1<<MACH_BASE), 0 } } } }
24324 +  },
24325 +/* __unused__DSP_18 */
24326 +  {
24327 +    UBICOM32_INSN_UNUSED_DSP_18, "unused.DSP_18", "__unused__DSP_18", 32,
24328 +    { 0|A(NO_DIS), { { { (1<<MACH_BASE), 0 } } } }
24329 +  },
24330 +/* __unused__DSP_19 */
24331 +  {
24332 +    UBICOM32_INSN_UNUSED_DSP_19, "unused.DSP_19", "__unused__DSP_19", 32,
24333 +    { 0|A(NO_DIS), { { { (1<<MACH_BASE), 0 } } } }
24334 +  },
24335 +/* __unused__DSP_1a */
24336 +  {
24337 +    UBICOM32_INSN_UNUSED_DSP_1A, "unused.DSP_1a", "__unused__DSP_1a", 32,
24338 +    { 0|A(NO_DIS), { { { (1<<MACH_BASE), 0 } } } }
24339 +  },
24340 +/* __unused__DSP_1b */
24341 +  {
24342 +    UBICOM32_INSN_UNUSED_DSP_1B, "unused.DSP_1b", "__unused__DSP_1b", 32,
24343 +    { 0|A(NO_DIS), { { { (1<<MACH_BASE), 0 } } } }
24344 +  },
24345 +/* __unused__DSP_1c */
24346 +  {
24347 +    UBICOM32_INSN_UNUSED_DSP_1C, "unused.DSP_1c", "__unused__DSP_1c", 32,
24348 +    { 0|A(NO_DIS), { { { (1<<MACH_BASE), 0 } } } }
24349 +  },
24350 +/* __unused__DSP_1d */
24351 +  {
24352 +    UBICOM32_INSN_UNUSED_DSP_1D, "unused.DSP_1d", "__unused__DSP_1d", 32,
24353 +    { 0|A(NO_DIS), { { { (1<<MACH_BASE), 0 } } } }
24354 +  },
24355 +/* __unused__DSP_1e */
24356 +  {
24357 +    UBICOM32_INSN_UNUSED_DSP_1E, "unused.DSP_1e", "__unused__DSP_1e", 32,
24358 +    { 0|A(NO_DIS), { { { (1<<MACH_BASE), 0 } } } }
24359 +  },
24360 +/* __unused__DSP_1f */
24361 +  {
24362 +    UBICOM32_INSN_UNUSED_DSP_1F, "unused.DSP_1f", "__unused__DSP_1f", 32,
24363 +    { 0|A(NO_DIS), { { { (1<<MACH_BASE), 0 } } } }
24364 +  },
24365 +};
24366 +
24367 +#undef OP
24368 +#undef A
24369 +
24370 +/* Initialize anything needed to be done once, before any cpu_open call.  */
24371 +
24372 +static void
24373 +init_tables (void)
24374 +{
24375 +}
24376 +
24377 +static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
24378 +static void build_hw_table      (CGEN_CPU_TABLE *);
24379 +static void build_ifield_table  (CGEN_CPU_TABLE *);
24380 +static void build_operand_table (CGEN_CPU_TABLE *);
24381 +static void build_insn_table    (CGEN_CPU_TABLE *);
24382 +static void ubicom32_cgen_rebuild_tables (CGEN_CPU_TABLE *);
24383 +
24384 +/* Subroutine of ubicom32_cgen_cpu_open to look up a mach via its bfd name.  */
24385 +
24386 +static const CGEN_MACH *
24387 +lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
24388 +{
24389 +  while (table->name)
24390 +    {
24391 +      if (strcmp (name, table->bfd_name) == 0)
24392 +       return table;
24393 +      ++table;
24394 +    }
24395 +  abort ();
24396 +}
24397 +
24398 +/* Subroutine of ubicom32_cgen_cpu_open to build the hardware table.  */
24399 +
24400 +static void
24401 +build_hw_table (CGEN_CPU_TABLE *cd)
24402 +{
24403 +  int i;
24404 +  int machs = cd->machs;
24405 +  const CGEN_HW_ENTRY *init = & ubicom32_cgen_hw_table[0];
24406 +  /* MAX_HW is only an upper bound on the number of selected entries.
24407 +     However each entry is indexed by it's enum so there can be holes in
24408 +     the table.  */
24409 +  const CGEN_HW_ENTRY **selected =
24410 +    (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
24411 +
24412 +  cd->hw_table.init_entries = init;
24413 +  cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
24414 +  memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
24415 +  /* ??? For now we just use machs to determine which ones we want.  */
24416 +  for (i = 0; init[i].name != NULL; ++i)
24417 +    if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
24418 +       & machs)
24419 +      selected[init[i].type] = &init[i];
24420 +  cd->hw_table.entries = selected;
24421 +  cd->hw_table.num_entries = MAX_HW;
24422 +}
24423 +
24424 +/* Subroutine of ubicom32_cgen_cpu_open to build the hardware table.  */
24425 +
24426 +static void
24427 +build_ifield_table (CGEN_CPU_TABLE *cd)
24428 +{
24429 +  cd->ifld_table = & ubicom32_cgen_ifld_table[0];
24430 +}
24431 +
24432 +/* Subroutine of ubicom32_cgen_cpu_open to build the hardware table.  */
24433 +
24434 +static void
24435 +build_operand_table (CGEN_CPU_TABLE *cd)
24436 +{
24437 +  int i;
24438 +  int machs = cd->machs;
24439 +  const CGEN_OPERAND *init = & ubicom32_cgen_operand_table[0];
24440 +  /* MAX_OPERANDS is only an upper bound on the number of selected entries.
24441 +     However each entry is indexed by it's enum so there can be holes in
24442 +     the table.  */
24443 +  const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
24444 +
24445 +  cd->operand_table.init_entries = init;
24446 +  cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
24447 +  memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
24448 +  /* ??? For now we just use mach to determine which ones we want.  */
24449 +  for (i = 0; init[i].name != NULL; ++i)
24450 +    if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
24451 +       & machs)
24452 +      selected[init[i].type] = &init[i];
24453 +  cd->operand_table.entries = selected;
24454 +  cd->operand_table.num_entries = MAX_OPERANDS;
24455 +}
24456 +
24457 +/* Subroutine of ubicom32_cgen_cpu_open to build the hardware table.
24458 +   ??? This could leave out insns not supported by the specified mach/isa,
24459 +   but that would cause errors like "foo only supported by bar" to become
24460 +   "unknown insn", so for now we include all insns and require the app to
24461 +   do the checking later.
24462 +   ??? On the other hand, parsing of such insns may require their hardware or
24463 +   operand elements to be in the table [which they mightn't be].  */
24464 +
24465 +static void
24466 +build_insn_table (CGEN_CPU_TABLE *cd)
24467 +{
24468 +  int i;
24469 +  const CGEN_IBASE *ib = & ubicom32_cgen_insn_table[0];
24470 +  CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
24471 +
24472 +  memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
24473 +  for (i = 0; i < MAX_INSNS; ++i)
24474 +    insns[i].base = &ib[i];
24475 +  cd->insn_table.init_entries = insns;
24476 +  cd->insn_table.entry_size = sizeof (CGEN_IBASE);
24477 +  cd->insn_table.num_init_entries = MAX_INSNS;
24478 +}
24479 +
24480 +/* Subroutine of ubicom32_cgen_cpu_open to rebuild the tables.  */
24481 +
24482 +static void
24483 +ubicom32_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
24484 +{
24485 +  int i;
24486 +  CGEN_BITSET *isas = cd->isas;
24487 +  unsigned int machs = cd->machs;
24488 +
24489 +  cd->int_insn_p = CGEN_INT_INSN_P;
24490 +
24491 +  /* Data derived from the isa spec.  */
24492 +#define UNSET (CGEN_SIZE_UNKNOWN + 1)
24493 +  cd->default_insn_bitsize = UNSET;
24494 +  cd->base_insn_bitsize = UNSET;
24495 +  cd->min_insn_bitsize = 65535; /* Some ridiculously big number.  */
24496 +  cd->max_insn_bitsize = 0;
24497 +  for (i = 0; i < MAX_ISAS; ++i)
24498 +    if (cgen_bitset_contains (isas, i))
24499 +      {
24500 +       const CGEN_ISA *isa = & ubicom32_cgen_isa_table[i];
24501 +
24502 +       /* Default insn sizes of all selected isas must be
24503 +          equal or we set the result to 0, meaning "unknown".  */
24504 +       if (cd->default_insn_bitsize == UNSET)
24505 +         cd->default_insn_bitsize = isa->default_insn_bitsize;
24506 +       else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
24507 +         ; /* This is ok.  */
24508 +       else
24509 +         cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
24510 +
24511 +       /* Base insn sizes of all selected isas must be equal
24512 +          or we set the result to 0, meaning "unknown".  */
24513 +       if (cd->base_insn_bitsize == UNSET)
24514 +         cd->base_insn_bitsize = isa->base_insn_bitsize;
24515 +       else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
24516 +         ; /* This is ok.  */
24517 +       else
24518 +         cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
24519 +
24520 +       /* Set min,max insn sizes.  */
24521 +       if (isa->min_insn_bitsize < cd->min_insn_bitsize)
24522 +         cd->min_insn_bitsize = isa->min_insn_bitsize;
24523 +       if (isa->max_insn_bitsize > cd->max_insn_bitsize)
24524 +         cd->max_insn_bitsize = isa->max_insn_bitsize;
24525 +      }
24526 +
24527 +  /* Data derived from the mach spec.  */
24528 +  for (i = 0; i < MAX_MACHS; ++i)
24529 +    if (((1 << i) & machs) != 0)
24530 +      {
24531 +       const CGEN_MACH *mach = & ubicom32_cgen_mach_table[i];
24532 +
24533 +       if (mach->insn_chunk_bitsize != 0)
24534 +       {
24535 +         if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
24536 +           {
24537 +             fprintf (stderr, "ubicom32_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
24538 +                      cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
24539 +             abort ();
24540 +           }
24541 +
24542 +         cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
24543 +       }
24544 +      }
24545 +
24546 +  /* Determine which hw elements are used by MACH.  */
24547 +  build_hw_table (cd);
24548 +
24549 +  /* Build the ifield table.  */
24550 +  build_ifield_table (cd);
24551 +
24552 +  /* Determine which operands are used by MACH/ISA.  */
24553 +  build_operand_table (cd);
24554 +
24555 +  /* Build the instruction table.  */
24556 +  build_insn_table (cd);
24557 +}
24558 +
24559 +/* Initialize a cpu table and return a descriptor.
24560 +   It's much like opening a file, and must be the first function called.
24561 +   The arguments are a set of (type/value) pairs, terminated with
24562 +   CGEN_CPU_OPEN_END.
24563 +
24564 +   Currently supported values:
24565 +   CGEN_CPU_OPEN_ISAS:    bitmap of values in enum isa_attr
24566 +   CGEN_CPU_OPEN_MACHS:   bitmap of values in enum mach_attr
24567 +   CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
24568 +   CGEN_CPU_OPEN_ENDIAN:  specify endian choice
24569 +   CGEN_CPU_OPEN_END:     terminates arguments
24570 +
24571 +   ??? Simultaneous multiple isas might not make sense, but it's not (yet)
24572 +   precluded.
24573 +
24574 +   ??? We only support ISO C stdargs here, not K&R.
24575 +   Laziness, plus experiment to see if anything requires K&R - eventually
24576 +   K&R will no longer be supported - e.g. GDB is currently trying this.  */
24577 +
24578 +CGEN_CPU_DESC
24579 +ubicom32_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
24580 +{
24581 +  CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
24582 +  static int init_p;
24583 +  CGEN_BITSET *isas = 0;  /* 0 = "unspecified" */
24584 +  unsigned int machs = 0; /* 0 = "unspecified" */
24585 +  enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
24586 +  va_list ap;
24587 +
24588 +  if (! init_p)
24589 +    {
24590 +      init_tables ();
24591 +      init_p = 1;
24592 +    }
24593 +
24594 +  memset (cd, 0, sizeof (*cd));
24595 +
24596 +  va_start (ap, arg_type);
24597 +  while (arg_type != CGEN_CPU_OPEN_END)
24598 +    {
24599 +      switch (arg_type)
24600 +       {
24601 +       case CGEN_CPU_OPEN_ISAS :
24602 +         isas = va_arg (ap, CGEN_BITSET *);
24603 +         break;
24604 +       case CGEN_CPU_OPEN_MACHS :
24605 +         machs = va_arg (ap, unsigned int);
24606 +         break;
24607 +       case CGEN_CPU_OPEN_BFDMACH :
24608 +         {
24609 +           const char *name = va_arg (ap, const char *);
24610 +           const CGEN_MACH *mach =
24611 +             lookup_mach_via_bfd_name (ubicom32_cgen_mach_table, name);
24612 +
24613 +           machs |= 1 << mach->num;
24614 +           break;
24615 +         }
24616 +       case CGEN_CPU_OPEN_ENDIAN :
24617 +         endian = va_arg (ap, enum cgen_endian);
24618 +         break;
24619 +       default :
24620 +         fprintf (stderr, "ubicom32_cgen_cpu_open: unsupported argument `%d'\n",
24621 +                  arg_type);
24622 +         abort (); /* ??? return NULL? */
24623 +       }
24624 +      arg_type = va_arg (ap, enum cgen_cpu_open_arg);
24625 +    }
24626 +  va_end (ap);
24627 +
24628 +  /* Mach unspecified means "all".  */
24629 +  if (machs == 0)
24630 +    machs = (1 << MAX_MACHS) - 1;
24631 +  /* Base mach is always selected.  */
24632 +  machs |= 1;
24633 +  if (endian == CGEN_ENDIAN_UNKNOWN)
24634 +    {
24635 +      /* ??? If target has only one, could have a default.  */
24636 +      fprintf (stderr, "ubicom32_cgen_cpu_open: no endianness specified\n");
24637 +      abort ();
24638 +    }
24639 +
24640 +  cd->isas = cgen_bitset_copy (isas);
24641 +  cd->machs = machs;
24642 +  cd->endian = endian;
24643 +  /* FIXME: for the sparc case we can determine insn-endianness statically.
24644 +     The worry here is where both data and insn endian can be independently
24645 +     chosen, in which case this function will need another argument.
24646 +     Actually, will want to allow for more arguments in the future anyway.  */
24647 +  cd->insn_endian = endian;
24648 +
24649 +  /* Table (re)builder.  */
24650 +  cd->rebuild_tables = ubicom32_cgen_rebuild_tables;
24651 +  ubicom32_cgen_rebuild_tables (cd);
24652 +
24653 +  /* Default to not allowing signed overflow.  */
24654 +  cd->signed_overflow_ok_p = 0;
24655 +  
24656 +  return (CGEN_CPU_DESC) cd;
24657 +}
24658 +
24659 +/* Cover fn to ubicom32_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
24660 +   MACH_NAME is the bfd name of the mach.  */
24661 +
24662 +CGEN_CPU_DESC
24663 +ubicom32_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
24664 +{
24665 +  return ubicom32_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
24666 +                              CGEN_CPU_OPEN_ENDIAN, endian,
24667 +                              CGEN_CPU_OPEN_END);
24668 +}
24669 +
24670 +/* Close a cpu table.
24671 +   ??? This can live in a machine independent file, but there's currently
24672 +   no place to put this file (there's no libcgen).  libopcodes is the wrong
24673 +   place as some simulator ports use this but they don't use libopcodes.  */
24674 +
24675 +void
24676 +ubicom32_cgen_cpu_close (CGEN_CPU_DESC cd)
24677 +{
24678 +  unsigned int i;
24679 +  const CGEN_INSN *insns;
24680 +
24681 +  if (cd->macro_insn_table.init_entries)
24682 +    {
24683 +      insns = cd->macro_insn_table.init_entries;
24684 +      for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
24685 +       if (CGEN_INSN_RX ((insns)))
24686 +         regfree (CGEN_INSN_RX (insns));
24687 +    }
24688 +
24689 +  if (cd->insn_table.init_entries)
24690 +    {
24691 +      insns = cd->insn_table.init_entries;
24692 +      for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
24693 +       if (CGEN_INSN_RX (insns))
24694 +         regfree (CGEN_INSN_RX (insns));
24695 +    }  
24696 +
24697 +  if (cd->macro_insn_table.init_entries)
24698 +    free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
24699 +
24700 +  if (cd->insn_table.init_entries)
24701 +    free ((CGEN_INSN *) cd->insn_table.init_entries);
24702 +
24703 +  if (cd->hw_table.entries)
24704 +    free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
24705 +
24706 +  if (cd->operand_table.entries)
24707 +    free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
24708 +
24709 +  free (cd);
24710 +}
24711 +
24712 --- /dev/null
24713 +++ b/opcodes/ubicom32-desc.h
24714 @@ -0,0 +1,369 @@
24715 +/* CPU data header for ubicom32.
24716 +
24717 +THIS FILE IS MACHINE GENERATED WITH CGEN.
24718 +
24719 +Copyright 1996-2007 Free Software Foundation, Inc.
24720 +
24721 +This file is part of the GNU Binutils and/or GDB, the GNU debugger.
24722 +
24723 +   This file is free software; you can redistribute it and/or modify
24724 +   it under the terms of the GNU General Public License as published by
24725 +   the Free Software Foundation; either version 3, or (at your option)
24726 +   any later version.
24727 +
24728 +   It is distributed in the hope that it will be useful, but WITHOUT
24729 +   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
24730 +   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
24731 +   License for more details.
24732 +
24733 +   You should have received a copy of the GNU General Public License along
24734 +   with this program; if not, write to the Free Software Foundation, Inc.,
24735 +   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
24736 +
24737 +*/
24738 +
24739 +#ifndef UBICOM32_CPU_H
24740 +#define UBICOM32_CPU_H
24741 +
24742 +#include "opcode/cgen-bitset.h"
24743 +
24744 +#define CGEN_ARCH ubicom32
24745 +
24746 +/* Given symbol S, return ubicom32_cgen_<S>.  */
24747 +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
24748 +#define CGEN_SYM(s) ubicom32##_cgen_##s
24749 +#else
24750 +#define CGEN_SYM(s) ubicom32/**/_cgen_/**/s
24751 +#endif
24752 +
24753 +
24754 +/* Selected cpu families.  */
24755 +#define HAVE_CPU_UBICOM32BF
24756 +
24757 +#define CGEN_INSN_LSB0_P 1
24758 +
24759 +/* Minimum size of any insn (in bytes).  */
24760 +#define CGEN_MIN_INSN_SIZE 4
24761 +
24762 +/* Maximum size of any insn (in bytes).  */
24763 +#define CGEN_MAX_INSN_SIZE 4
24764 +
24765 +#define CGEN_INT_INSN_P 1
24766 +
24767 +/* Maximum number of syntax elements in an instruction.  */
24768 +#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 27
24769 +
24770 +/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
24771 +   e.g. In "b,a foo" the ",a" is an operand.  If mnemonics have operands
24772 +   we can't hash on everything up to the space.  */
24773 +#define CGEN_MNEMONIC_OPERANDS
24774 +
24775 +/* Maximum number of fields in an instruction.  */
24776 +#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 15
24777 +
24778 +/* Enums.  */
24779 +
24780 +/* Enum declaration for insn format enums.  */
24781 +typedef enum insn_op1 {
24782 +  OP_X0, OP_UNUSED_01, OP_X2, OP_UNUSED_03
24783 + , OP_BSET, OP_BCLR, OP_DSP, OP_UNUSED_07
24784 + , OP_AND_2, OP_AND_4, OP_OR_2, OP_OR_4
24785 + , OP_XOR_2, OP_XOR_4, OP_ADD_2, OP_ADD_4
24786 + , OP_ADDC, OP_SUB_2, OP_SUB_4, OP_SUBC
24787 + , OP_PXBLEND, OP_PXVI, OP_PXADDS, OP_UNUSED_17
24788 + , OP_CMPI, OP_MOVEI, OP_JMP, OP_CALL
24789 + , OP_MOVEAI, OP_UNUSED_1D, OP_CALLI, OP_UNUSED_1F
24790 +} INSN_OP1;
24791 +
24792 +/* Enum declaration for insn x0 opcode ext enums.  */
24793 +typedef enum insn_op2 {
24794 +  OPX0_UNUSED_00, OPX0_SUSPEND, OPX0_UNUSED_02, OPX0_UNUSED_03
24795 + , OPX0_RET, OPX0_IERASE, OPX0_IREAD, OPX0_BKPT
24796 + , OPX0_UNUSED_08, OPX0_UNUSED_09, OPX0_NOT_4, OPX0_NOT_2
24797 + , OPX0_MOVE_4, OPX0_MOVE_2, OPX0_MOVEA, OPX0_MOVE_1
24798 + , OPX0_IWRITE, OPX0_UNUSED_11, OPX0_SETCSR, OPX0_UNUSED_13
24799 + , OPX0_UNUSED_14, OPX0_EXT_2, OPX0_UNUSED_16, OPX0_EXT_1
24800 + , OPX0_SWAPB_2, OPX0_SWAPB_4, OPX0_PXCNV, OPX0_PXCNV_T
24801 + , OPX0_LEA_4, OPX0_LEA_2, OPX0_PDEC, OPX0_LEA_1
24802 +} INSN_OP2;
24803 +
24804 +/* Enum declaration for insn x2 opcode ext enums.  */
24805 +typedef enum insn_opext {
24806 +  OPX2_PXHI, OPX2_MULS, OPX2_PXHI_S, OPX2_MULU
24807 + , OPX2_UNUSED_04, OPX2_MULF, OPX2_BTST, OPX2_UNUSED_07
24808 + , OPX2_CRCGEN, OPX2_MAC, OPX2_LSL_1, OPX2_LSR_1
24809 + , OPX2_ASR_1, OPX2_UNUSED_0D, OPX2_UNUSED_0E, OPX2_UNUSED_0F
24810 + , OPX2_LSL_4, OPX2_LSL_2, OPX2_LSR_4, OPX2_LSR_2
24811 + , OPX2_ASR_4, OPX2_ASR_2, OPX2_BFEXTU, OPX2_UNUSED_17
24812 + , OPX2_BFRVRS, OPX2_UNUSED_19, OPX2_SHFTD, OPX2_UNUSED_1B
24813 + , OPX2_MERGE, OPX2_UNUSED_1D, OPX2_SHMRG_2, OPX2_SHMRG_1
24814 +} INSN_OPEXT;
24815 +
24816 +/* Enum declaration for insn dsp opcode ext enums.  */
24817 +typedef enum insn_dsp_subop {
24818 +  OPDSP_MULS, OPDSP_MACS, OPDSP_MULU, OPDSP_MACU
24819 + , OPDSP_MULF, OPDSP_MACF, OPDSP_UNUSED_06, OPDSP_MACUS
24820 + , OPDSP_MULS_4, OPDSP_MSUF, OPDSP_MULU_4, OPDSP_UNUSED_0B
24821 + , OPDSP_UNUSED_0C, OPDSP_UNUSED_0D, OPDSP_UNUSED_0E, OPDSP_UNUSED_0F
24822 + , OPDSP_MADD_4, OPDSP_MADD_2, OPDSP_MSUB_4, OPDSP_MSUB_2
24823 + , OPDSP_UNUSED_14, OPDSP_UNUSED_15, OPDSP_UNUSED_16, OPDSP_UNUSED_17
24824 + , OPDSP_UNUSED_18, OPDSP_UNUSED_19, OPDSP_UNUSED_1A, OPDSP_UNUSED_1B
24825 + , OPDSP_UNUSED_1C, OPDSP_UNUSED_1D, OPDSP_UNUSED_1E, OPDSP_UNUSED_1F
24826 +} INSN_DSP_SUBOP;
24827 +
24828 +/* Enum declaration for .  */
24829 +typedef enum data_names {
24830 +  H_DR_D0, H_DR_D1, H_DR_D2, H_DR_D3
24831 + , H_DR_D4, H_DR_D5, H_DR_D6, H_DR_D7
24832 + , H_DR_D8, H_DR_D9, H_DR_D10, H_DR_D11
24833 + , H_DR_D12, H_DR_D13, H_DR_D14, H_DR_D15
24834 +} DATA_NAMES;
24835 +
24836 +/* Enum declaration for .  */
24837 +typedef enum addr_names {
24838 +  H_AR_SP = 7, H_AR_A0 = 0, H_AR_A1 = 1, H_AR_A2 = 2
24839 + , H_AR_A3 = 3, H_AR_A4 = 4, H_AR_A5 = 5, H_AR_A6 = 6
24840 + , H_AR_A7 = 7
24841 +} ADDR_NAMES;
24842 +
24843 +/* Enum declaration for .  */
24844 +typedef enum acc_names {
24845 +  ACC_LOS_ACC0, ACC_LOS_ACC1
24846 +} ACC_NAMES;
24847 +
24848 +/* Enum declaration for .  */
24849 +typedef enum spad_names {
24850 +  H_SP_SCRATCHPAD0 = 0, H_SP_SCRATCHPAD1 = 0, H_SP_SCRATCHPAD2 = 0, H_SP_SCRATCHPAD3 = 0
24851 +} SPAD_NAMES;
24852 +
24853 +/* Attributes.  */
24854 +
24855 +/* Enum declaration for machine type selection.  */
24856 +typedef enum mach_attr {
24857 +  MACH_BASE, MACH_IP3035, MACH_UBICOM32DSP, MACH_IP3023COMPATIBILITY
24858 + , MACH_UBICOM32_VER4, MACH_MAX
24859 +} MACH_ATTR;
24860 +
24861 +/* Enum declaration for instruction set selection.  */
24862 +typedef enum isa_attr {
24863 +  ISA_UBICOM32, ISA_MAX
24864 +} ISA_ATTR;
24865 +
24866 +/* Number of architecture variants.  */
24867 +#define MAX_ISAS  1
24868 +#define MAX_MACHS ((int) MACH_MAX)
24869 +
24870 +/* Ifield support.  */
24871 +
24872 +/* Ifield attribute indices.  */
24873 +
24874 +/* Enum declaration for cgen_ifld attrs.  */
24875 +typedef enum cgen_ifld_attr {
24876 +  CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
24877 + , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31
24878 + , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS
24879 +} CGEN_IFLD_ATTR;
24880 +
24881 +/* Number of non-boolean elements in cgen_ifld_attr.  */
24882 +#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
24883 +
24884 +/* cgen_ifld attribute accessor macros.  */
24885 +#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset)
24886 +#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0)
24887 +#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0)
24888 +#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0)
24889 +#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0)
24890 +#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0)
24891 +#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0)
24892 +
24893 +/* Enum declaration for ubicom32 ifield types.  */
24894 +typedef enum ifield_type {
24895 +  UBICOM32_F_NIL, UBICOM32_F_ANYOF, UBICOM32_F_D, UBICOM32_F_D_BIT10
24896 + , UBICOM32_F_D_TYPE, UBICOM32_F_D_R, UBICOM32_F_D_M, UBICOM32_F_D_I4_1
24897 + , UBICOM32_F_D_I4_2, UBICOM32_F_D_I4_4, UBICOM32_F_D_AN, UBICOM32_F_D_DIRECT
24898 + , UBICOM32_F_D_IMM8, UBICOM32_F_D_IMM7_T, UBICOM32_F_D_IMM7_B, UBICOM32_F_D_IMM7_1
24899 + , UBICOM32_F_D_IMM7_2, UBICOM32_F_D_IMM7_4, UBICOM32_F_S1, UBICOM32_F_S1_BIT10
24900 + , UBICOM32_F_S1_TYPE, UBICOM32_F_S1_R, UBICOM32_F_S1_M, UBICOM32_F_S1_I4_1
24901 + , UBICOM32_F_S1_I4_2, UBICOM32_F_S1_I4_4, UBICOM32_F_S1_AN, UBICOM32_F_S1_DIRECT
24902 + , UBICOM32_F_S1_IMM8, UBICOM32_F_S1_IMM7_T, UBICOM32_F_S1_IMM7_B, UBICOM32_F_S1_IMM7_1
24903 + , UBICOM32_F_S1_IMM7_2, UBICOM32_F_S1_IMM7_4, UBICOM32_F_OP1, UBICOM32_F_OP2
24904 + , UBICOM32_F_BIT26, UBICOM32_F_OPEXT, UBICOM32_F_COND, UBICOM32_F_IMM16_1
24905 + , UBICOM32_F_IMM16_2, UBICOM32_F_O21, UBICOM32_F_O23_21, UBICOM32_F_O20_0
24906 + , UBICOM32_F_O24, UBICOM32_F_IMM23_21, UBICOM32_F_IMM24, UBICOM32_F_O15_13
24907 + , UBICOM32_F_O12_8, UBICOM32_F_O7_5, UBICOM32_F_O4_0, UBICOM32_F_O16
24908 + , UBICOM32_F_AN, UBICOM32_F_AM, UBICOM32_F_DN, UBICOM32_F_BIT5
24909 + , UBICOM32_F_P, UBICOM32_F_C, UBICOM32_F_INT, UBICOM32_F_DSP_C
24910 + , UBICOM32_F_DSP_T, UBICOM32_F_DSP_S2_SEL, UBICOM32_F_DSP_R, UBICOM32_F_DSP_DESTA
24911 + , UBICOM32_F_DSP_B15, UBICOM32_F_DSP_S2, UBICOM32_F_DSP_J, UBICOM32_F_S2
24912 + , UBICOM32_F_B15, UBICOM32_F_MAX
24913 +} IFIELD_TYPE;
24914 +
24915 +#define MAX_IFLD ((int) UBICOM32_F_MAX)
24916 +
24917 +/* Hardware attribute indices.  */
24918 +
24919 +/* Enum declaration for cgen_hw attrs.  */
24920 +typedef enum cgen_hw_attr {
24921 +  CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
24922 + , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
24923 +} CGEN_HW_ATTR;
24924 +
24925 +/* Number of non-boolean elements in cgen_hw_attr.  */
24926 +#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
24927 +
24928 +/* cgen_hw attribute accessor macros.  */
24929 +#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset)
24930 +#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0)
24931 +#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0)
24932 +#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0)
24933 +#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0)
24934 +
24935 +/* Enum declaration for ubicom32 hardware types.  */
24936 +typedef enum cgen_hw_type {
24937 +  HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
24938 + , HW_H_IADDR, HW_H_GLOBAL_CONTROL, HW_H_MT_BREAK, HW_H_MT_ACTIVE
24939 + , HW_H_MT_ENABLE, HW_H_MT_PRIORITY, HW_H_MT_SCHEDULE, HW_H_IRQ_STATUS_0
24940 + , HW_H_IRQ_STATUS_1, HW_H_DR, HW_H_S1_DR, HW_H_AR
24941 + , HW_H_AR_INC, HW_H_AR_INC_FLAG, HW_H_MAC_HI, HW_H_MAC_LO
24942 + , HW_H_SRC_3, HW_H_CSR, HW_H_IREAD, HW_H_ACC1_HI
24943 + , HW_H_ACC1_LO, HW_H_PC, HW_H_NBIT_16, HW_H_ZBIT_16
24944 + , HW_H_VBIT_16, HW_H_CBIT_16, HW_H_NBIT_32, HW_H_ZBIT_32
24945 + , HW_H_VBIT_32, HW_H_CBIT_32, HW_H_CC, HW_H_C
24946 + , HW_H_P, HW_H_DSP_C, HW_H_DSP_DEST_A, HW_H_DSP_T
24947 + , HW_H_DSP_T_ADDSUB, HW_H_DSP_S2_ACC_REG_MUL, HW_H_DSP_S2_ACC_REG_ADDSUB, HW_H_SP
24948 + , HW_MAX
24949 +} CGEN_HW_TYPE;
24950 +
24951 +#define MAX_HW ((int) HW_MAX)
24952 +
24953 +/* Operand attribute indices.  */
24954 +
24955 +/* Enum declaration for cgen_operand attrs.  */
24956 +typedef enum cgen_operand_attr {
24957 +  CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
24958 + , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
24959 + , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS
24960 +} CGEN_OPERAND_ATTR;
24961 +
24962 +/* Number of non-boolean elements in cgen_operand_attr.  */
24963 +#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
24964 +
24965 +/* cgen_operand attribute accessor macros.  */
24966 +#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
24967 +#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0)
24968 +#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0)
24969 +#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0)
24970 +#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0)
24971 +#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0)
24972 +#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0)
24973 +#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0)
24974 +#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0)
24975 +
24976 +/* Enum declaration for ubicom32 operand types.  */
24977 +typedef enum cgen_operand_type {
24978 +  UBICOM32_OPERAND_PC, UBICOM32_OPERAND_S2, UBICOM32_OPERAND_SRC3, UBICOM32_OPERAND_OFFSET24
24979 + , UBICOM32_OPERAND_AN, UBICOM32_OPERAND_CC, UBICOM32_OPERAND_C, UBICOM32_OPERAND_P
24980 + , UBICOM32_OPERAND_AM, UBICOM32_OPERAND_DN, UBICOM32_OPERAND_INTERRUPT, UBICOM32_OPERAND_IMM16_1
24981 + , UBICOM32_OPERAND_X_OP2, UBICOM32_OPERAND_X_BIT26, UBICOM32_OPERAND_X_S1, UBICOM32_OPERAND_X_D
24982 + , UBICOM32_OPERAND_X_DN, UBICOM32_OPERAND_MACHI, UBICOM32_OPERAND_MACLO, UBICOM32_OPERAND_ACC1HI
24983 + , UBICOM32_OPERAND_ACC1LO, UBICOM32_OPERAND_IRQ_0, UBICOM32_OPERAND_IRQ_1, UBICOM32_OPERAND_IREAD
24984 + , UBICOM32_OPERAND_OPC1, UBICOM32_OPERAND_OPC2, UBICOM32_OPERAND_AN_INC, UBICOM32_OPERAND_DSP_C
24985 + , UBICOM32_OPERAND_DSP_T, UBICOM32_OPERAND_DSP_DESTA, UBICOM32_OPERAND_DSP_S2_SEL, UBICOM32_OPERAND_DSP_S2_DATA_REG
24986 + , UBICOM32_OPERAND_DSP_S2_ACC_REG_MUL, UBICOM32_OPERAND_DSP_S2_ACC_REG_ADDSUB, UBICOM32_OPERAND_DSP_S2_DATA_REG_ADDSUB, UBICOM32_OPERAND_DSP_T_ADDSUB
24987 + , UBICOM32_OPERAND_BIT5, UBICOM32_OPERAND_BIT5_ADDSUB, UBICOM32_OPERAND_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_OPERAND_DSP_SRC2_REG_ACC_REG_ADDSUB
24988 + , UBICOM32_OPERAND_DSP_SRC2_DATA_REG, UBICOM32_OPERAND_DSP_SRC2_DATA_REG_ADDSUB, UBICOM32_OPERAND_DSP_SRC2_DATA_REG_ADDSUB2, UBICOM32_OPERAND_DSP_IMM_BIT5
24989 + , UBICOM32_OPERAND_DSP_IMM_BIT5_ADDSUB, UBICOM32_OPERAND_DSP_IMM_BIT5_ADDSUB2, UBICOM32_OPERAND_IMM_BIT5, UBICOM32_OPERAND_DYN_REG
24990 + , UBICOM32_OPERAND_OP3, UBICOM32_OPERAND_DSP_SRC2_MUL, UBICOM32_OPERAND_DSP_COMPATIBILITY_SRC2_MUL, UBICOM32_OPERAND_DSP_SRC2_ADDSUB
24991 + , UBICOM32_OPERAND_DSP_SRC2_ADDSUB2, UBICOM32_OPERAND_OFFSET21, UBICOM32_OPERAND_OFFSET16, UBICOM32_OPERAND_IMM24
24992 + , UBICOM32_OPERAND_NBIT_16, UBICOM32_OPERAND_VBIT_16, UBICOM32_OPERAND_ZBIT_16, UBICOM32_OPERAND_CBIT_16
24993 + , UBICOM32_OPERAND_NBIT_32, UBICOM32_OPERAND_VBIT_32, UBICOM32_OPERAND_ZBIT_32, UBICOM32_OPERAND_CBIT_32
24994 + , UBICOM32_OPERAND_S1_IMM7_1, UBICOM32_OPERAND_S1_IMM7_2, UBICOM32_OPERAND_S1_IMM7_4, UBICOM32_OPERAND_PDEC_S1_IMM7_4
24995 + , UBICOM32_OPERAND_S1_IMM8, UBICOM32_OPERAND_S1_AN, UBICOM32_OPERAND_S1_R, UBICOM32_OPERAND_S1_AN_INC
24996 + , UBICOM32_OPERAND_S1_I4_1, UBICOM32_OPERAND_S1_I4_2, UBICOM32_OPERAND_S1_I4_4, UBICOM32_OPERAND_S1_INDIRECT_1
24997 + , UBICOM32_OPERAND_S1_INDIRECT_2, UBICOM32_OPERAND_S1_INDIRECT_4, UBICOM32_OPERAND_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_OPERAND_S1_INDIRECT_WITH_OFFSET_2
24998 + , UBICOM32_OPERAND_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_OPERAND_S1_INDIRECT_WITH_INDEX_1, UBICOM32_OPERAND_S1_INDIRECT_WITH_INDEX_2, UBICOM32_OPERAND_S1_INDIRECT_WITH_INDEX_4
24999 + , UBICOM32_OPERAND_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_OPERAND_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_OPERAND_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_OPERAND_S1_INDIRECT_WITH_PRE_INCREMENT_1
25000 + , UBICOM32_OPERAND_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_OPERAND_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_OPERAND_S1_DIRECT_ADDR, UBICOM32_OPERAND_S1_DIRECT
25001 + , UBICOM32_OPERAND_S1_IMMEDIATE, UBICOM32_OPERAND_S1_1, UBICOM32_OPERAND_S1_2, UBICOM32_OPERAND_S1_4
25002 + , UBICOM32_OPERAND_S1_EA_INDIRECT, UBICOM32_OPERAND_S1_EA_INDIRECT_WITH_OFFSET_1, UBICOM32_OPERAND_S1_EA_INDIRECT_WITH_OFFSET_2, UBICOM32_OPERAND_S1_EA_INDIRECT_WITH_OFFSET_4
25003 + , UBICOM32_OPERAND_S1_EA_INDIRECT_WITH_INDEX_1, UBICOM32_OPERAND_S1_EA_INDIRECT_WITH_INDEX_2, UBICOM32_OPERAND_S1_EA_INDIRECT_WITH_INDEX_4, UBICOM32_OPERAND_S1_EA_INDIRECT_WITH_POST_INCREMENT_1
25004 + , UBICOM32_OPERAND_S1_EA_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_OPERAND_S1_EA_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_OPERAND_S1_EA_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_OPERAND_S1_EA_INDIRECT_WITH_PRE_INCREMENT_2
25005 + , UBICOM32_OPERAND_S1_EA_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_OPERAND_S1_EA_IMMEDIATE, UBICOM32_OPERAND_S1_EA_DIRECT, UBICOM32_OPERAND_S1_EA_1
25006 + , UBICOM32_OPERAND_S1_EA_2, UBICOM32_OPERAND_S1_EA_4, UBICOM32_OPERAND_S1_PEA, UBICOM32_OPERAND_PDEC_S1_EA_INDIRECT_WITH_OFFSET_4
25007 + , UBICOM32_OPERAND_PDEC_PEA_S1, UBICOM32_OPERAND_D_IMM7_1, UBICOM32_OPERAND_D_IMM7_2, UBICOM32_OPERAND_D_IMM7_4
25008 + , UBICOM32_OPERAND_D_IMM8, UBICOM32_OPERAND_D_AN, UBICOM32_OPERAND_D_R, UBICOM32_OPERAND_D_AN_INC
25009 + , UBICOM32_OPERAND_D_I4_1, UBICOM32_OPERAND_D_I4_2, UBICOM32_OPERAND_D_I4_4, UBICOM32_OPERAND_D_INDIRECT_1
25010 + , UBICOM32_OPERAND_D_INDIRECT_2, UBICOM32_OPERAND_D_INDIRECT_4, UBICOM32_OPERAND_D_INDIRECT_WITH_OFFSET_1, UBICOM32_OPERAND_D_INDIRECT_WITH_OFFSET_2
25011 + , UBICOM32_OPERAND_D_INDIRECT_WITH_OFFSET_4, UBICOM32_OPERAND_D_INDIRECT_WITH_INDEX_1, UBICOM32_OPERAND_D_INDIRECT_WITH_INDEX_2, UBICOM32_OPERAND_D_INDIRECT_WITH_INDEX_4
25012 + , UBICOM32_OPERAND_D_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_OPERAND_D_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_OPERAND_D_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_OPERAND_D_INDIRECT_WITH_PRE_INCREMENT_1
25013 + , UBICOM32_OPERAND_D_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_OPERAND_D_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_OPERAND_D_DIRECT_ADDR, UBICOM32_OPERAND_D_DIRECT
25014 + , UBICOM32_OPERAND_D_IMMEDIATE_1, UBICOM32_OPERAND_D_IMMEDIATE_2, UBICOM32_OPERAND_D_IMMEDIATE_4, UBICOM32_OPERAND_D_1
25015 + , UBICOM32_OPERAND_D_2, UBICOM32_OPERAND_D_4, UBICOM32_OPERAND_D_PEA_INDIRECT, UBICOM32_OPERAND_D_PEA_INDIRECT_WITH_OFFSET
25016 + , UBICOM32_OPERAND_D_PEA_INDIRECT_WITH_POST_INCREMENT, UBICOM32_OPERAND_D_PEA_INDIRECT_WITH_PRE_INCREMENT, UBICOM32_OPERAND_D_PEA_INDIRECT_WITH_INDEX, UBICOM32_OPERAND_D_PEA
25017 + , UBICOM32_OPERAND_IMM16_2, UBICOM32_OPERAND_MAX
25018 +} CGEN_OPERAND_TYPE;
25019 +
25020 +/* Number of operands types.  */
25021 +#define MAX_OPERANDS 157
25022 +
25023 +/* Maximum number of operands referenced by any insn.  */
25024 +#define MAX_OPERAND_INSTANCES 8
25025 +
25026 +/* Insn attribute indices.  */
25027 +
25028 +/* Enum declaration for cgen_insn attrs.  */
25029 +typedef enum cgen_insn_attr {
25030 +  CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
25031 + , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
25032 + , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31
25033 + , CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS
25034 +} CGEN_INSN_ATTR;
25035 +
25036 +/* Number of non-boolean elements in cgen_insn_attr.  */
25037 +#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
25038 +
25039 +/* cgen_insn attribute accessor macros.  */
25040 +#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)
25041 +#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0)
25042 +#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0)
25043 +#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0)
25044 +#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0)
25045 +#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0)
25046 +#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0)
25047 +#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0)
25048 +#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0)
25049 +#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0)
25050 +#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0)
25051 +
25052 +/* cgen.h uses things we just defined.  */
25053 +#include "opcode/cgen.h"
25054 +
25055 +extern const struct cgen_ifld ubicom32_cgen_ifld_table[];
25056 +
25057 +/* Attributes.  */
25058 +extern const CGEN_ATTR_TABLE ubicom32_cgen_hardware_attr_table[];
25059 +extern const CGEN_ATTR_TABLE ubicom32_cgen_ifield_attr_table[];
25060 +extern const CGEN_ATTR_TABLE ubicom32_cgen_operand_attr_table[];
25061 +extern const CGEN_ATTR_TABLE ubicom32_cgen_insn_attr_table[];
25062 +
25063 +/* Hardware decls.  */
25064 +
25065 +extern CGEN_KEYWORD ubicom32_cgen_opval_data_names;
25066 +extern CGEN_KEYWORD ubicom32_cgen_opval_data_names;
25067 +extern CGEN_KEYWORD ubicom32_cgen_opval_addr_names;
25068 +extern CGEN_KEYWORD ubicom32_cgen_opval_h_cc;
25069 +extern CGEN_KEYWORD ubicom32_cgen_opval_h_C;
25070 +extern CGEN_KEYWORD ubicom32_cgen_opval_h_P;
25071 +extern CGEN_KEYWORD ubicom32_cgen_opval_h_DSP_C;
25072 +extern CGEN_KEYWORD ubicom32_cgen_opval_h_DSP_Dest_A;
25073 +extern CGEN_KEYWORD ubicom32_cgen_opval_h_DSP_T;
25074 +extern CGEN_KEYWORD ubicom32_cgen_opval_h_DSP_T_addsub;
25075 +extern CGEN_KEYWORD ubicom32_cgen_opval_acc_names;
25076 +extern CGEN_KEYWORD ubicom32_cgen_opval_acc_names;
25077 +extern CGEN_KEYWORD ubicom32_cgen_opval_spad_names;
25078 +
25079 +extern const CGEN_HW_ENTRY ubicom32_cgen_hw_table[];
25080 +
25081 +
25082 +
25083 +#endif /* UBICOM32_CPU_H */
25084 --- /dev/null
25085 +++ b/opcodes/ubicom32-dis.c
25086 @@ -0,0 +1,809 @@
25087 +/* Disassembler interface for targets using CGEN. -*- C -*-
25088 +   CGEN: Cpu tools GENerator
25089 +
25090 +   THIS FILE IS MACHINE GENERATED WITH CGEN.
25091 +   - the resultant file is machine generated, cgen-dis.in isn't
25092 +
25093 +   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2007
25094 +   Free Software Foundation, Inc.
25095 +
25096 +   This file is part of libopcodes.
25097 +
25098 +   This library is free software; you can redistribute it and/or modify
25099 +   it under the terms of the GNU General Public License as published by
25100 +   the Free Software Foundation; either version 3, or (at your option)
25101 +   any later version.
25102 +
25103 +   It is distributed in the hope that it will be useful, but WITHOUT
25104 +   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
25105 +   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
25106 +   License for more details.
25107 +
25108 +   You should have received a copy of the GNU General Public License
25109 +   along with this program; if not, write to the Free Software Foundation, Inc.,
25110 +   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
25111 +
25112 +/* ??? Eventually more and more of this stuff can go to cpu-independent files.
25113 +   Keep that in mind.  */
25114 +
25115 +#include "sysdep.h"
25116 +#include <stdio.h>
25117 +#include "ansidecl.h"
25118 +#include "dis-asm.h"
25119 +#include "bfd.h"
25120 +#include "symcat.h"
25121 +#include "libiberty.h"
25122 +#include "ubicom32-desc.h"
25123 +#include "ubicom32-opc.h"
25124 +#include "opintl.h"
25125 +
25126 +/* Default text to print if an instruction isn't recognized.  */
25127 +#define UNKNOWN_INSN_MSG _("*unknown*")
25128 +
25129 +static void print_normal
25130 +  (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int);
25131 +static void print_address
25132 +  (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED;
25133 +static void print_keyword
25134 +  (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED;
25135 +static void print_insn_normal
25136 +  (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int);
25137 +static int print_insn
25138 +  (CGEN_CPU_DESC, bfd_vma,  disassemble_info *, bfd_byte *, unsigned);
25139 +static int default_print_insn
25140 +  (CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED;
25141 +static int read_insn
25142 +  (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *,
25143 +   unsigned long *);
25144 +\f
25145 +/* -- disassembler routines inserted here.  */
25146 +
25147 +/* -- dis.c */
25148 +
25149 +/* Output a signed 4 bit integer */
25150 +static void
25151 +print_imm4 (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
25152 +           PTR dis_info,
25153 +           long value,
25154 +           unsigned int attrs ATTRIBUTE_UNUSED,
25155 +           bfd_vma pc ATTRIBUTE_UNUSED,
25156 +           int length ATTRIBUTE_UNUSED)
25157 +{
25158 +  disassemble_info *info = (disassemble_info *) dis_info;
25159 +  (*info->fprintf_func) (info->stream, "%d", (int)value);
25160 +}
25161 +
25162 +/* Output an unsigned 7-bit integer */
25163 +static void
25164 +print_imm7 (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
25165 +           PTR dis_info,
25166 +           long value,
25167 +           unsigned int attrs ATTRIBUTE_UNUSED,
25168 +           bfd_vma pc ATTRIBUTE_UNUSED,
25169 +           int length ATTRIBUTE_UNUSED)
25170 +{
25171 +  disassemble_info *info = (disassemble_info *) dis_info;
25172 +  if (value != 0)
25173 +    (*info->fprintf_func) (info->stream, "%ld", value);
25174 +}
25175 +
25176 +/* Output an unsigned 7-bit integer */
25177 +static void
25178 +print_pdec_imm7 (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
25179 +                PTR dis_info,
25180 +                long value,
25181 +                unsigned int attrs ATTRIBUTE_UNUSED,
25182 +                bfd_vma pc ATTRIBUTE_UNUSED,
25183 +                int length ATTRIBUTE_UNUSED)
25184 +{
25185 +  disassemble_info *info = (disassemble_info *) dis_info;
25186 +  if (value != 0)
25187 +    {
25188 +      value = ~value;
25189 +      value ++;
25190 +      value &= 0x1fc;
25191 +      (*info->fprintf_func) (info->stream, "%ld", value);
25192 +    }
25193 +  else
25194 +    {
25195 +      (*info->fprintf_func) (info->stream, "%d", 512);
25196 +    }
25197 +}
25198 +
25199 +/* Output either a register or a 11bit literal immediate value */
25200 +static void
25201 +print_direct_addr (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
25202 +                  PTR dis_info,
25203 +                  long value,
25204 +                  unsigned int attrs ATTRIBUTE_UNUSED,
25205 +                  bfd_vma pc ATTRIBUTE_UNUSED,
25206 +                  int length ATTRIBUTE_UNUSED)
25207 +{
25208 +  disassemble_info *info = (disassemble_info *) dis_info;
25209 +  struct ubicom32_cgen_data_space_map *cur;
25210 +
25211 +  if(cd->machs & (1<<MACH_IP3035))
25212 +    {
25213 +      /* cpu is mercury */
25214 +      cur = ubicom32_cgen_data_space_map_mercury;
25215 +    }
25216 +  else
25217 +    {
25218 +      /* cpu is mars */
25219 +      cur = ubicom32_cgen_data_space_map_mars;
25220 +    }
25221 +
25222 +
25223 +  //if (value > 0x3ff)
25224 +    /* XXX: some warning? */ ;
25225 +  value &= 0x3ff;
25226 +  for (; cur->name; cur++)
25227 +    if (value == cur->address)
25228 +      {
25229 +        (*info->fprintf_func) (info->stream, "%s", cur->name);
25230 +        return;
25231 +      }
25232 +  (*info->fprintf_func) (info->stream, "#%lx", value);
25233 +}
25234 +
25235 +static void
25236 +print_imm24 (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
25237 +            PTR dis_info,
25238 +            long value,
25239 +            unsigned int attrs ATTRIBUTE_UNUSED,
25240 +            bfd_vma pc ATTRIBUTE_UNUSED,
25241 +            int length ATTRIBUTE_UNUSED)
25242 +{
25243 +  disassemble_info *info = (disassemble_info *) dis_info;
25244 +  (*info->fprintf_func) (info->stream, "%%hi(0x%08lx)", value << 7);
25245 +}
25246 +
25247 +/* -- */
25248 +
25249 +void ubicom32_cgen_print_operand
25250 +  (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int);
25251 +
25252 +/* Main entry point for printing operands.
25253 +   XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
25254 +   of dis-asm.h on cgen.h.
25255 +
25256 +   This function is basically just a big switch statement.  Earlier versions
25257 +   used tables to look up the function to use, but
25258 +   - if the table contains both assembler and disassembler functions then
25259 +     the disassembler contains much of the assembler and vice-versa,
25260 +   - there's a lot of inlining possibilities as things grow,
25261 +   - using a switch statement avoids the function call overhead.
25262 +
25263 +   This function could be moved into `print_insn_normal', but keeping it
25264 +   separate makes clear the interface between `print_insn_normal' and each of
25265 +   the handlers.  */
25266 +
25267 +void
25268 +ubicom32_cgen_print_operand (CGEN_CPU_DESC cd,
25269 +                          int opindex,
25270 +                          void * xinfo,
25271 +                          CGEN_FIELDS *fields,
25272 +                          void const *attrs ATTRIBUTE_UNUSED,
25273 +                          bfd_vma pc,
25274 +                          int length)
25275 +{
25276 +  disassemble_info *info = (disassemble_info *) xinfo;
25277 +
25278 +  switch (opindex)
25279 +    {
25280 +    case UBICOM32_OPERAND_AM :
25281 +      print_keyword (cd, info, & ubicom32_cgen_opval_addr_names, fields->f_Am, 0);
25282 +      break;
25283 +    case UBICOM32_OPERAND_AN :
25284 +      print_keyword (cd, info, & ubicom32_cgen_opval_addr_names, fields->f_An, 0);
25285 +      break;
25286 +    case UBICOM32_OPERAND_C :
25287 +      print_keyword (cd, info, & ubicom32_cgen_opval_h_C, fields->f_C, 0);
25288 +      break;
25289 +    case UBICOM32_OPERAND_DN :
25290 +      print_keyword (cd, info, & ubicom32_cgen_opval_data_names, fields->f_Dn, 0);
25291 +      break;
25292 +    case UBICOM32_OPERAND_P :
25293 +      print_keyword (cd, info, & ubicom32_cgen_opval_h_P, fields->f_P, 0);
25294 +      break;
25295 +    case UBICOM32_OPERAND_ACC1HI :
25296 +      print_normal (cd, info, 0, 0, pc, length);
25297 +      break;
25298 +    case UBICOM32_OPERAND_ACC1LO :
25299 +      print_normal (cd, info, 0, 0, pc, length);
25300 +      break;
25301 +    case UBICOM32_OPERAND_BIT5 :
25302 +      print_normal (cd, info, fields->f_bit5, 0, pc, length);
25303 +      break;
25304 +    case UBICOM32_OPERAND_BIT5_ADDSUB :
25305 +      print_normal (cd, info, fields->f_bit5, 0, pc, length);
25306 +      break;
25307 +    case UBICOM32_OPERAND_CC :
25308 +      print_keyword (cd, info, & ubicom32_cgen_opval_h_cc, fields->f_cond, 0);
25309 +      break;
25310 +    case UBICOM32_OPERAND_D_AN :
25311 +      print_keyword (cd, info, & ubicom32_cgen_opval_addr_names, fields->f_d_An, 0);
25312 +      break;
25313 +    case UBICOM32_OPERAND_D_DIRECT_ADDR :
25314 +      print_direct_addr (cd, info, fields->f_d_direct, 0, pc, length);
25315 +      break;
25316 +    case UBICOM32_OPERAND_D_I4_1 :
25317 +      print_imm4 (cd, info, fields->f_d_i4_1, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
25318 +      break;
25319 +    case UBICOM32_OPERAND_D_I4_2 :
25320 +      print_imm4 (cd, info, fields->f_d_i4_2, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
25321 +      break;
25322 +    case UBICOM32_OPERAND_D_I4_4 :
25323 +      print_imm4 (cd, info, fields->f_d_i4_4, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
25324 +      break;
25325 +    case UBICOM32_OPERAND_D_IMM7_1 :
25326 +      print_imm7 (cd, info, fields->f_d_imm7_1, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
25327 +      break;
25328 +    case UBICOM32_OPERAND_D_IMM7_2 :
25329 +      print_imm7 (cd, info, fields->f_d_imm7_2, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
25330 +      break;
25331 +    case UBICOM32_OPERAND_D_IMM7_4 :
25332 +      print_imm7 (cd, info, fields->f_d_imm7_4, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
25333 +      break;
25334 +    case UBICOM32_OPERAND_D_IMM8 :
25335 +      print_normal (cd, info, fields->f_d_imm8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
25336 +      break;
25337 +    case UBICOM32_OPERAND_D_R :
25338 +      print_keyword (cd, info, & ubicom32_cgen_opval_data_names, fields->f_d_r, 0);
25339 +      break;
25340 +    case UBICOM32_OPERAND_DSP_S2_ACC_REG_ADDSUB :
25341 +      print_keyword (cd, info, & ubicom32_cgen_opval_acc_names, fields->f_dsp_S2, 0);
25342 +      break;
25343 +    case UBICOM32_OPERAND_DSP_S2_ACC_REG_MUL :
25344 +      print_keyword (cd, info, & ubicom32_cgen_opval_acc_names, fields->f_dsp_S2, 0);
25345 +      break;
25346 +    case UBICOM32_OPERAND_DSP_S2_DATA_REG :
25347 +      print_keyword (cd, info, & ubicom32_cgen_opval_data_names, fields->f_dsp_S2, 0);
25348 +      break;
25349 +    case UBICOM32_OPERAND_DSP_S2_DATA_REG_ADDSUB :
25350 +      print_keyword (cd, info, & ubicom32_cgen_opval_data_names, fields->f_dsp_S2, 0);
25351 +      break;
25352 +    case UBICOM32_OPERAND_DSP_S2_SEL :
25353 +      print_normal (cd, info, fields->f_dsp_S2_sel, 0, pc, length);
25354 +      break;
25355 +    case UBICOM32_OPERAND_DSP_C :
25356 +      print_keyword (cd, info, & ubicom32_cgen_opval_h_DSP_C, fields->f_dsp_C, 0);
25357 +      break;
25358 +    case UBICOM32_OPERAND_DSP_DESTA :
25359 +      print_keyword (cd, info, & ubicom32_cgen_opval_h_DSP_Dest_A, fields->f_dsp_destA, 0);
25360 +      break;
25361 +    case UBICOM32_OPERAND_DSP_T :
25362 +      print_keyword (cd, info, & ubicom32_cgen_opval_h_DSP_T, fields->f_dsp_T, 0);
25363 +      break;
25364 +    case UBICOM32_OPERAND_DSP_T_ADDSUB :
25365 +      print_keyword (cd, info, & ubicom32_cgen_opval_h_DSP_T_addsub, fields->f_dsp_T, 0);
25366 +      break;
25367 +    case UBICOM32_OPERAND_IMM16_1 :
25368 +      print_normal (cd, info, fields->f_imm16_1, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
25369 +      break;
25370 +    case UBICOM32_OPERAND_IMM16_2 :
25371 +      print_normal (cd, info, fields->f_imm16_2, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
25372 +      break;
25373 +    case UBICOM32_OPERAND_IMM24 :
25374 +      print_imm24 (cd, info, fields->f_imm24, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
25375 +      break;
25376 +    case UBICOM32_OPERAND_INTERRUPT :
25377 +      print_normal (cd, info, fields->f_int, 0, pc, length);
25378 +      break;
25379 +    case UBICOM32_OPERAND_IREAD :
25380 +      print_normal (cd, info, 0, 0, pc, length);
25381 +      break;
25382 +    case UBICOM32_OPERAND_IRQ_0 :
25383 +      print_normal (cd, info, 0, 0, pc, length);
25384 +      break;
25385 +    case UBICOM32_OPERAND_IRQ_1 :
25386 +      print_normal (cd, info, 0, 0, pc, length);
25387 +      break;
25388 +    case UBICOM32_OPERAND_MACHI :
25389 +      print_normal (cd, info, 0, 0, pc, length);
25390 +      break;
25391 +    case UBICOM32_OPERAND_MACLO :
25392 +      print_normal (cd, info, 0, 0, pc, length);
25393 +      break;
25394 +    case UBICOM32_OPERAND_OFFSET16 :
25395 +      print_normal (cd, info, fields->f_o16, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
25396 +      break;
25397 +    case UBICOM32_OPERAND_OFFSET21 :
25398 +      print_address (cd, info, fields->f_o21, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
25399 +      break;
25400 +    case UBICOM32_OPERAND_OFFSET24 :
25401 +      print_address (cd, info, fields->f_o24, 0|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
25402 +      break;
25403 +    case UBICOM32_OPERAND_OPC1 :
25404 +      print_normal (cd, info, fields->f_op1, 0, pc, length);
25405 +      break;
25406 +    case UBICOM32_OPERAND_OPC2 :
25407 +      print_normal (cd, info, fields->f_op2, 0, pc, length);
25408 +      break;
25409 +    case UBICOM32_OPERAND_PDEC_S1_IMM7_4 :
25410 +      print_pdec_imm7 (cd, info, fields->f_s1_imm7_4, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
25411 +      break;
25412 +    case UBICOM32_OPERAND_S1_AN :
25413 +      print_keyword (cd, info, & ubicom32_cgen_opval_addr_names, fields->f_s1_An, 0);
25414 +      break;
25415 +    case UBICOM32_OPERAND_S1_DIRECT_ADDR :
25416 +      print_direct_addr (cd, info, fields->f_s1_direct, 0, pc, length);
25417 +      break;
25418 +    case UBICOM32_OPERAND_S1_I4_1 :
25419 +      print_imm4 (cd, info, fields->f_s1_i4_1, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
25420 +      break;
25421 +    case UBICOM32_OPERAND_S1_I4_2 :
25422 +      print_imm4 (cd, info, fields->f_s1_i4_2, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
25423 +      break;
25424 +    case UBICOM32_OPERAND_S1_I4_4 :
25425 +      print_imm4 (cd, info, fields->f_s1_i4_4, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
25426 +      break;
25427 +    case UBICOM32_OPERAND_S1_IMM7_1 :
25428 +      print_imm7 (cd, info, fields->f_s1_imm7_1, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
25429 +      break;
25430 +    case UBICOM32_OPERAND_S1_IMM7_2 :
25431 +      print_imm7 (cd, info, fields->f_s1_imm7_2, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
25432 +      break;
25433 +    case UBICOM32_OPERAND_S1_IMM7_4 :
25434 +      print_imm7 (cd, info, fields->f_s1_imm7_4, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
25435 +      break;
25436 +    case UBICOM32_OPERAND_S1_IMM8 :
25437 +      print_normal (cd, info, fields->f_s1_imm8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
25438 +      break;
25439 +    case UBICOM32_OPERAND_S1_R :
25440 +      print_keyword (cd, info, & ubicom32_cgen_opval_data_names, fields->f_s1_r, 0);
25441 +      break;
25442 +    case UBICOM32_OPERAND_S2 :
25443 +      print_keyword (cd, info, & ubicom32_cgen_opval_data_names, fields->f_s2, 0);
25444 +      break;
25445 +    case UBICOM32_OPERAND_SRC3 :
25446 +      print_normal (cd, info, 0, 0, pc, length);
25447 +      break;
25448 +    case UBICOM32_OPERAND_X_BIT26 :
25449 +      print_normal (cd, info, fields->f_bit26, 0, pc, length);
25450 +      break;
25451 +    case UBICOM32_OPERAND_X_D :
25452 +      print_normal (cd, info, fields->f_d, 0, pc, length);
25453 +      break;
25454 +    case UBICOM32_OPERAND_X_DN :
25455 +      print_normal (cd, info, fields->f_Dn, 0, pc, length);
25456 +      break;
25457 +    case UBICOM32_OPERAND_X_OP2 :
25458 +      print_normal (cd, info, fields->f_op2, 0, pc, length);
25459 +      break;
25460 +    case UBICOM32_OPERAND_X_S1 :
25461 +      print_normal (cd, info, fields->f_s1, 0, pc, length);
25462 +      break;
25463 +
25464 +    default :
25465 +      /* xgettext:c-format */
25466 +      fprintf (stderr, _("Unrecognized field %d while printing insn.\n"),
25467 +              opindex);
25468 +    abort ();
25469 +  }
25470 +}
25471 +
25472 +cgen_print_fn * const ubicom32_cgen_print_handlers[] = 
25473 +{
25474 +  print_insn_normal,
25475 +};
25476 +
25477 +
25478 +void
25479 +ubicom32_cgen_init_dis (CGEN_CPU_DESC cd)
25480 +{
25481 +  ubicom32_cgen_init_opcode_table (cd);
25482 +  ubicom32_cgen_init_ibld_table (cd);
25483 +  cd->print_handlers = & ubicom32_cgen_print_handlers[0];
25484 +  cd->print_operand = ubicom32_cgen_print_operand;
25485 +}
25486 +
25487 +\f
25488 +/* Default print handler.  */
25489 +
25490 +static void
25491 +print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
25492 +             void *dis_info,
25493 +             long value,
25494 +             unsigned int attrs,
25495 +             bfd_vma pc ATTRIBUTE_UNUSED,
25496 +             int length ATTRIBUTE_UNUSED)
25497 +{
25498 +  disassemble_info *info = (disassemble_info *) dis_info;
25499 +
25500 +#ifdef CGEN_PRINT_NORMAL
25501 +  CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length);
25502 +#endif
25503 +
25504 +  /* Print the operand as directed by the attributes.  */
25505 +  if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
25506 +    ; /* nothing to do */
25507 +  else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
25508 +    (*info->fprintf_func) (info->stream, "%ld", value);
25509 +  else
25510 +    (*info->fprintf_func) (info->stream, "0x%lx", value);
25511 +}
25512 +
25513 +/* Default address handler.  */
25514 +
25515 +static void
25516 +print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
25517 +              void *dis_info,
25518 +              bfd_vma value,
25519 +              unsigned int attrs,
25520 +              bfd_vma pc ATTRIBUTE_UNUSED,
25521 +              int length ATTRIBUTE_UNUSED)
25522 +{
25523 +  disassemble_info *info = (disassemble_info *) dis_info;
25524 +
25525 +#ifdef CGEN_PRINT_ADDRESS
25526 +  CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length);
25527 +#endif
25528 +
25529 +  /* Print the operand as directed by the attributes.  */
25530 +  if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
25531 +    ; /* Nothing to do.  */
25532 +  else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
25533 +    (*info->print_address_func) (value, info);
25534 +  else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
25535 +    (*info->print_address_func) (value, info);
25536 +  else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
25537 +    (*info->fprintf_func) (info->stream, "%ld", (long) value);
25538 +  else
25539 +    (*info->fprintf_func) (info->stream, "0x%lx", (long) value);
25540 +}
25541 +
25542 +/* Keyword print handler.  */
25543 +
25544 +static void
25545 +print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
25546 +              void *dis_info,
25547 +              CGEN_KEYWORD *keyword_table,
25548 +              long value,
25549 +              unsigned int attrs ATTRIBUTE_UNUSED)
25550 +{
25551 +  disassemble_info *info = (disassemble_info *) dis_info;
25552 +  const CGEN_KEYWORD_ENTRY *ke;
25553 +
25554 +  ke = cgen_keyword_lookup_value (keyword_table, value);
25555 +  if (ke != NULL)
25556 +    (*info->fprintf_func) (info->stream, "%s", ke->name);
25557 +  else
25558 +    (*info->fprintf_func) (info->stream, "???");
25559 +}
25560 +\f
25561 +/* Default insn printer.
25562 +
25563 +   DIS_INFO is defined as `void *' so the disassembler needn't know anything
25564 +   about disassemble_info.  */
25565 +
25566 +static void
25567 +print_insn_normal (CGEN_CPU_DESC cd,
25568 +                  void *dis_info,
25569 +                  const CGEN_INSN *insn,
25570 +                  CGEN_FIELDS *fields,
25571 +                  bfd_vma pc,
25572 +                  int length)
25573 +{
25574 +  const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
25575 +  disassemble_info *info = (disassemble_info *) dis_info;
25576 +  const CGEN_SYNTAX_CHAR_TYPE *syn;
25577 +
25578 +  CGEN_INIT_PRINT (cd);
25579 +
25580 +  for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
25581 +    {
25582 +      if (CGEN_SYNTAX_MNEMONIC_P (*syn))
25583 +       {
25584 +         (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
25585 +         continue;
25586 +       }
25587 +      if (CGEN_SYNTAX_CHAR_P (*syn))
25588 +       {
25589 +         (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
25590 +         continue;
25591 +       }
25592 +
25593 +      /* We have an operand.  */
25594 +      ubicom32_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
25595 +                                fields, CGEN_INSN_ATTRS (insn), pc, length);
25596 +    }
25597 +}
25598 +\f
25599 +/* Subroutine of print_insn. Reads an insn into the given buffers and updates
25600 +   the extract info.
25601 +   Returns 0 if all is well, non-zero otherwise.  */
25602 +
25603 +static int
25604 +read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
25605 +          bfd_vma pc,
25606 +          disassemble_info *info,
25607 +          bfd_byte *buf,
25608 +          int buflen,
25609 +          CGEN_EXTRACT_INFO *ex_info,
25610 +          unsigned long *insn_value)
25611 +{
25612 +  int status = (*info->read_memory_func) (pc, buf, buflen, info);
25613 +
25614 +  if (status != 0)
25615 +    {
25616 +      (*info->memory_error_func) (status, pc, info);
25617 +      return -1;
25618 +    }
25619 +
25620 +  ex_info->dis_info = info;
25621 +  ex_info->valid = (1 << buflen) - 1;
25622 +  ex_info->insn_bytes = buf;
25623 +
25624 +  *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG);
25625 +  return 0;
25626 +}
25627 +
25628 +/* Utility to print an insn.
25629 +   BUF is the base part of the insn, target byte order, BUFLEN bytes long.
25630 +   The result is the size of the insn in bytes or zero for an unknown insn
25631 +   or -1 if an error occurs fetching data (memory_error_func will have
25632 +   been called).  */
25633 +
25634 +static int
25635 +print_insn (CGEN_CPU_DESC cd,
25636 +           bfd_vma pc,
25637 +           disassemble_info *info,
25638 +           bfd_byte *buf,
25639 +           unsigned int buflen)
25640 +{
25641 +  CGEN_INSN_INT insn_value;
25642 +  const CGEN_INSN_LIST *insn_list;
25643 +  CGEN_EXTRACT_INFO ex_info;
25644 +  int basesize;
25645 +
25646 +  /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
25647 +  basesize = cd->base_insn_bitsize < buflen * 8 ?
25648 +                                     cd->base_insn_bitsize : buflen * 8;
25649 +  insn_value = cgen_get_insn_value (cd, buf, basesize);
25650 +
25651 +
25652 +  /* Fill in ex_info fields like read_insn would.  Don't actually call
25653 +     read_insn, since the incoming buffer is already read (and possibly
25654 +     modified a la m32r).  */
25655 +  ex_info.valid = (1 << buflen) - 1;
25656 +  ex_info.dis_info = info;
25657 +  ex_info.insn_bytes = buf;
25658 +
25659 +  /* The instructions are stored in hash lists.
25660 +     Pick the first one and keep trying until we find the right one.  */
25661 +
25662 +  insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value);
25663 +  while (insn_list != NULL)
25664 +    {
25665 +      const CGEN_INSN *insn = insn_list->insn;
25666 +      CGEN_FIELDS fields;
25667 +      int length;
25668 +      unsigned long insn_value_cropped;
25669 +
25670 +#ifdef CGEN_VALIDATE_INSN_SUPPORTED 
25671 +      /* Not needed as insn shouldn't be in hash lists if not supported.  */
25672 +      /* Supported by this cpu?  */
25673 +      if (! ubicom32_cgen_insn_supported (cd, insn))
25674 +        {
25675 +          insn_list = CGEN_DIS_NEXT_INSN (insn_list);
25676 +         continue;
25677 +        }
25678 +#endif
25679 +
25680 +      /* Basic bit mask must be correct.  */
25681 +      /* ??? May wish to allow target to defer this check until the extract
25682 +        handler.  */
25683 +
25684 +      /* Base size may exceed this instruction's size.  Extract the
25685 +         relevant part from the buffer. */
25686 +      if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
25687 +         (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
25688 +       insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn), 
25689 +                                          info->endian == BFD_ENDIAN_BIG);
25690 +      else
25691 +       insn_value_cropped = insn_value;
25692 +
25693 +      if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn))
25694 +         == CGEN_INSN_BASE_VALUE (insn))
25695 +       {
25696 +         /* Printing is handled in two passes.  The first pass parses the
25697 +            machine insn and extracts the fields.  The second pass prints
25698 +            them.  */
25699 +
25700 +         /* Make sure the entire insn is loaded into insn_value, if it
25701 +            can fit.  */
25702 +         if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) &&
25703 +             (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
25704 +           {
25705 +             unsigned long full_insn_value;
25706 +             int rc = read_insn (cd, pc, info, buf,
25707 +                                 CGEN_INSN_BITSIZE (insn) / 8,
25708 +                                 & ex_info, & full_insn_value);
25709 +             if (rc != 0)
25710 +               return rc;
25711 +             length = CGEN_EXTRACT_FN (cd, insn)
25712 +               (cd, insn, &ex_info, full_insn_value, &fields, pc);
25713 +           }
25714 +         else
25715 +           length = CGEN_EXTRACT_FN (cd, insn)
25716 +             (cd, insn, &ex_info, insn_value_cropped, &fields, pc);
25717 +
25718 +         /* Length < 0 -> error.  */
25719 +         if (length < 0)
25720 +           return length;
25721 +         if (length > 0)
25722 +           {
25723 +             CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
25724 +             /* Length is in bits, result is in bytes.  */
25725 +             return length / 8;
25726 +           }
25727 +       }
25728 +
25729 +      insn_list = CGEN_DIS_NEXT_INSN (insn_list);
25730 +    }
25731 +
25732 +  return 0;
25733 +}
25734 +
25735 +/* Default value for CGEN_PRINT_INSN.
25736 +   The result is the size of the insn in bytes or zero for an unknown insn
25737 +   or -1 if an error occured fetching bytes.  */
25738 +
25739 +#ifndef CGEN_PRINT_INSN
25740 +#define CGEN_PRINT_INSN default_print_insn
25741 +#endif
25742 +
25743 +static int
25744 +default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
25745 +{
25746 +  bfd_byte buf[CGEN_MAX_INSN_SIZE];
25747 +  int buflen;
25748 +  int status;
25749 +
25750 +  /* Attempt to read the base part of the insn.  */
25751 +  buflen = cd->base_insn_bitsize / 8;
25752 +  status = (*info->read_memory_func) (pc, buf, buflen, info);
25753 +
25754 +  /* Try again with the minimum part, if min < base.  */
25755 +  if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
25756 +    {
25757 +      buflen = cd->min_insn_bitsize / 8;
25758 +      status = (*info->read_memory_func) (pc, buf, buflen, info);
25759 +    }
25760 +
25761 +  if (status != 0)
25762 +    {
25763 +      (*info->memory_error_func) (status, pc, info);
25764 +      return -1;
25765 +    }
25766 +
25767 +  return print_insn (cd, pc, info, buf, buflen);
25768 +}
25769 +
25770 +/* Main entry point.
25771 +   Print one instruction from PC on INFO->STREAM.
25772 +   Return the size of the instruction (in bytes).  */
25773 +
25774 +typedef struct cpu_desc_list
25775 +{
25776 +  struct cpu_desc_list *next;
25777 +  CGEN_BITSET *isa;
25778 +  int mach;
25779 +  int endian;
25780 +  CGEN_CPU_DESC cd;
25781 +} cpu_desc_list;
25782 +
25783 +int
25784 +print_insn_ubicom32 (bfd_vma pc, disassemble_info *info)
25785 +{
25786 +  static cpu_desc_list *cd_list = 0;
25787 +  cpu_desc_list *cl = 0;
25788 +  static CGEN_CPU_DESC cd = 0;
25789 +  static CGEN_BITSET *prev_isa;
25790 +  static int prev_mach;
25791 +  static int prev_endian;
25792 +  int length;
25793 +  CGEN_BITSET *isa;
25794 +  int mach;
25795 +  int endian = (info->endian == BFD_ENDIAN_BIG
25796 +               ? CGEN_ENDIAN_BIG
25797 +               : CGEN_ENDIAN_LITTLE);
25798 +  enum bfd_architecture arch;
25799 +
25800 +  /* ??? gdb will set mach but leave the architecture as "unknown" */
25801 +#ifndef CGEN_BFD_ARCH
25802 +#define CGEN_BFD_ARCH bfd_arch_ubicom32
25803 +#endif
25804 +  arch = info->arch;
25805 +  if (arch == bfd_arch_unknown)
25806 +    arch = CGEN_BFD_ARCH;
25807 +   
25808 +  /* There's no standard way to compute the machine or isa number
25809 +     so we leave it to the target.  */
25810 +#ifdef CGEN_COMPUTE_MACH
25811 +  mach = CGEN_COMPUTE_MACH (info);
25812 +#else
25813 +  mach = info->mach;
25814 +#endif
25815 +
25816 +#ifdef CGEN_COMPUTE_ISA
25817 +  {
25818 +    static CGEN_BITSET *permanent_isa;
25819 +
25820 +    if (!permanent_isa)
25821 +      permanent_isa = cgen_bitset_create (MAX_ISAS);
25822 +    isa = permanent_isa;
25823 +    cgen_bitset_clear (isa);
25824 +    cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
25825 +  }
25826 +#else
25827 +  isa = info->insn_sets;
25828 +#endif
25829 +
25830 +  /* If we've switched cpu's, try to find a handle we've used before */
25831 +  if (cd
25832 +      && (cgen_bitset_compare (isa, prev_isa) != 0
25833 +         || mach != prev_mach
25834 +         || endian != prev_endian))
25835 +    {
25836 +      cd = 0;
25837 +      for (cl = cd_list; cl; cl = cl->next)
25838 +       {
25839 +         if (cgen_bitset_compare (cl->isa, isa) == 0 &&
25840 +             cl->mach == mach &&
25841 +             cl->endian == endian)
25842 +           {
25843 +             cd = cl->cd;
25844 +             prev_isa = cd->isas;
25845 +             break;
25846 +           }
25847 +       }
25848 +    } 
25849 +
25850 +  /* If we haven't initialized yet, initialize the opcode table.  */
25851 +  if (! cd)
25852 +    {
25853 +      const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
25854 +      const char *mach_name;
25855 +
25856 +      if (!arch_type)
25857 +       abort ();
25858 +      mach_name = arch_type->printable_name;
25859 +
25860 +      prev_isa = cgen_bitset_copy (isa);
25861 +      prev_mach = mach;
25862 +      prev_endian = endian;
25863 +      cd = ubicom32_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
25864 +                                CGEN_CPU_OPEN_BFDMACH, mach_name,
25865 +                                CGEN_CPU_OPEN_ENDIAN, prev_endian,
25866 +                                CGEN_CPU_OPEN_END);
25867 +      if (!cd)
25868 +       abort ();
25869 +
25870 +      /* Save this away for future reference.  */
25871 +      cl = xmalloc (sizeof (struct cpu_desc_list));
25872 +      cl->cd = cd;
25873 +      cl->isa = prev_isa;
25874 +      cl->mach = mach;
25875 +      cl->endian = endian;
25876 +      cl->next = cd_list;
25877 +      cd_list = cl;
25878 +
25879 +      ubicom32_cgen_init_dis (cd);
25880 +    }
25881 +
25882 +  /* We try to have as much common code as possible.
25883 +     But at this point some targets need to take over.  */
25884 +  /* ??? Some targets may need a hook elsewhere.  Try to avoid this,
25885 +     but if not possible try to move this hook elsewhere rather than
25886 +     have two hooks.  */
25887 +  length = CGEN_PRINT_INSN (cd, pc, info);
25888 +  if (length > 0)
25889 +    return length;
25890 +  if (length < 0)
25891 +    return -1;
25892 +
25893 +  (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
25894 +  return cd->default_insn_bitsize / 8;
25895 +}
25896 --- /dev/null
25897 +++ b/opcodes/ubicom32-ibld.c
25898 @@ -0,0 +1,2072 @@
25899 +/* Instruction building/extraction support for ubicom32. -*- C -*-
25900 +
25901 +   THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
25902 +   - the resultant file is machine generated, cgen-ibld.in isn't
25903 +
25904 +   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005, 2006, 2007
25905 +   Free Software Foundation, Inc.
25906 +
25907 +   This file is part of libopcodes.
25908 +
25909 +   This library is free software; you can redistribute it and/or modify
25910 +   it under the terms of the GNU General Public License as published by
25911 +   the Free Software Foundation; either version 3, or (at your option)
25912 +   any later version.
25913 +
25914 +   It is distributed in the hope that it will be useful, but WITHOUT
25915 +   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
25916 +   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
25917 +   License for more details.
25918 +
25919 +   You should have received a copy of the GNU General Public License
25920 +   along with this program; if not, write to the Free Software Foundation, Inc.,
25921 +   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
25922 +
25923 +/* ??? Eventually more and more of this stuff can go to cpu-independent files.
25924 +   Keep that in mind.  */
25925 +
25926 +#include "sysdep.h"
25927 +#include <stdio.h>
25928 +#include "ansidecl.h"
25929 +#include "dis-asm.h"
25930 +#include "bfd.h"
25931 +#include "symcat.h"
25932 +#include "ubicom32-desc.h"
25933 +#include "ubicom32-opc.h"
25934 +#include "opintl.h"
25935 +#include "safe-ctype.h"
25936 +
25937 +#undef  min
25938 +#define min(a,b) ((a) < (b) ? (a) : (b))
25939 +#undef  max
25940 +#define max(a,b) ((a) > (b) ? (a) : (b))
25941 +
25942 +/* Used by the ifield rtx function.  */
25943 +#define FLD(f) (fields->f)
25944 +
25945 +static const char * insert_normal
25946 +  (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int,
25947 +   unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR);
25948 +static const char * insert_insn_normal
25949 +  (CGEN_CPU_DESC, const CGEN_INSN *,
25950 +   CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
25951 +static int extract_normal
25952 +  (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
25953 +   unsigned int, unsigned int, unsigned int, unsigned int,
25954 +   unsigned int, unsigned int, bfd_vma, long *);
25955 +static int extract_insn_normal
25956 +  (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
25957 +   CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
25958 +#if CGEN_INT_INSN_P
25959 +static void put_insn_int_value
25960 +  (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT);
25961 +#endif
25962 +#if ! CGEN_INT_INSN_P
25963 +static CGEN_INLINE void insert_1
25964 +  (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *);
25965 +static CGEN_INLINE int fill_cache
25966 +  (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *,  int, int, bfd_vma);
25967 +static CGEN_INLINE long extract_1
25968 +  (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma);
25969 +#endif
25970 +\f
25971 +/* Operand insertion.  */
25972 +
25973 +#if ! CGEN_INT_INSN_P
25974 +
25975 +/* Subroutine of insert_normal.  */
25976 +
25977 +static CGEN_INLINE void
25978 +insert_1 (CGEN_CPU_DESC cd,
25979 +         unsigned long value,
25980 +         int start,
25981 +         int length,
25982 +         int word_length,
25983 +         unsigned char *bufp)
25984 +{
25985 +  unsigned long x,mask;
25986 +  int shift;
25987 +
25988 +  x = cgen_get_insn_value (cd, bufp, word_length);
25989 +
25990 +  /* Written this way to avoid undefined behaviour.  */
25991 +  mask = (((1L << (length - 1)) - 1) << 1) | 1;
25992 +  if (CGEN_INSN_LSB0_P)
25993 +    shift = (start + 1) - length;
25994 +  else
25995 +    shift = (word_length - (start + length));
25996 +  x = (x & ~(mask << shift)) | ((value & mask) << shift);
25997 +
25998 +  cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x);
25999 +}
26000 +
26001 +#endif /* ! CGEN_INT_INSN_P */
26002 +
26003 +/* Default insertion routine.
26004 +
26005 +   ATTRS is a mask of the boolean attributes.
26006 +   WORD_OFFSET is the offset in bits from the start of the insn of the value.
26007 +   WORD_LENGTH is the length of the word in bits in which the value resides.
26008 +   START is the starting bit number in the word, architecture origin.
26009 +   LENGTH is the length of VALUE in bits.
26010 +   TOTAL_LENGTH is the total length of the insn in bits.
26011 +
26012 +   The result is an error message or NULL if success.  */
26013 +
26014 +/* ??? This duplicates functionality with bfd's howto table and
26015 +   bfd_install_relocation.  */
26016 +/* ??? This doesn't handle bfd_vma's.  Create another function when
26017 +   necessary.  */
26018 +
26019 +static const char *
26020 +insert_normal (CGEN_CPU_DESC cd,
26021 +              long value,
26022 +              unsigned int attrs,
26023 +              unsigned int word_offset,
26024 +              unsigned int start,
26025 +              unsigned int length,
26026 +              unsigned int word_length,
26027 +              unsigned int total_length,
26028 +              CGEN_INSN_BYTES_PTR buffer)
26029 +{
26030 +  static char errbuf[100];
26031 +  /* Written this way to avoid undefined behaviour.  */
26032 +  unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1;
26033 +
26034 +  /* If LENGTH is zero, this operand doesn't contribute to the value.  */
26035 +  if (length == 0)
26036 +    return NULL;
26037 +
26038 +  if (word_length > 32)
26039 +    abort ();
26040 +
26041 +  /* For architectures with insns smaller than the base-insn-bitsize,
26042 +     word_length may be too big.  */
26043 +  if (cd->min_insn_bitsize < cd->base_insn_bitsize)
26044 +    {
26045 +      if (word_offset == 0
26046 +         && word_length > total_length)
26047 +       word_length = total_length;
26048 +    }
26049 +
26050 +  /* Ensure VALUE will fit.  */
26051 +  if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT))
26052 +    {
26053 +      long minval = - (1L << (length - 1));
26054 +      unsigned long maxval = mask;
26055 +      
26056 +      if ((value > 0 && (unsigned long) value > maxval)
26057 +         || value < minval)
26058 +       {
26059 +         /* xgettext:c-format */
26060 +         sprintf (errbuf,
26061 +                  _("operand out of range (%ld not between %ld and %lu)"),
26062 +                  value, minval, maxval);
26063 +         return errbuf;
26064 +       }
26065 +    }
26066 +  else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED))
26067 +    {
26068 +      unsigned long maxval = mask;
26069 +      unsigned long val = (unsigned long) value;
26070 +
26071 +      /* For hosts with a word size > 32 check to see if value has been sign
26072 +        extended beyond 32 bits.  If so then ignore these higher sign bits
26073 +        as the user is attempting to store a 32-bit signed value into an
26074 +        unsigned 32-bit field which is allowed.  */
26075 +      if (sizeof (unsigned long) > 4 && ((value >> 32) == -1))
26076 +       val &= 0xFFFFFFFF;
26077 +
26078 +      if (val > maxval)
26079 +       {
26080 +         /* xgettext:c-format */
26081 +         sprintf (errbuf,
26082 +                  _("operand out of range (0x%lx not between 0 and 0x%lx)"),
26083 +                  val, maxval);
26084 +         return errbuf;
26085 +       }
26086 +    }
26087 +  else
26088 +    {
26089 +      if (! cgen_signed_overflow_ok_p (cd))
26090 +       {
26091 +         long minval = - (1L << (length - 1));
26092 +         long maxval =   (1L << (length - 1)) - 1;
26093 +         
26094 +         if (value < minval || value > maxval)
26095 +           {
26096 +             sprintf
26097 +               /* xgettext:c-format */
26098 +               (errbuf, _("operand out of range (%ld not between %ld and %ld)"),
26099 +                value, minval, maxval);
26100 +             return errbuf;
26101 +           }
26102 +       }
26103 +    }
26104 +
26105 +#if CGEN_INT_INSN_P
26106 +
26107 +  {
26108 +    int shift;
26109 +
26110 +    if (CGEN_INSN_LSB0_P)
26111 +      shift = (word_offset + start + 1) - length;
26112 +    else
26113 +      shift = total_length - (word_offset + start + length);
26114 +    *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift);
26115 +  }
26116 +
26117 +#else /* ! CGEN_INT_INSN_P */
26118 +
26119 +  {
26120 +    unsigned char *bufp = (unsigned char *) buffer + word_offset / 8;
26121 +
26122 +    insert_1 (cd, value, start, length, word_length, bufp);
26123 +  }
26124 +
26125 +#endif /* ! CGEN_INT_INSN_P */
26126 +
26127 +  return NULL;
26128 +}
26129 +
26130 +/* Default insn builder (insert handler).
26131 +   The instruction is recorded in CGEN_INT_INSN_P byte order (meaning
26132 +   that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is
26133 +   recorded in host byte order, otherwise BUFFER is an array of bytes
26134 +   and the value is recorded in target byte order).
26135 +   The result is an error message or NULL if success.  */
26136 +
26137 +static const char *
26138 +insert_insn_normal (CGEN_CPU_DESC cd,
26139 +                   const CGEN_INSN * insn,
26140 +                   CGEN_FIELDS * fields,
26141 +                   CGEN_INSN_BYTES_PTR buffer,
26142 +                   bfd_vma pc)
26143 +{
26144 +  const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
26145 +  unsigned long value;
26146 +  const CGEN_SYNTAX_CHAR_TYPE * syn;
26147 +
26148 +  CGEN_INIT_INSERT (cd);
26149 +  value = CGEN_INSN_BASE_VALUE (insn);
26150 +
26151 +  /* If we're recording insns as numbers (rather than a string of bytes),
26152 +     target byte order handling is deferred until later.  */
26153 +
26154 +#if CGEN_INT_INSN_P
26155 +
26156 +  put_insn_int_value (cd, buffer, cd->base_insn_bitsize,
26157 +                     CGEN_FIELDS_BITSIZE (fields), value);
26158 +
26159 +#else
26160 +
26161 +  cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize,
26162 +                                       (unsigned) CGEN_FIELDS_BITSIZE (fields)),
26163 +                      value);
26164 +
26165 +#endif /* ! CGEN_INT_INSN_P */
26166 +
26167 +  /* ??? It would be better to scan the format's fields.
26168 +     Still need to be able to insert a value based on the operand though;
26169 +     e.g. storing a branch displacement that got resolved later.
26170 +     Needs more thought first.  */
26171 +
26172 +  for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn)
26173 +    {
26174 +      const char *errmsg;
26175 +
26176 +      if (CGEN_SYNTAX_CHAR_P (* syn))
26177 +       continue;
26178 +
26179 +      errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
26180 +                                      fields, buffer, pc);
26181 +      if (errmsg)
26182 +       return errmsg;
26183 +    }
26184 +
26185 +  return NULL;
26186 +}
26187 +
26188 +#if CGEN_INT_INSN_P
26189 +/* Cover function to store an insn value into an integral insn.  Must go here
26190 +   because it needs <prefix>-desc.h for CGEN_INT_INSN_P.  */
26191 +
26192 +static void
26193 +put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
26194 +                   CGEN_INSN_BYTES_PTR buf,
26195 +                   int length,
26196 +                   int insn_length,
26197 +                   CGEN_INSN_INT value)
26198 +{
26199 +  /* For architectures with insns smaller than the base-insn-bitsize,
26200 +     length may be too big.  */
26201 +  if (length > insn_length)
26202 +    *buf = value;
26203 +  else
26204 +    {
26205 +      int shift = insn_length - length;
26206 +      /* Written this way to avoid undefined behaviour.  */
26207 +      CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1;
26208 +
26209 +      *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift);
26210 +    }
26211 +}
26212 +#endif
26213 +\f
26214 +/* Operand extraction.  */
26215 +
26216 +#if ! CGEN_INT_INSN_P
26217 +
26218 +/* Subroutine of extract_normal.
26219 +   Ensure sufficient bytes are cached in EX_INFO.
26220 +   OFFSET is the offset in bytes from the start of the insn of the value.
26221 +   BYTES is the length of the needed value.
26222 +   Returns 1 for success, 0 for failure.  */
26223 +
26224 +static CGEN_INLINE int
26225 +fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
26226 +           CGEN_EXTRACT_INFO *ex_info,
26227 +           int offset,
26228 +           int bytes,
26229 +           bfd_vma pc)
26230 +{
26231 +  /* It's doubtful that the middle part has already been fetched so
26232 +     we don't optimize that case.  kiss.  */
26233 +  unsigned int mask;
26234 +  disassemble_info *info = (disassemble_info *) ex_info->dis_info;
26235 +
26236 +  /* First do a quick check.  */
26237 +  mask = (1 << bytes) - 1;
26238 +  if (((ex_info->valid >> offset) & mask) == mask)
26239 +    return 1;
26240 +
26241 +  /* Search for the first byte we need to read.  */
26242 +  for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1)
26243 +    if (! (mask & ex_info->valid))
26244 +      break;
26245 +
26246 +  if (bytes)
26247 +    {
26248 +      int status;
26249 +
26250 +      pc += offset;
26251 +      status = (*info->read_memory_func)
26252 +       (pc, ex_info->insn_bytes + offset, bytes, info);
26253 +
26254 +      if (status != 0)
26255 +       {
26256 +         (*info->memory_error_func) (status, pc, info);
26257 +         return 0;
26258 +       }
26259 +
26260 +      ex_info->valid |= ((1 << bytes) - 1) << offset;
26261 +    }
26262 +
26263 +  return 1;
26264 +}
26265 +
26266 +/* Subroutine of extract_normal.  */
26267 +
26268 +static CGEN_INLINE long
26269 +extract_1 (CGEN_CPU_DESC cd,
26270 +          CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
26271 +          int start,
26272 +          int length,
26273 +          int word_length,
26274 +          unsigned char *bufp,
26275 +          bfd_vma pc ATTRIBUTE_UNUSED)
26276 +{
26277 +  unsigned long x;
26278 +  int shift;
26279 +
26280 +  x = cgen_get_insn_value (cd, bufp, word_length);
26281 +
26282 +  if (CGEN_INSN_LSB0_P)
26283 +    shift = (start + 1) - length;
26284 +  else
26285 +    shift = (word_length - (start + length));
26286 +  return x >> shift;
26287 +}
26288 +
26289 +#endif /* ! CGEN_INT_INSN_P */
26290 +
26291 +/* Default extraction routine.
26292 +
26293 +   INSN_VALUE is the first base_insn_bitsize bits of the insn in host order,
26294 +   or sometimes less for cases like the m32r where the base insn size is 32
26295 +   but some insns are 16 bits.
26296 +   ATTRS is a mask of the boolean attributes.  We only need `SIGNED',
26297 +   but for generality we take a bitmask of all of them.
26298 +   WORD_OFFSET is the offset in bits from the start of the insn of the value.
26299 +   WORD_LENGTH is the length of the word in bits in which the value resides.
26300 +   START is the starting bit number in the word, architecture origin.
26301 +   LENGTH is the length of VALUE in bits.
26302 +   TOTAL_LENGTH is the total length of the insn in bits.
26303 +
26304 +   Returns 1 for success, 0 for failure.  */
26305 +
26306 +/* ??? The return code isn't properly used.  wip.  */
26307 +
26308 +/* ??? This doesn't handle bfd_vma's.  Create another function when
26309 +   necessary.  */
26310 +
26311 +static int
26312 +extract_normal (CGEN_CPU_DESC cd,
26313 +#if ! CGEN_INT_INSN_P
26314 +               CGEN_EXTRACT_INFO *ex_info,
26315 +#else
26316 +               CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
26317 +#endif
26318 +               CGEN_INSN_INT insn_value,
26319 +               unsigned int attrs,
26320 +               unsigned int word_offset,
26321 +               unsigned int start,
26322 +               unsigned int length,
26323 +               unsigned int word_length,
26324 +               unsigned int total_length,
26325 +#if ! CGEN_INT_INSN_P
26326 +               bfd_vma pc,
26327 +#else
26328 +               bfd_vma pc ATTRIBUTE_UNUSED,
26329 +#endif
26330 +               long *valuep)
26331 +{
26332 +  long value, mask;
26333 +
26334 +  /* If LENGTH is zero, this operand doesn't contribute to the value
26335 +     so give it a standard value of zero.  */
26336 +  if (length == 0)
26337 +    {
26338 +      *valuep = 0;
26339 +      return 1;
26340 +    }
26341 +
26342 +  if (word_length > 32)
26343 +    abort ();
26344 +
26345 +  /* For architectures with insns smaller than the insn-base-bitsize,
26346 +     word_length may be too big.  */
26347 +  if (cd->min_insn_bitsize < cd->base_insn_bitsize)
26348 +    {
26349 +      if (word_offset + word_length > total_length)
26350 +       word_length = total_length - word_offset;
26351 +    }
26352 +
26353 +  /* Does the value reside in INSN_VALUE, and at the right alignment?  */
26354 +
26355 +  if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length))
26356 +    {
26357 +      if (CGEN_INSN_LSB0_P)
26358 +       value = insn_value >> ((word_offset + start + 1) - length);
26359 +      else
26360 +       value = insn_value >> (total_length - ( word_offset + start + length));
26361 +    }
26362 +
26363 +#if ! CGEN_INT_INSN_P
26364 +
26365 +  else
26366 +    {
26367 +      unsigned char *bufp = ex_info->insn_bytes + word_offset / 8;
26368 +
26369 +      if (word_length > 32)
26370 +       abort ();
26371 +
26372 +      if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0)
26373 +       return 0;
26374 +
26375 +      value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc);
26376 +    }
26377 +
26378 +#endif /* ! CGEN_INT_INSN_P */
26379 +
26380 +  /* Written this way to avoid undefined behaviour.  */
26381 +  mask = (((1L << (length - 1)) - 1) << 1) | 1;
26382 +
26383 +  value &= mask;
26384 +  /* sign extend? */
26385 +  if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)
26386 +      && (value & (1L << (length - 1))))
26387 +    value |= ~mask;
26388 +
26389 +  *valuep = value;
26390 +
26391 +  return 1;
26392 +}
26393 +
26394 +/* Default insn extractor.
26395 +
26396 +   INSN_VALUE is the first base_insn_bitsize bits, translated to host order.
26397 +   The extracted fields are stored in FIELDS.
26398 +   EX_INFO is used to handle reading variable length insns.
26399 +   Return the length of the insn in bits, or 0 if no match,
26400 +   or -1 if an error occurs fetching data (memory_error_func will have
26401 +   been called).  */
26402 +
26403 +static int
26404 +extract_insn_normal (CGEN_CPU_DESC cd,
26405 +                    const CGEN_INSN *insn,
26406 +                    CGEN_EXTRACT_INFO *ex_info,
26407 +                    CGEN_INSN_INT insn_value,
26408 +                    CGEN_FIELDS *fields,
26409 +                    bfd_vma pc)
26410 +{
26411 +  const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
26412 +  const CGEN_SYNTAX_CHAR_TYPE *syn;
26413 +
26414 +  CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
26415 +
26416 +  CGEN_INIT_EXTRACT (cd);
26417 +
26418 +  for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
26419 +    {
26420 +      int length;
26421 +
26422 +      if (CGEN_SYNTAX_CHAR_P (*syn))
26423 +       continue;
26424 +
26425 +      length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
26426 +                                       ex_info, insn_value, fields, pc);
26427 +      if (length <= 0)
26428 +       return length;
26429 +    }
26430 +
26431 +  /* We recognized and successfully extracted this insn.  */
26432 +  return CGEN_INSN_BITSIZE (insn);
26433 +}
26434 +\f
26435 +/* Machine generated code added here.  */
26436 +
26437 +const char * ubicom32_cgen_insert_operand
26438 +  (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
26439 +
26440 +/* Main entry point for operand insertion.
26441 +
26442 +   This function is basically just a big switch statement.  Earlier versions
26443 +   used tables to look up the function to use, but
26444 +   - if the table contains both assembler and disassembler functions then
26445 +     the disassembler contains much of the assembler and vice-versa,
26446 +   - there's a lot of inlining possibilities as things grow,
26447 +   - using a switch statement avoids the function call overhead.
26448 +
26449 +   This function could be moved into `parse_insn_normal', but keeping it
26450 +   separate makes clear the interface between `parse_insn_normal' and each of
26451 +   the handlers.  It's also needed by GAS to insert operands that couldn't be
26452 +   resolved during parsing.  */
26453 +
26454 +const char *
26455 +ubicom32_cgen_insert_operand (CGEN_CPU_DESC cd,
26456 +                            int opindex,
26457 +                            CGEN_FIELDS * fields,
26458 +                            CGEN_INSN_BYTES_PTR buffer,
26459 +                            bfd_vma pc ATTRIBUTE_UNUSED)
26460 +{
26461 +  const char * errmsg = NULL;
26462 +  unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
26463 +
26464 +  switch (opindex)
26465 +    {
26466 +    case UBICOM32_OPERAND_AM :
26467 +      errmsg = insert_normal (cd, fields->f_Am, 0, 0, 7, 3, 32, total_length, buffer);
26468 +      break;
26469 +    case UBICOM32_OPERAND_AN :
26470 +      errmsg = insert_normal (cd, fields->f_An, 0, 0, 23, 3, 32, total_length, buffer);
26471 +      break;
26472 +    case UBICOM32_OPERAND_C :
26473 +      errmsg = insert_normal (cd, fields->f_C, 0, 0, 21, 1, 32, total_length, buffer);
26474 +      break;
26475 +    case UBICOM32_OPERAND_DN :
26476 +      errmsg = insert_normal (cd, fields->f_Dn, 0, 0, 20, 5, 32, total_length, buffer);
26477 +      break;
26478 +    case UBICOM32_OPERAND_P :
26479 +      errmsg = insert_normal (cd, fields->f_P, 0, 0, 22, 1, 32, total_length, buffer);
26480 +      break;
26481 +    case UBICOM32_OPERAND_ACC1HI :
26482 +      break;
26483 +    case UBICOM32_OPERAND_ACC1LO :
26484 +      break;
26485 +    case UBICOM32_OPERAND_BIT5 :
26486 +      errmsg = insert_normal (cd, fields->f_bit5, 0, 0, 15, 5, 32, total_length, buffer);
26487 +      break;
26488 +    case UBICOM32_OPERAND_BIT5_ADDSUB :
26489 +      errmsg = insert_normal (cd, fields->f_bit5, 0, 0, 15, 5, 32, total_length, buffer);
26490 +      break;
26491 +    case UBICOM32_OPERAND_CC :
26492 +      errmsg = insert_normal (cd, fields->f_cond, 0, 0, 26, 4, 32, total_length, buffer);
26493 +      break;
26494 +    case UBICOM32_OPERAND_D_AN :
26495 +      errmsg = insert_normal (cd, fields->f_d_An, 0, 0, 23, 3, 32, total_length, buffer);
26496 +      break;
26497 +    case UBICOM32_OPERAND_D_DIRECT_ADDR :
26498 +      {
26499 +        long value = fields->f_d_direct;
26500 +        value = ((unsigned int) (value) >> (2));
26501 +        errmsg = insert_normal (cd, value, 0, 0, 23, 8, 32, total_length, buffer);
26502 +      }
26503 +      break;
26504 +    case UBICOM32_OPERAND_D_I4_1 :
26505 +      errmsg = insert_normal (cd, fields->f_d_i4_1, 0|(1<<CGEN_IFLD_SIGNED), 0, 19, 4, 32, total_length, buffer);
26506 +      break;
26507 +    case UBICOM32_OPERAND_D_I4_2 :
26508 +      {
26509 +        long value = fields->f_d_i4_2;
26510 +        value = ((unsigned int) (value) >> (1));
26511 +        errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED), 0, 19, 4, 32, total_length, buffer);
26512 +      }
26513 +      break;
26514 +    case UBICOM32_OPERAND_D_I4_4 :
26515 +      {
26516 +        long value = fields->f_d_i4_4;
26517 +        value = ((unsigned int) (value) >> (2));
26518 +        errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED), 0, 19, 4, 32, total_length, buffer);
26519 +      }
26520 +      break;
26521 +    case UBICOM32_OPERAND_D_IMM7_1 :
26522 +      {
26523 +{
26524 +  FLD (f_d_imm7_t) = ((((unsigned int) (FLD (f_d_imm7_1)) >> (5))) & (3));
26525 +  FLD (f_d_imm7_b) = ((((unsigned int) (FLD (f_d_imm7_1)) >> (0))) & (31));
26526 +}
26527 +        errmsg = insert_normal (cd, fields->f_d_imm7_t, 0, 0, 25, 2, 32, total_length, buffer);
26528 +        if (errmsg)
26529 +          break;
26530 +        errmsg = insert_normal (cd, fields->f_d_imm7_b, 0, 0, 20, 5, 32, total_length, buffer);
26531 +        if (errmsg)
26532 +          break;
26533 +      }
26534 +      break;
26535 +    case UBICOM32_OPERAND_D_IMM7_2 :
26536 +      {
26537 +{
26538 +  FLD (f_d_imm7_t) = ((((unsigned int) (FLD (f_d_imm7_2)) >> (6))) & (3));
26539 +  FLD (f_d_imm7_b) = ((((unsigned int) (FLD (f_d_imm7_2)) >> (1))) & (31));
26540 +}
26541 +        errmsg = insert_normal (cd, fields->f_d_imm7_t, 0, 0, 25, 2, 32, total_length, buffer);
26542 +        if (errmsg)
26543 +          break;
26544 +        errmsg = insert_normal (cd, fields->f_d_imm7_b, 0, 0, 20, 5, 32, total_length, buffer);
26545 +        if (errmsg)
26546 +          break;
26547 +      }
26548 +      break;
26549 +    case UBICOM32_OPERAND_D_IMM7_4 :
26550 +      {
26551 +{
26552 +  FLD (f_d_imm7_t) = ((((unsigned int) (FLD (f_d_imm7_4)) >> (7))) & (3));
26553 +  FLD (f_d_imm7_b) = ((((unsigned int) (FLD (f_d_imm7_4)) >> (2))) & (31));
26554 +}
26555 +        errmsg = insert_normal (cd, fields->f_d_imm7_t, 0, 0, 25, 2, 32, total_length, buffer);
26556 +        if (errmsg)
26557 +          break;
26558 +        errmsg = insert_normal (cd, fields->f_d_imm7_b, 0, 0, 20, 5, 32, total_length, buffer);
26559 +        if (errmsg)
26560 +          break;
26561 +      }
26562 +      break;
26563 +    case UBICOM32_OPERAND_D_IMM8 :
26564 +      errmsg = insert_normal (cd, fields->f_d_imm8, 0|(1<<CGEN_IFLD_SIGNED), 0, 23, 8, 32, total_length, buffer);
26565 +      break;
26566 +    case UBICOM32_OPERAND_D_R :
26567 +      errmsg = insert_normal (cd, fields->f_d_r, 0, 0, 20, 5, 32, total_length, buffer);
26568 +      break;
26569 +    case UBICOM32_OPERAND_DSP_S2_ACC_REG_ADDSUB :
26570 +      errmsg = insert_normal (cd, fields->f_dsp_S2, 0, 0, 14, 4, 32, total_length, buffer);
26571 +      break;
26572 +    case UBICOM32_OPERAND_DSP_S2_ACC_REG_MUL :
26573 +      errmsg = insert_normal (cd, fields->f_dsp_S2, 0, 0, 14, 4, 32, total_length, buffer);
26574 +      break;
26575 +    case UBICOM32_OPERAND_DSP_S2_DATA_REG :
26576 +      errmsg = insert_normal (cd, fields->f_dsp_S2, 0, 0, 14, 4, 32, total_length, buffer);
26577 +      break;
26578 +    case UBICOM32_OPERAND_DSP_S2_DATA_REG_ADDSUB :
26579 +      errmsg = insert_normal (cd, fields->f_dsp_S2, 0, 0, 14, 4, 32, total_length, buffer);
26580 +      break;
26581 +    case UBICOM32_OPERAND_DSP_S2_SEL :
26582 +      errmsg = insert_normal (cd, fields->f_dsp_S2_sel, 0, 0, 18, 1, 32, total_length, buffer);
26583 +      break;
26584 +    case UBICOM32_OPERAND_DSP_C :
26585 +      errmsg = insert_normal (cd, fields->f_dsp_C, 0, 0, 20, 1, 32, total_length, buffer);
26586 +      break;
26587 +    case UBICOM32_OPERAND_DSP_DESTA :
26588 +      errmsg = insert_normal (cd, fields->f_dsp_destA, 0, 0, 16, 1, 32, total_length, buffer);
26589 +      break;
26590 +    case UBICOM32_OPERAND_DSP_T :
26591 +      errmsg = insert_normal (cd, fields->f_dsp_T, 0, 0, 19, 1, 32, total_length, buffer);
26592 +      break;
26593 +    case UBICOM32_OPERAND_DSP_T_ADDSUB :
26594 +      errmsg = insert_normal (cd, fields->f_dsp_T, 0, 0, 19, 1, 32, total_length, buffer);
26595 +      break;
26596 +    case UBICOM32_OPERAND_IMM16_1 :
26597 +      errmsg = insert_normal (cd, fields->f_imm16_1, 0|(1<<CGEN_IFLD_SIGNED), 0, 26, 16, 32, total_length, buffer);
26598 +      break;
26599 +    case UBICOM32_OPERAND_IMM16_2 :
26600 +      errmsg = insert_normal (cd, fields->f_imm16_2, 0|(1<<CGEN_IFLD_SIGNED), 0, 15, 16, 32, total_length, buffer);
26601 +      break;
26602 +    case UBICOM32_OPERAND_IMM24 :
26603 +      {
26604 +{
26605 +  FLD (f_imm23_21) = ((((unsigned int) (FLD (f_imm24)) >> (21))) & (7));
26606 +  FLD (f_o20_0) = ((FLD (f_imm24)) & (2097151));
26607 +}
26608 +        errmsg = insert_normal (cd, fields->f_imm23_21, 0, 0, 26, 3, 32, total_length, buffer);
26609 +        if (errmsg)
26610 +          break;
26611 +        errmsg = insert_normal (cd, fields->f_o20_0, 0, 0, 20, 21, 32, total_length, buffer);
26612 +        if (errmsg)
26613 +          break;
26614 +      }
26615 +      break;
26616 +    case UBICOM32_OPERAND_INTERRUPT :
26617 +      errmsg = insert_normal (cd, fields->f_int, 0, 0, 5, 6, 32, total_length, buffer);
26618 +      break;
26619 +    case UBICOM32_OPERAND_IREAD :
26620 +      break;
26621 +    case UBICOM32_OPERAND_IRQ_0 :
26622 +      break;
26623 +    case UBICOM32_OPERAND_IRQ_1 :
26624 +      break;
26625 +    case UBICOM32_OPERAND_MACHI :
26626 +      break;
26627 +    case UBICOM32_OPERAND_MACLO :
26628 +      break;
26629 +    case UBICOM32_OPERAND_OFFSET16 :
26630 +      {
26631 +        fields->f_o16 = ((int) (fields->f_o16) >> (2));
26632 +{
26633 +  FLD (f_o15_13) = ((((unsigned int) (FLD (f_o16)) >> (13))) & (7));
26634 +  FLD (f_o12_8) = ((((unsigned int) (FLD (f_o16)) >> (8))) & (31));
26635 +  FLD (f_o7_5) = ((((unsigned int) (FLD (f_o16)) >> (5))) & (7));
26636 +  FLD (f_o4_0) = ((FLD (f_o16)) & (31));
26637 +}
26638 +        errmsg = insert_normal (cd, fields->f_o15_13, 0|(1<<CGEN_IFLD_SIGNED), 0, 26, 3, 32, total_length, buffer);
26639 +        if (errmsg)
26640 +          break;
26641 +        errmsg = insert_normal (cd, fields->f_o12_8, 0, 0, 20, 5, 32, total_length, buffer);
26642 +        if (errmsg)
26643 +          break;
26644 +        errmsg = insert_normal (cd, fields->f_o7_5, 0, 0, 10, 3, 32, total_length, buffer);
26645 +        if (errmsg)
26646 +          break;
26647 +        errmsg = insert_normal (cd, fields->f_o4_0, 0, 0, 4, 5, 32, total_length, buffer);
26648 +        if (errmsg)
26649 +          break;
26650 +      }
26651 +      break;
26652 +    case UBICOM32_OPERAND_OFFSET21 :
26653 +      {
26654 +        long value = fields->f_o21;
26655 +        value = ((unsigned int) (((value) - (pc))) >> (2));
26656 +        errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 20, 21, 32, total_length, buffer);
26657 +      }
26658 +      break;
26659 +    case UBICOM32_OPERAND_OFFSET24 :
26660 +      {
26661 +        fields->f_o24 = ((int) (((fields->f_o24) - (pc))) >> (2));
26662 +{
26663 +  FLD (f_o23_21) = ((((unsigned int) (FLD (f_o24)) >> (21))) & (7));
26664 +  FLD (f_o20_0) = ((FLD (f_o24)) & (2097151));
26665 +}
26666 +        errmsg = insert_normal (cd, fields->f_o23_21, 0|(1<<CGEN_IFLD_SIGNED), 0, 26, 3, 32, total_length, buffer);
26667 +        if (errmsg)
26668 +          break;
26669 +        errmsg = insert_normal (cd, fields->f_o20_0, 0, 0, 20, 21, 32, total_length, buffer);
26670 +        if (errmsg)
26671 +          break;
26672 +      }
26673 +      break;
26674 +    case UBICOM32_OPERAND_OPC1 :
26675 +      errmsg = insert_normal (cd, fields->f_op1, 0, 0, 31, 5, 32, total_length, buffer);
26676 +      break;
26677 +    case UBICOM32_OPERAND_OPC2 :
26678 +      errmsg = insert_normal (cd, fields->f_op2, 0, 0, 15, 5, 32, total_length, buffer);
26679 +      break;
26680 +    case UBICOM32_OPERAND_PDEC_S1_IMM7_4 :
26681 +      {
26682 +{
26683 +  FLD (f_s1_imm7_t) = ((((unsigned int) (FLD (f_s1_imm7_4)) >> (7))) & (3));
26684 +  FLD (f_s1_imm7_b) = ((((unsigned int) (FLD (f_s1_imm7_4)) >> (2))) & (31));
26685 +}
26686 +        errmsg = insert_normal (cd, fields->f_s1_imm7_t, 0, 0, 9, 2, 32, total_length, buffer);
26687 +        if (errmsg)
26688 +          break;
26689 +        errmsg = insert_normal (cd, fields->f_s1_imm7_b, 0, 0, 4, 5, 32, total_length, buffer);
26690 +        if (errmsg)
26691 +          break;
26692 +      }
26693 +      break;
26694 +    case UBICOM32_OPERAND_S1_AN :
26695 +      errmsg = insert_normal (cd, fields->f_s1_An, 0, 0, 7, 3, 32, total_length, buffer);
26696 +      break;
26697 +    case UBICOM32_OPERAND_S1_DIRECT_ADDR :
26698 +      {
26699 +        long value = fields->f_s1_direct;
26700 +        value = ((unsigned int) (value) >> (2));
26701 +        errmsg = insert_normal (cd, value, 0, 0, 7, 8, 32, total_length, buffer);
26702 +      }
26703 +      break;
26704 +    case UBICOM32_OPERAND_S1_I4_1 :
26705 +      errmsg = insert_normal (cd, fields->f_s1_i4_1, 0|(1<<CGEN_IFLD_SIGNED), 0, 3, 4, 32, total_length, buffer);
26706 +      break;
26707 +    case UBICOM32_OPERAND_S1_I4_2 :
26708 +      {
26709 +        long value = fields->f_s1_i4_2;
26710 +        value = ((unsigned int) (value) >> (1));
26711 +        errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED), 0, 3, 4, 32, total_length, buffer);
26712 +      }
26713 +      break;
26714 +    case UBICOM32_OPERAND_S1_I4_4 :
26715 +      {
26716 +        long value = fields->f_s1_i4_4;
26717 +        value = ((unsigned int) (value) >> (2));
26718 +        errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED), 0, 3, 4, 32, total_length, buffer);
26719 +      }
26720 +      break;
26721 +    case UBICOM32_OPERAND_S1_IMM7_1 :
26722 +      {
26723 +{
26724 +  FLD (f_s1_imm7_t) = ((((unsigned int) (FLD (f_s1_imm7_1)) >> (5))) & (3));
26725 +  FLD (f_s1_imm7_b) = ((((unsigned int) (FLD (f_s1_imm7_1)) >> (0))) & (31));
26726 +}
26727 +        errmsg = insert_normal (cd, fields->f_s1_imm7_t, 0, 0, 9, 2, 32, total_length, buffer);
26728 +        if (errmsg)
26729 +          break;
26730 +        errmsg = insert_normal (cd, fields->f_s1_imm7_b, 0, 0, 4, 5, 32, total_length, buffer);
26731 +        if (errmsg)
26732 +          break;
26733 +      }
26734 +      break;
26735 +    case UBICOM32_OPERAND_S1_IMM7_2 :
26736 +      {
26737 +{
26738 +  FLD (f_s1_imm7_t) = ((((unsigned int) (FLD (f_s1_imm7_2)) >> (6))) & (3));
26739 +  FLD (f_s1_imm7_b) = ((((unsigned int) (FLD (f_s1_imm7_2)) >> (1))) & (31));
26740 +}
26741 +        errmsg = insert_normal (cd, fields->f_s1_imm7_t, 0, 0, 9, 2, 32, total_length, buffer);
26742 +        if (errmsg)
26743 +          break;
26744 +        errmsg = insert_normal (cd, fields->f_s1_imm7_b, 0, 0, 4, 5, 32, total_length, buffer);
26745 +        if (errmsg)
26746 +          break;
26747 +      }
26748 +      break;
26749 +    case UBICOM32_OPERAND_S1_IMM7_4 :
26750 +      {
26751 +{
26752 +  FLD (f_s1_imm7_t) = ((((unsigned int) (FLD (f_s1_imm7_4)) >> (7))) & (3));
26753 +  FLD (f_s1_imm7_b) = ((((unsigned int) (FLD (f_s1_imm7_4)) >> (2))) & (31));
26754 +}
26755 +        errmsg = insert_normal (cd, fields->f_s1_imm7_t, 0, 0, 9, 2, 32, total_length, buffer);
26756 +        if (errmsg)
26757 +          break;
26758 +        errmsg = insert_normal (cd, fields->f_s1_imm7_b, 0, 0, 4, 5, 32, total_length, buffer);
26759 +        if (errmsg)
26760 +          break;
26761 +      }
26762 +      break;
26763 +    case UBICOM32_OPERAND_S1_IMM8 :
26764 +      errmsg = insert_normal (cd, fields->f_s1_imm8, 0|(1<<CGEN_IFLD_SIGNED), 0, 7, 8, 32, total_length, buffer);
26765 +      break;
26766 +    case UBICOM32_OPERAND_S1_R :
26767 +      errmsg = insert_normal (cd, fields->f_s1_r, 0, 0, 4, 5, 32, total_length, buffer);
26768 +      break;
26769 +    case UBICOM32_OPERAND_S2 :
26770 +      errmsg = insert_normal (cd, fields->f_s2, 0, 0, 14, 4, 32, total_length, buffer);
26771 +      break;
26772 +    case UBICOM32_OPERAND_SRC3 :
26773 +      break;
26774 +    case UBICOM32_OPERAND_X_BIT26 :
26775 +      errmsg = insert_normal (cd, fields->f_bit26, 0, 0, 26, 1, 32, total_length, buffer);
26776 +      break;
26777 +    case UBICOM32_OPERAND_X_D :
26778 +      errmsg = insert_normal (cd, fields->f_d, 0, 0, 26, 11, 32, total_length, buffer);
26779 +      break;
26780 +    case UBICOM32_OPERAND_X_DN :
26781 +      errmsg = insert_normal (cd, fields->f_Dn, 0, 0, 20, 5, 32, total_length, buffer);
26782 +      break;
26783 +    case UBICOM32_OPERAND_X_OP2 :
26784 +      errmsg = insert_normal (cd, fields->f_op2, 0, 0, 15, 5, 32, total_length, buffer);
26785 +      break;
26786 +    case UBICOM32_OPERAND_X_S1 :
26787 +      errmsg = insert_normal (cd, fields->f_s1, 0, 0, 10, 11, 32, total_length, buffer);
26788 +      break;
26789 +
26790 +    default :
26791 +      /* xgettext:c-format */
26792 +      fprintf (stderr, _("Unrecognized field %d while building insn.\n"),
26793 +              opindex);
26794 +      abort ();
26795 +  }
26796 +
26797 +  return errmsg;
26798 +}
26799 +
26800 +int ubicom32_cgen_extract_operand
26801 +  (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
26802 +
26803 +/* Main entry point for operand extraction.
26804 +   The result is <= 0 for error, >0 for success.
26805 +   ??? Actual values aren't well defined right now.
26806 +
26807 +   This function is basically just a big switch statement.  Earlier versions
26808 +   used tables to look up the function to use, but
26809 +   - if the table contains both assembler and disassembler functions then
26810 +     the disassembler contains much of the assembler and vice-versa,
26811 +   - there's a lot of inlining possibilities as things grow,
26812 +   - using a switch statement avoids the function call overhead.
26813 +
26814 +   This function could be moved into `print_insn_normal', but keeping it
26815 +   separate makes clear the interface between `print_insn_normal' and each of
26816 +   the handlers.  */
26817 +
26818 +int
26819 +ubicom32_cgen_extract_operand (CGEN_CPU_DESC cd,
26820 +                            int opindex,
26821 +                            CGEN_EXTRACT_INFO *ex_info,
26822 +                            CGEN_INSN_INT insn_value,
26823 +                            CGEN_FIELDS * fields,
26824 +                            bfd_vma pc)
26825 +{
26826 +  /* Assume success (for those operands that are nops).  */
26827 +  int length = 1;
26828 +  unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
26829 +
26830 +  switch (opindex)
26831 +    {
26832 +    case UBICOM32_OPERAND_AM :
26833 +      length = extract_normal (cd, ex_info, insn_value, 0, 0, 7, 3, 32, total_length, pc, & fields->f_Am);
26834 +      break;
26835 +    case UBICOM32_OPERAND_AN :
26836 +      length = extract_normal (cd, ex_info, insn_value, 0, 0, 23, 3, 32, total_length, pc, & fields->f_An);
26837 +      break;
26838 +    case UBICOM32_OPERAND_C :
26839 +      length = extract_normal (cd, ex_info, insn_value, 0, 0, 21, 1, 32, total_length, pc, & fields->f_C);
26840 +      break;
26841 +    case UBICOM32_OPERAND_DN :
26842 +      length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_Dn);
26843 +      break;
26844 +    case UBICOM32_OPERAND_P :
26845 +      length = extract_normal (cd, ex_info, insn_value, 0, 0, 22, 1, 32, total_length, pc, & fields->f_P);
26846 +      break;
26847 +    case UBICOM32_OPERAND_ACC1HI :
26848 +      break;
26849 +    case UBICOM32_OPERAND_ACC1LO :
26850 +      break;
26851 +    case UBICOM32_OPERAND_BIT5 :
26852 +      length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_bit5);
26853 +      break;
26854 +    case UBICOM32_OPERAND_BIT5_ADDSUB :
26855 +      length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_bit5);
26856 +      break;
26857 +    case UBICOM32_OPERAND_CC :
26858 +      length = extract_normal (cd, ex_info, insn_value, 0, 0, 26, 4, 32, total_length, pc, & fields->f_cond);
26859 +      break;
26860 +    case UBICOM32_OPERAND_D_AN :
26861 +      length = extract_normal (cd, ex_info, insn_value, 0, 0, 23, 3, 32, total_length, pc, & fields->f_d_An);
26862 +      break;
26863 +    case UBICOM32_OPERAND_D_DIRECT_ADDR :
26864 +      {
26865 +        long value;
26866 +        length = extract_normal (cd, ex_info, insn_value, 0, 0, 23, 8, 32, total_length, pc, & value);
26867 +        value = ((value) << (2));
26868 +        fields->f_d_direct = value;
26869 +      }
26870 +      break;
26871 +    case UBICOM32_OPERAND_D_I4_1 :
26872 +      length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 19, 4, 32, total_length, pc, & fields->f_d_i4_1);
26873 +      break;
26874 +    case UBICOM32_OPERAND_D_I4_2 :
26875 +      {
26876 +        long value;
26877 +        length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 19, 4, 32, total_length, pc, & value);
26878 +        value = ((value) << (1));
26879 +        fields->f_d_i4_2 = value;
26880 +      }
26881 +      break;
26882 +    case UBICOM32_OPERAND_D_I4_4 :
26883 +      {
26884 +        long value;
26885 +        length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 19, 4, 32, total_length, pc, & value);
26886 +        value = ((value) << (2));
26887 +        fields->f_d_i4_4 = value;
26888 +      }
26889 +      break;
26890 +    case UBICOM32_OPERAND_D_IMM7_1 :
26891 +      {
26892 +        length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 2, 32, total_length, pc, & fields->f_d_imm7_t);
26893 +        if (length <= 0) break;
26894 +        length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_d_imm7_b);
26895 +        if (length <= 0) break;
26896 +{
26897 +  FLD (f_d_imm7_1) = ((((((FLD (f_d_imm7_t)) << (5))) | (FLD (f_d_imm7_b)))) << (0));
26898 +}
26899 +      }
26900 +      break;
26901 +    case UBICOM32_OPERAND_D_IMM7_2 :
26902 +      {
26903 +        length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 2, 32, total_length, pc, & fields->f_d_imm7_t);
26904 +        if (length <= 0) break;
26905 +        length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_d_imm7_b);
26906 +        if (length <= 0) break;
26907 +{
26908 +  FLD (f_d_imm7_2) = ((((((FLD (f_d_imm7_t)) << (5))) | (FLD (f_d_imm7_b)))) << (1));
26909 +}
26910 +      }
26911 +      break;
26912 +    case UBICOM32_OPERAND_D_IMM7_4 :
26913 +      {
26914 +        length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 2, 32, total_length, pc, & fields->f_d_imm7_t);
26915 +        if (length <= 0) break;
26916 +        length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_d_imm7_b);
26917 +        if (length <= 0) break;
26918 +{
26919 +  FLD (f_d_imm7_4) = ((((((FLD (f_d_imm7_t)) << (5))) | (FLD (f_d_imm7_b)))) << (2));
26920 +}
26921 +      }
26922 +      break;
26923 +    case UBICOM32_OPERAND_D_IMM8 :
26924 +      length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 23, 8, 32, total_length, pc, & fields->f_d_imm8);
26925 +      break;
26926 +    case UBICOM32_OPERAND_D_R :
26927 +      length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_d_r);
26928 +      break;
26929 +    case UBICOM32_OPERAND_DSP_S2_ACC_REG_ADDSUB :
26930 +      length = extract_normal (cd, ex_info, insn_value, 0, 0, 14, 4, 32, total_length, pc, & fields->f_dsp_S2);
26931 +      break;
26932 +    case UBICOM32_OPERAND_DSP_S2_ACC_REG_MUL :
26933 +      length = extract_normal (cd, ex_info, insn_value, 0, 0, 14, 4, 32, total_length, pc, & fields->f_dsp_S2);
26934 +      break;
26935 +    case UBICOM32_OPERAND_DSP_S2_DATA_REG :
26936 +      length = extract_normal (cd, ex_info, insn_value, 0, 0, 14, 4, 32, total_length, pc, & fields->f_dsp_S2);
26937 +      break;
26938 +    case UBICOM32_OPERAND_DSP_S2_DATA_REG_ADDSUB :
26939 +      length = extract_normal (cd, ex_info, insn_value, 0, 0, 14, 4, 32, total_length, pc, & fields->f_dsp_S2);
26940 +      break;
26941 +    case UBICOM32_OPERAND_DSP_S2_SEL :
26942 +      length = extract_normal (cd, ex_info, insn_value, 0, 0, 18, 1, 32, total_length, pc, & fields->f_dsp_S2_sel);
26943 +      break;
26944 +    case UBICOM32_OPERAND_DSP_C :
26945 +      length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 1, 32, total_length, pc, & fields->f_dsp_C);
26946 +      break;
26947 +    case UBICOM32_OPERAND_DSP_DESTA :
26948 +      length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 1, 32, total_length, pc, & fields->f_dsp_destA);
26949 +      break;
26950 +    case UBICOM32_OPERAND_DSP_T :
26951 +      length = extract_normal (cd, ex_info, insn_value, 0, 0, 19, 1, 32, total_length, pc, & fields->f_dsp_T);
26952 +      break;
26953 +    case UBICOM32_OPERAND_DSP_T_ADDSUB :
26954 +      length = extract_normal (cd, ex_info, insn_value, 0, 0, 19, 1, 32, total_length, pc, & fields->f_dsp_T);
26955 +      break;
26956 +    case UBICOM32_OPERAND_IMM16_1 :
26957 +      length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 26, 16, 32, total_length, pc, & fields->f_imm16_1);
26958 +      break;
26959 +    case UBICOM32_OPERAND_IMM16_2 :
26960 +      length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 15, 16, 32, total_length, pc, & fields->f_imm16_2);
26961 +      break;
26962 +    case UBICOM32_OPERAND_IMM24 :
26963 +      {
26964 +        length = extract_normal (cd, ex_info, insn_value, 0, 0, 26, 3, 32, total_length, pc, & fields->f_imm23_21);
26965 +        if (length <= 0) break;
26966 +        length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 21, 32, total_length, pc, & fields->f_o20_0);
26967 +        if (length <= 0) break;
26968 +{
26969 +  FLD (f_imm24) = ((FLD (f_o20_0)) | (((FLD (f_imm23_21)) << (21))));
26970 +}
26971 +      }
26972 +      break;
26973 +    case UBICOM32_OPERAND_INTERRUPT :
26974 +      length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 6, 32, total_length, pc, & fields->f_int);
26975 +      break;
26976 +    case UBICOM32_OPERAND_IREAD :
26977 +      break;
26978 +    case UBICOM32_OPERAND_IRQ_0 :
26979 +      break;
26980 +    case UBICOM32_OPERAND_IRQ_1 :
26981 +      break;
26982 +    case UBICOM32_OPERAND_MACHI :
26983 +      break;
26984 +    case UBICOM32_OPERAND_MACLO :
26985 +      break;
26986 +    case UBICOM32_OPERAND_OFFSET16 :
26987 +      {
26988 +        length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 26, 3, 32, total_length, pc, & fields->f_o15_13);
26989 +        if (length <= 0) break;
26990 +        length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_o12_8);
26991 +        if (length <= 0) break;
26992 +        length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 3, 32, total_length, pc, & fields->f_o7_5);
26993 +        if (length <= 0) break;
26994 +        length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 5, 32, total_length, pc, & fields->f_o4_0);
26995 +        if (length <= 0) break;
26996 +{
26997 +  FLD (f_o16) = ((FLD (f_o4_0)) | (((((FLD (f_o15_13)) << (13))) | (((((FLD (f_o12_8)) << (8))) | (((FLD (f_o7_5)) << (5))))))));
26998 +}
26999 +        fields->f_o16 = ((fields->f_o16) << (2));
27000 +      }
27001 +      break;
27002 +    case UBICOM32_OPERAND_OFFSET21 :
27003 +      {
27004 +        long value;
27005 +        length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 20, 21, 32, total_length, pc, & value);
27006 +        value = ((((((value) << (2))) + (pc))) & (0xfffffffc));
27007 +        fields->f_o21 = value;
27008 +      }
27009 +      break;
27010 +    case UBICOM32_OPERAND_OFFSET24 :
27011 +      {
27012 +        length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 26, 3, 32, total_length, pc, & fields->f_o23_21);
27013 +        if (length <= 0) break;
27014 +        length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 21, 32, total_length, pc, & fields->f_o20_0);
27015 +        if (length <= 0) break;
27016 +{
27017 +  FLD (f_o24) = ((FLD (f_o20_0)) | (((FLD (f_o23_21)) << (21))));
27018 +}
27019 +        fields->f_o24 = ((((fields->f_o24) << (2))) + (pc));
27020 +      }
27021 +      break;
27022 +    case UBICOM32_OPERAND_OPC1 :
27023 +      length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 5, 32, total_length, pc, & fields->f_op1);
27024 +      break;
27025 +    case UBICOM32_OPERAND_OPC2 :
27026 +      length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_op2);
27027 +      break;
27028 +    case UBICOM32_OPERAND_PDEC_S1_IMM7_4 :
27029 +      {
27030 +        length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 2, 32, total_length, pc, & fields->f_s1_imm7_t);
27031 +        if (length <= 0) break;
27032 +        length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 5, 32, total_length, pc, & fields->f_s1_imm7_b);
27033 +        if (length <= 0) break;
27034 +{
27035 +  FLD (f_s1_imm7_4) = ((((((FLD (f_s1_imm7_t)) << (5))) | (FLD (f_s1_imm7_b)))) << (2));
27036 +}
27037 +      }
27038 +      break;
27039 +    case UBICOM32_OPERAND_S1_AN :
27040 +      length = extract_normal (cd, ex_info, insn_value, 0, 0, 7, 3, 32, total_length, pc, & fields->f_s1_An);
27041 +      break;
27042 +    case UBICOM32_OPERAND_S1_DIRECT_ADDR :
27043 +      {
27044 +        long value;
27045 +        length = extract_normal (cd, ex_info, insn_value, 0, 0, 7, 8, 32, total_length, pc, & value);
27046 +        value = ((value) << (2));
27047 +        fields->f_s1_direct = value;
27048 +      }
27049 +      break;
27050 +    case UBICOM32_OPERAND_S1_I4_1 :
27051 +      length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 3, 4, 32, total_length, pc, & fields->f_s1_i4_1);
27052 +      break;
27053 +    case UBICOM32_OPERAND_S1_I4_2 :
27054 +      {
27055 +        long value;
27056 +        length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 3, 4, 32, total_length, pc, & value);
27057 +        value = ((value) << (1));
27058 +        fields->f_s1_i4_2 = value;
27059 +      }
27060 +      break;
27061 +    case UBICOM32_OPERAND_S1_I4_4 :
27062 +      {
27063 +        long value;
27064 +        length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 3, 4, 32, total_length, pc, & value);
27065 +        value = ((value) << (2));
27066 +        fields->f_s1_i4_4 = value;
27067 +      }
27068 +      break;
27069 +    case UBICOM32_OPERAND_S1_IMM7_1 :
27070 +      {
27071 +        length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 2, 32, total_length, pc, & fields->f_s1_imm7_t);
27072 +        if (length <= 0) break;
27073 +        length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 5, 32, total_length, pc, & fields->f_s1_imm7_b);
27074 +        if (length <= 0) break;
27075 +{
27076 +  FLD (f_s1_imm7_1) = ((((((FLD (f_s1_imm7_t)) << (5))) | (FLD (f_s1_imm7_b)))) << (0));
27077 +}
27078 +      }
27079 +      break;
27080 +    case UBICOM32_OPERAND_S1_IMM7_2 :
27081 +      {
27082 +        length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 2, 32, total_length, pc, & fields->f_s1_imm7_t);
27083 +        if (length <= 0) break;
27084 +        length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 5, 32, total_length, pc, & fields->f_s1_imm7_b);
27085 +        if (length <= 0) break;
27086 +{
27087 +  FLD (f_s1_imm7_2) = ((((((FLD (f_s1_imm7_t)) << (5))) | (FLD (f_s1_imm7_b)))) << (1));
27088 +}
27089 +      }
27090 +      break;
27091 +    case UBICOM32_OPERAND_S1_IMM7_4 :
27092 +      {
27093 +        length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 2, 32, total_length, pc, & fields->f_s1_imm7_t);
27094 +        if (length <= 0) break;
27095 +        length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 5, 32, total_length, pc, & fields->f_s1_imm7_b);
27096 +        if (length <= 0) break;
27097 +{
27098 +  FLD (f_s1_imm7_4) = ((((((FLD (f_s1_imm7_t)) << (5))) | (FLD (f_s1_imm7_b)))) << (2));
27099 +}
27100 +      }
27101 +      break;
27102 +    case UBICOM32_OPERAND_S1_IMM8 :
27103 +      length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 7, 8, 32, total_length, pc, & fields->f_s1_imm8);
27104 +      break;
27105 +    case UBICOM32_OPERAND_S1_R :
27106 +      length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 5, 32, total_length, pc, & fields->f_s1_r);
27107 +      break;
27108 +    case UBICOM32_OPERAND_S2 :
27109 +      length = extract_normal (cd, ex_info, insn_value, 0, 0, 14, 4, 32, total_length, pc, & fields->f_s2);
27110 +      break;
27111 +    case UBICOM32_OPERAND_SRC3 :
27112 +      break;
27113 +    case UBICOM32_OPERAND_X_BIT26 :
27114 +      length = extract_normal (cd, ex_info, insn_value, 0, 0, 26, 1, 32, total_length, pc, & fields->f_bit26);
27115 +      break;
27116 +    case UBICOM32_OPERAND_X_D :
27117 +      length = extract_normal (cd, ex_info, insn_value, 0, 0, 26, 11, 32, total_length, pc, & fields->f_d);
27118 +      break;
27119 +    case UBICOM32_OPERAND_X_DN :
27120 +      length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_Dn);
27121 +      break;
27122 +    case UBICOM32_OPERAND_X_OP2 :
27123 +      length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_op2);
27124 +      break;
27125 +    case UBICOM32_OPERAND_X_S1 :
27126 +      length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 11, 32, total_length, pc, & fields->f_s1);
27127 +      break;
27128 +
27129 +    default :
27130 +      /* xgettext:c-format */
27131 +      fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"),
27132 +              opindex);
27133 +      abort ();
27134 +    }
27135 +
27136 +  return length;
27137 +}
27138 +
27139 +cgen_insert_fn * const ubicom32_cgen_insert_handlers[] = 
27140 +{
27141 +  insert_insn_normal,
27142 +};
27143 +
27144 +cgen_extract_fn * const ubicom32_cgen_extract_handlers[] = 
27145 +{
27146 +  extract_insn_normal,
27147 +};
27148 +
27149 +int ubicom32_cgen_get_int_operand     (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
27150 +bfd_vma ubicom32_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
27151 +
27152 +/* Getting values from cgen_fields is handled by a collection of functions.
27153 +   They are distinguished by the type of the VALUE argument they return.
27154 +   TODO: floating point, inlining support, remove cases where result type
27155 +   not appropriate.  */
27156 +
27157 +int
27158 +ubicom32_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
27159 +                            int opindex,
27160 +                            const CGEN_FIELDS * fields)
27161 +{
27162 +  int value;
27163 +
27164 +  switch (opindex)
27165 +    {
27166 +    case UBICOM32_OPERAND_AM :
27167 +      value = fields->f_Am;
27168 +      break;
27169 +    case UBICOM32_OPERAND_AN :
27170 +      value = fields->f_An;
27171 +      break;
27172 +    case UBICOM32_OPERAND_C :
27173 +      value = fields->f_C;
27174 +      break;
27175 +    case UBICOM32_OPERAND_DN :
27176 +      value = fields->f_Dn;
27177 +      break;
27178 +    case UBICOM32_OPERAND_P :
27179 +      value = fields->f_P;
27180 +      break;
27181 +    case UBICOM32_OPERAND_ACC1HI :
27182 +      value = 0;
27183 +      break;
27184 +    case UBICOM32_OPERAND_ACC1LO :
27185 +      value = 0;
27186 +      break;
27187 +    case UBICOM32_OPERAND_BIT5 :
27188 +      value = fields->f_bit5;
27189 +      break;
27190 +    case UBICOM32_OPERAND_BIT5_ADDSUB :
27191 +      value = fields->f_bit5;
27192 +      break;
27193 +    case UBICOM32_OPERAND_CC :
27194 +      value = fields->f_cond;
27195 +      break;
27196 +    case UBICOM32_OPERAND_D_AN :
27197 +      value = fields->f_d_An;
27198 +      break;
27199 +    case UBICOM32_OPERAND_D_DIRECT_ADDR :
27200 +      value = fields->f_d_direct;
27201 +      break;
27202 +    case UBICOM32_OPERAND_D_I4_1 :
27203 +      value = fields->f_d_i4_1;
27204 +      break;
27205 +    case UBICOM32_OPERAND_D_I4_2 :
27206 +      value = fields->f_d_i4_2;
27207 +      break;
27208 +    case UBICOM32_OPERAND_D_I4_4 :
27209 +      value = fields->f_d_i4_4;
27210 +      break;
27211 +    case UBICOM32_OPERAND_D_IMM7_1 :
27212 +      value = fields->f_d_imm7_1;
27213 +      break;
27214 +    case UBICOM32_OPERAND_D_IMM7_2 :
27215 +      value = fields->f_d_imm7_2;
27216 +      break;
27217 +    case UBICOM32_OPERAND_D_IMM7_4 :
27218 +      value = fields->f_d_imm7_4;
27219 +      break;
27220 +    case UBICOM32_OPERAND_D_IMM8 :
27221 +      value = fields->f_d_imm8;
27222 +      break;
27223 +    case UBICOM32_OPERAND_D_R :
27224 +      value = fields->f_d_r;
27225 +      break;
27226 +    case UBICOM32_OPERAND_DSP_S2_ACC_REG_ADDSUB :
27227 +      value = fields->f_dsp_S2;
27228 +      break;
27229 +    case UBICOM32_OPERAND_DSP_S2_ACC_REG_MUL :
27230 +      value = fields->f_dsp_S2;
27231 +      break;
27232 +    case UBICOM32_OPERAND_DSP_S2_DATA_REG :
27233 +      value = fields->f_dsp_S2;
27234 +      break;
27235 +    case UBICOM32_OPERAND_DSP_S2_DATA_REG_ADDSUB :
27236 +      value = fields->f_dsp_S2;
27237 +      break;
27238 +    case UBICOM32_OPERAND_DSP_S2_SEL :
27239 +      value = fields->f_dsp_S2_sel;
27240 +      break;
27241 +    case UBICOM32_OPERAND_DSP_C :
27242 +      value = fields->f_dsp_C;
27243 +      break;
27244 +    case UBICOM32_OPERAND_DSP_DESTA :
27245 +      value = fields->f_dsp_destA;
27246 +      break;
27247 +    case UBICOM32_OPERAND_DSP_T :
27248 +      value = fields->f_dsp_T;
27249 +      break;
27250 +    case UBICOM32_OPERAND_DSP_T_ADDSUB :
27251 +      value = fields->f_dsp_T;
27252 +      break;
27253 +    case UBICOM32_OPERAND_IMM16_1 :
27254 +      value = fields->f_imm16_1;
27255 +      break;
27256 +    case UBICOM32_OPERAND_IMM16_2 :
27257 +      value = fields->f_imm16_2;
27258 +      break;
27259 +    case UBICOM32_OPERAND_IMM24 :
27260 +      value = fields->f_imm24;
27261 +      break;
27262 +    case UBICOM32_OPERAND_INTERRUPT :
27263 +      value = fields->f_int;
27264 +      break;
27265 +    case UBICOM32_OPERAND_IREAD :
27266 +      value = 0;
27267 +      break;
27268 +    case UBICOM32_OPERAND_IRQ_0 :
27269 +      value = 0;
27270 +      break;
27271 +    case UBICOM32_OPERAND_IRQ_1 :
27272 +      value = 0;
27273 +      break;
27274 +    case UBICOM32_OPERAND_MACHI :
27275 +      value = 0;
27276 +      break;
27277 +    case UBICOM32_OPERAND_MACLO :
27278 +      value = 0;
27279 +      break;
27280 +    case UBICOM32_OPERAND_OFFSET16 :
27281 +      value = fields->f_o16;
27282 +      break;
27283 +    case UBICOM32_OPERAND_OFFSET21 :
27284 +      value = fields->f_o21;
27285 +      break;
27286 +    case UBICOM32_OPERAND_OFFSET24 :
27287 +      value = fields->f_o24;
27288 +      break;
27289 +    case UBICOM32_OPERAND_OPC1 :
27290 +      value = fields->f_op1;
27291 +      break;
27292 +    case UBICOM32_OPERAND_OPC2 :
27293 +      value = fields->f_op2;
27294 +      break;
27295 +    case UBICOM32_OPERAND_PDEC_S1_IMM7_4 :
27296 +      value = fields->f_s1_imm7_4;
27297 +      break;
27298 +    case UBICOM32_OPERAND_S1_AN :
27299 +      value = fields->f_s1_An;
27300 +      break;
27301 +    case UBICOM32_OPERAND_S1_DIRECT_ADDR :
27302 +      value = fields->f_s1_direct;
27303 +      break;
27304 +    case UBICOM32_OPERAND_S1_I4_1 :
27305 +      value = fields->f_s1_i4_1;
27306 +      break;
27307 +    case UBICOM32_OPERAND_S1_I4_2 :
27308 +      value = fields->f_s1_i4_2;
27309 +      break;
27310 +    case UBICOM32_OPERAND_S1_I4_4 :
27311 +      value = fields->f_s1_i4_4;
27312 +      break;
27313 +    case UBICOM32_OPERAND_S1_IMM7_1 :
27314 +      value = fields->f_s1_imm7_1;
27315 +      break;
27316 +    case UBICOM32_OPERAND_S1_IMM7_2 :
27317 +      value = fields->f_s1_imm7_2;
27318 +      break;
27319 +    case UBICOM32_OPERAND_S1_IMM7_4 :
27320 +      value = fields->f_s1_imm7_4;
27321 +      break;
27322 +    case UBICOM32_OPERAND_S1_IMM8 :
27323 +      value = fields->f_s1_imm8;
27324 +      break;
27325 +    case UBICOM32_OPERAND_S1_R :
27326 +      value = fields->f_s1_r;
27327 +      break;
27328 +    case UBICOM32_OPERAND_S2 :
27329 +      value = fields->f_s2;
27330 +      break;
27331 +    case UBICOM32_OPERAND_SRC3 :
27332 +      value = 0;
27333 +      break;
27334 +    case UBICOM32_OPERAND_X_BIT26 :
27335 +      value = fields->f_bit26;
27336 +      break;
27337 +    case UBICOM32_OPERAND_X_D :
27338 +      value = fields->f_d;
27339 +      break;
27340 +    case UBICOM32_OPERAND_X_DN :
27341 +      value = fields->f_Dn;
27342 +      break;
27343 +    case UBICOM32_OPERAND_X_OP2 :
27344 +      value = fields->f_op2;
27345 +      break;
27346 +    case UBICOM32_OPERAND_X_S1 :
27347 +      value = fields->f_s1;
27348 +      break;
27349 +
27350 +    default :
27351 +      /* xgettext:c-format */
27352 +      fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"),
27353 +                      opindex);
27354 +      abort ();
27355 +  }
27356 +
27357 +  return value;
27358 +}
27359 +
27360 +bfd_vma
27361 +ubicom32_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
27362 +                            int opindex,
27363 +                            const CGEN_FIELDS * fields)
27364 +{
27365 +  bfd_vma value;
27366 +
27367 +  switch (opindex)
27368 +    {
27369 +    case UBICOM32_OPERAND_AM :
27370 +      value = fields->f_Am;
27371 +      break;
27372 +    case UBICOM32_OPERAND_AN :
27373 +      value = fields->f_An;
27374 +      break;
27375 +    case UBICOM32_OPERAND_C :
27376 +      value = fields->f_C;
27377 +      break;
27378 +    case UBICOM32_OPERAND_DN :
27379 +      value = fields->f_Dn;
27380 +      break;
27381 +    case UBICOM32_OPERAND_P :
27382 +      value = fields->f_P;
27383 +      break;
27384 +    case UBICOM32_OPERAND_ACC1HI :
27385 +      value = 0;
27386 +      break;
27387 +    case UBICOM32_OPERAND_ACC1LO :
27388 +      value = 0;
27389 +      break;
27390 +    case UBICOM32_OPERAND_BIT5 :
27391 +      value = fields->f_bit5;
27392 +      break;
27393 +    case UBICOM32_OPERAND_BIT5_ADDSUB :
27394 +      value = fields->f_bit5;
27395 +      break;
27396 +    case UBICOM32_OPERAND_CC :
27397 +      value = fields->f_cond;
27398 +      break;
27399 +    case UBICOM32_OPERAND_D_AN :
27400 +      value = fields->f_d_An;
27401 +      break;
27402 +    case UBICOM32_OPERAND_D_DIRECT_ADDR :
27403 +      value = fields->f_d_direct;
27404 +      break;
27405 +    case UBICOM32_OPERAND_D_I4_1 :
27406 +      value = fields->f_d_i4_1;
27407 +      break;
27408 +    case UBICOM32_OPERAND_D_I4_2 :
27409 +      value = fields->f_d_i4_2;
27410 +      break;
27411 +    case UBICOM32_OPERAND_D_I4_4 :
27412 +      value = fields->f_d_i4_4;
27413 +      break;
27414 +    case UBICOM32_OPERAND_D_IMM7_1 :
27415 +      value = fields->f_d_imm7_1;
27416 +      break;
27417 +    case UBICOM32_OPERAND_D_IMM7_2 :
27418 +      value = fields->f_d_imm7_2;
27419 +      break;
27420 +    case UBICOM32_OPERAND_D_IMM7_4 :
27421 +      value = fields->f_d_imm7_4;
27422 +      break;
27423 +    case UBICOM32_OPERAND_D_IMM8 :
27424 +      value = fields->f_d_imm8;
27425 +      break;
27426 +    case UBICOM32_OPERAND_D_R :
27427 +      value = fields->f_d_r;
27428 +      break;
27429 +    case UBICOM32_OPERAND_DSP_S2_ACC_REG_ADDSUB :
27430 +      value = fields->f_dsp_S2;
27431 +      break;
27432 +    case UBICOM32_OPERAND_DSP_S2_ACC_REG_MUL :
27433 +      value = fields->f_dsp_S2;
27434 +      break;
27435 +    case UBICOM32_OPERAND_DSP_S2_DATA_REG :
27436 +      value = fields->f_dsp_S2;
27437 +      break;
27438 +    case UBICOM32_OPERAND_DSP_S2_DATA_REG_ADDSUB :
27439 +      value = fields->f_dsp_S2;
27440 +      break;
27441 +    case UBICOM32_OPERAND_DSP_S2_SEL :
27442 +      value = fields->f_dsp_S2_sel;
27443 +      break;
27444 +    case UBICOM32_OPERAND_DSP_C :
27445 +      value = fields->f_dsp_C;
27446 +      break;
27447 +    case UBICOM32_OPERAND_DSP_DESTA :
27448 +      value = fields->f_dsp_destA;
27449 +      break;
27450 +    case UBICOM32_OPERAND_DSP_T :
27451 +      value = fields->f_dsp_T;
27452 +      break;
27453 +    case UBICOM32_OPERAND_DSP_T_ADDSUB :
27454 +      value = fields->f_dsp_T;
27455 +      break;
27456 +    case UBICOM32_OPERAND_IMM16_1 :
27457 +      value = fields->f_imm16_1;
27458 +      break;
27459 +    case UBICOM32_OPERAND_IMM16_2 :
27460 +      value = fields->f_imm16_2;
27461 +      break;
27462 +    case UBICOM32_OPERAND_IMM24 :
27463 +      value = fields->f_imm24;
27464 +      break;
27465 +    case UBICOM32_OPERAND_INTERRUPT :
27466 +      value = fields->f_int;
27467 +      break;
27468 +    case UBICOM32_OPERAND_IREAD :
27469 +      value = 0;
27470 +      break;
27471 +    case UBICOM32_OPERAND_IRQ_0 :
27472 +      value = 0;
27473 +      break;
27474 +    case UBICOM32_OPERAND_IRQ_1 :
27475 +      value = 0;
27476 +      break;
27477 +    case UBICOM32_OPERAND_MACHI :
27478 +      value = 0;
27479 +      break;
27480 +    case UBICOM32_OPERAND_MACLO :
27481 +      value = 0;
27482 +      break;
27483 +    case UBICOM32_OPERAND_OFFSET16 :
27484 +      value = fields->f_o16;
27485 +      break;
27486 +    case UBICOM32_OPERAND_OFFSET21 :
27487 +      value = fields->f_o21;
27488 +      break;
27489 +    case UBICOM32_OPERAND_OFFSET24 :
27490 +      value = fields->f_o24;
27491 +      break;
27492 +    case UBICOM32_OPERAND_OPC1 :
27493 +      value = fields->f_op1;
27494 +      break;
27495 +    case UBICOM32_OPERAND_OPC2 :
27496 +      value = fields->f_op2;
27497 +      break;
27498 +    case UBICOM32_OPERAND_PDEC_S1_IMM7_4 :
27499 +      value = fields->f_s1_imm7_4;
27500 +      break;
27501 +    case UBICOM32_OPERAND_S1_AN :
27502 +      value = fields->f_s1_An;
27503 +      break;
27504 +    case UBICOM32_OPERAND_S1_DIRECT_ADDR :
27505 +      value = fields->f_s1_direct;
27506 +      break;
27507 +    case UBICOM32_OPERAND_S1_I4_1 :
27508 +      value = fields->f_s1_i4_1;
27509 +      break;
27510 +    case UBICOM32_OPERAND_S1_I4_2 :
27511 +      value = fields->f_s1_i4_2;
27512 +      break;
27513 +    case UBICOM32_OPERAND_S1_I4_4 :
27514 +      value = fields->f_s1_i4_4;
27515 +      break;
27516 +    case UBICOM32_OPERAND_S1_IMM7_1 :
27517 +      value = fields->f_s1_imm7_1;
27518 +      break;
27519 +    case UBICOM32_OPERAND_S1_IMM7_2 :
27520 +      value = fields->f_s1_imm7_2;
27521 +      break;
27522 +    case UBICOM32_OPERAND_S1_IMM7_4 :
27523 +      value = fields->f_s1_imm7_4;
27524 +      break;
27525 +    case UBICOM32_OPERAND_S1_IMM8 :
27526 +      value = fields->f_s1_imm8;
27527 +      break;
27528 +    case UBICOM32_OPERAND_S1_R :
27529 +      value = fields->f_s1_r;
27530 +      break;
27531 +    case UBICOM32_OPERAND_S2 :
27532 +      value = fields->f_s2;
27533 +      break;
27534 +    case UBICOM32_OPERAND_SRC3 :
27535 +      value = 0;
27536 +      break;
27537 +    case UBICOM32_OPERAND_X_BIT26 :
27538 +      value = fields->f_bit26;
27539 +      break;
27540 +    case UBICOM32_OPERAND_X_D :
27541 +      value = fields->f_d;
27542 +      break;
27543 +    case UBICOM32_OPERAND_X_DN :
27544 +      value = fields->f_Dn;
27545 +      break;
27546 +    case UBICOM32_OPERAND_X_OP2 :
27547 +      value = fields->f_op2;
27548 +      break;
27549 +    case UBICOM32_OPERAND_X_S1 :
27550 +      value = fields->f_s1;
27551 +      break;
27552 +
27553 +    default :
27554 +      /* xgettext:c-format */
27555 +      fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"),
27556 +                      opindex);
27557 +      abort ();
27558 +  }
27559 +
27560 +  return value;
27561 +}
27562 +
27563 +void ubicom32_cgen_set_int_operand  (CGEN_CPU_DESC, int, CGEN_FIELDS *, int);
27564 +void ubicom32_cgen_set_vma_operand  (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma);
27565 +
27566 +/* Stuffing values in cgen_fields is handled by a collection of functions.
27567 +   They are distinguished by the type of the VALUE argument they accept.
27568 +   TODO: floating point, inlining support, remove cases where argument type
27569 +   not appropriate.  */
27570 +
27571 +void
27572 +ubicom32_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
27573 +                            int opindex,
27574 +                            CGEN_FIELDS * fields,
27575 +                            int value)
27576 +{
27577 +  switch (opindex)
27578 +    {
27579 +    case UBICOM32_OPERAND_AM :
27580 +      fields->f_Am = value;
27581 +      break;
27582 +    case UBICOM32_OPERAND_AN :
27583 +      fields->f_An = value;
27584 +      break;
27585 +    case UBICOM32_OPERAND_C :
27586 +      fields->f_C = value;
27587 +      break;
27588 +    case UBICOM32_OPERAND_DN :
27589 +      fields->f_Dn = value;
27590 +      break;
27591 +    case UBICOM32_OPERAND_P :
27592 +      fields->f_P = value;
27593 +      break;
27594 +    case UBICOM32_OPERAND_ACC1HI :
27595 +      break;
27596 +    case UBICOM32_OPERAND_ACC1LO :
27597 +      break;
27598 +    case UBICOM32_OPERAND_BIT5 :
27599 +      fields->f_bit5 = value;
27600 +      break;
27601 +    case UBICOM32_OPERAND_BIT5_ADDSUB :
27602 +      fields->f_bit5 = value;
27603 +      break;
27604 +    case UBICOM32_OPERAND_CC :
27605 +      fields->f_cond = value;
27606 +      break;
27607 +    case UBICOM32_OPERAND_D_AN :
27608 +      fields->f_d_An = value;
27609 +      break;
27610 +    case UBICOM32_OPERAND_D_DIRECT_ADDR :
27611 +      fields->f_d_direct = value;
27612 +      break;
27613 +    case UBICOM32_OPERAND_D_I4_1 :
27614 +      fields->f_d_i4_1 = value;
27615 +      break;
27616 +    case UBICOM32_OPERAND_D_I4_2 :
27617 +      fields->f_d_i4_2 = value;
27618 +      break;
27619 +    case UBICOM32_OPERAND_D_I4_4 :
27620 +      fields->f_d_i4_4 = value;
27621 +      break;
27622 +    case UBICOM32_OPERAND_D_IMM7_1 :
27623 +      fields->f_d_imm7_1 = value;
27624 +      break;
27625 +    case UBICOM32_OPERAND_D_IMM7_2 :
27626 +      fields->f_d_imm7_2 = value;
27627 +      break;
27628 +    case UBICOM32_OPERAND_D_IMM7_4 :
27629 +      fields->f_d_imm7_4 = value;
27630 +      break;
27631 +    case UBICOM32_OPERAND_D_IMM8 :
27632 +      fields->f_d_imm8 = value;
27633 +      break;
27634 +    case UBICOM32_OPERAND_D_R :
27635 +      fields->f_d_r = value;
27636 +      break;
27637 +    case UBICOM32_OPERAND_DSP_S2_ACC_REG_ADDSUB :
27638 +      fields->f_dsp_S2 = value;
27639 +      break;
27640 +    case UBICOM32_OPERAND_DSP_S2_ACC_REG_MUL :
27641 +      fields->f_dsp_S2 = value;
27642 +      break;
27643 +    case UBICOM32_OPERAND_DSP_S2_DATA_REG :
27644 +      fields->f_dsp_S2 = value;
27645 +      break;
27646 +    case UBICOM32_OPERAND_DSP_S2_DATA_REG_ADDSUB :
27647 +      fields->f_dsp_S2 = value;
27648 +      break;
27649 +    case UBICOM32_OPERAND_DSP_S2_SEL :
27650 +      fields->f_dsp_S2_sel = value;
27651 +      break;
27652 +    case UBICOM32_OPERAND_DSP_C :
27653 +      fields->f_dsp_C = value;
27654 +      break;
27655 +    case UBICOM32_OPERAND_DSP_DESTA :
27656 +      fields->f_dsp_destA = value;
27657 +      break;
27658 +    case UBICOM32_OPERAND_DSP_T :
27659 +      fields->f_dsp_T = value;
27660 +      break;
27661 +    case UBICOM32_OPERAND_DSP_T_ADDSUB :
27662 +      fields->f_dsp_T = value;
27663 +      break;
27664 +    case UBICOM32_OPERAND_IMM16_1 :
27665 +      fields->f_imm16_1 = value;
27666 +      break;
27667 +    case UBICOM32_OPERAND_IMM16_2 :
27668 +      fields->f_imm16_2 = value;
27669 +      break;
27670 +    case UBICOM32_OPERAND_IMM24 :
27671 +      fields->f_imm24 = value;
27672 +      break;
27673 +    case UBICOM32_OPERAND_INTERRUPT :
27674 +      fields->f_int = value;
27675 +      break;
27676 +    case UBICOM32_OPERAND_IREAD :
27677 +      break;
27678 +    case UBICOM32_OPERAND_IRQ_0 :
27679 +      break;
27680 +    case UBICOM32_OPERAND_IRQ_1 :
27681 +      break;
27682 +    case UBICOM32_OPERAND_MACHI :
27683 +      break;
27684 +    case UBICOM32_OPERAND_MACLO :
27685 +      break;
27686 +    case UBICOM32_OPERAND_OFFSET16 :
27687 +      fields->f_o16 = value;
27688 +      break;
27689 +    case UBICOM32_OPERAND_OFFSET21 :
27690 +      fields->f_o21 = value;
27691 +      break;
27692 +    case UBICOM32_OPERAND_OFFSET24 :
27693 +      fields->f_o24 = value;
27694 +      break;
27695 +    case UBICOM32_OPERAND_OPC1 :
27696 +      fields->f_op1 = value;
27697 +      break;
27698 +    case UBICOM32_OPERAND_OPC2 :
27699 +      fields->f_op2 = value;
27700 +      break;
27701 +    case UBICOM32_OPERAND_PDEC_S1_IMM7_4 :
27702 +      fields->f_s1_imm7_4 = value;
27703 +      break;
27704 +    case UBICOM32_OPERAND_S1_AN :
27705 +      fields->f_s1_An = value;
27706 +      break;
27707 +    case UBICOM32_OPERAND_S1_DIRECT_ADDR :
27708 +      fields->f_s1_direct = value;
27709 +      break;
27710 +    case UBICOM32_OPERAND_S1_I4_1 :
27711 +      fields->f_s1_i4_1 = value;
27712 +      break;
27713 +    case UBICOM32_OPERAND_S1_I4_2 :
27714 +      fields->f_s1_i4_2 = value;
27715 +      break;
27716 +    case UBICOM32_OPERAND_S1_I4_4 :
27717 +      fields->f_s1_i4_4 = value;
27718 +      break;
27719 +    case UBICOM32_OPERAND_S1_IMM7_1 :
27720 +      fields->f_s1_imm7_1 = value;
27721 +      break;
27722 +    case UBICOM32_OPERAND_S1_IMM7_2 :
27723 +      fields->f_s1_imm7_2 = value;
27724 +      break;
27725 +    case UBICOM32_OPERAND_S1_IMM7_4 :
27726 +      fields->f_s1_imm7_4 = value;
27727 +      break;
27728 +    case UBICOM32_OPERAND_S1_IMM8 :
27729 +      fields->f_s1_imm8 = value;
27730 +      break;
27731 +    case UBICOM32_OPERAND_S1_R :
27732 +      fields->f_s1_r = value;
27733 +      break;
27734 +    case UBICOM32_OPERAND_S2 :
27735 +      fields->f_s2 = value;
27736 +      break;
27737 +    case UBICOM32_OPERAND_SRC3 :
27738 +      break;
27739 +    case UBICOM32_OPERAND_X_BIT26 :
27740 +      fields->f_bit26 = value;
27741 +      break;
27742 +    case UBICOM32_OPERAND_X_D :
27743 +      fields->f_d = value;
27744 +      break;
27745 +    case UBICOM32_OPERAND_X_DN :
27746 +      fields->f_Dn = value;
27747 +      break;
27748 +    case UBICOM32_OPERAND_X_OP2 :
27749 +      fields->f_op2 = value;
27750 +      break;
27751 +    case UBICOM32_OPERAND_X_S1 :
27752 +      fields->f_s1 = value;
27753 +      break;
27754 +
27755 +    default :
27756 +      /* xgettext:c-format */
27757 +      fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"),
27758 +                      opindex);
27759 +      abort ();
27760 +  }
27761 +}
27762 +
27763 +void
27764 +ubicom32_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
27765 +                            int opindex,
27766 +                            CGEN_FIELDS * fields,
27767 +                            bfd_vma value)
27768 +{
27769 +  switch (opindex)
27770 +    {
27771 +    case UBICOM32_OPERAND_AM :
27772 +      fields->f_Am = value;
27773 +      break;
27774 +    case UBICOM32_OPERAND_AN :
27775 +      fields->f_An = value;
27776 +      break;
27777 +    case UBICOM32_OPERAND_C :
27778 +      fields->f_C = value;
27779 +      break;
27780 +    case UBICOM32_OPERAND_DN :
27781 +      fields->f_Dn = value;
27782 +      break;
27783 +    case UBICOM32_OPERAND_P :
27784 +      fields->f_P = value;
27785 +      break;
27786 +    case UBICOM32_OPERAND_ACC1HI :
27787 +      break;
27788 +    case UBICOM32_OPERAND_ACC1LO :
27789 +      break;
27790 +    case UBICOM32_OPERAND_BIT5 :
27791 +      fields->f_bit5 = value;
27792 +      break;
27793 +    case UBICOM32_OPERAND_BIT5_ADDSUB :
27794 +      fields->f_bit5 = value;
27795 +      break;
27796 +    case UBICOM32_OPERAND_CC :
27797 +      fields->f_cond = value;
27798 +      break;
27799 +    case UBICOM32_OPERAND_D_AN :
27800 +      fields->f_d_An = value;
27801 +      break;
27802 +    case UBICOM32_OPERAND_D_DIRECT_ADDR :
27803 +      fields->f_d_direct = value;
27804 +      break;
27805 +    case UBICOM32_OPERAND_D_I4_1 :
27806 +      fields->f_d_i4_1 = value;
27807 +      break;
27808 +    case UBICOM32_OPERAND_D_I4_2 :
27809 +      fields->f_d_i4_2 = value;
27810 +      break;
27811 +    case UBICOM32_OPERAND_D_I4_4 :
27812 +      fields->f_d_i4_4 = value;
27813 +      break;
27814 +    case UBICOM32_OPERAND_D_IMM7_1 :
27815 +      fields->f_d_imm7_1 = value;
27816 +      break;
27817 +    case UBICOM32_OPERAND_D_IMM7_2 :
27818 +      fields->f_d_imm7_2 = value;
27819 +      break;
27820 +    case UBICOM32_OPERAND_D_IMM7_4 :
27821 +      fields->f_d_imm7_4 = value;
27822 +      break;
27823 +    case UBICOM32_OPERAND_D_IMM8 :
27824 +      fields->f_d_imm8 = value;
27825 +      break;
27826 +    case UBICOM32_OPERAND_D_R :
27827 +      fields->f_d_r = value;
27828 +      break;
27829 +    case UBICOM32_OPERAND_DSP_S2_ACC_REG_ADDSUB :
27830 +      fields->f_dsp_S2 = value;
27831 +      break;
27832 +    case UBICOM32_OPERAND_DSP_S2_ACC_REG_MUL :
27833 +      fields->f_dsp_S2 = value;
27834 +      break;
27835 +    case UBICOM32_OPERAND_DSP_S2_DATA_REG :
27836 +      fields->f_dsp_S2 = value;
27837 +      break;
27838 +    case UBICOM32_OPERAND_DSP_S2_DATA_REG_ADDSUB :
27839 +      fields->f_dsp_S2 = value;
27840 +      break;
27841 +    case UBICOM32_OPERAND_DSP_S2_SEL :
27842 +      fields->f_dsp_S2_sel = value;
27843 +      break;
27844 +    case UBICOM32_OPERAND_DSP_C :
27845 +      fields->f_dsp_C = value;
27846 +      break;
27847 +    case UBICOM32_OPERAND_DSP_DESTA :
27848 +      fields->f_dsp_destA = value;
27849 +      break;
27850 +    case UBICOM32_OPERAND_DSP_T :
27851 +      fields->f_dsp_T = value;
27852 +      break;
27853 +    case UBICOM32_OPERAND_DSP_T_ADDSUB :
27854 +      fields->f_dsp_T = value;
27855 +      break;
27856 +    case UBICOM32_OPERAND_IMM16_1 :
27857 +      fields->f_imm16_1 = value;
27858 +      break;
27859 +    case UBICOM32_OPERAND_IMM16_2 :
27860 +      fields->f_imm16_2 = value;
27861 +      break;
27862 +    case UBICOM32_OPERAND_IMM24 :
27863 +      fields->f_imm24 = value;
27864 +      break;
27865 +    case UBICOM32_OPERAND_INTERRUPT :
27866 +      fields->f_int = value;
27867 +      break;
27868 +    case UBICOM32_OPERAND_IREAD :
27869 +      break;
27870 +    case UBICOM32_OPERAND_IRQ_0 :
27871 +      break;
27872 +    case UBICOM32_OPERAND_IRQ_1 :
27873 +      break;
27874 +    case UBICOM32_OPERAND_MACHI :
27875 +      break;
27876 +    case UBICOM32_OPERAND_MACLO :
27877 +      break;
27878 +    case UBICOM32_OPERAND_OFFSET16 :
27879 +      fields->f_o16 = value;
27880 +      break;
27881 +    case UBICOM32_OPERAND_OFFSET21 :
27882 +      fields->f_o21 = value;
27883 +      break;
27884 +    case UBICOM32_OPERAND_OFFSET24 :
27885 +      fields->f_o24 = value;
27886 +      break;
27887 +    case UBICOM32_OPERAND_OPC1 :
27888 +      fields->f_op1 = value;
27889 +      break;
27890 +    case UBICOM32_OPERAND_OPC2 :
27891 +      fields->f_op2 = value;
27892 +      break;
27893 +    case UBICOM32_OPERAND_PDEC_S1_IMM7_4 :
27894 +      fields->f_s1_imm7_4 = value;
27895 +      break;
27896 +    case UBICOM32_OPERAND_S1_AN :
27897 +      fields->f_s1_An = value;
27898 +      break;
27899 +    case UBICOM32_OPERAND_S1_DIRECT_ADDR :
27900 +      fields->f_s1_direct = value;
27901 +      break;
27902 +    case UBICOM32_OPERAND_S1_I4_1 :
27903 +      fields->f_s1_i4_1 = value;
27904 +      break;
27905 +    case UBICOM32_OPERAND_S1_I4_2 :
27906 +      fields->f_s1_i4_2 = value;
27907 +      break;
27908 +    case UBICOM32_OPERAND_S1_I4_4 :
27909 +      fields->f_s1_i4_4 = value;
27910 +      break;
27911 +    case UBICOM32_OPERAND_S1_IMM7_1 :
27912 +      fields->f_s1_imm7_1 = value;
27913 +      break;
27914 +    case UBICOM32_OPERAND_S1_IMM7_2 :
27915 +      fields->f_s1_imm7_2 = value;
27916 +      break;
27917 +    case UBICOM32_OPERAND_S1_IMM7_4 :
27918 +      fields->f_s1_imm7_4 = value;
27919 +      break;
27920 +    case UBICOM32_OPERAND_S1_IMM8 :
27921 +      fields->f_s1_imm8 = value;
27922 +      break;
27923 +    case UBICOM32_OPERAND_S1_R :
27924 +      fields->f_s1_r = value;
27925 +      break;
27926 +    case UBICOM32_OPERAND_S2 :
27927 +      fields->f_s2 = value;
27928 +      break;
27929 +    case UBICOM32_OPERAND_SRC3 :
27930 +      break;
27931 +    case UBICOM32_OPERAND_X_BIT26 :
27932 +      fields->f_bit26 = value;
27933 +      break;
27934 +    case UBICOM32_OPERAND_X_D :
27935 +      fields->f_d = value;
27936 +      break;
27937 +    case UBICOM32_OPERAND_X_DN :
27938 +      fields->f_Dn = value;
27939 +      break;
27940 +    case UBICOM32_OPERAND_X_OP2 :
27941 +      fields->f_op2 = value;
27942 +      break;
27943 +    case UBICOM32_OPERAND_X_S1 :
27944 +      fields->f_s1 = value;
27945 +      break;
27946 +
27947 +    default :
27948 +      /* xgettext:c-format */
27949 +      fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"),
27950 +                      opindex);
27951 +      abort ();
27952 +  }
27953 +}
27954 +
27955 +/* Function to call before using the instruction builder tables.  */
27956 +
27957 +void
27958 +ubicom32_cgen_init_ibld_table (CGEN_CPU_DESC cd)
27959 +{
27960 +  cd->insert_handlers = & ubicom32_cgen_insert_handlers[0];
27961 +  cd->extract_handlers = & ubicom32_cgen_extract_handlers[0];
27962 +
27963 +  cd->insert_operand = ubicom32_cgen_insert_operand;
27964 +  cd->extract_operand = ubicom32_cgen_extract_operand;
27965 +
27966 +  cd->get_int_operand = ubicom32_cgen_get_int_operand;
27967 +  cd->set_int_operand = ubicom32_cgen_set_int_operand;
27968 +  cd->get_vma_operand = ubicom32_cgen_get_vma_operand;
27969 +  cd->set_vma_operand = ubicom32_cgen_set_vma_operand;
27970 +}
27971 --- /dev/null
27972 +++ b/opcodes/ubicom32-opc.c
27973 @@ -0,0 +1,20075 @@
27974 +/* Instruction opcode table for ubicom32.
27975 +
27976 +THIS FILE IS MACHINE GENERATED WITH CGEN.
27977 +
27978 +Copyright 1996-2007 Free Software Foundation, Inc.
27979 +
27980 +This file is part of the GNU Binutils and/or GDB, the GNU debugger.
27981 +
27982 +   This file is free software; you can redistribute it and/or modify
27983 +   it under the terms of the GNU General Public License as published by
27984 +   the Free Software Foundation; either version 3, or (at your option)
27985 +   any later version.
27986 +
27987 +   It is distributed in the hope that it will be useful, but WITHOUT
27988 +   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
27989 +   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
27990 +   License for more details.
27991 +
27992 +   You should have received a copy of the GNU General Public License along
27993 +   with this program; if not, write to the Free Software Foundation, Inc.,
27994 +   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
27995 +
27996 +*/
27997 +
27998 +#include "sysdep.h"
27999 +#include "ansidecl.h"
28000 +#include "bfd.h"
28001 +#include "symcat.h"
28002 +#include "ubicom32-desc.h"
28003 +#include "ubicom32-opc.h"
28004 +#include "libiberty.h"
28005 +
28006 +/* -- opc.c */
28007 +#include "safe-ctype.h"
28008 +
28009 +unsigned int
28010 +ubicom32_dis_hash (const char *buf, CGEN_INSN_INT value ATTRIBUTE_UNUSED)
28011 +{
28012 +  unsigned int hash = (*buf >> 3);
28013 +  return hash % CGEN_DIS_HASH_SIZE;
28014 +}
28015 +
28016 +
28017 +/* A better hash function for instruction mnemonics. */
28018 +unsigned int
28019 +ubicom32_asm_hash (const char* insn)
28020 +{
28021 +  unsigned int hash;
28022 +  const char* m = insn;
28023 +
28024 +  /* for certain instructions, the variations are coded as operands
28025 +     and so only the mnemonic will have been used to seed the hash table.
28026 +     Examples of this are the jmp family and the int instruction.
28027 +     If we suspect we may have these instructions, just use the first 3 chars.
28028 +   */
28029 +  if (*m == 'j' || *m == 'i' || *m=='m')
28030 +    {
28031 +      int i = 0;
28032 +      for (hash = 0; *m && !ISSPACE(*m) && i < 3; m++, ++i)
28033 +        hash = (hash * 23) ^ (0x1F & TOLOWER(*m));
28034 +    }
28035 +  else
28036 +    {
28037 +      for (hash = 0; *m && !ISSPACE(*m); m++)
28038 +        hash = (hash * 23) ^ (0x1F & TOLOWER(*m));
28039 +    }
28040 +
28041 +  /* printf ("%s %d\n", insn, (hash % CGEN_ASM_HASH_SIZE)); */
28042 +
28043 +  return hash % CGEN_ASM_HASH_SIZE;
28044 +}
28045 +
28046 +/* Special check to ensure that instruction exists for given machine. */
28047 +int
28048 +ubicom32_cgen_insn_supported (CGEN_CPU_DESC cd,
28049 +                         const CGEN_INSN *insn)
28050 +{
28051 +  int machs = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH);
28052 +
28053 +  /* No mach attribute?  Assume it's supported for all machs.  */
28054 +  if (machs == 0)
28055 +    return 1;
28056 +  
28057 +  return ((machs & cd->machs) != 0);
28058 +}
28059 +
28060 +/* -- asm.c */
28061 +/* The hash functions are recorded here to help keep assembler code out of
28062 +   the disassembler and vice versa.  */
28063 +
28064 +static int asm_hash_insn_p        (const CGEN_INSN *);
28065 +static unsigned int asm_hash_insn (const char *);
28066 +static int dis_hash_insn_p        (const CGEN_INSN *);
28067 +static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT);
28068 +
28069 +/* Instruction formats.  */
28070 +
28071 +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
28072 +#define F(f) & ubicom32_cgen_ifld_table[UBICOM32_##f]
28073 +#else
28074 +#define F(f) & ubicom32_cgen_ifld_table[UBICOM32_/**/f]
28075 +#endif
28076 +static const CGEN_IFMT ifmt_empty ATTRIBUTE_UNUSED = {
28077 +  0, 0, 0x0, { { 0 } }
28078 +};
28079 +
28080 +static const CGEN_IFMT ifmt_dsp_msub_2_s1_direct_dsp_src2_data_reg_addsub2 ATTRIBUTE_UNUSED = {
28081 +  32, 32, 0xffe68700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28082 +};
28083 +
28084 +static const CGEN_IFMT ifmt_dsp_msub_2_s1_immediate_dsp_src2_data_reg_addsub2 ATTRIBUTE_UNUSED = {
28085 +  32, 32, 0xffe68700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28086 +};
28087 +
28088 +static const CGEN_IFMT ifmt_dsp_msub_2_s1_indirect_with_index_2_dsp_src2_data_reg_addsub2 ATTRIBUTE_UNUSED = {
28089 +  32, 32, 0xffe68700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28090 +};
28091 +
28092 +static const CGEN_IFMT ifmt_dsp_msub_2_s1_indirect_with_offset_2_dsp_src2_data_reg_addsub2 ATTRIBUTE_UNUSED = {
28093 +  32, 32, 0xffe68400, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28094 +};
28095 +
28096 +static const CGEN_IFMT ifmt_dsp_msub_2_s1_indirect_2_dsp_src2_data_reg_addsub2 ATTRIBUTE_UNUSED = {
28097 +  32, 32, 0xffe6871f, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28098 +};
28099 +
28100 +static const CGEN_IFMT ifmt_dsp_msub_2_s1_indirect_with_post_increment_2_dsp_src2_data_reg_addsub2 ATTRIBUTE_UNUSED = {
28101 +  32, 32, 0xffe68710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28102 +};
28103 +
28104 +static const CGEN_IFMT ifmt_dsp_msub_2_s1_indirect_with_pre_increment_2_dsp_src2_data_reg_addsub2 ATTRIBUTE_UNUSED = {
28105 +  32, 32, 0xffe68710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28106 +};
28107 +
28108 +static const CGEN_IFMT ifmt_dsp_msub_2_s1_direct_dsp_src2_reg_acc_reg_addsub ATTRIBUTE_UNUSED = {
28109 +  32, 32, 0xffe68700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28110 +};
28111 +
28112 +static const CGEN_IFMT ifmt_dsp_msub_2_s1_immediate_dsp_src2_reg_acc_reg_addsub ATTRIBUTE_UNUSED = {
28113 +  32, 32, 0xffe68700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28114 +};
28115 +
28116 +static const CGEN_IFMT ifmt_dsp_msub_2_s1_indirect_with_index_2_dsp_src2_reg_acc_reg_addsub ATTRIBUTE_UNUSED = {
28117 +  32, 32, 0xffe68700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28118 +};
28119 +
28120 +static const CGEN_IFMT ifmt_dsp_msub_2_s1_indirect_with_offset_2_dsp_src2_reg_acc_reg_addsub ATTRIBUTE_UNUSED = {
28121 +  32, 32, 0xffe68400, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28122 +};
28123 +
28124 +static const CGEN_IFMT ifmt_dsp_msub_2_s1_indirect_2_dsp_src2_reg_acc_reg_addsub ATTRIBUTE_UNUSED = {
28125 +  32, 32, 0xffe6871f, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28126 +};
28127 +
28128 +static const CGEN_IFMT ifmt_dsp_msub_2_s1_indirect_with_post_increment_2_dsp_src2_reg_acc_reg_addsub ATTRIBUTE_UNUSED = {
28129 +  32, 32, 0xffe68710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28130 +};
28131 +
28132 +static const CGEN_IFMT ifmt_dsp_msub_2_s1_indirect_with_pre_increment_2_dsp_src2_reg_acc_reg_addsub ATTRIBUTE_UNUSED = {
28133 +  32, 32, 0xffe68710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28134 +};
28135 +
28136 +static const CGEN_IFMT ifmt_dsp_msub_2_s1_direct_dsp_imm_bit5_addsub2 ATTRIBUTE_UNUSED = {
28137 +  32, 32, 0xffe60700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } }
28138 +};
28139 +
28140 +static const CGEN_IFMT ifmt_dsp_msub_2_s1_immediate_dsp_imm_bit5_addsub2 ATTRIBUTE_UNUSED = {
28141 +  32, 32, 0xffe60700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } }
28142 +};
28143 +
28144 +static const CGEN_IFMT ifmt_dsp_msub_2_s1_indirect_with_index_2_dsp_imm_bit5_addsub2 ATTRIBUTE_UNUSED = {
28145 +  32, 32, 0xffe60700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } }
28146 +};
28147 +
28148 +static const CGEN_IFMT ifmt_dsp_msub_2_s1_indirect_with_offset_2_dsp_imm_bit5_addsub2 ATTRIBUTE_UNUSED = {
28149 +  32, 32, 0xffe60400, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } }
28150 +};
28151 +
28152 +static const CGEN_IFMT ifmt_dsp_msub_2_s1_indirect_2_dsp_imm_bit5_addsub2 ATTRIBUTE_UNUSED = {
28153 +  32, 32, 0xffe6071f, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } }
28154 +};
28155 +
28156 +static const CGEN_IFMT ifmt_dsp_msub_2_s1_indirect_with_post_increment_2_dsp_imm_bit5_addsub2 ATTRIBUTE_UNUSED = {
28157 +  32, 32, 0xffe60710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } }
28158 +};
28159 +
28160 +static const CGEN_IFMT ifmt_dsp_msub_2_s1_indirect_with_pre_increment_2_dsp_imm_bit5_addsub2 ATTRIBUTE_UNUSED = {
28161 +  32, 32, 0xffe60710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } }
28162 +};
28163 +
28164 +static const CGEN_IFMT ifmt_dsp_msub_4_s1_direct_dsp_src2_data_reg_addsub ATTRIBUTE_UNUSED = {
28165 +  32, 32, 0xffee8700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28166 +};
28167 +
28168 +static const CGEN_IFMT ifmt_dsp_msub_4_s1_immediate_dsp_src2_data_reg_addsub ATTRIBUTE_UNUSED = {
28169 +  32, 32, 0xffee8700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28170 +};
28171 +
28172 +static const CGEN_IFMT ifmt_dsp_msub_4_s1_indirect_with_index_4_dsp_src2_data_reg_addsub ATTRIBUTE_UNUSED = {
28173 +  32, 32, 0xffee8700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28174 +};
28175 +
28176 +static const CGEN_IFMT ifmt_dsp_msub_4_s1_indirect_with_offset_4_dsp_src2_data_reg_addsub ATTRIBUTE_UNUSED = {
28177 +  32, 32, 0xffee8400, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28178 +};
28179 +
28180 +static const CGEN_IFMT ifmt_dsp_msub_4_s1_indirect_4_dsp_src2_data_reg_addsub ATTRIBUTE_UNUSED = {
28181 +  32, 32, 0xffee871f, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28182 +};
28183 +
28184 +static const CGEN_IFMT ifmt_dsp_msub_4_s1_indirect_with_post_increment_4_dsp_src2_data_reg_addsub ATTRIBUTE_UNUSED = {
28185 +  32, 32, 0xffee8710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28186 +};
28187 +
28188 +static const CGEN_IFMT ifmt_dsp_msub_4_s1_indirect_with_pre_increment_4_dsp_src2_data_reg_addsub ATTRIBUTE_UNUSED = {
28189 +  32, 32, 0xffee8710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28190 +};
28191 +
28192 +static const CGEN_IFMT ifmt_dsp_msub_4_s1_direct_dsp_src2_reg_acc_reg_addsub ATTRIBUTE_UNUSED = {
28193 +  32, 32, 0xffee8700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28194 +};
28195 +
28196 +static const CGEN_IFMT ifmt_dsp_msub_4_s1_immediate_dsp_src2_reg_acc_reg_addsub ATTRIBUTE_UNUSED = {
28197 +  32, 32, 0xffee8700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28198 +};
28199 +
28200 +static const CGEN_IFMT ifmt_dsp_msub_4_s1_indirect_with_index_4_dsp_src2_reg_acc_reg_addsub ATTRIBUTE_UNUSED = {
28201 +  32, 32, 0xffee8700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28202 +};
28203 +
28204 +static const CGEN_IFMT ifmt_dsp_msub_4_s1_indirect_with_offset_4_dsp_src2_reg_acc_reg_addsub ATTRIBUTE_UNUSED = {
28205 +  32, 32, 0xffee8400, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28206 +};
28207 +
28208 +static const CGEN_IFMT ifmt_dsp_msub_4_s1_indirect_4_dsp_src2_reg_acc_reg_addsub ATTRIBUTE_UNUSED = {
28209 +  32, 32, 0xffee871f, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28210 +};
28211 +
28212 +static const CGEN_IFMT ifmt_dsp_msub_4_s1_indirect_with_post_increment_4_dsp_src2_reg_acc_reg_addsub ATTRIBUTE_UNUSED = {
28213 +  32, 32, 0xffee8710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28214 +};
28215 +
28216 +static const CGEN_IFMT ifmt_dsp_msub_4_s1_indirect_with_pre_increment_4_dsp_src2_reg_acc_reg_addsub ATTRIBUTE_UNUSED = {
28217 +  32, 32, 0xffee8710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28218 +};
28219 +
28220 +static const CGEN_IFMT ifmt_dsp_msub_4_s1_direct_dsp_imm_bit5_addsub ATTRIBUTE_UNUSED = {
28221 +  32, 32, 0xffee0700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } }
28222 +};
28223 +
28224 +static const CGEN_IFMT ifmt_dsp_msub_4_s1_immediate_dsp_imm_bit5_addsub ATTRIBUTE_UNUSED = {
28225 +  32, 32, 0xffee0700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } }
28226 +};
28227 +
28228 +static const CGEN_IFMT ifmt_dsp_msub_4_s1_indirect_with_index_4_dsp_imm_bit5_addsub ATTRIBUTE_UNUSED = {
28229 +  32, 32, 0xffee0700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } }
28230 +};
28231 +
28232 +static const CGEN_IFMT ifmt_dsp_msub_4_s1_indirect_with_offset_4_dsp_imm_bit5_addsub ATTRIBUTE_UNUSED = {
28233 +  32, 32, 0xffee0400, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } }
28234 +};
28235 +
28236 +static const CGEN_IFMT ifmt_dsp_msub_4_s1_indirect_4_dsp_imm_bit5_addsub ATTRIBUTE_UNUSED = {
28237 +  32, 32, 0xffee071f, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } }
28238 +};
28239 +
28240 +static const CGEN_IFMT ifmt_dsp_msub_4_s1_indirect_with_post_increment_4_dsp_imm_bit5_addsub ATTRIBUTE_UNUSED = {
28241 +  32, 32, 0xffee0710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } }
28242 +};
28243 +
28244 +static const CGEN_IFMT ifmt_dsp_msub_4_s1_indirect_with_pre_increment_4_dsp_imm_bit5_addsub ATTRIBUTE_UNUSED = {
28245 +  32, 32, 0xffee0710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } }
28246 +};
28247 +
28248 +static const CGEN_IFMT ifmt_dsp_msuf_s1_direct_dsp_src2_data_reg ATTRIBUTE_UNUSED = {
28249 +  32, 32, 0xffe68700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28250 +};
28251 +
28252 +static const CGEN_IFMT ifmt_dsp_msuf_s1_immediate_dsp_src2_data_reg ATTRIBUTE_UNUSED = {
28253 +  32, 32, 0xffe68700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28254 +};
28255 +
28256 +static const CGEN_IFMT ifmt_dsp_msuf_s1_indirect_with_index_2_dsp_src2_data_reg ATTRIBUTE_UNUSED = {
28257 +  32, 32, 0xffe68700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28258 +};
28259 +
28260 +static const CGEN_IFMT ifmt_dsp_msuf_s1_indirect_with_offset_2_dsp_src2_data_reg ATTRIBUTE_UNUSED = {
28261 +  32, 32, 0xffe68400, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28262 +};
28263 +
28264 +static const CGEN_IFMT ifmt_dsp_msuf_s1_indirect_2_dsp_src2_data_reg ATTRIBUTE_UNUSED = {
28265 +  32, 32, 0xffe6871f, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28266 +};
28267 +
28268 +static const CGEN_IFMT ifmt_dsp_msuf_s1_indirect_with_post_increment_2_dsp_src2_data_reg ATTRIBUTE_UNUSED = {
28269 +  32, 32, 0xffe68710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28270 +};
28271 +
28272 +static const CGEN_IFMT ifmt_dsp_msuf_s1_indirect_with_pre_increment_2_dsp_src2_data_reg ATTRIBUTE_UNUSED = {
28273 +  32, 32, 0xffe68710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28274 +};
28275 +
28276 +static const CGEN_IFMT ifmt_dsp_msuf_s1_direct_dsp_src2_reg_acc_reg_mul ATTRIBUTE_UNUSED = {
28277 +  32, 32, 0xffe68700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28278 +};
28279 +
28280 +static const CGEN_IFMT ifmt_dsp_msuf_s1_immediate_dsp_src2_reg_acc_reg_mul ATTRIBUTE_UNUSED = {
28281 +  32, 32, 0xffe68700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28282 +};
28283 +
28284 +static const CGEN_IFMT ifmt_dsp_msuf_s1_indirect_with_index_2_dsp_src2_reg_acc_reg_mul ATTRIBUTE_UNUSED = {
28285 +  32, 32, 0xffe68700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28286 +};
28287 +
28288 +static const CGEN_IFMT ifmt_dsp_msuf_s1_indirect_with_offset_2_dsp_src2_reg_acc_reg_mul ATTRIBUTE_UNUSED = {
28289 +  32, 32, 0xffe68400, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28290 +};
28291 +
28292 +static const CGEN_IFMT ifmt_dsp_msuf_s1_indirect_2_dsp_src2_reg_acc_reg_mul ATTRIBUTE_UNUSED = {
28293 +  32, 32, 0xffe6871f, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28294 +};
28295 +
28296 +static const CGEN_IFMT ifmt_dsp_msuf_s1_indirect_with_post_increment_2_dsp_src2_reg_acc_reg_mul ATTRIBUTE_UNUSED = {
28297 +  32, 32, 0xffe68710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28298 +};
28299 +
28300 +static const CGEN_IFMT ifmt_dsp_msuf_s1_indirect_with_pre_increment_2_dsp_src2_reg_acc_reg_mul ATTRIBUTE_UNUSED = {
28301 +  32, 32, 0xffe68710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28302 +};
28303 +
28304 +static const CGEN_IFMT ifmt_dsp_msuf_s1_direct_dsp_imm_bit5 ATTRIBUTE_UNUSED = {
28305 +  32, 32, 0xffe60700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } }
28306 +};
28307 +
28308 +static const CGEN_IFMT ifmt_dsp_msuf_s1_immediate_dsp_imm_bit5 ATTRIBUTE_UNUSED = {
28309 +  32, 32, 0xffe60700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } }
28310 +};
28311 +
28312 +static const CGEN_IFMT ifmt_dsp_msuf_s1_indirect_with_index_2_dsp_imm_bit5 ATTRIBUTE_UNUSED = {
28313 +  32, 32, 0xffe60700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } }
28314 +};
28315 +
28316 +static const CGEN_IFMT ifmt_dsp_msuf_s1_indirect_with_offset_2_dsp_imm_bit5 ATTRIBUTE_UNUSED = {
28317 +  32, 32, 0xffe60400, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } }
28318 +};
28319 +
28320 +static const CGEN_IFMT ifmt_dsp_msuf_s1_indirect_2_dsp_imm_bit5 ATTRIBUTE_UNUSED = {
28321 +  32, 32, 0xffe6071f, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } }
28322 +};
28323 +
28324 +static const CGEN_IFMT ifmt_dsp_msuf_s1_indirect_with_post_increment_2_dsp_imm_bit5 ATTRIBUTE_UNUSED = {
28325 +  32, 32, 0xffe60710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } }
28326 +};
28327 +
28328 +static const CGEN_IFMT ifmt_dsp_msuf_s1_indirect_with_pre_increment_2_dsp_imm_bit5 ATTRIBUTE_UNUSED = {
28329 +  32, 32, 0xffe60710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } }
28330 +};
28331 +
28332 +static const CGEN_IFMT ifmt_dsp_mulu_4_s1_direct_dsp_src2_data_reg ATTRIBUTE_UNUSED = {
28333 +  32, 32, 0xfffe8700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28334 +};
28335 +
28336 +static const CGEN_IFMT ifmt_dsp_mulu_4_s1_immediate_dsp_src2_data_reg ATTRIBUTE_UNUSED = {
28337 +  32, 32, 0xfffe8700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28338 +};
28339 +
28340 +static const CGEN_IFMT ifmt_dsp_mulu_4_s1_indirect_with_index_4_dsp_src2_data_reg ATTRIBUTE_UNUSED = {
28341 +  32, 32, 0xfffe8700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28342 +};
28343 +
28344 +static const CGEN_IFMT ifmt_dsp_mulu_4_s1_indirect_with_offset_4_dsp_src2_data_reg ATTRIBUTE_UNUSED = {
28345 +  32, 32, 0xfffe8400, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28346 +};
28347 +
28348 +static const CGEN_IFMT ifmt_dsp_mulu_4_s1_indirect_4_dsp_src2_data_reg ATTRIBUTE_UNUSED = {
28349 +  32, 32, 0xfffe871f, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28350 +};
28351 +
28352 +static const CGEN_IFMT ifmt_dsp_mulu_4_s1_indirect_with_post_increment_4_dsp_src2_data_reg ATTRIBUTE_UNUSED = {
28353 +  32, 32, 0xfffe8710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28354 +};
28355 +
28356 +static const CGEN_IFMT ifmt_dsp_mulu_4_s1_indirect_with_pre_increment_4_dsp_src2_data_reg ATTRIBUTE_UNUSED = {
28357 +  32, 32, 0xfffe8710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28358 +};
28359 +
28360 +static const CGEN_IFMT ifmt_dsp_mulu_4_s1_direct_dsp_src2_reg_acc_reg_mul ATTRIBUTE_UNUSED = {
28361 +  32, 32, 0xfffe8700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28362 +};
28363 +
28364 +static const CGEN_IFMT ifmt_dsp_mulu_4_s1_immediate_dsp_src2_reg_acc_reg_mul ATTRIBUTE_UNUSED = {
28365 +  32, 32, 0xfffe8700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28366 +};
28367 +
28368 +static const CGEN_IFMT ifmt_dsp_mulu_4_s1_indirect_with_index_4_dsp_src2_reg_acc_reg_mul ATTRIBUTE_UNUSED = {
28369 +  32, 32, 0xfffe8700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28370 +};
28371 +
28372 +static const CGEN_IFMT ifmt_dsp_mulu_4_s1_indirect_with_offset_4_dsp_src2_reg_acc_reg_mul ATTRIBUTE_UNUSED = {
28373 +  32, 32, 0xfffe8400, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28374 +};
28375 +
28376 +static const CGEN_IFMT ifmt_dsp_mulu_4_s1_indirect_4_dsp_src2_reg_acc_reg_mul ATTRIBUTE_UNUSED = {
28377 +  32, 32, 0xfffe871f, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28378 +};
28379 +
28380 +static const CGEN_IFMT ifmt_dsp_mulu_4_s1_indirect_with_post_increment_4_dsp_src2_reg_acc_reg_mul ATTRIBUTE_UNUSED = {
28381 +  32, 32, 0xfffe8710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28382 +};
28383 +
28384 +static const CGEN_IFMT ifmt_dsp_mulu_4_s1_indirect_with_pre_increment_4_dsp_src2_reg_acc_reg_mul ATTRIBUTE_UNUSED = {
28385 +  32, 32, 0xfffe8710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28386 +};
28387 +
28388 +static const CGEN_IFMT ifmt_dsp_mulu_4_s1_direct_dsp_imm_bit5 ATTRIBUTE_UNUSED = {
28389 +  32, 32, 0xfffe0700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } }
28390 +};
28391 +
28392 +static const CGEN_IFMT ifmt_dsp_mulu_4_s1_immediate_dsp_imm_bit5 ATTRIBUTE_UNUSED = {
28393 +  32, 32, 0xfffe0700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } }
28394 +};
28395 +
28396 +static const CGEN_IFMT ifmt_dsp_mulu_4_s1_indirect_with_index_4_dsp_imm_bit5 ATTRIBUTE_UNUSED = {
28397 +  32, 32, 0xfffe0700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } }
28398 +};
28399 +
28400 +static const CGEN_IFMT ifmt_dsp_mulu_4_s1_indirect_with_offset_4_dsp_imm_bit5 ATTRIBUTE_UNUSED = {
28401 +  32, 32, 0xfffe0400, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } }
28402 +};
28403 +
28404 +static const CGEN_IFMT ifmt_dsp_mulu_4_s1_indirect_4_dsp_imm_bit5 ATTRIBUTE_UNUSED = {
28405 +  32, 32, 0xfffe071f, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } }
28406 +};
28407 +
28408 +static const CGEN_IFMT ifmt_dsp_mulu_4_s1_indirect_with_post_increment_4_dsp_imm_bit5 ATTRIBUTE_UNUSED = {
28409 +  32, 32, 0xfffe0710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } }
28410 +};
28411 +
28412 +static const CGEN_IFMT ifmt_dsp_mulu_4_s1_indirect_with_pre_increment_4_dsp_imm_bit5 ATTRIBUTE_UNUSED = {
28413 +  32, 32, 0xfffe0710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } }
28414 +};
28415 +
28416 +static const CGEN_IFMT ifmt_dsp_mulu_s1_direct_dsp_src2_data_reg ATTRIBUTE_UNUSED = {
28417 +  32, 32, 0xfff68700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28418 +};
28419 +
28420 +static const CGEN_IFMT ifmt_dsp_mulu_s1_immediate_dsp_src2_data_reg ATTRIBUTE_UNUSED = {
28421 +  32, 32, 0xfff68700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28422 +};
28423 +
28424 +static const CGEN_IFMT ifmt_dsp_mulu_s1_indirect_with_index_2_dsp_src2_data_reg ATTRIBUTE_UNUSED = {
28425 +  32, 32, 0xfff68700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28426 +};
28427 +
28428 +static const CGEN_IFMT ifmt_dsp_mulu_s1_indirect_with_offset_2_dsp_src2_data_reg ATTRIBUTE_UNUSED = {
28429 +  32, 32, 0xfff68400, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28430 +};
28431 +
28432 +static const CGEN_IFMT ifmt_dsp_mulu_s1_indirect_2_dsp_src2_data_reg ATTRIBUTE_UNUSED = {
28433 +  32, 32, 0xfff6871f, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28434 +};
28435 +
28436 +static const CGEN_IFMT ifmt_dsp_mulu_s1_indirect_with_post_increment_2_dsp_src2_data_reg ATTRIBUTE_UNUSED = {
28437 +  32, 32, 0xfff68710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28438 +};
28439 +
28440 +static const CGEN_IFMT ifmt_dsp_mulu_s1_indirect_with_pre_increment_2_dsp_src2_data_reg ATTRIBUTE_UNUSED = {
28441 +  32, 32, 0xfff68710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28442 +};
28443 +
28444 +static const CGEN_IFMT ifmt_dsp_mulu_s1_direct_dsp_src2_reg_acc_reg_mul ATTRIBUTE_UNUSED = {
28445 +  32, 32, 0xfff68700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28446 +};
28447 +
28448 +static const CGEN_IFMT ifmt_dsp_mulu_s1_immediate_dsp_src2_reg_acc_reg_mul ATTRIBUTE_UNUSED = {
28449 +  32, 32, 0xfff68700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28450 +};
28451 +
28452 +static const CGEN_IFMT ifmt_dsp_mulu_s1_indirect_with_index_2_dsp_src2_reg_acc_reg_mul ATTRIBUTE_UNUSED = {
28453 +  32, 32, 0xfff68700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28454 +};
28455 +
28456 +static const CGEN_IFMT ifmt_dsp_mulu_s1_indirect_with_offset_2_dsp_src2_reg_acc_reg_mul ATTRIBUTE_UNUSED = {
28457 +  32, 32, 0xfff68400, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28458 +};
28459 +
28460 +static const CGEN_IFMT ifmt_dsp_mulu_s1_indirect_2_dsp_src2_reg_acc_reg_mul ATTRIBUTE_UNUSED = {
28461 +  32, 32, 0xfff6871f, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28462 +};
28463 +
28464 +static const CGEN_IFMT ifmt_dsp_mulu_s1_indirect_with_post_increment_2_dsp_src2_reg_acc_reg_mul ATTRIBUTE_UNUSED = {
28465 +  32, 32, 0xfff68710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28466 +};
28467 +
28468 +static const CGEN_IFMT ifmt_dsp_mulu_s1_indirect_with_pre_increment_2_dsp_src2_reg_acc_reg_mul ATTRIBUTE_UNUSED = {
28469 +  32, 32, 0xfff68710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
28470 +};
28471 +
28472 +static const CGEN_IFMT ifmt_dsp_mulu_s1_direct_dsp_imm_bit5 ATTRIBUTE_UNUSED = {
28473 +  32, 32, 0xfff60700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } }
28474 +};
28475 +
28476 +static const CGEN_IFMT ifmt_dsp_mulu_s1_immediate_dsp_imm_bit5 ATTRIBUTE_UNUSED = {
28477 +  32, 32, 0xfff60700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } }
28478 +};
28479 +
28480 +static const CGEN_IFMT ifmt_dsp_mulu_s1_indirect_with_index_2_dsp_imm_bit5 ATTRIBUTE_UNUSED = {
28481 +  32, 32, 0xfff60700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } }
28482 +};
28483 +
28484 +static const CGEN_IFMT ifmt_dsp_mulu_s1_indirect_with_offset_2_dsp_imm_bit5 ATTRIBUTE_UNUSED = {
28485 +  32, 32, 0xfff60400, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } }
28486 +};
28487 +
28488 +static const CGEN_IFMT ifmt_dsp_mulu_s1_indirect_2_dsp_imm_bit5 ATTRIBUTE_UNUSED = {
28489 +  32, 32, 0xfff6071f, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } }
28490 +};
28491 +
28492 +static const CGEN_IFMT ifmt_dsp_mulu_s1_indirect_with_post_increment_2_dsp_imm_bit5 ATTRIBUTE_UNUSED = {
28493 +  32, 32, 0xfff60710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } }
28494 +};
28495 +
28496 +static const CGEN_IFMT ifmt_dsp_mulu_s1_indirect_with_pre_increment_2_dsp_imm_bit5 ATTRIBUTE_UNUSED = {
28497 +  32, 32, 0xfff60710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } }
28498 +};
28499 +
28500 +static const CGEN_IFMT ifmt_ierase_d_pea_indirect_with_index ATTRIBUTE_UNUSED = {
28501 +  32, 32, 0xff00ffff, { { F (F_OP1) }, { F (F_OP2) }, { F (F_S1) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { 0 } }
28502 +};
28503 +
28504 +static const CGEN_IFMT ifmt_ierase_d_pea_indirect_with_offset ATTRIBUTE_UNUSED = {
28505 +  32, 32, 0xfc00ffff, { { F (F_OP1) }, { F (F_OP2) }, { F (F_S1) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { 0 } }
28506 +};
28507 +
28508 +static const CGEN_IFMT ifmt_ierase_d_pea_indirect ATTRIBUTE_UNUSED = {
28509 +  32, 32, 0xff1fffff, { { F (F_OP1) }, { F (F_OP2) }, { F (F_S1) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { 0 } }
28510 +};
28511 +
28512 +static const CGEN_IFMT ifmt_ierase_d_pea_indirect_with_post_increment ATTRIBUTE_UNUSED = {
28513 +  32, 32, 0xff10ffff, { { F (F_OP1) }, { F (F_OP2) }, { F (F_S1) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { 0 } }
28514 +};
28515 +
28516 +static const CGEN_IFMT ifmt_ierase_d_pea_indirect_with_pre_increment ATTRIBUTE_UNUSED = {
28517 +  32, 32, 0xff10ffff, { { F (F_OP1) }, { F (F_OP2) }, { F (F_S1) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { 0 } }
28518 +};
28519 +
28520 +static const CGEN_IFMT ifmt_iread_s1_ea_indirect ATTRIBUTE_UNUSED = {
28521 +  32, 32, 0xffffff1f, { { F (F_OP1) }, { F (F_D) }, { F (F_OP2) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
28522 +};
28523 +
28524 +static const CGEN_IFMT ifmt_iread_s1_ea_indirect_with_index_4 ATTRIBUTE_UNUSED = {
28525 +  32, 32, 0xffffff00, { { F (F_OP1) }, { F (F_D) }, { F (F_OP2) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
28526 +};
28527 +
28528 +static const CGEN_IFMT ifmt_iread_s1_ea_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = {
28529 +  32, 32, 0xffffff10, { { F (F_OP1) }, { F (F_D) }, { F (F_OP2) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
28530 +};
28531 +
28532 +static const CGEN_IFMT ifmt_iread_s1_ea_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = {
28533 +  32, 32, 0xffffff10, { { F (F_OP1) }, { F (F_D) }, { F (F_OP2) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
28534 +};
28535 +
28536 +static const CGEN_IFMT ifmt_iread_s1_ea_indirect_with_offset_4 ATTRIBUTE_UNUSED = {
28537 +  32, 32, 0xfffffc00, { { F (F_OP1) }, { F (F_D) }, { F (F_OP2) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
28538 +};
28539 +
28540 +static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_with_index_s1_direct ATTRIBUTE_UNUSED = {
28541 +  32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } }
28542 +};
28543 +
28544 +static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_with_offset_s1_direct ATTRIBUTE_UNUSED = {
28545 +  32, 32, 0xfc00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } }
28546 +};
28547 +
28548 +static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_s1_direct ATTRIBUTE_UNUSED = {
28549 +  32, 32, 0xff1fff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } }
28550 +};
28551 +
28552 +static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_with_post_increment_s1_direct ATTRIBUTE_UNUSED = {
28553 +  32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } }
28554 +};
28555 +
28556 +static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_with_pre_increment_s1_direct ATTRIBUTE_UNUSED = {
28557 +  32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } }
28558 +};
28559 +
28560 +static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_with_index_s1_immediate ATTRIBUTE_UNUSED = {
28561 +  32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } }
28562 +};
28563 +
28564 +static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_with_offset_s1_immediate ATTRIBUTE_UNUSED = {
28565 +  32, 32, 0xfc00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } }
28566 +};
28567 +
28568 +static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_s1_immediate ATTRIBUTE_UNUSED = {
28569 +  32, 32, 0xff1fff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } }
28570 +};
28571 +
28572 +static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_with_post_increment_s1_immediate ATTRIBUTE_UNUSED = {
28573 +  32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } }
28574 +};
28575 +
28576 +static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_with_pre_increment_s1_immediate ATTRIBUTE_UNUSED = {
28577 +  32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } }
28578 +};
28579 +
28580 +static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_with_index_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = {
28581 +  32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
28582 +};
28583 +
28584 +static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_with_offset_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = {
28585 +  32, 32, 0xfc00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
28586 +};
28587 +
28588 +static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = {
28589 +  32, 32, 0xff1fff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
28590 +};
28591 +
28592 +static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_with_post_increment_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = {
28593 +  32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
28594 +};
28595 +
28596 +static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_with_pre_increment_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = {
28597 +  32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
28598 +};
28599 +
28600 +static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_with_index_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = {
28601 +  32, 32, 0xff00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
28602 +};
28603 +
28604 +static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_with_offset_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = {
28605 +  32, 32, 0xfc00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
28606 +};
28607 +
28608 +static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = {
28609 +  32, 32, 0xff1ffc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
28610 +};
28611 +
28612 +static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_with_post_increment_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = {
28613 +  32, 32, 0xff10fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
28614 +};
28615 +
28616 +static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_with_pre_increment_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = {
28617 +  32, 32, 0xff10fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
28618 +};
28619 +
28620 +static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_with_index_s1_indirect_4 ATTRIBUTE_UNUSED = {
28621 +  32, 32, 0xff00ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
28622 +};
28623 +
28624 +static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_with_offset_s1_indirect_4 ATTRIBUTE_UNUSED = {
28625 +  32, 32, 0xfc00ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
28626 +};
28627 +
28628 +static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_s1_indirect_4 ATTRIBUTE_UNUSED = {
28629 +  32, 32, 0xff1fff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
28630 +};
28631 +
28632 +static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_with_post_increment_s1_indirect_4 ATTRIBUTE_UNUSED = {
28633 +  32, 32, 0xff10ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
28634 +};
28635 +
28636 +static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_with_pre_increment_s1_indirect_4 ATTRIBUTE_UNUSED = {
28637 +  32, 32, 0xff10ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
28638 +};
28639 +
28640 +static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_with_index_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = {
28641 +  32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
28642 +};
28643 +
28644 +static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_with_offset_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = {
28645 +  32, 32, 0xfc00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
28646 +};
28647 +
28648 +static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = {
28649 +  32, 32, 0xff1fff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
28650 +};
28651 +
28652 +static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_with_post_increment_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = {
28653 +  32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
28654 +};
28655 +
28656 +static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_with_pre_increment_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = {
28657 +  32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
28658 +};
28659 +
28660 +static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_with_index_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = {
28661 +  32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
28662 +};
28663 +
28664 +static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_with_offset_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = {
28665 +  32, 32, 0xfc00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
28666 +};
28667 +
28668 +static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = {
28669 +  32, 32, 0xff1fff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
28670 +};
28671 +
28672 +static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_with_post_increment_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = {
28673 +  32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
28674 +};
28675 +
28676 +static const CGEN_IFMT ifmt_iwrite_d_pea_indirect_with_pre_increment_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = {
28677 +  32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
28678 +};
28679 +
28680 +static const CGEN_IFMT ifmt_setcsr_s1_direct ATTRIBUTE_UNUSED = {
28681 +  32, 32, 0xffffff00, { { F (F_OP1) }, { F (F_D) }, { F (F_OP2) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } }
28682 +};
28683 +
28684 +static const CGEN_IFMT ifmt_setcsr_s1_immediate ATTRIBUTE_UNUSED = {
28685 +  32, 32, 0xffffff00, { { F (F_OP1) }, { F (F_D) }, { F (F_OP2) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } }
28686 +};
28687 +
28688 +static const CGEN_IFMT ifmt_setcsr_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = {
28689 +  32, 32, 0xffffff00, { { F (F_OP1) }, { F (F_D) }, { F (F_OP2) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
28690 +};
28691 +
28692 +static const CGEN_IFMT ifmt_setcsr_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = {
28693 +  32, 32, 0xfffffc00, { { F (F_OP1) }, { F (F_D) }, { F (F_OP2) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
28694 +};
28695 +
28696 +static const CGEN_IFMT ifmt_setcsr_s1_indirect_4 ATTRIBUTE_UNUSED = {
28697 +  32, 32, 0xffffff1f, { { F (F_OP1) }, { F (F_D) }, { F (F_OP2) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
28698 +};
28699 +
28700 +static const CGEN_IFMT ifmt_setcsr_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = {
28701 +  32, 32, 0xffffff10, { { F (F_OP1) }, { F (F_D) }, { F (F_OP2) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
28702 +};
28703 +
28704 +static const CGEN_IFMT ifmt_setcsr_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = {
28705 +  32, 32, 0xffffff10, { { F (F_OP1) }, { F (F_D) }, { F (F_OP2) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
28706 +};
28707 +
28708 +static const CGEN_IFMT ifmt_movea_d_direct_s1_direct ATTRIBUTE_UNUSED = {
28709 +  32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } }
28710 +};
28711 +
28712 +static const CGEN_IFMT ifmt_movea_d_immediate_4_s1_direct ATTRIBUTE_UNUSED = {
28713 +  32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } }
28714 +};
28715 +
28716 +static const CGEN_IFMT ifmt_movea_d_indirect_with_index_4_s1_direct ATTRIBUTE_UNUSED = {
28717 +  32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } }
28718 +};
28719 +
28720 +static const CGEN_IFMT ifmt_movea_d_indirect_with_offset_4_s1_direct ATTRIBUTE_UNUSED = {
28721 +  32, 32, 0xfc00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } }
28722 +};
28723 +
28724 +static const CGEN_IFMT ifmt_movea_d_indirect_4_s1_direct ATTRIBUTE_UNUSED = {
28725 +  32, 32, 0xff1fff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } }
28726 +};
28727 +
28728 +static const CGEN_IFMT ifmt_movea_d_indirect_with_post_increment_4_s1_direct ATTRIBUTE_UNUSED = {
28729 +  32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } }
28730 +};
28731 +
28732 +static const CGEN_IFMT ifmt_movea_d_indirect_with_pre_increment_4_s1_direct ATTRIBUTE_UNUSED = {
28733 +  32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } }
28734 +};
28735 +
28736 +static const CGEN_IFMT ifmt_movea_d_direct_s1_immediate ATTRIBUTE_UNUSED = {
28737 +  32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } }
28738 +};
28739 +
28740 +static const CGEN_IFMT ifmt_movea_d_immediate_4_s1_immediate ATTRIBUTE_UNUSED = {
28741 +  32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } }
28742 +};
28743 +
28744 +static const CGEN_IFMT ifmt_movea_d_indirect_with_index_4_s1_immediate ATTRIBUTE_UNUSED = {
28745 +  32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } }
28746 +};
28747 +
28748 +static const CGEN_IFMT ifmt_movea_d_indirect_with_offset_4_s1_immediate ATTRIBUTE_UNUSED = {
28749 +  32, 32, 0xfc00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } }
28750 +};
28751 +
28752 +static const CGEN_IFMT ifmt_movea_d_indirect_4_s1_immediate ATTRIBUTE_UNUSED = {
28753 +  32, 32, 0xff1fff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } }
28754 +};
28755 +
28756 +static const CGEN_IFMT ifmt_movea_d_indirect_with_post_increment_4_s1_immediate ATTRIBUTE_UNUSED = {
28757 +  32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } }
28758 +};
28759 +
28760 +static const CGEN_IFMT ifmt_movea_d_indirect_with_pre_increment_4_s1_immediate ATTRIBUTE_UNUSED = {
28761 +  32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } }
28762 +};
28763 +
28764 +static const CGEN_IFMT ifmt_movea_d_direct_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = {
28765 +  32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
28766 +};
28767 +
28768 +static const CGEN_IFMT ifmt_movea_d_immediate_4_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = {
28769 +  32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
28770 +};
28771 +
28772 +static const CGEN_IFMT ifmt_movea_d_indirect_with_index_4_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = {
28773 +  32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
28774 +};
28775 +
28776 +static const CGEN_IFMT ifmt_movea_d_indirect_with_offset_4_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = {
28777 +  32, 32, 0xfc00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
28778 +};
28779 +
28780 +static const CGEN_IFMT ifmt_movea_d_indirect_4_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = {
28781 +  32, 32, 0xff1fff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
28782 +};
28783 +
28784 +static const CGEN_IFMT ifmt_movea_d_indirect_with_post_increment_4_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = {
28785 +  32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
28786 +};
28787 +
28788 +static const CGEN_IFMT ifmt_movea_d_indirect_with_pre_increment_4_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = {
28789 +  32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
28790 +};
28791 +
28792 +static const CGEN_IFMT ifmt_movea_d_direct_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = {
28793 +  32, 32, 0xff00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
28794 +};
28795 +
28796 +static const CGEN_IFMT ifmt_movea_d_immediate_4_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = {
28797 +  32, 32, 0xff00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
28798 +};
28799 +
28800 +static const CGEN_IFMT ifmt_movea_d_indirect_with_index_4_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = {
28801 +  32, 32, 0xff00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
28802 +};
28803 +
28804 +static const CGEN_IFMT ifmt_movea_d_indirect_with_offset_4_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = {
28805 +  32, 32, 0xfc00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
28806 +};
28807 +
28808 +static const CGEN_IFMT ifmt_movea_d_indirect_4_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = {
28809 +  32, 32, 0xff1ffc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
28810 +};
28811 +
28812 +static const CGEN_IFMT ifmt_movea_d_indirect_with_post_increment_4_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = {
28813 +  32, 32, 0xff10fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
28814 +};
28815 +
28816 +static const CGEN_IFMT ifmt_movea_d_indirect_with_pre_increment_4_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = {
28817 +  32, 32, 0xff10fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
28818 +};
28819 +
28820 +static const CGEN_IFMT ifmt_movea_d_direct_s1_indirect_4 ATTRIBUTE_UNUSED = {
28821 +  32, 32, 0xff00ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
28822 +};
28823 +
28824 +static const CGEN_IFMT ifmt_movea_d_immediate_4_s1_indirect_4 ATTRIBUTE_UNUSED = {
28825 +  32, 32, 0xff00ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
28826 +};
28827 +
28828 +static const CGEN_IFMT ifmt_movea_d_indirect_with_index_4_s1_indirect_4 ATTRIBUTE_UNUSED = {
28829 +  32, 32, 0xff00ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
28830 +};
28831 +
28832 +static const CGEN_IFMT ifmt_movea_d_indirect_with_offset_4_s1_indirect_4 ATTRIBUTE_UNUSED = {
28833 +  32, 32, 0xfc00ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
28834 +};
28835 +
28836 +static const CGEN_IFMT ifmt_movea_d_indirect_4_s1_indirect_4 ATTRIBUTE_UNUSED = {
28837 +  32, 32, 0xff1fff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
28838 +};
28839 +
28840 +static const CGEN_IFMT ifmt_movea_d_indirect_with_post_increment_4_s1_indirect_4 ATTRIBUTE_UNUSED = {
28841 +  32, 32, 0xff10ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
28842 +};
28843 +
28844 +static const CGEN_IFMT ifmt_movea_d_indirect_with_pre_increment_4_s1_indirect_4 ATTRIBUTE_UNUSED = {
28845 +  32, 32, 0xff10ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
28846 +};
28847 +
28848 +static const CGEN_IFMT ifmt_movea_d_direct_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = {
28849 +  32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
28850 +};
28851 +
28852 +static const CGEN_IFMT ifmt_movea_d_immediate_4_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = {
28853 +  32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
28854 +};
28855 +
28856 +static const CGEN_IFMT ifmt_movea_d_indirect_with_index_4_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = {
28857 +  32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
28858 +};
28859 +
28860 +static const CGEN_IFMT ifmt_movea_d_indirect_with_offset_4_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = {
28861 +  32, 32, 0xfc00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
28862 +};
28863 +
28864 +static const CGEN_IFMT ifmt_movea_d_indirect_4_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = {
28865 +  32, 32, 0xff1fff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
28866 +};
28867 +
28868 +static const CGEN_IFMT ifmt_movea_d_indirect_with_post_increment_4_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = {
28869 +  32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
28870 +};
28871 +
28872 +static const CGEN_IFMT ifmt_movea_d_indirect_with_pre_increment_4_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = {
28873 +  32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
28874 +};
28875 +
28876 +static const CGEN_IFMT ifmt_movea_d_direct_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = {
28877 +  32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
28878 +};
28879 +
28880 +static const CGEN_IFMT ifmt_movea_d_immediate_4_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = {
28881 +  32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
28882 +};
28883 +
28884 +static const CGEN_IFMT ifmt_movea_d_indirect_with_index_4_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = {
28885 +  32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
28886 +};
28887 +
28888 +static const CGEN_IFMT ifmt_movea_d_indirect_with_offset_4_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = {
28889 +  32, 32, 0xfc00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
28890 +};
28891 +
28892 +static const CGEN_IFMT ifmt_movea_d_indirect_4_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = {
28893 +  32, 32, 0xff1fff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
28894 +};
28895 +
28896 +static const CGEN_IFMT ifmt_movea_d_indirect_with_post_increment_4_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = {
28897 +  32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
28898 +};
28899 +
28900 +static const CGEN_IFMT ifmt_movea_d_indirect_with_pre_increment_4_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = {
28901 +  32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
28902 +};
28903 +
28904 +static const CGEN_IFMT ifmt_move_2_d_immediate_2_s1_direct ATTRIBUTE_UNUSED = {
28905 +  32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } }
28906 +};
28907 +
28908 +static const CGEN_IFMT ifmt_move_2_d_indirect_with_index_2_s1_direct ATTRIBUTE_UNUSED = {
28909 +  32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } }
28910 +};
28911 +
28912 +static const CGEN_IFMT ifmt_move_2_d_indirect_with_offset_2_s1_direct ATTRIBUTE_UNUSED = {
28913 +  32, 32, 0xfc00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } }
28914 +};
28915 +
28916 +static const CGEN_IFMT ifmt_move_2_d_indirect_2_s1_direct ATTRIBUTE_UNUSED = {
28917 +  32, 32, 0xff1fff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } }
28918 +};
28919 +
28920 +static const CGEN_IFMT ifmt_move_2_d_indirect_with_post_increment_2_s1_direct ATTRIBUTE_UNUSED = {
28921 +  32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } }
28922 +};
28923 +
28924 +static const CGEN_IFMT ifmt_move_2_d_indirect_with_pre_increment_2_s1_direct ATTRIBUTE_UNUSED = {
28925 +  32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } }
28926 +};
28927 +
28928 +static const CGEN_IFMT ifmt_move_2_d_immediate_2_s1_immediate ATTRIBUTE_UNUSED = {
28929 +  32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } }
28930 +};
28931 +
28932 +static const CGEN_IFMT ifmt_move_2_d_indirect_with_index_2_s1_immediate ATTRIBUTE_UNUSED = {
28933 +  32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } }
28934 +};
28935 +
28936 +static const CGEN_IFMT ifmt_move_2_d_indirect_with_offset_2_s1_immediate ATTRIBUTE_UNUSED = {
28937 +  32, 32, 0xfc00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } }
28938 +};
28939 +
28940 +static const CGEN_IFMT ifmt_move_2_d_indirect_2_s1_immediate ATTRIBUTE_UNUSED = {
28941 +  32, 32, 0xff1fff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } }
28942 +};
28943 +
28944 +static const CGEN_IFMT ifmt_move_2_d_indirect_with_post_increment_2_s1_immediate ATTRIBUTE_UNUSED = {
28945 +  32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } }
28946 +};
28947 +
28948 +static const CGEN_IFMT ifmt_move_2_d_indirect_with_pre_increment_2_s1_immediate ATTRIBUTE_UNUSED = {
28949 +  32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } }
28950 +};
28951 +
28952 +static const CGEN_IFMT ifmt_move_2_d_direct_s1_indirect_with_index_2 ATTRIBUTE_UNUSED = {
28953 +  32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
28954 +};
28955 +
28956 +static const CGEN_IFMT ifmt_move_2_d_immediate_2_s1_indirect_with_index_2 ATTRIBUTE_UNUSED = {
28957 +  32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
28958 +};
28959 +
28960 +static const CGEN_IFMT ifmt_move_2_d_indirect_with_index_2_s1_indirect_with_index_2 ATTRIBUTE_UNUSED = {
28961 +  32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
28962 +};
28963 +
28964 +static const CGEN_IFMT ifmt_move_2_d_indirect_with_offset_2_s1_indirect_with_index_2 ATTRIBUTE_UNUSED = {
28965 +  32, 32, 0xfc00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
28966 +};
28967 +
28968 +static const CGEN_IFMT ifmt_move_2_d_indirect_2_s1_indirect_with_index_2 ATTRIBUTE_UNUSED = {
28969 +  32, 32, 0xff1fff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
28970 +};
28971 +
28972 +static const CGEN_IFMT ifmt_move_2_d_indirect_with_post_increment_2_s1_indirect_with_index_2 ATTRIBUTE_UNUSED = {
28973 +  32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
28974 +};
28975 +
28976 +static const CGEN_IFMT ifmt_move_2_d_indirect_with_pre_increment_2_s1_indirect_with_index_2 ATTRIBUTE_UNUSED = {
28977 +  32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
28978 +};
28979 +
28980 +static const CGEN_IFMT ifmt_move_2_d_direct_s1_indirect_with_offset_2 ATTRIBUTE_UNUSED = {
28981 +  32, 32, 0xff00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } }
28982 +};
28983 +
28984 +static const CGEN_IFMT ifmt_move_2_d_immediate_2_s1_indirect_with_offset_2 ATTRIBUTE_UNUSED = {
28985 +  32, 32, 0xff00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } }
28986 +};
28987 +
28988 +static const CGEN_IFMT ifmt_move_2_d_indirect_with_index_2_s1_indirect_with_offset_2 ATTRIBUTE_UNUSED = {
28989 +  32, 32, 0xff00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } }
28990 +};
28991 +
28992 +static const CGEN_IFMT ifmt_move_2_d_indirect_with_offset_2_s1_indirect_with_offset_2 ATTRIBUTE_UNUSED = {
28993 +  32, 32, 0xfc00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } }
28994 +};
28995 +
28996 +static const CGEN_IFMT ifmt_move_2_d_indirect_2_s1_indirect_with_offset_2 ATTRIBUTE_UNUSED = {
28997 +  32, 32, 0xff1ffc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } }
28998 +};
28999 +
29000 +static const CGEN_IFMT ifmt_move_2_d_indirect_with_post_increment_2_s1_indirect_with_offset_2 ATTRIBUTE_UNUSED = {
29001 +  32, 32, 0xff10fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } }
29002 +};
29003 +
29004 +static const CGEN_IFMT ifmt_move_2_d_indirect_with_pre_increment_2_s1_indirect_with_offset_2 ATTRIBUTE_UNUSED = {
29005 +  32, 32, 0xff10fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } }
29006 +};
29007 +
29008 +static const CGEN_IFMT ifmt_move_2_d_direct_s1_indirect_2 ATTRIBUTE_UNUSED = {
29009 +  32, 32, 0xff00ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } }
29010 +};
29011 +
29012 +static const CGEN_IFMT ifmt_move_2_d_immediate_2_s1_indirect_2 ATTRIBUTE_UNUSED = {
29013 +  32, 32, 0xff00ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } }
29014 +};
29015 +
29016 +static const CGEN_IFMT ifmt_move_2_d_indirect_with_index_2_s1_indirect_2 ATTRIBUTE_UNUSED = {
29017 +  32, 32, 0xff00ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } }
29018 +};
29019 +
29020 +static const CGEN_IFMT ifmt_move_2_d_indirect_with_offset_2_s1_indirect_2 ATTRIBUTE_UNUSED = {
29021 +  32, 32, 0xfc00ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } }
29022 +};
29023 +
29024 +static const CGEN_IFMT ifmt_move_2_d_indirect_2_s1_indirect_2 ATTRIBUTE_UNUSED = {
29025 +  32, 32, 0xff1fff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } }
29026 +};
29027 +
29028 +static const CGEN_IFMT ifmt_move_2_d_indirect_with_post_increment_2_s1_indirect_2 ATTRIBUTE_UNUSED = {
29029 +  32, 32, 0xff10ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } }
29030 +};
29031 +
29032 +static const CGEN_IFMT ifmt_move_2_d_indirect_with_pre_increment_2_s1_indirect_2 ATTRIBUTE_UNUSED = {
29033 +  32, 32, 0xff10ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } }
29034 +};
29035 +
29036 +static const CGEN_IFMT ifmt_move_2_d_direct_s1_indirect_with_post_increment_2 ATTRIBUTE_UNUSED = {
29037 +  32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } }
29038 +};
29039 +
29040 +static const CGEN_IFMT ifmt_move_2_d_immediate_2_s1_indirect_with_post_increment_2 ATTRIBUTE_UNUSED = {
29041 +  32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } }
29042 +};
29043 +
29044 +static const CGEN_IFMT ifmt_move_2_d_indirect_with_index_2_s1_indirect_with_post_increment_2 ATTRIBUTE_UNUSED = {
29045 +  32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } }
29046 +};
29047 +
29048 +static const CGEN_IFMT ifmt_move_2_d_indirect_with_offset_2_s1_indirect_with_post_increment_2 ATTRIBUTE_UNUSED = {
29049 +  32, 32, 0xfc00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } }
29050 +};
29051 +
29052 +static const CGEN_IFMT ifmt_move_2_d_indirect_2_s1_indirect_with_post_increment_2 ATTRIBUTE_UNUSED = {
29053 +  32, 32, 0xff1fff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } }
29054 +};
29055 +
29056 +static const CGEN_IFMT ifmt_move_2_d_indirect_with_post_increment_2_s1_indirect_with_post_increment_2 ATTRIBUTE_UNUSED = {
29057 +  32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } }
29058 +};
29059 +
29060 +static const CGEN_IFMT ifmt_move_2_d_indirect_with_pre_increment_2_s1_indirect_with_post_increment_2 ATTRIBUTE_UNUSED = {
29061 +  32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } }
29062 +};
29063 +
29064 +static const CGEN_IFMT ifmt_move_2_d_direct_s1_indirect_with_pre_increment_2 ATTRIBUTE_UNUSED = {
29065 +  32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } }
29066 +};
29067 +
29068 +static const CGEN_IFMT ifmt_move_2_d_immediate_2_s1_indirect_with_pre_increment_2 ATTRIBUTE_UNUSED = {
29069 +  32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } }
29070 +};
29071 +
29072 +static const CGEN_IFMT ifmt_move_2_d_indirect_with_index_2_s1_indirect_with_pre_increment_2 ATTRIBUTE_UNUSED = {
29073 +  32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } }
29074 +};
29075 +
29076 +static const CGEN_IFMT ifmt_move_2_d_indirect_with_offset_2_s1_indirect_with_pre_increment_2 ATTRIBUTE_UNUSED = {
29077 +  32, 32, 0xfc00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } }
29078 +};
29079 +
29080 +static const CGEN_IFMT ifmt_move_2_d_indirect_2_s1_indirect_with_pre_increment_2 ATTRIBUTE_UNUSED = {
29081 +  32, 32, 0xff1fff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } }
29082 +};
29083 +
29084 +static const CGEN_IFMT ifmt_move_2_d_indirect_with_post_increment_2_s1_indirect_with_pre_increment_2 ATTRIBUTE_UNUSED = {
29085 +  32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } }
29086 +};
29087 +
29088 +static const CGEN_IFMT ifmt_move_2_d_indirect_with_pre_increment_2_s1_indirect_with_pre_increment_2 ATTRIBUTE_UNUSED = {
29089 +  32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } }
29090 +};
29091 +
29092 +static const CGEN_IFMT ifmt_move_1_d_immediate_1_s1_direct ATTRIBUTE_UNUSED = {
29093 +  32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } }
29094 +};
29095 +
29096 +static const CGEN_IFMT ifmt_move_1_d_indirect_with_index_1_s1_direct ATTRIBUTE_UNUSED = {
29097 +  32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } }
29098 +};
29099 +
29100 +static const CGEN_IFMT ifmt_move_1_d_indirect_with_offset_1_s1_direct ATTRIBUTE_UNUSED = {
29101 +  32, 32, 0xfc00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } }
29102 +};
29103 +
29104 +static const CGEN_IFMT ifmt_move_1_d_indirect_1_s1_direct ATTRIBUTE_UNUSED = {
29105 +  32, 32, 0xff1fff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } }
29106 +};
29107 +
29108 +static const CGEN_IFMT ifmt_move_1_d_indirect_with_post_increment_1_s1_direct ATTRIBUTE_UNUSED = {
29109 +  32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } }
29110 +};
29111 +
29112 +static const CGEN_IFMT ifmt_move_1_d_indirect_with_pre_increment_1_s1_direct ATTRIBUTE_UNUSED = {
29113 +  32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } }
29114 +};
29115 +
29116 +static const CGEN_IFMT ifmt_move_1_d_immediate_1_s1_immediate ATTRIBUTE_UNUSED = {
29117 +  32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } }
29118 +};
29119 +
29120 +static const CGEN_IFMT ifmt_move_1_d_indirect_with_index_1_s1_immediate ATTRIBUTE_UNUSED = {
29121 +  32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } }
29122 +};
29123 +
29124 +static const CGEN_IFMT ifmt_move_1_d_indirect_with_offset_1_s1_immediate ATTRIBUTE_UNUSED = {
29125 +  32, 32, 0xfc00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } }
29126 +};
29127 +
29128 +static const CGEN_IFMT ifmt_move_1_d_indirect_1_s1_immediate ATTRIBUTE_UNUSED = {
29129 +  32, 32, 0xff1fff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } }
29130 +};
29131 +
29132 +static const CGEN_IFMT ifmt_move_1_d_indirect_with_post_increment_1_s1_immediate ATTRIBUTE_UNUSED = {
29133 +  32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } }
29134 +};
29135 +
29136 +static const CGEN_IFMT ifmt_move_1_d_indirect_with_pre_increment_1_s1_immediate ATTRIBUTE_UNUSED = {
29137 +  32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } }
29138 +};
29139 +
29140 +static const CGEN_IFMT ifmt_move_1_d_direct_s1_indirect_with_index_1 ATTRIBUTE_UNUSED = {
29141 +  32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
29142 +};
29143 +
29144 +static const CGEN_IFMT ifmt_move_1_d_immediate_1_s1_indirect_with_index_1 ATTRIBUTE_UNUSED = {
29145 +  32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
29146 +};
29147 +
29148 +static const CGEN_IFMT ifmt_move_1_d_indirect_with_index_1_s1_indirect_with_index_1 ATTRIBUTE_UNUSED = {
29149 +  32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
29150 +};
29151 +
29152 +static const CGEN_IFMT ifmt_move_1_d_indirect_with_offset_1_s1_indirect_with_index_1 ATTRIBUTE_UNUSED = {
29153 +  32, 32, 0xfc00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
29154 +};
29155 +
29156 +static const CGEN_IFMT ifmt_move_1_d_indirect_1_s1_indirect_with_index_1 ATTRIBUTE_UNUSED = {
29157 +  32, 32, 0xff1fff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
29158 +};
29159 +
29160 +static const CGEN_IFMT ifmt_move_1_d_indirect_with_post_increment_1_s1_indirect_with_index_1 ATTRIBUTE_UNUSED = {
29161 +  32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
29162 +};
29163 +
29164 +static const CGEN_IFMT ifmt_move_1_d_indirect_with_pre_increment_1_s1_indirect_with_index_1 ATTRIBUTE_UNUSED = {
29165 +  32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
29166 +};
29167 +
29168 +static const CGEN_IFMT ifmt_move_1_d_direct_s1_indirect_with_offset_1 ATTRIBUTE_UNUSED = {
29169 +  32, 32, 0xff00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } }
29170 +};
29171 +
29172 +static const CGEN_IFMT ifmt_move_1_d_immediate_1_s1_indirect_with_offset_1 ATTRIBUTE_UNUSED = {
29173 +  32, 32, 0xff00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } }
29174 +};
29175 +
29176 +static const CGEN_IFMT ifmt_move_1_d_indirect_with_index_1_s1_indirect_with_offset_1 ATTRIBUTE_UNUSED = {
29177 +  32, 32, 0xff00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } }
29178 +};
29179 +
29180 +static const CGEN_IFMT ifmt_move_1_d_indirect_with_offset_1_s1_indirect_with_offset_1 ATTRIBUTE_UNUSED = {
29181 +  32, 32, 0xfc00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } }
29182 +};
29183 +
29184 +static const CGEN_IFMT ifmt_move_1_d_indirect_1_s1_indirect_with_offset_1 ATTRIBUTE_UNUSED = {
29185 +  32, 32, 0xff1ffc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } }
29186 +};
29187 +
29188 +static const CGEN_IFMT ifmt_move_1_d_indirect_with_post_increment_1_s1_indirect_with_offset_1 ATTRIBUTE_UNUSED = {
29189 +  32, 32, 0xff10fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } }
29190 +};
29191 +
29192 +static const CGEN_IFMT ifmt_move_1_d_indirect_with_pre_increment_1_s1_indirect_with_offset_1 ATTRIBUTE_UNUSED = {
29193 +  32, 32, 0xff10fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } }
29194 +};
29195 +
29196 +static const CGEN_IFMT ifmt_move_1_d_direct_s1_indirect_1 ATTRIBUTE_UNUSED = {
29197 +  32, 32, 0xff00ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } }
29198 +};
29199 +
29200 +static const CGEN_IFMT ifmt_move_1_d_immediate_1_s1_indirect_1 ATTRIBUTE_UNUSED = {
29201 +  32, 32, 0xff00ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } }
29202 +};
29203 +
29204 +static const CGEN_IFMT ifmt_move_1_d_indirect_with_index_1_s1_indirect_1 ATTRIBUTE_UNUSED = {
29205 +  32, 32, 0xff00ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } }
29206 +};
29207 +
29208 +static const CGEN_IFMT ifmt_move_1_d_indirect_with_offset_1_s1_indirect_1 ATTRIBUTE_UNUSED = {
29209 +  32, 32, 0xfc00ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } }
29210 +};
29211 +
29212 +static const CGEN_IFMT ifmt_move_1_d_indirect_1_s1_indirect_1 ATTRIBUTE_UNUSED = {
29213 +  32, 32, 0xff1fff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } }
29214 +};
29215 +
29216 +static const CGEN_IFMT ifmt_move_1_d_indirect_with_post_increment_1_s1_indirect_1 ATTRIBUTE_UNUSED = {
29217 +  32, 32, 0xff10ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } }
29218 +};
29219 +
29220 +static const CGEN_IFMT ifmt_move_1_d_indirect_with_pre_increment_1_s1_indirect_1 ATTRIBUTE_UNUSED = {
29221 +  32, 32, 0xff10ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } }
29222 +};
29223 +
29224 +static const CGEN_IFMT ifmt_move_1_d_direct_s1_indirect_with_post_increment_1 ATTRIBUTE_UNUSED = {
29225 +  32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } }
29226 +};
29227 +
29228 +static const CGEN_IFMT ifmt_move_1_d_immediate_1_s1_indirect_with_post_increment_1 ATTRIBUTE_UNUSED = {
29229 +  32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } }
29230 +};
29231 +
29232 +static const CGEN_IFMT ifmt_move_1_d_indirect_with_index_1_s1_indirect_with_post_increment_1 ATTRIBUTE_UNUSED = {
29233 +  32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } }
29234 +};
29235 +
29236 +static const CGEN_IFMT ifmt_move_1_d_indirect_with_offset_1_s1_indirect_with_post_increment_1 ATTRIBUTE_UNUSED = {
29237 +  32, 32, 0xfc00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } }
29238 +};
29239 +
29240 +static const CGEN_IFMT ifmt_move_1_d_indirect_1_s1_indirect_with_post_increment_1 ATTRIBUTE_UNUSED = {
29241 +  32, 32, 0xff1fff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } }
29242 +};
29243 +
29244 +static const CGEN_IFMT ifmt_move_1_d_indirect_with_post_increment_1_s1_indirect_with_post_increment_1 ATTRIBUTE_UNUSED = {
29245 +  32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } }
29246 +};
29247 +
29248 +static const CGEN_IFMT ifmt_move_1_d_indirect_with_pre_increment_1_s1_indirect_with_post_increment_1 ATTRIBUTE_UNUSED = {
29249 +  32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } }
29250 +};
29251 +
29252 +static const CGEN_IFMT ifmt_move_1_d_direct_s1_indirect_with_pre_increment_1 ATTRIBUTE_UNUSED = {
29253 +  32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } }
29254 +};
29255 +
29256 +static const CGEN_IFMT ifmt_move_1_d_immediate_1_s1_indirect_with_pre_increment_1 ATTRIBUTE_UNUSED = {
29257 +  32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } }
29258 +};
29259 +
29260 +static const CGEN_IFMT ifmt_move_1_d_indirect_with_index_1_s1_indirect_with_pre_increment_1 ATTRIBUTE_UNUSED = {
29261 +  32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } }
29262 +};
29263 +
29264 +static const CGEN_IFMT ifmt_move_1_d_indirect_with_offset_1_s1_indirect_with_pre_increment_1 ATTRIBUTE_UNUSED = {
29265 +  32, 32, 0xfc00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } }
29266 +};
29267 +
29268 +static const CGEN_IFMT ifmt_move_1_d_indirect_1_s1_indirect_with_pre_increment_1 ATTRIBUTE_UNUSED = {
29269 +  32, 32, 0xff1fff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } }
29270 +};
29271 +
29272 +static const CGEN_IFMT ifmt_move_1_d_indirect_with_post_increment_1_s1_indirect_with_pre_increment_1 ATTRIBUTE_UNUSED = {
29273 +  32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } }
29274 +};
29275 +
29276 +static const CGEN_IFMT ifmt_move_1_d_indirect_with_pre_increment_1_s1_indirect_with_pre_increment_1 ATTRIBUTE_UNUSED = {
29277 +  32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } }
29278 +};
29279 +
29280 +static const CGEN_IFMT ifmt_movei_d_direct ATTRIBUTE_UNUSED = {
29281 +  32, 32, 0xff000000, { { F (F_OP1) }, { F (F_IMM16_2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { 0 } }
29282 +};
29283 +
29284 +static const CGEN_IFMT ifmt_movei_d_immediate_2 ATTRIBUTE_UNUSED = {
29285 +  32, 32, 0xff000000, { { F (F_OP1) }, { F (F_IMM16_2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { 0 } }
29286 +};
29287 +
29288 +static const CGEN_IFMT ifmt_movei_d_indirect_with_index_2 ATTRIBUTE_UNUSED = {
29289 +  32, 32, 0xff000000, { { F (F_OP1) }, { F (F_IMM16_2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { 0 } }
29290 +};
29291 +
29292 +static const CGEN_IFMT ifmt_movei_d_indirect_with_offset_2 ATTRIBUTE_UNUSED = {
29293 +  32, 32, 0xfc000000, { { F (F_OP1) }, { F (F_IMM16_2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { 0 } }
29294 +};
29295 +
29296 +static const CGEN_IFMT ifmt_movei_d_indirect_2 ATTRIBUTE_UNUSED = {
29297 +  32, 32, 0xff1f0000, { { F (F_OP1) }, { F (F_IMM16_2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { 0 } }
29298 +};
29299 +
29300 +static const CGEN_IFMT ifmt_movei_d_indirect_with_post_increment_2 ATTRIBUTE_UNUSED = {
29301 +  32, 32, 0xff100000, { { F (F_OP1) }, { F (F_IMM16_2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { 0 } }
29302 +};
29303 +
29304 +static const CGEN_IFMT ifmt_movei_d_indirect_with_pre_increment_2 ATTRIBUTE_UNUSED = {
29305 +  32, 32, 0xff100000, { { F (F_OP1) }, { F (F_IMM16_2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { 0 } }
29306 +};
29307 +
29308 +static const CGEN_IFMT ifmt_bclr_d_direct_s1_direct ATTRIBUTE_UNUSED = {
29309 +  32, 32, 0xff000700, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } }
29310 +};
29311 +
29312 +static const CGEN_IFMT ifmt_bclr_d_immediate_4_s1_direct ATTRIBUTE_UNUSED = {
29313 +  32, 32, 0xff000700, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } }
29314 +};
29315 +
29316 +static const CGEN_IFMT ifmt_bclr_d_indirect_with_index_4_s1_direct ATTRIBUTE_UNUSED = {
29317 +  32, 32, 0xff000700, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } }
29318 +};
29319 +
29320 +static const CGEN_IFMT ifmt_bclr_d_indirect_with_offset_4_s1_direct ATTRIBUTE_UNUSED = {
29321 +  32, 32, 0xfc000700, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } }
29322 +};
29323 +
29324 +static const CGEN_IFMT ifmt_bclr_d_indirect_4_s1_direct ATTRIBUTE_UNUSED = {
29325 +  32, 32, 0xff1f0700, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } }
29326 +};
29327 +
29328 +static const CGEN_IFMT ifmt_bclr_d_indirect_with_post_increment_4_s1_direct ATTRIBUTE_UNUSED = {
29329 +  32, 32, 0xff100700, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } }
29330 +};
29331 +
29332 +static const CGEN_IFMT ifmt_bclr_d_indirect_with_pre_increment_4_s1_direct ATTRIBUTE_UNUSED = {
29333 +  32, 32, 0xff100700, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } }
29334 +};
29335 +
29336 +static const CGEN_IFMT ifmt_bclr_d_direct_s1_immediate ATTRIBUTE_UNUSED = {
29337 +  32, 32, 0xff000700, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } }
29338 +};
29339 +
29340 +static const CGEN_IFMT ifmt_bclr_d_immediate_4_s1_immediate ATTRIBUTE_UNUSED = {
29341 +  32, 32, 0xff000700, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } }
29342 +};
29343 +
29344 +static const CGEN_IFMT ifmt_bclr_d_indirect_with_index_4_s1_immediate ATTRIBUTE_UNUSED = {
29345 +  32, 32, 0xff000700, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } }
29346 +};
29347 +
29348 +static const CGEN_IFMT ifmt_bclr_d_indirect_with_offset_4_s1_immediate ATTRIBUTE_UNUSED = {
29349 +  32, 32, 0xfc000700, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } }
29350 +};
29351 +
29352 +static const CGEN_IFMT ifmt_bclr_d_indirect_4_s1_immediate ATTRIBUTE_UNUSED = {
29353 +  32, 32, 0xff1f0700, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } }
29354 +};
29355 +
29356 +static const CGEN_IFMT ifmt_bclr_d_indirect_with_post_increment_4_s1_immediate ATTRIBUTE_UNUSED = {
29357 +  32, 32, 0xff100700, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } }
29358 +};
29359 +
29360 +static const CGEN_IFMT ifmt_bclr_d_indirect_with_pre_increment_4_s1_immediate ATTRIBUTE_UNUSED = {
29361 +  32, 32, 0xff100700, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } }
29362 +};
29363 +
29364 +static const CGEN_IFMT ifmt_bclr_d_direct_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = {
29365 +  32, 32, 0xff000700, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
29366 +};
29367 +
29368 +static const CGEN_IFMT ifmt_bclr_d_immediate_4_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = {
29369 +  32, 32, 0xff000700, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
29370 +};
29371 +
29372 +static const CGEN_IFMT ifmt_bclr_d_indirect_with_index_4_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = {
29373 +  32, 32, 0xff000700, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
29374 +};
29375 +
29376 +static const CGEN_IFMT ifmt_bclr_d_indirect_with_offset_4_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = {
29377 +  32, 32, 0xfc000700, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
29378 +};
29379 +
29380 +static const CGEN_IFMT ifmt_bclr_d_indirect_4_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = {
29381 +  32, 32, 0xff1f0700, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
29382 +};
29383 +
29384 +static const CGEN_IFMT ifmt_bclr_d_indirect_with_post_increment_4_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = {
29385 +  32, 32, 0xff100700, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
29386 +};
29387 +
29388 +static const CGEN_IFMT ifmt_bclr_d_indirect_with_pre_increment_4_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = {
29389 +  32, 32, 0xff100700, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
29390 +};
29391 +
29392 +static const CGEN_IFMT ifmt_bclr_d_direct_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = {
29393 +  32, 32, 0xff000400, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
29394 +};
29395 +
29396 +static const CGEN_IFMT ifmt_bclr_d_immediate_4_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = {
29397 +  32, 32, 0xff000400, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
29398 +};
29399 +
29400 +static const CGEN_IFMT ifmt_bclr_d_indirect_with_index_4_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = {
29401 +  32, 32, 0xff000400, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
29402 +};
29403 +
29404 +static const CGEN_IFMT ifmt_bclr_d_indirect_with_offset_4_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = {
29405 +  32, 32, 0xfc000400, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
29406 +};
29407 +
29408 +static const CGEN_IFMT ifmt_bclr_d_indirect_4_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = {
29409 +  32, 32, 0xff1f0400, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
29410 +};
29411 +
29412 +static const CGEN_IFMT ifmt_bclr_d_indirect_with_post_increment_4_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = {
29413 +  32, 32, 0xff100400, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
29414 +};
29415 +
29416 +static const CGEN_IFMT ifmt_bclr_d_indirect_with_pre_increment_4_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = {
29417 +  32, 32, 0xff100400, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
29418 +};
29419 +
29420 +static const CGEN_IFMT ifmt_bclr_d_direct_s1_indirect_4 ATTRIBUTE_UNUSED = {
29421 +  32, 32, 0xff00071f, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
29422 +};
29423 +
29424 +static const CGEN_IFMT ifmt_bclr_d_immediate_4_s1_indirect_4 ATTRIBUTE_UNUSED = {
29425 +  32, 32, 0xff00071f, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
29426 +};
29427 +
29428 +static const CGEN_IFMT ifmt_bclr_d_indirect_with_index_4_s1_indirect_4 ATTRIBUTE_UNUSED = {
29429 +  32, 32, 0xff00071f, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
29430 +};
29431 +
29432 +static const CGEN_IFMT ifmt_bclr_d_indirect_with_offset_4_s1_indirect_4 ATTRIBUTE_UNUSED = {
29433 +  32, 32, 0xfc00071f, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
29434 +};
29435 +
29436 +static const CGEN_IFMT ifmt_bclr_d_indirect_4_s1_indirect_4 ATTRIBUTE_UNUSED = {
29437 +  32, 32, 0xff1f071f, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
29438 +};
29439 +
29440 +static const CGEN_IFMT ifmt_bclr_d_indirect_with_post_increment_4_s1_indirect_4 ATTRIBUTE_UNUSED = {
29441 +  32, 32, 0xff10071f, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
29442 +};
29443 +
29444 +static const CGEN_IFMT ifmt_bclr_d_indirect_with_pre_increment_4_s1_indirect_4 ATTRIBUTE_UNUSED = {
29445 +  32, 32, 0xff10071f, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
29446 +};
29447 +
29448 +static const CGEN_IFMT ifmt_bclr_d_direct_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = {
29449 +  32, 32, 0xff000710, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
29450 +};
29451 +
29452 +static const CGEN_IFMT ifmt_bclr_d_immediate_4_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = {
29453 +  32, 32, 0xff000710, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
29454 +};
29455 +
29456 +static const CGEN_IFMT ifmt_bclr_d_indirect_with_index_4_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = {
29457 +  32, 32, 0xff000710, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
29458 +};
29459 +
29460 +static const CGEN_IFMT ifmt_bclr_d_indirect_with_offset_4_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = {
29461 +  32, 32, 0xfc000710, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
29462 +};
29463 +
29464 +static const CGEN_IFMT ifmt_bclr_d_indirect_4_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = {
29465 +  32, 32, 0xff1f0710, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
29466 +};
29467 +
29468 +static const CGEN_IFMT ifmt_bclr_d_indirect_with_post_increment_4_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = {
29469 +  32, 32, 0xff100710, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
29470 +};
29471 +
29472 +static const CGEN_IFMT ifmt_bclr_d_indirect_with_pre_increment_4_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = {
29473 +  32, 32, 0xff100710, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
29474 +};
29475 +
29476 +static const CGEN_IFMT ifmt_bclr_d_direct_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = {
29477 +  32, 32, 0xff000710, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
29478 +};
29479 +
29480 +static const CGEN_IFMT ifmt_bclr_d_immediate_4_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = {
29481 +  32, 32, 0xff000710, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
29482 +};
29483 +
29484 +static const CGEN_IFMT ifmt_bclr_d_indirect_with_index_4_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = {
29485 +  32, 32, 0xff000710, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
29486 +};
29487 +
29488 +static const CGEN_IFMT ifmt_bclr_d_indirect_with_offset_4_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = {
29489 +  32, 32, 0xfc000710, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
29490 +};
29491 +
29492 +static const CGEN_IFMT ifmt_bclr_d_indirect_4_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = {
29493 +  32, 32, 0xff1f0710, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
29494 +};
29495 +
29496 +static const CGEN_IFMT ifmt_bclr_d_indirect_with_post_increment_4_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = {
29497 +  32, 32, 0xff100710, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
29498 +};
29499 +
29500 +static const CGEN_IFMT ifmt_bclr_d_indirect_with_pre_increment_4_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = {
29501 +  32, 32, 0xff100710, { { F (F_OP1) }, { F (F_BIT5) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
29502 +};
29503 +
29504 +static const CGEN_IFMT ifmt_btst_s1_direct_imm_bit5 ATTRIBUTE_UNUSED = {
29505 +  32, 32, 0xffff0700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { F (F_BIT26) }, { F (F_BIT5) }, { 0 } }
29506 +};
29507 +
29508 +static const CGEN_IFMT ifmt_btst_s1_immediate_imm_bit5 ATTRIBUTE_UNUSED = {
29509 +  32, 32, 0xffff0700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { F (F_BIT26) }, { F (F_BIT5) }, { 0 } }
29510 +};
29511 +
29512 +static const CGEN_IFMT ifmt_btst_s1_indirect_with_index_4_imm_bit5 ATTRIBUTE_UNUSED = {
29513 +  32, 32, 0xffff0700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_BIT5) }, { 0 } }
29514 +};
29515 +
29516 +static const CGEN_IFMT ifmt_btst_s1_indirect_with_offset_4_imm_bit5 ATTRIBUTE_UNUSED = {
29517 +  32, 32, 0xffff0400, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_BIT5) }, { 0 } }
29518 +};
29519 +
29520 +static const CGEN_IFMT ifmt_btst_s1_indirect_4_imm_bit5 ATTRIBUTE_UNUSED = {
29521 +  32, 32, 0xffff071f, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_BIT5) }, { 0 } }
29522 +};
29523 +
29524 +static const CGEN_IFMT ifmt_btst_s1_indirect_with_post_increment_4_imm_bit5 ATTRIBUTE_UNUSED = {
29525 +  32, 32, 0xffff0710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_BIT5) }, { 0 } }
29526 +};
29527 +
29528 +static const CGEN_IFMT ifmt_btst_s1_indirect_with_pre_increment_4_imm_bit5 ATTRIBUTE_UNUSED = {
29529 +  32, 32, 0xffff0710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_BIT5) }, { 0 } }
29530 +};
29531 +
29532 +static const CGEN_IFMT ifmt_btst_s1_direct_dyn_reg ATTRIBUTE_UNUSED = {
29533 +  32, 32, 0xffff8700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { 0 } }
29534 +};
29535 +
29536 +static const CGEN_IFMT ifmt_btst_s1_immediate_dyn_reg ATTRIBUTE_UNUSED = {
29537 +  32, 32, 0xffff8700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { 0 } }
29538 +};
29539 +
29540 +static const CGEN_IFMT ifmt_btst_s1_indirect_with_index_4_dyn_reg ATTRIBUTE_UNUSED = {
29541 +  32, 32, 0xffff8700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { 0 } }
29542 +};
29543 +
29544 +static const CGEN_IFMT ifmt_btst_s1_indirect_with_offset_4_dyn_reg ATTRIBUTE_UNUSED = {
29545 +  32, 32, 0xffff8400, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { 0 } }
29546 +};
29547 +
29548 +static const CGEN_IFMT ifmt_btst_s1_indirect_4_dyn_reg ATTRIBUTE_UNUSED = {
29549 +  32, 32, 0xffff871f, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { 0 } }
29550 +};
29551 +
29552 +static const CGEN_IFMT ifmt_btst_s1_indirect_with_post_increment_4_dyn_reg ATTRIBUTE_UNUSED = {
29553 +  32, 32, 0xffff8710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { 0 } }
29554 +};
29555 +
29556 +static const CGEN_IFMT ifmt_btst_s1_indirect_with_pre_increment_4_dyn_reg ATTRIBUTE_UNUSED = {
29557 +  32, 32, 0xffff8710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { 0 } }
29558 +};
29559 +
29560 +static const CGEN_IFMT ifmt_shmrg_2_imm_bit5_s1_direct ATTRIBUTE_UNUSED = {
29561 +  32, 32, 0xffe00700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_BIT5) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } }
29562 +};
29563 +
29564 +static const CGEN_IFMT ifmt_shmrg_2_dyn_reg_s1_direct ATTRIBUTE_UNUSED = {
29565 +  32, 32, 0xffe08700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } }
29566 +};
29567 +
29568 +static const CGEN_IFMT ifmt_shmrg_2_imm_bit5_s1_immediate ATTRIBUTE_UNUSED = {
29569 +  32, 32, 0xffe00700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_BIT5) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } }
29570 +};
29571 +
29572 +static const CGEN_IFMT ifmt_shmrg_2_dyn_reg_s1_immediate ATTRIBUTE_UNUSED = {
29573 +  32, 32, 0xffe08700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } }
29574 +};
29575 +
29576 +static const CGEN_IFMT ifmt_shmrg_2_imm_bit5_s1_indirect_with_index_2 ATTRIBUTE_UNUSED = {
29577 +  32, 32, 0xffe00700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_BIT5) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
29578 +};
29579 +
29580 +static const CGEN_IFMT ifmt_shmrg_2_dyn_reg_s1_indirect_with_index_2 ATTRIBUTE_UNUSED = {
29581 +  32, 32, 0xffe08700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
29582 +};
29583 +
29584 +static const CGEN_IFMT ifmt_shmrg_2_imm_bit5_s1_indirect_with_offset_2 ATTRIBUTE_UNUSED = {
29585 +  32, 32, 0xffe00400, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_BIT5) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } }
29586 +};
29587 +
29588 +static const CGEN_IFMT ifmt_shmrg_2_dyn_reg_s1_indirect_with_offset_2 ATTRIBUTE_UNUSED = {
29589 +  32, 32, 0xffe08400, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } }
29590 +};
29591 +
29592 +static const CGEN_IFMT ifmt_shmrg_2_imm_bit5_s1_indirect_2 ATTRIBUTE_UNUSED = {
29593 +  32, 32, 0xffe0071f, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_BIT5) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } }
29594 +};
29595 +
29596 +static const CGEN_IFMT ifmt_shmrg_2_dyn_reg_s1_indirect_2 ATTRIBUTE_UNUSED = {
29597 +  32, 32, 0xffe0871f, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } }
29598 +};
29599 +
29600 +static const CGEN_IFMT ifmt_shmrg_2_imm_bit5_s1_indirect_with_post_increment_2 ATTRIBUTE_UNUSED = {
29601 +  32, 32, 0xffe00710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_BIT5) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } }
29602 +};
29603 +
29604 +static const CGEN_IFMT ifmt_shmrg_2_dyn_reg_s1_indirect_with_post_increment_2 ATTRIBUTE_UNUSED = {
29605 +  32, 32, 0xffe08710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } }
29606 +};
29607 +
29608 +static const CGEN_IFMT ifmt_shmrg_2_imm_bit5_s1_indirect_with_pre_increment_2 ATTRIBUTE_UNUSED = {
29609 +  32, 32, 0xffe00710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_BIT5) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } }
29610 +};
29611 +
29612 +static const CGEN_IFMT ifmt_shmrg_2_dyn_reg_s1_indirect_with_pre_increment_2 ATTRIBUTE_UNUSED = {
29613 +  32, 32, 0xffe08710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } }
29614 +};
29615 +
29616 +static const CGEN_IFMT ifmt_shmrg_1_imm_bit5_s1_indirect_with_index_1 ATTRIBUTE_UNUSED = {
29617 +  32, 32, 0xffe00700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_BIT5) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
29618 +};
29619 +
29620 +static const CGEN_IFMT ifmt_shmrg_1_dyn_reg_s1_indirect_with_index_1 ATTRIBUTE_UNUSED = {
29621 +  32, 32, 0xffe08700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
29622 +};
29623 +
29624 +static const CGEN_IFMT ifmt_shmrg_1_imm_bit5_s1_indirect_with_offset_1 ATTRIBUTE_UNUSED = {
29625 +  32, 32, 0xffe00400, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_BIT5) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } }
29626 +};
29627 +
29628 +static const CGEN_IFMT ifmt_shmrg_1_dyn_reg_s1_indirect_with_offset_1 ATTRIBUTE_UNUSED = {
29629 +  32, 32, 0xffe08400, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } }
29630 +};
29631 +
29632 +static const CGEN_IFMT ifmt_shmrg_1_imm_bit5_s1_indirect_1 ATTRIBUTE_UNUSED = {
29633 +  32, 32, 0xffe0071f, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_BIT5) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } }
29634 +};
29635 +
29636 +static const CGEN_IFMT ifmt_shmrg_1_dyn_reg_s1_indirect_1 ATTRIBUTE_UNUSED = {
29637 +  32, 32, 0xffe0871f, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } }
29638 +};
29639 +
29640 +static const CGEN_IFMT ifmt_shmrg_1_imm_bit5_s1_indirect_with_post_increment_1 ATTRIBUTE_UNUSED = {
29641 +  32, 32, 0xffe00710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_BIT5) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } }
29642 +};
29643 +
29644 +static const CGEN_IFMT ifmt_shmrg_1_dyn_reg_s1_indirect_with_post_increment_1 ATTRIBUTE_UNUSED = {
29645 +  32, 32, 0xffe08710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } }
29646 +};
29647 +
29648 +static const CGEN_IFMT ifmt_shmrg_1_imm_bit5_s1_indirect_with_pre_increment_1 ATTRIBUTE_UNUSED = {
29649 +  32, 32, 0xffe00710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_BIT5) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } }
29650 +};
29651 +
29652 +static const CGEN_IFMT ifmt_shmrg_1_dyn_reg_s1_indirect_with_pre_increment_1 ATTRIBUTE_UNUSED = {
29653 +  32, 32, 0xffe08710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } }
29654 +};
29655 +
29656 +static const CGEN_IFMT ifmt_crcgen_s1_indirect_with_index_1_imm_bit5 ATTRIBUTE_UNUSED = {
29657 +  32, 32, 0xffff0700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_BIT5) }, { 0 } }
29658 +};
29659 +
29660 +static const CGEN_IFMT ifmt_crcgen_s1_indirect_with_offset_1_imm_bit5 ATTRIBUTE_UNUSED = {
29661 +  32, 32, 0xffff0400, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_BIT5) }, { 0 } }
29662 +};
29663 +
29664 +static const CGEN_IFMT ifmt_crcgen_s1_indirect_1_imm_bit5 ATTRIBUTE_UNUSED = {
29665 +  32, 32, 0xffff071f, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_BIT5) }, { 0 } }
29666 +};
29667 +
29668 +static const CGEN_IFMT ifmt_crcgen_s1_indirect_with_post_increment_1_imm_bit5 ATTRIBUTE_UNUSED = {
29669 +  32, 32, 0xffff0710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_BIT5) }, { 0 } }
29670 +};
29671 +
29672 +static const CGEN_IFMT ifmt_crcgen_s1_indirect_with_pre_increment_1_imm_bit5 ATTRIBUTE_UNUSED = {
29673 +  32, 32, 0xffff0710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_BIT5) }, { 0 } }
29674 +};
29675 +
29676 +static const CGEN_IFMT ifmt_crcgen_s1_indirect_with_index_1_dyn_reg ATTRIBUTE_UNUSED = {
29677 +  32, 32, 0xffff8700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { 0 } }
29678 +};
29679 +
29680 +static const CGEN_IFMT ifmt_crcgen_s1_indirect_with_offset_1_dyn_reg ATTRIBUTE_UNUSED = {
29681 +  32, 32, 0xffff8400, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { 0 } }
29682 +};
29683 +
29684 +static const CGEN_IFMT ifmt_crcgen_s1_indirect_1_dyn_reg ATTRIBUTE_UNUSED = {
29685 +  32, 32, 0xffff871f, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { 0 } }
29686 +};
29687 +
29688 +static const CGEN_IFMT ifmt_crcgen_s1_indirect_with_post_increment_1_dyn_reg ATTRIBUTE_UNUSED = {
29689 +  32, 32, 0xffff8710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { 0 } }
29690 +};
29691 +
29692 +static const CGEN_IFMT ifmt_crcgen_s1_indirect_with_pre_increment_1_dyn_reg ATTRIBUTE_UNUSED = {
29693 +  32, 32, 0xffff8710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { 0 } }
29694 +};
29695 +
29696 +static const CGEN_IFMT ifmt_bfextu_s1_direct_imm_bit5 ATTRIBUTE_UNUSED = {
29697 +  32, 32, 0xffe00700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { F (F_BIT26) }, { F (F_BIT5) }, { 0 } }
29698 +};
29699 +
29700 +static const CGEN_IFMT ifmt_bfextu_s1_immediate_imm_bit5 ATTRIBUTE_UNUSED = {
29701 +  32, 32, 0xffe00700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { F (F_BIT26) }, { F (F_BIT5) }, { 0 } }
29702 +};
29703 +
29704 +static const CGEN_IFMT ifmt_bfextu_s1_indirect_with_index_4_imm_bit5 ATTRIBUTE_UNUSED = {
29705 +  32, 32, 0xffe00700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_BIT5) }, { 0 } }
29706 +};
29707 +
29708 +static const CGEN_IFMT ifmt_bfextu_s1_indirect_with_offset_4_imm_bit5 ATTRIBUTE_UNUSED = {
29709 +  32, 32, 0xffe00400, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_BIT5) }, { 0 } }
29710 +};
29711 +
29712 +static const CGEN_IFMT ifmt_bfextu_s1_indirect_4_imm_bit5 ATTRIBUTE_UNUSED = {
29713 +  32, 32, 0xffe0071f, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_BIT5) }, { 0 } }
29714 +};
29715 +
29716 +static const CGEN_IFMT ifmt_bfextu_s1_indirect_with_post_increment_4_imm_bit5 ATTRIBUTE_UNUSED = {
29717 +  32, 32, 0xffe00710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_BIT5) }, { 0 } }
29718 +};
29719 +
29720 +static const CGEN_IFMT ifmt_bfextu_s1_indirect_with_pre_increment_4_imm_bit5 ATTRIBUTE_UNUSED = {
29721 +  32, 32, 0xffe00710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_BIT5) }, { 0 } }
29722 +};
29723 +
29724 +static const CGEN_IFMT ifmt_bfextu_s1_direct_dyn_reg ATTRIBUTE_UNUSED = {
29725 +  32, 32, 0xffe08700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { 0 } }
29726 +};
29727 +
29728 +static const CGEN_IFMT ifmt_bfextu_s1_immediate_dyn_reg ATTRIBUTE_UNUSED = {
29729 +  32, 32, 0xffe08700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { 0 } }
29730 +};
29731 +
29732 +static const CGEN_IFMT ifmt_bfextu_s1_indirect_with_index_4_dyn_reg ATTRIBUTE_UNUSED = {
29733 +  32, 32, 0xffe08700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { 0 } }
29734 +};
29735 +
29736 +static const CGEN_IFMT ifmt_bfextu_s1_indirect_with_offset_4_dyn_reg ATTRIBUTE_UNUSED = {
29737 +  32, 32, 0xffe08400, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { 0 } }
29738 +};
29739 +
29740 +static const CGEN_IFMT ifmt_bfextu_s1_indirect_4_dyn_reg ATTRIBUTE_UNUSED = {
29741 +  32, 32, 0xffe0871f, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { 0 } }
29742 +};
29743 +
29744 +static const CGEN_IFMT ifmt_bfextu_s1_indirect_with_post_increment_4_dyn_reg ATTRIBUTE_UNUSED = {
29745 +  32, 32, 0xffe08710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { 0 } }
29746 +};
29747 +
29748 +static const CGEN_IFMT ifmt_bfextu_s1_indirect_with_pre_increment_4_dyn_reg ATTRIBUTE_UNUSED = {
29749 +  32, 32, 0xffe08710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { 0 } }
29750 +};
29751 +
29752 +static const CGEN_IFMT ifmt_asr_4_imm_bit5_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = {
29753 +  32, 32, 0xffe00700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_BIT5) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
29754 +};
29755 +
29756 +static const CGEN_IFMT ifmt_asr_4_dyn_reg_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = {
29757 +  32, 32, 0xffe08700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
29758 +};
29759 +
29760 +static const CGEN_IFMT ifmt_asr_4_imm_bit5_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = {
29761 +  32, 32, 0xffe00400, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_BIT5) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
29762 +};
29763 +
29764 +static const CGEN_IFMT ifmt_asr_4_dyn_reg_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = {
29765 +  32, 32, 0xffe08400, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
29766 +};
29767 +
29768 +static const CGEN_IFMT ifmt_asr_4_imm_bit5_s1_indirect_4 ATTRIBUTE_UNUSED = {
29769 +  32, 32, 0xffe0071f, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_BIT5) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
29770 +};
29771 +
29772 +static const CGEN_IFMT ifmt_asr_4_dyn_reg_s1_indirect_4 ATTRIBUTE_UNUSED = {
29773 +  32, 32, 0xffe0871f, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
29774 +};
29775 +
29776 +static const CGEN_IFMT ifmt_asr_4_imm_bit5_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = {
29777 +  32, 32, 0xffe00710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_BIT5) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
29778 +};
29779 +
29780 +static const CGEN_IFMT ifmt_asr_4_dyn_reg_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = {
29781 +  32, 32, 0xffe08710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
29782 +};
29783 +
29784 +static const CGEN_IFMT ifmt_asr_4_imm_bit5_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = {
29785 +  32, 32, 0xffe00710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_BIT5) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
29786 +};
29787 +
29788 +static const CGEN_IFMT ifmt_asr_4_dyn_reg_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = {
29789 +  32, 32, 0xffe08710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
29790 +};
29791 +
29792 +static const CGEN_IFMT ifmt_compatibility_mac_s1_direct_dsp_src2_data_reg ATTRIBUTE_UNUSED = {
29793 +  32, 32, 0xffff8700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
29794 +};
29795 +
29796 +static const CGEN_IFMT ifmt_compatibility_mac_s1_immediate_dsp_src2_data_reg ATTRIBUTE_UNUSED = {
29797 +  32, 32, 0xffff8700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
29798 +};
29799 +
29800 +static const CGEN_IFMT ifmt_compatibility_mac_s1_indirect_with_index_2_dsp_src2_data_reg ATTRIBUTE_UNUSED = {
29801 +  32, 32, 0xffff8700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
29802 +};
29803 +
29804 +static const CGEN_IFMT ifmt_compatibility_mac_s1_indirect_with_offset_2_dsp_src2_data_reg ATTRIBUTE_UNUSED = {
29805 +  32, 32, 0xffff8400, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
29806 +};
29807 +
29808 +static const CGEN_IFMT ifmt_compatibility_mac_s1_indirect_2_dsp_src2_data_reg ATTRIBUTE_UNUSED = {
29809 +  32, 32, 0xffff871f, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
29810 +};
29811 +
29812 +static const CGEN_IFMT ifmt_compatibility_mac_s1_indirect_with_post_increment_2_dsp_src2_data_reg ATTRIBUTE_UNUSED = {
29813 +  32, 32, 0xffff8710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
29814 +};
29815 +
29816 +static const CGEN_IFMT ifmt_compatibility_mac_s1_indirect_with_pre_increment_2_dsp_src2_data_reg ATTRIBUTE_UNUSED = {
29817 +  32, 32, 0xffff8710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_B15) }, { F (F_BIT26) }, { F (F_DSP_S2) }, { 0 } }
29818 +};
29819 +
29820 +static const CGEN_IFMT ifmt_compatibility_mac_s1_direct_dsp_imm_bit5 ATTRIBUTE_UNUSED = {
29821 +  32, 32, 0xffff0700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } }
29822 +};
29823 +
29824 +static const CGEN_IFMT ifmt_compatibility_mac_s1_immediate_dsp_imm_bit5 ATTRIBUTE_UNUSED = {
29825 +  32, 32, 0xffff0700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } }
29826 +};
29827 +
29828 +static const CGEN_IFMT ifmt_compatibility_mac_s1_indirect_with_index_2_dsp_imm_bit5 ATTRIBUTE_UNUSED = {
29829 +  32, 32, 0xffff0700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } }
29830 +};
29831 +
29832 +static const CGEN_IFMT ifmt_compatibility_mac_s1_indirect_with_offset_2_dsp_imm_bit5 ATTRIBUTE_UNUSED = {
29833 +  32, 32, 0xffff0400, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } }
29834 +};
29835 +
29836 +static const CGEN_IFMT ifmt_compatibility_mac_s1_indirect_2_dsp_imm_bit5 ATTRIBUTE_UNUSED = {
29837 +  32, 32, 0xffff071f, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } }
29838 +};
29839 +
29840 +static const CGEN_IFMT ifmt_compatibility_mac_s1_indirect_with_post_increment_2_dsp_imm_bit5 ATTRIBUTE_UNUSED = {
29841 +  32, 32, 0xffff0710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } }
29842 +};
29843 +
29844 +static const CGEN_IFMT ifmt_compatibility_mac_s1_indirect_with_pre_increment_2_dsp_imm_bit5 ATTRIBUTE_UNUSED = {
29845 +  32, 32, 0xffff0710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { 0 } }
29846 +};
29847 +
29848 +static const CGEN_IFMT ifmt_mac_s1_indirect_with_index_2_imm_bit5 ATTRIBUTE_UNUSED = {
29849 +  32, 32, 0xffff0700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_BIT5) }, { 0 } }
29850 +};
29851 +
29852 +static const CGEN_IFMT ifmt_mac_s1_indirect_with_offset_2_imm_bit5 ATTRIBUTE_UNUSED = {
29853 +  32, 32, 0xffff0400, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_BIT5) }, { 0 } }
29854 +};
29855 +
29856 +static const CGEN_IFMT ifmt_mac_s1_indirect_2_imm_bit5 ATTRIBUTE_UNUSED = {
29857 +  32, 32, 0xffff071f, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_BIT5) }, { 0 } }
29858 +};
29859 +
29860 +static const CGEN_IFMT ifmt_mac_s1_indirect_with_post_increment_2_imm_bit5 ATTRIBUTE_UNUSED = {
29861 +  32, 32, 0xffff0710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_BIT5) }, { 0 } }
29862 +};
29863 +
29864 +static const CGEN_IFMT ifmt_mac_s1_indirect_with_pre_increment_2_imm_bit5 ATTRIBUTE_UNUSED = {
29865 +  32, 32, 0xffff0710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_BIT5) }, { 0 } }
29866 +};
29867 +
29868 +static const CGEN_IFMT ifmt_mac_s1_indirect_with_index_2_dyn_reg ATTRIBUTE_UNUSED = {
29869 +  32, 32, 0xffff8700, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { 0 } }
29870 +};
29871 +
29872 +static const CGEN_IFMT ifmt_mac_s1_indirect_with_offset_2_dyn_reg ATTRIBUTE_UNUSED = {
29873 +  32, 32, 0xffff8400, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { 0 } }
29874 +};
29875 +
29876 +static const CGEN_IFMT ifmt_mac_s1_indirect_2_dyn_reg ATTRIBUTE_UNUSED = {
29877 +  32, 32, 0xffff871f, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { 0 } }
29878 +};
29879 +
29880 +static const CGEN_IFMT ifmt_mac_s1_indirect_with_post_increment_2_dyn_reg ATTRIBUTE_UNUSED = {
29881 +  32, 32, 0xffff8710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { 0 } }
29882 +};
29883 +
29884 +static const CGEN_IFMT ifmt_mac_s1_indirect_with_pre_increment_2_dyn_reg ATTRIBUTE_UNUSED = {
29885 +  32, 32, 0xffff8710, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { F (F_BIT26) }, { F (F_B15) }, { F (F_S2) }, { 0 } }
29886 +};
29887 +
29888 +static const CGEN_IFMT ifmt_pdec_d_direct_pdec_s1_ea_indirect_with_offset_4 ATTRIBUTE_UNUSED = {
29889 +  32, 32, 0xff00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
29890 +};
29891 +
29892 +static const CGEN_IFMT ifmt_pdec_d_immediate_4_pdec_s1_ea_indirect_with_offset_4 ATTRIBUTE_UNUSED = {
29893 +  32, 32, 0xff00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
29894 +};
29895 +
29896 +static const CGEN_IFMT ifmt_pdec_d_indirect_with_index_4_pdec_s1_ea_indirect_with_offset_4 ATTRIBUTE_UNUSED = {
29897 +  32, 32, 0xff00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
29898 +};
29899 +
29900 +static const CGEN_IFMT ifmt_pdec_d_indirect_with_offset_4_pdec_s1_ea_indirect_with_offset_4 ATTRIBUTE_UNUSED = {
29901 +  32, 32, 0xfc00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
29902 +};
29903 +
29904 +static const CGEN_IFMT ifmt_pdec_d_indirect_4_pdec_s1_ea_indirect_with_offset_4 ATTRIBUTE_UNUSED = {
29905 +  32, 32, 0xff1ffc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
29906 +};
29907 +
29908 +static const CGEN_IFMT ifmt_pdec_d_indirect_with_post_increment_4_pdec_s1_ea_indirect_with_offset_4 ATTRIBUTE_UNUSED = {
29909 +  32, 32, 0xff10fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
29910 +};
29911 +
29912 +static const CGEN_IFMT ifmt_pdec_d_indirect_with_pre_increment_4_pdec_s1_ea_indirect_with_offset_4 ATTRIBUTE_UNUSED = {
29913 +  32, 32, 0xff10fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
29914 +};
29915 +
29916 +static const CGEN_IFMT ifmt_lea_4_d_direct_s1_ea_indirect ATTRIBUTE_UNUSED = {
29917 +  32, 32, 0xff00ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
29918 +};
29919 +
29920 +static const CGEN_IFMT ifmt_lea_4_d_immediate_4_s1_ea_indirect ATTRIBUTE_UNUSED = {
29921 +  32, 32, 0xff00ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
29922 +};
29923 +
29924 +static const CGEN_IFMT ifmt_lea_4_d_indirect_with_index_4_s1_ea_indirect ATTRIBUTE_UNUSED = {
29925 +  32, 32, 0xff00ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
29926 +};
29927 +
29928 +static const CGEN_IFMT ifmt_lea_4_d_indirect_with_offset_4_s1_ea_indirect ATTRIBUTE_UNUSED = {
29929 +  32, 32, 0xfc00ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
29930 +};
29931 +
29932 +static const CGEN_IFMT ifmt_lea_4_d_indirect_4_s1_ea_indirect ATTRIBUTE_UNUSED = {
29933 +  32, 32, 0xff1fff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
29934 +};
29935 +
29936 +static const CGEN_IFMT ifmt_lea_4_d_indirect_with_post_increment_4_s1_ea_indirect ATTRIBUTE_UNUSED = {
29937 +  32, 32, 0xff10ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
29938 +};
29939 +
29940 +static const CGEN_IFMT ifmt_lea_4_d_indirect_with_pre_increment_4_s1_ea_indirect ATTRIBUTE_UNUSED = {
29941 +  32, 32, 0xff10ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
29942 +};
29943 +
29944 +static const CGEN_IFMT ifmt_lea_4_d_direct_s1_ea_indirect_with_offset_4 ATTRIBUTE_UNUSED = {
29945 +  32, 32, 0xff00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
29946 +};
29947 +
29948 +static const CGEN_IFMT ifmt_lea_4_d_immediate_4_s1_ea_indirect_with_offset_4 ATTRIBUTE_UNUSED = {
29949 +  32, 32, 0xff00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
29950 +};
29951 +
29952 +static const CGEN_IFMT ifmt_lea_4_d_indirect_with_index_4_s1_ea_indirect_with_offset_4 ATTRIBUTE_UNUSED = {
29953 +  32, 32, 0xff00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
29954 +};
29955 +
29956 +static const CGEN_IFMT ifmt_lea_4_d_indirect_with_offset_4_s1_ea_indirect_with_offset_4 ATTRIBUTE_UNUSED = {
29957 +  32, 32, 0xfc00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
29958 +};
29959 +
29960 +static const CGEN_IFMT ifmt_lea_4_d_indirect_4_s1_ea_indirect_with_offset_4 ATTRIBUTE_UNUSED = {
29961 +  32, 32, 0xff1ffc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
29962 +};
29963 +
29964 +static const CGEN_IFMT ifmt_lea_4_d_indirect_with_post_increment_4_s1_ea_indirect_with_offset_4 ATTRIBUTE_UNUSED = {
29965 +  32, 32, 0xff10fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
29966 +};
29967 +
29968 +static const CGEN_IFMT ifmt_lea_4_d_indirect_with_pre_increment_4_s1_ea_indirect_with_offset_4 ATTRIBUTE_UNUSED = {
29969 +  32, 32, 0xff10fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
29970 +};
29971 +
29972 +static const CGEN_IFMT ifmt_lea_4_d_direct_s1_ea_indirect_with_index_4 ATTRIBUTE_UNUSED = {
29973 +  32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
29974 +};
29975 +
29976 +static const CGEN_IFMT ifmt_lea_4_d_immediate_4_s1_ea_indirect_with_index_4 ATTRIBUTE_UNUSED = {
29977 +  32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
29978 +};
29979 +
29980 +static const CGEN_IFMT ifmt_lea_4_d_indirect_with_index_4_s1_ea_indirect_with_index_4 ATTRIBUTE_UNUSED = {
29981 +  32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
29982 +};
29983 +
29984 +static const CGEN_IFMT ifmt_lea_4_d_indirect_with_offset_4_s1_ea_indirect_with_index_4 ATTRIBUTE_UNUSED = {
29985 +  32, 32, 0xfc00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
29986 +};
29987 +
29988 +static const CGEN_IFMT ifmt_lea_4_d_indirect_4_s1_ea_indirect_with_index_4 ATTRIBUTE_UNUSED = {
29989 +  32, 32, 0xff1fff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
29990 +};
29991 +
29992 +static const CGEN_IFMT ifmt_lea_4_d_indirect_with_post_increment_4_s1_ea_indirect_with_index_4 ATTRIBUTE_UNUSED = {
29993 +  32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
29994 +};
29995 +
29996 +static const CGEN_IFMT ifmt_lea_4_d_indirect_with_pre_increment_4_s1_ea_indirect_with_index_4 ATTRIBUTE_UNUSED = {
29997 +  32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
29998 +};
29999 +
30000 +static const CGEN_IFMT ifmt_lea_4_d_direct_s1_ea_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = {
30001 +  32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
30002 +};
30003 +
30004 +static const CGEN_IFMT ifmt_lea_4_d_immediate_4_s1_ea_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = {
30005 +  32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
30006 +};
30007 +
30008 +static const CGEN_IFMT ifmt_lea_4_d_indirect_with_index_4_s1_ea_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = {
30009 +  32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
30010 +};
30011 +
30012 +static const CGEN_IFMT ifmt_lea_4_d_indirect_with_offset_4_s1_ea_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = {
30013 +  32, 32, 0xfc00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
30014 +};
30015 +
30016 +static const CGEN_IFMT ifmt_lea_4_d_indirect_4_s1_ea_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = {
30017 +  32, 32, 0xff1fff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
30018 +};
30019 +
30020 +static const CGEN_IFMT ifmt_lea_4_d_indirect_with_post_increment_4_s1_ea_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = {
30021 +  32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
30022 +};
30023 +
30024 +static const CGEN_IFMT ifmt_lea_4_d_indirect_with_pre_increment_4_s1_ea_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = {
30025 +  32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
30026 +};
30027 +
30028 +static const CGEN_IFMT ifmt_lea_4_d_direct_s1_ea_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = {
30029 +  32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
30030 +};
30031 +
30032 +static const CGEN_IFMT ifmt_lea_4_d_immediate_4_s1_ea_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = {
30033 +  32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
30034 +};
30035 +
30036 +static const CGEN_IFMT ifmt_lea_4_d_indirect_with_index_4_s1_ea_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = {
30037 +  32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
30038 +};
30039 +
30040 +static const CGEN_IFMT ifmt_lea_4_d_indirect_with_offset_4_s1_ea_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = {
30041 +  32, 32, 0xfc00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
30042 +};
30043 +
30044 +static const CGEN_IFMT ifmt_lea_4_d_indirect_4_s1_ea_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = {
30045 +  32, 32, 0xff1fff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
30046 +};
30047 +
30048 +static const CGEN_IFMT ifmt_lea_4_d_indirect_with_post_increment_4_s1_ea_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = {
30049 +  32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
30050 +};
30051 +
30052 +static const CGEN_IFMT ifmt_lea_4_d_indirect_with_pre_increment_4_s1_ea_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = {
30053 +  32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
30054 +};
30055 +
30056 +static const CGEN_IFMT ifmt_lea_4_d_direct_s1_ea_immediate ATTRIBUTE_UNUSED = {
30057 +  32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } }
30058 +};
30059 +
30060 +static const CGEN_IFMT ifmt_lea_4_d_immediate_4_s1_ea_immediate ATTRIBUTE_UNUSED = {
30061 +  32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } }
30062 +};
30063 +
30064 +static const CGEN_IFMT ifmt_lea_4_d_indirect_with_index_4_s1_ea_immediate ATTRIBUTE_UNUSED = {
30065 +  32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } }
30066 +};
30067 +
30068 +static const CGEN_IFMT ifmt_lea_4_d_indirect_with_offset_4_s1_ea_immediate ATTRIBUTE_UNUSED = {
30069 +  32, 32, 0xfc00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } }
30070 +};
30071 +
30072 +static const CGEN_IFMT ifmt_lea_4_d_indirect_4_s1_ea_immediate ATTRIBUTE_UNUSED = {
30073 +  32, 32, 0xff1fff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } }
30074 +};
30075 +
30076 +static const CGEN_IFMT ifmt_lea_4_d_indirect_with_post_increment_4_s1_ea_immediate ATTRIBUTE_UNUSED = {
30077 +  32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } }
30078 +};
30079 +
30080 +static const CGEN_IFMT ifmt_lea_4_d_indirect_with_pre_increment_4_s1_ea_immediate ATTRIBUTE_UNUSED = {
30081 +  32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } }
30082 +};
30083 +
30084 +static const CGEN_IFMT ifmt_lea_2_d_direct_s1_ea_indirect_with_offset_2 ATTRIBUTE_UNUSED = {
30085 +  32, 32, 0xff00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } }
30086 +};
30087 +
30088 +static const CGEN_IFMT ifmt_lea_2_d_immediate_4_s1_ea_indirect_with_offset_2 ATTRIBUTE_UNUSED = {
30089 +  32, 32, 0xff00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } }
30090 +};
30091 +
30092 +static const CGEN_IFMT ifmt_lea_2_d_indirect_with_index_4_s1_ea_indirect_with_offset_2 ATTRIBUTE_UNUSED = {
30093 +  32, 32, 0xff00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } }
30094 +};
30095 +
30096 +static const CGEN_IFMT ifmt_lea_2_d_indirect_with_offset_4_s1_ea_indirect_with_offset_2 ATTRIBUTE_UNUSED = {
30097 +  32, 32, 0xfc00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } }
30098 +};
30099 +
30100 +static const CGEN_IFMT ifmt_lea_2_d_indirect_4_s1_ea_indirect_with_offset_2 ATTRIBUTE_UNUSED = {
30101 +  32, 32, 0xff1ffc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } }
30102 +};
30103 +
30104 +static const CGEN_IFMT ifmt_lea_2_d_indirect_with_post_increment_4_s1_ea_indirect_with_offset_2 ATTRIBUTE_UNUSED = {
30105 +  32, 32, 0xff10fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } }
30106 +};
30107 +
30108 +static const CGEN_IFMT ifmt_lea_2_d_indirect_with_pre_increment_4_s1_ea_indirect_with_offset_2 ATTRIBUTE_UNUSED = {
30109 +  32, 32, 0xff10fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } }
30110 +};
30111 +
30112 +static const CGEN_IFMT ifmt_lea_2_d_direct_s1_ea_indirect_with_index_2 ATTRIBUTE_UNUSED = {
30113 +  32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
30114 +};
30115 +
30116 +static const CGEN_IFMT ifmt_lea_2_d_immediate_4_s1_ea_indirect_with_index_2 ATTRIBUTE_UNUSED = {
30117 +  32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
30118 +};
30119 +
30120 +static const CGEN_IFMT ifmt_lea_2_d_indirect_with_index_4_s1_ea_indirect_with_index_2 ATTRIBUTE_UNUSED = {
30121 +  32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
30122 +};
30123 +
30124 +static const CGEN_IFMT ifmt_lea_2_d_indirect_with_offset_4_s1_ea_indirect_with_index_2 ATTRIBUTE_UNUSED = {
30125 +  32, 32, 0xfc00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
30126 +};
30127 +
30128 +static const CGEN_IFMT ifmt_lea_2_d_indirect_4_s1_ea_indirect_with_index_2 ATTRIBUTE_UNUSED = {
30129 +  32, 32, 0xff1fff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
30130 +};
30131 +
30132 +static const CGEN_IFMT ifmt_lea_2_d_indirect_with_post_increment_4_s1_ea_indirect_with_index_2 ATTRIBUTE_UNUSED = {
30133 +  32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
30134 +};
30135 +
30136 +static const CGEN_IFMT ifmt_lea_2_d_indirect_with_pre_increment_4_s1_ea_indirect_with_index_2 ATTRIBUTE_UNUSED = {
30137 +  32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
30138 +};
30139 +
30140 +static const CGEN_IFMT ifmt_lea_2_d_direct_s1_ea_indirect_with_post_increment_2 ATTRIBUTE_UNUSED = {
30141 +  32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } }
30142 +};
30143 +
30144 +static const CGEN_IFMT ifmt_lea_2_d_immediate_4_s1_ea_indirect_with_post_increment_2 ATTRIBUTE_UNUSED = {
30145 +  32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } }
30146 +};
30147 +
30148 +static const CGEN_IFMT ifmt_lea_2_d_indirect_with_index_4_s1_ea_indirect_with_post_increment_2 ATTRIBUTE_UNUSED = {
30149 +  32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } }
30150 +};
30151 +
30152 +static const CGEN_IFMT ifmt_lea_2_d_indirect_with_offset_4_s1_ea_indirect_with_post_increment_2 ATTRIBUTE_UNUSED = {
30153 +  32, 32, 0xfc00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } }
30154 +};
30155 +
30156 +static const CGEN_IFMT ifmt_lea_2_d_indirect_4_s1_ea_indirect_with_post_increment_2 ATTRIBUTE_UNUSED = {
30157 +  32, 32, 0xff1fff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } }
30158 +};
30159 +
30160 +static const CGEN_IFMT ifmt_lea_2_d_indirect_with_post_increment_4_s1_ea_indirect_with_post_increment_2 ATTRIBUTE_UNUSED = {
30161 +  32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } }
30162 +};
30163 +
30164 +static const CGEN_IFMT ifmt_lea_2_d_indirect_with_pre_increment_4_s1_ea_indirect_with_post_increment_2 ATTRIBUTE_UNUSED = {
30165 +  32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } }
30166 +};
30167 +
30168 +static const CGEN_IFMT ifmt_lea_2_d_direct_s1_ea_indirect_with_pre_increment_2 ATTRIBUTE_UNUSED = {
30169 +  32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } }
30170 +};
30171 +
30172 +static const CGEN_IFMT ifmt_lea_2_d_immediate_4_s1_ea_indirect_with_pre_increment_2 ATTRIBUTE_UNUSED = {
30173 +  32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } }
30174 +};
30175 +
30176 +static const CGEN_IFMT ifmt_lea_2_d_indirect_with_index_4_s1_ea_indirect_with_pre_increment_2 ATTRIBUTE_UNUSED = {
30177 +  32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } }
30178 +};
30179 +
30180 +static const CGEN_IFMT ifmt_lea_2_d_indirect_with_offset_4_s1_ea_indirect_with_pre_increment_2 ATTRIBUTE_UNUSED = {
30181 +  32, 32, 0xfc00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } }
30182 +};
30183 +
30184 +static const CGEN_IFMT ifmt_lea_2_d_indirect_4_s1_ea_indirect_with_pre_increment_2 ATTRIBUTE_UNUSED = {
30185 +  32, 32, 0xff1fff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } }
30186 +};
30187 +
30188 +static const CGEN_IFMT ifmt_lea_2_d_indirect_with_post_increment_4_s1_ea_indirect_with_pre_increment_2 ATTRIBUTE_UNUSED = {
30189 +  32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } }
30190 +};
30191 +
30192 +static const CGEN_IFMT ifmt_lea_2_d_indirect_with_pre_increment_4_s1_ea_indirect_with_pre_increment_2 ATTRIBUTE_UNUSED = {
30193 +  32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } }
30194 +};
30195 +
30196 +static const CGEN_IFMT ifmt_lea_1_d_direct_s1_ea_indirect_with_offset_1 ATTRIBUTE_UNUSED = {
30197 +  32, 32, 0xff00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } }
30198 +};
30199 +
30200 +static const CGEN_IFMT ifmt_lea_1_d_immediate_4_s1_ea_indirect_with_offset_1 ATTRIBUTE_UNUSED = {
30201 +  32, 32, 0xff00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } }
30202 +};
30203 +
30204 +static const CGEN_IFMT ifmt_lea_1_d_indirect_with_index_4_s1_ea_indirect_with_offset_1 ATTRIBUTE_UNUSED = {
30205 +  32, 32, 0xff00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } }
30206 +};
30207 +
30208 +static const CGEN_IFMT ifmt_lea_1_d_indirect_with_offset_4_s1_ea_indirect_with_offset_1 ATTRIBUTE_UNUSED = {
30209 +  32, 32, 0xfc00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } }
30210 +};
30211 +
30212 +static const CGEN_IFMT ifmt_lea_1_d_indirect_4_s1_ea_indirect_with_offset_1 ATTRIBUTE_UNUSED = {
30213 +  32, 32, 0xff1ffc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } }
30214 +};
30215 +
30216 +static const CGEN_IFMT ifmt_lea_1_d_indirect_with_post_increment_4_s1_ea_indirect_with_offset_1 ATTRIBUTE_UNUSED = {
30217 +  32, 32, 0xff10fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } }
30218 +};
30219 +
30220 +static const CGEN_IFMT ifmt_lea_1_d_indirect_with_pre_increment_4_s1_ea_indirect_with_offset_1 ATTRIBUTE_UNUSED = {
30221 +  32, 32, 0xff10fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } }
30222 +};
30223 +
30224 +static const CGEN_IFMT ifmt_lea_1_d_direct_s1_ea_indirect_with_index_1 ATTRIBUTE_UNUSED = {
30225 +  32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
30226 +};
30227 +
30228 +static const CGEN_IFMT ifmt_lea_1_d_immediate_4_s1_ea_indirect_with_index_1 ATTRIBUTE_UNUSED = {
30229 +  32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
30230 +};
30231 +
30232 +static const CGEN_IFMT ifmt_lea_1_d_indirect_with_index_4_s1_ea_indirect_with_index_1 ATTRIBUTE_UNUSED = {
30233 +  32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
30234 +};
30235 +
30236 +static const CGEN_IFMT ifmt_lea_1_d_indirect_with_offset_4_s1_ea_indirect_with_index_1 ATTRIBUTE_UNUSED = {
30237 +  32, 32, 0xfc00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
30238 +};
30239 +
30240 +static const CGEN_IFMT ifmt_lea_1_d_indirect_4_s1_ea_indirect_with_index_1 ATTRIBUTE_UNUSED = {
30241 +  32, 32, 0xff1fff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
30242 +};
30243 +
30244 +static const CGEN_IFMT ifmt_lea_1_d_indirect_with_post_increment_4_s1_ea_indirect_with_index_1 ATTRIBUTE_UNUSED = {
30245 +  32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
30246 +};
30247 +
30248 +static const CGEN_IFMT ifmt_lea_1_d_indirect_with_pre_increment_4_s1_ea_indirect_with_index_1 ATTRIBUTE_UNUSED = {
30249 +  32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
30250 +};
30251 +
30252 +static const CGEN_IFMT ifmt_lea_1_d_direct_s1_ea_indirect_with_post_increment_1 ATTRIBUTE_UNUSED = {
30253 +  32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } }
30254 +};
30255 +
30256 +static const CGEN_IFMT ifmt_lea_1_d_immediate_4_s1_ea_indirect_with_post_increment_1 ATTRIBUTE_UNUSED = {
30257 +  32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } }
30258 +};
30259 +
30260 +static const CGEN_IFMT ifmt_lea_1_d_indirect_with_index_4_s1_ea_indirect_with_post_increment_1 ATTRIBUTE_UNUSED = {
30261 +  32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } }
30262 +};
30263 +
30264 +static const CGEN_IFMT ifmt_lea_1_d_indirect_with_offset_4_s1_ea_indirect_with_post_increment_1 ATTRIBUTE_UNUSED = {
30265 +  32, 32, 0xfc00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } }
30266 +};
30267 +
30268 +static const CGEN_IFMT ifmt_lea_1_d_indirect_4_s1_ea_indirect_with_post_increment_1 ATTRIBUTE_UNUSED = {
30269 +  32, 32, 0xff1fff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } }
30270 +};
30271 +
30272 +static const CGEN_IFMT ifmt_lea_1_d_indirect_with_post_increment_4_s1_ea_indirect_with_post_increment_1 ATTRIBUTE_UNUSED = {
30273 +  32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } }
30274 +};
30275 +
30276 +static const CGEN_IFMT ifmt_lea_1_d_indirect_with_pre_increment_4_s1_ea_indirect_with_post_increment_1 ATTRIBUTE_UNUSED = {
30277 +  32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } }
30278 +};
30279 +
30280 +static const CGEN_IFMT ifmt_lea_1_d_direct_s1_ea_indirect_with_pre_increment_1 ATTRIBUTE_UNUSED = {
30281 +  32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } }
30282 +};
30283 +
30284 +static const CGEN_IFMT ifmt_lea_1_d_immediate_4_s1_ea_indirect_with_pre_increment_1 ATTRIBUTE_UNUSED = {
30285 +  32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } }
30286 +};
30287 +
30288 +static const CGEN_IFMT ifmt_lea_1_d_indirect_with_index_4_s1_ea_indirect_with_pre_increment_1 ATTRIBUTE_UNUSED = {
30289 +  32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } }
30290 +};
30291 +
30292 +static const CGEN_IFMT ifmt_lea_1_d_indirect_with_offset_4_s1_ea_indirect_with_pre_increment_1 ATTRIBUTE_UNUSED = {
30293 +  32, 32, 0xfc00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } }
30294 +};
30295 +
30296 +static const CGEN_IFMT ifmt_lea_1_d_indirect_4_s1_ea_indirect_with_pre_increment_1 ATTRIBUTE_UNUSED = {
30297 +  32, 32, 0xff1fff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } }
30298 +};
30299 +
30300 +static const CGEN_IFMT ifmt_lea_1_d_indirect_with_post_increment_4_s1_ea_indirect_with_pre_increment_1 ATTRIBUTE_UNUSED = {
30301 +  32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } }
30302 +};
30303 +
30304 +static const CGEN_IFMT ifmt_lea_1_d_indirect_with_pre_increment_4_s1_ea_indirect_with_pre_increment_1 ATTRIBUTE_UNUSED = {
30305 +  32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } }
30306 +};
30307 +
30308 +static const CGEN_IFMT ifmt_cmpi_s1_direct ATTRIBUTE_UNUSED = {
30309 +  32, 32, 0xf8000700, { { F (F_OP1) }, { F (F_IMM16_1) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } }
30310 +};
30311 +
30312 +static const CGEN_IFMT ifmt_cmpi_s1_immediate ATTRIBUTE_UNUSED = {
30313 +  32, 32, 0xf8000700, { { F (F_OP1) }, { F (F_IMM16_1) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } }
30314 +};
30315 +
30316 +static const CGEN_IFMT ifmt_cmpi_s1_indirect_with_index_2 ATTRIBUTE_UNUSED = {
30317 +  32, 32, 0xf8000700, { { F (F_OP1) }, { F (F_IMM16_1) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
30318 +};
30319 +
30320 +static const CGEN_IFMT ifmt_cmpi_s1_indirect_with_offset_2 ATTRIBUTE_UNUSED = {
30321 +  32, 32, 0xf8000400, { { F (F_OP1) }, { F (F_IMM16_1) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } }
30322 +};
30323 +
30324 +static const CGEN_IFMT ifmt_cmpi_s1_indirect_2 ATTRIBUTE_UNUSED = {
30325 +  32, 32, 0xf800071f, { { F (F_OP1) }, { F (F_IMM16_1) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } }
30326 +};
30327 +
30328 +static const CGEN_IFMT ifmt_cmpi_s1_indirect_with_post_increment_2 ATTRIBUTE_UNUSED = {
30329 +  32, 32, 0xf8000710, { { F (F_OP1) }, { F (F_IMM16_1) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } }
30330 +};
30331 +
30332 +static const CGEN_IFMT ifmt_cmpi_s1_indirect_with_pre_increment_2 ATTRIBUTE_UNUSED = {
30333 +  32, 32, 0xf8000710, { { F (F_OP1) }, { F (F_IMM16_1) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } }
30334 +};
30335 +
30336 +static const CGEN_IFMT ifmt_pxadds_u_d_direct_s1_direct ATTRIBUTE_UNUSED = {
30337 +  32, 32, 0xff008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } }
30338 +};
30339 +
30340 +static const CGEN_IFMT ifmt_pxadds_u_d_immediate_2_s1_direct ATTRIBUTE_UNUSED = {
30341 +  32, 32, 0xff008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } }
30342 +};
30343 +
30344 +static const CGEN_IFMT ifmt_pxadds_u_d_indirect_with_index_2_s1_direct ATTRIBUTE_UNUSED = {
30345 +  32, 32, 0xff008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } }
30346 +};
30347 +
30348 +static const CGEN_IFMT ifmt_pxadds_u_d_indirect_with_offset_2_s1_direct ATTRIBUTE_UNUSED = {
30349 +  32, 32, 0xfc008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } }
30350 +};
30351 +
30352 +static const CGEN_IFMT ifmt_pxadds_u_d_indirect_2_s1_direct ATTRIBUTE_UNUSED = {
30353 +  32, 32, 0xff1f8700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } }
30354 +};
30355 +
30356 +static const CGEN_IFMT ifmt_pxadds_u_d_indirect_with_post_increment_2_s1_direct ATTRIBUTE_UNUSED = {
30357 +  32, 32, 0xff108700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } }
30358 +};
30359 +
30360 +static const CGEN_IFMT ifmt_pxadds_u_d_indirect_with_pre_increment_2_s1_direct ATTRIBUTE_UNUSED = {
30361 +  32, 32, 0xff108700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } }
30362 +};
30363 +
30364 +static const CGEN_IFMT ifmt_pxadds_u_d_direct_s1_immediate ATTRIBUTE_UNUSED = {
30365 +  32, 32, 0xff008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } }
30366 +};
30367 +
30368 +static const CGEN_IFMT ifmt_pxadds_u_d_immediate_2_s1_immediate ATTRIBUTE_UNUSED = {
30369 +  32, 32, 0xff008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } }
30370 +};
30371 +
30372 +static const CGEN_IFMT ifmt_pxadds_u_d_indirect_with_index_2_s1_immediate ATTRIBUTE_UNUSED = {
30373 +  32, 32, 0xff008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } }
30374 +};
30375 +
30376 +static const CGEN_IFMT ifmt_pxadds_u_d_indirect_with_offset_2_s1_immediate ATTRIBUTE_UNUSED = {
30377 +  32, 32, 0xfc008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } }
30378 +};
30379 +
30380 +static const CGEN_IFMT ifmt_pxadds_u_d_indirect_2_s1_immediate ATTRIBUTE_UNUSED = {
30381 +  32, 32, 0xff1f8700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } }
30382 +};
30383 +
30384 +static const CGEN_IFMT ifmt_pxadds_u_d_indirect_with_post_increment_2_s1_immediate ATTRIBUTE_UNUSED = {
30385 +  32, 32, 0xff108700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } }
30386 +};
30387 +
30388 +static const CGEN_IFMT ifmt_pxadds_u_d_indirect_with_pre_increment_2_s1_immediate ATTRIBUTE_UNUSED = {
30389 +  32, 32, 0xff108700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } }
30390 +};
30391 +
30392 +static const CGEN_IFMT ifmt_pxadds_u_d_direct_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = {
30393 +  32, 32, 0xff008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
30394 +};
30395 +
30396 +static const CGEN_IFMT ifmt_pxadds_u_d_immediate_2_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = {
30397 +  32, 32, 0xff008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
30398 +};
30399 +
30400 +static const CGEN_IFMT ifmt_pxadds_u_d_indirect_with_index_2_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = {
30401 +  32, 32, 0xff008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
30402 +};
30403 +
30404 +static const CGEN_IFMT ifmt_pxadds_u_d_indirect_with_offset_2_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = {
30405 +  32, 32, 0xfc008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
30406 +};
30407 +
30408 +static const CGEN_IFMT ifmt_pxadds_u_d_indirect_2_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = {
30409 +  32, 32, 0xff1f8700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
30410 +};
30411 +
30412 +static const CGEN_IFMT ifmt_pxadds_u_d_indirect_with_post_increment_2_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = {
30413 +  32, 32, 0xff108700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
30414 +};
30415 +
30416 +static const CGEN_IFMT ifmt_pxadds_u_d_indirect_with_pre_increment_2_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = {
30417 +  32, 32, 0xff108700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
30418 +};
30419 +
30420 +static const CGEN_IFMT ifmt_pxadds_u_d_direct_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = {
30421 +  32, 32, 0xff008400, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
30422 +};
30423 +
30424 +static const CGEN_IFMT ifmt_pxadds_u_d_immediate_2_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = {
30425 +  32, 32, 0xff008400, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
30426 +};
30427 +
30428 +static const CGEN_IFMT ifmt_pxadds_u_d_indirect_with_index_2_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = {
30429 +  32, 32, 0xff008400, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
30430 +};
30431 +
30432 +static const CGEN_IFMT ifmt_pxadds_u_d_indirect_with_offset_2_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = {
30433 +  32, 32, 0xfc008400, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
30434 +};
30435 +
30436 +static const CGEN_IFMT ifmt_pxadds_u_d_indirect_2_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = {
30437 +  32, 32, 0xff1f8400, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
30438 +};
30439 +
30440 +static const CGEN_IFMT ifmt_pxadds_u_d_indirect_with_post_increment_2_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = {
30441 +  32, 32, 0xff108400, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
30442 +};
30443 +
30444 +static const CGEN_IFMT ifmt_pxadds_u_d_indirect_with_pre_increment_2_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = {
30445 +  32, 32, 0xff108400, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
30446 +};
30447 +
30448 +static const CGEN_IFMT ifmt_pxadds_u_d_direct_s1_indirect_4 ATTRIBUTE_UNUSED = {
30449 +  32, 32, 0xff00871f, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
30450 +};
30451 +
30452 +static const CGEN_IFMT ifmt_pxadds_u_d_immediate_2_s1_indirect_4 ATTRIBUTE_UNUSED = {
30453 +  32, 32, 0xff00871f, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
30454 +};
30455 +
30456 +static const CGEN_IFMT ifmt_pxadds_u_d_indirect_with_index_2_s1_indirect_4 ATTRIBUTE_UNUSED = {
30457 +  32, 32, 0xff00871f, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
30458 +};
30459 +
30460 +static const CGEN_IFMT ifmt_pxadds_u_d_indirect_with_offset_2_s1_indirect_4 ATTRIBUTE_UNUSED = {
30461 +  32, 32, 0xfc00871f, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
30462 +};
30463 +
30464 +static const CGEN_IFMT ifmt_pxadds_u_d_indirect_2_s1_indirect_4 ATTRIBUTE_UNUSED = {
30465 +  32, 32, 0xff1f871f, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
30466 +};
30467 +
30468 +static const CGEN_IFMT ifmt_pxadds_u_d_indirect_with_post_increment_2_s1_indirect_4 ATTRIBUTE_UNUSED = {
30469 +  32, 32, 0xff10871f, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
30470 +};
30471 +
30472 +static const CGEN_IFMT ifmt_pxadds_u_d_indirect_with_pre_increment_2_s1_indirect_4 ATTRIBUTE_UNUSED = {
30473 +  32, 32, 0xff10871f, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
30474 +};
30475 +
30476 +static const CGEN_IFMT ifmt_pxadds_u_d_direct_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = {
30477 +  32, 32, 0xff008710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
30478 +};
30479 +
30480 +static const CGEN_IFMT ifmt_pxadds_u_d_immediate_2_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = {
30481 +  32, 32, 0xff008710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
30482 +};
30483 +
30484 +static const CGEN_IFMT ifmt_pxadds_u_d_indirect_with_index_2_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = {
30485 +  32, 32, 0xff008710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
30486 +};
30487 +
30488 +static const CGEN_IFMT ifmt_pxadds_u_d_indirect_with_offset_2_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = {
30489 +  32, 32, 0xfc008710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
30490 +};
30491 +
30492 +static const CGEN_IFMT ifmt_pxadds_u_d_indirect_2_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = {
30493 +  32, 32, 0xff1f8710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
30494 +};
30495 +
30496 +static const CGEN_IFMT ifmt_pxadds_u_d_indirect_with_post_increment_2_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = {
30497 +  32, 32, 0xff108710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
30498 +};
30499 +
30500 +static const CGEN_IFMT ifmt_pxadds_u_d_indirect_with_pre_increment_2_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = {
30501 +  32, 32, 0xff108710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
30502 +};
30503 +
30504 +static const CGEN_IFMT ifmt_pxadds_u_d_direct_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = {
30505 +  32, 32, 0xff008710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
30506 +};
30507 +
30508 +static const CGEN_IFMT ifmt_pxadds_u_d_immediate_2_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = {
30509 +  32, 32, 0xff008710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
30510 +};
30511 +
30512 +static const CGEN_IFMT ifmt_pxadds_u_d_indirect_with_index_2_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = {
30513 +  32, 32, 0xff008710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
30514 +};
30515 +
30516 +static const CGEN_IFMT ifmt_pxadds_u_d_indirect_with_offset_2_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = {
30517 +  32, 32, 0xfc008710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
30518 +};
30519 +
30520 +static const CGEN_IFMT ifmt_pxadds_u_d_indirect_2_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = {
30521 +  32, 32, 0xff1f8710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
30522 +};
30523 +
30524 +static const CGEN_IFMT ifmt_pxadds_u_d_indirect_with_post_increment_2_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = {
30525 +  32, 32, 0xff108710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
30526 +};
30527 +
30528 +static const CGEN_IFMT ifmt_pxadds_u_d_indirect_with_pre_increment_2_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = {
30529 +  32, 32, 0xff108710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
30530 +};
30531 +
30532 +static const CGEN_IFMT ifmt_pxhi_s_s1_direct ATTRIBUTE_UNUSED = {
30533 +  32, 32, 0xffe08700, { { F (F_OP1) }, { F (F_BIT26) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_B15) }, { F (F_S2) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } }
30534 +};
30535 +
30536 +static const CGEN_IFMT ifmt_pxhi_s_s1_immediate ATTRIBUTE_UNUSED = {
30537 +  32, 32, 0xffe08700, { { F (F_OP1) }, { F (F_BIT26) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_B15) }, { F (F_S2) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } }
30538 +};
30539 +
30540 +static const CGEN_IFMT ifmt_pxhi_s_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = {
30541 +  32, 32, 0xffe08700, { { F (F_OP1) }, { F (F_BIT26) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_B15) }, { F (F_S2) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
30542 +};
30543 +
30544 +static const CGEN_IFMT ifmt_pxhi_s_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = {
30545 +  32, 32, 0xffe08400, { { F (F_OP1) }, { F (F_BIT26) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_B15) }, { F (F_S2) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
30546 +};
30547 +
30548 +static const CGEN_IFMT ifmt_pxhi_s_s1_indirect_4 ATTRIBUTE_UNUSED = {
30549 +  32, 32, 0xffe0871f, { { F (F_OP1) }, { F (F_BIT26) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_B15) }, { F (F_S2) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
30550 +};
30551 +
30552 +static const CGEN_IFMT ifmt_pxhi_s_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = {
30553 +  32, 32, 0xffe08710, { { F (F_OP1) }, { F (F_BIT26) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_B15) }, { F (F_S2) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
30554 +};
30555 +
30556 +static const CGEN_IFMT ifmt_pxhi_s_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = {
30557 +  32, 32, 0xffe08710, { { F (F_OP1) }, { F (F_BIT26) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_B15) }, { F (F_S2) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
30558 +};
30559 +
30560 +static const CGEN_IFMT ifmt_pxvi_s_d_immediate_4_s1_direct ATTRIBUTE_UNUSED = {
30561 +  32, 32, 0xff008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } }
30562 +};
30563 +
30564 +static const CGEN_IFMT ifmt_pxvi_s_d_indirect_with_index_4_s1_direct ATTRIBUTE_UNUSED = {
30565 +  32, 32, 0xff008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } }
30566 +};
30567 +
30568 +static const CGEN_IFMT ifmt_pxvi_s_d_indirect_with_offset_4_s1_direct ATTRIBUTE_UNUSED = {
30569 +  32, 32, 0xfc008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } }
30570 +};
30571 +
30572 +static const CGEN_IFMT ifmt_pxvi_s_d_indirect_4_s1_direct ATTRIBUTE_UNUSED = {
30573 +  32, 32, 0xff1f8700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } }
30574 +};
30575 +
30576 +static const CGEN_IFMT ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_direct ATTRIBUTE_UNUSED = {
30577 +  32, 32, 0xff108700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } }
30578 +};
30579 +
30580 +static const CGEN_IFMT ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_direct ATTRIBUTE_UNUSED = {
30581 +  32, 32, 0xff108700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } }
30582 +};
30583 +
30584 +static const CGEN_IFMT ifmt_pxvi_s_d_immediate_4_s1_immediate ATTRIBUTE_UNUSED = {
30585 +  32, 32, 0xff008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } }
30586 +};
30587 +
30588 +static const CGEN_IFMT ifmt_pxvi_s_d_indirect_with_index_4_s1_immediate ATTRIBUTE_UNUSED = {
30589 +  32, 32, 0xff008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } }
30590 +};
30591 +
30592 +static const CGEN_IFMT ifmt_pxvi_s_d_indirect_with_offset_4_s1_immediate ATTRIBUTE_UNUSED = {
30593 +  32, 32, 0xfc008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } }
30594 +};
30595 +
30596 +static const CGEN_IFMT ifmt_pxvi_s_d_indirect_4_s1_immediate ATTRIBUTE_UNUSED = {
30597 +  32, 32, 0xff1f8700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } }
30598 +};
30599 +
30600 +static const CGEN_IFMT ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_immediate ATTRIBUTE_UNUSED = {
30601 +  32, 32, 0xff108700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } }
30602 +};
30603 +
30604 +static const CGEN_IFMT ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_immediate ATTRIBUTE_UNUSED = {
30605 +  32, 32, 0xff108700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } }
30606 +};
30607 +
30608 +static const CGEN_IFMT ifmt_pxvi_s_d_immediate_4_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = {
30609 +  32, 32, 0xff008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
30610 +};
30611 +
30612 +static const CGEN_IFMT ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = {
30613 +  32, 32, 0xff008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
30614 +};
30615 +
30616 +static const CGEN_IFMT ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = {
30617 +  32, 32, 0xfc008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
30618 +};
30619 +
30620 +static const CGEN_IFMT ifmt_pxvi_s_d_indirect_4_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = {
30621 +  32, 32, 0xff1f8700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
30622 +};
30623 +
30624 +static const CGEN_IFMT ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = {
30625 +  32, 32, 0xff108700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
30626 +};
30627 +
30628 +static const CGEN_IFMT ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = {
30629 +  32, 32, 0xff108700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
30630 +};
30631 +
30632 +static const CGEN_IFMT ifmt_pxvi_s_d_immediate_4_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = {
30633 +  32, 32, 0xff008400, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
30634 +};
30635 +
30636 +static const CGEN_IFMT ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = {
30637 +  32, 32, 0xff008400, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
30638 +};
30639 +
30640 +static const CGEN_IFMT ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = {
30641 +  32, 32, 0xfc008400, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
30642 +};
30643 +
30644 +static const CGEN_IFMT ifmt_pxvi_s_d_indirect_4_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = {
30645 +  32, 32, 0xff1f8400, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
30646 +};
30647 +
30648 +static const CGEN_IFMT ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = {
30649 +  32, 32, 0xff108400, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
30650 +};
30651 +
30652 +static const CGEN_IFMT ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = {
30653 +  32, 32, 0xff108400, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
30654 +};
30655 +
30656 +static const CGEN_IFMT ifmt_pxvi_s_d_immediate_4_s1_indirect_4 ATTRIBUTE_UNUSED = {
30657 +  32, 32, 0xff00871f, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
30658 +};
30659 +
30660 +static const CGEN_IFMT ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_4 ATTRIBUTE_UNUSED = {
30661 +  32, 32, 0xff00871f, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
30662 +};
30663 +
30664 +static const CGEN_IFMT ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_4 ATTRIBUTE_UNUSED = {
30665 +  32, 32, 0xfc00871f, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
30666 +};
30667 +
30668 +static const CGEN_IFMT ifmt_pxvi_s_d_indirect_4_s1_indirect_4 ATTRIBUTE_UNUSED = {
30669 +  32, 32, 0xff1f871f, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
30670 +};
30671 +
30672 +static const CGEN_IFMT ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_4 ATTRIBUTE_UNUSED = {
30673 +  32, 32, 0xff10871f, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
30674 +};
30675 +
30676 +static const CGEN_IFMT ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_4 ATTRIBUTE_UNUSED = {
30677 +  32, 32, 0xff10871f, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
30678 +};
30679 +
30680 +static const CGEN_IFMT ifmt_pxvi_s_d_immediate_4_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = {
30681 +  32, 32, 0xff008710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
30682 +};
30683 +
30684 +static const CGEN_IFMT ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = {
30685 +  32, 32, 0xff008710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
30686 +};
30687 +
30688 +static const CGEN_IFMT ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = {
30689 +  32, 32, 0xfc008710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
30690 +};
30691 +
30692 +static const CGEN_IFMT ifmt_pxvi_s_d_indirect_4_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = {
30693 +  32, 32, 0xff1f8710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
30694 +};
30695 +
30696 +static const CGEN_IFMT ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = {
30697 +  32, 32, 0xff108710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
30698 +};
30699 +
30700 +static const CGEN_IFMT ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = {
30701 +  32, 32, 0xff108710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
30702 +};
30703 +
30704 +static const CGEN_IFMT ifmt_pxvi_s_d_immediate_4_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = {
30705 +  32, 32, 0xff008710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
30706 +};
30707 +
30708 +static const CGEN_IFMT ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = {
30709 +  32, 32, 0xff008710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
30710 +};
30711 +
30712 +static const CGEN_IFMT ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = {
30713 +  32, 32, 0xfc008710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
30714 +};
30715 +
30716 +static const CGEN_IFMT ifmt_pxvi_s_d_indirect_4_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = {
30717 +  32, 32, 0xff1f8710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
30718 +};
30719 +
30720 +static const CGEN_IFMT ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = {
30721 +  32, 32, 0xff108710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
30722 +};
30723 +
30724 +static const CGEN_IFMT ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = {
30725 +  32, 32, 0xff108710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_4) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
30726 +};
30727 +
30728 +static const CGEN_IFMT ifmt_pxcnv_t_d_immediate_2_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = {
30729 +  32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
30730 +};
30731 +
30732 +static const CGEN_IFMT ifmt_pxcnv_t_d_indirect_with_index_2_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = {
30733 +  32, 32, 0xff00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
30734 +};
30735 +
30736 +static const CGEN_IFMT ifmt_pxcnv_t_d_indirect_with_offset_2_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = {
30737 +  32, 32, 0xfc00ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
30738 +};
30739 +
30740 +static const CGEN_IFMT ifmt_pxcnv_t_d_indirect_2_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = {
30741 +  32, 32, 0xff1fff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
30742 +};
30743 +
30744 +static const CGEN_IFMT ifmt_pxcnv_t_d_indirect_with_post_increment_2_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = {
30745 +  32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
30746 +};
30747 +
30748 +static const CGEN_IFMT ifmt_pxcnv_t_d_indirect_with_pre_increment_2_s1_indirect_with_index_4 ATTRIBUTE_UNUSED = {
30749 +  32, 32, 0xff10ff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
30750 +};
30751 +
30752 +static const CGEN_IFMT ifmt_pxcnv_t_d_immediate_2_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = {
30753 +  32, 32, 0xff00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
30754 +};
30755 +
30756 +static const CGEN_IFMT ifmt_pxcnv_t_d_indirect_with_index_2_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = {
30757 +  32, 32, 0xff00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
30758 +};
30759 +
30760 +static const CGEN_IFMT ifmt_pxcnv_t_d_indirect_with_offset_2_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = {
30761 +  32, 32, 0xfc00fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
30762 +};
30763 +
30764 +static const CGEN_IFMT ifmt_pxcnv_t_d_indirect_2_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = {
30765 +  32, 32, 0xff1ffc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
30766 +};
30767 +
30768 +static const CGEN_IFMT ifmt_pxcnv_t_d_indirect_with_post_increment_2_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = {
30769 +  32, 32, 0xff10fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
30770 +};
30771 +
30772 +static const CGEN_IFMT ifmt_pxcnv_t_d_indirect_with_pre_increment_2_s1_indirect_with_offset_4 ATTRIBUTE_UNUSED = {
30773 +  32, 32, 0xff10fc00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
30774 +};
30775 +
30776 +static const CGEN_IFMT ifmt_pxcnv_t_d_immediate_2_s1_indirect_4 ATTRIBUTE_UNUSED = {
30777 +  32, 32, 0xff00ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
30778 +};
30779 +
30780 +static const CGEN_IFMT ifmt_pxcnv_t_d_indirect_with_index_2_s1_indirect_4 ATTRIBUTE_UNUSED = {
30781 +  32, 32, 0xff00ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
30782 +};
30783 +
30784 +static const CGEN_IFMT ifmt_pxcnv_t_d_indirect_with_offset_2_s1_indirect_4 ATTRIBUTE_UNUSED = {
30785 +  32, 32, 0xfc00ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
30786 +};
30787 +
30788 +static const CGEN_IFMT ifmt_pxcnv_t_d_indirect_2_s1_indirect_4 ATTRIBUTE_UNUSED = {
30789 +  32, 32, 0xff1fff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
30790 +};
30791 +
30792 +static const CGEN_IFMT ifmt_pxcnv_t_d_indirect_with_post_increment_2_s1_indirect_4 ATTRIBUTE_UNUSED = {
30793 +  32, 32, 0xff10ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
30794 +};
30795 +
30796 +static const CGEN_IFMT ifmt_pxcnv_t_d_indirect_with_pre_increment_2_s1_indirect_4 ATTRIBUTE_UNUSED = {
30797 +  32, 32, 0xff10ff1f, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_4) }, { F (F_S1_AN) }, { 0 } }
30798 +};
30799 +
30800 +static const CGEN_IFMT ifmt_pxcnv_t_d_immediate_2_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = {
30801 +  32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
30802 +};
30803 +
30804 +static const CGEN_IFMT ifmt_pxcnv_t_d_indirect_with_index_2_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = {
30805 +  32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
30806 +};
30807 +
30808 +static const CGEN_IFMT ifmt_pxcnv_t_d_indirect_with_offset_2_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = {
30809 +  32, 32, 0xfc00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
30810 +};
30811 +
30812 +static const CGEN_IFMT ifmt_pxcnv_t_d_indirect_2_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = {
30813 +  32, 32, 0xff1fff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
30814 +};
30815 +
30816 +static const CGEN_IFMT ifmt_pxcnv_t_d_indirect_with_post_increment_2_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = {
30817 +  32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
30818 +};
30819 +
30820 +static const CGEN_IFMT ifmt_pxcnv_t_d_indirect_with_pre_increment_2_s1_indirect_with_post_increment_4 ATTRIBUTE_UNUSED = {
30821 +  32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
30822 +};
30823 +
30824 +static const CGEN_IFMT ifmt_pxcnv_t_d_immediate_2_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = {
30825 +  32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
30826 +};
30827 +
30828 +static const CGEN_IFMT ifmt_pxcnv_t_d_indirect_with_index_2_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = {
30829 +  32, 32, 0xff00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
30830 +};
30831 +
30832 +static const CGEN_IFMT ifmt_pxcnv_t_d_indirect_with_offset_2_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = {
30833 +  32, 32, 0xfc00ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
30834 +};
30835 +
30836 +static const CGEN_IFMT ifmt_pxcnv_t_d_indirect_2_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = {
30837 +  32, 32, 0xff1fff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
30838 +};
30839 +
30840 +static const CGEN_IFMT ifmt_pxcnv_t_d_indirect_with_post_increment_2_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = {
30841 +  32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
30842 +};
30843 +
30844 +static const CGEN_IFMT ifmt_pxcnv_t_d_indirect_with_pre_increment_2_s1_indirect_with_pre_increment_4 ATTRIBUTE_UNUSED = {
30845 +  32, 32, 0xff10ff10, { { F (F_OP1) }, { F (F_OP2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_4) }, { F (F_S1_AN) }, { 0 } }
30846 +};
30847 +
30848 +static const CGEN_IFMT ifmt_sub_1_d_immediate_1_s1_direct ATTRIBUTE_UNUSED = {
30849 +  32, 32, 0xff008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } }
30850 +};
30851 +
30852 +static const CGEN_IFMT ifmt_sub_1_d_indirect_with_index_1_s1_direct ATTRIBUTE_UNUSED = {
30853 +  32, 32, 0xff008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } }
30854 +};
30855 +
30856 +static const CGEN_IFMT ifmt_sub_1_d_indirect_with_offset_1_s1_direct ATTRIBUTE_UNUSED = {
30857 +  32, 32, 0xfc008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } }
30858 +};
30859 +
30860 +static const CGEN_IFMT ifmt_sub_1_d_indirect_1_s1_direct ATTRIBUTE_UNUSED = {
30861 +  32, 32, 0xff1f8700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } }
30862 +};
30863 +
30864 +static const CGEN_IFMT ifmt_sub_1_d_indirect_with_post_increment_1_s1_direct ATTRIBUTE_UNUSED = {
30865 +  32, 32, 0xff108700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } }
30866 +};
30867 +
30868 +static const CGEN_IFMT ifmt_sub_1_d_indirect_with_pre_increment_1_s1_direct ATTRIBUTE_UNUSED = {
30869 +  32, 32, 0xff108700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_DIRECT) }, { 0 } }
30870 +};
30871 +
30872 +static const CGEN_IFMT ifmt_sub_1_d_immediate_1_s1_immediate ATTRIBUTE_UNUSED = {
30873 +  32, 32, 0xff008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } }
30874 +};
30875 +
30876 +static const CGEN_IFMT ifmt_sub_1_d_indirect_with_index_1_s1_immediate ATTRIBUTE_UNUSED = {
30877 +  32, 32, 0xff008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } }
30878 +};
30879 +
30880 +static const CGEN_IFMT ifmt_sub_1_d_indirect_with_offset_1_s1_immediate ATTRIBUTE_UNUSED = {
30881 +  32, 32, 0xfc008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } }
30882 +};
30883 +
30884 +static const CGEN_IFMT ifmt_sub_1_d_indirect_1_s1_immediate ATTRIBUTE_UNUSED = {
30885 +  32, 32, 0xff1f8700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } }
30886 +};
30887 +
30888 +static const CGEN_IFMT ifmt_sub_1_d_indirect_with_post_increment_1_s1_immediate ATTRIBUTE_UNUSED = {
30889 +  32, 32, 0xff108700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } }
30890 +};
30891 +
30892 +static const CGEN_IFMT ifmt_sub_1_d_indirect_with_pre_increment_1_s1_immediate ATTRIBUTE_UNUSED = {
30893 +  32, 32, 0xff108700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_IMM8) }, { 0 } }
30894 +};
30895 +
30896 +static const CGEN_IFMT ifmt_sub_1_d_direct_s1_indirect_with_index_1 ATTRIBUTE_UNUSED = {
30897 +  32, 32, 0xff008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
30898 +};
30899 +
30900 +static const CGEN_IFMT ifmt_sub_1_d_immediate_1_s1_indirect_with_index_1 ATTRIBUTE_UNUSED = {
30901 +  32, 32, 0xff008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
30902 +};
30903 +
30904 +static const CGEN_IFMT ifmt_sub_1_d_indirect_with_index_1_s1_indirect_with_index_1 ATTRIBUTE_UNUSED = {
30905 +  32, 32, 0xff008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
30906 +};
30907 +
30908 +static const CGEN_IFMT ifmt_sub_1_d_indirect_with_offset_1_s1_indirect_with_index_1 ATTRIBUTE_UNUSED = {
30909 +  32, 32, 0xfc008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
30910 +};
30911 +
30912 +static const CGEN_IFMT ifmt_sub_1_d_indirect_1_s1_indirect_with_index_1 ATTRIBUTE_UNUSED = {
30913 +  32, 32, 0xff1f8700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
30914 +};
30915 +
30916 +static const CGEN_IFMT ifmt_sub_1_d_indirect_with_post_increment_1_s1_indirect_with_index_1 ATTRIBUTE_UNUSED = {
30917 +  32, 32, 0xff108700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
30918 +};
30919 +
30920 +static const CGEN_IFMT ifmt_sub_1_d_indirect_with_pre_increment_1_s1_indirect_with_index_1 ATTRIBUTE_UNUSED = {
30921 +  32, 32, 0xff108700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
30922 +};
30923 +
30924 +static const CGEN_IFMT ifmt_sub_1_d_direct_s1_indirect_with_offset_1 ATTRIBUTE_UNUSED = {
30925 +  32, 32, 0xff008400, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } }
30926 +};
30927 +
30928 +static const CGEN_IFMT ifmt_sub_1_d_immediate_1_s1_indirect_with_offset_1 ATTRIBUTE_UNUSED = {
30929 +  32, 32, 0xff008400, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } }
30930 +};
30931 +
30932 +static const CGEN_IFMT ifmt_sub_1_d_indirect_with_index_1_s1_indirect_with_offset_1 ATTRIBUTE_UNUSED = {
30933 +  32, 32, 0xff008400, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } }
30934 +};
30935 +
30936 +static const CGEN_IFMT ifmt_sub_1_d_indirect_with_offset_1_s1_indirect_with_offset_1 ATTRIBUTE_UNUSED = {
30937 +  32, 32, 0xfc008400, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } }
30938 +};
30939 +
30940 +static const CGEN_IFMT ifmt_sub_1_d_indirect_1_s1_indirect_with_offset_1 ATTRIBUTE_UNUSED = {
30941 +  32, 32, 0xff1f8400, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } }
30942 +};
30943 +
30944 +static const CGEN_IFMT ifmt_sub_1_d_indirect_with_post_increment_1_s1_indirect_with_offset_1 ATTRIBUTE_UNUSED = {
30945 +  32, 32, 0xff108400, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } }
30946 +};
30947 +
30948 +static const CGEN_IFMT ifmt_sub_1_d_indirect_with_pre_increment_1_s1_indirect_with_offset_1 ATTRIBUTE_UNUSED = {
30949 +  32, 32, 0xff108400, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } }
30950 +};
30951 +
30952 +static const CGEN_IFMT ifmt_sub_1_d_direct_s1_indirect_1 ATTRIBUTE_UNUSED = {
30953 +  32, 32, 0xff00871f, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } }
30954 +};
30955 +
30956 +static const CGEN_IFMT ifmt_sub_1_d_immediate_1_s1_indirect_1 ATTRIBUTE_UNUSED = {
30957 +  32, 32, 0xff00871f, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } }
30958 +};
30959 +
30960 +static const CGEN_IFMT ifmt_sub_1_d_indirect_with_index_1_s1_indirect_1 ATTRIBUTE_UNUSED = {
30961 +  32, 32, 0xff00871f, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } }
30962 +};
30963 +
30964 +static const CGEN_IFMT ifmt_sub_1_d_indirect_with_offset_1_s1_indirect_1 ATTRIBUTE_UNUSED = {
30965 +  32, 32, 0xfc00871f, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } }
30966 +};
30967 +
30968 +static const CGEN_IFMT ifmt_sub_1_d_indirect_1_s1_indirect_1 ATTRIBUTE_UNUSED = {
30969 +  32, 32, 0xff1f871f, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } }
30970 +};
30971 +
30972 +static const CGEN_IFMT ifmt_sub_1_d_indirect_with_post_increment_1_s1_indirect_1 ATTRIBUTE_UNUSED = {
30973 +  32, 32, 0xff10871f, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } }
30974 +};
30975 +
30976 +static const CGEN_IFMT ifmt_sub_1_d_indirect_with_pre_increment_1_s1_indirect_1 ATTRIBUTE_UNUSED = {
30977 +  32, 32, 0xff10871f, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_1) }, { F (F_S1_AN) }, { 0 } }
30978 +};
30979 +
30980 +static const CGEN_IFMT ifmt_sub_1_d_direct_s1_indirect_with_post_increment_1 ATTRIBUTE_UNUSED = {
30981 +  32, 32, 0xff008710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } }
30982 +};
30983 +
30984 +static const CGEN_IFMT ifmt_sub_1_d_immediate_1_s1_indirect_with_post_increment_1 ATTRIBUTE_UNUSED = {
30985 +  32, 32, 0xff008710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } }
30986 +};
30987 +
30988 +static const CGEN_IFMT ifmt_sub_1_d_indirect_with_index_1_s1_indirect_with_post_increment_1 ATTRIBUTE_UNUSED = {
30989 +  32, 32, 0xff008710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } }
30990 +};
30991 +
30992 +static const CGEN_IFMT ifmt_sub_1_d_indirect_with_offset_1_s1_indirect_with_post_increment_1 ATTRIBUTE_UNUSED = {
30993 +  32, 32, 0xfc008710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } }
30994 +};
30995 +
30996 +static const CGEN_IFMT ifmt_sub_1_d_indirect_1_s1_indirect_with_post_increment_1 ATTRIBUTE_UNUSED = {
30997 +  32, 32, 0xff1f8710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } }
30998 +};
30999 +
31000 +static const CGEN_IFMT ifmt_sub_1_d_indirect_with_post_increment_1_s1_indirect_with_post_increment_1 ATTRIBUTE_UNUSED = {
31001 +  32, 32, 0xff108710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } }
31002 +};
31003 +
31004 +static const CGEN_IFMT ifmt_sub_1_d_indirect_with_pre_increment_1_s1_indirect_with_post_increment_1 ATTRIBUTE_UNUSED = {
31005 +  32, 32, 0xff108710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } }
31006 +};
31007 +
31008 +static const CGEN_IFMT ifmt_sub_1_d_direct_s1_indirect_with_pre_increment_1 ATTRIBUTE_UNUSED = {
31009 +  32, 32, 0xff008710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } }
31010 +};
31011 +
31012 +static const CGEN_IFMT ifmt_sub_1_d_immediate_1_s1_indirect_with_pre_increment_1 ATTRIBUTE_UNUSED = {
31013 +  32, 32, 0xff008710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } }
31014 +};
31015 +
31016 +static const CGEN_IFMT ifmt_sub_1_d_indirect_with_index_1_s1_indirect_with_pre_increment_1 ATTRIBUTE_UNUSED = {
31017 +  32, 32, 0xff008710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } }
31018 +};
31019 +
31020 +static const CGEN_IFMT ifmt_sub_1_d_indirect_with_offset_1_s1_indirect_with_pre_increment_1 ATTRIBUTE_UNUSED = {
31021 +  32, 32, 0xfc008710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } }
31022 +};
31023 +
31024 +static const CGEN_IFMT ifmt_sub_1_d_indirect_1_s1_indirect_with_pre_increment_1 ATTRIBUTE_UNUSED = {
31025 +  32, 32, 0xff1f8710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } }
31026 +};
31027 +
31028 +static const CGEN_IFMT ifmt_sub_1_d_indirect_with_post_increment_1_s1_indirect_with_pre_increment_1 ATTRIBUTE_UNUSED = {
31029 +  32, 32, 0xff108710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } }
31030 +};
31031 +
31032 +static const CGEN_IFMT ifmt_sub_1_d_indirect_with_pre_increment_1_s1_indirect_with_pre_increment_1 ATTRIBUTE_UNUSED = {
31033 +  32, 32, 0xff108710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_1) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_1) }, { F (F_S1_AN) }, { 0 } }
31034 +};
31035 +
31036 +static const CGEN_IFMT ifmt_sub_2_d_direct_s1_indirect_with_index_2 ATTRIBUTE_UNUSED = {
31037 +  32, 32, 0xff008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
31038 +};
31039 +
31040 +static const CGEN_IFMT ifmt_sub_2_d_immediate_2_s1_indirect_with_index_2 ATTRIBUTE_UNUSED = {
31041 +  32, 32, 0xff008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
31042 +};
31043 +
31044 +static const CGEN_IFMT ifmt_sub_2_d_indirect_with_index_2_s1_indirect_with_index_2 ATTRIBUTE_UNUSED = {
31045 +  32, 32, 0xff008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
31046 +};
31047 +
31048 +static const CGEN_IFMT ifmt_sub_2_d_indirect_with_offset_2_s1_indirect_with_index_2 ATTRIBUTE_UNUSED = {
31049 +  32, 32, 0xfc008700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
31050 +};
31051 +
31052 +static const CGEN_IFMT ifmt_sub_2_d_indirect_2_s1_indirect_with_index_2 ATTRIBUTE_UNUSED = {
31053 +  32, 32, 0xff1f8700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
31054 +};
31055 +
31056 +static const CGEN_IFMT ifmt_sub_2_d_indirect_with_post_increment_2_s1_indirect_with_index_2 ATTRIBUTE_UNUSED = {
31057 +  32, 32, 0xff108700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
31058 +};
31059 +
31060 +static const CGEN_IFMT ifmt_sub_2_d_indirect_with_pre_increment_2_s1_indirect_with_index_2 ATTRIBUTE_UNUSED = {
31061 +  32, 32, 0xff108700, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_R) }, { F (F_S1_AN) }, { 0 } }
31062 +};
31063 +
31064 +static const CGEN_IFMT ifmt_sub_2_d_direct_s1_indirect_with_offset_2 ATTRIBUTE_UNUSED = {
31065 +  32, 32, 0xff008400, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } }
31066 +};
31067 +
31068 +static const CGEN_IFMT ifmt_sub_2_d_immediate_2_s1_indirect_with_offset_2 ATTRIBUTE_UNUSED = {
31069 +  32, 32, 0xff008400, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } }
31070 +};
31071 +
31072 +static const CGEN_IFMT ifmt_sub_2_d_indirect_with_index_2_s1_indirect_with_offset_2 ATTRIBUTE_UNUSED = {
31073 +  32, 32, 0xff008400, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } }
31074 +};
31075 +
31076 +static const CGEN_IFMT ifmt_sub_2_d_indirect_with_offset_2_s1_indirect_with_offset_2 ATTRIBUTE_UNUSED = {
31077 +  32, 32, 0xfc008400, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } }
31078 +};
31079 +
31080 +static const CGEN_IFMT ifmt_sub_2_d_indirect_2_s1_indirect_with_offset_2 ATTRIBUTE_UNUSED = {
31081 +  32, 32, 0xff1f8400, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } }
31082 +};
31083 +
31084 +static const CGEN_IFMT ifmt_sub_2_d_indirect_with_post_increment_2_s1_indirect_with_offset_2 ATTRIBUTE_UNUSED = {
31085 +  32, 32, 0xff108400, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } }
31086 +};
31087 +
31088 +static const CGEN_IFMT ifmt_sub_2_d_indirect_with_pre_increment_2_s1_indirect_with_offset_2 ATTRIBUTE_UNUSED = {
31089 +  32, 32, 0xff108400, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } }
31090 +};
31091 +
31092 +static const CGEN_IFMT ifmt_sub_2_d_direct_s1_indirect_2 ATTRIBUTE_UNUSED = {
31093 +  32, 32, 0xff00871f, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } }
31094 +};
31095 +
31096 +static const CGEN_IFMT ifmt_sub_2_d_immediate_2_s1_indirect_2 ATTRIBUTE_UNUSED = {
31097 +  32, 32, 0xff00871f, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } }
31098 +};
31099 +
31100 +static const CGEN_IFMT ifmt_sub_2_d_indirect_with_index_2_s1_indirect_2 ATTRIBUTE_UNUSED = {
31101 +  32, 32, 0xff00871f, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } }
31102 +};
31103 +
31104 +static const CGEN_IFMT ifmt_sub_2_d_indirect_with_offset_2_s1_indirect_2 ATTRIBUTE_UNUSED = {
31105 +  32, 32, 0xfc00871f, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } }
31106 +};
31107 +
31108 +static const CGEN_IFMT ifmt_sub_2_d_indirect_2_s1_indirect_2 ATTRIBUTE_UNUSED = {
31109 +  32, 32, 0xff1f871f, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } }
31110 +};
31111 +
31112 +static const CGEN_IFMT ifmt_sub_2_d_indirect_with_post_increment_2_s1_indirect_2 ATTRIBUTE_UNUSED = {
31113 +  32, 32, 0xff10871f, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } }
31114 +};
31115 +
31116 +static const CGEN_IFMT ifmt_sub_2_d_indirect_with_pre_increment_2_s1_indirect_2 ATTRIBUTE_UNUSED = {
31117 +  32, 32, 0xff10871f, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_IMM7_2) }, { F (F_S1_AN) }, { 0 } }
31118 +};
31119 +
31120 +static const CGEN_IFMT ifmt_sub_2_d_direct_s1_indirect_with_post_increment_2 ATTRIBUTE_UNUSED = {
31121 +  32, 32, 0xff008710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } }
31122 +};
31123 +
31124 +static const CGEN_IFMT ifmt_sub_2_d_immediate_2_s1_indirect_with_post_increment_2 ATTRIBUTE_UNUSED = {
31125 +  32, 32, 0xff008710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } }
31126 +};
31127 +
31128 +static const CGEN_IFMT ifmt_sub_2_d_indirect_with_index_2_s1_indirect_with_post_increment_2 ATTRIBUTE_UNUSED = {
31129 +  32, 32, 0xff008710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } }
31130 +};
31131 +
31132 +static const CGEN_IFMT ifmt_sub_2_d_indirect_with_offset_2_s1_indirect_with_post_increment_2 ATTRIBUTE_UNUSED = {
31133 +  32, 32, 0xfc008710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } }
31134 +};
31135 +
31136 +static const CGEN_IFMT ifmt_sub_2_d_indirect_2_s1_indirect_with_post_increment_2 ATTRIBUTE_UNUSED = {
31137 +  32, 32, 0xff1f8710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } }
31138 +};
31139 +
31140 +static const CGEN_IFMT ifmt_sub_2_d_indirect_with_post_increment_2_s1_indirect_with_post_increment_2 ATTRIBUTE_UNUSED = {
31141 +  32, 32, 0xff108710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } }
31142 +};
31143 +
31144 +static const CGEN_IFMT ifmt_sub_2_d_indirect_with_pre_increment_2_s1_indirect_with_post_increment_2 ATTRIBUTE_UNUSED = {
31145 +  32, 32, 0xff108710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } }
31146 +};
31147 +
31148 +static const CGEN_IFMT ifmt_sub_2_d_direct_s1_indirect_with_pre_increment_2 ATTRIBUTE_UNUSED = {
31149 +  32, 32, 0xff008710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_DIRECT) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } }
31150 +};
31151 +
31152 +static const CGEN_IFMT ifmt_sub_2_d_immediate_2_s1_indirect_with_pre_increment_2 ATTRIBUTE_UNUSED = {
31153 +  32, 32, 0xff008710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_IMM8) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } }
31154 +};
31155 +
31156 +static const CGEN_IFMT ifmt_sub_2_d_indirect_with_index_2_s1_indirect_with_pre_increment_2 ATTRIBUTE_UNUSED = {
31157 +  32, 32, 0xff008710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_R) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } }
31158 +};
31159 +
31160 +static const CGEN_IFMT ifmt_sub_2_d_indirect_with_offset_2_s1_indirect_with_pre_increment_2 ATTRIBUTE_UNUSED = {
31161 +  32, 32, 0xfc008710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } }
31162 +};
31163 +
31164 +static const CGEN_IFMT ifmt_sub_2_d_indirect_2_s1_indirect_with_pre_increment_2 ATTRIBUTE_UNUSED = {
31165 +  32, 32, 0xff1f8710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_IMM7_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } }
31166 +};
31167 +
31168 +static const CGEN_IFMT ifmt_sub_2_d_indirect_with_post_increment_2_s1_indirect_with_pre_increment_2 ATTRIBUTE_UNUSED = {
31169 +  32, 32, 0xff108710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } }
31170 +};
31171 +
31172 +static const CGEN_IFMT ifmt_sub_2_d_indirect_with_pre_increment_2_s1_indirect_with_pre_increment_2 ATTRIBUTE_UNUSED = {
31173 +  32, 32, 0xff108710, { { F (F_OP1) }, { F (F_B15) }, { F (F_S2) }, { F (F_D_BIT10) }, { F (F_D_TYPE) }, { F (F_D_M) }, { F (F_D_I4_2) }, { F (F_D_AN) }, { F (F_S1_BIT10) }, { F (F_S1_TYPE) }, { F (F_S1_M) }, { F (F_S1_I4_2) }, { F (F_S1_AN) }, { 0 } }
31174 +};
31175 +
31176 +static const CGEN_IFMT ifmt_moveai ATTRIBUTE_UNUSED = {
31177 +  32, 32, 0xf8000000, { { F (F_OP1) }, { F (F_AN) }, { F (F_IMM24) }, { 0 } }
31178 +};
31179 +
31180 +static const CGEN_IFMT ifmt_nop_insn ATTRIBUTE_UNUSED = {
31181 +  32, 32, 0xffffffff, { { F (F_OP1) }, { F (F_D) }, { F (F_IMM16_2) }, { 0 } }
31182 +};
31183 +
31184 +static const CGEN_IFMT ifmt_jmpcc ATTRIBUTE_UNUSED = {
31185 +  32, 32, 0xf8000000, { { F (F_OP1) }, { F (F_COND) }, { F (F_P) }, { F (F_C) }, { F (F_O21) }, { 0 } }
31186 +};
31187 +
31188 +static const CGEN_IFMT ifmt_call ATTRIBUTE_UNUSED = {
31189 +  32, 32, 0xf8000000, { { F (F_OP1) }, { F (F_AN) }, { F (F_O24) }, { 0 } }
31190 +};
31191 +
31192 +static const CGEN_IFMT ifmt_calli ATTRIBUTE_UNUSED = {
31193 +  32, 32, 0xf800f800, { { F (F_OP1) }, { F (F_AN) }, { F (F_BIT5) }, { F (F_AM) }, { F (F_O16) }, { 0 } }
31194 +};
31195 +
31196 +static const CGEN_IFMT ifmt_suspend ATTRIBUTE_UNUSED = {
31197 +  32, 32, 0xffffffff, { { F (F_OP1) }, { F (F_D) }, { F (F_OP2) }, { F (F_S1) }, { 0 } }
31198 +};
31199 +
31200 +static const CGEN_IFMT ifmt_dsp_clracc ATTRIBUTE_UNUSED = {
31201 +  32, 32, 0xfffeffff, { { F (F_OP1) }, { F (F_BIT26) }, { F (F_OPEXT) }, { F (F_DSP_C) }, { F (F_DSP_T) }, { F (F_DSP_S2_SEL) }, { F (F_DSP_R) }, { F (F_DSP_DESTA) }, { F (F_BIT5) }, { F (F_S1) }, { 0 } }
31202 +};
31203 +
31204 +static const CGEN_IFMT ifmt_unused_00_11 ATTRIBUTE_UNUSED = {
31205 +  32, 32, 0xf800f800, { { F (F_OP1) }, { F (F_D) }, { F (F_OP2) }, { F (F_S1) }, { 0 } }
31206 +};
31207 +
31208 +static const CGEN_IFMT ifmt_unused_02_04 ATTRIBUTE_UNUSED = {
31209 +  32, 32, 0xfbe00000, { { F (F_OP1) }, { F (F_BIT26) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_OP2) }, { F (F_S1) }, { 0 } }
31210 +};
31211 +
31212 +static const CGEN_IFMT ifmt_unused_01 ATTRIBUTE_UNUSED = {
31213 +  32, 32, 0xf8000000, { { F (F_OP1) }, { F (F_D) }, { F (F_OP2) }, { F (F_S1) }, { 0 } }
31214 +};
31215 +
31216 +static const CGEN_IFMT ifmt_unused_DSP_06 ATTRIBUTE_UNUSED = {
31217 +  32, 32, 0xfbe00000, { { F (F_OP1) }, { F (F_BIT26) }, { F (F_OPEXT) }, { F (F_DN) }, { F (F_OP2) }, { F (F_S1) }, { 0 } }
31218 +};
31219 +
31220 +#undef F
31221 +
31222 +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
31223 +#define A(a) (1 << CGEN_INSN_##a)
31224 +#else
31225 +#define A(a) (1 << CGEN_INSN_/**/a)
31226 +#endif
31227 +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
31228 +#define OPERAND(op) UBICOM32_OPERAND_##op
31229 +#else
31230 +#define OPERAND(op) UBICOM32_OPERAND_/**/op
31231 +#endif
31232 +#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
31233 +#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
31234 +
31235 +/* The instruction table.  */
31236 +
31237 +static const CGEN_OPCODE ubicom32_cgen_insn_opcode_table[MAX_INSNS] =
31238 +{
31239 +  /* Special null first entry.
31240 +     A `num' value of zero is thus invalid.
31241 +     Also, the special `invalid' insn resides here.  */
31242 +  { { 0, 0, 0, 0 }, {{0}}, 0, {0}},
31243 +/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},${s1-direct-addr},${dsp-S2-data-reg-addsub} */
31244 +  {
31245 +    { 0, 0, 0, 0 },
31246 +    { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_DATA_REG_ADDSUB), 0 } },
31247 +    & ifmt_dsp_msub_2_s1_direct_dsp_src2_data_reg_addsub2, { 0x36600100 }
31248 +  },
31249 +/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},#${s1-imm8},${dsp-S2-data-reg-addsub} */
31250 +  {
31251 +    { 0, 0, 0, 0 },
31252 +    { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', OP (DSP_S2_DATA_REG_ADDSUB), 0 } },
31253 +    & ifmt_dsp_msub_2_s1_immediate_dsp_src2_data_reg_addsub2, { 0x36600000 }
31254 +  },
31255 +/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-data-reg-addsub} */
31256 +  {
31257 +    { 0, 0, 0, 0 },
31258 +    { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_DATA_REG_ADDSUB), 0 } },
31259 +    & ifmt_dsp_msub_2_s1_indirect_with_index_2_dsp_src2_data_reg_addsub2, { 0x36600300 }
31260 +  },
31261 +/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},${s1-imm7-2}(${s1-An}),${dsp-S2-data-reg-addsub} */
31262 +  {
31263 +    { 0, 0, 0, 0 },
31264 +    { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG_ADDSUB), 0 } },
31265 +    & ifmt_dsp_msub_2_s1_indirect_with_offset_2_dsp_src2_data_reg_addsub2, { 0x36600400 }
31266 +  },
31267 +/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},(${s1-An}),${dsp-S2-data-reg-addsub} */
31268 +  {
31269 +    { 0, 0, 0, 0 },
31270 +    { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG_ADDSUB), 0 } },
31271 +    & ifmt_dsp_msub_2_s1_indirect_2_dsp_src2_data_reg_addsub2, { 0x36600400 }
31272 +  },
31273 +/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},(${s1-An})${s1-i4-2}++,${dsp-S2-data-reg-addsub} */
31274 +  {
31275 +    { 0, 0, 0, 0 },
31276 +    { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (DSP_S2_DATA_REG_ADDSUB), 0 } },
31277 +    & ifmt_dsp_msub_2_s1_indirect_with_post_increment_2_dsp_src2_data_reg_addsub2, { 0x36600200 }
31278 +  },
31279 +/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},${s1-i4-2}(${s1-An})++,${dsp-S2-data-reg-addsub} */
31280 +  {
31281 +    { 0, 0, 0, 0 },
31282 +    { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_DATA_REG_ADDSUB), 0 } },
31283 +    & ifmt_dsp_msub_2_s1_indirect_with_pre_increment_2_dsp_src2_data_reg_addsub2, { 0x36600210 }
31284 +  },
31285 +/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},${s1-direct-addr},${dsp-S2-acc-reg-addsub} */
31286 +  {
31287 +    { 0, 0, 0, 0 },
31288 +    { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_ACC_REG_ADDSUB), 0 } },
31289 +    & ifmt_dsp_msub_2_s1_direct_dsp_src2_reg_acc_reg_addsub, { 0x36640100 }
31290 +  },
31291 +/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},#${s1-imm8},${dsp-S2-acc-reg-addsub} */
31292 +  {
31293 +    { 0, 0, 0, 0 },
31294 +    { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', OP (DSP_S2_ACC_REG_ADDSUB), 0 } },
31295 +    & ifmt_dsp_msub_2_s1_immediate_dsp_src2_reg_acc_reg_addsub, { 0x36640000 }
31296 +  },
31297 +/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-acc-reg-addsub} */
31298 +  {
31299 +    { 0, 0, 0, 0 },
31300 +    { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_ACC_REG_ADDSUB), 0 } },
31301 +    & ifmt_dsp_msub_2_s1_indirect_with_index_2_dsp_src2_reg_acc_reg_addsub, { 0x36640300 }
31302 +  },
31303 +/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},${s1-imm7-2}(${s1-An}),${dsp-S2-acc-reg-addsub} */
31304 +  {
31305 +    { 0, 0, 0, 0 },
31306 +    { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (DSP_S2_ACC_REG_ADDSUB), 0 } },
31307 +    & ifmt_dsp_msub_2_s1_indirect_with_offset_2_dsp_src2_reg_acc_reg_addsub, { 0x36640400 }
31308 +  },
31309 +/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},(${s1-An}),${dsp-S2-acc-reg-addsub} */
31310 +  {
31311 +    { 0, 0, 0, 0 },
31312 +    { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', OP (DSP_S2_ACC_REG_ADDSUB), 0 } },
31313 +    & ifmt_dsp_msub_2_s1_indirect_2_dsp_src2_reg_acc_reg_addsub, { 0x36640400 }
31314 +  },
31315 +/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},(${s1-An})${s1-i4-2}++,${dsp-S2-acc-reg-addsub} */
31316 +  {
31317 +    { 0, 0, 0, 0 },
31318 +    { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (DSP_S2_ACC_REG_ADDSUB), 0 } },
31319 +    & ifmt_dsp_msub_2_s1_indirect_with_post_increment_2_dsp_src2_reg_acc_reg_addsub, { 0x36640200 }
31320 +  },
31321 +/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},${s1-i4-2}(${s1-An})++,${dsp-S2-acc-reg-addsub} */
31322 +  {
31323 +    { 0, 0, 0, 0 },
31324 +    { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_ACC_REG_ADDSUB), 0 } },
31325 +    & ifmt_dsp_msub_2_s1_indirect_with_pre_increment_2_dsp_src2_reg_acc_reg_addsub, { 0x36640210 }
31326 +  },
31327 +/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},${s1-direct-addr},#${bit5-addsub} */
31328 +  {
31329 +    { 0, 0, 0, 0 },
31330 +    { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5_ADDSUB), 0 } },
31331 +    & ifmt_dsp_msub_2_s1_direct_dsp_imm_bit5_addsub2, { 0x32600100 }
31332 +  },
31333 +/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},#${s1-imm8},#${bit5-addsub} */
31334 +  {
31335 +    { 0, 0, 0, 0 },
31336 +    { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5_ADDSUB), 0 } },
31337 +    & ifmt_dsp_msub_2_s1_immediate_dsp_imm_bit5_addsub2, { 0x32600000 }
31338 +  },
31339 +/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},(${s1-An},${s1-r}),#${bit5-addsub} */
31340 +  {
31341 +    { 0, 0, 0, 0 },
31342 +    { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5_ADDSUB), 0 } },
31343 +    & ifmt_dsp_msub_2_s1_indirect_with_index_2_dsp_imm_bit5_addsub2, { 0x32600300 }
31344 +  },
31345 +/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},${s1-imm7-2}(${s1-An}),#${bit5-addsub} */
31346 +  {
31347 +    { 0, 0, 0, 0 },
31348 +    { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', '#', OP (BIT5_ADDSUB), 0 } },
31349 +    & ifmt_dsp_msub_2_s1_indirect_with_offset_2_dsp_imm_bit5_addsub2, { 0x32600400 }
31350 +  },
31351 +/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},(${s1-An}),#${bit5-addsub} */
31352 +  {
31353 +    { 0, 0, 0, 0 },
31354 +    { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5_ADDSUB), 0 } },
31355 +    & ifmt_dsp_msub_2_s1_indirect_2_dsp_imm_bit5_addsub2, { 0x32600400 }
31356 +  },
31357 +/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},(${s1-An})${s1-i4-2}++,#${bit5-addsub} */
31358 +  {
31359 +    { 0, 0, 0, 0 },
31360 +    { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', '#', OP (BIT5_ADDSUB), 0 } },
31361 +    & ifmt_dsp_msub_2_s1_indirect_with_post_increment_2_dsp_imm_bit5_addsub2, { 0x32600200 }
31362 +  },
31363 +/* msub.2${dsp-c}${dsp-t-addsub} ${dsp-destA},${s1-i4-2}(${s1-An})++,#${bit5-addsub} */
31364 +  {
31365 +    { 0, 0, 0, 0 },
31366 +    { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5_ADDSUB), 0 } },
31367 +    & ifmt_dsp_msub_2_s1_indirect_with_pre_increment_2_dsp_imm_bit5_addsub2, { 0x32600210 }
31368 +  },
31369 +/* msub.4${dsp-c} ${dsp-destA},${s1-direct-addr},${dsp-S2-data-reg-addsub} */
31370 +  {
31371 +    { 0, 0, 0, 0 },
31372 +    { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_DATA_REG_ADDSUB), 0 } },
31373 +    & ifmt_dsp_msub_4_s1_direct_dsp_src2_data_reg_addsub, { 0x36400100 }
31374 +  },
31375 +/* msub.4${dsp-c} ${dsp-destA},#${s1-imm8},${dsp-S2-data-reg-addsub} */
31376 +  {
31377 +    { 0, 0, 0, 0 },
31378 +    { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', OP (DSP_S2_DATA_REG_ADDSUB), 0 } },
31379 +    & ifmt_dsp_msub_4_s1_immediate_dsp_src2_data_reg_addsub, { 0x36400000 }
31380 +  },
31381 +/* msub.4${dsp-c} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-data-reg-addsub} */
31382 +  {
31383 +    { 0, 0, 0, 0 },
31384 +    { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_DATA_REG_ADDSUB), 0 } },
31385 +    & ifmt_dsp_msub_4_s1_indirect_with_index_4_dsp_src2_data_reg_addsub, { 0x36400300 }
31386 +  },
31387 +/* msub.4${dsp-c} ${dsp-destA},${s1-imm7-4}(${s1-An}),${dsp-S2-data-reg-addsub} */
31388 +  {
31389 +    { 0, 0, 0, 0 },
31390 +    { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG_ADDSUB), 0 } },
31391 +    & ifmt_dsp_msub_4_s1_indirect_with_offset_4_dsp_src2_data_reg_addsub, { 0x36400400 }
31392 +  },
31393 +/* msub.4${dsp-c} ${dsp-destA},(${s1-An}),${dsp-S2-data-reg-addsub} */
31394 +  {
31395 +    { 0, 0, 0, 0 },
31396 +    { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG_ADDSUB), 0 } },
31397 +    & ifmt_dsp_msub_4_s1_indirect_4_dsp_src2_data_reg_addsub, { 0x36400400 }
31398 +  },
31399 +/* msub.4${dsp-c} ${dsp-destA},(${s1-An})${s1-i4-4}++,${dsp-S2-data-reg-addsub} */
31400 +  {
31401 +    { 0, 0, 0, 0 },
31402 +    { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (DSP_S2_DATA_REG_ADDSUB), 0 } },
31403 +    & ifmt_dsp_msub_4_s1_indirect_with_post_increment_4_dsp_src2_data_reg_addsub, { 0x36400200 }
31404 +  },
31405 +/* msub.4${dsp-c} ${dsp-destA},${s1-i4-4}(${s1-An})++,${dsp-S2-data-reg-addsub} */
31406 +  {
31407 +    { 0, 0, 0, 0 },
31408 +    { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_DATA_REG_ADDSUB), 0 } },
31409 +    & ifmt_dsp_msub_4_s1_indirect_with_pre_increment_4_dsp_src2_data_reg_addsub, { 0x36400210 }
31410 +  },
31411 +/* msub.4${dsp-c} ${dsp-destA},${s1-direct-addr},${dsp-S2-acc-reg-addsub} */
31412 +  {
31413 +    { 0, 0, 0, 0 },
31414 +    { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_ACC_REG_ADDSUB), 0 } },
31415 +    & ifmt_dsp_msub_4_s1_direct_dsp_src2_reg_acc_reg_addsub, { 0x36440100 }
31416 +  },
31417 +/* msub.4${dsp-c} ${dsp-destA},#${s1-imm8},${dsp-S2-acc-reg-addsub} */
31418 +  {
31419 +    { 0, 0, 0, 0 },
31420 +    { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', OP (DSP_S2_ACC_REG_ADDSUB), 0 } },
31421 +    & ifmt_dsp_msub_4_s1_immediate_dsp_src2_reg_acc_reg_addsub, { 0x36440000 }
31422 +  },
31423 +/* msub.4${dsp-c} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-acc-reg-addsub} */
31424 +  {
31425 +    { 0, 0, 0, 0 },
31426 +    { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_ACC_REG_ADDSUB), 0 } },
31427 +    & ifmt_dsp_msub_4_s1_indirect_with_index_4_dsp_src2_reg_acc_reg_addsub, { 0x36440300 }
31428 +  },
31429 +/* msub.4${dsp-c} ${dsp-destA},${s1-imm7-4}(${s1-An}),${dsp-S2-acc-reg-addsub} */
31430 +  {
31431 +    { 0, 0, 0, 0 },
31432 +    { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (DSP_S2_ACC_REG_ADDSUB), 0 } },
31433 +    & ifmt_dsp_msub_4_s1_indirect_with_offset_4_dsp_src2_reg_acc_reg_addsub, { 0x36440400 }
31434 +  },
31435 +/* msub.4${dsp-c} ${dsp-destA},(${s1-An}),${dsp-S2-acc-reg-addsub} */
31436 +  {
31437 +    { 0, 0, 0, 0 },
31438 +    { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', OP (DSP_S2_ACC_REG_ADDSUB), 0 } },
31439 +    & ifmt_dsp_msub_4_s1_indirect_4_dsp_src2_reg_acc_reg_addsub, { 0x36440400 }
31440 +  },
31441 +/* msub.4${dsp-c} ${dsp-destA},(${s1-An})${s1-i4-4}++,${dsp-S2-acc-reg-addsub} */
31442 +  {
31443 +    { 0, 0, 0, 0 },
31444 +    { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (DSP_S2_ACC_REG_ADDSUB), 0 } },
31445 +    & ifmt_dsp_msub_4_s1_indirect_with_post_increment_4_dsp_src2_reg_acc_reg_addsub, { 0x36440200 }
31446 +  },
31447 +/* msub.4${dsp-c} ${dsp-destA},${s1-i4-4}(${s1-An})++,${dsp-S2-acc-reg-addsub} */
31448 +  {
31449 +    { 0, 0, 0, 0 },
31450 +    { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_ACC_REG_ADDSUB), 0 } },
31451 +    & ifmt_dsp_msub_4_s1_indirect_with_pre_increment_4_dsp_src2_reg_acc_reg_addsub, { 0x36440210 }
31452 +  },
31453 +/* msub.4${dsp-c} ${dsp-destA},${s1-direct-addr},#${bit5-addsub} */
31454 +  {
31455 +    { 0, 0, 0, 0 },
31456 +    { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5_ADDSUB), 0 } },
31457 +    & ifmt_dsp_msub_4_s1_direct_dsp_imm_bit5_addsub, { 0x32400100 }
31458 +  },
31459 +/* msub.4${dsp-c} ${dsp-destA},#${s1-imm8},#${bit5-addsub} */
31460 +  {
31461 +    { 0, 0, 0, 0 },
31462 +    { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5_ADDSUB), 0 } },
31463 +    & ifmt_dsp_msub_4_s1_immediate_dsp_imm_bit5_addsub, { 0x32400000 }
31464 +  },
31465 +/* msub.4${dsp-c} ${dsp-destA},(${s1-An},${s1-r}),#${bit5-addsub} */
31466 +  {
31467 +    { 0, 0, 0, 0 },
31468 +    { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5_ADDSUB), 0 } },
31469 +    & ifmt_dsp_msub_4_s1_indirect_with_index_4_dsp_imm_bit5_addsub, { 0x32400300 }
31470 +  },
31471 +/* msub.4${dsp-c} ${dsp-destA},${s1-imm7-4}(${s1-An}),#${bit5-addsub} */
31472 +  {
31473 +    { 0, 0, 0, 0 },
31474 +    { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', '#', OP (BIT5_ADDSUB), 0 } },
31475 +    & ifmt_dsp_msub_4_s1_indirect_with_offset_4_dsp_imm_bit5_addsub, { 0x32400400 }
31476 +  },
31477 +/* msub.4${dsp-c} ${dsp-destA},(${s1-An}),#${bit5-addsub} */
31478 +  {
31479 +    { 0, 0, 0, 0 },
31480 +    { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5_ADDSUB), 0 } },
31481 +    & ifmt_dsp_msub_4_s1_indirect_4_dsp_imm_bit5_addsub, { 0x32400400 }
31482 +  },
31483 +/* msub.4${dsp-c} ${dsp-destA},(${s1-An})${s1-i4-4}++,#${bit5-addsub} */
31484 +  {
31485 +    { 0, 0, 0, 0 },
31486 +    { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', '#', OP (BIT5_ADDSUB), 0 } },
31487 +    & ifmt_dsp_msub_4_s1_indirect_with_post_increment_4_dsp_imm_bit5_addsub, { 0x32400200 }
31488 +  },
31489 +/* msub.4${dsp-c} ${dsp-destA},${s1-i4-4}(${s1-An})++,#${bit5-addsub} */
31490 +  {
31491 +    { 0, 0, 0, 0 },
31492 +    { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5_ADDSUB), 0 } },
31493 +    & ifmt_dsp_msub_4_s1_indirect_with_pre_increment_4_dsp_imm_bit5_addsub, { 0x32400210 }
31494 +  },
31495 +/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},${s1-direct-addr},${dsp-S2-data-reg-addsub} */
31496 +  {
31497 +    { 0, 0, 0, 0 },
31498 +    { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_DATA_REG_ADDSUB), 0 } },
31499 +    & ifmt_dsp_msub_2_s1_direct_dsp_src2_data_reg_addsub2, { 0x36200100 }
31500 +  },
31501 +/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},#${s1-imm8},${dsp-S2-data-reg-addsub} */
31502 +  {
31503 +    { 0, 0, 0, 0 },
31504 +    { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', OP (DSP_S2_DATA_REG_ADDSUB), 0 } },
31505 +    & ifmt_dsp_msub_2_s1_immediate_dsp_src2_data_reg_addsub2, { 0x36200000 }
31506 +  },
31507 +/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-data-reg-addsub} */
31508 +  {
31509 +    { 0, 0, 0, 0 },
31510 +    { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_DATA_REG_ADDSUB), 0 } },
31511 +    & ifmt_dsp_msub_2_s1_indirect_with_index_2_dsp_src2_data_reg_addsub2, { 0x36200300 }
31512 +  },
31513 +/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},${s1-imm7-2}(${s1-An}),${dsp-S2-data-reg-addsub} */
31514 +  {
31515 +    { 0, 0, 0, 0 },
31516 +    { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG_ADDSUB), 0 } },
31517 +    & ifmt_dsp_msub_2_s1_indirect_with_offset_2_dsp_src2_data_reg_addsub2, { 0x36200400 }
31518 +  },
31519 +/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},(${s1-An}),${dsp-S2-data-reg-addsub} */
31520 +  {
31521 +    { 0, 0, 0, 0 },
31522 +    { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG_ADDSUB), 0 } },
31523 +    & ifmt_dsp_msub_2_s1_indirect_2_dsp_src2_data_reg_addsub2, { 0x36200400 }
31524 +  },
31525 +/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},(${s1-An})${s1-i4-2}++,${dsp-S2-data-reg-addsub} */
31526 +  {
31527 +    { 0, 0, 0, 0 },
31528 +    { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (DSP_S2_DATA_REG_ADDSUB), 0 } },
31529 +    & ifmt_dsp_msub_2_s1_indirect_with_post_increment_2_dsp_src2_data_reg_addsub2, { 0x36200200 }
31530 +  },
31531 +/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},${s1-i4-2}(${s1-An})++,${dsp-S2-data-reg-addsub} */
31532 +  {
31533 +    { 0, 0, 0, 0 },
31534 +    { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_DATA_REG_ADDSUB), 0 } },
31535 +    & ifmt_dsp_msub_2_s1_indirect_with_pre_increment_2_dsp_src2_data_reg_addsub2, { 0x36200210 }
31536 +  },
31537 +/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},${s1-direct-addr},${dsp-S2-acc-reg-addsub} */
31538 +  {
31539 +    { 0, 0, 0, 0 },
31540 +    { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_ACC_REG_ADDSUB), 0 } },
31541 +    & ifmt_dsp_msub_2_s1_direct_dsp_src2_reg_acc_reg_addsub, { 0x36240100 }
31542 +  },
31543 +/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},#${s1-imm8},${dsp-S2-acc-reg-addsub} */
31544 +  {
31545 +    { 0, 0, 0, 0 },
31546 +    { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', OP (DSP_S2_ACC_REG_ADDSUB), 0 } },
31547 +    & ifmt_dsp_msub_2_s1_immediate_dsp_src2_reg_acc_reg_addsub, { 0x36240000 }
31548 +  },
31549 +/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-acc-reg-addsub} */
31550 +  {
31551 +    { 0, 0, 0, 0 },
31552 +    { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_ACC_REG_ADDSUB), 0 } },
31553 +    & ifmt_dsp_msub_2_s1_indirect_with_index_2_dsp_src2_reg_acc_reg_addsub, { 0x36240300 }
31554 +  },
31555 +/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},${s1-imm7-2}(${s1-An}),${dsp-S2-acc-reg-addsub} */
31556 +  {
31557 +    { 0, 0, 0, 0 },
31558 +    { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (DSP_S2_ACC_REG_ADDSUB), 0 } },
31559 +    & ifmt_dsp_msub_2_s1_indirect_with_offset_2_dsp_src2_reg_acc_reg_addsub, { 0x36240400 }
31560 +  },
31561 +/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},(${s1-An}),${dsp-S2-acc-reg-addsub} */
31562 +  {
31563 +    { 0, 0, 0, 0 },
31564 +    { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', OP (DSP_S2_ACC_REG_ADDSUB), 0 } },
31565 +    & ifmt_dsp_msub_2_s1_indirect_2_dsp_src2_reg_acc_reg_addsub, { 0x36240400 }
31566 +  },
31567 +/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},(${s1-An})${s1-i4-2}++,${dsp-S2-acc-reg-addsub} */
31568 +  {
31569 +    { 0, 0, 0, 0 },
31570 +    { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (DSP_S2_ACC_REG_ADDSUB), 0 } },
31571 +    & ifmt_dsp_msub_2_s1_indirect_with_post_increment_2_dsp_src2_reg_acc_reg_addsub, { 0x36240200 }
31572 +  },
31573 +/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},${s1-i4-2}(${s1-An})++,${dsp-S2-acc-reg-addsub} */
31574 +  {
31575 +    { 0, 0, 0, 0 },
31576 +    { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_ACC_REG_ADDSUB), 0 } },
31577 +    & ifmt_dsp_msub_2_s1_indirect_with_pre_increment_2_dsp_src2_reg_acc_reg_addsub, { 0x36240210 }
31578 +  },
31579 +/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},${s1-direct-addr},#${bit5-addsub} */
31580 +  {
31581 +    { 0, 0, 0, 0 },
31582 +    { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5_ADDSUB), 0 } },
31583 +    & ifmt_dsp_msub_2_s1_direct_dsp_imm_bit5_addsub2, { 0x32200100 }
31584 +  },
31585 +/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},#${s1-imm8},#${bit5-addsub} */
31586 +  {
31587 +    { 0, 0, 0, 0 },
31588 +    { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5_ADDSUB), 0 } },
31589 +    & ifmt_dsp_msub_2_s1_immediate_dsp_imm_bit5_addsub2, { 0x32200000 }
31590 +  },
31591 +/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},(${s1-An},${s1-r}),#${bit5-addsub} */
31592 +  {
31593 +    { 0, 0, 0, 0 },
31594 +    { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5_ADDSUB), 0 } },
31595 +    & ifmt_dsp_msub_2_s1_indirect_with_index_2_dsp_imm_bit5_addsub2, { 0x32200300 }
31596 +  },
31597 +/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},${s1-imm7-2}(${s1-An}),#${bit5-addsub} */
31598 +  {
31599 +    { 0, 0, 0, 0 },
31600 +    { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', '#', OP (BIT5_ADDSUB), 0 } },
31601 +    & ifmt_dsp_msub_2_s1_indirect_with_offset_2_dsp_imm_bit5_addsub2, { 0x32200400 }
31602 +  },
31603 +/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},(${s1-An}),#${bit5-addsub} */
31604 +  {
31605 +    { 0, 0, 0, 0 },
31606 +    { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5_ADDSUB), 0 } },
31607 +    & ifmt_dsp_msub_2_s1_indirect_2_dsp_imm_bit5_addsub2, { 0x32200400 }
31608 +  },
31609 +/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},(${s1-An})${s1-i4-2}++,#${bit5-addsub} */
31610 +  {
31611 +    { 0, 0, 0, 0 },
31612 +    { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', '#', OP (BIT5_ADDSUB), 0 } },
31613 +    & ifmt_dsp_msub_2_s1_indirect_with_post_increment_2_dsp_imm_bit5_addsub2, { 0x32200200 }
31614 +  },
31615 +/* madd.2${dsp-c}${dsp-t-addsub} ${dsp-destA},${s1-i4-2}(${s1-An})++,#${bit5-addsub} */
31616 +  {
31617 +    { 0, 0, 0, 0 },
31618 +    { { MNEM, OP (DSP_C), OP (DSP_T_ADDSUB), ' ', OP (DSP_DESTA), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5_ADDSUB), 0 } },
31619 +    & ifmt_dsp_msub_2_s1_indirect_with_pre_increment_2_dsp_imm_bit5_addsub2, { 0x32200210 }
31620 +  },
31621 +/* madd.4${dsp-c} ${dsp-destA},${s1-direct-addr},${dsp-S2-data-reg-addsub} */
31622 +  {
31623 +    { 0, 0, 0, 0 },
31624 +    { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_DATA_REG_ADDSUB), 0 } },
31625 +    & ifmt_dsp_msub_4_s1_direct_dsp_src2_data_reg_addsub, { 0x36000100 }
31626 +  },
31627 +/* madd.4${dsp-c} ${dsp-destA},#${s1-imm8},${dsp-S2-data-reg-addsub} */
31628 +  {
31629 +    { 0, 0, 0, 0 },
31630 +    { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', OP (DSP_S2_DATA_REG_ADDSUB), 0 } },
31631 +    & ifmt_dsp_msub_4_s1_immediate_dsp_src2_data_reg_addsub, { 0x36000000 }
31632 +  },
31633 +/* madd.4${dsp-c} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-data-reg-addsub} */
31634 +  {
31635 +    { 0, 0, 0, 0 },
31636 +    { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_DATA_REG_ADDSUB), 0 } },
31637 +    & ifmt_dsp_msub_4_s1_indirect_with_index_4_dsp_src2_data_reg_addsub, { 0x36000300 }
31638 +  },
31639 +/* madd.4${dsp-c} ${dsp-destA},${s1-imm7-4}(${s1-An}),${dsp-S2-data-reg-addsub} */
31640 +  {
31641 +    { 0, 0, 0, 0 },
31642 +    { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG_ADDSUB), 0 } },
31643 +    & ifmt_dsp_msub_4_s1_indirect_with_offset_4_dsp_src2_data_reg_addsub, { 0x36000400 }
31644 +  },
31645 +/* madd.4${dsp-c} ${dsp-destA},(${s1-An}),${dsp-S2-data-reg-addsub} */
31646 +  {
31647 +    { 0, 0, 0, 0 },
31648 +    { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG_ADDSUB), 0 } },
31649 +    & ifmt_dsp_msub_4_s1_indirect_4_dsp_src2_data_reg_addsub, { 0x36000400 }
31650 +  },
31651 +/* madd.4${dsp-c} ${dsp-destA},(${s1-An})${s1-i4-4}++,${dsp-S2-data-reg-addsub} */
31652 +  {
31653 +    { 0, 0, 0, 0 },
31654 +    { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (DSP_S2_DATA_REG_ADDSUB), 0 } },
31655 +    & ifmt_dsp_msub_4_s1_indirect_with_post_increment_4_dsp_src2_data_reg_addsub, { 0x36000200 }
31656 +  },
31657 +/* madd.4${dsp-c} ${dsp-destA},${s1-i4-4}(${s1-An})++,${dsp-S2-data-reg-addsub} */
31658 +  {
31659 +    { 0, 0, 0, 0 },
31660 +    { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_DATA_REG_ADDSUB), 0 } },
31661 +    & ifmt_dsp_msub_4_s1_indirect_with_pre_increment_4_dsp_src2_data_reg_addsub, { 0x36000210 }
31662 +  },
31663 +/* madd.4${dsp-c} ${dsp-destA},${s1-direct-addr},${dsp-S2-acc-reg-addsub} */
31664 +  {
31665 +    { 0, 0, 0, 0 },
31666 +    { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_ACC_REG_ADDSUB), 0 } },
31667 +    & ifmt_dsp_msub_4_s1_direct_dsp_src2_reg_acc_reg_addsub, { 0x36040100 }
31668 +  },
31669 +/* madd.4${dsp-c} ${dsp-destA},#${s1-imm8},${dsp-S2-acc-reg-addsub} */
31670 +  {
31671 +    { 0, 0, 0, 0 },
31672 +    { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', OP (DSP_S2_ACC_REG_ADDSUB), 0 } },
31673 +    & ifmt_dsp_msub_4_s1_immediate_dsp_src2_reg_acc_reg_addsub, { 0x36040000 }
31674 +  },
31675 +/* madd.4${dsp-c} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-acc-reg-addsub} */
31676 +  {
31677 +    { 0, 0, 0, 0 },
31678 +    { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_ACC_REG_ADDSUB), 0 } },
31679 +    & ifmt_dsp_msub_4_s1_indirect_with_index_4_dsp_src2_reg_acc_reg_addsub, { 0x36040300 }
31680 +  },
31681 +/* madd.4${dsp-c} ${dsp-destA},${s1-imm7-4}(${s1-An}),${dsp-S2-acc-reg-addsub} */
31682 +  {
31683 +    { 0, 0, 0, 0 },
31684 +    { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (DSP_S2_ACC_REG_ADDSUB), 0 } },
31685 +    & ifmt_dsp_msub_4_s1_indirect_with_offset_4_dsp_src2_reg_acc_reg_addsub, { 0x36040400 }
31686 +  },
31687 +/* madd.4${dsp-c} ${dsp-destA},(${s1-An}),${dsp-S2-acc-reg-addsub} */
31688 +  {
31689 +    { 0, 0, 0, 0 },
31690 +    { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', OP (DSP_S2_ACC_REG_ADDSUB), 0 } },
31691 +    & ifmt_dsp_msub_4_s1_indirect_4_dsp_src2_reg_acc_reg_addsub, { 0x36040400 }
31692 +  },
31693 +/* madd.4${dsp-c} ${dsp-destA},(${s1-An})${s1-i4-4}++,${dsp-S2-acc-reg-addsub} */
31694 +  {
31695 +    { 0, 0, 0, 0 },
31696 +    { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (DSP_S2_ACC_REG_ADDSUB), 0 } },
31697 +    & ifmt_dsp_msub_4_s1_indirect_with_post_increment_4_dsp_src2_reg_acc_reg_addsub, { 0x36040200 }
31698 +  },
31699 +/* madd.4${dsp-c} ${dsp-destA},${s1-i4-4}(${s1-An})++,${dsp-S2-acc-reg-addsub} */
31700 +  {
31701 +    { 0, 0, 0, 0 },
31702 +    { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_ACC_REG_ADDSUB), 0 } },
31703 +    & ifmt_dsp_msub_4_s1_indirect_with_pre_increment_4_dsp_src2_reg_acc_reg_addsub, { 0x36040210 }
31704 +  },
31705 +/* madd.4${dsp-c} ${dsp-destA},${s1-direct-addr},#${bit5-addsub} */
31706 +  {
31707 +    { 0, 0, 0, 0 },
31708 +    { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5_ADDSUB), 0 } },
31709 +    & ifmt_dsp_msub_4_s1_direct_dsp_imm_bit5_addsub, { 0x32000100 }
31710 +  },
31711 +/* madd.4${dsp-c} ${dsp-destA},#${s1-imm8},#${bit5-addsub} */
31712 +  {
31713 +    { 0, 0, 0, 0 },
31714 +    { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5_ADDSUB), 0 } },
31715 +    & ifmt_dsp_msub_4_s1_immediate_dsp_imm_bit5_addsub, { 0x32000000 }
31716 +  },
31717 +/* madd.4${dsp-c} ${dsp-destA},(${s1-An},${s1-r}),#${bit5-addsub} */
31718 +  {
31719 +    { 0, 0, 0, 0 },
31720 +    { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5_ADDSUB), 0 } },
31721 +    & ifmt_dsp_msub_4_s1_indirect_with_index_4_dsp_imm_bit5_addsub, { 0x32000300 }
31722 +  },
31723 +/* madd.4${dsp-c} ${dsp-destA},${s1-imm7-4}(${s1-An}),#${bit5-addsub} */
31724 +  {
31725 +    { 0, 0, 0, 0 },
31726 +    { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', '#', OP (BIT5_ADDSUB), 0 } },
31727 +    & ifmt_dsp_msub_4_s1_indirect_with_offset_4_dsp_imm_bit5_addsub, { 0x32000400 }
31728 +  },
31729 +/* madd.4${dsp-c} ${dsp-destA},(${s1-An}),#${bit5-addsub} */
31730 +  {
31731 +    { 0, 0, 0, 0 },
31732 +    { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5_ADDSUB), 0 } },
31733 +    & ifmt_dsp_msub_4_s1_indirect_4_dsp_imm_bit5_addsub, { 0x32000400 }
31734 +  },
31735 +/* madd.4${dsp-c} ${dsp-destA},(${s1-An})${s1-i4-4}++,#${bit5-addsub} */
31736 +  {
31737 +    { 0, 0, 0, 0 },
31738 +    { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', '#', OP (BIT5_ADDSUB), 0 } },
31739 +    & ifmt_dsp_msub_4_s1_indirect_with_post_increment_4_dsp_imm_bit5_addsub, { 0x32000200 }
31740 +  },
31741 +/* madd.4${dsp-c} ${dsp-destA},${s1-i4-4}(${s1-An})++,#${bit5-addsub} */
31742 +  {
31743 +    { 0, 0, 0, 0 },
31744 +    { { MNEM, OP (DSP_C), ' ', OP (DSP_DESTA), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5_ADDSUB), 0 } },
31745 +    & ifmt_dsp_msub_4_s1_indirect_with_pre_increment_4_dsp_imm_bit5_addsub, { 0x32000210 }
31746 +  },
31747 +/* msuf${dsp-c}${dsp-t} ${dsp-destA},${s1-direct-addr},${dsp-S2-data-reg} */
31748 +  {
31749 +    { 0, 0, 0, 0 },
31750 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_DATA_REG), 0 } },
31751 +    & ifmt_dsp_msuf_s1_direct_dsp_src2_data_reg, { 0x35200100 }
31752 +  },
31753 +/* msuf${dsp-c}${dsp-t} ${dsp-destA},#${s1-imm8},${dsp-S2-data-reg} */
31754 +  {
31755 +    { 0, 0, 0, 0 },
31756 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', OP (DSP_S2_DATA_REG), 0 } },
31757 +    & ifmt_dsp_msuf_s1_immediate_dsp_src2_data_reg, { 0x35200000 }
31758 +  },
31759 +/* msuf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-data-reg} */
31760 +  {
31761 +    { 0, 0, 0, 0 },
31762 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_DATA_REG), 0 } },
31763 +    & ifmt_dsp_msuf_s1_indirect_with_index_2_dsp_src2_data_reg, { 0x35200300 }
31764 +  },
31765 +/* msuf${dsp-c}${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),${dsp-S2-data-reg} */
31766 +  {
31767 +    { 0, 0, 0, 0 },
31768 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG), 0 } },
31769 +    & ifmt_dsp_msuf_s1_indirect_with_offset_2_dsp_src2_data_reg, { 0x35200400 }
31770 +  },
31771 +/* msuf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An}),${dsp-S2-data-reg} */
31772 +  {
31773 +    { 0, 0, 0, 0 },
31774 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG), 0 } },
31775 +    & ifmt_dsp_msuf_s1_indirect_2_dsp_src2_data_reg, { 0x35200400 }
31776 +  },
31777 +/* msuf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,${dsp-S2-data-reg} */
31778 +  {
31779 +    { 0, 0, 0, 0 },
31780 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (DSP_S2_DATA_REG), 0 } },
31781 +    & ifmt_dsp_msuf_s1_indirect_with_post_increment_2_dsp_src2_data_reg, { 0x35200200 }
31782 +  },
31783 +/* msuf${dsp-c}${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,${dsp-S2-data-reg} */
31784 +  {
31785 +    { 0, 0, 0, 0 },
31786 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_DATA_REG), 0 } },
31787 +    & ifmt_dsp_msuf_s1_indirect_with_pre_increment_2_dsp_src2_data_reg, { 0x35200210 }
31788 +  },
31789 +/* msuf${dsp-c}${dsp-t} ${dsp-destA},${s1-direct-addr},${dsp-S2-acc-reg-mul} */
31790 +  {
31791 +    { 0, 0, 0, 0 },
31792 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
31793 +    & ifmt_dsp_msuf_s1_direct_dsp_src2_reg_acc_reg_mul, { 0x35240100 }
31794 +  },
31795 +/* msuf${dsp-c}${dsp-t} ${dsp-destA},#${s1-imm8},${dsp-S2-acc-reg-mul} */
31796 +  {
31797 +    { 0, 0, 0, 0 },
31798 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
31799 +    & ifmt_dsp_msuf_s1_immediate_dsp_src2_reg_acc_reg_mul, { 0x35240000 }
31800 +  },
31801 +/* msuf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-acc-reg-mul} */
31802 +  {
31803 +    { 0, 0, 0, 0 },
31804 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
31805 +    & ifmt_dsp_msuf_s1_indirect_with_index_2_dsp_src2_reg_acc_reg_mul, { 0x35240300 }
31806 +  },
31807 +/* msuf${dsp-c}${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),${dsp-S2-acc-reg-mul} */
31808 +  {
31809 +    { 0, 0, 0, 0 },
31810 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
31811 +    & ifmt_dsp_msuf_s1_indirect_with_offset_2_dsp_src2_reg_acc_reg_mul, { 0x35240400 }
31812 +  },
31813 +/* msuf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An}),${dsp-S2-acc-reg-mul} */
31814 +  {
31815 +    { 0, 0, 0, 0 },
31816 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
31817 +    & ifmt_dsp_msuf_s1_indirect_2_dsp_src2_reg_acc_reg_mul, { 0x35240400 }
31818 +  },
31819 +/* msuf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,${dsp-S2-acc-reg-mul} */
31820 +  {
31821 +    { 0, 0, 0, 0 },
31822 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
31823 +    & ifmt_dsp_msuf_s1_indirect_with_post_increment_2_dsp_src2_reg_acc_reg_mul, { 0x35240200 }
31824 +  },
31825 +/* msuf${dsp-c}${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,${dsp-S2-acc-reg-mul} */
31826 +  {
31827 +    { 0, 0, 0, 0 },
31828 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
31829 +    & ifmt_dsp_msuf_s1_indirect_with_pre_increment_2_dsp_src2_reg_acc_reg_mul, { 0x35240210 }
31830 +  },
31831 +/* msuf${dsp-c}${dsp-t} ${dsp-destA},${s1-direct-addr},#${bit5} */
31832 +  {
31833 +    { 0, 0, 0, 0 },
31834 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } },
31835 +    & ifmt_dsp_msuf_s1_direct_dsp_imm_bit5, { 0x31200100 }
31836 +  },
31837 +/* msuf${dsp-c}${dsp-t} ${dsp-destA},#${s1-imm8},#${bit5} */
31838 +  {
31839 +    { 0, 0, 0, 0 },
31840 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } },
31841 +    & ifmt_dsp_msuf_s1_immediate_dsp_imm_bit5, { 0x31200000 }
31842 +  },
31843 +/* msuf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),#${bit5} */
31844 +  {
31845 +    { 0, 0, 0, 0 },
31846 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } },
31847 +    & ifmt_dsp_msuf_s1_indirect_with_index_2_dsp_imm_bit5, { 0x31200300 }
31848 +  },
31849 +/* msuf${dsp-c}${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),#${bit5} */
31850 +  {
31851 +    { 0, 0, 0, 0 },
31852 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
31853 +    & ifmt_dsp_msuf_s1_indirect_with_offset_2_dsp_imm_bit5, { 0x31200400 }
31854 +  },
31855 +/* msuf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An}),#${bit5} */
31856 +  {
31857 +    { 0, 0, 0, 0 },
31858 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
31859 +    & ifmt_dsp_msuf_s1_indirect_2_dsp_imm_bit5, { 0x31200400 }
31860 +  },
31861 +/* msuf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,#${bit5} */
31862 +  {
31863 +    { 0, 0, 0, 0 },
31864 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', '#', OP (BIT5), 0 } },
31865 +    & ifmt_dsp_msuf_s1_indirect_with_post_increment_2_dsp_imm_bit5, { 0x31200200 }
31866 +  },
31867 +/* msuf${dsp-c}${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,#${bit5} */
31868 +  {
31869 +    { 0, 0, 0, 0 },
31870 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } },
31871 +    & ifmt_dsp_msuf_s1_indirect_with_pre_increment_2_dsp_imm_bit5, { 0x31200210 }
31872 +  },
31873 +/* macus${dsp-c}${dsp-t} ${dsp-destA},${s1-direct-addr},${dsp-S2-data-reg} */
31874 +  {
31875 +    { 0, 0, 0, 0 },
31876 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_DATA_REG), 0 } },
31877 +    & ifmt_dsp_msuf_s1_direct_dsp_src2_data_reg, { 0x34e00100 }
31878 +  },
31879 +/* macus${dsp-c}${dsp-t} ${dsp-destA},#${s1-imm8},${dsp-S2-data-reg} */
31880 +  {
31881 +    { 0, 0, 0, 0 },
31882 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', OP (DSP_S2_DATA_REG), 0 } },
31883 +    & ifmt_dsp_msuf_s1_immediate_dsp_src2_data_reg, { 0x34e00000 }
31884 +  },
31885 +/* macus${dsp-c}${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-data-reg} */
31886 +  {
31887 +    { 0, 0, 0, 0 },
31888 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_DATA_REG), 0 } },
31889 +    & ifmt_dsp_msuf_s1_indirect_with_index_2_dsp_src2_data_reg, { 0x34e00300 }
31890 +  },
31891 +/* macus${dsp-c}${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),${dsp-S2-data-reg} */
31892 +  {
31893 +    { 0, 0, 0, 0 },
31894 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG), 0 } },
31895 +    & ifmt_dsp_msuf_s1_indirect_with_offset_2_dsp_src2_data_reg, { 0x34e00400 }
31896 +  },
31897 +/* macus${dsp-c}${dsp-t} ${dsp-destA},(${s1-An}),${dsp-S2-data-reg} */
31898 +  {
31899 +    { 0, 0, 0, 0 },
31900 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG), 0 } },
31901 +    & ifmt_dsp_msuf_s1_indirect_2_dsp_src2_data_reg, { 0x34e00400 }
31902 +  },
31903 +/* macus${dsp-c}${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,${dsp-S2-data-reg} */
31904 +  {
31905 +    { 0, 0, 0, 0 },
31906 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (DSP_S2_DATA_REG), 0 } },
31907 +    & ifmt_dsp_msuf_s1_indirect_with_post_increment_2_dsp_src2_data_reg, { 0x34e00200 }
31908 +  },
31909 +/* macus${dsp-c}${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,${dsp-S2-data-reg} */
31910 +  {
31911 +    { 0, 0, 0, 0 },
31912 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_DATA_REG), 0 } },
31913 +    & ifmt_dsp_msuf_s1_indirect_with_pre_increment_2_dsp_src2_data_reg, { 0x34e00210 }
31914 +  },
31915 +/* macus${dsp-c}${dsp-t} ${dsp-destA},${s1-direct-addr},${dsp-S2-acc-reg-mul} */
31916 +  {
31917 +    { 0, 0, 0, 0 },
31918 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
31919 +    & ifmt_dsp_msuf_s1_direct_dsp_src2_reg_acc_reg_mul, { 0x34e40100 }
31920 +  },
31921 +/* macus${dsp-c}${dsp-t} ${dsp-destA},#${s1-imm8},${dsp-S2-acc-reg-mul} */
31922 +  {
31923 +    { 0, 0, 0, 0 },
31924 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
31925 +    & ifmt_dsp_msuf_s1_immediate_dsp_src2_reg_acc_reg_mul, { 0x34e40000 }
31926 +  },
31927 +/* macus${dsp-c}${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-acc-reg-mul} */
31928 +  {
31929 +    { 0, 0, 0, 0 },
31930 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
31931 +    & ifmt_dsp_msuf_s1_indirect_with_index_2_dsp_src2_reg_acc_reg_mul, { 0x34e40300 }
31932 +  },
31933 +/* macus${dsp-c}${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),${dsp-S2-acc-reg-mul} */
31934 +  {
31935 +    { 0, 0, 0, 0 },
31936 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
31937 +    & ifmt_dsp_msuf_s1_indirect_with_offset_2_dsp_src2_reg_acc_reg_mul, { 0x34e40400 }
31938 +  },
31939 +/* macus${dsp-c}${dsp-t} ${dsp-destA},(${s1-An}),${dsp-S2-acc-reg-mul} */
31940 +  {
31941 +    { 0, 0, 0, 0 },
31942 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
31943 +    & ifmt_dsp_msuf_s1_indirect_2_dsp_src2_reg_acc_reg_mul, { 0x34e40400 }
31944 +  },
31945 +/* macus${dsp-c}${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,${dsp-S2-acc-reg-mul} */
31946 +  {
31947 +    { 0, 0, 0, 0 },
31948 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
31949 +    & ifmt_dsp_msuf_s1_indirect_with_post_increment_2_dsp_src2_reg_acc_reg_mul, { 0x34e40200 }
31950 +  },
31951 +/* macus${dsp-c}${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,${dsp-S2-acc-reg-mul} */
31952 +  {
31953 +    { 0, 0, 0, 0 },
31954 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
31955 +    & ifmt_dsp_msuf_s1_indirect_with_pre_increment_2_dsp_src2_reg_acc_reg_mul, { 0x34e40210 }
31956 +  },
31957 +/* macus${dsp-c}${dsp-t} ${dsp-destA},${s1-direct-addr},#${bit5} */
31958 +  {
31959 +    { 0, 0, 0, 0 },
31960 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } },
31961 +    & ifmt_dsp_msuf_s1_direct_dsp_imm_bit5, { 0x30e00100 }
31962 +  },
31963 +/* macus${dsp-c}${dsp-t} ${dsp-destA},#${s1-imm8},#${bit5} */
31964 +  {
31965 +    { 0, 0, 0, 0 },
31966 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } },
31967 +    & ifmt_dsp_msuf_s1_immediate_dsp_imm_bit5, { 0x30e00000 }
31968 +  },
31969 +/* macus${dsp-c}${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),#${bit5} */
31970 +  {
31971 +    { 0, 0, 0, 0 },
31972 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } },
31973 +    & ifmt_dsp_msuf_s1_indirect_with_index_2_dsp_imm_bit5, { 0x30e00300 }
31974 +  },
31975 +/* macus${dsp-c}${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),#${bit5} */
31976 +  {
31977 +    { 0, 0, 0, 0 },
31978 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
31979 +    & ifmt_dsp_msuf_s1_indirect_with_offset_2_dsp_imm_bit5, { 0x30e00400 }
31980 +  },
31981 +/* macus${dsp-c}${dsp-t} ${dsp-destA},(${s1-An}),#${bit5} */
31982 +  {
31983 +    { 0, 0, 0, 0 },
31984 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
31985 +    & ifmt_dsp_msuf_s1_indirect_2_dsp_imm_bit5, { 0x30e00400 }
31986 +  },
31987 +/* macus${dsp-c}${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,#${bit5} */
31988 +  {
31989 +    { 0, 0, 0, 0 },
31990 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', '#', OP (BIT5), 0 } },
31991 +    & ifmt_dsp_msuf_s1_indirect_with_post_increment_2_dsp_imm_bit5, { 0x30e00200 }
31992 +  },
31993 +/* macus${dsp-c}${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,#${bit5} */
31994 +  {
31995 +    { 0, 0, 0, 0 },
31996 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } },
31997 +    & ifmt_dsp_msuf_s1_indirect_with_pre_increment_2_dsp_imm_bit5, { 0x30e00210 }
31998 +  },
31999 +/* macf${dsp-c}${dsp-t} ${dsp-destA},${s1-direct-addr},${dsp-S2-data-reg} */
32000 +  {
32001 +    { 0, 0, 0, 0 },
32002 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_DATA_REG), 0 } },
32003 +    & ifmt_dsp_msuf_s1_direct_dsp_src2_data_reg, { 0x34a00100 }
32004 +  },
32005 +/* macf${dsp-c}${dsp-t} ${dsp-destA},#${s1-imm8},${dsp-S2-data-reg} */
32006 +  {
32007 +    { 0, 0, 0, 0 },
32008 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', OP (DSP_S2_DATA_REG), 0 } },
32009 +    & ifmt_dsp_msuf_s1_immediate_dsp_src2_data_reg, { 0x34a00000 }
32010 +  },
32011 +/* macf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-data-reg} */
32012 +  {
32013 +    { 0, 0, 0, 0 },
32014 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_DATA_REG), 0 } },
32015 +    & ifmt_dsp_msuf_s1_indirect_with_index_2_dsp_src2_data_reg, { 0x34a00300 }
32016 +  },
32017 +/* macf${dsp-c}${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),${dsp-S2-data-reg} */
32018 +  {
32019 +    { 0, 0, 0, 0 },
32020 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG), 0 } },
32021 +    & ifmt_dsp_msuf_s1_indirect_with_offset_2_dsp_src2_data_reg, { 0x34a00400 }
32022 +  },
32023 +/* macf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An}),${dsp-S2-data-reg} */
32024 +  {
32025 +    { 0, 0, 0, 0 },
32026 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG), 0 } },
32027 +    & ifmt_dsp_msuf_s1_indirect_2_dsp_src2_data_reg, { 0x34a00400 }
32028 +  },
32029 +/* macf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,${dsp-S2-data-reg} */
32030 +  {
32031 +    { 0, 0, 0, 0 },
32032 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (DSP_S2_DATA_REG), 0 } },
32033 +    & ifmt_dsp_msuf_s1_indirect_with_post_increment_2_dsp_src2_data_reg, { 0x34a00200 }
32034 +  },
32035 +/* macf${dsp-c}${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,${dsp-S2-data-reg} */
32036 +  {
32037 +    { 0, 0, 0, 0 },
32038 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_DATA_REG), 0 } },
32039 +    & ifmt_dsp_msuf_s1_indirect_with_pre_increment_2_dsp_src2_data_reg, { 0x34a00210 }
32040 +  },
32041 +/* macf${dsp-c}${dsp-t} ${dsp-destA},${s1-direct-addr},${dsp-S2-acc-reg-mul} */
32042 +  {
32043 +    { 0, 0, 0, 0 },
32044 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
32045 +    & ifmt_dsp_msuf_s1_direct_dsp_src2_reg_acc_reg_mul, { 0x34a40100 }
32046 +  },
32047 +/* macf${dsp-c}${dsp-t} ${dsp-destA},#${s1-imm8},${dsp-S2-acc-reg-mul} */
32048 +  {
32049 +    { 0, 0, 0, 0 },
32050 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
32051 +    & ifmt_dsp_msuf_s1_immediate_dsp_src2_reg_acc_reg_mul, { 0x34a40000 }
32052 +  },
32053 +/* macf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-acc-reg-mul} */
32054 +  {
32055 +    { 0, 0, 0, 0 },
32056 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
32057 +    & ifmt_dsp_msuf_s1_indirect_with_index_2_dsp_src2_reg_acc_reg_mul, { 0x34a40300 }
32058 +  },
32059 +/* macf${dsp-c}${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),${dsp-S2-acc-reg-mul} */
32060 +  {
32061 +    { 0, 0, 0, 0 },
32062 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
32063 +    & ifmt_dsp_msuf_s1_indirect_with_offset_2_dsp_src2_reg_acc_reg_mul, { 0x34a40400 }
32064 +  },
32065 +/* macf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An}),${dsp-S2-acc-reg-mul} */
32066 +  {
32067 +    { 0, 0, 0, 0 },
32068 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
32069 +    & ifmt_dsp_msuf_s1_indirect_2_dsp_src2_reg_acc_reg_mul, { 0x34a40400 }
32070 +  },
32071 +/* macf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,${dsp-S2-acc-reg-mul} */
32072 +  {
32073 +    { 0, 0, 0, 0 },
32074 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
32075 +    & ifmt_dsp_msuf_s1_indirect_with_post_increment_2_dsp_src2_reg_acc_reg_mul, { 0x34a40200 }
32076 +  },
32077 +/* macf${dsp-c}${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,${dsp-S2-acc-reg-mul} */
32078 +  {
32079 +    { 0, 0, 0, 0 },
32080 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
32081 +    & ifmt_dsp_msuf_s1_indirect_with_pre_increment_2_dsp_src2_reg_acc_reg_mul, { 0x34a40210 }
32082 +  },
32083 +/* macf${dsp-c}${dsp-t} ${dsp-destA},${s1-direct-addr},#${bit5} */
32084 +  {
32085 +    { 0, 0, 0, 0 },
32086 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } },
32087 +    & ifmt_dsp_msuf_s1_direct_dsp_imm_bit5, { 0x30a00100 }
32088 +  },
32089 +/* macf${dsp-c}${dsp-t} ${dsp-destA},#${s1-imm8},#${bit5} */
32090 +  {
32091 +    { 0, 0, 0, 0 },
32092 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } },
32093 +    & ifmt_dsp_msuf_s1_immediate_dsp_imm_bit5, { 0x30a00000 }
32094 +  },
32095 +/* macf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),#${bit5} */
32096 +  {
32097 +    { 0, 0, 0, 0 },
32098 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } },
32099 +    & ifmt_dsp_msuf_s1_indirect_with_index_2_dsp_imm_bit5, { 0x30a00300 }
32100 +  },
32101 +/* macf${dsp-c}${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),#${bit5} */
32102 +  {
32103 +    { 0, 0, 0, 0 },
32104 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
32105 +    & ifmt_dsp_msuf_s1_indirect_with_offset_2_dsp_imm_bit5, { 0x30a00400 }
32106 +  },
32107 +/* macf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An}),#${bit5} */
32108 +  {
32109 +    { 0, 0, 0, 0 },
32110 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
32111 +    & ifmt_dsp_msuf_s1_indirect_2_dsp_imm_bit5, { 0x30a00400 }
32112 +  },
32113 +/* macf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,#${bit5} */
32114 +  {
32115 +    { 0, 0, 0, 0 },
32116 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', '#', OP (BIT5), 0 } },
32117 +    & ifmt_dsp_msuf_s1_indirect_with_post_increment_2_dsp_imm_bit5, { 0x30a00200 }
32118 +  },
32119 +/* macf${dsp-c}${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,#${bit5} */
32120 +  {
32121 +    { 0, 0, 0, 0 },
32122 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } },
32123 +    & ifmt_dsp_msuf_s1_indirect_with_pre_increment_2_dsp_imm_bit5, { 0x30a00210 }
32124 +  },
32125 +/* mulf${dsp-c}${dsp-t} ${dsp-destA},${s1-direct-addr},${dsp-S2-data-reg} */
32126 +  {
32127 +    { 0, 0, 0, 0 },
32128 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_DATA_REG), 0 } },
32129 +    & ifmt_dsp_msuf_s1_direct_dsp_src2_data_reg, { 0x34800100 }
32130 +  },
32131 +/* mulf${dsp-c}${dsp-t} ${dsp-destA},#${s1-imm8},${dsp-S2-data-reg} */
32132 +  {
32133 +    { 0, 0, 0, 0 },
32134 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', OP (DSP_S2_DATA_REG), 0 } },
32135 +    & ifmt_dsp_msuf_s1_immediate_dsp_src2_data_reg, { 0x34800000 }
32136 +  },
32137 +/* mulf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-data-reg} */
32138 +  {
32139 +    { 0, 0, 0, 0 },
32140 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_DATA_REG), 0 } },
32141 +    & ifmt_dsp_msuf_s1_indirect_with_index_2_dsp_src2_data_reg, { 0x34800300 }
32142 +  },
32143 +/* mulf${dsp-c}${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),${dsp-S2-data-reg} */
32144 +  {
32145 +    { 0, 0, 0, 0 },
32146 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG), 0 } },
32147 +    & ifmt_dsp_msuf_s1_indirect_with_offset_2_dsp_src2_data_reg, { 0x34800400 }
32148 +  },
32149 +/* mulf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An}),${dsp-S2-data-reg} */
32150 +  {
32151 +    { 0, 0, 0, 0 },
32152 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG), 0 } },
32153 +    & ifmt_dsp_msuf_s1_indirect_2_dsp_src2_data_reg, { 0x34800400 }
32154 +  },
32155 +/* mulf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,${dsp-S2-data-reg} */
32156 +  {
32157 +    { 0, 0, 0, 0 },
32158 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (DSP_S2_DATA_REG), 0 } },
32159 +    & ifmt_dsp_msuf_s1_indirect_with_post_increment_2_dsp_src2_data_reg, { 0x34800200 }
32160 +  },
32161 +/* mulf${dsp-c}${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,${dsp-S2-data-reg} */
32162 +  {
32163 +    { 0, 0, 0, 0 },
32164 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_DATA_REG), 0 } },
32165 +    & ifmt_dsp_msuf_s1_indirect_with_pre_increment_2_dsp_src2_data_reg, { 0x34800210 }
32166 +  },
32167 +/* mulf${dsp-c}${dsp-t} ${dsp-destA},${s1-direct-addr},${dsp-S2-acc-reg-mul} */
32168 +  {
32169 +    { 0, 0, 0, 0 },
32170 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
32171 +    & ifmt_dsp_msuf_s1_direct_dsp_src2_reg_acc_reg_mul, { 0x34840100 }
32172 +  },
32173 +/* mulf${dsp-c}${dsp-t} ${dsp-destA},#${s1-imm8},${dsp-S2-acc-reg-mul} */
32174 +  {
32175 +    { 0, 0, 0, 0 },
32176 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
32177 +    & ifmt_dsp_msuf_s1_immediate_dsp_src2_reg_acc_reg_mul, { 0x34840000 }
32178 +  },
32179 +/* mulf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-acc-reg-mul} */
32180 +  {
32181 +    { 0, 0, 0, 0 },
32182 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
32183 +    & ifmt_dsp_msuf_s1_indirect_with_index_2_dsp_src2_reg_acc_reg_mul, { 0x34840300 }
32184 +  },
32185 +/* mulf${dsp-c}${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),${dsp-S2-acc-reg-mul} */
32186 +  {
32187 +    { 0, 0, 0, 0 },
32188 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
32189 +    & ifmt_dsp_msuf_s1_indirect_with_offset_2_dsp_src2_reg_acc_reg_mul, { 0x34840400 }
32190 +  },
32191 +/* mulf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An}),${dsp-S2-acc-reg-mul} */
32192 +  {
32193 +    { 0, 0, 0, 0 },
32194 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
32195 +    & ifmt_dsp_msuf_s1_indirect_2_dsp_src2_reg_acc_reg_mul, { 0x34840400 }
32196 +  },
32197 +/* mulf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,${dsp-S2-acc-reg-mul} */
32198 +  {
32199 +    { 0, 0, 0, 0 },
32200 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
32201 +    & ifmt_dsp_msuf_s1_indirect_with_post_increment_2_dsp_src2_reg_acc_reg_mul, { 0x34840200 }
32202 +  },
32203 +/* mulf${dsp-c}${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,${dsp-S2-acc-reg-mul} */
32204 +  {
32205 +    { 0, 0, 0, 0 },
32206 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
32207 +    & ifmt_dsp_msuf_s1_indirect_with_pre_increment_2_dsp_src2_reg_acc_reg_mul, { 0x34840210 }
32208 +  },
32209 +/* mulf${dsp-c}${dsp-t} ${dsp-destA},${s1-direct-addr},#${bit5} */
32210 +  {
32211 +    { 0, 0, 0, 0 },
32212 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } },
32213 +    & ifmt_dsp_msuf_s1_direct_dsp_imm_bit5, { 0x30800100 }
32214 +  },
32215 +/* mulf${dsp-c}${dsp-t} ${dsp-destA},#${s1-imm8},#${bit5} */
32216 +  {
32217 +    { 0, 0, 0, 0 },
32218 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } },
32219 +    & ifmt_dsp_msuf_s1_immediate_dsp_imm_bit5, { 0x30800000 }
32220 +  },
32221 +/* mulf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),#${bit5} */
32222 +  {
32223 +    { 0, 0, 0, 0 },
32224 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } },
32225 +    & ifmt_dsp_msuf_s1_indirect_with_index_2_dsp_imm_bit5, { 0x30800300 }
32226 +  },
32227 +/* mulf${dsp-c}${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),#${bit5} */
32228 +  {
32229 +    { 0, 0, 0, 0 },
32230 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
32231 +    & ifmt_dsp_msuf_s1_indirect_with_offset_2_dsp_imm_bit5, { 0x30800400 }
32232 +  },
32233 +/* mulf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An}),#${bit5} */
32234 +  {
32235 +    { 0, 0, 0, 0 },
32236 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
32237 +    & ifmt_dsp_msuf_s1_indirect_2_dsp_imm_bit5, { 0x30800400 }
32238 +  },
32239 +/* mulf${dsp-c}${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,#${bit5} */
32240 +  {
32241 +    { 0, 0, 0, 0 },
32242 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', '#', OP (BIT5), 0 } },
32243 +    & ifmt_dsp_msuf_s1_indirect_with_post_increment_2_dsp_imm_bit5, { 0x30800200 }
32244 +  },
32245 +/* mulf${dsp-c}${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,#${bit5} */
32246 +  {
32247 +    { 0, 0, 0, 0 },
32248 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } },
32249 +    & ifmt_dsp_msuf_s1_indirect_with_pre_increment_2_dsp_imm_bit5, { 0x30800210 }
32250 +  },
32251 +/* macu${dsp-c}${dsp-t} ${dsp-destA},${s1-direct-addr},${dsp-S2-data-reg} */
32252 +  {
32253 +    { 0, 0, 0, 0 },
32254 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_DATA_REG), 0 } },
32255 +    & ifmt_dsp_msuf_s1_direct_dsp_src2_data_reg, { 0x34600100 }
32256 +  },
32257 +/* macu${dsp-c}${dsp-t} ${dsp-destA},#${s1-imm8},${dsp-S2-data-reg} */
32258 +  {
32259 +    { 0, 0, 0, 0 },
32260 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', OP (DSP_S2_DATA_REG), 0 } },
32261 +    & ifmt_dsp_msuf_s1_immediate_dsp_src2_data_reg, { 0x34600000 }
32262 +  },
32263 +/* macu${dsp-c}${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-data-reg} */
32264 +  {
32265 +    { 0, 0, 0, 0 },
32266 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_DATA_REG), 0 } },
32267 +    & ifmt_dsp_msuf_s1_indirect_with_index_2_dsp_src2_data_reg, { 0x34600300 }
32268 +  },
32269 +/* macu${dsp-c}${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),${dsp-S2-data-reg} */
32270 +  {
32271 +    { 0, 0, 0, 0 },
32272 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG), 0 } },
32273 +    & ifmt_dsp_msuf_s1_indirect_with_offset_2_dsp_src2_data_reg, { 0x34600400 }
32274 +  },
32275 +/* macu${dsp-c}${dsp-t} ${dsp-destA},(${s1-An}),${dsp-S2-data-reg} */
32276 +  {
32277 +    { 0, 0, 0, 0 },
32278 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG), 0 } },
32279 +    & ifmt_dsp_msuf_s1_indirect_2_dsp_src2_data_reg, { 0x34600400 }
32280 +  },
32281 +/* macu${dsp-c}${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,${dsp-S2-data-reg} */
32282 +  {
32283 +    { 0, 0, 0, 0 },
32284 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (DSP_S2_DATA_REG), 0 } },
32285 +    & ifmt_dsp_msuf_s1_indirect_with_post_increment_2_dsp_src2_data_reg, { 0x34600200 }
32286 +  },
32287 +/* macu${dsp-c}${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,${dsp-S2-data-reg} */
32288 +  {
32289 +    { 0, 0, 0, 0 },
32290 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_DATA_REG), 0 } },
32291 +    & ifmt_dsp_msuf_s1_indirect_with_pre_increment_2_dsp_src2_data_reg, { 0x34600210 }
32292 +  },
32293 +/* macu${dsp-c}${dsp-t} ${dsp-destA},${s1-direct-addr},${dsp-S2-acc-reg-mul} */
32294 +  {
32295 +    { 0, 0, 0, 0 },
32296 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
32297 +    & ifmt_dsp_msuf_s1_direct_dsp_src2_reg_acc_reg_mul, { 0x34640100 }
32298 +  },
32299 +/* macu${dsp-c}${dsp-t} ${dsp-destA},#${s1-imm8},${dsp-S2-acc-reg-mul} */
32300 +  {
32301 +    { 0, 0, 0, 0 },
32302 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
32303 +    & ifmt_dsp_msuf_s1_immediate_dsp_src2_reg_acc_reg_mul, { 0x34640000 }
32304 +  },
32305 +/* macu${dsp-c}${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-acc-reg-mul} */
32306 +  {
32307 +    { 0, 0, 0, 0 },
32308 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
32309 +    & ifmt_dsp_msuf_s1_indirect_with_index_2_dsp_src2_reg_acc_reg_mul, { 0x34640300 }
32310 +  },
32311 +/* macu${dsp-c}${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),${dsp-S2-acc-reg-mul} */
32312 +  {
32313 +    { 0, 0, 0, 0 },
32314 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
32315 +    & ifmt_dsp_msuf_s1_indirect_with_offset_2_dsp_src2_reg_acc_reg_mul, { 0x34640400 }
32316 +  },
32317 +/* macu${dsp-c}${dsp-t} ${dsp-destA},(${s1-An}),${dsp-S2-acc-reg-mul} */
32318 +  {
32319 +    { 0, 0, 0, 0 },
32320 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
32321 +    & ifmt_dsp_msuf_s1_indirect_2_dsp_src2_reg_acc_reg_mul, { 0x34640400 }
32322 +  },
32323 +/* macu${dsp-c}${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,${dsp-S2-acc-reg-mul} */
32324 +  {
32325 +    { 0, 0, 0, 0 },
32326 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
32327 +    & ifmt_dsp_msuf_s1_indirect_with_post_increment_2_dsp_src2_reg_acc_reg_mul, { 0x34640200 }
32328 +  },
32329 +/* macu${dsp-c}${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,${dsp-S2-acc-reg-mul} */
32330 +  {
32331 +    { 0, 0, 0, 0 },
32332 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
32333 +    & ifmt_dsp_msuf_s1_indirect_with_pre_increment_2_dsp_src2_reg_acc_reg_mul, { 0x34640210 }
32334 +  },
32335 +/* macu${dsp-c}${dsp-t} ${dsp-destA},${s1-direct-addr},#${bit5} */
32336 +  {
32337 +    { 0, 0, 0, 0 },
32338 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } },
32339 +    & ifmt_dsp_msuf_s1_direct_dsp_imm_bit5, { 0x30600100 }
32340 +  },
32341 +/* macu${dsp-c}${dsp-t} ${dsp-destA},#${s1-imm8},#${bit5} */
32342 +  {
32343 +    { 0, 0, 0, 0 },
32344 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } },
32345 +    & ifmt_dsp_msuf_s1_immediate_dsp_imm_bit5, { 0x30600000 }
32346 +  },
32347 +/* macu${dsp-c}${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),#${bit5} */
32348 +  {
32349 +    { 0, 0, 0, 0 },
32350 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } },
32351 +    & ifmt_dsp_msuf_s1_indirect_with_index_2_dsp_imm_bit5, { 0x30600300 }
32352 +  },
32353 +/* macu${dsp-c}${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),#${bit5} */
32354 +  {
32355 +    { 0, 0, 0, 0 },
32356 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
32357 +    & ifmt_dsp_msuf_s1_indirect_with_offset_2_dsp_imm_bit5, { 0x30600400 }
32358 +  },
32359 +/* macu${dsp-c}${dsp-t} ${dsp-destA},(${s1-An}),#${bit5} */
32360 +  {
32361 +    { 0, 0, 0, 0 },
32362 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
32363 +    & ifmt_dsp_msuf_s1_indirect_2_dsp_imm_bit5, { 0x30600400 }
32364 +  },
32365 +/* macu${dsp-c}${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,#${bit5} */
32366 +  {
32367 +    { 0, 0, 0, 0 },
32368 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', '#', OP (BIT5), 0 } },
32369 +    & ifmt_dsp_msuf_s1_indirect_with_post_increment_2_dsp_imm_bit5, { 0x30600200 }
32370 +  },
32371 +/* macu${dsp-c}${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,#${bit5} */
32372 +  {
32373 +    { 0, 0, 0, 0 },
32374 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } },
32375 +    & ifmt_dsp_msuf_s1_indirect_with_pre_increment_2_dsp_imm_bit5, { 0x30600210 }
32376 +  },
32377 +/* mulu.4 ${dsp-destA},${s1-direct-addr},${dsp-S2-data-reg} */
32378 +  {
32379 +    { 0, 0, 0, 0 },
32380 +    { { MNEM, ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_DATA_REG), 0 } },
32381 +    & ifmt_dsp_mulu_4_s1_direct_dsp_src2_data_reg, { 0x35400100 }
32382 +  },
32383 +/* mulu.4 ${dsp-destA},#${s1-imm8},${dsp-S2-data-reg} */
32384 +  {
32385 +    { 0, 0, 0, 0 },
32386 +    { { MNEM, ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', OP (DSP_S2_DATA_REG), 0 } },
32387 +    & ifmt_dsp_mulu_4_s1_immediate_dsp_src2_data_reg, { 0x35400000 }
32388 +  },
32389 +/* mulu.4 ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-data-reg} */
32390 +  {
32391 +    { 0, 0, 0, 0 },
32392 +    { { MNEM, ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_DATA_REG), 0 } },
32393 +    & ifmt_dsp_mulu_4_s1_indirect_with_index_4_dsp_src2_data_reg, { 0x35400300 }
32394 +  },
32395 +/* mulu.4 ${dsp-destA},${s1-imm7-4}(${s1-An}),${dsp-S2-data-reg} */
32396 +  {
32397 +    { 0, 0, 0, 0 },
32398 +    { { MNEM, ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG), 0 } },
32399 +    & ifmt_dsp_mulu_4_s1_indirect_with_offset_4_dsp_src2_data_reg, { 0x35400400 }
32400 +  },
32401 +/* mulu.4 ${dsp-destA},(${s1-An}),${dsp-S2-data-reg} */
32402 +  {
32403 +    { 0, 0, 0, 0 },
32404 +    { { MNEM, ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG), 0 } },
32405 +    & ifmt_dsp_mulu_4_s1_indirect_4_dsp_src2_data_reg, { 0x35400400 }
32406 +  },
32407 +/* mulu.4 ${dsp-destA},(${s1-An})${s1-i4-4}++,${dsp-S2-data-reg} */
32408 +  {
32409 +    { 0, 0, 0, 0 },
32410 +    { { MNEM, ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (DSP_S2_DATA_REG), 0 } },
32411 +    & ifmt_dsp_mulu_4_s1_indirect_with_post_increment_4_dsp_src2_data_reg, { 0x35400200 }
32412 +  },
32413 +/* mulu.4 ${dsp-destA},${s1-i4-4}(${s1-An})++,${dsp-S2-data-reg} */
32414 +  {
32415 +    { 0, 0, 0, 0 },
32416 +    { { MNEM, ' ', OP (DSP_DESTA), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_DATA_REG), 0 } },
32417 +    & ifmt_dsp_mulu_4_s1_indirect_with_pre_increment_4_dsp_src2_data_reg, { 0x35400210 }
32418 +  },
32419 +/* mulu.4 ${dsp-destA},${s1-direct-addr},${dsp-S2-acc-reg-mul} */
32420 +  {
32421 +    { 0, 0, 0, 0 },
32422 +    { { MNEM, ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
32423 +    & ifmt_dsp_mulu_4_s1_direct_dsp_src2_reg_acc_reg_mul, { 0x35440100 }
32424 +  },
32425 +/* mulu.4 ${dsp-destA},#${s1-imm8},${dsp-S2-acc-reg-mul} */
32426 +  {
32427 +    { 0, 0, 0, 0 },
32428 +    { { MNEM, ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
32429 +    & ifmt_dsp_mulu_4_s1_immediate_dsp_src2_reg_acc_reg_mul, { 0x35440000 }
32430 +  },
32431 +/* mulu.4 ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-acc-reg-mul} */
32432 +  {
32433 +    { 0, 0, 0, 0 },
32434 +    { { MNEM, ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
32435 +    & ifmt_dsp_mulu_4_s1_indirect_with_index_4_dsp_src2_reg_acc_reg_mul, { 0x35440300 }
32436 +  },
32437 +/* mulu.4 ${dsp-destA},${s1-imm7-4}(${s1-An}),${dsp-S2-acc-reg-mul} */
32438 +  {
32439 +    { 0, 0, 0, 0 },
32440 +    { { MNEM, ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
32441 +    & ifmt_dsp_mulu_4_s1_indirect_with_offset_4_dsp_src2_reg_acc_reg_mul, { 0x35440400 }
32442 +  },
32443 +/* mulu.4 ${dsp-destA},(${s1-An}),${dsp-S2-acc-reg-mul} */
32444 +  {
32445 +    { 0, 0, 0, 0 },
32446 +    { { MNEM, ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
32447 +    & ifmt_dsp_mulu_4_s1_indirect_4_dsp_src2_reg_acc_reg_mul, { 0x35440400 }
32448 +  },
32449 +/* mulu.4 ${dsp-destA},(${s1-An})${s1-i4-4}++,${dsp-S2-acc-reg-mul} */
32450 +  {
32451 +    { 0, 0, 0, 0 },
32452 +    { { MNEM, ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
32453 +    & ifmt_dsp_mulu_4_s1_indirect_with_post_increment_4_dsp_src2_reg_acc_reg_mul, { 0x35440200 }
32454 +  },
32455 +/* mulu.4 ${dsp-destA},${s1-i4-4}(${s1-An})++,${dsp-S2-acc-reg-mul} */
32456 +  {
32457 +    { 0, 0, 0, 0 },
32458 +    { { MNEM, ' ', OP (DSP_DESTA), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
32459 +    & ifmt_dsp_mulu_4_s1_indirect_with_pre_increment_4_dsp_src2_reg_acc_reg_mul, { 0x35440210 }
32460 +  },
32461 +/* mulu.4 ${dsp-destA},${s1-direct-addr},#${bit5} */
32462 +  {
32463 +    { 0, 0, 0, 0 },
32464 +    { { MNEM, ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } },
32465 +    & ifmt_dsp_mulu_4_s1_direct_dsp_imm_bit5, { 0x31400100 }
32466 +  },
32467 +/* mulu.4 ${dsp-destA},#${s1-imm8},#${bit5} */
32468 +  {
32469 +    { 0, 0, 0, 0 },
32470 +    { { MNEM, ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } },
32471 +    & ifmt_dsp_mulu_4_s1_immediate_dsp_imm_bit5, { 0x31400000 }
32472 +  },
32473 +/* mulu.4 ${dsp-destA},(${s1-An},${s1-r}),#${bit5} */
32474 +  {
32475 +    { 0, 0, 0, 0 },
32476 +    { { MNEM, ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } },
32477 +    & ifmt_dsp_mulu_4_s1_indirect_with_index_4_dsp_imm_bit5, { 0x31400300 }
32478 +  },
32479 +/* mulu.4 ${dsp-destA},${s1-imm7-4}(${s1-An}),#${bit5} */
32480 +  {
32481 +    { 0, 0, 0, 0 },
32482 +    { { MNEM, ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
32483 +    & ifmt_dsp_mulu_4_s1_indirect_with_offset_4_dsp_imm_bit5, { 0x31400400 }
32484 +  },
32485 +/* mulu.4 ${dsp-destA},(${s1-An}),#${bit5} */
32486 +  {
32487 +    { 0, 0, 0, 0 },
32488 +    { { MNEM, ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
32489 +    & ifmt_dsp_mulu_4_s1_indirect_4_dsp_imm_bit5, { 0x31400400 }
32490 +  },
32491 +/* mulu.4 ${dsp-destA},(${s1-An})${s1-i4-4}++,#${bit5} */
32492 +  {
32493 +    { 0, 0, 0, 0 },
32494 +    { { MNEM, ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', '#', OP (BIT5), 0 } },
32495 +    & ifmt_dsp_mulu_4_s1_indirect_with_post_increment_4_dsp_imm_bit5, { 0x31400200 }
32496 +  },
32497 +/* mulu.4 ${dsp-destA},${s1-i4-4}(${s1-An})++,#${bit5} */
32498 +  {
32499 +    { 0, 0, 0, 0 },
32500 +    { { MNEM, ' ', OP (DSP_DESTA), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } },
32501 +    & ifmt_dsp_mulu_4_s1_indirect_with_pre_increment_4_dsp_imm_bit5, { 0x31400210 }
32502 +  },
32503 +/* mulu${dsp-t} ${dsp-destA},${s1-direct-addr},${dsp-S2-data-reg} */
32504 +  {
32505 +    { 0, 0, 0, 0 },
32506 +    { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_DATA_REG), 0 } },
32507 +    & ifmt_dsp_mulu_s1_direct_dsp_src2_data_reg, { 0x34400100 }
32508 +  },
32509 +/* mulu${dsp-t} ${dsp-destA},#${s1-imm8},${dsp-S2-data-reg} */
32510 +  {
32511 +    { 0, 0, 0, 0 },
32512 +    { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', OP (DSP_S2_DATA_REG), 0 } },
32513 +    & ifmt_dsp_mulu_s1_immediate_dsp_src2_data_reg, { 0x34400000 }
32514 +  },
32515 +/* mulu${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-data-reg} */
32516 +  {
32517 +    { 0, 0, 0, 0 },
32518 +    { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_DATA_REG), 0 } },
32519 +    & ifmt_dsp_mulu_s1_indirect_with_index_2_dsp_src2_data_reg, { 0x34400300 }
32520 +  },
32521 +/* mulu${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),${dsp-S2-data-reg} */
32522 +  {
32523 +    { 0, 0, 0, 0 },
32524 +    { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG), 0 } },
32525 +    & ifmt_dsp_mulu_s1_indirect_with_offset_2_dsp_src2_data_reg, { 0x34400400 }
32526 +  },
32527 +/* mulu${dsp-t} ${dsp-destA},(${s1-An}),${dsp-S2-data-reg} */
32528 +  {
32529 +    { 0, 0, 0, 0 },
32530 +    { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG), 0 } },
32531 +    & ifmt_dsp_mulu_s1_indirect_2_dsp_src2_data_reg, { 0x34400400 }
32532 +  },
32533 +/* mulu${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,${dsp-S2-data-reg} */
32534 +  {
32535 +    { 0, 0, 0, 0 },
32536 +    { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (DSP_S2_DATA_REG), 0 } },
32537 +    & ifmt_dsp_mulu_s1_indirect_with_post_increment_2_dsp_src2_data_reg, { 0x34400200 }
32538 +  },
32539 +/* mulu${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,${dsp-S2-data-reg} */
32540 +  {
32541 +    { 0, 0, 0, 0 },
32542 +    { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_DATA_REG), 0 } },
32543 +    & ifmt_dsp_mulu_s1_indirect_with_pre_increment_2_dsp_src2_data_reg, { 0x34400210 }
32544 +  },
32545 +/* mulu${dsp-t} ${dsp-destA},${s1-direct-addr},${dsp-S2-acc-reg-mul} */
32546 +  {
32547 +    { 0, 0, 0, 0 },
32548 +    { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
32549 +    & ifmt_dsp_mulu_s1_direct_dsp_src2_reg_acc_reg_mul, { 0x34440100 }
32550 +  },
32551 +/* mulu${dsp-t} ${dsp-destA},#${s1-imm8},${dsp-S2-acc-reg-mul} */
32552 +  {
32553 +    { 0, 0, 0, 0 },
32554 +    { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
32555 +    & ifmt_dsp_mulu_s1_immediate_dsp_src2_reg_acc_reg_mul, { 0x34440000 }
32556 +  },
32557 +/* mulu${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-acc-reg-mul} */
32558 +  {
32559 +    { 0, 0, 0, 0 },
32560 +    { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
32561 +    & ifmt_dsp_mulu_s1_indirect_with_index_2_dsp_src2_reg_acc_reg_mul, { 0x34440300 }
32562 +  },
32563 +/* mulu${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),${dsp-S2-acc-reg-mul} */
32564 +  {
32565 +    { 0, 0, 0, 0 },
32566 +    { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
32567 +    & ifmt_dsp_mulu_s1_indirect_with_offset_2_dsp_src2_reg_acc_reg_mul, { 0x34440400 }
32568 +  },
32569 +/* mulu${dsp-t} ${dsp-destA},(${s1-An}),${dsp-S2-acc-reg-mul} */
32570 +  {
32571 +    { 0, 0, 0, 0 },
32572 +    { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
32573 +    & ifmt_dsp_mulu_s1_indirect_2_dsp_src2_reg_acc_reg_mul, { 0x34440400 }
32574 +  },
32575 +/* mulu${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,${dsp-S2-acc-reg-mul} */
32576 +  {
32577 +    { 0, 0, 0, 0 },
32578 +    { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
32579 +    & ifmt_dsp_mulu_s1_indirect_with_post_increment_2_dsp_src2_reg_acc_reg_mul, { 0x34440200 }
32580 +  },
32581 +/* mulu${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,${dsp-S2-acc-reg-mul} */
32582 +  {
32583 +    { 0, 0, 0, 0 },
32584 +    { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
32585 +    & ifmt_dsp_mulu_s1_indirect_with_pre_increment_2_dsp_src2_reg_acc_reg_mul, { 0x34440210 }
32586 +  },
32587 +/* mulu${dsp-t} ${dsp-destA},${s1-direct-addr},#${bit5} */
32588 +  {
32589 +    { 0, 0, 0, 0 },
32590 +    { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } },
32591 +    & ifmt_dsp_mulu_s1_direct_dsp_imm_bit5, { 0x30400100 }
32592 +  },
32593 +/* mulu${dsp-t} ${dsp-destA},#${s1-imm8},#${bit5} */
32594 +  {
32595 +    { 0, 0, 0, 0 },
32596 +    { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } },
32597 +    & ifmt_dsp_mulu_s1_immediate_dsp_imm_bit5, { 0x30400000 }
32598 +  },
32599 +/* mulu${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),#${bit5} */
32600 +  {
32601 +    { 0, 0, 0, 0 },
32602 +    { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } },
32603 +    & ifmt_dsp_mulu_s1_indirect_with_index_2_dsp_imm_bit5, { 0x30400300 }
32604 +  },
32605 +/* mulu${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),#${bit5} */
32606 +  {
32607 +    { 0, 0, 0, 0 },
32608 +    { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
32609 +    & ifmt_dsp_mulu_s1_indirect_with_offset_2_dsp_imm_bit5, { 0x30400400 }
32610 +  },
32611 +/* mulu${dsp-t} ${dsp-destA},(${s1-An}),#${bit5} */
32612 +  {
32613 +    { 0, 0, 0, 0 },
32614 +    { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
32615 +    & ifmt_dsp_mulu_s1_indirect_2_dsp_imm_bit5, { 0x30400400 }
32616 +  },
32617 +/* mulu${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,#${bit5} */
32618 +  {
32619 +    { 0, 0, 0, 0 },
32620 +    { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', '#', OP (BIT5), 0 } },
32621 +    & ifmt_dsp_mulu_s1_indirect_with_post_increment_2_dsp_imm_bit5, { 0x30400200 }
32622 +  },
32623 +/* mulu${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,#${bit5} */
32624 +  {
32625 +    { 0, 0, 0, 0 },
32626 +    { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } },
32627 +    & ifmt_dsp_mulu_s1_indirect_with_pre_increment_2_dsp_imm_bit5, { 0x30400210 }
32628 +  },
32629 +/* macs${dsp-c}${dsp-t} ${dsp-destA},${s1-direct-addr},${dsp-S2-data-reg} */
32630 +  {
32631 +    { 0, 0, 0, 0 },
32632 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_DATA_REG), 0 } },
32633 +    & ifmt_dsp_msuf_s1_direct_dsp_src2_data_reg, { 0x34200100 }
32634 +  },
32635 +/* macs${dsp-c}${dsp-t} ${dsp-destA},#${s1-imm8},${dsp-S2-data-reg} */
32636 +  {
32637 +    { 0, 0, 0, 0 },
32638 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', OP (DSP_S2_DATA_REG), 0 } },
32639 +    & ifmt_dsp_msuf_s1_immediate_dsp_src2_data_reg, { 0x34200000 }
32640 +  },
32641 +/* macs${dsp-c}${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-data-reg} */
32642 +  {
32643 +    { 0, 0, 0, 0 },
32644 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_DATA_REG), 0 } },
32645 +    & ifmt_dsp_msuf_s1_indirect_with_index_2_dsp_src2_data_reg, { 0x34200300 }
32646 +  },
32647 +/* macs${dsp-c}${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),${dsp-S2-data-reg} */
32648 +  {
32649 +    { 0, 0, 0, 0 },
32650 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG), 0 } },
32651 +    & ifmt_dsp_msuf_s1_indirect_with_offset_2_dsp_src2_data_reg, { 0x34200400 }
32652 +  },
32653 +/* macs${dsp-c}${dsp-t} ${dsp-destA},(${s1-An}),${dsp-S2-data-reg} */
32654 +  {
32655 +    { 0, 0, 0, 0 },
32656 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG), 0 } },
32657 +    & ifmt_dsp_msuf_s1_indirect_2_dsp_src2_data_reg, { 0x34200400 }
32658 +  },
32659 +/* macs${dsp-c}${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,${dsp-S2-data-reg} */
32660 +  {
32661 +    { 0, 0, 0, 0 },
32662 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (DSP_S2_DATA_REG), 0 } },
32663 +    & ifmt_dsp_msuf_s1_indirect_with_post_increment_2_dsp_src2_data_reg, { 0x34200200 }
32664 +  },
32665 +/* macs${dsp-c}${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,${dsp-S2-data-reg} */
32666 +  {
32667 +    { 0, 0, 0, 0 },
32668 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_DATA_REG), 0 } },
32669 +    & ifmt_dsp_msuf_s1_indirect_with_pre_increment_2_dsp_src2_data_reg, { 0x34200210 }
32670 +  },
32671 +/* macs${dsp-c}${dsp-t} ${dsp-destA},${s1-direct-addr},${dsp-S2-acc-reg-mul} */
32672 +  {
32673 +    { 0, 0, 0, 0 },
32674 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
32675 +    & ifmt_dsp_msuf_s1_direct_dsp_src2_reg_acc_reg_mul, { 0x34240100 }
32676 +  },
32677 +/* macs${dsp-c}${dsp-t} ${dsp-destA},#${s1-imm8},${dsp-S2-acc-reg-mul} */
32678 +  {
32679 +    { 0, 0, 0, 0 },
32680 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
32681 +    & ifmt_dsp_msuf_s1_immediate_dsp_src2_reg_acc_reg_mul, { 0x34240000 }
32682 +  },
32683 +/* macs${dsp-c}${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-acc-reg-mul} */
32684 +  {
32685 +    { 0, 0, 0, 0 },
32686 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
32687 +    & ifmt_dsp_msuf_s1_indirect_with_index_2_dsp_src2_reg_acc_reg_mul, { 0x34240300 }
32688 +  },
32689 +/* macs${dsp-c}${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),${dsp-S2-acc-reg-mul} */
32690 +  {
32691 +    { 0, 0, 0, 0 },
32692 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
32693 +    & ifmt_dsp_msuf_s1_indirect_with_offset_2_dsp_src2_reg_acc_reg_mul, { 0x34240400 }
32694 +  },
32695 +/* macs${dsp-c}${dsp-t} ${dsp-destA},(${s1-An}),${dsp-S2-acc-reg-mul} */
32696 +  {
32697 +    { 0, 0, 0, 0 },
32698 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
32699 +    & ifmt_dsp_msuf_s1_indirect_2_dsp_src2_reg_acc_reg_mul, { 0x34240400 }
32700 +  },
32701 +/* macs${dsp-c}${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,${dsp-S2-acc-reg-mul} */
32702 +  {
32703 +    { 0, 0, 0, 0 },
32704 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
32705 +    & ifmt_dsp_msuf_s1_indirect_with_post_increment_2_dsp_src2_reg_acc_reg_mul, { 0x34240200 }
32706 +  },
32707 +/* macs${dsp-c}${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,${dsp-S2-acc-reg-mul} */
32708 +  {
32709 +    { 0, 0, 0, 0 },
32710 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
32711 +    & ifmt_dsp_msuf_s1_indirect_with_pre_increment_2_dsp_src2_reg_acc_reg_mul, { 0x34240210 }
32712 +  },
32713 +/* macs${dsp-c}${dsp-t} ${dsp-destA},${s1-direct-addr},#${bit5} */
32714 +  {
32715 +    { 0, 0, 0, 0 },
32716 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } },
32717 +    & ifmt_dsp_msuf_s1_direct_dsp_imm_bit5, { 0x30200100 }
32718 +  },
32719 +/* macs${dsp-c}${dsp-t} ${dsp-destA},#${s1-imm8},#${bit5} */
32720 +  {
32721 +    { 0, 0, 0, 0 },
32722 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } },
32723 +    & ifmt_dsp_msuf_s1_immediate_dsp_imm_bit5, { 0x30200000 }
32724 +  },
32725 +/* macs${dsp-c}${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),#${bit5} */
32726 +  {
32727 +    { 0, 0, 0, 0 },
32728 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } },
32729 +    & ifmt_dsp_msuf_s1_indirect_with_index_2_dsp_imm_bit5, { 0x30200300 }
32730 +  },
32731 +/* macs${dsp-c}${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),#${bit5} */
32732 +  {
32733 +    { 0, 0, 0, 0 },
32734 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
32735 +    & ifmt_dsp_msuf_s1_indirect_with_offset_2_dsp_imm_bit5, { 0x30200400 }
32736 +  },
32737 +/* macs${dsp-c}${dsp-t} ${dsp-destA},(${s1-An}),#${bit5} */
32738 +  {
32739 +    { 0, 0, 0, 0 },
32740 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
32741 +    & ifmt_dsp_msuf_s1_indirect_2_dsp_imm_bit5, { 0x30200400 }
32742 +  },
32743 +/* macs${dsp-c}${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,#${bit5} */
32744 +  {
32745 +    { 0, 0, 0, 0 },
32746 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', '#', OP (BIT5), 0 } },
32747 +    & ifmt_dsp_msuf_s1_indirect_with_post_increment_2_dsp_imm_bit5, { 0x30200200 }
32748 +  },
32749 +/* macs${dsp-c}${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,#${bit5} */
32750 +  {
32751 +    { 0, 0, 0, 0 },
32752 +    { { MNEM, OP (DSP_C), OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } },
32753 +    & ifmt_dsp_msuf_s1_indirect_with_pre_increment_2_dsp_imm_bit5, { 0x30200210 }
32754 +  },
32755 +/* muls.4 ${dsp-destA},${s1-direct-addr},${dsp-S2-data-reg} */
32756 +  {
32757 +    { 0, 0, 0, 0 },
32758 +    { { MNEM, ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_DATA_REG), 0 } },
32759 +    & ifmt_dsp_mulu_4_s1_direct_dsp_src2_data_reg, { 0x35000100 }
32760 +  },
32761 +/* muls.4 ${dsp-destA},#${s1-imm8},${dsp-S2-data-reg} */
32762 +  {
32763 +    { 0, 0, 0, 0 },
32764 +    { { MNEM, ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', OP (DSP_S2_DATA_REG), 0 } },
32765 +    & ifmt_dsp_mulu_4_s1_immediate_dsp_src2_data_reg, { 0x35000000 }
32766 +  },
32767 +/* muls.4 ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-data-reg} */
32768 +  {
32769 +    { 0, 0, 0, 0 },
32770 +    { { MNEM, ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_DATA_REG), 0 } },
32771 +    & ifmt_dsp_mulu_4_s1_indirect_with_index_4_dsp_src2_data_reg, { 0x35000300 }
32772 +  },
32773 +/* muls.4 ${dsp-destA},${s1-imm7-4}(${s1-An}),${dsp-S2-data-reg} */
32774 +  {
32775 +    { 0, 0, 0, 0 },
32776 +    { { MNEM, ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG), 0 } },
32777 +    & ifmt_dsp_mulu_4_s1_indirect_with_offset_4_dsp_src2_data_reg, { 0x35000400 }
32778 +  },
32779 +/* muls.4 ${dsp-destA},(${s1-An}),${dsp-S2-data-reg} */
32780 +  {
32781 +    { 0, 0, 0, 0 },
32782 +    { { MNEM, ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG), 0 } },
32783 +    & ifmt_dsp_mulu_4_s1_indirect_4_dsp_src2_data_reg, { 0x35000400 }
32784 +  },
32785 +/* muls.4 ${dsp-destA},(${s1-An})${s1-i4-4}++,${dsp-S2-data-reg} */
32786 +  {
32787 +    { 0, 0, 0, 0 },
32788 +    { { MNEM, ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (DSP_S2_DATA_REG), 0 } },
32789 +    & ifmt_dsp_mulu_4_s1_indirect_with_post_increment_4_dsp_src2_data_reg, { 0x35000200 }
32790 +  },
32791 +/* muls.4 ${dsp-destA},${s1-i4-4}(${s1-An})++,${dsp-S2-data-reg} */
32792 +  {
32793 +    { 0, 0, 0, 0 },
32794 +    { { MNEM, ' ', OP (DSP_DESTA), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_DATA_REG), 0 } },
32795 +    & ifmt_dsp_mulu_4_s1_indirect_with_pre_increment_4_dsp_src2_data_reg, { 0x35000210 }
32796 +  },
32797 +/* muls.4 ${dsp-destA},${s1-direct-addr},${dsp-S2-acc-reg-mul} */
32798 +  {
32799 +    { 0, 0, 0, 0 },
32800 +    { { MNEM, ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
32801 +    & ifmt_dsp_mulu_4_s1_direct_dsp_src2_reg_acc_reg_mul, { 0x35040100 }
32802 +  },
32803 +/* muls.4 ${dsp-destA},#${s1-imm8},${dsp-S2-acc-reg-mul} */
32804 +  {
32805 +    { 0, 0, 0, 0 },
32806 +    { { MNEM, ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
32807 +    & ifmt_dsp_mulu_4_s1_immediate_dsp_src2_reg_acc_reg_mul, { 0x35040000 }
32808 +  },
32809 +/* muls.4 ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-acc-reg-mul} */
32810 +  {
32811 +    { 0, 0, 0, 0 },
32812 +    { { MNEM, ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
32813 +    & ifmt_dsp_mulu_4_s1_indirect_with_index_4_dsp_src2_reg_acc_reg_mul, { 0x35040300 }
32814 +  },
32815 +/* muls.4 ${dsp-destA},${s1-imm7-4}(${s1-An}),${dsp-S2-acc-reg-mul} */
32816 +  {
32817 +    { 0, 0, 0, 0 },
32818 +    { { MNEM, ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
32819 +    & ifmt_dsp_mulu_4_s1_indirect_with_offset_4_dsp_src2_reg_acc_reg_mul, { 0x35040400 }
32820 +  },
32821 +/* muls.4 ${dsp-destA},(${s1-An}),${dsp-S2-acc-reg-mul} */
32822 +  {
32823 +    { 0, 0, 0, 0 },
32824 +    { { MNEM, ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
32825 +    & ifmt_dsp_mulu_4_s1_indirect_4_dsp_src2_reg_acc_reg_mul, { 0x35040400 }
32826 +  },
32827 +/* muls.4 ${dsp-destA},(${s1-An})${s1-i4-4}++,${dsp-S2-acc-reg-mul} */
32828 +  {
32829 +    { 0, 0, 0, 0 },
32830 +    { { MNEM, ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
32831 +    & ifmt_dsp_mulu_4_s1_indirect_with_post_increment_4_dsp_src2_reg_acc_reg_mul, { 0x35040200 }
32832 +  },
32833 +/* muls.4 ${dsp-destA},${s1-i4-4}(${s1-An})++,${dsp-S2-acc-reg-mul} */
32834 +  {
32835 +    { 0, 0, 0, 0 },
32836 +    { { MNEM, ' ', OP (DSP_DESTA), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
32837 +    & ifmt_dsp_mulu_4_s1_indirect_with_pre_increment_4_dsp_src2_reg_acc_reg_mul, { 0x35040210 }
32838 +  },
32839 +/* muls.4 ${dsp-destA},${s1-direct-addr},#${bit5} */
32840 +  {
32841 +    { 0, 0, 0, 0 },
32842 +    { { MNEM, ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } },
32843 +    & ifmt_dsp_mulu_4_s1_direct_dsp_imm_bit5, { 0x31000100 }
32844 +  },
32845 +/* muls.4 ${dsp-destA},#${s1-imm8},#${bit5} */
32846 +  {
32847 +    { 0, 0, 0, 0 },
32848 +    { { MNEM, ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } },
32849 +    & ifmt_dsp_mulu_4_s1_immediate_dsp_imm_bit5, { 0x31000000 }
32850 +  },
32851 +/* muls.4 ${dsp-destA},(${s1-An},${s1-r}),#${bit5} */
32852 +  {
32853 +    { 0, 0, 0, 0 },
32854 +    { { MNEM, ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } },
32855 +    & ifmt_dsp_mulu_4_s1_indirect_with_index_4_dsp_imm_bit5, { 0x31000300 }
32856 +  },
32857 +/* muls.4 ${dsp-destA},${s1-imm7-4}(${s1-An}),#${bit5} */
32858 +  {
32859 +    { 0, 0, 0, 0 },
32860 +    { { MNEM, ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
32861 +    & ifmt_dsp_mulu_4_s1_indirect_with_offset_4_dsp_imm_bit5, { 0x31000400 }
32862 +  },
32863 +/* muls.4 ${dsp-destA},(${s1-An}),#${bit5} */
32864 +  {
32865 +    { 0, 0, 0, 0 },
32866 +    { { MNEM, ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
32867 +    & ifmt_dsp_mulu_4_s1_indirect_4_dsp_imm_bit5, { 0x31000400 }
32868 +  },
32869 +/* muls.4 ${dsp-destA},(${s1-An})${s1-i4-4}++,#${bit5} */
32870 +  {
32871 +    { 0, 0, 0, 0 },
32872 +    { { MNEM, ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', '#', OP (BIT5), 0 } },
32873 +    & ifmt_dsp_mulu_4_s1_indirect_with_post_increment_4_dsp_imm_bit5, { 0x31000200 }
32874 +  },
32875 +/* muls.4 ${dsp-destA},${s1-i4-4}(${s1-An})++,#${bit5} */
32876 +  {
32877 +    { 0, 0, 0, 0 },
32878 +    { { MNEM, ' ', OP (DSP_DESTA), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } },
32879 +    & ifmt_dsp_mulu_4_s1_indirect_with_pre_increment_4_dsp_imm_bit5, { 0x31000210 }
32880 +  },
32881 +/* muls${dsp-t} ${dsp-destA},${s1-direct-addr},${dsp-S2-data-reg} */
32882 +  {
32883 +    { 0, 0, 0, 0 },
32884 +    { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_DATA_REG), 0 } },
32885 +    & ifmt_dsp_mulu_s1_direct_dsp_src2_data_reg, { 0x34000100 }
32886 +  },
32887 +/* muls${dsp-t} ${dsp-destA},#${s1-imm8},${dsp-S2-data-reg} */
32888 +  {
32889 +    { 0, 0, 0, 0 },
32890 +    { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', OP (DSP_S2_DATA_REG), 0 } },
32891 +    & ifmt_dsp_mulu_s1_immediate_dsp_src2_data_reg, { 0x34000000 }
32892 +  },
32893 +/* muls${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-data-reg} */
32894 +  {
32895 +    { 0, 0, 0, 0 },
32896 +    { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_DATA_REG), 0 } },
32897 +    & ifmt_dsp_mulu_s1_indirect_with_index_2_dsp_src2_data_reg, { 0x34000300 }
32898 +  },
32899 +/* muls${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),${dsp-S2-data-reg} */
32900 +  {
32901 +    { 0, 0, 0, 0 },
32902 +    { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG), 0 } },
32903 +    & ifmt_dsp_mulu_s1_indirect_with_offset_2_dsp_src2_data_reg, { 0x34000400 }
32904 +  },
32905 +/* muls${dsp-t} ${dsp-destA},(${s1-An}),${dsp-S2-data-reg} */
32906 +  {
32907 +    { 0, 0, 0, 0 },
32908 +    { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG), 0 } },
32909 +    & ifmt_dsp_mulu_s1_indirect_2_dsp_src2_data_reg, { 0x34000400 }
32910 +  },
32911 +/* muls${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,${dsp-S2-data-reg} */
32912 +  {
32913 +    { 0, 0, 0, 0 },
32914 +    { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (DSP_S2_DATA_REG), 0 } },
32915 +    & ifmt_dsp_mulu_s1_indirect_with_post_increment_2_dsp_src2_data_reg, { 0x34000200 }
32916 +  },
32917 +/* muls${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,${dsp-S2-data-reg} */
32918 +  {
32919 +    { 0, 0, 0, 0 },
32920 +    { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_DATA_REG), 0 } },
32921 +    & ifmt_dsp_mulu_s1_indirect_with_pre_increment_2_dsp_src2_data_reg, { 0x34000210 }
32922 +  },
32923 +/* muls${dsp-t} ${dsp-destA},${s1-direct-addr},${dsp-S2-acc-reg-mul} */
32924 +  {
32925 +    { 0, 0, 0, 0 },
32926 +    { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
32927 +    & ifmt_dsp_mulu_s1_direct_dsp_src2_reg_acc_reg_mul, { 0x34040100 }
32928 +  },
32929 +/* muls${dsp-t} ${dsp-destA},#${s1-imm8},${dsp-S2-acc-reg-mul} */
32930 +  {
32931 +    { 0, 0, 0, 0 },
32932 +    { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
32933 +    & ifmt_dsp_mulu_s1_immediate_dsp_src2_reg_acc_reg_mul, { 0x34040000 }
32934 +  },
32935 +/* muls${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),${dsp-S2-acc-reg-mul} */
32936 +  {
32937 +    { 0, 0, 0, 0 },
32938 +    { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
32939 +    & ifmt_dsp_mulu_s1_indirect_with_index_2_dsp_src2_reg_acc_reg_mul, { 0x34040300 }
32940 +  },
32941 +/* muls${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),${dsp-S2-acc-reg-mul} */
32942 +  {
32943 +    { 0, 0, 0, 0 },
32944 +    { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
32945 +    & ifmt_dsp_mulu_s1_indirect_with_offset_2_dsp_src2_reg_acc_reg_mul, { 0x34040400 }
32946 +  },
32947 +/* muls${dsp-t} ${dsp-destA},(${s1-An}),${dsp-S2-acc-reg-mul} */
32948 +  {
32949 +    { 0, 0, 0, 0 },
32950 +    { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
32951 +    & ifmt_dsp_mulu_s1_indirect_2_dsp_src2_reg_acc_reg_mul, { 0x34040400 }
32952 +  },
32953 +/* muls${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,${dsp-S2-acc-reg-mul} */
32954 +  {
32955 +    { 0, 0, 0, 0 },
32956 +    { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
32957 +    & ifmt_dsp_mulu_s1_indirect_with_post_increment_2_dsp_src2_reg_acc_reg_mul, { 0x34040200 }
32958 +  },
32959 +/* muls${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,${dsp-S2-acc-reg-mul} */
32960 +  {
32961 +    { 0, 0, 0, 0 },
32962 +    { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_ACC_REG_MUL), 0 } },
32963 +    & ifmt_dsp_mulu_s1_indirect_with_pre_increment_2_dsp_src2_reg_acc_reg_mul, { 0x34040210 }
32964 +  },
32965 +/* muls${dsp-t} ${dsp-destA},${s1-direct-addr},#${bit5} */
32966 +  {
32967 +    { 0, 0, 0, 0 },
32968 +    { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } },
32969 +    & ifmt_dsp_mulu_s1_direct_dsp_imm_bit5, { 0x30000100 }
32970 +  },
32971 +/* muls${dsp-t} ${dsp-destA},#${s1-imm8},#${bit5} */
32972 +  {
32973 +    { 0, 0, 0, 0 },
32974 +    { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } },
32975 +    & ifmt_dsp_mulu_s1_immediate_dsp_imm_bit5, { 0x30000000 }
32976 +  },
32977 +/* muls${dsp-t} ${dsp-destA},(${s1-An},${s1-r}),#${bit5} */
32978 +  {
32979 +    { 0, 0, 0, 0 },
32980 +    { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } },
32981 +    & ifmt_dsp_mulu_s1_indirect_with_index_2_dsp_imm_bit5, { 0x30000300 }
32982 +  },
32983 +/* muls${dsp-t} ${dsp-destA},${s1-imm7-2}(${s1-An}),#${bit5} */
32984 +  {
32985 +    { 0, 0, 0, 0 },
32986 +    { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
32987 +    & ifmt_dsp_mulu_s1_indirect_with_offset_2_dsp_imm_bit5, { 0x30000400 }
32988 +  },
32989 +/* muls${dsp-t} ${dsp-destA},(${s1-An}),#${bit5} */
32990 +  {
32991 +    { 0, 0, 0, 0 },
32992 +    { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
32993 +    & ifmt_dsp_mulu_s1_indirect_2_dsp_imm_bit5, { 0x30000400 }
32994 +  },
32995 +/* muls${dsp-t} ${dsp-destA},(${s1-An})${s1-i4-2}++,#${bit5} */
32996 +  {
32997 +    { 0, 0, 0, 0 },
32998 +    { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', '#', OP (BIT5), 0 } },
32999 +    & ifmt_dsp_mulu_s1_indirect_with_post_increment_2_dsp_imm_bit5, { 0x30000200 }
33000 +  },
33001 +/* muls${dsp-t} ${dsp-destA},${s1-i4-2}(${s1-An})++,#${bit5} */
33002 +  {
33003 +    { 0, 0, 0, 0 },
33004 +    { { MNEM, OP (DSP_T), ' ', OP (DSP_DESTA), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } },
33005 +    & ifmt_dsp_mulu_s1_indirect_with_pre_increment_2_dsp_imm_bit5, { 0x30000210 }
33006 +  },
33007 +/* ierase (${d-An},${d-r}) */
33008 +  {
33009 +    { 0, 0, 0, 0 },
33010 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', 0 } },
33011 +    & ifmt_ierase_d_pea_indirect_with_index, { 0x3002800 }
33012 +  },
33013 +/* ierase ${d-imm7-4}(${d-An}) */
33014 +  {
33015 +    { 0, 0, 0, 0 },
33016 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', 0 } },
33017 +    & ifmt_ierase_d_pea_indirect_with_offset, { 0x4002800 }
33018 +  },
33019 +/* ierase (${d-An}) */
33020 +  {
33021 +    { 0, 0, 0, 0 },
33022 +    { { MNEM, ' ', '(', OP (D_AN), ')', 0 } },
33023 +    & ifmt_ierase_d_pea_indirect, { 0x4002800 }
33024 +  },
33025 +/* ierase (${d-An})${d-i4-4}++ */
33026 +  {
33027 +    { 0, 0, 0, 0 },
33028 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', 0 } },
33029 +    & ifmt_ierase_d_pea_indirect_with_post_increment, { 0x2002800 }
33030 +  },
33031 +/* ierase ${d-i4-4}(${d-An})++ */
33032 +  {
33033 +    { 0, 0, 0, 0 },
33034 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', 0 } },
33035 +    & ifmt_ierase_d_pea_indirect_with_pre_increment, { 0x2102800 }
33036 +  },
33037 +/* iread (${s1-An}) */
33038 +  {
33039 +    { 0, 0, 0, 0 },
33040 +    { { MNEM, ' ', '(', OP (S1_AN), ')', 0 } },
33041 +    & ifmt_iread_s1_ea_indirect, { 0x3400 }
33042 +  },
33043 +/* iread (${s1-An},${s1-r}) */
33044 +  {
33045 +    { 0, 0, 0, 0 },
33046 +    { { MNEM, ' ', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
33047 +    & ifmt_iread_s1_ea_indirect_with_index_4, { 0x3300 }
33048 +  },
33049 +/* iread (${s1-An})${s1-i4-4}++ */
33050 +  {
33051 +    { 0, 0, 0, 0 },
33052 +    { { MNEM, ' ', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
33053 +    & ifmt_iread_s1_ea_indirect_with_post_increment_4, { 0x3200 }
33054 +  },
33055 +/* iread ${s1-i4-4}(${s1-An})++ */
33056 +  {
33057 +    { 0, 0, 0, 0 },
33058 +    { { MNEM, ' ', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
33059 +    & ifmt_iread_s1_ea_indirect_with_pre_increment_4, { 0x3210 }
33060 +  },
33061 +/* iread ${s1-imm7-4}(${s1-An}) */
33062 +  {
33063 +    { 0, 0, 0, 0 },
33064 +    { { MNEM, ' ', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
33065 +    & ifmt_iread_s1_ea_indirect_with_offset_4, { 0x3400 }
33066 +  },
33067 +/* iwrite (${d-An},${d-r}),${s1-direct-addr} */
33068 +  {
33069 +    { 0, 0, 0, 0 },
33070 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), 0 } },
33071 +    & ifmt_iwrite_d_pea_indirect_with_index_s1_direct, { 0x3008100 }
33072 +  },
33073 +/* iwrite ${d-imm7-4}(${d-An}),${s1-direct-addr} */
33074 +  {
33075 +    { 0, 0, 0, 0 },
33076 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), 0 } },
33077 +    & ifmt_iwrite_d_pea_indirect_with_offset_s1_direct, { 0x4008100 }
33078 +  },
33079 +/* iwrite (${d-An}),${s1-direct-addr} */
33080 +  {
33081 +    { 0, 0, 0, 0 },
33082 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), 0 } },
33083 +    & ifmt_iwrite_d_pea_indirect_s1_direct, { 0x4008100 }
33084 +  },
33085 +/* iwrite (${d-An})${d-i4-4}++,${s1-direct-addr} */
33086 +  {
33087 +    { 0, 0, 0, 0 },
33088 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_DIRECT_ADDR), 0 } },
33089 +    & ifmt_iwrite_d_pea_indirect_with_post_increment_s1_direct, { 0x2008100 }
33090 +  },
33091 +/* iwrite ${d-i4-4}(${d-An})++,${s1-direct-addr} */
33092 +  {
33093 +    { 0, 0, 0, 0 },
33094 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), 0 } },
33095 +    & ifmt_iwrite_d_pea_indirect_with_pre_increment_s1_direct, { 0x2108100 }
33096 +  },
33097 +/* iwrite (${d-An},${d-r}),#${s1-imm8} */
33098 +  {
33099 +    { 0, 0, 0, 0 },
33100 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), 0 } },
33101 +    & ifmt_iwrite_d_pea_indirect_with_index_s1_immediate, { 0x3008000 }
33102 +  },
33103 +/* iwrite ${d-imm7-4}(${d-An}),#${s1-imm8} */
33104 +  {
33105 +    { 0, 0, 0, 0 },
33106 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } },
33107 +    & ifmt_iwrite_d_pea_indirect_with_offset_s1_immediate, { 0x4008000 }
33108 +  },
33109 +/* iwrite (${d-An}),#${s1-imm8} */
33110 +  {
33111 +    { 0, 0, 0, 0 },
33112 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } },
33113 +    & ifmt_iwrite_d_pea_indirect_s1_immediate, { 0x4008000 }
33114 +  },
33115 +/* iwrite (${d-An})${d-i4-4}++,#${s1-imm8} */
33116 +  {
33117 +    { 0, 0, 0, 0 },
33118 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '#', OP (S1_IMM8), 0 } },
33119 +    & ifmt_iwrite_d_pea_indirect_with_post_increment_s1_immediate, { 0x2008000 }
33120 +  },
33121 +/* iwrite ${d-i4-4}(${d-An})++,#${s1-imm8} */
33122 +  {
33123 +    { 0, 0, 0, 0 },
33124 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), 0 } },
33125 +    & ifmt_iwrite_d_pea_indirect_with_pre_increment_s1_immediate, { 0x2108000 }
33126 +  },
33127 +/* iwrite (${d-An},${d-r}),(${s1-An},${s1-r}) */
33128 +  {
33129 +    { 0, 0, 0, 0 },
33130 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
33131 +    & ifmt_iwrite_d_pea_indirect_with_index_s1_indirect_with_index_4, { 0x3008300 }
33132 +  },
33133 +/* iwrite ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}) */
33134 +  {
33135 +    { 0, 0, 0, 0 },
33136 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
33137 +    & ifmt_iwrite_d_pea_indirect_with_offset_s1_indirect_with_index_4, { 0x4008300 }
33138 +  },
33139 +/* iwrite (${d-An}),(${s1-An},${s1-r}) */
33140 +  {
33141 +    { 0, 0, 0, 0 },
33142 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
33143 +    & ifmt_iwrite_d_pea_indirect_s1_indirect_with_index_4, { 0x4008300 }
33144 +  },
33145 +/* iwrite (${d-An})${d-i4-4}++,(${s1-An},${s1-r}) */
33146 +  {
33147 +    { 0, 0, 0, 0 },
33148 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
33149 +    & ifmt_iwrite_d_pea_indirect_with_post_increment_s1_indirect_with_index_4, { 0x2008300 }
33150 +  },
33151 +/* iwrite ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}) */
33152 +  {
33153 +    { 0, 0, 0, 0 },
33154 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
33155 +    & ifmt_iwrite_d_pea_indirect_with_pre_increment_s1_indirect_with_index_4, { 0x2108300 }
33156 +  },
33157 +/* iwrite (${d-An},${d-r}),${s1-imm7-4}(${s1-An}) */
33158 +  {
33159 +    { 0, 0, 0, 0 },
33160 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
33161 +    & ifmt_iwrite_d_pea_indirect_with_index_s1_indirect_with_offset_4, { 0x3008400 }
33162 +  },
33163 +/* iwrite ${d-imm7-4}(${d-An}),${s1-imm7-4}(${s1-An}) */
33164 +  {
33165 +    { 0, 0, 0, 0 },
33166 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
33167 +    & ifmt_iwrite_d_pea_indirect_with_offset_s1_indirect_with_offset_4, { 0x4008400 }
33168 +  },
33169 +/* iwrite (${d-An}),${s1-imm7-4}(${s1-An}) */
33170 +  {
33171 +    { 0, 0, 0, 0 },
33172 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
33173 +    & ifmt_iwrite_d_pea_indirect_s1_indirect_with_offset_4, { 0x4008400 }
33174 +  },
33175 +/* iwrite (${d-An})${d-i4-4}++,${s1-imm7-4}(${s1-An}) */
33176 +  {
33177 +    { 0, 0, 0, 0 },
33178 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
33179 +    & ifmt_iwrite_d_pea_indirect_with_post_increment_s1_indirect_with_offset_4, { 0x2008400 }
33180 +  },
33181 +/* iwrite ${d-i4-4}(${d-An})++,${s1-imm7-4}(${s1-An}) */
33182 +  {
33183 +    { 0, 0, 0, 0 },
33184 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
33185 +    & ifmt_iwrite_d_pea_indirect_with_pre_increment_s1_indirect_with_offset_4, { 0x2108400 }
33186 +  },
33187 +/* iwrite (${d-An},${d-r}),(${s1-An}) */
33188 +  {
33189 +    { 0, 0, 0, 0 },
33190 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', 0 } },
33191 +    & ifmt_iwrite_d_pea_indirect_with_index_s1_indirect_4, { 0x3008400 }
33192 +  },
33193 +/* iwrite ${d-imm7-4}(${d-An}),(${s1-An}) */
33194 +  {
33195 +    { 0, 0, 0, 0 },
33196 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } },
33197 +    & ifmt_iwrite_d_pea_indirect_with_offset_s1_indirect_4, { 0x4008400 }
33198 +  },
33199 +/* iwrite (${d-An}),(${s1-An}) */
33200 +  {
33201 +    { 0, 0, 0, 0 },
33202 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } },
33203 +    & ifmt_iwrite_d_pea_indirect_s1_indirect_4, { 0x4008400 }
33204 +  },
33205 +/* iwrite (${d-An})${d-i4-4}++,(${s1-An}) */
33206 +  {
33207 +    { 0, 0, 0, 0 },
33208 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', 0 } },
33209 +    & ifmt_iwrite_d_pea_indirect_with_post_increment_s1_indirect_4, { 0x2008400 }
33210 +  },
33211 +/* iwrite ${d-i4-4}(${d-An})++,(${s1-An}) */
33212 +  {
33213 +    { 0, 0, 0, 0 },
33214 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', 0 } },
33215 +    & ifmt_iwrite_d_pea_indirect_with_pre_increment_s1_indirect_4, { 0x2108400 }
33216 +  },
33217 +/* iwrite (${d-An},${d-r}),(${s1-An})${s1-i4-4}++ */
33218 +  {
33219 +    { 0, 0, 0, 0 },
33220 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
33221 +    & ifmt_iwrite_d_pea_indirect_with_index_s1_indirect_with_post_increment_4, { 0x3008200 }
33222 +  },
33223 +/* iwrite ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-4}++ */
33224 +  {
33225 +    { 0, 0, 0, 0 },
33226 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
33227 +    & ifmt_iwrite_d_pea_indirect_with_offset_s1_indirect_with_post_increment_4, { 0x4008200 }
33228 +  },
33229 +/* iwrite (${d-An}),(${s1-An})${s1-i4-4}++ */
33230 +  {
33231 +    { 0, 0, 0, 0 },
33232 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
33233 +    & ifmt_iwrite_d_pea_indirect_s1_indirect_with_post_increment_4, { 0x4008200 }
33234 +  },
33235 +/* iwrite (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-4}++ */
33236 +  {
33237 +    { 0, 0, 0, 0 },
33238 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
33239 +    & ifmt_iwrite_d_pea_indirect_with_post_increment_s1_indirect_with_post_increment_4, { 0x2008200 }
33240 +  },
33241 +/* iwrite ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-4}++ */
33242 +  {
33243 +    { 0, 0, 0, 0 },
33244 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
33245 +    & ifmt_iwrite_d_pea_indirect_with_pre_increment_s1_indirect_with_post_increment_4, { 0x2108200 }
33246 +  },
33247 +/* iwrite (${d-An},${d-r}),${s1-i4-4}(${s1-An})++ */
33248 +  {
33249 +    { 0, 0, 0, 0 },
33250 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
33251 +    & ifmt_iwrite_d_pea_indirect_with_index_s1_indirect_with_pre_increment_4, { 0x3008210 }
33252 +  },
33253 +/* iwrite ${d-imm7-4}(${d-An}),${s1-i4-4}(${s1-An})++ */
33254 +  {
33255 +    { 0, 0, 0, 0 },
33256 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
33257 +    & ifmt_iwrite_d_pea_indirect_with_offset_s1_indirect_with_pre_increment_4, { 0x4008210 }
33258 +  },
33259 +/* iwrite (${d-An}),${s1-i4-4}(${s1-An})++ */
33260 +  {
33261 +    { 0, 0, 0, 0 },
33262 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
33263 +    & ifmt_iwrite_d_pea_indirect_s1_indirect_with_pre_increment_4, { 0x4008210 }
33264 +  },
33265 +/* iwrite (${d-An})${d-i4-4}++,${s1-i4-4}(${s1-An})++ */
33266 +  {
33267 +    { 0, 0, 0, 0 },
33268 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
33269 +    & ifmt_iwrite_d_pea_indirect_with_post_increment_s1_indirect_with_pre_increment_4, { 0x2008210 }
33270 +  },
33271 +/* iwrite ${d-i4-4}(${d-An})++,${s1-i4-4}(${s1-An})++ */
33272 +  {
33273 +    { 0, 0, 0, 0 },
33274 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
33275 +    & ifmt_iwrite_d_pea_indirect_with_pre_increment_s1_indirect_with_pre_increment_4, { 0x2108210 }
33276 +  },
33277 +/* setcsr ${s1-direct-addr} */
33278 +  {
33279 +    { 0, 0, 0, 0 },
33280 +    { { MNEM, ' ', OP (S1_DIRECT_ADDR), 0 } },
33281 +    & ifmt_setcsr_s1_direct, { 0x12d9100 }
33282 +  },
33283 +/* setcsr #${s1-imm8} */
33284 +  {
33285 +    { 0, 0, 0, 0 },
33286 +    { { MNEM, ' ', '#', OP (S1_IMM8), 0 } },
33287 +    & ifmt_setcsr_s1_immediate, { 0x12d9000 }
33288 +  },
33289 +/* setcsr (${s1-An},${s1-r}) */
33290 +  {
33291 +    { 0, 0, 0, 0 },
33292 +    { { MNEM, ' ', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
33293 +    & ifmt_setcsr_s1_indirect_with_index_4, { 0x12d9300 }
33294 +  },
33295 +/* setcsr ${s1-imm7-4}(${s1-An}) */
33296 +  {
33297 +    { 0, 0, 0, 0 },
33298 +    { { MNEM, ' ', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
33299 +    & ifmt_setcsr_s1_indirect_with_offset_4, { 0x12d9400 }
33300 +  },
33301 +/* setcsr (${s1-An}) */
33302 +  {
33303 +    { 0, 0, 0, 0 },
33304 +    { { MNEM, ' ', '(', OP (S1_AN), ')', 0 } },
33305 +    & ifmt_setcsr_s1_indirect_4, { 0x12d9400 }
33306 +  },
33307 +/* setcsr (${s1-An})${s1-i4-4}++ */
33308 +  {
33309 +    { 0, 0, 0, 0 },
33310 +    { { MNEM, ' ', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
33311 +    & ifmt_setcsr_s1_indirect_with_post_increment_4, { 0x12d9200 }
33312 +  },
33313 +/* setcsr ${s1-i4-4}(${s1-An})++ */
33314 +  {
33315 +    { 0, 0, 0, 0 },
33316 +    { { MNEM, ' ', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
33317 +    & ifmt_setcsr_s1_indirect_with_pre_increment_4, { 0x12d9210 }
33318 +  },
33319 +/* bkpt ${s1-direct-addr} */
33320 +  {
33321 +    { 0, 0, 0, 0 },
33322 +    { { MNEM, ' ', OP (S1_DIRECT_ADDR), 0 } },
33323 +    & ifmt_setcsr_s1_direct, { 0x3900 }
33324 +  },
33325 +/* bkpt #${s1-imm8} */
33326 +  {
33327 +    { 0, 0, 0, 0 },
33328 +    { { MNEM, ' ', '#', OP (S1_IMM8), 0 } },
33329 +    & ifmt_setcsr_s1_immediate, { 0x3800 }
33330 +  },
33331 +/* bkpt (${s1-An},${s1-r}) */
33332 +  {
33333 +    { 0, 0, 0, 0 },
33334 +    { { MNEM, ' ', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
33335 +    & ifmt_setcsr_s1_indirect_with_index_4, { 0x3b00 }
33336 +  },
33337 +/* bkpt ${s1-imm7-4}(${s1-An}) */
33338 +  {
33339 +    { 0, 0, 0, 0 },
33340 +    { { MNEM, ' ', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
33341 +    & ifmt_setcsr_s1_indirect_with_offset_4, { 0x3c00 }
33342 +  },
33343 +/* bkpt (${s1-An}) */
33344 +  {
33345 +    { 0, 0, 0, 0 },
33346 +    { { MNEM, ' ', '(', OP (S1_AN), ')', 0 } },
33347 +    & ifmt_setcsr_s1_indirect_4, { 0x3c00 }
33348 +  },
33349 +/* bkpt (${s1-An})${s1-i4-4}++ */
33350 +  {
33351 +    { 0, 0, 0, 0 },
33352 +    { { MNEM, ' ', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
33353 +    & ifmt_setcsr_s1_indirect_with_post_increment_4, { 0x3a00 }
33354 +  },
33355 +/* bkpt ${s1-i4-4}(${s1-An})++ */
33356 +  {
33357 +    { 0, 0, 0, 0 },
33358 +    { { MNEM, ' ', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
33359 +    & ifmt_setcsr_s1_indirect_with_pre_increment_4, { 0x3a10 }
33360 +  },
33361 +/* ret ${s1-direct-addr} */
33362 +  {
33363 +    { 0, 0, 0, 0 },
33364 +    { { MNEM, ' ', OP (S1_DIRECT_ADDR), 0 } },
33365 +    & ifmt_setcsr_s1_direct, { 0x2100 }
33366 +  },
33367 +/* ret #${s1-imm8} */
33368 +  {
33369 +    { 0, 0, 0, 0 },
33370 +    { { MNEM, ' ', '#', OP (S1_IMM8), 0 } },
33371 +    & ifmt_setcsr_s1_immediate, { 0x2000 }
33372 +  },
33373 +/* ret (${s1-An},${s1-r}) */
33374 +  {
33375 +    { 0, 0, 0, 0 },
33376 +    { { MNEM, ' ', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
33377 +    & ifmt_setcsr_s1_indirect_with_index_4, { 0x2300 }
33378 +  },
33379 +/* ret ${s1-imm7-4}(${s1-An}) */
33380 +  {
33381 +    { 0, 0, 0, 0 },
33382 +    { { MNEM, ' ', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
33383 +    & ifmt_setcsr_s1_indirect_with_offset_4, { 0x2400 }
33384 +  },
33385 +/* ret (${s1-An}) */
33386 +  {
33387 +    { 0, 0, 0, 0 },
33388 +    { { MNEM, ' ', '(', OP (S1_AN), ')', 0 } },
33389 +    & ifmt_setcsr_s1_indirect_4, { 0x2400 }
33390 +  },
33391 +/* ret (${s1-An})${s1-i4-4}++ */
33392 +  {
33393 +    { 0, 0, 0, 0 },
33394 +    { { MNEM, ' ', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
33395 +    & ifmt_setcsr_s1_indirect_with_post_increment_4, { 0x2200 }
33396 +  },
33397 +/* ret ${s1-i4-4}(${s1-An})++ */
33398 +  {
33399 +    { 0, 0, 0, 0 },
33400 +    { { MNEM, ' ', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
33401 +    & ifmt_setcsr_s1_indirect_with_pre_increment_4, { 0x2210 }
33402 +  },
33403 +/* movea ${d-direct-addr},${s1-direct-addr} */
33404 +  {
33405 +    { 0, 0, 0, 0 },
33406 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), 0 } },
33407 +    & ifmt_movea_d_direct_s1_direct, { 0x1007100 }
33408 +  },
33409 +/* movea #${d-imm8},${s1-direct-addr} */
33410 +  {
33411 +    { 0, 0, 0, 0 },
33412 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), 0 } },
33413 +    & ifmt_movea_d_immediate_4_s1_direct, { 0x7100 }
33414 +  },
33415 +/* movea (${d-An},${d-r}),${s1-direct-addr} */
33416 +  {
33417 +    { 0, 0, 0, 0 },
33418 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), 0 } },
33419 +    & ifmt_movea_d_indirect_with_index_4_s1_direct, { 0x3007100 }
33420 +  },
33421 +/* movea ${d-imm7-4}(${d-An}),${s1-direct-addr} */
33422 +  {
33423 +    { 0, 0, 0, 0 },
33424 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), 0 } },
33425 +    & ifmt_movea_d_indirect_with_offset_4_s1_direct, { 0x4007100 }
33426 +  },
33427 +/* movea (${d-An}),${s1-direct-addr} */
33428 +  {
33429 +    { 0, 0, 0, 0 },
33430 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), 0 } },
33431 +    & ifmt_movea_d_indirect_4_s1_direct, { 0x4007100 }
33432 +  },
33433 +/* movea (${d-An})${d-i4-4}++,${s1-direct-addr} */
33434 +  {
33435 +    { 0, 0, 0, 0 },
33436 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_DIRECT_ADDR), 0 } },
33437 +    & ifmt_movea_d_indirect_with_post_increment_4_s1_direct, { 0x2007100 }
33438 +  },
33439 +/* movea ${d-i4-4}(${d-An})++,${s1-direct-addr} */
33440 +  {
33441 +    { 0, 0, 0, 0 },
33442 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), 0 } },
33443 +    & ifmt_movea_d_indirect_with_pre_increment_4_s1_direct, { 0x2107100 }
33444 +  },
33445 +/* movea ${d-direct-addr},#${s1-imm8} */
33446 +  {
33447 +    { 0, 0, 0, 0 },
33448 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), 0 } },
33449 +    & ifmt_movea_d_direct_s1_immediate, { 0x1007000 }
33450 +  },
33451 +/* movea #${d-imm8},#${s1-imm8} */
33452 +  {
33453 +    { 0, 0, 0, 0 },
33454 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), 0 } },
33455 +    & ifmt_movea_d_immediate_4_s1_immediate, { 0x7000 }
33456 +  },
33457 +/* movea (${d-An},${d-r}),#${s1-imm8} */
33458 +  {
33459 +    { 0, 0, 0, 0 },
33460 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), 0 } },
33461 +    & ifmt_movea_d_indirect_with_index_4_s1_immediate, { 0x3007000 }
33462 +  },
33463 +/* movea ${d-imm7-4}(${d-An}),#${s1-imm8} */
33464 +  {
33465 +    { 0, 0, 0, 0 },
33466 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } },
33467 +    & ifmt_movea_d_indirect_with_offset_4_s1_immediate, { 0x4007000 }
33468 +  },
33469 +/* movea (${d-An}),#${s1-imm8} */
33470 +  {
33471 +    { 0, 0, 0, 0 },
33472 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } },
33473 +    & ifmt_movea_d_indirect_4_s1_immediate, { 0x4007000 }
33474 +  },
33475 +/* movea (${d-An})${d-i4-4}++,#${s1-imm8} */
33476 +  {
33477 +    { 0, 0, 0, 0 },
33478 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '#', OP (S1_IMM8), 0 } },
33479 +    & ifmt_movea_d_indirect_with_post_increment_4_s1_immediate, { 0x2007000 }
33480 +  },
33481 +/* movea ${d-i4-4}(${d-An})++,#${s1-imm8} */
33482 +  {
33483 +    { 0, 0, 0, 0 },
33484 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), 0 } },
33485 +    & ifmt_movea_d_indirect_with_pre_increment_4_s1_immediate, { 0x2107000 }
33486 +  },
33487 +/* movea ${d-direct-addr},(${s1-An},${s1-r}) */
33488 +  {
33489 +    { 0, 0, 0, 0 },
33490 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
33491 +    & ifmt_movea_d_direct_s1_indirect_with_index_4, { 0x1007300 }
33492 +  },
33493 +/* movea #${d-imm8},(${s1-An},${s1-r}) */
33494 +  {
33495 +    { 0, 0, 0, 0 },
33496 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
33497 +    & ifmt_movea_d_immediate_4_s1_indirect_with_index_4, { 0x7300 }
33498 +  },
33499 +/* movea (${d-An},${d-r}),(${s1-An},${s1-r}) */
33500 +  {
33501 +    { 0, 0, 0, 0 },
33502 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
33503 +    & ifmt_movea_d_indirect_with_index_4_s1_indirect_with_index_4, { 0x3007300 }
33504 +  },
33505 +/* movea ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}) */
33506 +  {
33507 +    { 0, 0, 0, 0 },
33508 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
33509 +    & ifmt_movea_d_indirect_with_offset_4_s1_indirect_with_index_4, { 0x4007300 }
33510 +  },
33511 +/* movea (${d-An}),(${s1-An},${s1-r}) */
33512 +  {
33513 +    { 0, 0, 0, 0 },
33514 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
33515 +    & ifmt_movea_d_indirect_4_s1_indirect_with_index_4, { 0x4007300 }
33516 +  },
33517 +/* movea (${d-An})${d-i4-4}++,(${s1-An},${s1-r}) */
33518 +  {
33519 +    { 0, 0, 0, 0 },
33520 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
33521 +    & ifmt_movea_d_indirect_with_post_increment_4_s1_indirect_with_index_4, { 0x2007300 }
33522 +  },
33523 +/* movea ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}) */
33524 +  {
33525 +    { 0, 0, 0, 0 },
33526 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
33527 +    & ifmt_movea_d_indirect_with_pre_increment_4_s1_indirect_with_index_4, { 0x2107300 }
33528 +  },
33529 +/* movea ${d-direct-addr},${s1-imm7-4}(${s1-An}) */
33530 +  {
33531 +    { 0, 0, 0, 0 },
33532 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
33533 +    & ifmt_movea_d_direct_s1_indirect_with_offset_4, { 0x1007400 }
33534 +  },
33535 +/* movea #${d-imm8},${s1-imm7-4}(${s1-An}) */
33536 +  {
33537 +    { 0, 0, 0, 0 },
33538 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
33539 +    & ifmt_movea_d_immediate_4_s1_indirect_with_offset_4, { 0x7400 }
33540 +  },
33541 +/* movea (${d-An},${d-r}),${s1-imm7-4}(${s1-An}) */
33542 +  {
33543 +    { 0, 0, 0, 0 },
33544 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
33545 +    & ifmt_movea_d_indirect_with_index_4_s1_indirect_with_offset_4, { 0x3007400 }
33546 +  },
33547 +/* movea ${d-imm7-4}(${d-An}),${s1-imm7-4}(${s1-An}) */
33548 +  {
33549 +    { 0, 0, 0, 0 },
33550 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
33551 +    & ifmt_movea_d_indirect_with_offset_4_s1_indirect_with_offset_4, { 0x4007400 }
33552 +  },
33553 +/* movea (${d-An}),${s1-imm7-4}(${s1-An}) */
33554 +  {
33555 +    { 0, 0, 0, 0 },
33556 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
33557 +    & ifmt_movea_d_indirect_4_s1_indirect_with_offset_4, { 0x4007400 }
33558 +  },
33559 +/* movea (${d-An})${d-i4-4}++,${s1-imm7-4}(${s1-An}) */
33560 +  {
33561 +    { 0, 0, 0, 0 },
33562 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
33563 +    & ifmt_movea_d_indirect_with_post_increment_4_s1_indirect_with_offset_4, { 0x2007400 }
33564 +  },
33565 +/* movea ${d-i4-4}(${d-An})++,${s1-imm7-4}(${s1-An}) */
33566 +  {
33567 +    { 0, 0, 0, 0 },
33568 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
33569 +    & ifmt_movea_d_indirect_with_pre_increment_4_s1_indirect_with_offset_4, { 0x2107400 }
33570 +  },
33571 +/* movea ${d-direct-addr},(${s1-An}) */
33572 +  {
33573 +    { 0, 0, 0, 0 },
33574 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', 0 } },
33575 +    & ifmt_movea_d_direct_s1_indirect_4, { 0x1007400 }
33576 +  },
33577 +/* movea #${d-imm8},(${s1-An}) */
33578 +  {
33579 +    { 0, 0, 0, 0 },
33580 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', 0 } },
33581 +    & ifmt_movea_d_immediate_4_s1_indirect_4, { 0x7400 }
33582 +  },
33583 +/* movea (${d-An},${d-r}),(${s1-An}) */
33584 +  {
33585 +    { 0, 0, 0, 0 },
33586 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', 0 } },
33587 +    & ifmt_movea_d_indirect_with_index_4_s1_indirect_4, { 0x3007400 }
33588 +  },
33589 +/* movea ${d-imm7-4}(${d-An}),(${s1-An}) */
33590 +  {
33591 +    { 0, 0, 0, 0 },
33592 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } },
33593 +    & ifmt_movea_d_indirect_with_offset_4_s1_indirect_4, { 0x4007400 }
33594 +  },
33595 +/* movea (${d-An}),(${s1-An}) */
33596 +  {
33597 +    { 0, 0, 0, 0 },
33598 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } },
33599 +    & ifmt_movea_d_indirect_4_s1_indirect_4, { 0x4007400 }
33600 +  },
33601 +/* movea (${d-An})${d-i4-4}++,(${s1-An}) */
33602 +  {
33603 +    { 0, 0, 0, 0 },
33604 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', 0 } },
33605 +    & ifmt_movea_d_indirect_with_post_increment_4_s1_indirect_4, { 0x2007400 }
33606 +  },
33607 +/* movea ${d-i4-4}(${d-An})++,(${s1-An}) */
33608 +  {
33609 +    { 0, 0, 0, 0 },
33610 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', 0 } },
33611 +    & ifmt_movea_d_indirect_with_pre_increment_4_s1_indirect_4, { 0x2107400 }
33612 +  },
33613 +/* movea ${d-direct-addr},(${s1-An})${s1-i4-4}++ */
33614 +  {
33615 +    { 0, 0, 0, 0 },
33616 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
33617 +    & ifmt_movea_d_direct_s1_indirect_with_post_increment_4, { 0x1007200 }
33618 +  },
33619 +/* movea #${d-imm8},(${s1-An})${s1-i4-4}++ */
33620 +  {
33621 +    { 0, 0, 0, 0 },
33622 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
33623 +    & ifmt_movea_d_immediate_4_s1_indirect_with_post_increment_4, { 0x7200 }
33624 +  },
33625 +/* movea (${d-An},${d-r}),(${s1-An})${s1-i4-4}++ */
33626 +  {
33627 +    { 0, 0, 0, 0 },
33628 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
33629 +    & ifmt_movea_d_indirect_with_index_4_s1_indirect_with_post_increment_4, { 0x3007200 }
33630 +  },
33631 +/* movea ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-4}++ */
33632 +  {
33633 +    { 0, 0, 0, 0 },
33634 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
33635 +    & ifmt_movea_d_indirect_with_offset_4_s1_indirect_with_post_increment_4, { 0x4007200 }
33636 +  },
33637 +/* movea (${d-An}),(${s1-An})${s1-i4-4}++ */
33638 +  {
33639 +    { 0, 0, 0, 0 },
33640 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
33641 +    & ifmt_movea_d_indirect_4_s1_indirect_with_post_increment_4, { 0x4007200 }
33642 +  },
33643 +/* movea (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-4}++ */
33644 +  {
33645 +    { 0, 0, 0, 0 },
33646 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
33647 +    & ifmt_movea_d_indirect_with_post_increment_4_s1_indirect_with_post_increment_4, { 0x2007200 }
33648 +  },
33649 +/* movea ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-4}++ */
33650 +  {
33651 +    { 0, 0, 0, 0 },
33652 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
33653 +    & ifmt_movea_d_indirect_with_pre_increment_4_s1_indirect_with_post_increment_4, { 0x2107200 }
33654 +  },
33655 +/* movea ${d-direct-addr},${s1-i4-4}(${s1-An})++ */
33656 +  {
33657 +    { 0, 0, 0, 0 },
33658 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
33659 +    & ifmt_movea_d_direct_s1_indirect_with_pre_increment_4, { 0x1007210 }
33660 +  },
33661 +/* movea #${d-imm8},${s1-i4-4}(${s1-An})++ */
33662 +  {
33663 +    { 0, 0, 0, 0 },
33664 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
33665 +    & ifmt_movea_d_immediate_4_s1_indirect_with_pre_increment_4, { 0x7210 }
33666 +  },
33667 +/* movea (${d-An},${d-r}),${s1-i4-4}(${s1-An})++ */
33668 +  {
33669 +    { 0, 0, 0, 0 },
33670 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
33671 +    & ifmt_movea_d_indirect_with_index_4_s1_indirect_with_pre_increment_4, { 0x3007210 }
33672 +  },
33673 +/* movea ${d-imm7-4}(${d-An}),${s1-i4-4}(${s1-An})++ */
33674 +  {
33675 +    { 0, 0, 0, 0 },
33676 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
33677 +    & ifmt_movea_d_indirect_with_offset_4_s1_indirect_with_pre_increment_4, { 0x4007210 }
33678 +  },
33679 +/* movea (${d-An}),${s1-i4-4}(${s1-An})++ */
33680 +  {
33681 +    { 0, 0, 0, 0 },
33682 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
33683 +    & ifmt_movea_d_indirect_4_s1_indirect_with_pre_increment_4, { 0x4007210 }
33684 +  },
33685 +/* movea (${d-An})${d-i4-4}++,${s1-i4-4}(${s1-An})++ */
33686 +  {
33687 +    { 0, 0, 0, 0 },
33688 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
33689 +    & ifmt_movea_d_indirect_with_post_increment_4_s1_indirect_with_pre_increment_4, { 0x2007210 }
33690 +  },
33691 +/* movea ${d-i4-4}(${d-An})++,${s1-i4-4}(${s1-An})++ */
33692 +  {
33693 +    { 0, 0, 0, 0 },
33694 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
33695 +    & ifmt_movea_d_indirect_with_pre_increment_4_s1_indirect_with_pre_increment_4, { 0x2107210 }
33696 +  },
33697 +/* move.4 ${d-direct-addr},${s1-direct-addr} */
33698 +  {
33699 +    { 0, 0, 0, 0 },
33700 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), 0 } },
33701 +    & ifmt_movea_d_direct_s1_direct, { 0x1006100 }
33702 +  },
33703 +/* move.4 #${d-imm8},${s1-direct-addr} */
33704 +  {
33705 +    { 0, 0, 0, 0 },
33706 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), 0 } },
33707 +    & ifmt_movea_d_immediate_4_s1_direct, { 0x6100 }
33708 +  },
33709 +/* move.4 (${d-An},${d-r}),${s1-direct-addr} */
33710 +  {
33711 +    { 0, 0, 0, 0 },
33712 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), 0 } },
33713 +    & ifmt_movea_d_indirect_with_index_4_s1_direct, { 0x3006100 }
33714 +  },
33715 +/* move.4 ${d-imm7-4}(${d-An}),${s1-direct-addr} */
33716 +  {
33717 +    { 0, 0, 0, 0 },
33718 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), 0 } },
33719 +    & ifmt_movea_d_indirect_with_offset_4_s1_direct, { 0x4006100 }
33720 +  },
33721 +/* move.4 (${d-An}),${s1-direct-addr} */
33722 +  {
33723 +    { 0, 0, 0, 0 },
33724 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), 0 } },
33725 +    & ifmt_movea_d_indirect_4_s1_direct, { 0x4006100 }
33726 +  },
33727 +/* move.4 (${d-An})${d-i4-4}++,${s1-direct-addr} */
33728 +  {
33729 +    { 0, 0, 0, 0 },
33730 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_DIRECT_ADDR), 0 } },
33731 +    & ifmt_movea_d_indirect_with_post_increment_4_s1_direct, { 0x2006100 }
33732 +  },
33733 +/* move.4 ${d-i4-4}(${d-An})++,${s1-direct-addr} */
33734 +  {
33735 +    { 0, 0, 0, 0 },
33736 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), 0 } },
33737 +    & ifmt_movea_d_indirect_with_pre_increment_4_s1_direct, { 0x2106100 }
33738 +  },
33739 +/* move.4 ${d-direct-addr},#${s1-imm8} */
33740 +  {
33741 +    { 0, 0, 0, 0 },
33742 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), 0 } },
33743 +    & ifmt_movea_d_direct_s1_immediate, { 0x1006000 }
33744 +  },
33745 +/* move.4 #${d-imm8},#${s1-imm8} */
33746 +  {
33747 +    { 0, 0, 0, 0 },
33748 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), 0 } },
33749 +    & ifmt_movea_d_immediate_4_s1_immediate, { 0x6000 }
33750 +  },
33751 +/* move.4 (${d-An},${d-r}),#${s1-imm8} */
33752 +  {
33753 +    { 0, 0, 0, 0 },
33754 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), 0 } },
33755 +    & ifmt_movea_d_indirect_with_index_4_s1_immediate, { 0x3006000 }
33756 +  },
33757 +/* move.4 ${d-imm7-4}(${d-An}),#${s1-imm8} */
33758 +  {
33759 +    { 0, 0, 0, 0 },
33760 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } },
33761 +    & ifmt_movea_d_indirect_with_offset_4_s1_immediate, { 0x4006000 }
33762 +  },
33763 +/* move.4 (${d-An}),#${s1-imm8} */
33764 +  {
33765 +    { 0, 0, 0, 0 },
33766 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } },
33767 +    & ifmt_movea_d_indirect_4_s1_immediate, { 0x4006000 }
33768 +  },
33769 +/* move.4 (${d-An})${d-i4-4}++,#${s1-imm8} */
33770 +  {
33771 +    { 0, 0, 0, 0 },
33772 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '#', OP (S1_IMM8), 0 } },
33773 +    & ifmt_movea_d_indirect_with_post_increment_4_s1_immediate, { 0x2006000 }
33774 +  },
33775 +/* move.4 ${d-i4-4}(${d-An})++,#${s1-imm8} */
33776 +  {
33777 +    { 0, 0, 0, 0 },
33778 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), 0 } },
33779 +    & ifmt_movea_d_indirect_with_pre_increment_4_s1_immediate, { 0x2106000 }
33780 +  },
33781 +/* move.4 ${d-direct-addr},(${s1-An},${s1-r}) */
33782 +  {
33783 +    { 0, 0, 0, 0 },
33784 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
33785 +    & ifmt_movea_d_direct_s1_indirect_with_index_4, { 0x1006300 }
33786 +  },
33787 +/* move.4 #${d-imm8},(${s1-An},${s1-r}) */
33788 +  {
33789 +    { 0, 0, 0, 0 },
33790 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
33791 +    & ifmt_movea_d_immediate_4_s1_indirect_with_index_4, { 0x6300 }
33792 +  },
33793 +/* move.4 (${d-An},${d-r}),(${s1-An},${s1-r}) */
33794 +  {
33795 +    { 0, 0, 0, 0 },
33796 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
33797 +    & ifmt_movea_d_indirect_with_index_4_s1_indirect_with_index_4, { 0x3006300 }
33798 +  },
33799 +/* move.4 ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}) */
33800 +  {
33801 +    { 0, 0, 0, 0 },
33802 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
33803 +    & ifmt_movea_d_indirect_with_offset_4_s1_indirect_with_index_4, { 0x4006300 }
33804 +  },
33805 +/* move.4 (${d-An}),(${s1-An},${s1-r}) */
33806 +  {
33807 +    { 0, 0, 0, 0 },
33808 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
33809 +    & ifmt_movea_d_indirect_4_s1_indirect_with_index_4, { 0x4006300 }
33810 +  },
33811 +/* move.4 (${d-An})${d-i4-4}++,(${s1-An},${s1-r}) */
33812 +  {
33813 +    { 0, 0, 0, 0 },
33814 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
33815 +    & ifmt_movea_d_indirect_with_post_increment_4_s1_indirect_with_index_4, { 0x2006300 }
33816 +  },
33817 +/* move.4 ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}) */
33818 +  {
33819 +    { 0, 0, 0, 0 },
33820 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
33821 +    & ifmt_movea_d_indirect_with_pre_increment_4_s1_indirect_with_index_4, { 0x2106300 }
33822 +  },
33823 +/* move.4 ${d-direct-addr},${s1-imm7-4}(${s1-An}) */
33824 +  {
33825 +    { 0, 0, 0, 0 },
33826 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
33827 +    & ifmt_movea_d_direct_s1_indirect_with_offset_4, { 0x1006400 }
33828 +  },
33829 +/* move.4 #${d-imm8},${s1-imm7-4}(${s1-An}) */
33830 +  {
33831 +    { 0, 0, 0, 0 },
33832 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
33833 +    & ifmt_movea_d_immediate_4_s1_indirect_with_offset_4, { 0x6400 }
33834 +  },
33835 +/* move.4 (${d-An},${d-r}),${s1-imm7-4}(${s1-An}) */
33836 +  {
33837 +    { 0, 0, 0, 0 },
33838 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
33839 +    & ifmt_movea_d_indirect_with_index_4_s1_indirect_with_offset_4, { 0x3006400 }
33840 +  },
33841 +/* move.4 ${d-imm7-4}(${d-An}),${s1-imm7-4}(${s1-An}) */
33842 +  {
33843 +    { 0, 0, 0, 0 },
33844 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
33845 +    & ifmt_movea_d_indirect_with_offset_4_s1_indirect_with_offset_4, { 0x4006400 }
33846 +  },
33847 +/* move.4 (${d-An}),${s1-imm7-4}(${s1-An}) */
33848 +  {
33849 +    { 0, 0, 0, 0 },
33850 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
33851 +    & ifmt_movea_d_indirect_4_s1_indirect_with_offset_4, { 0x4006400 }
33852 +  },
33853 +/* move.4 (${d-An})${d-i4-4}++,${s1-imm7-4}(${s1-An}) */
33854 +  {
33855 +    { 0, 0, 0, 0 },
33856 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
33857 +    & ifmt_movea_d_indirect_with_post_increment_4_s1_indirect_with_offset_4, { 0x2006400 }
33858 +  },
33859 +/* move.4 ${d-i4-4}(${d-An})++,${s1-imm7-4}(${s1-An}) */
33860 +  {
33861 +    { 0, 0, 0, 0 },
33862 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
33863 +    & ifmt_movea_d_indirect_with_pre_increment_4_s1_indirect_with_offset_4, { 0x2106400 }
33864 +  },
33865 +/* move.4 ${d-direct-addr},(${s1-An}) */
33866 +  {
33867 +    { 0, 0, 0, 0 },
33868 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', 0 } },
33869 +    & ifmt_movea_d_direct_s1_indirect_4, { 0x1006400 }
33870 +  },
33871 +/* move.4 #${d-imm8},(${s1-An}) */
33872 +  {
33873 +    { 0, 0, 0, 0 },
33874 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', 0 } },
33875 +    & ifmt_movea_d_immediate_4_s1_indirect_4, { 0x6400 }
33876 +  },
33877 +/* move.4 (${d-An},${d-r}),(${s1-An}) */
33878 +  {
33879 +    { 0, 0, 0, 0 },
33880 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', 0 } },
33881 +    & ifmt_movea_d_indirect_with_index_4_s1_indirect_4, { 0x3006400 }
33882 +  },
33883 +/* move.4 ${d-imm7-4}(${d-An}),(${s1-An}) */
33884 +  {
33885 +    { 0, 0, 0, 0 },
33886 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } },
33887 +    & ifmt_movea_d_indirect_with_offset_4_s1_indirect_4, { 0x4006400 }
33888 +  },
33889 +/* move.4 (${d-An}),(${s1-An}) */
33890 +  {
33891 +    { 0, 0, 0, 0 },
33892 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } },
33893 +    & ifmt_movea_d_indirect_4_s1_indirect_4, { 0x4006400 }
33894 +  },
33895 +/* move.4 (${d-An})${d-i4-4}++,(${s1-An}) */
33896 +  {
33897 +    { 0, 0, 0, 0 },
33898 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', 0 } },
33899 +    & ifmt_movea_d_indirect_with_post_increment_4_s1_indirect_4, { 0x2006400 }
33900 +  },
33901 +/* move.4 ${d-i4-4}(${d-An})++,(${s1-An}) */
33902 +  {
33903 +    { 0, 0, 0, 0 },
33904 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', 0 } },
33905 +    & ifmt_movea_d_indirect_with_pre_increment_4_s1_indirect_4, { 0x2106400 }
33906 +  },
33907 +/* move.4 ${d-direct-addr},(${s1-An})${s1-i4-4}++ */
33908 +  {
33909 +    { 0, 0, 0, 0 },
33910 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
33911 +    & ifmt_movea_d_direct_s1_indirect_with_post_increment_4, { 0x1006200 }
33912 +  },
33913 +/* move.4 #${d-imm8},(${s1-An})${s1-i4-4}++ */
33914 +  {
33915 +    { 0, 0, 0, 0 },
33916 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
33917 +    & ifmt_movea_d_immediate_4_s1_indirect_with_post_increment_4, { 0x6200 }
33918 +  },
33919 +/* move.4 (${d-An},${d-r}),(${s1-An})${s1-i4-4}++ */
33920 +  {
33921 +    { 0, 0, 0, 0 },
33922 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
33923 +    & ifmt_movea_d_indirect_with_index_4_s1_indirect_with_post_increment_4, { 0x3006200 }
33924 +  },
33925 +/* move.4 ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-4}++ */
33926 +  {
33927 +    { 0, 0, 0, 0 },
33928 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
33929 +    & ifmt_movea_d_indirect_with_offset_4_s1_indirect_with_post_increment_4, { 0x4006200 }
33930 +  },
33931 +/* move.4 (${d-An}),(${s1-An})${s1-i4-4}++ */
33932 +  {
33933 +    { 0, 0, 0, 0 },
33934 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
33935 +    & ifmt_movea_d_indirect_4_s1_indirect_with_post_increment_4, { 0x4006200 }
33936 +  },
33937 +/* move.4 (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-4}++ */
33938 +  {
33939 +    { 0, 0, 0, 0 },
33940 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
33941 +    & ifmt_movea_d_indirect_with_post_increment_4_s1_indirect_with_post_increment_4, { 0x2006200 }
33942 +  },
33943 +/* move.4 ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-4}++ */
33944 +  {
33945 +    { 0, 0, 0, 0 },
33946 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
33947 +    & ifmt_movea_d_indirect_with_pre_increment_4_s1_indirect_with_post_increment_4, { 0x2106200 }
33948 +  },
33949 +/* move.4 ${d-direct-addr},${s1-i4-4}(${s1-An})++ */
33950 +  {
33951 +    { 0, 0, 0, 0 },
33952 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
33953 +    & ifmt_movea_d_direct_s1_indirect_with_pre_increment_4, { 0x1006210 }
33954 +  },
33955 +/* move.4 #${d-imm8},${s1-i4-4}(${s1-An})++ */
33956 +  {
33957 +    { 0, 0, 0, 0 },
33958 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
33959 +    & ifmt_movea_d_immediate_4_s1_indirect_with_pre_increment_4, { 0x6210 }
33960 +  },
33961 +/* move.4 (${d-An},${d-r}),${s1-i4-4}(${s1-An})++ */
33962 +  {
33963 +    { 0, 0, 0, 0 },
33964 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
33965 +    & ifmt_movea_d_indirect_with_index_4_s1_indirect_with_pre_increment_4, { 0x3006210 }
33966 +  },
33967 +/* move.4 ${d-imm7-4}(${d-An}),${s1-i4-4}(${s1-An})++ */
33968 +  {
33969 +    { 0, 0, 0, 0 },
33970 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
33971 +    & ifmt_movea_d_indirect_with_offset_4_s1_indirect_with_pre_increment_4, { 0x4006210 }
33972 +  },
33973 +/* move.4 (${d-An}),${s1-i4-4}(${s1-An})++ */
33974 +  {
33975 +    { 0, 0, 0, 0 },
33976 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
33977 +    & ifmt_movea_d_indirect_4_s1_indirect_with_pre_increment_4, { 0x4006210 }
33978 +  },
33979 +/* move.4 (${d-An})${d-i4-4}++,${s1-i4-4}(${s1-An})++ */
33980 +  {
33981 +    { 0, 0, 0, 0 },
33982 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
33983 +    & ifmt_movea_d_indirect_with_post_increment_4_s1_indirect_with_pre_increment_4, { 0x2006210 }
33984 +  },
33985 +/* move.4 ${d-i4-4}(${d-An})++,${s1-i4-4}(${s1-An})++ */
33986 +  {
33987 +    { 0, 0, 0, 0 },
33988 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
33989 +    & ifmt_movea_d_indirect_with_pre_increment_4_s1_indirect_with_pre_increment_4, { 0x2106210 }
33990 +  },
33991 +/* iread (${s1-An}) */
33992 +  {
33993 +    { 0, 0, 0, 0 },
33994 +    { { MNEM, ' ', '(', OP (S1_AN), ')', 0 } },
33995 +    & ifmt_iread_s1_ea_indirect, { 0x12f6400 }
33996 +  },
33997 +/* iread (${s1-An},${s1-r}) */
33998 +  {
33999 +    { 0, 0, 0, 0 },
34000 +    { { MNEM, ' ', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
34001 +    & ifmt_iread_s1_ea_indirect_with_index_4, { 0x12f6300 }
34002 +  },
34003 +/* iread (${s1-An})${s1-i4-4}++ */
34004 +  {
34005 +    { 0, 0, 0, 0 },
34006 +    { { MNEM, ' ', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
34007 +    & ifmt_iread_s1_ea_indirect_with_post_increment_4, { 0x12f6200 }
34008 +  },
34009 +/* iread ${s1-i4-4}(${s1-An})++ */
34010 +  {
34011 +    { 0, 0, 0, 0 },
34012 +    { { MNEM, ' ', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
34013 +    & ifmt_iread_s1_ea_indirect_with_pre_increment_4, { 0x12f6210 }
34014 +  },
34015 +/* iread ${s1-imm7-4}(${s1-An}) */
34016 +  {
34017 +    { 0, 0, 0, 0 },
34018 +    { { MNEM, ' ', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
34019 +    & ifmt_iread_s1_ea_indirect_with_offset_4, { 0x12f6400 }
34020 +  },
34021 +/* iwrite (${d-An},${d-r}),${s1-direct-addr} */
34022 +  {
34023 +    { 0, 0, 0, 0 },
34024 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), 0 } },
34025 +    & ifmt_iwrite_d_pea_indirect_with_index_s1_direct, { 0x3006100 }
34026 +  },
34027 +/* iwrite ${d-imm7-4}(${d-An}),${s1-direct-addr} */
34028 +  {
34029 +    { 0, 0, 0, 0 },
34030 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), 0 } },
34031 +    & ifmt_iwrite_d_pea_indirect_with_offset_s1_direct, { 0x4006100 }
34032 +  },
34033 +/* iwrite (${d-An}),${s1-direct-addr} */
34034 +  {
34035 +    { 0, 0, 0, 0 },
34036 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), 0 } },
34037 +    & ifmt_iwrite_d_pea_indirect_s1_direct, { 0x4006100 }
34038 +  },
34039 +/* iwrite (${d-An})${d-i4-4}++,${s1-direct-addr} */
34040 +  {
34041 +    { 0, 0, 0, 0 },
34042 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_DIRECT_ADDR), 0 } },
34043 +    & ifmt_iwrite_d_pea_indirect_with_post_increment_s1_direct, { 0x2006100 }
34044 +  },
34045 +/* iwrite ${d-i4-4}(${d-An})++,${s1-direct-addr} */
34046 +  {
34047 +    { 0, 0, 0, 0 },
34048 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), 0 } },
34049 +    & ifmt_iwrite_d_pea_indirect_with_pre_increment_s1_direct, { 0x2106100 }
34050 +  },
34051 +/* iwrite (${d-An},${d-r}),#${s1-imm8} */
34052 +  {
34053 +    { 0, 0, 0, 0 },
34054 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), 0 } },
34055 +    & ifmt_iwrite_d_pea_indirect_with_index_s1_immediate, { 0x3006000 }
34056 +  },
34057 +/* iwrite ${d-imm7-4}(${d-An}),#${s1-imm8} */
34058 +  {
34059 +    { 0, 0, 0, 0 },
34060 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } },
34061 +    & ifmt_iwrite_d_pea_indirect_with_offset_s1_immediate, { 0x4006000 }
34062 +  },
34063 +/* iwrite (${d-An}),#${s1-imm8} */
34064 +  {
34065 +    { 0, 0, 0, 0 },
34066 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } },
34067 +    & ifmt_iwrite_d_pea_indirect_s1_immediate, { 0x4006000 }
34068 +  },
34069 +/* iwrite (${d-An})${d-i4-4}++,#${s1-imm8} */
34070 +  {
34071 +    { 0, 0, 0, 0 },
34072 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '#', OP (S1_IMM8), 0 } },
34073 +    & ifmt_iwrite_d_pea_indirect_with_post_increment_s1_immediate, { 0x2006000 }
34074 +  },
34075 +/* iwrite ${d-i4-4}(${d-An})++,#${s1-imm8} */
34076 +  {
34077 +    { 0, 0, 0, 0 },
34078 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), 0 } },
34079 +    & ifmt_iwrite_d_pea_indirect_with_pre_increment_s1_immediate, { 0x2106000 }
34080 +  },
34081 +/* iwrite (${d-An},${d-r}),(${s1-An},${s1-r}) */
34082 +  {
34083 +    { 0, 0, 0, 0 },
34084 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
34085 +    & ifmt_iwrite_d_pea_indirect_with_index_s1_indirect_with_index_4, { 0x3006300 }
34086 +  },
34087 +/* iwrite ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}) */
34088 +  {
34089 +    { 0, 0, 0, 0 },
34090 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
34091 +    & ifmt_iwrite_d_pea_indirect_with_offset_s1_indirect_with_index_4, { 0x4006300 }
34092 +  },
34093 +/* iwrite (${d-An}),(${s1-An},${s1-r}) */
34094 +  {
34095 +    { 0, 0, 0, 0 },
34096 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
34097 +    & ifmt_iwrite_d_pea_indirect_s1_indirect_with_index_4, { 0x4006300 }
34098 +  },
34099 +/* iwrite (${d-An})${d-i4-4}++,(${s1-An},${s1-r}) */
34100 +  {
34101 +    { 0, 0, 0, 0 },
34102 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
34103 +    & ifmt_iwrite_d_pea_indirect_with_post_increment_s1_indirect_with_index_4, { 0x2006300 }
34104 +  },
34105 +/* iwrite ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}) */
34106 +  {
34107 +    { 0, 0, 0, 0 },
34108 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
34109 +    & ifmt_iwrite_d_pea_indirect_with_pre_increment_s1_indirect_with_index_4, { 0x2106300 }
34110 +  },
34111 +/* iwrite (${d-An},${d-r}),${s1-imm7-4}(${s1-An}) */
34112 +  {
34113 +    { 0, 0, 0, 0 },
34114 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
34115 +    & ifmt_iwrite_d_pea_indirect_with_index_s1_indirect_with_offset_4, { 0x3006400 }
34116 +  },
34117 +/* iwrite ${d-imm7-4}(${d-An}),${s1-imm7-4}(${s1-An}) */
34118 +  {
34119 +    { 0, 0, 0, 0 },
34120 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
34121 +    & ifmt_iwrite_d_pea_indirect_with_offset_s1_indirect_with_offset_4, { 0x4006400 }
34122 +  },
34123 +/* iwrite (${d-An}),${s1-imm7-4}(${s1-An}) */
34124 +  {
34125 +    { 0, 0, 0, 0 },
34126 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
34127 +    & ifmt_iwrite_d_pea_indirect_s1_indirect_with_offset_4, { 0x4006400 }
34128 +  },
34129 +/* iwrite (${d-An})${d-i4-4}++,${s1-imm7-4}(${s1-An}) */
34130 +  {
34131 +    { 0, 0, 0, 0 },
34132 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
34133 +    & ifmt_iwrite_d_pea_indirect_with_post_increment_s1_indirect_with_offset_4, { 0x2006400 }
34134 +  },
34135 +/* iwrite ${d-i4-4}(${d-An})++,${s1-imm7-4}(${s1-An}) */
34136 +  {
34137 +    { 0, 0, 0, 0 },
34138 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
34139 +    & ifmt_iwrite_d_pea_indirect_with_pre_increment_s1_indirect_with_offset_4, { 0x2106400 }
34140 +  },
34141 +/* iwrite (${d-An},${d-r}),(${s1-An}) */
34142 +  {
34143 +    { 0, 0, 0, 0 },
34144 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', 0 } },
34145 +    & ifmt_iwrite_d_pea_indirect_with_index_s1_indirect_4, { 0x3006400 }
34146 +  },
34147 +/* iwrite ${d-imm7-4}(${d-An}),(${s1-An}) */
34148 +  {
34149 +    { 0, 0, 0, 0 },
34150 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } },
34151 +    & ifmt_iwrite_d_pea_indirect_with_offset_s1_indirect_4, { 0x4006400 }
34152 +  },
34153 +/* iwrite (${d-An}),(${s1-An}) */
34154 +  {
34155 +    { 0, 0, 0, 0 },
34156 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } },
34157 +    & ifmt_iwrite_d_pea_indirect_s1_indirect_4, { 0x4006400 }
34158 +  },
34159 +/* iwrite (${d-An})${d-i4-4}++,(${s1-An}) */
34160 +  {
34161 +    { 0, 0, 0, 0 },
34162 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', 0 } },
34163 +    & ifmt_iwrite_d_pea_indirect_with_post_increment_s1_indirect_4, { 0x2006400 }
34164 +  },
34165 +/* iwrite ${d-i4-4}(${d-An})++,(${s1-An}) */
34166 +  {
34167 +    { 0, 0, 0, 0 },
34168 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', 0 } },
34169 +    & ifmt_iwrite_d_pea_indirect_with_pre_increment_s1_indirect_4, { 0x2106400 }
34170 +  },
34171 +/* iwrite (${d-An},${d-r}),(${s1-An})${s1-i4-4}++ */
34172 +  {
34173 +    { 0, 0, 0, 0 },
34174 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
34175 +    & ifmt_iwrite_d_pea_indirect_with_index_s1_indirect_with_post_increment_4, { 0x3006200 }
34176 +  },
34177 +/* iwrite ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-4}++ */
34178 +  {
34179 +    { 0, 0, 0, 0 },
34180 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
34181 +    & ifmt_iwrite_d_pea_indirect_with_offset_s1_indirect_with_post_increment_4, { 0x4006200 }
34182 +  },
34183 +/* iwrite (${d-An}),(${s1-An})${s1-i4-4}++ */
34184 +  {
34185 +    { 0, 0, 0, 0 },
34186 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
34187 +    & ifmt_iwrite_d_pea_indirect_s1_indirect_with_post_increment_4, { 0x4006200 }
34188 +  },
34189 +/* iwrite (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-4}++ */
34190 +  {
34191 +    { 0, 0, 0, 0 },
34192 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
34193 +    & ifmt_iwrite_d_pea_indirect_with_post_increment_s1_indirect_with_post_increment_4, { 0x2006200 }
34194 +  },
34195 +/* iwrite ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-4}++ */
34196 +  {
34197 +    { 0, 0, 0, 0 },
34198 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
34199 +    & ifmt_iwrite_d_pea_indirect_with_pre_increment_s1_indirect_with_post_increment_4, { 0x2106200 }
34200 +  },
34201 +/* iwrite (${d-An},${d-r}),${s1-i4-4}(${s1-An})++ */
34202 +  {
34203 +    { 0, 0, 0, 0 },
34204 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
34205 +    & ifmt_iwrite_d_pea_indirect_with_index_s1_indirect_with_pre_increment_4, { 0x3006210 }
34206 +  },
34207 +/* iwrite ${d-imm7-4}(${d-An}),${s1-i4-4}(${s1-An})++ */
34208 +  {
34209 +    { 0, 0, 0, 0 },
34210 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
34211 +    & ifmt_iwrite_d_pea_indirect_with_offset_s1_indirect_with_pre_increment_4, { 0x4006210 }
34212 +  },
34213 +/* iwrite (${d-An}),${s1-i4-4}(${s1-An})++ */
34214 +  {
34215 +    { 0, 0, 0, 0 },
34216 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
34217 +    & ifmt_iwrite_d_pea_indirect_s1_indirect_with_pre_increment_4, { 0x4006210 }
34218 +  },
34219 +/* iwrite (${d-An})${d-i4-4}++,${s1-i4-4}(${s1-An})++ */
34220 +  {
34221 +    { 0, 0, 0, 0 },
34222 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
34223 +    & ifmt_iwrite_d_pea_indirect_with_post_increment_s1_indirect_with_pre_increment_4, { 0x2006210 }
34224 +  },
34225 +/* iwrite ${d-i4-4}(${d-An})++,${s1-i4-4}(${s1-An})++ */
34226 +  {
34227 +    { 0, 0, 0, 0 },
34228 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
34229 +    & ifmt_iwrite_d_pea_indirect_with_pre_increment_s1_indirect_with_pre_increment_4, { 0x2106210 }
34230 +  },
34231 +/* move.2 ${d-direct-addr},${s1-direct-addr} */
34232 +  {
34233 +    { 0, 0, 0, 0 },
34234 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), 0 } },
34235 +    & ifmt_movea_d_direct_s1_direct, { 0x1006900 }
34236 +  },
34237 +/* move.2 #${d-imm8},${s1-direct-addr} */
34238 +  {
34239 +    { 0, 0, 0, 0 },
34240 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), 0 } },
34241 +    & ifmt_move_2_d_immediate_2_s1_direct, { 0x6900 }
34242 +  },
34243 +/* move.2 (${d-An},${d-r}),${s1-direct-addr} */
34244 +  {
34245 +    { 0, 0, 0, 0 },
34246 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), 0 } },
34247 +    & ifmt_move_2_d_indirect_with_index_2_s1_direct, { 0x3006900 }
34248 +  },
34249 +/* move.2 ${d-imm7-2}(${d-An}),${s1-direct-addr} */
34250 +  {
34251 +    { 0, 0, 0, 0 },
34252 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), 0 } },
34253 +    & ifmt_move_2_d_indirect_with_offset_2_s1_direct, { 0x4006900 }
34254 +  },
34255 +/* move.2 (${d-An}),${s1-direct-addr} */
34256 +  {
34257 +    { 0, 0, 0, 0 },
34258 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), 0 } },
34259 +    & ifmt_move_2_d_indirect_2_s1_direct, { 0x4006900 }
34260 +  },
34261 +/* move.2 (${d-An})${d-i4-2}++,${s1-direct-addr} */
34262 +  {
34263 +    { 0, 0, 0, 0 },
34264 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_DIRECT_ADDR), 0 } },
34265 +    & ifmt_move_2_d_indirect_with_post_increment_2_s1_direct, { 0x2006900 }
34266 +  },
34267 +/* move.2 ${d-i4-2}(${d-An})++,${s1-direct-addr} */
34268 +  {
34269 +    { 0, 0, 0, 0 },
34270 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), 0 } },
34271 +    & ifmt_move_2_d_indirect_with_pre_increment_2_s1_direct, { 0x2106900 }
34272 +  },
34273 +/* move.2 ${d-direct-addr},#${s1-imm8} */
34274 +  {
34275 +    { 0, 0, 0, 0 },
34276 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), 0 } },
34277 +    & ifmt_movea_d_direct_s1_immediate, { 0x1006800 }
34278 +  },
34279 +/* move.2 #${d-imm8},#${s1-imm8} */
34280 +  {
34281 +    { 0, 0, 0, 0 },
34282 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), 0 } },
34283 +    & ifmt_move_2_d_immediate_2_s1_immediate, { 0x6800 }
34284 +  },
34285 +/* move.2 (${d-An},${d-r}),#${s1-imm8} */
34286 +  {
34287 +    { 0, 0, 0, 0 },
34288 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), 0 } },
34289 +    & ifmt_move_2_d_indirect_with_index_2_s1_immediate, { 0x3006800 }
34290 +  },
34291 +/* move.2 ${d-imm7-2}(${d-An}),#${s1-imm8} */
34292 +  {
34293 +    { 0, 0, 0, 0 },
34294 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } },
34295 +    & ifmt_move_2_d_indirect_with_offset_2_s1_immediate, { 0x4006800 }
34296 +  },
34297 +/* move.2 (${d-An}),#${s1-imm8} */
34298 +  {
34299 +    { 0, 0, 0, 0 },
34300 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } },
34301 +    & ifmt_move_2_d_indirect_2_s1_immediate, { 0x4006800 }
34302 +  },
34303 +/* move.2 (${d-An})${d-i4-2}++,#${s1-imm8} */
34304 +  {
34305 +    { 0, 0, 0, 0 },
34306 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '#', OP (S1_IMM8), 0 } },
34307 +    & ifmt_move_2_d_indirect_with_post_increment_2_s1_immediate, { 0x2006800 }
34308 +  },
34309 +/* move.2 ${d-i4-2}(${d-An})++,#${s1-imm8} */
34310 +  {
34311 +    { 0, 0, 0, 0 },
34312 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), 0 } },
34313 +    & ifmt_move_2_d_indirect_with_pre_increment_2_s1_immediate, { 0x2106800 }
34314 +  },
34315 +/* move.2 ${d-direct-addr},(${s1-An},${s1-r}) */
34316 +  {
34317 +    { 0, 0, 0, 0 },
34318 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
34319 +    & ifmt_move_2_d_direct_s1_indirect_with_index_2, { 0x1006b00 }
34320 +  },
34321 +/* move.2 #${d-imm8},(${s1-An},${s1-r}) */
34322 +  {
34323 +    { 0, 0, 0, 0 },
34324 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
34325 +    & ifmt_move_2_d_immediate_2_s1_indirect_with_index_2, { 0x6b00 }
34326 +  },
34327 +/* move.2 (${d-An},${d-r}),(${s1-An},${s1-r}) */
34328 +  {
34329 +    { 0, 0, 0, 0 },
34330 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
34331 +    & ifmt_move_2_d_indirect_with_index_2_s1_indirect_with_index_2, { 0x3006b00 }
34332 +  },
34333 +/* move.2 ${d-imm7-2}(${d-An}),(${s1-An},${s1-r}) */
34334 +  {
34335 +    { 0, 0, 0, 0 },
34336 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
34337 +    & ifmt_move_2_d_indirect_with_offset_2_s1_indirect_with_index_2, { 0x4006b00 }
34338 +  },
34339 +/* move.2 (${d-An}),(${s1-An},${s1-r}) */
34340 +  {
34341 +    { 0, 0, 0, 0 },
34342 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
34343 +    & ifmt_move_2_d_indirect_2_s1_indirect_with_index_2, { 0x4006b00 }
34344 +  },
34345 +/* move.2 (${d-An})${d-i4-2}++,(${s1-An},${s1-r}) */
34346 +  {
34347 +    { 0, 0, 0, 0 },
34348 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
34349 +    & ifmt_move_2_d_indirect_with_post_increment_2_s1_indirect_with_index_2, { 0x2006b00 }
34350 +  },
34351 +/* move.2 ${d-i4-2}(${d-An})++,(${s1-An},${s1-r}) */
34352 +  {
34353 +    { 0, 0, 0, 0 },
34354 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
34355 +    & ifmt_move_2_d_indirect_with_pre_increment_2_s1_indirect_with_index_2, { 0x2106b00 }
34356 +  },
34357 +/* move.2 ${d-direct-addr},${s1-imm7-2}(${s1-An}) */
34358 +  {
34359 +    { 0, 0, 0, 0 },
34360 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } },
34361 +    & ifmt_move_2_d_direct_s1_indirect_with_offset_2, { 0x1006c00 }
34362 +  },
34363 +/* move.2 #${d-imm8},${s1-imm7-2}(${s1-An}) */
34364 +  {
34365 +    { 0, 0, 0, 0 },
34366 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } },
34367 +    & ifmt_move_2_d_immediate_2_s1_indirect_with_offset_2, { 0x6c00 }
34368 +  },
34369 +/* move.2 (${d-An},${d-r}),${s1-imm7-2}(${s1-An}) */
34370 +  {
34371 +    { 0, 0, 0, 0 },
34372 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } },
34373 +    & ifmt_move_2_d_indirect_with_index_2_s1_indirect_with_offset_2, { 0x3006c00 }
34374 +  },
34375 +/* move.2 ${d-imm7-2}(${d-An}),${s1-imm7-2}(${s1-An}) */
34376 +  {
34377 +    { 0, 0, 0, 0 },
34378 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } },
34379 +    & ifmt_move_2_d_indirect_with_offset_2_s1_indirect_with_offset_2, { 0x4006c00 }
34380 +  },
34381 +/* move.2 (${d-An}),${s1-imm7-2}(${s1-An}) */
34382 +  {
34383 +    { 0, 0, 0, 0 },
34384 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } },
34385 +    & ifmt_move_2_d_indirect_2_s1_indirect_with_offset_2, { 0x4006c00 }
34386 +  },
34387 +/* move.2 (${d-An})${d-i4-2}++,${s1-imm7-2}(${s1-An}) */
34388 +  {
34389 +    { 0, 0, 0, 0 },
34390 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } },
34391 +    & ifmt_move_2_d_indirect_with_post_increment_2_s1_indirect_with_offset_2, { 0x2006c00 }
34392 +  },
34393 +/* move.2 ${d-i4-2}(${d-An})++,${s1-imm7-2}(${s1-An}) */
34394 +  {
34395 +    { 0, 0, 0, 0 },
34396 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } },
34397 +    & ifmt_move_2_d_indirect_with_pre_increment_2_s1_indirect_with_offset_2, { 0x2106c00 }
34398 +  },
34399 +/* move.2 ${d-direct-addr},(${s1-An}) */
34400 +  {
34401 +    { 0, 0, 0, 0 },
34402 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', 0 } },
34403 +    & ifmt_move_2_d_direct_s1_indirect_2, { 0x1006c00 }
34404 +  },
34405 +/* move.2 #${d-imm8},(${s1-An}) */
34406 +  {
34407 +    { 0, 0, 0, 0 },
34408 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', 0 } },
34409 +    & ifmt_move_2_d_immediate_2_s1_indirect_2, { 0x6c00 }
34410 +  },
34411 +/* move.2 (${d-An},${d-r}),(${s1-An}) */
34412 +  {
34413 +    { 0, 0, 0, 0 },
34414 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', 0 } },
34415 +    & ifmt_move_2_d_indirect_with_index_2_s1_indirect_2, { 0x3006c00 }
34416 +  },
34417 +/* move.2 ${d-imm7-2}(${d-An}),(${s1-An}) */
34418 +  {
34419 +    { 0, 0, 0, 0 },
34420 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } },
34421 +    & ifmt_move_2_d_indirect_with_offset_2_s1_indirect_2, { 0x4006c00 }
34422 +  },
34423 +/* move.2 (${d-An}),(${s1-An}) */
34424 +  {
34425 +    { 0, 0, 0, 0 },
34426 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } },
34427 +    & ifmt_move_2_d_indirect_2_s1_indirect_2, { 0x4006c00 }
34428 +  },
34429 +/* move.2 (${d-An})${d-i4-2}++,(${s1-An}) */
34430 +  {
34431 +    { 0, 0, 0, 0 },
34432 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ')', 0 } },
34433 +    & ifmt_move_2_d_indirect_with_post_increment_2_s1_indirect_2, { 0x2006c00 }
34434 +  },
34435 +/* move.2 ${d-i4-2}(${d-An})++,(${s1-An}) */
34436 +  {
34437 +    { 0, 0, 0, 0 },
34438 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', 0 } },
34439 +    & ifmt_move_2_d_indirect_with_pre_increment_2_s1_indirect_2, { 0x2106c00 }
34440 +  },
34441 +/* move.2 ${d-direct-addr},(${s1-An})${s1-i4-2}++ */
34442 +  {
34443 +    { 0, 0, 0, 0 },
34444 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } },
34445 +    & ifmt_move_2_d_direct_s1_indirect_with_post_increment_2, { 0x1006a00 }
34446 +  },
34447 +/* move.2 #${d-imm8},(${s1-An})${s1-i4-2}++ */
34448 +  {
34449 +    { 0, 0, 0, 0 },
34450 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } },
34451 +    & ifmt_move_2_d_immediate_2_s1_indirect_with_post_increment_2, { 0x6a00 }
34452 +  },
34453 +/* move.2 (${d-An},${d-r}),(${s1-An})${s1-i4-2}++ */
34454 +  {
34455 +    { 0, 0, 0, 0 },
34456 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } },
34457 +    & ifmt_move_2_d_indirect_with_index_2_s1_indirect_with_post_increment_2, { 0x3006a00 }
34458 +  },
34459 +/* move.2 ${d-imm7-2}(${d-An}),(${s1-An})${s1-i4-2}++ */
34460 +  {
34461 +    { 0, 0, 0, 0 },
34462 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } },
34463 +    & ifmt_move_2_d_indirect_with_offset_2_s1_indirect_with_post_increment_2, { 0x4006a00 }
34464 +  },
34465 +/* move.2 (${d-An}),(${s1-An})${s1-i4-2}++ */
34466 +  {
34467 +    { 0, 0, 0, 0 },
34468 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } },
34469 +    & ifmt_move_2_d_indirect_2_s1_indirect_with_post_increment_2, { 0x4006a00 }
34470 +  },
34471 +/* move.2 (${d-An})${d-i4-2}++,(${s1-An})${s1-i4-2}++ */
34472 +  {
34473 +    { 0, 0, 0, 0 },
34474 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } },
34475 +    & ifmt_move_2_d_indirect_with_post_increment_2_s1_indirect_with_post_increment_2, { 0x2006a00 }
34476 +  },
34477 +/* move.2 ${d-i4-2}(${d-An})++,(${s1-An})${s1-i4-2}++ */
34478 +  {
34479 +    { 0, 0, 0, 0 },
34480 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } },
34481 +    & ifmt_move_2_d_indirect_with_pre_increment_2_s1_indirect_with_post_increment_2, { 0x2106a00 }
34482 +  },
34483 +/* move.2 ${d-direct-addr},${s1-i4-2}(${s1-An})++ */
34484 +  {
34485 +    { 0, 0, 0, 0 },
34486 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } },
34487 +    & ifmt_move_2_d_direct_s1_indirect_with_pre_increment_2, { 0x1006a10 }
34488 +  },
34489 +/* move.2 #${d-imm8},${s1-i4-2}(${s1-An})++ */
34490 +  {
34491 +    { 0, 0, 0, 0 },
34492 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } },
34493 +    & ifmt_move_2_d_immediate_2_s1_indirect_with_pre_increment_2, { 0x6a10 }
34494 +  },
34495 +/* move.2 (${d-An},${d-r}),${s1-i4-2}(${s1-An})++ */
34496 +  {
34497 +    { 0, 0, 0, 0 },
34498 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } },
34499 +    & ifmt_move_2_d_indirect_with_index_2_s1_indirect_with_pre_increment_2, { 0x3006a10 }
34500 +  },
34501 +/* move.2 ${d-imm7-2}(${d-An}),${s1-i4-2}(${s1-An})++ */
34502 +  {
34503 +    { 0, 0, 0, 0 },
34504 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } },
34505 +    & ifmt_move_2_d_indirect_with_offset_2_s1_indirect_with_pre_increment_2, { 0x4006a10 }
34506 +  },
34507 +/* move.2 (${d-An}),${s1-i4-2}(${s1-An})++ */
34508 +  {
34509 +    { 0, 0, 0, 0 },
34510 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } },
34511 +    & ifmt_move_2_d_indirect_2_s1_indirect_with_pre_increment_2, { 0x4006a10 }
34512 +  },
34513 +/* move.2 (${d-An})${d-i4-2}++,${s1-i4-2}(${s1-An})++ */
34514 +  {
34515 +    { 0, 0, 0, 0 },
34516 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } },
34517 +    & ifmt_move_2_d_indirect_with_post_increment_2_s1_indirect_with_pre_increment_2, { 0x2006a10 }
34518 +  },
34519 +/* move.2 ${d-i4-2}(${d-An})++,${s1-i4-2}(${s1-An})++ */
34520 +  {
34521 +    { 0, 0, 0, 0 },
34522 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } },
34523 +    & ifmt_move_2_d_indirect_with_pre_increment_2_s1_indirect_with_pre_increment_2, { 0x2106a10 }
34524 +  },
34525 +/* move.1 ${d-direct-addr},${s1-direct-addr} */
34526 +  {
34527 +    { 0, 0, 0, 0 },
34528 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), 0 } },
34529 +    & ifmt_movea_d_direct_s1_direct, { 0x1007900 }
34530 +  },
34531 +/* move.1 #${d-imm8},${s1-direct-addr} */
34532 +  {
34533 +    { 0, 0, 0, 0 },
34534 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), 0 } },
34535 +    & ifmt_move_1_d_immediate_1_s1_direct, { 0x7900 }
34536 +  },
34537 +/* move.1 (${d-An},${d-r}),${s1-direct-addr} */
34538 +  {
34539 +    { 0, 0, 0, 0 },
34540 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), 0 } },
34541 +    & ifmt_move_1_d_indirect_with_index_1_s1_direct, { 0x3007900 }
34542 +  },
34543 +/* move.1 ${d-imm7-1}(${d-An}),${s1-direct-addr} */
34544 +  {
34545 +    { 0, 0, 0, 0 },
34546 +    { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), 0 } },
34547 +    & ifmt_move_1_d_indirect_with_offset_1_s1_direct, { 0x4007900 }
34548 +  },
34549 +/* move.1 (${d-An}),${s1-direct-addr} */
34550 +  {
34551 +    { 0, 0, 0, 0 },
34552 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), 0 } },
34553 +    & ifmt_move_1_d_indirect_1_s1_direct, { 0x4007900 }
34554 +  },
34555 +/* move.1 (${d-An})${d-i4-1}++,${s1-direct-addr} */
34556 +  {
34557 +    { 0, 0, 0, 0 },
34558 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', OP (S1_DIRECT_ADDR), 0 } },
34559 +    & ifmt_move_1_d_indirect_with_post_increment_1_s1_direct, { 0x2007900 }
34560 +  },
34561 +/* move.1 ${d-i4-1}(${d-An})++,${s1-direct-addr} */
34562 +  {
34563 +    { 0, 0, 0, 0 },
34564 +    { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), 0 } },
34565 +    & ifmt_move_1_d_indirect_with_pre_increment_1_s1_direct, { 0x2107900 }
34566 +  },
34567 +/* move.1 ${d-direct-addr},#${s1-imm8} */
34568 +  {
34569 +    { 0, 0, 0, 0 },
34570 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), 0 } },
34571 +    & ifmt_movea_d_direct_s1_immediate, { 0x1007800 }
34572 +  },
34573 +/* move.1 #${d-imm8},#${s1-imm8} */
34574 +  {
34575 +    { 0, 0, 0, 0 },
34576 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), 0 } },
34577 +    & ifmt_move_1_d_immediate_1_s1_immediate, { 0x7800 }
34578 +  },
34579 +/* move.1 (${d-An},${d-r}),#${s1-imm8} */
34580 +  {
34581 +    { 0, 0, 0, 0 },
34582 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), 0 } },
34583 +    & ifmt_move_1_d_indirect_with_index_1_s1_immediate, { 0x3007800 }
34584 +  },
34585 +/* move.1 ${d-imm7-1}(${d-An}),#${s1-imm8} */
34586 +  {
34587 +    { 0, 0, 0, 0 },
34588 +    { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } },
34589 +    & ifmt_move_1_d_indirect_with_offset_1_s1_immediate, { 0x4007800 }
34590 +  },
34591 +/* move.1 (${d-An}),#${s1-imm8} */
34592 +  {
34593 +    { 0, 0, 0, 0 },
34594 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } },
34595 +    & ifmt_move_1_d_indirect_1_s1_immediate, { 0x4007800 }
34596 +  },
34597 +/* move.1 (${d-An})${d-i4-1}++,#${s1-imm8} */
34598 +  {
34599 +    { 0, 0, 0, 0 },
34600 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', '#', OP (S1_IMM8), 0 } },
34601 +    & ifmt_move_1_d_indirect_with_post_increment_1_s1_immediate, { 0x2007800 }
34602 +  },
34603 +/* move.1 ${d-i4-1}(${d-An})++,#${s1-imm8} */
34604 +  {
34605 +    { 0, 0, 0, 0 },
34606 +    { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), 0 } },
34607 +    & ifmt_move_1_d_indirect_with_pre_increment_1_s1_immediate, { 0x2107800 }
34608 +  },
34609 +/* move.1 ${d-direct-addr},(${s1-An},${s1-r}) */
34610 +  {
34611 +    { 0, 0, 0, 0 },
34612 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
34613 +    & ifmt_move_1_d_direct_s1_indirect_with_index_1, { 0x1007b00 }
34614 +  },
34615 +/* move.1 #${d-imm8},(${s1-An},${s1-r}) */
34616 +  {
34617 +    { 0, 0, 0, 0 },
34618 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
34619 +    & ifmt_move_1_d_immediate_1_s1_indirect_with_index_1, { 0x7b00 }
34620 +  },
34621 +/* move.1 (${d-An},${d-r}),(${s1-An},${s1-r}) */
34622 +  {
34623 +    { 0, 0, 0, 0 },
34624 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
34625 +    & ifmt_move_1_d_indirect_with_index_1_s1_indirect_with_index_1, { 0x3007b00 }
34626 +  },
34627 +/* move.1 ${d-imm7-1}(${d-An}),(${s1-An},${s1-r}) */
34628 +  {
34629 +    { 0, 0, 0, 0 },
34630 +    { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
34631 +    & ifmt_move_1_d_indirect_with_offset_1_s1_indirect_with_index_1, { 0x4007b00 }
34632 +  },
34633 +/* move.1 (${d-An}),(${s1-An},${s1-r}) */
34634 +  {
34635 +    { 0, 0, 0, 0 },
34636 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
34637 +    & ifmt_move_1_d_indirect_1_s1_indirect_with_index_1, { 0x4007b00 }
34638 +  },
34639 +/* move.1 (${d-An})${d-i4-1}++,(${s1-An},${s1-r}) */
34640 +  {
34641 +    { 0, 0, 0, 0 },
34642 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
34643 +    & ifmt_move_1_d_indirect_with_post_increment_1_s1_indirect_with_index_1, { 0x2007b00 }
34644 +  },
34645 +/* move.1 ${d-i4-1}(${d-An})++,(${s1-An},${s1-r}) */
34646 +  {
34647 +    { 0, 0, 0, 0 },
34648 +    { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
34649 +    & ifmt_move_1_d_indirect_with_pre_increment_1_s1_indirect_with_index_1, { 0x2107b00 }
34650 +  },
34651 +/* move.1 ${d-direct-addr},${s1-imm7-1}(${s1-An}) */
34652 +  {
34653 +    { 0, 0, 0, 0 },
34654 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', 0 } },
34655 +    & ifmt_move_1_d_direct_s1_indirect_with_offset_1, { 0x1007c00 }
34656 +  },
34657 +/* move.1 #${d-imm8},${s1-imm7-1}(${s1-An}) */
34658 +  {
34659 +    { 0, 0, 0, 0 },
34660 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', 0 } },
34661 +    & ifmt_move_1_d_immediate_1_s1_indirect_with_offset_1, { 0x7c00 }
34662 +  },
34663 +/* move.1 (${d-An},${d-r}),${s1-imm7-1}(${s1-An}) */
34664 +  {
34665 +    { 0, 0, 0, 0 },
34666 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', 0 } },
34667 +    & ifmt_move_1_d_indirect_with_index_1_s1_indirect_with_offset_1, { 0x3007c00 }
34668 +  },
34669 +/* move.1 ${d-imm7-1}(${d-An}),${s1-imm7-1}(${s1-An}) */
34670 +  {
34671 +    { 0, 0, 0, 0 },
34672 +    { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', 0 } },
34673 +    & ifmt_move_1_d_indirect_with_offset_1_s1_indirect_with_offset_1, { 0x4007c00 }
34674 +  },
34675 +/* move.1 (${d-An}),${s1-imm7-1}(${s1-An}) */
34676 +  {
34677 +    { 0, 0, 0, 0 },
34678 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', 0 } },
34679 +    & ifmt_move_1_d_indirect_1_s1_indirect_with_offset_1, { 0x4007c00 }
34680 +  },
34681 +/* move.1 (${d-An})${d-i4-1}++,${s1-imm7-1}(${s1-An}) */
34682 +  {
34683 +    { 0, 0, 0, 0 },
34684 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', 0 } },
34685 +    & ifmt_move_1_d_indirect_with_post_increment_1_s1_indirect_with_offset_1, { 0x2007c00 }
34686 +  },
34687 +/* move.1 ${d-i4-1}(${d-An})++,${s1-imm7-1}(${s1-An}) */
34688 +  {
34689 +    { 0, 0, 0, 0 },
34690 +    { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', 0 } },
34691 +    & ifmt_move_1_d_indirect_with_pre_increment_1_s1_indirect_with_offset_1, { 0x2107c00 }
34692 +  },
34693 +/* move.1 ${d-direct-addr},(${s1-An}) */
34694 +  {
34695 +    { 0, 0, 0, 0 },
34696 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', 0 } },
34697 +    & ifmt_move_1_d_direct_s1_indirect_1, { 0x1007c00 }
34698 +  },
34699 +/* move.1 #${d-imm8},(${s1-An}) */
34700 +  {
34701 +    { 0, 0, 0, 0 },
34702 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', 0 } },
34703 +    & ifmt_move_1_d_immediate_1_s1_indirect_1, { 0x7c00 }
34704 +  },
34705 +/* move.1 (${d-An},${d-r}),(${s1-An}) */
34706 +  {
34707 +    { 0, 0, 0, 0 },
34708 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', 0 } },
34709 +    & ifmt_move_1_d_indirect_with_index_1_s1_indirect_1, { 0x3007c00 }
34710 +  },
34711 +/* move.1 ${d-imm7-1}(${d-An}),(${s1-An}) */
34712 +  {
34713 +    { 0, 0, 0, 0 },
34714 +    { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } },
34715 +    & ifmt_move_1_d_indirect_with_offset_1_s1_indirect_1, { 0x4007c00 }
34716 +  },
34717 +/* move.1 (${d-An}),(${s1-An}) */
34718 +  {
34719 +    { 0, 0, 0, 0 },
34720 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } },
34721 +    & ifmt_move_1_d_indirect_1_s1_indirect_1, { 0x4007c00 }
34722 +  },
34723 +/* move.1 (${d-An})${d-i4-1}++,(${s1-An}) */
34724 +  {
34725 +    { 0, 0, 0, 0 },
34726 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', '(', OP (S1_AN), ')', 0 } },
34727 +    & ifmt_move_1_d_indirect_with_post_increment_1_s1_indirect_1, { 0x2007c00 }
34728 +  },
34729 +/* move.1 ${d-i4-1}(${d-An})++,(${s1-An}) */
34730 +  {
34731 +    { 0, 0, 0, 0 },
34732 +    { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', 0 } },
34733 +    & ifmt_move_1_d_indirect_with_pre_increment_1_s1_indirect_1, { 0x2107c00 }
34734 +  },
34735 +/* move.1 ${d-direct-addr},(${s1-An})${s1-i4-1}++ */
34736 +  {
34737 +    { 0, 0, 0, 0 },
34738 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', 0 } },
34739 +    & ifmt_move_1_d_direct_s1_indirect_with_post_increment_1, { 0x1007a00 }
34740 +  },
34741 +/* move.1 #${d-imm8},(${s1-An})${s1-i4-1}++ */
34742 +  {
34743 +    { 0, 0, 0, 0 },
34744 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', 0 } },
34745 +    & ifmt_move_1_d_immediate_1_s1_indirect_with_post_increment_1, { 0x7a00 }
34746 +  },
34747 +/* move.1 (${d-An},${d-r}),(${s1-An})${s1-i4-1}++ */
34748 +  {
34749 +    { 0, 0, 0, 0 },
34750 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', 0 } },
34751 +    & ifmt_move_1_d_indirect_with_index_1_s1_indirect_with_post_increment_1, { 0x3007a00 }
34752 +  },
34753 +/* move.1 ${d-imm7-1}(${d-An}),(${s1-An})${s1-i4-1}++ */
34754 +  {
34755 +    { 0, 0, 0, 0 },
34756 +    { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', 0 } },
34757 +    & ifmt_move_1_d_indirect_with_offset_1_s1_indirect_with_post_increment_1, { 0x4007a00 }
34758 +  },
34759 +/* move.1 (${d-An}),(${s1-An})${s1-i4-1}++ */
34760 +  {
34761 +    { 0, 0, 0, 0 },
34762 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', 0 } },
34763 +    & ifmt_move_1_d_indirect_1_s1_indirect_with_post_increment_1, { 0x4007a00 }
34764 +  },
34765 +/* move.1 (${d-An})${d-i4-1}++,(${s1-An})${s1-i4-1}++ */
34766 +  {
34767 +    { 0, 0, 0, 0 },
34768 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', 0 } },
34769 +    & ifmt_move_1_d_indirect_with_post_increment_1_s1_indirect_with_post_increment_1, { 0x2007a00 }
34770 +  },
34771 +/* move.1 ${d-i4-1}(${d-An})++,(${s1-An})${s1-i4-1}++ */
34772 +  {
34773 +    { 0, 0, 0, 0 },
34774 +    { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', 0 } },
34775 +    & ifmt_move_1_d_indirect_with_pre_increment_1_s1_indirect_with_post_increment_1, { 0x2107a00 }
34776 +  },
34777 +/* move.1 ${d-direct-addr},${s1-i4-1}(${s1-An})++ */
34778 +  {
34779 +    { 0, 0, 0, 0 },
34780 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', 0 } },
34781 +    & ifmt_move_1_d_direct_s1_indirect_with_pre_increment_1, { 0x1007a10 }
34782 +  },
34783 +/* move.1 #${d-imm8},${s1-i4-1}(${s1-An})++ */
34784 +  {
34785 +    { 0, 0, 0, 0 },
34786 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', 0 } },
34787 +    & ifmt_move_1_d_immediate_1_s1_indirect_with_pre_increment_1, { 0x7a10 }
34788 +  },
34789 +/* move.1 (${d-An},${d-r}),${s1-i4-1}(${s1-An})++ */
34790 +  {
34791 +    { 0, 0, 0, 0 },
34792 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', 0 } },
34793 +    & ifmt_move_1_d_indirect_with_index_1_s1_indirect_with_pre_increment_1, { 0x3007a10 }
34794 +  },
34795 +/* move.1 ${d-imm7-1}(${d-An}),${s1-i4-1}(${s1-An})++ */
34796 +  {
34797 +    { 0, 0, 0, 0 },
34798 +    { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', 0 } },
34799 +    & ifmt_move_1_d_indirect_with_offset_1_s1_indirect_with_pre_increment_1, { 0x4007a10 }
34800 +  },
34801 +/* move.1 (${d-An}),${s1-i4-1}(${s1-An})++ */
34802 +  {
34803 +    { 0, 0, 0, 0 },
34804 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', 0 } },
34805 +    & ifmt_move_1_d_indirect_1_s1_indirect_with_pre_increment_1, { 0x4007a10 }
34806 +  },
34807 +/* move.1 (${d-An})${d-i4-1}++,${s1-i4-1}(${s1-An})++ */
34808 +  {
34809 +    { 0, 0, 0, 0 },
34810 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', 0 } },
34811 +    & ifmt_move_1_d_indirect_with_post_increment_1_s1_indirect_with_pre_increment_1, { 0x2007a10 }
34812 +  },
34813 +/* move.1 ${d-i4-1}(${d-An})++,${s1-i4-1}(${s1-An})++ */
34814 +  {
34815 +    { 0, 0, 0, 0 },
34816 +    { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', 0 } },
34817 +    & ifmt_move_1_d_indirect_with_pre_increment_1_s1_indirect_with_pre_increment_1, { 0x2107a10 }
34818 +  },
34819 +/* ext.2 ${d-direct-addr},${s1-direct-addr} */
34820 +  {
34821 +    { 0, 0, 0, 0 },
34822 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), 0 } },
34823 +    & ifmt_movea_d_direct_s1_direct, { 0x100a900 }
34824 +  },
34825 +/* ext.2 #${d-imm8},${s1-direct-addr} */
34826 +  {
34827 +    { 0, 0, 0, 0 },
34828 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), 0 } },
34829 +    & ifmt_move_2_d_immediate_2_s1_direct, { 0xa900 }
34830 +  },
34831 +/* ext.2 (${d-An},${d-r}),${s1-direct-addr} */
34832 +  {
34833 +    { 0, 0, 0, 0 },
34834 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), 0 } },
34835 +    & ifmt_move_2_d_indirect_with_index_2_s1_direct, { 0x300a900 }
34836 +  },
34837 +/* ext.2 ${d-imm7-2}(${d-An}),${s1-direct-addr} */
34838 +  {
34839 +    { 0, 0, 0, 0 },
34840 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), 0 } },
34841 +    & ifmt_move_2_d_indirect_with_offset_2_s1_direct, { 0x400a900 }
34842 +  },
34843 +/* ext.2 (${d-An}),${s1-direct-addr} */
34844 +  {
34845 +    { 0, 0, 0, 0 },
34846 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), 0 } },
34847 +    & ifmt_move_2_d_indirect_2_s1_direct, { 0x400a900 }
34848 +  },
34849 +/* ext.2 (${d-An})${d-i4-2}++,${s1-direct-addr} */
34850 +  {
34851 +    { 0, 0, 0, 0 },
34852 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_DIRECT_ADDR), 0 } },
34853 +    & ifmt_move_2_d_indirect_with_post_increment_2_s1_direct, { 0x200a900 }
34854 +  },
34855 +/* ext.2 ${d-i4-2}(${d-An})++,${s1-direct-addr} */
34856 +  {
34857 +    { 0, 0, 0, 0 },
34858 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), 0 } },
34859 +    & ifmt_move_2_d_indirect_with_pre_increment_2_s1_direct, { 0x210a900 }
34860 +  },
34861 +/* ext.2 ${d-direct-addr},#${s1-imm8} */
34862 +  {
34863 +    { 0, 0, 0, 0 },
34864 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), 0 } },
34865 +    & ifmt_movea_d_direct_s1_immediate, { 0x100a800 }
34866 +  },
34867 +/* ext.2 #${d-imm8},#${s1-imm8} */
34868 +  {
34869 +    { 0, 0, 0, 0 },
34870 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), 0 } },
34871 +    & ifmt_move_2_d_immediate_2_s1_immediate, { 0xa800 }
34872 +  },
34873 +/* ext.2 (${d-An},${d-r}),#${s1-imm8} */
34874 +  {
34875 +    { 0, 0, 0, 0 },
34876 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), 0 } },
34877 +    & ifmt_move_2_d_indirect_with_index_2_s1_immediate, { 0x300a800 }
34878 +  },
34879 +/* ext.2 ${d-imm7-2}(${d-An}),#${s1-imm8} */
34880 +  {
34881 +    { 0, 0, 0, 0 },
34882 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } },
34883 +    & ifmt_move_2_d_indirect_with_offset_2_s1_immediate, { 0x400a800 }
34884 +  },
34885 +/* ext.2 (${d-An}),#${s1-imm8} */
34886 +  {
34887 +    { 0, 0, 0, 0 },
34888 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } },
34889 +    & ifmt_move_2_d_indirect_2_s1_immediate, { 0x400a800 }
34890 +  },
34891 +/* ext.2 (${d-An})${d-i4-2}++,#${s1-imm8} */
34892 +  {
34893 +    { 0, 0, 0, 0 },
34894 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '#', OP (S1_IMM8), 0 } },
34895 +    & ifmt_move_2_d_indirect_with_post_increment_2_s1_immediate, { 0x200a800 }
34896 +  },
34897 +/* ext.2 ${d-i4-2}(${d-An})++,#${s1-imm8} */
34898 +  {
34899 +    { 0, 0, 0, 0 },
34900 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), 0 } },
34901 +    & ifmt_move_2_d_indirect_with_pre_increment_2_s1_immediate, { 0x210a800 }
34902 +  },
34903 +/* ext.2 ${d-direct-addr},(${s1-An},${s1-r}) */
34904 +  {
34905 +    { 0, 0, 0, 0 },
34906 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
34907 +    & ifmt_move_2_d_direct_s1_indirect_with_index_2, { 0x100ab00 }
34908 +  },
34909 +/* ext.2 #${d-imm8},(${s1-An},${s1-r}) */
34910 +  {
34911 +    { 0, 0, 0, 0 },
34912 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
34913 +    & ifmt_move_2_d_immediate_2_s1_indirect_with_index_2, { 0xab00 }
34914 +  },
34915 +/* ext.2 (${d-An},${d-r}),(${s1-An},${s1-r}) */
34916 +  {
34917 +    { 0, 0, 0, 0 },
34918 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
34919 +    & ifmt_move_2_d_indirect_with_index_2_s1_indirect_with_index_2, { 0x300ab00 }
34920 +  },
34921 +/* ext.2 ${d-imm7-2}(${d-An}),(${s1-An},${s1-r}) */
34922 +  {
34923 +    { 0, 0, 0, 0 },
34924 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
34925 +    & ifmt_move_2_d_indirect_with_offset_2_s1_indirect_with_index_2, { 0x400ab00 }
34926 +  },
34927 +/* ext.2 (${d-An}),(${s1-An},${s1-r}) */
34928 +  {
34929 +    { 0, 0, 0, 0 },
34930 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
34931 +    & ifmt_move_2_d_indirect_2_s1_indirect_with_index_2, { 0x400ab00 }
34932 +  },
34933 +/* ext.2 (${d-An})${d-i4-2}++,(${s1-An},${s1-r}) */
34934 +  {
34935 +    { 0, 0, 0, 0 },
34936 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
34937 +    & ifmt_move_2_d_indirect_with_post_increment_2_s1_indirect_with_index_2, { 0x200ab00 }
34938 +  },
34939 +/* ext.2 ${d-i4-2}(${d-An})++,(${s1-An},${s1-r}) */
34940 +  {
34941 +    { 0, 0, 0, 0 },
34942 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
34943 +    & ifmt_move_2_d_indirect_with_pre_increment_2_s1_indirect_with_index_2, { 0x210ab00 }
34944 +  },
34945 +/* ext.2 ${d-direct-addr},${s1-imm7-2}(${s1-An}) */
34946 +  {
34947 +    { 0, 0, 0, 0 },
34948 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } },
34949 +    & ifmt_move_2_d_direct_s1_indirect_with_offset_2, { 0x100ac00 }
34950 +  },
34951 +/* ext.2 #${d-imm8},${s1-imm7-2}(${s1-An}) */
34952 +  {
34953 +    { 0, 0, 0, 0 },
34954 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } },
34955 +    & ifmt_move_2_d_immediate_2_s1_indirect_with_offset_2, { 0xac00 }
34956 +  },
34957 +/* ext.2 (${d-An},${d-r}),${s1-imm7-2}(${s1-An}) */
34958 +  {
34959 +    { 0, 0, 0, 0 },
34960 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } },
34961 +    & ifmt_move_2_d_indirect_with_index_2_s1_indirect_with_offset_2, { 0x300ac00 }
34962 +  },
34963 +/* ext.2 ${d-imm7-2}(${d-An}),${s1-imm7-2}(${s1-An}) */
34964 +  {
34965 +    { 0, 0, 0, 0 },
34966 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } },
34967 +    & ifmt_move_2_d_indirect_with_offset_2_s1_indirect_with_offset_2, { 0x400ac00 }
34968 +  },
34969 +/* ext.2 (${d-An}),${s1-imm7-2}(${s1-An}) */
34970 +  {
34971 +    { 0, 0, 0, 0 },
34972 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } },
34973 +    & ifmt_move_2_d_indirect_2_s1_indirect_with_offset_2, { 0x400ac00 }
34974 +  },
34975 +/* ext.2 (${d-An})${d-i4-2}++,${s1-imm7-2}(${s1-An}) */
34976 +  {
34977 +    { 0, 0, 0, 0 },
34978 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } },
34979 +    & ifmt_move_2_d_indirect_with_post_increment_2_s1_indirect_with_offset_2, { 0x200ac00 }
34980 +  },
34981 +/* ext.2 ${d-i4-2}(${d-An})++,${s1-imm7-2}(${s1-An}) */
34982 +  {
34983 +    { 0, 0, 0, 0 },
34984 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } },
34985 +    & ifmt_move_2_d_indirect_with_pre_increment_2_s1_indirect_with_offset_2, { 0x210ac00 }
34986 +  },
34987 +/* ext.2 ${d-direct-addr},(${s1-An}) */
34988 +  {
34989 +    { 0, 0, 0, 0 },
34990 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', 0 } },
34991 +    & ifmt_move_2_d_direct_s1_indirect_2, { 0x100ac00 }
34992 +  },
34993 +/* ext.2 #${d-imm8},(${s1-An}) */
34994 +  {
34995 +    { 0, 0, 0, 0 },
34996 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', 0 } },
34997 +    & ifmt_move_2_d_immediate_2_s1_indirect_2, { 0xac00 }
34998 +  },
34999 +/* ext.2 (${d-An},${d-r}),(${s1-An}) */
35000 +  {
35001 +    { 0, 0, 0, 0 },
35002 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', 0 } },
35003 +    & ifmt_move_2_d_indirect_with_index_2_s1_indirect_2, { 0x300ac00 }
35004 +  },
35005 +/* ext.2 ${d-imm7-2}(${d-An}),(${s1-An}) */
35006 +  {
35007 +    { 0, 0, 0, 0 },
35008 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } },
35009 +    & ifmt_move_2_d_indirect_with_offset_2_s1_indirect_2, { 0x400ac00 }
35010 +  },
35011 +/* ext.2 (${d-An}),(${s1-An}) */
35012 +  {
35013 +    { 0, 0, 0, 0 },
35014 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } },
35015 +    & ifmt_move_2_d_indirect_2_s1_indirect_2, { 0x400ac00 }
35016 +  },
35017 +/* ext.2 (${d-An})${d-i4-2}++,(${s1-An}) */
35018 +  {
35019 +    { 0, 0, 0, 0 },
35020 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ')', 0 } },
35021 +    & ifmt_move_2_d_indirect_with_post_increment_2_s1_indirect_2, { 0x200ac00 }
35022 +  },
35023 +/* ext.2 ${d-i4-2}(${d-An})++,(${s1-An}) */
35024 +  {
35025 +    { 0, 0, 0, 0 },
35026 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', 0 } },
35027 +    & ifmt_move_2_d_indirect_with_pre_increment_2_s1_indirect_2, { 0x210ac00 }
35028 +  },
35029 +/* ext.2 ${d-direct-addr},(${s1-An})${s1-i4-2}++ */
35030 +  {
35031 +    { 0, 0, 0, 0 },
35032 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } },
35033 +    & ifmt_move_2_d_direct_s1_indirect_with_post_increment_2, { 0x100aa00 }
35034 +  },
35035 +/* ext.2 #${d-imm8},(${s1-An})${s1-i4-2}++ */
35036 +  {
35037 +    { 0, 0, 0, 0 },
35038 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } },
35039 +    & ifmt_move_2_d_immediate_2_s1_indirect_with_post_increment_2, { 0xaa00 }
35040 +  },
35041 +/* ext.2 (${d-An},${d-r}),(${s1-An})${s1-i4-2}++ */
35042 +  {
35043 +    { 0, 0, 0, 0 },
35044 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } },
35045 +    & ifmt_move_2_d_indirect_with_index_2_s1_indirect_with_post_increment_2, { 0x300aa00 }
35046 +  },
35047 +/* ext.2 ${d-imm7-2}(${d-An}),(${s1-An})${s1-i4-2}++ */
35048 +  {
35049 +    { 0, 0, 0, 0 },
35050 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } },
35051 +    & ifmt_move_2_d_indirect_with_offset_2_s1_indirect_with_post_increment_2, { 0x400aa00 }
35052 +  },
35053 +/* ext.2 (${d-An}),(${s1-An})${s1-i4-2}++ */
35054 +  {
35055 +    { 0, 0, 0, 0 },
35056 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } },
35057 +    & ifmt_move_2_d_indirect_2_s1_indirect_with_post_increment_2, { 0x400aa00 }
35058 +  },
35059 +/* ext.2 (${d-An})${d-i4-2}++,(${s1-An})${s1-i4-2}++ */
35060 +  {
35061 +    { 0, 0, 0, 0 },
35062 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } },
35063 +    & ifmt_move_2_d_indirect_with_post_increment_2_s1_indirect_with_post_increment_2, { 0x200aa00 }
35064 +  },
35065 +/* ext.2 ${d-i4-2}(${d-An})++,(${s1-An})${s1-i4-2}++ */
35066 +  {
35067 +    { 0, 0, 0, 0 },
35068 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } },
35069 +    & ifmt_move_2_d_indirect_with_pre_increment_2_s1_indirect_with_post_increment_2, { 0x210aa00 }
35070 +  },
35071 +/* ext.2 ${d-direct-addr},${s1-i4-2}(${s1-An})++ */
35072 +  {
35073 +    { 0, 0, 0, 0 },
35074 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } },
35075 +    & ifmt_move_2_d_direct_s1_indirect_with_pre_increment_2, { 0x100aa10 }
35076 +  },
35077 +/* ext.2 #${d-imm8},${s1-i4-2}(${s1-An})++ */
35078 +  {
35079 +    { 0, 0, 0, 0 },
35080 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } },
35081 +    & ifmt_move_2_d_immediate_2_s1_indirect_with_pre_increment_2, { 0xaa10 }
35082 +  },
35083 +/* ext.2 (${d-An},${d-r}),${s1-i4-2}(${s1-An})++ */
35084 +  {
35085 +    { 0, 0, 0, 0 },
35086 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } },
35087 +    & ifmt_move_2_d_indirect_with_index_2_s1_indirect_with_pre_increment_2, { 0x300aa10 }
35088 +  },
35089 +/* ext.2 ${d-imm7-2}(${d-An}),${s1-i4-2}(${s1-An})++ */
35090 +  {
35091 +    { 0, 0, 0, 0 },
35092 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } },
35093 +    & ifmt_move_2_d_indirect_with_offset_2_s1_indirect_with_pre_increment_2, { 0x400aa10 }
35094 +  },
35095 +/* ext.2 (${d-An}),${s1-i4-2}(${s1-An})++ */
35096 +  {
35097 +    { 0, 0, 0, 0 },
35098 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } },
35099 +    & ifmt_move_2_d_indirect_2_s1_indirect_with_pre_increment_2, { 0x400aa10 }
35100 +  },
35101 +/* ext.2 (${d-An})${d-i4-2}++,${s1-i4-2}(${s1-An})++ */
35102 +  {
35103 +    { 0, 0, 0, 0 },
35104 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } },
35105 +    & ifmt_move_2_d_indirect_with_post_increment_2_s1_indirect_with_pre_increment_2, { 0x200aa10 }
35106 +  },
35107 +/* ext.2 ${d-i4-2}(${d-An})++,${s1-i4-2}(${s1-An})++ */
35108 +  {
35109 +    { 0, 0, 0, 0 },
35110 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } },
35111 +    & ifmt_move_2_d_indirect_with_pre_increment_2_s1_indirect_with_pre_increment_2, { 0x210aa10 }
35112 +  },
35113 +/* ext.1 ${d-direct-addr},${s1-direct-addr} */
35114 +  {
35115 +    { 0, 0, 0, 0 },
35116 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), 0 } },
35117 +    & ifmt_movea_d_direct_s1_direct, { 0x100b900 }
35118 +  },
35119 +/* ext.1 #${d-imm8},${s1-direct-addr} */
35120 +  {
35121 +    { 0, 0, 0, 0 },
35122 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), 0 } },
35123 +    & ifmt_move_1_d_immediate_1_s1_direct, { 0xb900 }
35124 +  },
35125 +/* ext.1 (${d-An},${d-r}),${s1-direct-addr} */
35126 +  {
35127 +    { 0, 0, 0, 0 },
35128 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), 0 } },
35129 +    & ifmt_move_1_d_indirect_with_index_1_s1_direct, { 0x300b900 }
35130 +  },
35131 +/* ext.1 ${d-imm7-1}(${d-An}),${s1-direct-addr} */
35132 +  {
35133 +    { 0, 0, 0, 0 },
35134 +    { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), 0 } },
35135 +    & ifmt_move_1_d_indirect_with_offset_1_s1_direct, { 0x400b900 }
35136 +  },
35137 +/* ext.1 (${d-An}),${s1-direct-addr} */
35138 +  {
35139 +    { 0, 0, 0, 0 },
35140 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), 0 } },
35141 +    & ifmt_move_1_d_indirect_1_s1_direct, { 0x400b900 }
35142 +  },
35143 +/* ext.1 (${d-An})${d-i4-1}++,${s1-direct-addr} */
35144 +  {
35145 +    { 0, 0, 0, 0 },
35146 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', OP (S1_DIRECT_ADDR), 0 } },
35147 +    & ifmt_move_1_d_indirect_with_post_increment_1_s1_direct, { 0x200b900 }
35148 +  },
35149 +/* ext.1 ${d-i4-1}(${d-An})++,${s1-direct-addr} */
35150 +  {
35151 +    { 0, 0, 0, 0 },
35152 +    { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), 0 } },
35153 +    & ifmt_move_1_d_indirect_with_pre_increment_1_s1_direct, { 0x210b900 }
35154 +  },
35155 +/* ext.1 ${d-direct-addr},#${s1-imm8} */
35156 +  {
35157 +    { 0, 0, 0, 0 },
35158 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), 0 } },
35159 +    & ifmt_movea_d_direct_s1_immediate, { 0x100b800 }
35160 +  },
35161 +/* ext.1 #${d-imm8},#${s1-imm8} */
35162 +  {
35163 +    { 0, 0, 0, 0 },
35164 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), 0 } },
35165 +    & ifmt_move_1_d_immediate_1_s1_immediate, { 0xb800 }
35166 +  },
35167 +/* ext.1 (${d-An},${d-r}),#${s1-imm8} */
35168 +  {
35169 +    { 0, 0, 0, 0 },
35170 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), 0 } },
35171 +    & ifmt_move_1_d_indirect_with_index_1_s1_immediate, { 0x300b800 }
35172 +  },
35173 +/* ext.1 ${d-imm7-1}(${d-An}),#${s1-imm8} */
35174 +  {
35175 +    { 0, 0, 0, 0 },
35176 +    { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } },
35177 +    & ifmt_move_1_d_indirect_with_offset_1_s1_immediate, { 0x400b800 }
35178 +  },
35179 +/* ext.1 (${d-An}),#${s1-imm8} */
35180 +  {
35181 +    { 0, 0, 0, 0 },
35182 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } },
35183 +    & ifmt_move_1_d_indirect_1_s1_immediate, { 0x400b800 }
35184 +  },
35185 +/* ext.1 (${d-An})${d-i4-1}++,#${s1-imm8} */
35186 +  {
35187 +    { 0, 0, 0, 0 },
35188 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', '#', OP (S1_IMM8), 0 } },
35189 +    & ifmt_move_1_d_indirect_with_post_increment_1_s1_immediate, { 0x200b800 }
35190 +  },
35191 +/* ext.1 ${d-i4-1}(${d-An})++,#${s1-imm8} */
35192 +  {
35193 +    { 0, 0, 0, 0 },
35194 +    { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), 0 } },
35195 +    & ifmt_move_1_d_indirect_with_pre_increment_1_s1_immediate, { 0x210b800 }
35196 +  },
35197 +/* ext.1 ${d-direct-addr},(${s1-An},${s1-r}) */
35198 +  {
35199 +    { 0, 0, 0, 0 },
35200 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
35201 +    & ifmt_move_1_d_direct_s1_indirect_with_index_1, { 0x100bb00 }
35202 +  },
35203 +/* ext.1 #${d-imm8},(${s1-An},${s1-r}) */
35204 +  {
35205 +    { 0, 0, 0, 0 },
35206 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
35207 +    & ifmt_move_1_d_immediate_1_s1_indirect_with_index_1, { 0xbb00 }
35208 +  },
35209 +/* ext.1 (${d-An},${d-r}),(${s1-An},${s1-r}) */
35210 +  {
35211 +    { 0, 0, 0, 0 },
35212 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
35213 +    & ifmt_move_1_d_indirect_with_index_1_s1_indirect_with_index_1, { 0x300bb00 }
35214 +  },
35215 +/* ext.1 ${d-imm7-1}(${d-An}),(${s1-An},${s1-r}) */
35216 +  {
35217 +    { 0, 0, 0, 0 },
35218 +    { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
35219 +    & ifmt_move_1_d_indirect_with_offset_1_s1_indirect_with_index_1, { 0x400bb00 }
35220 +  },
35221 +/* ext.1 (${d-An}),(${s1-An},${s1-r}) */
35222 +  {
35223 +    { 0, 0, 0, 0 },
35224 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
35225 +    & ifmt_move_1_d_indirect_1_s1_indirect_with_index_1, { 0x400bb00 }
35226 +  },
35227 +/* ext.1 (${d-An})${d-i4-1}++,(${s1-An},${s1-r}) */
35228 +  {
35229 +    { 0, 0, 0, 0 },
35230 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
35231 +    & ifmt_move_1_d_indirect_with_post_increment_1_s1_indirect_with_index_1, { 0x200bb00 }
35232 +  },
35233 +/* ext.1 ${d-i4-1}(${d-An})++,(${s1-An},${s1-r}) */
35234 +  {
35235 +    { 0, 0, 0, 0 },
35236 +    { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
35237 +    & ifmt_move_1_d_indirect_with_pre_increment_1_s1_indirect_with_index_1, { 0x210bb00 }
35238 +  },
35239 +/* ext.1 ${d-direct-addr},${s1-imm7-1}(${s1-An}) */
35240 +  {
35241 +    { 0, 0, 0, 0 },
35242 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', 0 } },
35243 +    & ifmt_move_1_d_direct_s1_indirect_with_offset_1, { 0x100bc00 }
35244 +  },
35245 +/* ext.1 #${d-imm8},${s1-imm7-1}(${s1-An}) */
35246 +  {
35247 +    { 0, 0, 0, 0 },
35248 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', 0 } },
35249 +    & ifmt_move_1_d_immediate_1_s1_indirect_with_offset_1, { 0xbc00 }
35250 +  },
35251 +/* ext.1 (${d-An},${d-r}),${s1-imm7-1}(${s1-An}) */
35252 +  {
35253 +    { 0, 0, 0, 0 },
35254 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', 0 } },
35255 +    & ifmt_move_1_d_indirect_with_index_1_s1_indirect_with_offset_1, { 0x300bc00 }
35256 +  },
35257 +/* ext.1 ${d-imm7-1}(${d-An}),${s1-imm7-1}(${s1-An}) */
35258 +  {
35259 +    { 0, 0, 0, 0 },
35260 +    { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', 0 } },
35261 +    & ifmt_move_1_d_indirect_with_offset_1_s1_indirect_with_offset_1, { 0x400bc00 }
35262 +  },
35263 +/* ext.1 (${d-An}),${s1-imm7-1}(${s1-An}) */
35264 +  {
35265 +    { 0, 0, 0, 0 },
35266 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', 0 } },
35267 +    & ifmt_move_1_d_indirect_1_s1_indirect_with_offset_1, { 0x400bc00 }
35268 +  },
35269 +/* ext.1 (${d-An})${d-i4-1}++,${s1-imm7-1}(${s1-An}) */
35270 +  {
35271 +    { 0, 0, 0, 0 },
35272 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', 0 } },
35273 +    & ifmt_move_1_d_indirect_with_post_increment_1_s1_indirect_with_offset_1, { 0x200bc00 }
35274 +  },
35275 +/* ext.1 ${d-i4-1}(${d-An})++,${s1-imm7-1}(${s1-An}) */
35276 +  {
35277 +    { 0, 0, 0, 0 },
35278 +    { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', 0 } },
35279 +    & ifmt_move_1_d_indirect_with_pre_increment_1_s1_indirect_with_offset_1, { 0x210bc00 }
35280 +  },
35281 +/* ext.1 ${d-direct-addr},(${s1-An}) */
35282 +  {
35283 +    { 0, 0, 0, 0 },
35284 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', 0 } },
35285 +    & ifmt_move_1_d_direct_s1_indirect_1, { 0x100bc00 }
35286 +  },
35287 +/* ext.1 #${d-imm8},(${s1-An}) */
35288 +  {
35289 +    { 0, 0, 0, 0 },
35290 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', 0 } },
35291 +    & ifmt_move_1_d_immediate_1_s1_indirect_1, { 0xbc00 }
35292 +  },
35293 +/* ext.1 (${d-An},${d-r}),(${s1-An}) */
35294 +  {
35295 +    { 0, 0, 0, 0 },
35296 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', 0 } },
35297 +    & ifmt_move_1_d_indirect_with_index_1_s1_indirect_1, { 0x300bc00 }
35298 +  },
35299 +/* ext.1 ${d-imm7-1}(${d-An}),(${s1-An}) */
35300 +  {
35301 +    { 0, 0, 0, 0 },
35302 +    { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } },
35303 +    & ifmt_move_1_d_indirect_with_offset_1_s1_indirect_1, { 0x400bc00 }
35304 +  },
35305 +/* ext.1 (${d-An}),(${s1-An}) */
35306 +  {
35307 +    { 0, 0, 0, 0 },
35308 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } },
35309 +    & ifmt_move_1_d_indirect_1_s1_indirect_1, { 0x400bc00 }
35310 +  },
35311 +/* ext.1 (${d-An})${d-i4-1}++,(${s1-An}) */
35312 +  {
35313 +    { 0, 0, 0, 0 },
35314 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', '(', OP (S1_AN), ')', 0 } },
35315 +    & ifmt_move_1_d_indirect_with_post_increment_1_s1_indirect_1, { 0x200bc00 }
35316 +  },
35317 +/* ext.1 ${d-i4-1}(${d-An})++,(${s1-An}) */
35318 +  {
35319 +    { 0, 0, 0, 0 },
35320 +    { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', 0 } },
35321 +    & ifmt_move_1_d_indirect_with_pre_increment_1_s1_indirect_1, { 0x210bc00 }
35322 +  },
35323 +/* ext.1 ${d-direct-addr},(${s1-An})${s1-i4-1}++ */
35324 +  {
35325 +    { 0, 0, 0, 0 },
35326 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', 0 } },
35327 +    & ifmt_move_1_d_direct_s1_indirect_with_post_increment_1, { 0x100ba00 }
35328 +  },
35329 +/* ext.1 #${d-imm8},(${s1-An})${s1-i4-1}++ */
35330 +  {
35331 +    { 0, 0, 0, 0 },
35332 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', 0 } },
35333 +    & ifmt_move_1_d_immediate_1_s1_indirect_with_post_increment_1, { 0xba00 }
35334 +  },
35335 +/* ext.1 (${d-An},${d-r}),(${s1-An})${s1-i4-1}++ */
35336 +  {
35337 +    { 0, 0, 0, 0 },
35338 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', 0 } },
35339 +    & ifmt_move_1_d_indirect_with_index_1_s1_indirect_with_post_increment_1, { 0x300ba00 }
35340 +  },
35341 +/* ext.1 ${d-imm7-1}(${d-An}),(${s1-An})${s1-i4-1}++ */
35342 +  {
35343 +    { 0, 0, 0, 0 },
35344 +    { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', 0 } },
35345 +    & ifmt_move_1_d_indirect_with_offset_1_s1_indirect_with_post_increment_1, { 0x400ba00 }
35346 +  },
35347 +/* ext.1 (${d-An}),(${s1-An})${s1-i4-1}++ */
35348 +  {
35349 +    { 0, 0, 0, 0 },
35350 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', 0 } },
35351 +    & ifmt_move_1_d_indirect_1_s1_indirect_with_post_increment_1, { 0x400ba00 }
35352 +  },
35353 +/* ext.1 (${d-An})${d-i4-1}++,(${s1-An})${s1-i4-1}++ */
35354 +  {
35355 +    { 0, 0, 0, 0 },
35356 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', 0 } },
35357 +    & ifmt_move_1_d_indirect_with_post_increment_1_s1_indirect_with_post_increment_1, { 0x200ba00 }
35358 +  },
35359 +/* ext.1 ${d-i4-1}(${d-An})++,(${s1-An})${s1-i4-1}++ */
35360 +  {
35361 +    { 0, 0, 0, 0 },
35362 +    { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', 0 } },
35363 +    & ifmt_move_1_d_indirect_with_pre_increment_1_s1_indirect_with_post_increment_1, { 0x210ba00 }
35364 +  },
35365 +/* ext.1 ${d-direct-addr},${s1-i4-1}(${s1-An})++ */
35366 +  {
35367 +    { 0, 0, 0, 0 },
35368 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', 0 } },
35369 +    & ifmt_move_1_d_direct_s1_indirect_with_pre_increment_1, { 0x100ba10 }
35370 +  },
35371 +/* ext.1 #${d-imm8},${s1-i4-1}(${s1-An})++ */
35372 +  {
35373 +    { 0, 0, 0, 0 },
35374 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', 0 } },
35375 +    & ifmt_move_1_d_immediate_1_s1_indirect_with_pre_increment_1, { 0xba10 }
35376 +  },
35377 +/* ext.1 (${d-An},${d-r}),${s1-i4-1}(${s1-An})++ */
35378 +  {
35379 +    { 0, 0, 0, 0 },
35380 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', 0 } },
35381 +    & ifmt_move_1_d_indirect_with_index_1_s1_indirect_with_pre_increment_1, { 0x300ba10 }
35382 +  },
35383 +/* ext.1 ${d-imm7-1}(${d-An}),${s1-i4-1}(${s1-An})++ */
35384 +  {
35385 +    { 0, 0, 0, 0 },
35386 +    { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', 0 } },
35387 +    & ifmt_move_1_d_indirect_with_offset_1_s1_indirect_with_pre_increment_1, { 0x400ba10 }
35388 +  },
35389 +/* ext.1 (${d-An}),${s1-i4-1}(${s1-An})++ */
35390 +  {
35391 +    { 0, 0, 0, 0 },
35392 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', 0 } },
35393 +    & ifmt_move_1_d_indirect_1_s1_indirect_with_pre_increment_1, { 0x400ba10 }
35394 +  },
35395 +/* ext.1 (${d-An})${d-i4-1}++,${s1-i4-1}(${s1-An})++ */
35396 +  {
35397 +    { 0, 0, 0, 0 },
35398 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', 0 } },
35399 +    & ifmt_move_1_d_indirect_with_post_increment_1_s1_indirect_with_pre_increment_1, { 0x200ba10 }
35400 +  },
35401 +/* ext.1 ${d-i4-1}(${d-An})++,${s1-i4-1}(${s1-An})++ */
35402 +  {
35403 +    { 0, 0, 0, 0 },
35404 +    { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', 0 } },
35405 +    & ifmt_move_1_d_indirect_with_pre_increment_1_s1_indirect_with_pre_increment_1, { 0x210ba10 }
35406 +  },
35407 +/* movei ${d-direct-addr},#${imm16-2} */
35408 +  {
35409 +    { 0, 0, 0, 0 },
35410 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (IMM16_2), 0 } },
35411 +    & ifmt_movei_d_direct, { 0xc9000000 }
35412 +  },
35413 +/* movei #${d-imm8},#${imm16-2} */
35414 +  {
35415 +    { 0, 0, 0, 0 },
35416 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (IMM16_2), 0 } },
35417 +    & ifmt_movei_d_immediate_2, { 0xc8000000 }
35418 +  },
35419 +/* movei (${d-An},${d-r}),#${imm16-2} */
35420 +  {
35421 +    { 0, 0, 0, 0 },
35422 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (IMM16_2), 0 } },
35423 +    & ifmt_movei_d_indirect_with_index_2, { 0xcb000000 }
35424 +  },
35425 +/* movei ${d-imm7-2}(${d-An}),#${imm16-2} */
35426 +  {
35427 +    { 0, 0, 0, 0 },
35428 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '#', OP (IMM16_2), 0 } },
35429 +    & ifmt_movei_d_indirect_with_offset_2, { 0xcc000000 }
35430 +  },
35431 +/* movei (${d-An}),#${imm16-2} */
35432 +  {
35433 +    { 0, 0, 0, 0 },
35434 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (IMM16_2), 0 } },
35435 +    & ifmt_movei_d_indirect_2, { 0xcc000000 }
35436 +  },
35437 +/* movei (${d-An})${d-i4-2}++,#${imm16-2} */
35438 +  {
35439 +    { 0, 0, 0, 0 },
35440 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '#', OP (IMM16_2), 0 } },
35441 +    & ifmt_movei_d_indirect_with_post_increment_2, { 0xca000000 }
35442 +  },
35443 +/* movei ${d-i4-2}(${d-An})++,#${imm16-2} */
35444 +  {
35445 +    { 0, 0, 0, 0 },
35446 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (IMM16_2), 0 } },
35447 +    & ifmt_movei_d_indirect_with_pre_increment_2, { 0xca100000 }
35448 +  },
35449 +/* bclr ${d-direct-addr},${s1-direct-addr},#${bit5} */
35450 +  {
35451 +    { 0, 0, 0, 0 },
35452 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } },
35453 +    & ifmt_bclr_d_direct_s1_direct, { 0x29000100 }
35454 +  },
35455 +/* bclr #${d-imm8},${s1-direct-addr},#${bit5} */
35456 +  {
35457 +    { 0, 0, 0, 0 },
35458 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } },
35459 +    & ifmt_bclr_d_immediate_4_s1_direct, { 0x28000100 }
35460 +  },
35461 +/* bclr (${d-An},${d-r}),${s1-direct-addr},#${bit5} */
35462 +  {
35463 +    { 0, 0, 0, 0 },
35464 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } },
35465 +    & ifmt_bclr_d_indirect_with_index_4_s1_direct, { 0x2b000100 }
35466 +  },
35467 +/* bclr ${d-imm7-4}(${d-An}),${s1-direct-addr},#${bit5} */
35468 +  {
35469 +    { 0, 0, 0, 0 },
35470 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } },
35471 +    & ifmt_bclr_d_indirect_with_offset_4_s1_direct, { 0x2c000100 }
35472 +  },
35473 +/* bclr (${d-An}),${s1-direct-addr},#${bit5} */
35474 +  {
35475 +    { 0, 0, 0, 0 },
35476 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } },
35477 +    & ifmt_bclr_d_indirect_4_s1_direct, { 0x2c000100 }
35478 +  },
35479 +/* bclr (${d-An})${d-i4-4}++,${s1-direct-addr},#${bit5} */
35480 +  {
35481 +    { 0, 0, 0, 0 },
35482 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } },
35483 +    & ifmt_bclr_d_indirect_with_post_increment_4_s1_direct, { 0x2a000100 }
35484 +  },
35485 +/* bclr ${d-i4-4}(${d-An})++,${s1-direct-addr},#${bit5} */
35486 +  {
35487 +    { 0, 0, 0, 0 },
35488 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } },
35489 +    & ifmt_bclr_d_indirect_with_pre_increment_4_s1_direct, { 0x2a100100 }
35490 +  },
35491 +/* bclr ${d-direct-addr},#${s1-imm8},#${bit5} */
35492 +  {
35493 +    { 0, 0, 0, 0 },
35494 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } },
35495 +    & ifmt_bclr_d_direct_s1_immediate, { 0x29000000 }
35496 +  },
35497 +/* bclr #${d-imm8},#${s1-imm8},#${bit5} */
35498 +  {
35499 +    { 0, 0, 0, 0 },
35500 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } },
35501 +    & ifmt_bclr_d_immediate_4_s1_immediate, { 0x28000000 }
35502 +  },
35503 +/* bclr (${d-An},${d-r}),#${s1-imm8},#${bit5} */
35504 +  {
35505 +    { 0, 0, 0, 0 },
35506 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } },
35507 +    & ifmt_bclr_d_indirect_with_index_4_s1_immediate, { 0x2b000000 }
35508 +  },
35509 +/* bclr ${d-imm7-4}(${d-An}),#${s1-imm8},#${bit5} */
35510 +  {
35511 +    { 0, 0, 0, 0 },
35512 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } },
35513 +    & ifmt_bclr_d_indirect_with_offset_4_s1_immediate, { 0x2c000000 }
35514 +  },
35515 +/* bclr (${d-An}),#${s1-imm8},#${bit5} */
35516 +  {
35517 +    { 0, 0, 0, 0 },
35518 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } },
35519 +    & ifmt_bclr_d_indirect_4_s1_immediate, { 0x2c000000 }
35520 +  },
35521 +/* bclr (${d-An})${d-i4-4}++,#${s1-imm8},#${bit5} */
35522 +  {
35523 +    { 0, 0, 0, 0 },
35524 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } },
35525 +    & ifmt_bclr_d_indirect_with_post_increment_4_s1_immediate, { 0x2a000000 }
35526 +  },
35527 +/* bclr ${d-i4-4}(${d-An})++,#${s1-imm8},#${bit5} */
35528 +  {
35529 +    { 0, 0, 0, 0 },
35530 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } },
35531 +    & ifmt_bclr_d_indirect_with_pre_increment_4_s1_immediate, { 0x2a100000 }
35532 +  },
35533 +/* bclr ${d-direct-addr},(${s1-An},${s1-r}),#${bit5} */
35534 +  {
35535 +    { 0, 0, 0, 0 },
35536 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } },
35537 +    & ifmt_bclr_d_direct_s1_indirect_with_index_4, { 0x29000300 }
35538 +  },
35539 +/* bclr #${d-imm8},(${s1-An},${s1-r}),#${bit5} */
35540 +  {
35541 +    { 0, 0, 0, 0 },
35542 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } },
35543 +    & ifmt_bclr_d_immediate_4_s1_indirect_with_index_4, { 0x28000300 }
35544 +  },
35545 +/* bclr (${d-An},${d-r}),(${s1-An},${s1-r}),#${bit5} */
35546 +  {
35547 +    { 0, 0, 0, 0 },
35548 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } },
35549 +    & ifmt_bclr_d_indirect_with_index_4_s1_indirect_with_index_4, { 0x2b000300 }
35550 +  },
35551 +/* bclr ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}),#${bit5} */
35552 +  {
35553 +    { 0, 0, 0, 0 },
35554 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } },
35555 +    & ifmt_bclr_d_indirect_with_offset_4_s1_indirect_with_index_4, { 0x2c000300 }
35556 +  },
35557 +/* bclr (${d-An}),(${s1-An},${s1-r}),#${bit5} */
35558 +  {
35559 +    { 0, 0, 0, 0 },
35560 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } },
35561 +    & ifmt_bclr_d_indirect_4_s1_indirect_with_index_4, { 0x2c000300 }
35562 +  },
35563 +/* bclr (${d-An})${d-i4-4}++,(${s1-An},${s1-r}),#${bit5} */
35564 +  {
35565 +    { 0, 0, 0, 0 },
35566 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } },
35567 +    & ifmt_bclr_d_indirect_with_post_increment_4_s1_indirect_with_index_4, { 0x2a000300 }
35568 +  },
35569 +/* bclr ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}),#${bit5} */
35570 +  {
35571 +    { 0, 0, 0, 0 },
35572 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } },
35573 +    & ifmt_bclr_d_indirect_with_pre_increment_4_s1_indirect_with_index_4, { 0x2a100300 }
35574 +  },
35575 +/* bclr ${d-direct-addr},${s1-imm7-4}(${s1-An}),#${bit5} */
35576 +  {
35577 +    { 0, 0, 0, 0 },
35578 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
35579 +    & ifmt_bclr_d_direct_s1_indirect_with_offset_4, { 0x29000400 }
35580 +  },
35581 +/* bclr #${d-imm8},${s1-imm7-4}(${s1-An}),#${bit5} */
35582 +  {
35583 +    { 0, 0, 0, 0 },
35584 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
35585 +    & ifmt_bclr_d_immediate_4_s1_indirect_with_offset_4, { 0x28000400 }
35586 +  },
35587 +/* bclr (${d-An},${d-r}),${s1-imm7-4}(${s1-An}),#${bit5} */
35588 +  {
35589 +    { 0, 0, 0, 0 },
35590 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
35591 +    & ifmt_bclr_d_indirect_with_index_4_s1_indirect_with_offset_4, { 0x2b000400 }
35592 +  },
35593 +/* bclr ${d-imm7-4}(${d-An}),${s1-imm7-4}(${s1-An}),#${bit5} */
35594 +  {
35595 +    { 0, 0, 0, 0 },
35596 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
35597 +    & ifmt_bclr_d_indirect_with_offset_4_s1_indirect_with_offset_4, { 0x2c000400 }
35598 +  },
35599 +/* bclr (${d-An}),${s1-imm7-4}(${s1-An}),#${bit5} */
35600 +  {
35601 +    { 0, 0, 0, 0 },
35602 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
35603 +    & ifmt_bclr_d_indirect_4_s1_indirect_with_offset_4, { 0x2c000400 }
35604 +  },
35605 +/* bclr (${d-An})${d-i4-4}++,${s1-imm7-4}(${s1-An}),#${bit5} */
35606 +  {
35607 +    { 0, 0, 0, 0 },
35608 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
35609 +    & ifmt_bclr_d_indirect_with_post_increment_4_s1_indirect_with_offset_4, { 0x2a000400 }
35610 +  },
35611 +/* bclr ${d-i4-4}(${d-An})++,${s1-imm7-4}(${s1-An}),#${bit5} */
35612 +  {
35613 +    { 0, 0, 0, 0 },
35614 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
35615 +    & ifmt_bclr_d_indirect_with_pre_increment_4_s1_indirect_with_offset_4, { 0x2a100400 }
35616 +  },
35617 +/* bclr ${d-direct-addr},(${s1-An}),#${bit5} */
35618 +  {
35619 +    { 0, 0, 0, 0 },
35620 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
35621 +    & ifmt_bclr_d_direct_s1_indirect_4, { 0x29000400 }
35622 +  },
35623 +/* bclr #${d-imm8},(${s1-An}),#${bit5} */
35624 +  {
35625 +    { 0, 0, 0, 0 },
35626 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
35627 +    & ifmt_bclr_d_immediate_4_s1_indirect_4, { 0x28000400 }
35628 +  },
35629 +/* bclr (${d-An},${d-r}),(${s1-An}),#${bit5} */
35630 +  {
35631 +    { 0, 0, 0, 0 },
35632 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
35633 +    & ifmt_bclr_d_indirect_with_index_4_s1_indirect_4, { 0x2b000400 }
35634 +  },
35635 +/* bclr ${d-imm7-4}(${d-An}),(${s1-An}),#${bit5} */
35636 +  {
35637 +    { 0, 0, 0, 0 },
35638 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
35639 +    & ifmt_bclr_d_indirect_with_offset_4_s1_indirect_4, { 0x2c000400 }
35640 +  },
35641 +/* bclr (${d-An}),(${s1-An}),#${bit5} */
35642 +  {
35643 +    { 0, 0, 0, 0 },
35644 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
35645 +    & ifmt_bclr_d_indirect_4_s1_indirect_4, { 0x2c000400 }
35646 +  },
35647 +/* bclr (${d-An})${d-i4-4}++,(${s1-An}),#${bit5} */
35648 +  {
35649 +    { 0, 0, 0, 0 },
35650 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
35651 +    & ifmt_bclr_d_indirect_with_post_increment_4_s1_indirect_4, { 0x2a000400 }
35652 +  },
35653 +/* bclr ${d-i4-4}(${d-An})++,(${s1-An}),#${bit5} */
35654 +  {
35655 +    { 0, 0, 0, 0 },
35656 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
35657 +    & ifmt_bclr_d_indirect_with_pre_increment_4_s1_indirect_4, { 0x2a100400 }
35658 +  },
35659 +/* bclr ${d-direct-addr},(${s1-An})${s1-i4-4}++,#${bit5} */
35660 +  {
35661 +    { 0, 0, 0, 0 },
35662 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', '#', OP (BIT5), 0 } },
35663 +    & ifmt_bclr_d_direct_s1_indirect_with_post_increment_4, { 0x29000200 }
35664 +  },
35665 +/* bclr #${d-imm8},(${s1-An})${s1-i4-4}++,#${bit5} */
35666 +  {
35667 +    { 0, 0, 0, 0 },
35668 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', '#', OP (BIT5), 0 } },
35669 +    & ifmt_bclr_d_immediate_4_s1_indirect_with_post_increment_4, { 0x28000200 }
35670 +  },
35671 +/* bclr (${d-An},${d-r}),(${s1-An})${s1-i4-4}++,#${bit5} */
35672 +  {
35673 +    { 0, 0, 0, 0 },
35674 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', '#', OP (BIT5), 0 } },
35675 +    & ifmt_bclr_d_indirect_with_index_4_s1_indirect_with_post_increment_4, { 0x2b000200 }
35676 +  },
35677 +/* bclr ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-4}++,#${bit5} */
35678 +  {
35679 +    { 0, 0, 0, 0 },
35680 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', '#', OP (BIT5), 0 } },
35681 +    & ifmt_bclr_d_indirect_with_offset_4_s1_indirect_with_post_increment_4, { 0x2c000200 }
35682 +  },
35683 +/* bclr (${d-An}),(${s1-An})${s1-i4-4}++,#${bit5} */
35684 +  {
35685 +    { 0, 0, 0, 0 },
35686 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', '#', OP (BIT5), 0 } },
35687 +    & ifmt_bclr_d_indirect_4_s1_indirect_with_post_increment_4, { 0x2c000200 }
35688 +  },
35689 +/* bclr (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-4}++,#${bit5} */
35690 +  {
35691 +    { 0, 0, 0, 0 },
35692 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', '#', OP (BIT5), 0 } },
35693 +    & ifmt_bclr_d_indirect_with_post_increment_4_s1_indirect_with_post_increment_4, { 0x2a000200 }
35694 +  },
35695 +/* bclr ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-4}++,#${bit5} */
35696 +  {
35697 +    { 0, 0, 0, 0 },
35698 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', '#', OP (BIT5), 0 } },
35699 +    & ifmt_bclr_d_indirect_with_pre_increment_4_s1_indirect_with_post_increment_4, { 0x2a100200 }
35700 +  },
35701 +/* bclr ${d-direct-addr},${s1-i4-4}(${s1-An})++,#${bit5} */
35702 +  {
35703 +    { 0, 0, 0, 0 },
35704 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } },
35705 +    & ifmt_bclr_d_direct_s1_indirect_with_pre_increment_4, { 0x29000210 }
35706 +  },
35707 +/* bclr #${d-imm8},${s1-i4-4}(${s1-An})++,#${bit5} */
35708 +  {
35709 +    { 0, 0, 0, 0 },
35710 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } },
35711 +    & ifmt_bclr_d_immediate_4_s1_indirect_with_pre_increment_4, { 0x28000210 }
35712 +  },
35713 +/* bclr (${d-An},${d-r}),${s1-i4-4}(${s1-An})++,#${bit5} */
35714 +  {
35715 +    { 0, 0, 0, 0 },
35716 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } },
35717 +    & ifmt_bclr_d_indirect_with_index_4_s1_indirect_with_pre_increment_4, { 0x2b000210 }
35718 +  },
35719 +/* bclr ${d-imm7-4}(${d-An}),${s1-i4-4}(${s1-An})++,#${bit5} */
35720 +  {
35721 +    { 0, 0, 0, 0 },
35722 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } },
35723 +    & ifmt_bclr_d_indirect_with_offset_4_s1_indirect_with_pre_increment_4, { 0x2c000210 }
35724 +  },
35725 +/* bclr (${d-An}),${s1-i4-4}(${s1-An})++,#${bit5} */
35726 +  {
35727 +    { 0, 0, 0, 0 },
35728 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } },
35729 +    & ifmt_bclr_d_indirect_4_s1_indirect_with_pre_increment_4, { 0x2c000210 }
35730 +  },
35731 +/* bclr (${d-An})${d-i4-4}++,${s1-i4-4}(${s1-An})++,#${bit5} */
35732 +  {
35733 +    { 0, 0, 0, 0 },
35734 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } },
35735 +    & ifmt_bclr_d_indirect_with_post_increment_4_s1_indirect_with_pre_increment_4, { 0x2a000210 }
35736 +  },
35737 +/* bclr ${d-i4-4}(${d-An})++,${s1-i4-4}(${s1-An})++,#${bit5} */
35738 +  {
35739 +    { 0, 0, 0, 0 },
35740 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } },
35741 +    & ifmt_bclr_d_indirect_with_pre_increment_4_s1_indirect_with_pre_increment_4, { 0x2a100210 }
35742 +  },
35743 +/* bset ${d-direct-addr},${s1-direct-addr},#${bit5} */
35744 +  {
35745 +    { 0, 0, 0, 0 },
35746 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } },
35747 +    & ifmt_bclr_d_direct_s1_direct, { 0x21000100 }
35748 +  },
35749 +/* bset #${d-imm8},${s1-direct-addr},#${bit5} */
35750 +  {
35751 +    { 0, 0, 0, 0 },
35752 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } },
35753 +    & ifmt_bclr_d_immediate_4_s1_direct, { 0x20000100 }
35754 +  },
35755 +/* bset (${d-An},${d-r}),${s1-direct-addr},#${bit5} */
35756 +  {
35757 +    { 0, 0, 0, 0 },
35758 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } },
35759 +    & ifmt_bclr_d_indirect_with_index_4_s1_direct, { 0x23000100 }
35760 +  },
35761 +/* bset ${d-imm7-4}(${d-An}),${s1-direct-addr},#${bit5} */
35762 +  {
35763 +    { 0, 0, 0, 0 },
35764 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } },
35765 +    & ifmt_bclr_d_indirect_with_offset_4_s1_direct, { 0x24000100 }
35766 +  },
35767 +/* bset (${d-An}),${s1-direct-addr},#${bit5} */
35768 +  {
35769 +    { 0, 0, 0, 0 },
35770 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } },
35771 +    & ifmt_bclr_d_indirect_4_s1_direct, { 0x24000100 }
35772 +  },
35773 +/* bset (${d-An})${d-i4-4}++,${s1-direct-addr},#${bit5} */
35774 +  {
35775 +    { 0, 0, 0, 0 },
35776 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } },
35777 +    & ifmt_bclr_d_indirect_with_post_increment_4_s1_direct, { 0x22000100 }
35778 +  },
35779 +/* bset ${d-i4-4}(${d-An})++,${s1-direct-addr},#${bit5} */
35780 +  {
35781 +    { 0, 0, 0, 0 },
35782 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } },
35783 +    & ifmt_bclr_d_indirect_with_pre_increment_4_s1_direct, { 0x22100100 }
35784 +  },
35785 +/* bset ${d-direct-addr},#${s1-imm8},#${bit5} */
35786 +  {
35787 +    { 0, 0, 0, 0 },
35788 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } },
35789 +    & ifmt_bclr_d_direct_s1_immediate, { 0x21000000 }
35790 +  },
35791 +/* bset #${d-imm8},#${s1-imm8},#${bit5} */
35792 +  {
35793 +    { 0, 0, 0, 0 },
35794 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } },
35795 +    & ifmt_bclr_d_immediate_4_s1_immediate, { 0x20000000 }
35796 +  },
35797 +/* bset (${d-An},${d-r}),#${s1-imm8},#${bit5} */
35798 +  {
35799 +    { 0, 0, 0, 0 },
35800 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } },
35801 +    & ifmt_bclr_d_indirect_with_index_4_s1_immediate, { 0x23000000 }
35802 +  },
35803 +/* bset ${d-imm7-4}(${d-An}),#${s1-imm8},#${bit5} */
35804 +  {
35805 +    { 0, 0, 0, 0 },
35806 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } },
35807 +    & ifmt_bclr_d_indirect_with_offset_4_s1_immediate, { 0x24000000 }
35808 +  },
35809 +/* bset (${d-An}),#${s1-imm8},#${bit5} */
35810 +  {
35811 +    { 0, 0, 0, 0 },
35812 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } },
35813 +    & ifmt_bclr_d_indirect_4_s1_immediate, { 0x24000000 }
35814 +  },
35815 +/* bset (${d-An})${d-i4-4}++,#${s1-imm8},#${bit5} */
35816 +  {
35817 +    { 0, 0, 0, 0 },
35818 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } },
35819 +    & ifmt_bclr_d_indirect_with_post_increment_4_s1_immediate, { 0x22000000 }
35820 +  },
35821 +/* bset ${d-i4-4}(${d-An})++,#${s1-imm8},#${bit5} */
35822 +  {
35823 +    { 0, 0, 0, 0 },
35824 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } },
35825 +    & ifmt_bclr_d_indirect_with_pre_increment_4_s1_immediate, { 0x22100000 }
35826 +  },
35827 +/* bset ${d-direct-addr},(${s1-An},${s1-r}),#${bit5} */
35828 +  {
35829 +    { 0, 0, 0, 0 },
35830 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } },
35831 +    & ifmt_bclr_d_direct_s1_indirect_with_index_4, { 0x21000300 }
35832 +  },
35833 +/* bset #${d-imm8},(${s1-An},${s1-r}),#${bit5} */
35834 +  {
35835 +    { 0, 0, 0, 0 },
35836 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } },
35837 +    & ifmt_bclr_d_immediate_4_s1_indirect_with_index_4, { 0x20000300 }
35838 +  },
35839 +/* bset (${d-An},${d-r}),(${s1-An},${s1-r}),#${bit5} */
35840 +  {
35841 +    { 0, 0, 0, 0 },
35842 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } },
35843 +    & ifmt_bclr_d_indirect_with_index_4_s1_indirect_with_index_4, { 0x23000300 }
35844 +  },
35845 +/* bset ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}),#${bit5} */
35846 +  {
35847 +    { 0, 0, 0, 0 },
35848 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } },
35849 +    & ifmt_bclr_d_indirect_with_offset_4_s1_indirect_with_index_4, { 0x24000300 }
35850 +  },
35851 +/* bset (${d-An}),(${s1-An},${s1-r}),#${bit5} */
35852 +  {
35853 +    { 0, 0, 0, 0 },
35854 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } },
35855 +    & ifmt_bclr_d_indirect_4_s1_indirect_with_index_4, { 0x24000300 }
35856 +  },
35857 +/* bset (${d-An})${d-i4-4}++,(${s1-An},${s1-r}),#${bit5} */
35858 +  {
35859 +    { 0, 0, 0, 0 },
35860 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } },
35861 +    & ifmt_bclr_d_indirect_with_post_increment_4_s1_indirect_with_index_4, { 0x22000300 }
35862 +  },
35863 +/* bset ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}),#${bit5} */
35864 +  {
35865 +    { 0, 0, 0, 0 },
35866 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } },
35867 +    & ifmt_bclr_d_indirect_with_pre_increment_4_s1_indirect_with_index_4, { 0x22100300 }
35868 +  },
35869 +/* bset ${d-direct-addr},${s1-imm7-4}(${s1-An}),#${bit5} */
35870 +  {
35871 +    { 0, 0, 0, 0 },
35872 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
35873 +    & ifmt_bclr_d_direct_s1_indirect_with_offset_4, { 0x21000400 }
35874 +  },
35875 +/* bset #${d-imm8},${s1-imm7-4}(${s1-An}),#${bit5} */
35876 +  {
35877 +    { 0, 0, 0, 0 },
35878 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
35879 +    & ifmt_bclr_d_immediate_4_s1_indirect_with_offset_4, { 0x20000400 }
35880 +  },
35881 +/* bset (${d-An},${d-r}),${s1-imm7-4}(${s1-An}),#${bit5} */
35882 +  {
35883 +    { 0, 0, 0, 0 },
35884 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
35885 +    & ifmt_bclr_d_indirect_with_index_4_s1_indirect_with_offset_4, { 0x23000400 }
35886 +  },
35887 +/* bset ${d-imm7-4}(${d-An}),${s1-imm7-4}(${s1-An}),#${bit5} */
35888 +  {
35889 +    { 0, 0, 0, 0 },
35890 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
35891 +    & ifmt_bclr_d_indirect_with_offset_4_s1_indirect_with_offset_4, { 0x24000400 }
35892 +  },
35893 +/* bset (${d-An}),${s1-imm7-4}(${s1-An}),#${bit5} */
35894 +  {
35895 +    { 0, 0, 0, 0 },
35896 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
35897 +    & ifmt_bclr_d_indirect_4_s1_indirect_with_offset_4, { 0x24000400 }
35898 +  },
35899 +/* bset (${d-An})${d-i4-4}++,${s1-imm7-4}(${s1-An}),#${bit5} */
35900 +  {
35901 +    { 0, 0, 0, 0 },
35902 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
35903 +    & ifmt_bclr_d_indirect_with_post_increment_4_s1_indirect_with_offset_4, { 0x22000400 }
35904 +  },
35905 +/* bset ${d-i4-4}(${d-An})++,${s1-imm7-4}(${s1-An}),#${bit5} */
35906 +  {
35907 +    { 0, 0, 0, 0 },
35908 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
35909 +    & ifmt_bclr_d_indirect_with_pre_increment_4_s1_indirect_with_offset_4, { 0x22100400 }
35910 +  },
35911 +/* bset ${d-direct-addr},(${s1-An}),#${bit5} */
35912 +  {
35913 +    { 0, 0, 0, 0 },
35914 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
35915 +    & ifmt_bclr_d_direct_s1_indirect_4, { 0x21000400 }
35916 +  },
35917 +/* bset #${d-imm8},(${s1-An}),#${bit5} */
35918 +  {
35919 +    { 0, 0, 0, 0 },
35920 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
35921 +    & ifmt_bclr_d_immediate_4_s1_indirect_4, { 0x20000400 }
35922 +  },
35923 +/* bset (${d-An},${d-r}),(${s1-An}),#${bit5} */
35924 +  {
35925 +    { 0, 0, 0, 0 },
35926 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
35927 +    & ifmt_bclr_d_indirect_with_index_4_s1_indirect_4, { 0x23000400 }
35928 +  },
35929 +/* bset ${d-imm7-4}(${d-An}),(${s1-An}),#${bit5} */
35930 +  {
35931 +    { 0, 0, 0, 0 },
35932 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
35933 +    & ifmt_bclr_d_indirect_with_offset_4_s1_indirect_4, { 0x24000400 }
35934 +  },
35935 +/* bset (${d-An}),(${s1-An}),#${bit5} */
35936 +  {
35937 +    { 0, 0, 0, 0 },
35938 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
35939 +    & ifmt_bclr_d_indirect_4_s1_indirect_4, { 0x24000400 }
35940 +  },
35941 +/* bset (${d-An})${d-i4-4}++,(${s1-An}),#${bit5} */
35942 +  {
35943 +    { 0, 0, 0, 0 },
35944 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
35945 +    & ifmt_bclr_d_indirect_with_post_increment_4_s1_indirect_4, { 0x22000400 }
35946 +  },
35947 +/* bset ${d-i4-4}(${d-An})++,(${s1-An}),#${bit5} */
35948 +  {
35949 +    { 0, 0, 0, 0 },
35950 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
35951 +    & ifmt_bclr_d_indirect_with_pre_increment_4_s1_indirect_4, { 0x22100400 }
35952 +  },
35953 +/* bset ${d-direct-addr},(${s1-An})${s1-i4-4}++,#${bit5} */
35954 +  {
35955 +    { 0, 0, 0, 0 },
35956 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', '#', OP (BIT5), 0 } },
35957 +    & ifmt_bclr_d_direct_s1_indirect_with_post_increment_4, { 0x21000200 }
35958 +  },
35959 +/* bset #${d-imm8},(${s1-An})${s1-i4-4}++,#${bit5} */
35960 +  {
35961 +    { 0, 0, 0, 0 },
35962 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', '#', OP (BIT5), 0 } },
35963 +    & ifmt_bclr_d_immediate_4_s1_indirect_with_post_increment_4, { 0x20000200 }
35964 +  },
35965 +/* bset (${d-An},${d-r}),(${s1-An})${s1-i4-4}++,#${bit5} */
35966 +  {
35967 +    { 0, 0, 0, 0 },
35968 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', '#', OP (BIT5), 0 } },
35969 +    & ifmt_bclr_d_indirect_with_index_4_s1_indirect_with_post_increment_4, { 0x23000200 }
35970 +  },
35971 +/* bset ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-4}++,#${bit5} */
35972 +  {
35973 +    { 0, 0, 0, 0 },
35974 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', '#', OP (BIT5), 0 } },
35975 +    & ifmt_bclr_d_indirect_with_offset_4_s1_indirect_with_post_increment_4, { 0x24000200 }
35976 +  },
35977 +/* bset (${d-An}),(${s1-An})${s1-i4-4}++,#${bit5} */
35978 +  {
35979 +    { 0, 0, 0, 0 },
35980 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', '#', OP (BIT5), 0 } },
35981 +    & ifmt_bclr_d_indirect_4_s1_indirect_with_post_increment_4, { 0x24000200 }
35982 +  },
35983 +/* bset (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-4}++,#${bit5} */
35984 +  {
35985 +    { 0, 0, 0, 0 },
35986 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', '#', OP (BIT5), 0 } },
35987 +    & ifmt_bclr_d_indirect_with_post_increment_4_s1_indirect_with_post_increment_4, { 0x22000200 }
35988 +  },
35989 +/* bset ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-4}++,#${bit5} */
35990 +  {
35991 +    { 0, 0, 0, 0 },
35992 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', '#', OP (BIT5), 0 } },
35993 +    & ifmt_bclr_d_indirect_with_pre_increment_4_s1_indirect_with_post_increment_4, { 0x22100200 }
35994 +  },
35995 +/* bset ${d-direct-addr},${s1-i4-4}(${s1-An})++,#${bit5} */
35996 +  {
35997 +    { 0, 0, 0, 0 },
35998 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } },
35999 +    & ifmt_bclr_d_direct_s1_indirect_with_pre_increment_4, { 0x21000210 }
36000 +  },
36001 +/* bset #${d-imm8},${s1-i4-4}(${s1-An})++,#${bit5} */
36002 +  {
36003 +    { 0, 0, 0, 0 },
36004 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } },
36005 +    & ifmt_bclr_d_immediate_4_s1_indirect_with_pre_increment_4, { 0x20000210 }
36006 +  },
36007 +/* bset (${d-An},${d-r}),${s1-i4-4}(${s1-An})++,#${bit5} */
36008 +  {
36009 +    { 0, 0, 0, 0 },
36010 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } },
36011 +    & ifmt_bclr_d_indirect_with_index_4_s1_indirect_with_pre_increment_4, { 0x23000210 }
36012 +  },
36013 +/* bset ${d-imm7-4}(${d-An}),${s1-i4-4}(${s1-An})++,#${bit5} */
36014 +  {
36015 +    { 0, 0, 0, 0 },
36016 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } },
36017 +    & ifmt_bclr_d_indirect_with_offset_4_s1_indirect_with_pre_increment_4, { 0x24000210 }
36018 +  },
36019 +/* bset (${d-An}),${s1-i4-4}(${s1-An})++,#${bit5} */
36020 +  {
36021 +    { 0, 0, 0, 0 },
36022 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } },
36023 +    & ifmt_bclr_d_indirect_4_s1_indirect_with_pre_increment_4, { 0x24000210 }
36024 +  },
36025 +/* bset (${d-An})${d-i4-4}++,${s1-i4-4}(${s1-An})++,#${bit5} */
36026 +  {
36027 +    { 0, 0, 0, 0 },
36028 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } },
36029 +    & ifmt_bclr_d_indirect_with_post_increment_4_s1_indirect_with_pre_increment_4, { 0x22000210 }
36030 +  },
36031 +/* bset ${d-i4-4}(${d-An})++,${s1-i4-4}(${s1-An})++,#${bit5} */
36032 +  {
36033 +    { 0, 0, 0, 0 },
36034 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } },
36035 +    & ifmt_bclr_d_indirect_with_pre_increment_4_s1_indirect_with_pre_increment_4, { 0x22100210 }
36036 +  },
36037 +/* btst ${s1-direct-addr},#${bit5} */
36038 +  {
36039 +    { 0, 0, 0, 0 },
36040 +    { { MNEM, ' ', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } },
36041 +    & ifmt_btst_s1_direct_imm_bit5, { 0x10c00100 }
36042 +  },
36043 +/* btst #${s1-imm8},#${bit5} */
36044 +  {
36045 +    { 0, 0, 0, 0 },
36046 +    { { MNEM, ' ', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } },
36047 +    & ifmt_btst_s1_immediate_imm_bit5, { 0x10c00000 }
36048 +  },
36049 +/* btst (${s1-An},${s1-r}),#${bit5} */
36050 +  {
36051 +    { 0, 0, 0, 0 },
36052 +    { { MNEM, ' ', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } },
36053 +    & ifmt_btst_s1_indirect_with_index_4_imm_bit5, { 0x10c00300 }
36054 +  },
36055 +/* btst ${s1-imm7-4}(${s1-An}),#${bit5} */
36056 +  {
36057 +    { 0, 0, 0, 0 },
36058 +    { { MNEM, ' ', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
36059 +    & ifmt_btst_s1_indirect_with_offset_4_imm_bit5, { 0x10c00400 }
36060 +  },
36061 +/* btst (${s1-An}),#${bit5} */
36062 +  {
36063 +    { 0, 0, 0, 0 },
36064 +    { { MNEM, ' ', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
36065 +    & ifmt_btst_s1_indirect_4_imm_bit5, { 0x10c00400 }
36066 +  },
36067 +/* btst (${s1-An})${s1-i4-4}++,#${bit5} */
36068 +  {
36069 +    { 0, 0, 0, 0 },
36070 +    { { MNEM, ' ', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', '#', OP (BIT5), 0 } },
36071 +    & ifmt_btst_s1_indirect_with_post_increment_4_imm_bit5, { 0x10c00200 }
36072 +  },
36073 +/* btst ${s1-i4-4}(${s1-An})++,#${bit5} */
36074 +  {
36075 +    { 0, 0, 0, 0 },
36076 +    { { MNEM, ' ', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } },
36077 +    & ifmt_btst_s1_indirect_with_pre_increment_4_imm_bit5, { 0x10c00210 }
36078 +  },
36079 +/* btst ${s1-direct-addr},${s2} */
36080 +  {
36081 +    { 0, 0, 0, 0 },
36082 +    { { MNEM, ' ', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
36083 +    & ifmt_btst_s1_direct_dyn_reg, { 0x14c00100 }
36084 +  },
36085 +/* btst #${s1-imm8},${s2} */
36086 +  {
36087 +    { 0, 0, 0, 0 },
36088 +    { { MNEM, ' ', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
36089 +    & ifmt_btst_s1_immediate_dyn_reg, { 0x14c00000 }
36090 +  },
36091 +/* btst (${s1-An},${s1-r}),${s2} */
36092 +  {
36093 +    { 0, 0, 0, 0 },
36094 +    { { MNEM, ' ', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
36095 +    & ifmt_btst_s1_indirect_with_index_4_dyn_reg, { 0x14c00300 }
36096 +  },
36097 +/* btst ${s1-imm7-4}(${s1-An}),${s2} */
36098 +  {
36099 +    { 0, 0, 0, 0 },
36100 +    { { MNEM, ' ', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
36101 +    & ifmt_btst_s1_indirect_with_offset_4_dyn_reg, { 0x14c00400 }
36102 +  },
36103 +/* btst (${s1-An}),${s2} */
36104 +  {
36105 +    { 0, 0, 0, 0 },
36106 +    { { MNEM, ' ', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
36107 +    & ifmt_btst_s1_indirect_4_dyn_reg, { 0x14c00400 }
36108 +  },
36109 +/* btst (${s1-An})${s1-i4-4}++,${s2} */
36110 +  {
36111 +    { 0, 0, 0, 0 },
36112 +    { { MNEM, ' ', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
36113 +    & ifmt_btst_s1_indirect_with_post_increment_4_dyn_reg, { 0x14c00200 }
36114 +  },
36115 +/* btst ${s1-i4-4}(${s1-An})++,${s2} */
36116 +  {
36117 +    { 0, 0, 0, 0 },
36118 +    { { MNEM, ' ', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
36119 +    & ifmt_btst_s1_indirect_with_pre_increment_4_dyn_reg, { 0x14c00210 }
36120 +  },
36121 +/* shmrg.2 ${Dn},${s1-direct-addr},#${bit5} */
36122 +  {
36123 +    { 0, 0, 0, 0 },
36124 +    { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } },
36125 +    & ifmt_shmrg_2_imm_bit5_s1_direct, { 0x13c00100 }
36126 +  },
36127 +/* shmrg.2 ${Dn},${s1-direct-addr},${s2} */
36128 +  {
36129 +    { 0, 0, 0, 0 },
36130 +    { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
36131 +    & ifmt_shmrg_2_dyn_reg_s1_direct, { 0x17c00100 }
36132 +  },
36133 +/* shmrg.2 ${Dn},#${s1-imm8},#${bit5} */
36134 +  {
36135 +    { 0, 0, 0, 0 },
36136 +    { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } },
36137 +    & ifmt_shmrg_2_imm_bit5_s1_immediate, { 0x13c00000 }
36138 +  },
36139 +/* shmrg.2 ${Dn},#${s1-imm8},${s2} */
36140 +  {
36141 +    { 0, 0, 0, 0 },
36142 +    { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
36143 +    & ifmt_shmrg_2_dyn_reg_s1_immediate, { 0x17c00000 }
36144 +  },
36145 +/* shmrg.2 ${Dn},(${s1-An},${s1-r}),#${bit5} */
36146 +  {
36147 +    { 0, 0, 0, 0 },
36148 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } },
36149 +    & ifmt_shmrg_2_imm_bit5_s1_indirect_with_index_2, { 0x13c00300 }
36150 +  },
36151 +/* shmrg.2 ${Dn},(${s1-An},${s1-r}),${s2} */
36152 +  {
36153 +    { 0, 0, 0, 0 },
36154 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
36155 +    & ifmt_shmrg_2_dyn_reg_s1_indirect_with_index_2, { 0x17c00300 }
36156 +  },
36157 +/* shmrg.2 ${Dn},${s1-imm7-2}(${s1-An}),#${bit5} */
36158 +  {
36159 +    { 0, 0, 0, 0 },
36160 +    { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
36161 +    & ifmt_shmrg_2_imm_bit5_s1_indirect_with_offset_2, { 0x13c00400 }
36162 +  },
36163 +/* shmrg.2 ${Dn},${s1-imm7-2}(${s1-An}),${s2} */
36164 +  {
36165 +    { 0, 0, 0, 0 },
36166 +    { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
36167 +    & ifmt_shmrg_2_dyn_reg_s1_indirect_with_offset_2, { 0x17c00400 }
36168 +  },
36169 +/* shmrg.2 ${Dn},(${s1-An}),#${bit5} */
36170 +  {
36171 +    { 0, 0, 0, 0 },
36172 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
36173 +    & ifmt_shmrg_2_imm_bit5_s1_indirect_2, { 0x13c00400 }
36174 +  },
36175 +/* shmrg.2 ${Dn},(${s1-An}),${s2} */
36176 +  {
36177 +    { 0, 0, 0, 0 },
36178 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
36179 +    & ifmt_shmrg_2_dyn_reg_s1_indirect_2, { 0x17c00400 }
36180 +  },
36181 +/* shmrg.2 ${Dn},(${s1-An})${s1-i4-2}++,#${bit5} */
36182 +  {
36183 +    { 0, 0, 0, 0 },
36184 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', '#', OP (BIT5), 0 } },
36185 +    & ifmt_shmrg_2_imm_bit5_s1_indirect_with_post_increment_2, { 0x13c00200 }
36186 +  },
36187 +/* shmrg.2 ${Dn},(${s1-An})${s1-i4-2}++,${s2} */
36188 +  {
36189 +    { 0, 0, 0, 0 },
36190 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } },
36191 +    & ifmt_shmrg_2_dyn_reg_s1_indirect_with_post_increment_2, { 0x17c00200 }
36192 +  },
36193 +/* shmrg.2 ${Dn},${s1-i4-2}(${s1-An})++,#${bit5} */
36194 +  {
36195 +    { 0, 0, 0, 0 },
36196 +    { { MNEM, ' ', OP (DN), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } },
36197 +    & ifmt_shmrg_2_imm_bit5_s1_indirect_with_pre_increment_2, { 0x13c00210 }
36198 +  },
36199 +/* shmrg.2 ${Dn},${s1-i4-2}(${s1-An})++,${s2} */
36200 +  {
36201 +    { 0, 0, 0, 0 },
36202 +    { { MNEM, ' ', OP (DN), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
36203 +    & ifmt_shmrg_2_dyn_reg_s1_indirect_with_pre_increment_2, { 0x17c00210 }
36204 +  },
36205 +/* shmrg.1 ${Dn},${s1-direct-addr},#${bit5} */
36206 +  {
36207 +    { 0, 0, 0, 0 },
36208 +    { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } },
36209 +    & ifmt_shmrg_2_imm_bit5_s1_direct, { 0x13e00100 }
36210 +  },
36211 +/* shmrg.1 ${Dn},${s1-direct-addr},${s2} */
36212 +  {
36213 +    { 0, 0, 0, 0 },
36214 +    { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
36215 +    & ifmt_shmrg_2_dyn_reg_s1_direct, { 0x17e00100 }
36216 +  },
36217 +/* shmrg.1 ${Dn},#${s1-imm8},#${bit5} */
36218 +  {
36219 +    { 0, 0, 0, 0 },
36220 +    { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } },
36221 +    & ifmt_shmrg_2_imm_bit5_s1_immediate, { 0x13e00000 }
36222 +  },
36223 +/* shmrg.1 ${Dn},#${s1-imm8},${s2} */
36224 +  {
36225 +    { 0, 0, 0, 0 },
36226 +    { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
36227 +    & ifmt_shmrg_2_dyn_reg_s1_immediate, { 0x17e00000 }
36228 +  },
36229 +/* shmrg.1 ${Dn},(${s1-An},${s1-r}),#${bit5} */
36230 +  {
36231 +    { 0, 0, 0, 0 },
36232 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } },
36233 +    & ifmt_shmrg_1_imm_bit5_s1_indirect_with_index_1, { 0x13e00300 }
36234 +  },
36235 +/* shmrg.1 ${Dn},(${s1-An},${s1-r}),${s2} */
36236 +  {
36237 +    { 0, 0, 0, 0 },
36238 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
36239 +    & ifmt_shmrg_1_dyn_reg_s1_indirect_with_index_1, { 0x17e00300 }
36240 +  },
36241 +/* shmrg.1 ${Dn},${s1-imm7-1}(${s1-An}),#${bit5} */
36242 +  {
36243 +    { 0, 0, 0, 0 },
36244 +    { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
36245 +    & ifmt_shmrg_1_imm_bit5_s1_indirect_with_offset_1, { 0x13e00400 }
36246 +  },
36247 +/* shmrg.1 ${Dn},${s1-imm7-1}(${s1-An}),${s2} */
36248 +  {
36249 +    { 0, 0, 0, 0 },
36250 +    { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
36251 +    & ifmt_shmrg_1_dyn_reg_s1_indirect_with_offset_1, { 0x17e00400 }
36252 +  },
36253 +/* shmrg.1 ${Dn},(${s1-An}),#${bit5} */
36254 +  {
36255 +    { 0, 0, 0, 0 },
36256 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
36257 +    & ifmt_shmrg_1_imm_bit5_s1_indirect_1, { 0x13e00400 }
36258 +  },
36259 +/* shmrg.1 ${Dn},(${s1-An}),${s2} */
36260 +  {
36261 +    { 0, 0, 0, 0 },
36262 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
36263 +    & ifmt_shmrg_1_dyn_reg_s1_indirect_1, { 0x17e00400 }
36264 +  },
36265 +/* shmrg.1 ${Dn},(${s1-An})${s1-i4-1}++,#${bit5} */
36266 +  {
36267 +    { 0, 0, 0, 0 },
36268 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', '#', OP (BIT5), 0 } },
36269 +    & ifmt_shmrg_1_imm_bit5_s1_indirect_with_post_increment_1, { 0x13e00200 }
36270 +  },
36271 +/* shmrg.1 ${Dn},(${s1-An})${s1-i4-1}++,${s2} */
36272 +  {
36273 +    { 0, 0, 0, 0 },
36274 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } },
36275 +    & ifmt_shmrg_1_dyn_reg_s1_indirect_with_post_increment_1, { 0x17e00200 }
36276 +  },
36277 +/* shmrg.1 ${Dn},${s1-i4-1}(${s1-An})++,#${bit5} */
36278 +  {
36279 +    { 0, 0, 0, 0 },
36280 +    { { MNEM, ' ', OP (DN), ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } },
36281 +    & ifmt_shmrg_1_imm_bit5_s1_indirect_with_pre_increment_1, { 0x13e00210 }
36282 +  },
36283 +/* shmrg.1 ${Dn},${s1-i4-1}(${s1-An})++,${s2} */
36284 +  {
36285 +    { 0, 0, 0, 0 },
36286 +    { { MNEM, ' ', OP (DN), ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
36287 +    & ifmt_shmrg_1_dyn_reg_s1_indirect_with_pre_increment_1, { 0x17e00210 }
36288 +  },
36289 +/* crcgen ${s1-direct-addr},#${bit5} */
36290 +  {
36291 +    { 0, 0, 0, 0 },
36292 +    { { MNEM, ' ', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } },
36293 +    & ifmt_btst_s1_direct_imm_bit5, { 0x11000100 }
36294 +  },
36295 +/* crcgen #${s1-imm8},#${bit5} */
36296 +  {
36297 +    { 0, 0, 0, 0 },
36298 +    { { MNEM, ' ', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } },
36299 +    & ifmt_btst_s1_immediate_imm_bit5, { 0x11000000 }
36300 +  },
36301 +/* crcgen (${s1-An},${s1-r}),#${bit5} */
36302 +  {
36303 +    { 0, 0, 0, 0 },
36304 +    { { MNEM, ' ', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } },
36305 +    & ifmt_crcgen_s1_indirect_with_index_1_imm_bit5, { 0x11000300 }
36306 +  },
36307 +/* crcgen ${s1-imm7-1}(${s1-An}),#${bit5} */
36308 +  {
36309 +    { 0, 0, 0, 0 },
36310 +    { { MNEM, ' ', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
36311 +    & ifmt_crcgen_s1_indirect_with_offset_1_imm_bit5, { 0x11000400 }
36312 +  },
36313 +/* crcgen (${s1-An}),#${bit5} */
36314 +  {
36315 +    { 0, 0, 0, 0 },
36316 +    { { MNEM, ' ', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
36317 +    & ifmt_crcgen_s1_indirect_1_imm_bit5, { 0x11000400 }
36318 +  },
36319 +/* crcgen (${s1-An})${s1-i4-1}++,#${bit5} */
36320 +  {
36321 +    { 0, 0, 0, 0 },
36322 +    { { MNEM, ' ', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', '#', OP (BIT5), 0 } },
36323 +    & ifmt_crcgen_s1_indirect_with_post_increment_1_imm_bit5, { 0x11000200 }
36324 +  },
36325 +/* crcgen ${s1-i4-1}(${s1-An})++,#${bit5} */
36326 +  {
36327 +    { 0, 0, 0, 0 },
36328 +    { { MNEM, ' ', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } },
36329 +    & ifmt_crcgen_s1_indirect_with_pre_increment_1_imm_bit5, { 0x11000210 }
36330 +  },
36331 +/* crcgen ${s1-direct-addr},${s2} */
36332 +  {
36333 +    { 0, 0, 0, 0 },
36334 +    { { MNEM, ' ', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
36335 +    & ifmt_btst_s1_direct_dyn_reg, { 0x15000100 }
36336 +  },
36337 +/* crcgen #${s1-imm8},${s2} */
36338 +  {
36339 +    { 0, 0, 0, 0 },
36340 +    { { MNEM, ' ', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
36341 +    & ifmt_btst_s1_immediate_dyn_reg, { 0x15000000 }
36342 +  },
36343 +/* crcgen (${s1-An},${s1-r}),${s2} */
36344 +  {
36345 +    { 0, 0, 0, 0 },
36346 +    { { MNEM, ' ', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
36347 +    & ifmt_crcgen_s1_indirect_with_index_1_dyn_reg, { 0x15000300 }
36348 +  },
36349 +/* crcgen ${s1-imm7-1}(${s1-An}),${s2} */
36350 +  {
36351 +    { 0, 0, 0, 0 },
36352 +    { { MNEM, ' ', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
36353 +    & ifmt_crcgen_s1_indirect_with_offset_1_dyn_reg, { 0x15000400 }
36354 +  },
36355 +/* crcgen (${s1-An}),${s2} */
36356 +  {
36357 +    { 0, 0, 0, 0 },
36358 +    { { MNEM, ' ', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
36359 +    & ifmt_crcgen_s1_indirect_1_dyn_reg, { 0x15000400 }
36360 +  },
36361 +/* crcgen (${s1-An})${s1-i4-1}++,${s2} */
36362 +  {
36363 +    { 0, 0, 0, 0 },
36364 +    { { MNEM, ' ', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } },
36365 +    & ifmt_crcgen_s1_indirect_with_post_increment_1_dyn_reg, { 0x15000200 }
36366 +  },
36367 +/* crcgen ${s1-i4-1}(${s1-An})++,${s2} */
36368 +  {
36369 +    { 0, 0, 0, 0 },
36370 +    { { MNEM, ' ', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
36371 +    & ifmt_crcgen_s1_indirect_with_pre_increment_1_dyn_reg, { 0x15000210 }
36372 +  },
36373 +/* bfextu ${Dn},${s1-direct-addr},#${bit5} */
36374 +  {
36375 +    { 0, 0, 0, 0 },
36376 +    { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } },
36377 +    & ifmt_bfextu_s1_direct_imm_bit5, { 0x12c00100 }
36378 +  },
36379 +/* bfextu ${Dn},#${s1-imm8},#${bit5} */
36380 +  {
36381 +    { 0, 0, 0, 0 },
36382 +    { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } },
36383 +    & ifmt_bfextu_s1_immediate_imm_bit5, { 0x12c00000 }
36384 +  },
36385 +/* bfextu ${Dn},(${s1-An},${s1-r}),#${bit5} */
36386 +  {
36387 +    { 0, 0, 0, 0 },
36388 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } },
36389 +    & ifmt_bfextu_s1_indirect_with_index_4_imm_bit5, { 0x12c00300 }
36390 +  },
36391 +/* bfextu ${Dn},${s1-imm7-4}(${s1-An}),#${bit5} */
36392 +  {
36393 +    { 0, 0, 0, 0 },
36394 +    { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
36395 +    & ifmt_bfextu_s1_indirect_with_offset_4_imm_bit5, { 0x12c00400 }
36396 +  },
36397 +/* bfextu ${Dn},(${s1-An}),#${bit5} */
36398 +  {
36399 +    { 0, 0, 0, 0 },
36400 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
36401 +    & ifmt_bfextu_s1_indirect_4_imm_bit5, { 0x12c00400 }
36402 +  },
36403 +/* bfextu ${Dn},(${s1-An})${s1-i4-4}++,#${bit5} */
36404 +  {
36405 +    { 0, 0, 0, 0 },
36406 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', '#', OP (BIT5), 0 } },
36407 +    & ifmt_bfextu_s1_indirect_with_post_increment_4_imm_bit5, { 0x12c00200 }
36408 +  },
36409 +/* bfextu ${Dn},${s1-i4-4}(${s1-An})++,#${bit5} */
36410 +  {
36411 +    { 0, 0, 0, 0 },
36412 +    { { MNEM, ' ', OP (DN), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } },
36413 +    & ifmt_bfextu_s1_indirect_with_pre_increment_4_imm_bit5, { 0x12c00210 }
36414 +  },
36415 +/* bfextu ${Dn},${s1-direct-addr},${s2} */
36416 +  {
36417 +    { 0, 0, 0, 0 },
36418 +    { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
36419 +    & ifmt_bfextu_s1_direct_dyn_reg, { 0x16c00100 }
36420 +  },
36421 +/* bfextu ${Dn},#${s1-imm8},${s2} */
36422 +  {
36423 +    { 0, 0, 0, 0 },
36424 +    { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
36425 +    & ifmt_bfextu_s1_immediate_dyn_reg, { 0x16c00000 }
36426 +  },
36427 +/* bfextu ${Dn},(${s1-An},${s1-r}),${s2} */
36428 +  {
36429 +    { 0, 0, 0, 0 },
36430 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
36431 +    & ifmt_bfextu_s1_indirect_with_index_4_dyn_reg, { 0x16c00300 }
36432 +  },
36433 +/* bfextu ${Dn},${s1-imm7-4}(${s1-An}),${s2} */
36434 +  {
36435 +    { 0, 0, 0, 0 },
36436 +    { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
36437 +    & ifmt_bfextu_s1_indirect_with_offset_4_dyn_reg, { 0x16c00400 }
36438 +  },
36439 +/* bfextu ${Dn},(${s1-An}),${s2} */
36440 +  {
36441 +    { 0, 0, 0, 0 },
36442 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
36443 +    & ifmt_bfextu_s1_indirect_4_dyn_reg, { 0x16c00400 }
36444 +  },
36445 +/* bfextu ${Dn},(${s1-An})${s1-i4-4}++,${s2} */
36446 +  {
36447 +    { 0, 0, 0, 0 },
36448 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
36449 +    & ifmt_bfextu_s1_indirect_with_post_increment_4_dyn_reg, { 0x16c00200 }
36450 +  },
36451 +/* bfextu ${Dn},${s1-i4-4}(${s1-An})++,${s2} */
36452 +  {
36453 +    { 0, 0, 0, 0 },
36454 +    { { MNEM, ' ', OP (DN), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
36455 +    & ifmt_bfextu_s1_indirect_with_pre_increment_4_dyn_reg, { 0x16c00210 }
36456 +  },
36457 +/* bfrvrs ${Dn},${s1-direct-addr},#${bit5} */
36458 +  {
36459 +    { 0, 0, 0, 0 },
36460 +    { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } },
36461 +    & ifmt_bfextu_s1_direct_imm_bit5, { 0x13000100 }
36462 +  },
36463 +/* bfrvrs ${Dn},#${s1-imm8},#${bit5} */
36464 +  {
36465 +    { 0, 0, 0, 0 },
36466 +    { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } },
36467 +    & ifmt_bfextu_s1_immediate_imm_bit5, { 0x13000000 }
36468 +  },
36469 +/* bfrvrs ${Dn},(${s1-An},${s1-r}),#${bit5} */
36470 +  {
36471 +    { 0, 0, 0, 0 },
36472 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } },
36473 +    & ifmt_bfextu_s1_indirect_with_index_4_imm_bit5, { 0x13000300 }
36474 +  },
36475 +/* bfrvrs ${Dn},${s1-imm7-4}(${s1-An}),#${bit5} */
36476 +  {
36477 +    { 0, 0, 0, 0 },
36478 +    { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
36479 +    & ifmt_bfextu_s1_indirect_with_offset_4_imm_bit5, { 0x13000400 }
36480 +  },
36481 +/* bfrvrs ${Dn},(${s1-An}),#${bit5} */
36482 +  {
36483 +    { 0, 0, 0, 0 },
36484 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
36485 +    & ifmt_bfextu_s1_indirect_4_imm_bit5, { 0x13000400 }
36486 +  },
36487 +/* bfrvrs ${Dn},(${s1-An})${s1-i4-4}++,#${bit5} */
36488 +  {
36489 +    { 0, 0, 0, 0 },
36490 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', '#', OP (BIT5), 0 } },
36491 +    & ifmt_bfextu_s1_indirect_with_post_increment_4_imm_bit5, { 0x13000200 }
36492 +  },
36493 +/* bfrvrs ${Dn},${s1-i4-4}(${s1-An})++,#${bit5} */
36494 +  {
36495 +    { 0, 0, 0, 0 },
36496 +    { { MNEM, ' ', OP (DN), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } },
36497 +    & ifmt_bfextu_s1_indirect_with_pre_increment_4_imm_bit5, { 0x13000210 }
36498 +  },
36499 +/* bfrvrs ${Dn},${s1-direct-addr},${s2} */
36500 +  {
36501 +    { 0, 0, 0, 0 },
36502 +    { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
36503 +    & ifmt_bfextu_s1_direct_dyn_reg, { 0x17000100 }
36504 +  },
36505 +/* bfrvrs ${Dn},#${s1-imm8},${s2} */
36506 +  {
36507 +    { 0, 0, 0, 0 },
36508 +    { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
36509 +    & ifmt_bfextu_s1_immediate_dyn_reg, { 0x17000000 }
36510 +  },
36511 +/* bfrvrs ${Dn},(${s1-An},${s1-r}),${s2} */
36512 +  {
36513 +    { 0, 0, 0, 0 },
36514 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
36515 +    & ifmt_bfextu_s1_indirect_with_index_4_dyn_reg, { 0x17000300 }
36516 +  },
36517 +/* bfrvrs ${Dn},${s1-imm7-4}(${s1-An}),${s2} */
36518 +  {
36519 +    { 0, 0, 0, 0 },
36520 +    { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
36521 +    & ifmt_bfextu_s1_indirect_with_offset_4_dyn_reg, { 0x17000400 }
36522 +  },
36523 +/* bfrvrs ${Dn},(${s1-An}),${s2} */
36524 +  {
36525 +    { 0, 0, 0, 0 },
36526 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
36527 +    & ifmt_bfextu_s1_indirect_4_dyn_reg, { 0x17000400 }
36528 +  },
36529 +/* bfrvrs ${Dn},(${s1-An})${s1-i4-4}++,${s2} */
36530 +  {
36531 +    { 0, 0, 0, 0 },
36532 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
36533 +    & ifmt_bfextu_s1_indirect_with_post_increment_4_dyn_reg, { 0x17000200 }
36534 +  },
36535 +/* bfrvrs ${Dn},${s1-i4-4}(${s1-An})++,${s2} */
36536 +  {
36537 +    { 0, 0, 0, 0 },
36538 +    { { MNEM, ' ', OP (DN), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
36539 +    & ifmt_bfextu_s1_indirect_with_pre_increment_4_dyn_reg, { 0x17000210 }
36540 +  },
36541 +/* merge ${Dn},${s1-direct-addr},#${bit5} */
36542 +  {
36543 +    { 0, 0, 0, 0 },
36544 +    { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } },
36545 +    & ifmt_bfextu_s1_direct_imm_bit5, { 0x13800100 }
36546 +  },
36547 +/* merge ${Dn},#${s1-imm8},#${bit5} */
36548 +  {
36549 +    { 0, 0, 0, 0 },
36550 +    { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } },
36551 +    & ifmt_bfextu_s1_immediate_imm_bit5, { 0x13800000 }
36552 +  },
36553 +/* merge ${Dn},(${s1-An},${s1-r}),#${bit5} */
36554 +  {
36555 +    { 0, 0, 0, 0 },
36556 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } },
36557 +    & ifmt_bfextu_s1_indirect_with_index_4_imm_bit5, { 0x13800300 }
36558 +  },
36559 +/* merge ${Dn},${s1-imm7-4}(${s1-An}),#${bit5} */
36560 +  {
36561 +    { 0, 0, 0, 0 },
36562 +    { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
36563 +    & ifmt_bfextu_s1_indirect_with_offset_4_imm_bit5, { 0x13800400 }
36564 +  },
36565 +/* merge ${Dn},(${s1-An}),#${bit5} */
36566 +  {
36567 +    { 0, 0, 0, 0 },
36568 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
36569 +    & ifmt_bfextu_s1_indirect_4_imm_bit5, { 0x13800400 }
36570 +  },
36571 +/* merge ${Dn},(${s1-An})${s1-i4-4}++,#${bit5} */
36572 +  {
36573 +    { 0, 0, 0, 0 },
36574 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', '#', OP (BIT5), 0 } },
36575 +    & ifmt_bfextu_s1_indirect_with_post_increment_4_imm_bit5, { 0x13800200 }
36576 +  },
36577 +/* merge ${Dn},${s1-i4-4}(${s1-An})++,#${bit5} */
36578 +  {
36579 +    { 0, 0, 0, 0 },
36580 +    { { MNEM, ' ', OP (DN), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } },
36581 +    & ifmt_bfextu_s1_indirect_with_pre_increment_4_imm_bit5, { 0x13800210 }
36582 +  },
36583 +/* merge ${Dn},${s1-direct-addr},${s2} */
36584 +  {
36585 +    { 0, 0, 0, 0 },
36586 +    { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
36587 +    & ifmt_bfextu_s1_direct_dyn_reg, { 0x17800100 }
36588 +  },
36589 +/* merge ${Dn},#${s1-imm8},${s2} */
36590 +  {
36591 +    { 0, 0, 0, 0 },
36592 +    { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
36593 +    & ifmt_bfextu_s1_immediate_dyn_reg, { 0x17800000 }
36594 +  },
36595 +/* merge ${Dn},(${s1-An},${s1-r}),${s2} */
36596 +  {
36597 +    { 0, 0, 0, 0 },
36598 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
36599 +    & ifmt_bfextu_s1_indirect_with_index_4_dyn_reg, { 0x17800300 }
36600 +  },
36601 +/* merge ${Dn},${s1-imm7-4}(${s1-An}),${s2} */
36602 +  {
36603 +    { 0, 0, 0, 0 },
36604 +    { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
36605 +    & ifmt_bfextu_s1_indirect_with_offset_4_dyn_reg, { 0x17800400 }
36606 +  },
36607 +/* merge ${Dn},(${s1-An}),${s2} */
36608 +  {
36609 +    { 0, 0, 0, 0 },
36610 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
36611 +    & ifmt_bfextu_s1_indirect_4_dyn_reg, { 0x17800400 }
36612 +  },
36613 +/* merge ${Dn},(${s1-An})${s1-i4-4}++,${s2} */
36614 +  {
36615 +    { 0, 0, 0, 0 },
36616 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
36617 +    & ifmt_bfextu_s1_indirect_with_post_increment_4_dyn_reg, { 0x17800200 }
36618 +  },
36619 +/* merge ${Dn},${s1-i4-4}(${s1-An})++,${s2} */
36620 +  {
36621 +    { 0, 0, 0, 0 },
36622 +    { { MNEM, ' ', OP (DN), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
36623 +    & ifmt_bfextu_s1_indirect_with_pre_increment_4_dyn_reg, { 0x17800210 }
36624 +  },
36625 +/* shftd ${Dn},${s1-direct-addr},#${bit5} */
36626 +  {
36627 +    { 0, 0, 0, 0 },
36628 +    { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } },
36629 +    & ifmt_bfextu_s1_direct_imm_bit5, { 0x13400100 }
36630 +  },
36631 +/* shftd ${Dn},#${s1-imm8},#${bit5} */
36632 +  {
36633 +    { 0, 0, 0, 0 },
36634 +    { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } },
36635 +    & ifmt_bfextu_s1_immediate_imm_bit5, { 0x13400000 }
36636 +  },
36637 +/* shftd ${Dn},(${s1-An},${s1-r}),#${bit5} */
36638 +  {
36639 +    { 0, 0, 0, 0 },
36640 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } },
36641 +    & ifmt_bfextu_s1_indirect_with_index_4_imm_bit5, { 0x13400300 }
36642 +  },
36643 +/* shftd ${Dn},${s1-imm7-4}(${s1-An}),#${bit5} */
36644 +  {
36645 +    { 0, 0, 0, 0 },
36646 +    { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
36647 +    & ifmt_bfextu_s1_indirect_with_offset_4_imm_bit5, { 0x13400400 }
36648 +  },
36649 +/* shftd ${Dn},(${s1-An}),#${bit5} */
36650 +  {
36651 +    { 0, 0, 0, 0 },
36652 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
36653 +    & ifmt_bfextu_s1_indirect_4_imm_bit5, { 0x13400400 }
36654 +  },
36655 +/* shftd ${Dn},(${s1-An})${s1-i4-4}++,#${bit5} */
36656 +  {
36657 +    { 0, 0, 0, 0 },
36658 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', '#', OP (BIT5), 0 } },
36659 +    & ifmt_bfextu_s1_indirect_with_post_increment_4_imm_bit5, { 0x13400200 }
36660 +  },
36661 +/* shftd ${Dn},${s1-i4-4}(${s1-An})++,#${bit5} */
36662 +  {
36663 +    { 0, 0, 0, 0 },
36664 +    { { MNEM, ' ', OP (DN), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } },
36665 +    & ifmt_bfextu_s1_indirect_with_pre_increment_4_imm_bit5, { 0x13400210 }
36666 +  },
36667 +/* shftd ${Dn},${s1-direct-addr},${s2} */
36668 +  {
36669 +    { 0, 0, 0, 0 },
36670 +    { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
36671 +    & ifmt_bfextu_s1_direct_dyn_reg, { 0x17400100 }
36672 +  },
36673 +/* shftd ${Dn},#${s1-imm8},${s2} */
36674 +  {
36675 +    { 0, 0, 0, 0 },
36676 +    { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
36677 +    & ifmt_bfextu_s1_immediate_dyn_reg, { 0x17400000 }
36678 +  },
36679 +/* shftd ${Dn},(${s1-An},${s1-r}),${s2} */
36680 +  {
36681 +    { 0, 0, 0, 0 },
36682 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
36683 +    & ifmt_bfextu_s1_indirect_with_index_4_dyn_reg, { 0x17400300 }
36684 +  },
36685 +/* shftd ${Dn},${s1-imm7-4}(${s1-An}),${s2} */
36686 +  {
36687 +    { 0, 0, 0, 0 },
36688 +    { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
36689 +    & ifmt_bfextu_s1_indirect_with_offset_4_dyn_reg, { 0x17400400 }
36690 +  },
36691 +/* shftd ${Dn},(${s1-An}),${s2} */
36692 +  {
36693 +    { 0, 0, 0, 0 },
36694 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
36695 +    & ifmt_bfextu_s1_indirect_4_dyn_reg, { 0x17400400 }
36696 +  },
36697 +/* shftd ${Dn},(${s1-An})${s1-i4-4}++,${s2} */
36698 +  {
36699 +    { 0, 0, 0, 0 },
36700 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
36701 +    & ifmt_bfextu_s1_indirect_with_post_increment_4_dyn_reg, { 0x17400200 }
36702 +  },
36703 +/* shftd ${Dn},${s1-i4-4}(${s1-An})++,${s2} */
36704 +  {
36705 +    { 0, 0, 0, 0 },
36706 +    { { MNEM, ' ', OP (DN), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
36707 +    & ifmt_bfextu_s1_indirect_with_pre_increment_4_dyn_reg, { 0x17400210 }
36708 +  },
36709 +/* asr.1 ${Dn},${s1-direct-addr},#${bit5} */
36710 +  {
36711 +    { 0, 0, 0, 0 },
36712 +    { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } },
36713 +    & ifmt_shmrg_2_imm_bit5_s1_direct, { 0x11800100 }
36714 +  },
36715 +/* asr.1 ${Dn},${s1-direct-addr},${s2} */
36716 +  {
36717 +    { 0, 0, 0, 0 },
36718 +    { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
36719 +    & ifmt_shmrg_2_dyn_reg_s1_direct, { 0x15800100 }
36720 +  },
36721 +/* asr.1 ${Dn},#${s1-imm8},#${bit5} */
36722 +  {
36723 +    { 0, 0, 0, 0 },
36724 +    { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } },
36725 +    & ifmt_shmrg_2_imm_bit5_s1_immediate, { 0x11800000 }
36726 +  },
36727 +/* asr.1 ${Dn},#${s1-imm8},${s2} */
36728 +  {
36729 +    { 0, 0, 0, 0 },
36730 +    { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
36731 +    & ifmt_shmrg_2_dyn_reg_s1_immediate, { 0x15800000 }
36732 +  },
36733 +/* asr.1 ${Dn},(${s1-An},${s1-r}),#${bit5} */
36734 +  {
36735 +    { 0, 0, 0, 0 },
36736 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } },
36737 +    & ifmt_shmrg_1_imm_bit5_s1_indirect_with_index_1, { 0x11800300 }
36738 +  },
36739 +/* asr.1 ${Dn},(${s1-An},${s1-r}),${s2} */
36740 +  {
36741 +    { 0, 0, 0, 0 },
36742 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
36743 +    & ifmt_shmrg_1_dyn_reg_s1_indirect_with_index_1, { 0x15800300 }
36744 +  },
36745 +/* asr.1 ${Dn},${s1-imm7-1}(${s1-An}),#${bit5} */
36746 +  {
36747 +    { 0, 0, 0, 0 },
36748 +    { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
36749 +    & ifmt_shmrg_1_imm_bit5_s1_indirect_with_offset_1, { 0x11800400 }
36750 +  },
36751 +/* asr.1 ${Dn},${s1-imm7-1}(${s1-An}),${s2} */
36752 +  {
36753 +    { 0, 0, 0, 0 },
36754 +    { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
36755 +    & ifmt_shmrg_1_dyn_reg_s1_indirect_with_offset_1, { 0x15800400 }
36756 +  },
36757 +/* asr.1 ${Dn},(${s1-An}),#${bit5} */
36758 +  {
36759 +    { 0, 0, 0, 0 },
36760 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
36761 +    & ifmt_shmrg_1_imm_bit5_s1_indirect_1, { 0x11800400 }
36762 +  },
36763 +/* asr.1 ${Dn},(${s1-An}),${s2} */
36764 +  {
36765 +    { 0, 0, 0, 0 },
36766 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
36767 +    & ifmt_shmrg_1_dyn_reg_s1_indirect_1, { 0x15800400 }
36768 +  },
36769 +/* asr.1 ${Dn},(${s1-An})${s1-i4-1}++,#${bit5} */
36770 +  {
36771 +    { 0, 0, 0, 0 },
36772 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', '#', OP (BIT5), 0 } },
36773 +    & ifmt_shmrg_1_imm_bit5_s1_indirect_with_post_increment_1, { 0x11800200 }
36774 +  },
36775 +/* asr.1 ${Dn},(${s1-An})${s1-i4-1}++,${s2} */
36776 +  {
36777 +    { 0, 0, 0, 0 },
36778 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } },
36779 +    & ifmt_shmrg_1_dyn_reg_s1_indirect_with_post_increment_1, { 0x15800200 }
36780 +  },
36781 +/* asr.1 ${Dn},${s1-i4-1}(${s1-An})++,#${bit5} */
36782 +  {
36783 +    { 0, 0, 0, 0 },
36784 +    { { MNEM, ' ', OP (DN), ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } },
36785 +    & ifmt_shmrg_1_imm_bit5_s1_indirect_with_pre_increment_1, { 0x11800210 }
36786 +  },
36787 +/* asr.1 ${Dn},${s1-i4-1}(${s1-An})++,${s2} */
36788 +  {
36789 +    { 0, 0, 0, 0 },
36790 +    { { MNEM, ' ', OP (DN), ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
36791 +    & ifmt_shmrg_1_dyn_reg_s1_indirect_with_pre_increment_1, { 0x15800210 }
36792 +  },
36793 +/* lsl.1 ${Dn},${s1-direct-addr},#${bit5} */
36794 +  {
36795 +    { 0, 0, 0, 0 },
36796 +    { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } },
36797 +    & ifmt_shmrg_2_imm_bit5_s1_direct, { 0x11400100 }
36798 +  },
36799 +/* lsl.1 ${Dn},${s1-direct-addr},${s2} */
36800 +  {
36801 +    { 0, 0, 0, 0 },
36802 +    { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
36803 +    & ifmt_shmrg_2_dyn_reg_s1_direct, { 0x15400100 }
36804 +  },
36805 +/* lsl.1 ${Dn},#${s1-imm8},#${bit5} */
36806 +  {
36807 +    { 0, 0, 0, 0 },
36808 +    { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } },
36809 +    & ifmt_shmrg_2_imm_bit5_s1_immediate, { 0x11400000 }
36810 +  },
36811 +/* lsl.1 ${Dn},#${s1-imm8},${s2} */
36812 +  {
36813 +    { 0, 0, 0, 0 },
36814 +    { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
36815 +    & ifmt_shmrg_2_dyn_reg_s1_immediate, { 0x15400000 }
36816 +  },
36817 +/* lsl.1 ${Dn},(${s1-An},${s1-r}),#${bit5} */
36818 +  {
36819 +    { 0, 0, 0, 0 },
36820 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } },
36821 +    & ifmt_shmrg_1_imm_bit5_s1_indirect_with_index_1, { 0x11400300 }
36822 +  },
36823 +/* lsl.1 ${Dn},(${s1-An},${s1-r}),${s2} */
36824 +  {
36825 +    { 0, 0, 0, 0 },
36826 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
36827 +    & ifmt_shmrg_1_dyn_reg_s1_indirect_with_index_1, { 0x15400300 }
36828 +  },
36829 +/* lsl.1 ${Dn},${s1-imm7-1}(${s1-An}),#${bit5} */
36830 +  {
36831 +    { 0, 0, 0, 0 },
36832 +    { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
36833 +    & ifmt_shmrg_1_imm_bit5_s1_indirect_with_offset_1, { 0x11400400 }
36834 +  },
36835 +/* lsl.1 ${Dn},${s1-imm7-1}(${s1-An}),${s2} */
36836 +  {
36837 +    { 0, 0, 0, 0 },
36838 +    { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
36839 +    & ifmt_shmrg_1_dyn_reg_s1_indirect_with_offset_1, { 0x15400400 }
36840 +  },
36841 +/* lsl.1 ${Dn},(${s1-An}),#${bit5} */
36842 +  {
36843 +    { 0, 0, 0, 0 },
36844 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
36845 +    & ifmt_shmrg_1_imm_bit5_s1_indirect_1, { 0x11400400 }
36846 +  },
36847 +/* lsl.1 ${Dn},(${s1-An}),${s2} */
36848 +  {
36849 +    { 0, 0, 0, 0 },
36850 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
36851 +    & ifmt_shmrg_1_dyn_reg_s1_indirect_1, { 0x15400400 }
36852 +  },
36853 +/* lsl.1 ${Dn},(${s1-An})${s1-i4-1}++,#${bit5} */
36854 +  {
36855 +    { 0, 0, 0, 0 },
36856 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', '#', OP (BIT5), 0 } },
36857 +    & ifmt_shmrg_1_imm_bit5_s1_indirect_with_post_increment_1, { 0x11400200 }
36858 +  },
36859 +/* lsl.1 ${Dn},(${s1-An})${s1-i4-1}++,${s2} */
36860 +  {
36861 +    { 0, 0, 0, 0 },
36862 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } },
36863 +    & ifmt_shmrg_1_dyn_reg_s1_indirect_with_post_increment_1, { 0x15400200 }
36864 +  },
36865 +/* lsl.1 ${Dn},${s1-i4-1}(${s1-An})++,#${bit5} */
36866 +  {
36867 +    { 0, 0, 0, 0 },
36868 +    { { MNEM, ' ', OP (DN), ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } },
36869 +    & ifmt_shmrg_1_imm_bit5_s1_indirect_with_pre_increment_1, { 0x11400210 }
36870 +  },
36871 +/* lsl.1 ${Dn},${s1-i4-1}(${s1-An})++,${s2} */
36872 +  {
36873 +    { 0, 0, 0, 0 },
36874 +    { { MNEM, ' ', OP (DN), ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
36875 +    & ifmt_shmrg_1_dyn_reg_s1_indirect_with_pre_increment_1, { 0x15400210 }
36876 +  },
36877 +/* lsr.1 ${Dn},${s1-direct-addr},#${bit5} */
36878 +  {
36879 +    { 0, 0, 0, 0 },
36880 +    { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } },
36881 +    & ifmt_shmrg_2_imm_bit5_s1_direct, { 0x11600100 }
36882 +  },
36883 +/* lsr.1 ${Dn},${s1-direct-addr},${s2} */
36884 +  {
36885 +    { 0, 0, 0, 0 },
36886 +    { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
36887 +    & ifmt_shmrg_2_dyn_reg_s1_direct, { 0x15600100 }
36888 +  },
36889 +/* lsr.1 ${Dn},#${s1-imm8},#${bit5} */
36890 +  {
36891 +    { 0, 0, 0, 0 },
36892 +    { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } },
36893 +    & ifmt_shmrg_2_imm_bit5_s1_immediate, { 0x11600000 }
36894 +  },
36895 +/* lsr.1 ${Dn},#${s1-imm8},${s2} */
36896 +  {
36897 +    { 0, 0, 0, 0 },
36898 +    { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
36899 +    & ifmt_shmrg_2_dyn_reg_s1_immediate, { 0x15600000 }
36900 +  },
36901 +/* lsr.1 ${Dn},(${s1-An},${s1-r}),#${bit5} */
36902 +  {
36903 +    { 0, 0, 0, 0 },
36904 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } },
36905 +    & ifmt_shmrg_1_imm_bit5_s1_indirect_with_index_1, { 0x11600300 }
36906 +  },
36907 +/* lsr.1 ${Dn},(${s1-An},${s1-r}),${s2} */
36908 +  {
36909 +    { 0, 0, 0, 0 },
36910 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
36911 +    & ifmt_shmrg_1_dyn_reg_s1_indirect_with_index_1, { 0x15600300 }
36912 +  },
36913 +/* lsr.1 ${Dn},${s1-imm7-1}(${s1-An}),#${bit5} */
36914 +  {
36915 +    { 0, 0, 0, 0 },
36916 +    { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
36917 +    & ifmt_shmrg_1_imm_bit5_s1_indirect_with_offset_1, { 0x11600400 }
36918 +  },
36919 +/* lsr.1 ${Dn},${s1-imm7-1}(${s1-An}),${s2} */
36920 +  {
36921 +    { 0, 0, 0, 0 },
36922 +    { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
36923 +    & ifmt_shmrg_1_dyn_reg_s1_indirect_with_offset_1, { 0x15600400 }
36924 +  },
36925 +/* lsr.1 ${Dn},(${s1-An}),#${bit5} */
36926 +  {
36927 +    { 0, 0, 0, 0 },
36928 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
36929 +    & ifmt_shmrg_1_imm_bit5_s1_indirect_1, { 0x11600400 }
36930 +  },
36931 +/* lsr.1 ${Dn},(${s1-An}),${s2} */
36932 +  {
36933 +    { 0, 0, 0, 0 },
36934 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
36935 +    & ifmt_shmrg_1_dyn_reg_s1_indirect_1, { 0x15600400 }
36936 +  },
36937 +/* lsr.1 ${Dn},(${s1-An})${s1-i4-1}++,#${bit5} */
36938 +  {
36939 +    { 0, 0, 0, 0 },
36940 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', '#', OP (BIT5), 0 } },
36941 +    & ifmt_shmrg_1_imm_bit5_s1_indirect_with_post_increment_1, { 0x11600200 }
36942 +  },
36943 +/* lsr.1 ${Dn},(${s1-An})${s1-i4-1}++,${s2} */
36944 +  {
36945 +    { 0, 0, 0, 0 },
36946 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } },
36947 +    & ifmt_shmrg_1_dyn_reg_s1_indirect_with_post_increment_1, { 0x15600200 }
36948 +  },
36949 +/* lsr.1 ${Dn},${s1-i4-1}(${s1-An})++,#${bit5} */
36950 +  {
36951 +    { 0, 0, 0, 0 },
36952 +    { { MNEM, ' ', OP (DN), ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } },
36953 +    & ifmt_shmrg_1_imm_bit5_s1_indirect_with_pre_increment_1, { 0x11600210 }
36954 +  },
36955 +/* lsr.1 ${Dn},${s1-i4-1}(${s1-An})++,${s2} */
36956 +  {
36957 +    { 0, 0, 0, 0 },
36958 +    { { MNEM, ' ', OP (DN), ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
36959 +    & ifmt_shmrg_1_dyn_reg_s1_indirect_with_pre_increment_1, { 0x15600210 }
36960 +  },
36961 +/* asr.2 ${Dn},${s1-direct-addr},#${bit5} */
36962 +  {
36963 +    { 0, 0, 0, 0 },
36964 +    { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } },
36965 +    & ifmt_shmrg_2_imm_bit5_s1_direct, { 0x12a00100 }
36966 +  },
36967 +/* asr.2 ${Dn},${s1-direct-addr},${s2} */
36968 +  {
36969 +    { 0, 0, 0, 0 },
36970 +    { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
36971 +    & ifmt_shmrg_2_dyn_reg_s1_direct, { 0x16a00100 }
36972 +  },
36973 +/* asr.2 ${Dn},#${s1-imm8},#${bit5} */
36974 +  {
36975 +    { 0, 0, 0, 0 },
36976 +    { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } },
36977 +    & ifmt_shmrg_2_imm_bit5_s1_immediate, { 0x12a00000 }
36978 +  },
36979 +/* asr.2 ${Dn},#${s1-imm8},${s2} */
36980 +  {
36981 +    { 0, 0, 0, 0 },
36982 +    { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
36983 +    & ifmt_shmrg_2_dyn_reg_s1_immediate, { 0x16a00000 }
36984 +  },
36985 +/* asr.2 ${Dn},(${s1-An},${s1-r}),#${bit5} */
36986 +  {
36987 +    { 0, 0, 0, 0 },
36988 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } },
36989 +    & ifmt_shmrg_2_imm_bit5_s1_indirect_with_index_2, { 0x12a00300 }
36990 +  },
36991 +/* asr.2 ${Dn},(${s1-An},${s1-r}),${s2} */
36992 +  {
36993 +    { 0, 0, 0, 0 },
36994 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
36995 +    & ifmt_shmrg_2_dyn_reg_s1_indirect_with_index_2, { 0x16a00300 }
36996 +  },
36997 +/* asr.2 ${Dn},${s1-imm7-2}(${s1-An}),#${bit5} */
36998 +  {
36999 +    { 0, 0, 0, 0 },
37000 +    { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
37001 +    & ifmt_shmrg_2_imm_bit5_s1_indirect_with_offset_2, { 0x12a00400 }
37002 +  },
37003 +/* asr.2 ${Dn},${s1-imm7-2}(${s1-An}),${s2} */
37004 +  {
37005 +    { 0, 0, 0, 0 },
37006 +    { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
37007 +    & ifmt_shmrg_2_dyn_reg_s1_indirect_with_offset_2, { 0x16a00400 }
37008 +  },
37009 +/* asr.2 ${Dn},(${s1-An}),#${bit5} */
37010 +  {
37011 +    { 0, 0, 0, 0 },
37012 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
37013 +    & ifmt_shmrg_2_imm_bit5_s1_indirect_2, { 0x12a00400 }
37014 +  },
37015 +/* asr.2 ${Dn},(${s1-An}),${s2} */
37016 +  {
37017 +    { 0, 0, 0, 0 },
37018 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
37019 +    & ifmt_shmrg_2_dyn_reg_s1_indirect_2, { 0x16a00400 }
37020 +  },
37021 +/* asr.2 ${Dn},(${s1-An})${s1-i4-2}++,#${bit5} */
37022 +  {
37023 +    { 0, 0, 0, 0 },
37024 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', '#', OP (BIT5), 0 } },
37025 +    & ifmt_shmrg_2_imm_bit5_s1_indirect_with_post_increment_2, { 0x12a00200 }
37026 +  },
37027 +/* asr.2 ${Dn},(${s1-An})${s1-i4-2}++,${s2} */
37028 +  {
37029 +    { 0, 0, 0, 0 },
37030 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } },
37031 +    & ifmt_shmrg_2_dyn_reg_s1_indirect_with_post_increment_2, { 0x16a00200 }
37032 +  },
37033 +/* asr.2 ${Dn},${s1-i4-2}(${s1-An})++,#${bit5} */
37034 +  {
37035 +    { 0, 0, 0, 0 },
37036 +    { { MNEM, ' ', OP (DN), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } },
37037 +    & ifmt_shmrg_2_imm_bit5_s1_indirect_with_pre_increment_2, { 0x12a00210 }
37038 +  },
37039 +/* asr.2 ${Dn},${s1-i4-2}(${s1-An})++,${s2} */
37040 +  {
37041 +    { 0, 0, 0, 0 },
37042 +    { { MNEM, ' ', OP (DN), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
37043 +    & ifmt_shmrg_2_dyn_reg_s1_indirect_with_pre_increment_2, { 0x16a00210 }
37044 +  },
37045 +/* lsl.2 ${Dn},${s1-direct-addr},#${bit5} */
37046 +  {
37047 +    { 0, 0, 0, 0 },
37048 +    { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } },
37049 +    & ifmt_shmrg_2_imm_bit5_s1_direct, { 0x12200100 }
37050 +  },
37051 +/* lsl.2 ${Dn},${s1-direct-addr},${s2} */
37052 +  {
37053 +    { 0, 0, 0, 0 },
37054 +    { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
37055 +    & ifmt_shmrg_2_dyn_reg_s1_direct, { 0x16200100 }
37056 +  },
37057 +/* lsl.2 ${Dn},#${s1-imm8},#${bit5} */
37058 +  {
37059 +    { 0, 0, 0, 0 },
37060 +    { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } },
37061 +    & ifmt_shmrg_2_imm_bit5_s1_immediate, { 0x12200000 }
37062 +  },
37063 +/* lsl.2 ${Dn},#${s1-imm8},${s2} */
37064 +  {
37065 +    { 0, 0, 0, 0 },
37066 +    { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
37067 +    & ifmt_shmrg_2_dyn_reg_s1_immediate, { 0x16200000 }
37068 +  },
37069 +/* lsl.2 ${Dn},(${s1-An},${s1-r}),#${bit5} */
37070 +  {
37071 +    { 0, 0, 0, 0 },
37072 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } },
37073 +    & ifmt_shmrg_2_imm_bit5_s1_indirect_with_index_2, { 0x12200300 }
37074 +  },
37075 +/* lsl.2 ${Dn},(${s1-An},${s1-r}),${s2} */
37076 +  {
37077 +    { 0, 0, 0, 0 },
37078 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
37079 +    & ifmt_shmrg_2_dyn_reg_s1_indirect_with_index_2, { 0x16200300 }
37080 +  },
37081 +/* lsl.2 ${Dn},${s1-imm7-2}(${s1-An}),#${bit5} */
37082 +  {
37083 +    { 0, 0, 0, 0 },
37084 +    { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
37085 +    & ifmt_shmrg_2_imm_bit5_s1_indirect_with_offset_2, { 0x12200400 }
37086 +  },
37087 +/* lsl.2 ${Dn},${s1-imm7-2}(${s1-An}),${s2} */
37088 +  {
37089 +    { 0, 0, 0, 0 },
37090 +    { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
37091 +    & ifmt_shmrg_2_dyn_reg_s1_indirect_with_offset_2, { 0x16200400 }
37092 +  },
37093 +/* lsl.2 ${Dn},(${s1-An}),#${bit5} */
37094 +  {
37095 +    { 0, 0, 0, 0 },
37096 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
37097 +    & ifmt_shmrg_2_imm_bit5_s1_indirect_2, { 0x12200400 }
37098 +  },
37099 +/* lsl.2 ${Dn},(${s1-An}),${s2} */
37100 +  {
37101 +    { 0, 0, 0, 0 },
37102 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
37103 +    & ifmt_shmrg_2_dyn_reg_s1_indirect_2, { 0x16200400 }
37104 +  },
37105 +/* lsl.2 ${Dn},(${s1-An})${s1-i4-2}++,#${bit5} */
37106 +  {
37107 +    { 0, 0, 0, 0 },
37108 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', '#', OP (BIT5), 0 } },
37109 +    & ifmt_shmrg_2_imm_bit5_s1_indirect_with_post_increment_2, { 0x12200200 }
37110 +  },
37111 +/* lsl.2 ${Dn},(${s1-An})${s1-i4-2}++,${s2} */
37112 +  {
37113 +    { 0, 0, 0, 0 },
37114 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } },
37115 +    & ifmt_shmrg_2_dyn_reg_s1_indirect_with_post_increment_2, { 0x16200200 }
37116 +  },
37117 +/* lsl.2 ${Dn},${s1-i4-2}(${s1-An})++,#${bit5} */
37118 +  {
37119 +    { 0, 0, 0, 0 },
37120 +    { { MNEM, ' ', OP (DN), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } },
37121 +    & ifmt_shmrg_2_imm_bit5_s1_indirect_with_pre_increment_2, { 0x12200210 }
37122 +  },
37123 +/* lsl.2 ${Dn},${s1-i4-2}(${s1-An})++,${s2} */
37124 +  {
37125 +    { 0, 0, 0, 0 },
37126 +    { { MNEM, ' ', OP (DN), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
37127 +    & ifmt_shmrg_2_dyn_reg_s1_indirect_with_pre_increment_2, { 0x16200210 }
37128 +  },
37129 +/* lsr.2 ${Dn},${s1-direct-addr},#${bit5} */
37130 +  {
37131 +    { 0, 0, 0, 0 },
37132 +    { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } },
37133 +    & ifmt_shmrg_2_imm_bit5_s1_direct, { 0x12600100 }
37134 +  },
37135 +/* lsr.2 ${Dn},${s1-direct-addr},${s2} */
37136 +  {
37137 +    { 0, 0, 0, 0 },
37138 +    { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
37139 +    & ifmt_shmrg_2_dyn_reg_s1_direct, { 0x16600100 }
37140 +  },
37141 +/* lsr.2 ${Dn},#${s1-imm8},#${bit5} */
37142 +  {
37143 +    { 0, 0, 0, 0 },
37144 +    { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } },
37145 +    & ifmt_shmrg_2_imm_bit5_s1_immediate, { 0x12600000 }
37146 +  },
37147 +/* lsr.2 ${Dn},#${s1-imm8},${s2} */
37148 +  {
37149 +    { 0, 0, 0, 0 },
37150 +    { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
37151 +    & ifmt_shmrg_2_dyn_reg_s1_immediate, { 0x16600000 }
37152 +  },
37153 +/* lsr.2 ${Dn},(${s1-An},${s1-r}),#${bit5} */
37154 +  {
37155 +    { 0, 0, 0, 0 },
37156 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } },
37157 +    & ifmt_shmrg_2_imm_bit5_s1_indirect_with_index_2, { 0x12600300 }
37158 +  },
37159 +/* lsr.2 ${Dn},(${s1-An},${s1-r}),${s2} */
37160 +  {
37161 +    { 0, 0, 0, 0 },
37162 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
37163 +    & ifmt_shmrg_2_dyn_reg_s1_indirect_with_index_2, { 0x16600300 }
37164 +  },
37165 +/* lsr.2 ${Dn},${s1-imm7-2}(${s1-An}),#${bit5} */
37166 +  {
37167 +    { 0, 0, 0, 0 },
37168 +    { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
37169 +    & ifmt_shmrg_2_imm_bit5_s1_indirect_with_offset_2, { 0x12600400 }
37170 +  },
37171 +/* lsr.2 ${Dn},${s1-imm7-2}(${s1-An}),${s2} */
37172 +  {
37173 +    { 0, 0, 0, 0 },
37174 +    { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
37175 +    & ifmt_shmrg_2_dyn_reg_s1_indirect_with_offset_2, { 0x16600400 }
37176 +  },
37177 +/* lsr.2 ${Dn},(${s1-An}),#${bit5} */
37178 +  {
37179 +    { 0, 0, 0, 0 },
37180 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
37181 +    & ifmt_shmrg_2_imm_bit5_s1_indirect_2, { 0x12600400 }
37182 +  },
37183 +/* lsr.2 ${Dn},(${s1-An}),${s2} */
37184 +  {
37185 +    { 0, 0, 0, 0 },
37186 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
37187 +    & ifmt_shmrg_2_dyn_reg_s1_indirect_2, { 0x16600400 }
37188 +  },
37189 +/* lsr.2 ${Dn},(${s1-An})${s1-i4-2}++,#${bit5} */
37190 +  {
37191 +    { 0, 0, 0, 0 },
37192 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', '#', OP (BIT5), 0 } },
37193 +    & ifmt_shmrg_2_imm_bit5_s1_indirect_with_post_increment_2, { 0x12600200 }
37194 +  },
37195 +/* lsr.2 ${Dn},(${s1-An})${s1-i4-2}++,${s2} */
37196 +  {
37197 +    { 0, 0, 0, 0 },
37198 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } },
37199 +    & ifmt_shmrg_2_dyn_reg_s1_indirect_with_post_increment_2, { 0x16600200 }
37200 +  },
37201 +/* lsr.2 ${Dn},${s1-i4-2}(${s1-An})++,#${bit5} */
37202 +  {
37203 +    { 0, 0, 0, 0 },
37204 +    { { MNEM, ' ', OP (DN), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } },
37205 +    & ifmt_shmrg_2_imm_bit5_s1_indirect_with_pre_increment_2, { 0x12600210 }
37206 +  },
37207 +/* lsr.2 ${Dn},${s1-i4-2}(${s1-An})++,${s2} */
37208 +  {
37209 +    { 0, 0, 0, 0 },
37210 +    { { MNEM, ' ', OP (DN), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
37211 +    & ifmt_shmrg_2_dyn_reg_s1_indirect_with_pre_increment_2, { 0x16600210 }
37212 +  },
37213 +/* asr.4 ${Dn},${s1-direct-addr},#${bit5} */
37214 +  {
37215 +    { 0, 0, 0, 0 },
37216 +    { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } },
37217 +    & ifmt_shmrg_2_imm_bit5_s1_direct, { 0x12800100 }
37218 +  },
37219 +/* asr.4 ${Dn},${s1-direct-addr},${s2} */
37220 +  {
37221 +    { 0, 0, 0, 0 },
37222 +    { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
37223 +    & ifmt_shmrg_2_dyn_reg_s1_direct, { 0x16800100 }
37224 +  },
37225 +/* asr.4 ${Dn},#${s1-imm8},#${bit5} */
37226 +  {
37227 +    { 0, 0, 0, 0 },
37228 +    { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } },
37229 +    & ifmt_shmrg_2_imm_bit5_s1_immediate, { 0x12800000 }
37230 +  },
37231 +/* asr.4 ${Dn},#${s1-imm8},${s2} */
37232 +  {
37233 +    { 0, 0, 0, 0 },
37234 +    { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
37235 +    & ifmt_shmrg_2_dyn_reg_s1_immediate, { 0x16800000 }
37236 +  },
37237 +/* asr.4 ${Dn},(${s1-An},${s1-r}),#${bit5} */
37238 +  {
37239 +    { 0, 0, 0, 0 },
37240 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } },
37241 +    & ifmt_asr_4_imm_bit5_s1_indirect_with_index_4, { 0x12800300 }
37242 +  },
37243 +/* asr.4 ${Dn},(${s1-An},${s1-r}),${s2} */
37244 +  {
37245 +    { 0, 0, 0, 0 },
37246 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
37247 +    & ifmt_asr_4_dyn_reg_s1_indirect_with_index_4, { 0x16800300 }
37248 +  },
37249 +/* asr.4 ${Dn},${s1-imm7-4}(${s1-An}),#${bit5} */
37250 +  {
37251 +    { 0, 0, 0, 0 },
37252 +    { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
37253 +    & ifmt_asr_4_imm_bit5_s1_indirect_with_offset_4, { 0x12800400 }
37254 +  },
37255 +/* asr.4 ${Dn},${s1-imm7-4}(${s1-An}),${s2} */
37256 +  {
37257 +    { 0, 0, 0, 0 },
37258 +    { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
37259 +    & ifmt_asr_4_dyn_reg_s1_indirect_with_offset_4, { 0x16800400 }
37260 +  },
37261 +/* asr.4 ${Dn},(${s1-An}),#${bit5} */
37262 +  {
37263 +    { 0, 0, 0, 0 },
37264 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
37265 +    & ifmt_asr_4_imm_bit5_s1_indirect_4, { 0x12800400 }
37266 +  },
37267 +/* asr.4 ${Dn},(${s1-An}),${s2} */
37268 +  {
37269 +    { 0, 0, 0, 0 },
37270 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
37271 +    & ifmt_asr_4_dyn_reg_s1_indirect_4, { 0x16800400 }
37272 +  },
37273 +/* asr.4 ${Dn},(${s1-An})${s1-i4-4}++,#${bit5} */
37274 +  {
37275 +    { 0, 0, 0, 0 },
37276 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', '#', OP (BIT5), 0 } },
37277 +    & ifmt_asr_4_imm_bit5_s1_indirect_with_post_increment_4, { 0x12800200 }
37278 +  },
37279 +/* asr.4 ${Dn},(${s1-An})${s1-i4-4}++,${s2} */
37280 +  {
37281 +    { 0, 0, 0, 0 },
37282 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
37283 +    & ifmt_asr_4_dyn_reg_s1_indirect_with_post_increment_4, { 0x16800200 }
37284 +  },
37285 +/* asr.4 ${Dn},${s1-i4-4}(${s1-An})++,#${bit5} */
37286 +  {
37287 +    { 0, 0, 0, 0 },
37288 +    { { MNEM, ' ', OP (DN), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } },
37289 +    & ifmt_asr_4_imm_bit5_s1_indirect_with_pre_increment_4, { 0x12800210 }
37290 +  },
37291 +/* asr.4 ${Dn},${s1-i4-4}(${s1-An})++,${s2} */
37292 +  {
37293 +    { 0, 0, 0, 0 },
37294 +    { { MNEM, ' ', OP (DN), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
37295 +    & ifmt_asr_4_dyn_reg_s1_indirect_with_pre_increment_4, { 0x16800210 }
37296 +  },
37297 +/* lsl.4 ${Dn},${s1-direct-addr},#${bit5} */
37298 +  {
37299 +    { 0, 0, 0, 0 },
37300 +    { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } },
37301 +    & ifmt_shmrg_2_imm_bit5_s1_direct, { 0x12000100 }
37302 +  },
37303 +/* lsl.4 ${Dn},${s1-direct-addr},${s2} */
37304 +  {
37305 +    { 0, 0, 0, 0 },
37306 +    { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
37307 +    & ifmt_shmrg_2_dyn_reg_s1_direct, { 0x16000100 }
37308 +  },
37309 +/* lsl.4 ${Dn},#${s1-imm8},#${bit5} */
37310 +  {
37311 +    { 0, 0, 0, 0 },
37312 +    { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } },
37313 +    & ifmt_shmrg_2_imm_bit5_s1_immediate, { 0x12000000 }
37314 +  },
37315 +/* lsl.4 ${Dn},#${s1-imm8},${s2} */
37316 +  {
37317 +    { 0, 0, 0, 0 },
37318 +    { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
37319 +    & ifmt_shmrg_2_dyn_reg_s1_immediate, { 0x16000000 }
37320 +  },
37321 +/* lsl.4 ${Dn},(${s1-An},${s1-r}),#${bit5} */
37322 +  {
37323 +    { 0, 0, 0, 0 },
37324 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } },
37325 +    & ifmt_asr_4_imm_bit5_s1_indirect_with_index_4, { 0x12000300 }
37326 +  },
37327 +/* lsl.4 ${Dn},(${s1-An},${s1-r}),${s2} */
37328 +  {
37329 +    { 0, 0, 0, 0 },
37330 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
37331 +    & ifmt_asr_4_dyn_reg_s1_indirect_with_index_4, { 0x16000300 }
37332 +  },
37333 +/* lsl.4 ${Dn},${s1-imm7-4}(${s1-An}),#${bit5} */
37334 +  {
37335 +    { 0, 0, 0, 0 },
37336 +    { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
37337 +    & ifmt_asr_4_imm_bit5_s1_indirect_with_offset_4, { 0x12000400 }
37338 +  },
37339 +/* lsl.4 ${Dn},${s1-imm7-4}(${s1-An}),${s2} */
37340 +  {
37341 +    { 0, 0, 0, 0 },
37342 +    { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
37343 +    & ifmt_asr_4_dyn_reg_s1_indirect_with_offset_4, { 0x16000400 }
37344 +  },
37345 +/* lsl.4 ${Dn},(${s1-An}),#${bit5} */
37346 +  {
37347 +    { 0, 0, 0, 0 },
37348 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
37349 +    & ifmt_asr_4_imm_bit5_s1_indirect_4, { 0x12000400 }
37350 +  },
37351 +/* lsl.4 ${Dn},(${s1-An}),${s2} */
37352 +  {
37353 +    { 0, 0, 0, 0 },
37354 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
37355 +    & ifmt_asr_4_dyn_reg_s1_indirect_4, { 0x16000400 }
37356 +  },
37357 +/* lsl.4 ${Dn},(${s1-An})${s1-i4-4}++,#${bit5} */
37358 +  {
37359 +    { 0, 0, 0, 0 },
37360 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', '#', OP (BIT5), 0 } },
37361 +    & ifmt_asr_4_imm_bit5_s1_indirect_with_post_increment_4, { 0x12000200 }
37362 +  },
37363 +/* lsl.4 ${Dn},(${s1-An})${s1-i4-4}++,${s2} */
37364 +  {
37365 +    { 0, 0, 0, 0 },
37366 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
37367 +    & ifmt_asr_4_dyn_reg_s1_indirect_with_post_increment_4, { 0x16000200 }
37368 +  },
37369 +/* lsl.4 ${Dn},${s1-i4-4}(${s1-An})++,#${bit5} */
37370 +  {
37371 +    { 0, 0, 0, 0 },
37372 +    { { MNEM, ' ', OP (DN), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } },
37373 +    & ifmt_asr_4_imm_bit5_s1_indirect_with_pre_increment_4, { 0x12000210 }
37374 +  },
37375 +/* lsl.4 ${Dn},${s1-i4-4}(${s1-An})++,${s2} */
37376 +  {
37377 +    { 0, 0, 0, 0 },
37378 +    { { MNEM, ' ', OP (DN), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
37379 +    & ifmt_asr_4_dyn_reg_s1_indirect_with_pre_increment_4, { 0x16000210 }
37380 +  },
37381 +/* lsr.4 ${Dn},${s1-direct-addr},#${bit5} */
37382 +  {
37383 +    { 0, 0, 0, 0 },
37384 +    { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } },
37385 +    & ifmt_shmrg_2_imm_bit5_s1_direct, { 0x12400100 }
37386 +  },
37387 +/* lsr.4 ${Dn},${s1-direct-addr},${s2} */
37388 +  {
37389 +    { 0, 0, 0, 0 },
37390 +    { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
37391 +    & ifmt_shmrg_2_dyn_reg_s1_direct, { 0x16400100 }
37392 +  },
37393 +/* lsr.4 ${Dn},#${s1-imm8},#${bit5} */
37394 +  {
37395 +    { 0, 0, 0, 0 },
37396 +    { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } },
37397 +    & ifmt_shmrg_2_imm_bit5_s1_immediate, { 0x12400000 }
37398 +  },
37399 +/* lsr.4 ${Dn},#${s1-imm8},${s2} */
37400 +  {
37401 +    { 0, 0, 0, 0 },
37402 +    { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
37403 +    & ifmt_shmrg_2_dyn_reg_s1_immediate, { 0x16400000 }
37404 +  },
37405 +/* lsr.4 ${Dn},(${s1-An},${s1-r}),#${bit5} */
37406 +  {
37407 +    { 0, 0, 0, 0 },
37408 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } },
37409 +    & ifmt_asr_4_imm_bit5_s1_indirect_with_index_4, { 0x12400300 }
37410 +  },
37411 +/* lsr.4 ${Dn},(${s1-An},${s1-r}),${s2} */
37412 +  {
37413 +    { 0, 0, 0, 0 },
37414 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
37415 +    & ifmt_asr_4_dyn_reg_s1_indirect_with_index_4, { 0x16400300 }
37416 +  },
37417 +/* lsr.4 ${Dn},${s1-imm7-4}(${s1-An}),#${bit5} */
37418 +  {
37419 +    { 0, 0, 0, 0 },
37420 +    { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
37421 +    & ifmt_asr_4_imm_bit5_s1_indirect_with_offset_4, { 0x12400400 }
37422 +  },
37423 +/* lsr.4 ${Dn},${s1-imm7-4}(${s1-An}),${s2} */
37424 +  {
37425 +    { 0, 0, 0, 0 },
37426 +    { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
37427 +    & ifmt_asr_4_dyn_reg_s1_indirect_with_offset_4, { 0x16400400 }
37428 +  },
37429 +/* lsr.4 ${Dn},(${s1-An}),#${bit5} */
37430 +  {
37431 +    { 0, 0, 0, 0 },
37432 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
37433 +    & ifmt_asr_4_imm_bit5_s1_indirect_4, { 0x12400400 }
37434 +  },
37435 +/* lsr.4 ${Dn},(${s1-An}),${s2} */
37436 +  {
37437 +    { 0, 0, 0, 0 },
37438 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
37439 +    & ifmt_asr_4_dyn_reg_s1_indirect_4, { 0x16400400 }
37440 +  },
37441 +/* lsr.4 ${Dn},(${s1-An})${s1-i4-4}++,#${bit5} */
37442 +  {
37443 +    { 0, 0, 0, 0 },
37444 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', '#', OP (BIT5), 0 } },
37445 +    & ifmt_asr_4_imm_bit5_s1_indirect_with_post_increment_4, { 0x12400200 }
37446 +  },
37447 +/* lsr.4 ${Dn},(${s1-An})${s1-i4-4}++,${s2} */
37448 +  {
37449 +    { 0, 0, 0, 0 },
37450 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
37451 +    & ifmt_asr_4_dyn_reg_s1_indirect_with_post_increment_4, { 0x16400200 }
37452 +  },
37453 +/* lsr.4 ${Dn},${s1-i4-4}(${s1-An})++,#${bit5} */
37454 +  {
37455 +    { 0, 0, 0, 0 },
37456 +    { { MNEM, ' ', OP (DN), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } },
37457 +    & ifmt_asr_4_imm_bit5_s1_indirect_with_pre_increment_4, { 0x12400210 }
37458 +  },
37459 +/* lsr.4 ${Dn},${s1-i4-4}(${s1-An})++,${s2} */
37460 +  {
37461 +    { 0, 0, 0, 0 },
37462 +    { { MNEM, ' ', OP (DN), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
37463 +    & ifmt_asr_4_dyn_reg_s1_indirect_with_pre_increment_4, { 0x16400210 }
37464 +  },
37465 +/* mac ${s1-direct-addr},${dsp-S2-data-reg} */
37466 +  {
37467 +    { 0, 0, 0, 0 },
37468 +    { { MNEM, ' ', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_DATA_REG), 0 } },
37469 +    & ifmt_compatibility_mac_s1_direct_dsp_src2_data_reg, { 0x34200100 }
37470 +  },
37471 +/* mac #${s1-imm8},${dsp-S2-data-reg} */
37472 +  {
37473 +    { 0, 0, 0, 0 },
37474 +    { { MNEM, ' ', '#', OP (S1_IMM8), ',', OP (DSP_S2_DATA_REG), 0 } },
37475 +    & ifmt_compatibility_mac_s1_immediate_dsp_src2_data_reg, { 0x34200000 }
37476 +  },
37477 +/* mac (${s1-An},${s1-r}),${dsp-S2-data-reg} */
37478 +  {
37479 +    { 0, 0, 0, 0 },
37480 +    { { MNEM, ' ', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_DATA_REG), 0 } },
37481 +    & ifmt_compatibility_mac_s1_indirect_with_index_2_dsp_src2_data_reg, { 0x34200300 }
37482 +  },
37483 +/* mac ${s1-imm7-2}(${s1-An}),${dsp-S2-data-reg} */
37484 +  {
37485 +    { 0, 0, 0, 0 },
37486 +    { { MNEM, ' ', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG), 0 } },
37487 +    & ifmt_compatibility_mac_s1_indirect_with_offset_2_dsp_src2_data_reg, { 0x34200400 }
37488 +  },
37489 +/* mac (${s1-An}),${dsp-S2-data-reg} */
37490 +  {
37491 +    { 0, 0, 0, 0 },
37492 +    { { MNEM, ' ', '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG), 0 } },
37493 +    & ifmt_compatibility_mac_s1_indirect_2_dsp_src2_data_reg, { 0x34200400 }
37494 +  },
37495 +/* mac (${s1-An})${s1-i4-2}++,${dsp-S2-data-reg} */
37496 +  {
37497 +    { 0, 0, 0, 0 },
37498 +    { { MNEM, ' ', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (DSP_S2_DATA_REG), 0 } },
37499 +    & ifmt_compatibility_mac_s1_indirect_with_post_increment_2_dsp_src2_data_reg, { 0x34200200 }
37500 +  },
37501 +/* mac ${s1-i4-2}(${s1-An})++,${dsp-S2-data-reg} */
37502 +  {
37503 +    { 0, 0, 0, 0 },
37504 +    { { MNEM, ' ', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_DATA_REG), 0 } },
37505 +    & ifmt_compatibility_mac_s1_indirect_with_pre_increment_2_dsp_src2_data_reg, { 0x34200210 }
37506 +  },
37507 +/* mac ${s1-direct-addr},#${bit5} */
37508 +  {
37509 +    { 0, 0, 0, 0 },
37510 +    { { MNEM, ' ', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } },
37511 +    & ifmt_compatibility_mac_s1_direct_dsp_imm_bit5, { 0x30200100 }
37512 +  },
37513 +/* mac #${s1-imm8},#${bit5} */
37514 +  {
37515 +    { 0, 0, 0, 0 },
37516 +    { { MNEM, ' ', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } },
37517 +    & ifmt_compatibility_mac_s1_immediate_dsp_imm_bit5, { 0x30200000 }
37518 +  },
37519 +/* mac (${s1-An},${s1-r}),#${bit5} */
37520 +  {
37521 +    { 0, 0, 0, 0 },
37522 +    { { MNEM, ' ', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } },
37523 +    & ifmt_compatibility_mac_s1_indirect_with_index_2_dsp_imm_bit5, { 0x30200300 }
37524 +  },
37525 +/* mac ${s1-imm7-2}(${s1-An}),#${bit5} */
37526 +  {
37527 +    { 0, 0, 0, 0 },
37528 +    { { MNEM, ' ', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
37529 +    & ifmt_compatibility_mac_s1_indirect_with_offset_2_dsp_imm_bit5, { 0x30200400 }
37530 +  },
37531 +/* mac (${s1-An}),#${bit5} */
37532 +  {
37533 +    { 0, 0, 0, 0 },
37534 +    { { MNEM, ' ', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
37535 +    & ifmt_compatibility_mac_s1_indirect_2_dsp_imm_bit5, { 0x30200400 }
37536 +  },
37537 +/* mac (${s1-An})${s1-i4-2}++,#${bit5} */
37538 +  {
37539 +    { 0, 0, 0, 0 },
37540 +    { { MNEM, ' ', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', '#', OP (BIT5), 0 } },
37541 +    & ifmt_compatibility_mac_s1_indirect_with_post_increment_2_dsp_imm_bit5, { 0x30200200 }
37542 +  },
37543 +/* mac ${s1-i4-2}(${s1-An})++,#${bit5} */
37544 +  {
37545 +    { 0, 0, 0, 0 },
37546 +    { { MNEM, ' ', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } },
37547 +    & ifmt_compatibility_mac_s1_indirect_with_pre_increment_2_dsp_imm_bit5, { 0x30200210 }
37548 +  },
37549 +/* mac ${s1-direct-addr},#${bit5} */
37550 +  {
37551 +    { 0, 0, 0, 0 },
37552 +    { { MNEM, ' ', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } },
37553 +    & ifmt_btst_s1_direct_imm_bit5, { 0x11200100 }
37554 +  },
37555 +/* mac #${s1-imm8},#${bit5} */
37556 +  {
37557 +    { 0, 0, 0, 0 },
37558 +    { { MNEM, ' ', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } },
37559 +    & ifmt_btst_s1_immediate_imm_bit5, { 0x11200000 }
37560 +  },
37561 +/* mac (${s1-An},${s1-r}),#${bit5} */
37562 +  {
37563 +    { 0, 0, 0, 0 },
37564 +    { { MNEM, ' ', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } },
37565 +    & ifmt_mac_s1_indirect_with_index_2_imm_bit5, { 0x11200300 }
37566 +  },
37567 +/* mac ${s1-imm7-2}(${s1-An}),#${bit5} */
37568 +  {
37569 +    { 0, 0, 0, 0 },
37570 +    { { MNEM, ' ', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
37571 +    & ifmt_mac_s1_indirect_with_offset_2_imm_bit5, { 0x11200400 }
37572 +  },
37573 +/* mac (${s1-An}),#${bit5} */
37574 +  {
37575 +    { 0, 0, 0, 0 },
37576 +    { { MNEM, ' ', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
37577 +    & ifmt_mac_s1_indirect_2_imm_bit5, { 0x11200400 }
37578 +  },
37579 +/* mac (${s1-An})${s1-i4-2}++,#${bit5} */
37580 +  {
37581 +    { 0, 0, 0, 0 },
37582 +    { { MNEM, ' ', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', '#', OP (BIT5), 0 } },
37583 +    & ifmt_mac_s1_indirect_with_post_increment_2_imm_bit5, { 0x11200200 }
37584 +  },
37585 +/* mac ${s1-i4-2}(${s1-An})++,#${bit5} */
37586 +  {
37587 +    { 0, 0, 0, 0 },
37588 +    { { MNEM, ' ', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } },
37589 +    & ifmt_mac_s1_indirect_with_pre_increment_2_imm_bit5, { 0x11200210 }
37590 +  },
37591 +/* mac ${s1-direct-addr},${s2} */
37592 +  {
37593 +    { 0, 0, 0, 0 },
37594 +    { { MNEM, ' ', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
37595 +    & ifmt_btst_s1_direct_dyn_reg, { 0x15200100 }
37596 +  },
37597 +/* mac #${s1-imm8},${s2} */
37598 +  {
37599 +    { 0, 0, 0, 0 },
37600 +    { { MNEM, ' ', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
37601 +    & ifmt_btst_s1_immediate_dyn_reg, { 0x15200000 }
37602 +  },
37603 +/* mac (${s1-An},${s1-r}),${s2} */
37604 +  {
37605 +    { 0, 0, 0, 0 },
37606 +    { { MNEM, ' ', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
37607 +    & ifmt_mac_s1_indirect_with_index_2_dyn_reg, { 0x15200300 }
37608 +  },
37609 +/* mac ${s1-imm7-2}(${s1-An}),${s2} */
37610 +  {
37611 +    { 0, 0, 0, 0 },
37612 +    { { MNEM, ' ', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
37613 +    & ifmt_mac_s1_indirect_with_offset_2_dyn_reg, { 0x15200400 }
37614 +  },
37615 +/* mac (${s1-An}),${s2} */
37616 +  {
37617 +    { 0, 0, 0, 0 },
37618 +    { { MNEM, ' ', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
37619 +    & ifmt_mac_s1_indirect_2_dyn_reg, { 0x15200400 }
37620 +  },
37621 +/* mac (${s1-An})${s1-i4-2}++,${s2} */
37622 +  {
37623 +    { 0, 0, 0, 0 },
37624 +    { { MNEM, ' ', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } },
37625 +    & ifmt_mac_s1_indirect_with_post_increment_2_dyn_reg, { 0x15200200 }
37626 +  },
37627 +/* mac ${s1-i4-2}(${s1-An})++,${s2} */
37628 +  {
37629 +    { 0, 0, 0, 0 },
37630 +    { { MNEM, ' ', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
37631 +    & ifmt_mac_s1_indirect_with_pre_increment_2_dyn_reg, { 0x15200210 }
37632 +  },
37633 +/* mulf ${s1-direct-addr},${dsp-S2-data-reg} */
37634 +  {
37635 +    { 0, 0, 0, 0 },
37636 +    { { MNEM, ' ', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_DATA_REG), 0 } },
37637 +    & ifmt_compatibility_mac_s1_direct_dsp_src2_data_reg, { 0x34800100 }
37638 +  },
37639 +/* mulf #${s1-imm8},${dsp-S2-data-reg} */
37640 +  {
37641 +    { 0, 0, 0, 0 },
37642 +    { { MNEM, ' ', '#', OP (S1_IMM8), ',', OP (DSP_S2_DATA_REG), 0 } },
37643 +    & ifmt_compatibility_mac_s1_immediate_dsp_src2_data_reg, { 0x34800000 }
37644 +  },
37645 +/* mulf (${s1-An},${s1-r}),${dsp-S2-data-reg} */
37646 +  {
37647 +    { 0, 0, 0, 0 },
37648 +    { { MNEM, ' ', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_DATA_REG), 0 } },
37649 +    & ifmt_compatibility_mac_s1_indirect_with_index_2_dsp_src2_data_reg, { 0x34800300 }
37650 +  },
37651 +/* mulf ${s1-imm7-2}(${s1-An}),${dsp-S2-data-reg} */
37652 +  {
37653 +    { 0, 0, 0, 0 },
37654 +    { { MNEM, ' ', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG), 0 } },
37655 +    & ifmt_compatibility_mac_s1_indirect_with_offset_2_dsp_src2_data_reg, { 0x34800400 }
37656 +  },
37657 +/* mulf (${s1-An}),${dsp-S2-data-reg} */
37658 +  {
37659 +    { 0, 0, 0, 0 },
37660 +    { { MNEM, ' ', '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG), 0 } },
37661 +    & ifmt_compatibility_mac_s1_indirect_2_dsp_src2_data_reg, { 0x34800400 }
37662 +  },
37663 +/* mulf (${s1-An})${s1-i4-2}++,${dsp-S2-data-reg} */
37664 +  {
37665 +    { 0, 0, 0, 0 },
37666 +    { { MNEM, ' ', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (DSP_S2_DATA_REG), 0 } },
37667 +    & ifmt_compatibility_mac_s1_indirect_with_post_increment_2_dsp_src2_data_reg, { 0x34800200 }
37668 +  },
37669 +/* mulf ${s1-i4-2}(${s1-An})++,${dsp-S2-data-reg} */
37670 +  {
37671 +    { 0, 0, 0, 0 },
37672 +    { { MNEM, ' ', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_DATA_REG), 0 } },
37673 +    & ifmt_compatibility_mac_s1_indirect_with_pre_increment_2_dsp_src2_data_reg, { 0x34800210 }
37674 +  },
37675 +/* mulf ${s1-direct-addr},#${bit5} */
37676 +  {
37677 +    { 0, 0, 0, 0 },
37678 +    { { MNEM, ' ', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } },
37679 +    & ifmt_compatibility_mac_s1_direct_dsp_imm_bit5, { 0x30800100 }
37680 +  },
37681 +/* mulf #${s1-imm8},#${bit5} */
37682 +  {
37683 +    { 0, 0, 0, 0 },
37684 +    { { MNEM, ' ', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } },
37685 +    & ifmt_compatibility_mac_s1_immediate_dsp_imm_bit5, { 0x30800000 }
37686 +  },
37687 +/* mulf (${s1-An},${s1-r}),#${bit5} */
37688 +  {
37689 +    { 0, 0, 0, 0 },
37690 +    { { MNEM, ' ', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } },
37691 +    & ifmt_compatibility_mac_s1_indirect_with_index_2_dsp_imm_bit5, { 0x30800300 }
37692 +  },
37693 +/* mulf ${s1-imm7-2}(${s1-An}),#${bit5} */
37694 +  {
37695 +    { 0, 0, 0, 0 },
37696 +    { { MNEM, ' ', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
37697 +    & ifmt_compatibility_mac_s1_indirect_with_offset_2_dsp_imm_bit5, { 0x30800400 }
37698 +  },
37699 +/* mulf (${s1-An}),#${bit5} */
37700 +  {
37701 +    { 0, 0, 0, 0 },
37702 +    { { MNEM, ' ', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
37703 +    & ifmt_compatibility_mac_s1_indirect_2_dsp_imm_bit5, { 0x30800400 }
37704 +  },
37705 +/* mulf (${s1-An})${s1-i4-2}++,#${bit5} */
37706 +  {
37707 +    { 0, 0, 0, 0 },
37708 +    { { MNEM, ' ', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', '#', OP (BIT5), 0 } },
37709 +    & ifmt_compatibility_mac_s1_indirect_with_post_increment_2_dsp_imm_bit5, { 0x30800200 }
37710 +  },
37711 +/* mulf ${s1-i4-2}(${s1-An})++,#${bit5} */
37712 +  {
37713 +    { 0, 0, 0, 0 },
37714 +    { { MNEM, ' ', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } },
37715 +    & ifmt_compatibility_mac_s1_indirect_with_pre_increment_2_dsp_imm_bit5, { 0x30800210 }
37716 +  },
37717 +/* mulf ${s1-direct-addr},#${bit5} */
37718 +  {
37719 +    { 0, 0, 0, 0 },
37720 +    { { MNEM, ' ', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } },
37721 +    & ifmt_btst_s1_direct_imm_bit5, { 0x10a00100 }
37722 +  },
37723 +/* mulf #${s1-imm8},#${bit5} */
37724 +  {
37725 +    { 0, 0, 0, 0 },
37726 +    { { MNEM, ' ', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } },
37727 +    & ifmt_btst_s1_immediate_imm_bit5, { 0x10a00000 }
37728 +  },
37729 +/* mulf (${s1-An},${s1-r}),#${bit5} */
37730 +  {
37731 +    { 0, 0, 0, 0 },
37732 +    { { MNEM, ' ', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } },
37733 +    & ifmt_mac_s1_indirect_with_index_2_imm_bit5, { 0x10a00300 }
37734 +  },
37735 +/* mulf ${s1-imm7-2}(${s1-An}),#${bit5} */
37736 +  {
37737 +    { 0, 0, 0, 0 },
37738 +    { { MNEM, ' ', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
37739 +    & ifmt_mac_s1_indirect_with_offset_2_imm_bit5, { 0x10a00400 }
37740 +  },
37741 +/* mulf (${s1-An}),#${bit5} */
37742 +  {
37743 +    { 0, 0, 0, 0 },
37744 +    { { MNEM, ' ', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
37745 +    & ifmt_mac_s1_indirect_2_imm_bit5, { 0x10a00400 }
37746 +  },
37747 +/* mulf (${s1-An})${s1-i4-2}++,#${bit5} */
37748 +  {
37749 +    { 0, 0, 0, 0 },
37750 +    { { MNEM, ' ', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', '#', OP (BIT5), 0 } },
37751 +    & ifmt_mac_s1_indirect_with_post_increment_2_imm_bit5, { 0x10a00200 }
37752 +  },
37753 +/* mulf ${s1-i4-2}(${s1-An})++,#${bit5} */
37754 +  {
37755 +    { 0, 0, 0, 0 },
37756 +    { { MNEM, ' ', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } },
37757 +    & ifmt_mac_s1_indirect_with_pre_increment_2_imm_bit5, { 0x10a00210 }
37758 +  },
37759 +/* mulf ${s1-direct-addr},${s2} */
37760 +  {
37761 +    { 0, 0, 0, 0 },
37762 +    { { MNEM, ' ', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
37763 +    & ifmt_btst_s1_direct_dyn_reg, { 0x14a00100 }
37764 +  },
37765 +/* mulf #${s1-imm8},${s2} */
37766 +  {
37767 +    { 0, 0, 0, 0 },
37768 +    { { MNEM, ' ', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
37769 +    & ifmt_btst_s1_immediate_dyn_reg, { 0x14a00000 }
37770 +  },
37771 +/* mulf (${s1-An},${s1-r}),${s2} */
37772 +  {
37773 +    { 0, 0, 0, 0 },
37774 +    { { MNEM, ' ', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
37775 +    & ifmt_mac_s1_indirect_with_index_2_dyn_reg, { 0x14a00300 }
37776 +  },
37777 +/* mulf ${s1-imm7-2}(${s1-An}),${s2} */
37778 +  {
37779 +    { 0, 0, 0, 0 },
37780 +    { { MNEM, ' ', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
37781 +    & ifmt_mac_s1_indirect_with_offset_2_dyn_reg, { 0x14a00400 }
37782 +  },
37783 +/* mulf (${s1-An}),${s2} */
37784 +  {
37785 +    { 0, 0, 0, 0 },
37786 +    { { MNEM, ' ', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
37787 +    & ifmt_mac_s1_indirect_2_dyn_reg, { 0x14a00400 }
37788 +  },
37789 +/* mulf (${s1-An})${s1-i4-2}++,${s2} */
37790 +  {
37791 +    { 0, 0, 0, 0 },
37792 +    { { MNEM, ' ', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } },
37793 +    & ifmt_mac_s1_indirect_with_post_increment_2_dyn_reg, { 0x14a00200 }
37794 +  },
37795 +/* mulf ${s1-i4-2}(${s1-An})++,${s2} */
37796 +  {
37797 +    { 0, 0, 0, 0 },
37798 +    { { MNEM, ' ', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
37799 +    & ifmt_mac_s1_indirect_with_pre_increment_2_dyn_reg, { 0x14a00210 }
37800 +  },
37801 +/* mulu ${s1-direct-addr},${dsp-S2-data-reg} */
37802 +  {
37803 +    { 0, 0, 0, 0 },
37804 +    { { MNEM, ' ', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_DATA_REG), 0 } },
37805 +    & ifmt_compatibility_mac_s1_direct_dsp_src2_data_reg, { 0x34400100 }
37806 +  },
37807 +/* mulu #${s1-imm8},${dsp-S2-data-reg} */
37808 +  {
37809 +    { 0, 0, 0, 0 },
37810 +    { { MNEM, ' ', '#', OP (S1_IMM8), ',', OP (DSP_S2_DATA_REG), 0 } },
37811 +    & ifmt_compatibility_mac_s1_immediate_dsp_src2_data_reg, { 0x34400000 }
37812 +  },
37813 +/* mulu (${s1-An},${s1-r}),${dsp-S2-data-reg} */
37814 +  {
37815 +    { 0, 0, 0, 0 },
37816 +    { { MNEM, ' ', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_DATA_REG), 0 } },
37817 +    & ifmt_compatibility_mac_s1_indirect_with_index_2_dsp_src2_data_reg, { 0x34400300 }
37818 +  },
37819 +/* mulu ${s1-imm7-2}(${s1-An}),${dsp-S2-data-reg} */
37820 +  {
37821 +    { 0, 0, 0, 0 },
37822 +    { { MNEM, ' ', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG), 0 } },
37823 +    & ifmt_compatibility_mac_s1_indirect_with_offset_2_dsp_src2_data_reg, { 0x34400400 }
37824 +  },
37825 +/* mulu (${s1-An}),${dsp-S2-data-reg} */
37826 +  {
37827 +    { 0, 0, 0, 0 },
37828 +    { { MNEM, ' ', '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG), 0 } },
37829 +    & ifmt_compatibility_mac_s1_indirect_2_dsp_src2_data_reg, { 0x34400400 }
37830 +  },
37831 +/* mulu (${s1-An})${s1-i4-2}++,${dsp-S2-data-reg} */
37832 +  {
37833 +    { 0, 0, 0, 0 },
37834 +    { { MNEM, ' ', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (DSP_S2_DATA_REG), 0 } },
37835 +    & ifmt_compatibility_mac_s1_indirect_with_post_increment_2_dsp_src2_data_reg, { 0x34400200 }
37836 +  },
37837 +/* mulu ${s1-i4-2}(${s1-An})++,${dsp-S2-data-reg} */
37838 +  {
37839 +    { 0, 0, 0, 0 },
37840 +    { { MNEM, ' ', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_DATA_REG), 0 } },
37841 +    & ifmt_compatibility_mac_s1_indirect_with_pre_increment_2_dsp_src2_data_reg, { 0x34400210 }
37842 +  },
37843 +/* mulu ${s1-direct-addr},#${bit5} */
37844 +  {
37845 +    { 0, 0, 0, 0 },
37846 +    { { MNEM, ' ', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } },
37847 +    & ifmt_compatibility_mac_s1_direct_dsp_imm_bit5, { 0x30400100 }
37848 +  },
37849 +/* mulu #${s1-imm8},#${bit5} */
37850 +  {
37851 +    { 0, 0, 0, 0 },
37852 +    { { MNEM, ' ', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } },
37853 +    & ifmt_compatibility_mac_s1_immediate_dsp_imm_bit5, { 0x30400000 }
37854 +  },
37855 +/* mulu (${s1-An},${s1-r}),#${bit5} */
37856 +  {
37857 +    { 0, 0, 0, 0 },
37858 +    { { MNEM, ' ', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } },
37859 +    & ifmt_compatibility_mac_s1_indirect_with_index_2_dsp_imm_bit5, { 0x30400300 }
37860 +  },
37861 +/* mulu ${s1-imm7-2}(${s1-An}),#${bit5} */
37862 +  {
37863 +    { 0, 0, 0, 0 },
37864 +    { { MNEM, ' ', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
37865 +    & ifmt_compatibility_mac_s1_indirect_with_offset_2_dsp_imm_bit5, { 0x30400400 }
37866 +  },
37867 +/* mulu (${s1-An}),#${bit5} */
37868 +  {
37869 +    { 0, 0, 0, 0 },
37870 +    { { MNEM, ' ', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
37871 +    & ifmt_compatibility_mac_s1_indirect_2_dsp_imm_bit5, { 0x30400400 }
37872 +  },
37873 +/* mulu (${s1-An})${s1-i4-2}++,#${bit5} */
37874 +  {
37875 +    { 0, 0, 0, 0 },
37876 +    { { MNEM, ' ', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', '#', OP (BIT5), 0 } },
37877 +    & ifmt_compatibility_mac_s1_indirect_with_post_increment_2_dsp_imm_bit5, { 0x30400200 }
37878 +  },
37879 +/* mulu ${s1-i4-2}(${s1-An})++,#${bit5} */
37880 +  {
37881 +    { 0, 0, 0, 0 },
37882 +    { { MNEM, ' ', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } },
37883 +    & ifmt_compatibility_mac_s1_indirect_with_pre_increment_2_dsp_imm_bit5, { 0x30400210 }
37884 +  },
37885 +/* mulu ${s1-direct-addr},#${bit5} */
37886 +  {
37887 +    { 0, 0, 0, 0 },
37888 +    { { MNEM, ' ', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } },
37889 +    & ifmt_btst_s1_direct_imm_bit5, { 0x10600100 }
37890 +  },
37891 +/* mulu #${s1-imm8},#${bit5} */
37892 +  {
37893 +    { 0, 0, 0, 0 },
37894 +    { { MNEM, ' ', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } },
37895 +    & ifmt_btst_s1_immediate_imm_bit5, { 0x10600000 }
37896 +  },
37897 +/* mulu (${s1-An},${s1-r}),#${bit5} */
37898 +  {
37899 +    { 0, 0, 0, 0 },
37900 +    { { MNEM, ' ', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } },
37901 +    & ifmt_mac_s1_indirect_with_index_2_imm_bit5, { 0x10600300 }
37902 +  },
37903 +/* mulu ${s1-imm7-2}(${s1-An}),#${bit5} */
37904 +  {
37905 +    { 0, 0, 0, 0 },
37906 +    { { MNEM, ' ', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
37907 +    & ifmt_mac_s1_indirect_with_offset_2_imm_bit5, { 0x10600400 }
37908 +  },
37909 +/* mulu (${s1-An}),#${bit5} */
37910 +  {
37911 +    { 0, 0, 0, 0 },
37912 +    { { MNEM, ' ', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
37913 +    & ifmt_mac_s1_indirect_2_imm_bit5, { 0x10600400 }
37914 +  },
37915 +/* mulu (${s1-An})${s1-i4-2}++,#${bit5} */
37916 +  {
37917 +    { 0, 0, 0, 0 },
37918 +    { { MNEM, ' ', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', '#', OP (BIT5), 0 } },
37919 +    & ifmt_mac_s1_indirect_with_post_increment_2_imm_bit5, { 0x10600200 }
37920 +  },
37921 +/* mulu ${s1-i4-2}(${s1-An})++,#${bit5} */
37922 +  {
37923 +    { 0, 0, 0, 0 },
37924 +    { { MNEM, ' ', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } },
37925 +    & ifmt_mac_s1_indirect_with_pre_increment_2_imm_bit5, { 0x10600210 }
37926 +  },
37927 +/* mulu ${s1-direct-addr},${s2} */
37928 +  {
37929 +    { 0, 0, 0, 0 },
37930 +    { { MNEM, ' ', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
37931 +    & ifmt_btst_s1_direct_dyn_reg, { 0x14600100 }
37932 +  },
37933 +/* mulu #${s1-imm8},${s2} */
37934 +  {
37935 +    { 0, 0, 0, 0 },
37936 +    { { MNEM, ' ', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
37937 +    & ifmt_btst_s1_immediate_dyn_reg, { 0x14600000 }
37938 +  },
37939 +/* mulu (${s1-An},${s1-r}),${s2} */
37940 +  {
37941 +    { 0, 0, 0, 0 },
37942 +    { { MNEM, ' ', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
37943 +    & ifmt_mac_s1_indirect_with_index_2_dyn_reg, { 0x14600300 }
37944 +  },
37945 +/* mulu ${s1-imm7-2}(${s1-An}),${s2} */
37946 +  {
37947 +    { 0, 0, 0, 0 },
37948 +    { { MNEM, ' ', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
37949 +    & ifmt_mac_s1_indirect_with_offset_2_dyn_reg, { 0x14600400 }
37950 +  },
37951 +/* mulu (${s1-An}),${s2} */
37952 +  {
37953 +    { 0, 0, 0, 0 },
37954 +    { { MNEM, ' ', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
37955 +    & ifmt_mac_s1_indirect_2_dyn_reg, { 0x14600400 }
37956 +  },
37957 +/* mulu (${s1-An})${s1-i4-2}++,${s2} */
37958 +  {
37959 +    { 0, 0, 0, 0 },
37960 +    { { MNEM, ' ', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } },
37961 +    & ifmt_mac_s1_indirect_with_post_increment_2_dyn_reg, { 0x14600200 }
37962 +  },
37963 +/* mulu ${s1-i4-2}(${s1-An})++,${s2} */
37964 +  {
37965 +    { 0, 0, 0, 0 },
37966 +    { { MNEM, ' ', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
37967 +    & ifmt_mac_s1_indirect_with_pre_increment_2_dyn_reg, { 0x14600210 }
37968 +  },
37969 +/* muls ${s1-direct-addr},${dsp-S2-data-reg} */
37970 +  {
37971 +    { 0, 0, 0, 0 },
37972 +    { { MNEM, ' ', OP (S1_DIRECT_ADDR), ',', OP (DSP_S2_DATA_REG), 0 } },
37973 +    & ifmt_compatibility_mac_s1_direct_dsp_src2_data_reg, { 0x34000100 }
37974 +  },
37975 +/* muls #${s1-imm8},${dsp-S2-data-reg} */
37976 +  {
37977 +    { 0, 0, 0, 0 },
37978 +    { { MNEM, ' ', '#', OP (S1_IMM8), ',', OP (DSP_S2_DATA_REG), 0 } },
37979 +    & ifmt_compatibility_mac_s1_immediate_dsp_src2_data_reg, { 0x34000000 }
37980 +  },
37981 +/* muls (${s1-An},${s1-r}),${dsp-S2-data-reg} */
37982 +  {
37983 +    { 0, 0, 0, 0 },
37984 +    { { MNEM, ' ', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (DSP_S2_DATA_REG), 0 } },
37985 +    & ifmt_compatibility_mac_s1_indirect_with_index_2_dsp_src2_data_reg, { 0x34000300 }
37986 +  },
37987 +/* muls ${s1-imm7-2}(${s1-An}),${dsp-S2-data-reg} */
37988 +  {
37989 +    { 0, 0, 0, 0 },
37990 +    { { MNEM, ' ', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG), 0 } },
37991 +    & ifmt_compatibility_mac_s1_indirect_with_offset_2_dsp_src2_data_reg, { 0x34000400 }
37992 +  },
37993 +/* muls (${s1-An}),${dsp-S2-data-reg} */
37994 +  {
37995 +    { 0, 0, 0, 0 },
37996 +    { { MNEM, ' ', '(', OP (S1_AN), ')', ',', OP (DSP_S2_DATA_REG), 0 } },
37997 +    & ifmt_compatibility_mac_s1_indirect_2_dsp_src2_data_reg, { 0x34000400 }
37998 +  },
37999 +/* muls (${s1-An})${s1-i4-2}++,${dsp-S2-data-reg} */
38000 +  {
38001 +    { 0, 0, 0, 0 },
38002 +    { { MNEM, ' ', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (DSP_S2_DATA_REG), 0 } },
38003 +    & ifmt_compatibility_mac_s1_indirect_with_post_increment_2_dsp_src2_data_reg, { 0x34000200 }
38004 +  },
38005 +/* muls ${s1-i4-2}(${s1-An})++,${dsp-S2-data-reg} */
38006 +  {
38007 +    { 0, 0, 0, 0 },
38008 +    { { MNEM, ' ', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (DSP_S2_DATA_REG), 0 } },
38009 +    & ifmt_compatibility_mac_s1_indirect_with_pre_increment_2_dsp_src2_data_reg, { 0x34000210 }
38010 +  },
38011 +/* muls ${s1-direct-addr},#${bit5} */
38012 +  {
38013 +    { 0, 0, 0, 0 },
38014 +    { { MNEM, ' ', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } },
38015 +    & ifmt_compatibility_mac_s1_direct_dsp_imm_bit5, { 0x30000100 }
38016 +  },
38017 +/* muls #${s1-imm8},#${bit5} */
38018 +  {
38019 +    { 0, 0, 0, 0 },
38020 +    { { MNEM, ' ', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } },
38021 +    & ifmt_compatibility_mac_s1_immediate_dsp_imm_bit5, { 0x30000000 }
38022 +  },
38023 +/* muls (${s1-An},${s1-r}),#${bit5} */
38024 +  {
38025 +    { 0, 0, 0, 0 },
38026 +    { { MNEM, ' ', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } },
38027 +    & ifmt_compatibility_mac_s1_indirect_with_index_2_dsp_imm_bit5, { 0x30000300 }
38028 +  },
38029 +/* muls ${s1-imm7-2}(${s1-An}),#${bit5} */
38030 +  {
38031 +    { 0, 0, 0, 0 },
38032 +    { { MNEM, ' ', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
38033 +    & ifmt_compatibility_mac_s1_indirect_with_offset_2_dsp_imm_bit5, { 0x30000400 }
38034 +  },
38035 +/* muls (${s1-An}),#${bit5} */
38036 +  {
38037 +    { 0, 0, 0, 0 },
38038 +    { { MNEM, ' ', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
38039 +    & ifmt_compatibility_mac_s1_indirect_2_dsp_imm_bit5, { 0x30000400 }
38040 +  },
38041 +/* muls (${s1-An})${s1-i4-2}++,#${bit5} */
38042 +  {
38043 +    { 0, 0, 0, 0 },
38044 +    { { MNEM, ' ', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', '#', OP (BIT5), 0 } },
38045 +    & ifmt_compatibility_mac_s1_indirect_with_post_increment_2_dsp_imm_bit5, { 0x30000200 }
38046 +  },
38047 +/* muls ${s1-i4-2}(${s1-An})++,#${bit5} */
38048 +  {
38049 +    { 0, 0, 0, 0 },
38050 +    { { MNEM, ' ', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } },
38051 +    & ifmt_compatibility_mac_s1_indirect_with_pre_increment_2_dsp_imm_bit5, { 0x30000210 }
38052 +  },
38053 +/* muls ${s1-direct-addr},#${bit5} */
38054 +  {
38055 +    { 0, 0, 0, 0 },
38056 +    { { MNEM, ' ', OP (S1_DIRECT_ADDR), ',', '#', OP (BIT5), 0 } },
38057 +    & ifmt_btst_s1_direct_imm_bit5, { 0x10200100 }
38058 +  },
38059 +/* muls #${s1-imm8},#${bit5} */
38060 +  {
38061 +    { 0, 0, 0, 0 },
38062 +    { { MNEM, ' ', '#', OP (S1_IMM8), ',', '#', OP (BIT5), 0 } },
38063 +    & ifmt_btst_s1_immediate_imm_bit5, { 0x10200000 }
38064 +  },
38065 +/* muls (${s1-An},${s1-r}),#${bit5} */
38066 +  {
38067 +    { 0, 0, 0, 0 },
38068 +    { { MNEM, ' ', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (BIT5), 0 } },
38069 +    & ifmt_mac_s1_indirect_with_index_2_imm_bit5, { 0x10200300 }
38070 +  },
38071 +/* muls ${s1-imm7-2}(${s1-An}),#${bit5} */
38072 +  {
38073 +    { 0, 0, 0, 0 },
38074 +    { { MNEM, ' ', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
38075 +    & ifmt_mac_s1_indirect_with_offset_2_imm_bit5, { 0x10200400 }
38076 +  },
38077 +/* muls (${s1-An}),#${bit5} */
38078 +  {
38079 +    { 0, 0, 0, 0 },
38080 +    { { MNEM, ' ', '(', OP (S1_AN), ')', ',', '#', OP (BIT5), 0 } },
38081 +    & ifmt_mac_s1_indirect_2_imm_bit5, { 0x10200400 }
38082 +  },
38083 +/* muls (${s1-An})${s1-i4-2}++,#${bit5} */
38084 +  {
38085 +    { 0, 0, 0, 0 },
38086 +    { { MNEM, ' ', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', '#', OP (BIT5), 0 } },
38087 +    & ifmt_mac_s1_indirect_with_post_increment_2_imm_bit5, { 0x10200200 }
38088 +  },
38089 +/* muls ${s1-i4-2}(${s1-An})++,#${bit5} */
38090 +  {
38091 +    { 0, 0, 0, 0 },
38092 +    { { MNEM, ' ', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (BIT5), 0 } },
38093 +    & ifmt_mac_s1_indirect_with_pre_increment_2_imm_bit5, { 0x10200210 }
38094 +  },
38095 +/* muls ${s1-direct-addr},${s2} */
38096 +  {
38097 +    { 0, 0, 0, 0 },
38098 +    { { MNEM, ' ', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
38099 +    & ifmt_btst_s1_direct_dyn_reg, { 0x14200100 }
38100 +  },
38101 +/* muls #${s1-imm8},${s2} */
38102 +  {
38103 +    { 0, 0, 0, 0 },
38104 +    { { MNEM, ' ', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
38105 +    & ifmt_btst_s1_immediate_dyn_reg, { 0x14200000 }
38106 +  },
38107 +/* muls (${s1-An},${s1-r}),${s2} */
38108 +  {
38109 +    { 0, 0, 0, 0 },
38110 +    { { MNEM, ' ', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
38111 +    & ifmt_mac_s1_indirect_with_index_2_dyn_reg, { 0x14200300 }
38112 +  },
38113 +/* muls ${s1-imm7-2}(${s1-An}),${s2} */
38114 +  {
38115 +    { 0, 0, 0, 0 },
38116 +    { { MNEM, ' ', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
38117 +    & ifmt_mac_s1_indirect_with_offset_2_dyn_reg, { 0x14200400 }
38118 +  },
38119 +/* muls (${s1-An}),${s2} */
38120 +  {
38121 +    { 0, 0, 0, 0 },
38122 +    { { MNEM, ' ', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
38123 +    & ifmt_mac_s1_indirect_2_dyn_reg, { 0x14200400 }
38124 +  },
38125 +/* muls (${s1-An})${s1-i4-2}++,${s2} */
38126 +  {
38127 +    { 0, 0, 0, 0 },
38128 +    { { MNEM, ' ', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } },
38129 +    & ifmt_mac_s1_indirect_with_post_increment_2_dyn_reg, { 0x14200200 }
38130 +  },
38131 +/* muls ${s1-i4-2}(${s1-An})++,${s2} */
38132 +  {
38133 +    { 0, 0, 0, 0 },
38134 +    { { MNEM, ' ', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
38135 +    & ifmt_mac_s1_indirect_with_pre_increment_2_dyn_reg, { 0x14200210 }
38136 +  },
38137 +/* swapb.4 ${d-direct-addr},${s1-direct-addr} */
38138 +  {
38139 +    { 0, 0, 0, 0 },
38140 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), 0 } },
38141 +    & ifmt_movea_d_direct_s1_direct, { 0x100c900 }
38142 +  },
38143 +/* swapb.4 #${d-imm8},${s1-direct-addr} */
38144 +  {
38145 +    { 0, 0, 0, 0 },
38146 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), 0 } },
38147 +    & ifmt_movea_d_immediate_4_s1_direct, { 0xc900 }
38148 +  },
38149 +/* swapb.4 (${d-An},${d-r}),${s1-direct-addr} */
38150 +  {
38151 +    { 0, 0, 0, 0 },
38152 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), 0 } },
38153 +    & ifmt_movea_d_indirect_with_index_4_s1_direct, { 0x300c900 }
38154 +  },
38155 +/* swapb.4 ${d-imm7-4}(${d-An}),${s1-direct-addr} */
38156 +  {
38157 +    { 0, 0, 0, 0 },
38158 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), 0 } },
38159 +    & ifmt_movea_d_indirect_with_offset_4_s1_direct, { 0x400c900 }
38160 +  },
38161 +/* swapb.4 (${d-An}),${s1-direct-addr} */
38162 +  {
38163 +    { 0, 0, 0, 0 },
38164 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), 0 } },
38165 +    & ifmt_movea_d_indirect_4_s1_direct, { 0x400c900 }
38166 +  },
38167 +/* swapb.4 (${d-An})${d-i4-4}++,${s1-direct-addr} */
38168 +  {
38169 +    { 0, 0, 0, 0 },
38170 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_DIRECT_ADDR), 0 } },
38171 +    & ifmt_movea_d_indirect_with_post_increment_4_s1_direct, { 0x200c900 }
38172 +  },
38173 +/* swapb.4 ${d-i4-4}(${d-An})++,${s1-direct-addr} */
38174 +  {
38175 +    { 0, 0, 0, 0 },
38176 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), 0 } },
38177 +    & ifmt_movea_d_indirect_with_pre_increment_4_s1_direct, { 0x210c900 }
38178 +  },
38179 +/* swapb.4 ${d-direct-addr},#${s1-imm8} */
38180 +  {
38181 +    { 0, 0, 0, 0 },
38182 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), 0 } },
38183 +    & ifmt_movea_d_direct_s1_immediate, { 0x100c800 }
38184 +  },
38185 +/* swapb.4 #${d-imm8},#${s1-imm8} */
38186 +  {
38187 +    { 0, 0, 0, 0 },
38188 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), 0 } },
38189 +    & ifmt_movea_d_immediate_4_s1_immediate, { 0xc800 }
38190 +  },
38191 +/* swapb.4 (${d-An},${d-r}),#${s1-imm8} */
38192 +  {
38193 +    { 0, 0, 0, 0 },
38194 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), 0 } },
38195 +    & ifmt_movea_d_indirect_with_index_4_s1_immediate, { 0x300c800 }
38196 +  },
38197 +/* swapb.4 ${d-imm7-4}(${d-An}),#${s1-imm8} */
38198 +  {
38199 +    { 0, 0, 0, 0 },
38200 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } },
38201 +    & ifmt_movea_d_indirect_with_offset_4_s1_immediate, { 0x400c800 }
38202 +  },
38203 +/* swapb.4 (${d-An}),#${s1-imm8} */
38204 +  {
38205 +    { 0, 0, 0, 0 },
38206 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } },
38207 +    & ifmt_movea_d_indirect_4_s1_immediate, { 0x400c800 }
38208 +  },
38209 +/* swapb.4 (${d-An})${d-i4-4}++,#${s1-imm8} */
38210 +  {
38211 +    { 0, 0, 0, 0 },
38212 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '#', OP (S1_IMM8), 0 } },
38213 +    & ifmt_movea_d_indirect_with_post_increment_4_s1_immediate, { 0x200c800 }
38214 +  },
38215 +/* swapb.4 ${d-i4-4}(${d-An})++,#${s1-imm8} */
38216 +  {
38217 +    { 0, 0, 0, 0 },
38218 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), 0 } },
38219 +    & ifmt_movea_d_indirect_with_pre_increment_4_s1_immediate, { 0x210c800 }
38220 +  },
38221 +/* swapb.4 ${d-direct-addr},(${s1-An},${s1-r}) */
38222 +  {
38223 +    { 0, 0, 0, 0 },
38224 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
38225 +    & ifmt_movea_d_direct_s1_indirect_with_index_4, { 0x100cb00 }
38226 +  },
38227 +/* swapb.4 #${d-imm8},(${s1-An},${s1-r}) */
38228 +  {
38229 +    { 0, 0, 0, 0 },
38230 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
38231 +    & ifmt_movea_d_immediate_4_s1_indirect_with_index_4, { 0xcb00 }
38232 +  },
38233 +/* swapb.4 (${d-An},${d-r}),(${s1-An},${s1-r}) */
38234 +  {
38235 +    { 0, 0, 0, 0 },
38236 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
38237 +    & ifmt_movea_d_indirect_with_index_4_s1_indirect_with_index_4, { 0x300cb00 }
38238 +  },
38239 +/* swapb.4 ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}) */
38240 +  {
38241 +    { 0, 0, 0, 0 },
38242 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
38243 +    & ifmt_movea_d_indirect_with_offset_4_s1_indirect_with_index_4, { 0x400cb00 }
38244 +  },
38245 +/* swapb.4 (${d-An}),(${s1-An},${s1-r}) */
38246 +  {
38247 +    { 0, 0, 0, 0 },
38248 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
38249 +    & ifmt_movea_d_indirect_4_s1_indirect_with_index_4, { 0x400cb00 }
38250 +  },
38251 +/* swapb.4 (${d-An})${d-i4-4}++,(${s1-An},${s1-r}) */
38252 +  {
38253 +    { 0, 0, 0, 0 },
38254 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
38255 +    & ifmt_movea_d_indirect_with_post_increment_4_s1_indirect_with_index_4, { 0x200cb00 }
38256 +  },
38257 +/* swapb.4 ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}) */
38258 +  {
38259 +    { 0, 0, 0, 0 },
38260 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
38261 +    & ifmt_movea_d_indirect_with_pre_increment_4_s1_indirect_with_index_4, { 0x210cb00 }
38262 +  },
38263 +/* swapb.4 ${d-direct-addr},${s1-imm7-4}(${s1-An}) */
38264 +  {
38265 +    { 0, 0, 0, 0 },
38266 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
38267 +    & ifmt_movea_d_direct_s1_indirect_with_offset_4, { 0x100cc00 }
38268 +  },
38269 +/* swapb.4 #${d-imm8},${s1-imm7-4}(${s1-An}) */
38270 +  {
38271 +    { 0, 0, 0, 0 },
38272 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
38273 +    & ifmt_movea_d_immediate_4_s1_indirect_with_offset_4, { 0xcc00 }
38274 +  },
38275 +/* swapb.4 (${d-An},${d-r}),${s1-imm7-4}(${s1-An}) */
38276 +  {
38277 +    { 0, 0, 0, 0 },
38278 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
38279 +    & ifmt_movea_d_indirect_with_index_4_s1_indirect_with_offset_4, { 0x300cc00 }
38280 +  },
38281 +/* swapb.4 ${d-imm7-4}(${d-An}),${s1-imm7-4}(${s1-An}) */
38282 +  {
38283 +    { 0, 0, 0, 0 },
38284 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
38285 +    & ifmt_movea_d_indirect_with_offset_4_s1_indirect_with_offset_4, { 0x400cc00 }
38286 +  },
38287 +/* swapb.4 (${d-An}),${s1-imm7-4}(${s1-An}) */
38288 +  {
38289 +    { 0, 0, 0, 0 },
38290 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
38291 +    & ifmt_movea_d_indirect_4_s1_indirect_with_offset_4, { 0x400cc00 }
38292 +  },
38293 +/* swapb.4 (${d-An})${d-i4-4}++,${s1-imm7-4}(${s1-An}) */
38294 +  {
38295 +    { 0, 0, 0, 0 },
38296 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
38297 +    & ifmt_movea_d_indirect_with_post_increment_4_s1_indirect_with_offset_4, { 0x200cc00 }
38298 +  },
38299 +/* swapb.4 ${d-i4-4}(${d-An})++,${s1-imm7-4}(${s1-An}) */
38300 +  {
38301 +    { 0, 0, 0, 0 },
38302 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
38303 +    & ifmt_movea_d_indirect_with_pre_increment_4_s1_indirect_with_offset_4, { 0x210cc00 }
38304 +  },
38305 +/* swapb.4 ${d-direct-addr},(${s1-An}) */
38306 +  {
38307 +    { 0, 0, 0, 0 },
38308 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', 0 } },
38309 +    & ifmt_movea_d_direct_s1_indirect_4, { 0x100cc00 }
38310 +  },
38311 +/* swapb.4 #${d-imm8},(${s1-An}) */
38312 +  {
38313 +    { 0, 0, 0, 0 },
38314 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', 0 } },
38315 +    & ifmt_movea_d_immediate_4_s1_indirect_4, { 0xcc00 }
38316 +  },
38317 +/* swapb.4 (${d-An},${d-r}),(${s1-An}) */
38318 +  {
38319 +    { 0, 0, 0, 0 },
38320 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', 0 } },
38321 +    & ifmt_movea_d_indirect_with_index_4_s1_indirect_4, { 0x300cc00 }
38322 +  },
38323 +/* swapb.4 ${d-imm7-4}(${d-An}),(${s1-An}) */
38324 +  {
38325 +    { 0, 0, 0, 0 },
38326 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } },
38327 +    & ifmt_movea_d_indirect_with_offset_4_s1_indirect_4, { 0x400cc00 }
38328 +  },
38329 +/* swapb.4 (${d-An}),(${s1-An}) */
38330 +  {
38331 +    { 0, 0, 0, 0 },
38332 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } },
38333 +    & ifmt_movea_d_indirect_4_s1_indirect_4, { 0x400cc00 }
38334 +  },
38335 +/* swapb.4 (${d-An})${d-i4-4}++,(${s1-An}) */
38336 +  {
38337 +    { 0, 0, 0, 0 },
38338 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', 0 } },
38339 +    & ifmt_movea_d_indirect_with_post_increment_4_s1_indirect_4, { 0x200cc00 }
38340 +  },
38341 +/* swapb.4 ${d-i4-4}(${d-An})++,(${s1-An}) */
38342 +  {
38343 +    { 0, 0, 0, 0 },
38344 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', 0 } },
38345 +    & ifmt_movea_d_indirect_with_pre_increment_4_s1_indirect_4, { 0x210cc00 }
38346 +  },
38347 +/* swapb.4 ${d-direct-addr},(${s1-An})${s1-i4-4}++ */
38348 +  {
38349 +    { 0, 0, 0, 0 },
38350 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
38351 +    & ifmt_movea_d_direct_s1_indirect_with_post_increment_4, { 0x100ca00 }
38352 +  },
38353 +/* swapb.4 #${d-imm8},(${s1-An})${s1-i4-4}++ */
38354 +  {
38355 +    { 0, 0, 0, 0 },
38356 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
38357 +    & ifmt_movea_d_immediate_4_s1_indirect_with_post_increment_4, { 0xca00 }
38358 +  },
38359 +/* swapb.4 (${d-An},${d-r}),(${s1-An})${s1-i4-4}++ */
38360 +  {
38361 +    { 0, 0, 0, 0 },
38362 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
38363 +    & ifmt_movea_d_indirect_with_index_4_s1_indirect_with_post_increment_4, { 0x300ca00 }
38364 +  },
38365 +/* swapb.4 ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-4}++ */
38366 +  {
38367 +    { 0, 0, 0, 0 },
38368 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
38369 +    & ifmt_movea_d_indirect_with_offset_4_s1_indirect_with_post_increment_4, { 0x400ca00 }
38370 +  },
38371 +/* swapb.4 (${d-An}),(${s1-An})${s1-i4-4}++ */
38372 +  {
38373 +    { 0, 0, 0, 0 },
38374 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
38375 +    & ifmt_movea_d_indirect_4_s1_indirect_with_post_increment_4, { 0x400ca00 }
38376 +  },
38377 +/* swapb.4 (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-4}++ */
38378 +  {
38379 +    { 0, 0, 0, 0 },
38380 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
38381 +    & ifmt_movea_d_indirect_with_post_increment_4_s1_indirect_with_post_increment_4, { 0x200ca00 }
38382 +  },
38383 +/* swapb.4 ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-4}++ */
38384 +  {
38385 +    { 0, 0, 0, 0 },
38386 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
38387 +    & ifmt_movea_d_indirect_with_pre_increment_4_s1_indirect_with_post_increment_4, { 0x210ca00 }
38388 +  },
38389 +/* swapb.4 ${d-direct-addr},${s1-i4-4}(${s1-An})++ */
38390 +  {
38391 +    { 0, 0, 0, 0 },
38392 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
38393 +    & ifmt_movea_d_direct_s1_indirect_with_pre_increment_4, { 0x100ca10 }
38394 +  },
38395 +/* swapb.4 #${d-imm8},${s1-i4-4}(${s1-An})++ */
38396 +  {
38397 +    { 0, 0, 0, 0 },
38398 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
38399 +    & ifmt_movea_d_immediate_4_s1_indirect_with_pre_increment_4, { 0xca10 }
38400 +  },
38401 +/* swapb.4 (${d-An},${d-r}),${s1-i4-4}(${s1-An})++ */
38402 +  {
38403 +    { 0, 0, 0, 0 },
38404 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
38405 +    & ifmt_movea_d_indirect_with_index_4_s1_indirect_with_pre_increment_4, { 0x300ca10 }
38406 +  },
38407 +/* swapb.4 ${d-imm7-4}(${d-An}),${s1-i4-4}(${s1-An})++ */
38408 +  {
38409 +    { 0, 0, 0, 0 },
38410 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
38411 +    & ifmt_movea_d_indirect_with_offset_4_s1_indirect_with_pre_increment_4, { 0x400ca10 }
38412 +  },
38413 +/* swapb.4 (${d-An}),${s1-i4-4}(${s1-An})++ */
38414 +  {
38415 +    { 0, 0, 0, 0 },
38416 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
38417 +    & ifmt_movea_d_indirect_4_s1_indirect_with_pre_increment_4, { 0x400ca10 }
38418 +  },
38419 +/* swapb.4 (${d-An})${d-i4-4}++,${s1-i4-4}(${s1-An})++ */
38420 +  {
38421 +    { 0, 0, 0, 0 },
38422 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
38423 +    & ifmt_movea_d_indirect_with_post_increment_4_s1_indirect_with_pre_increment_4, { 0x200ca10 }
38424 +  },
38425 +/* swapb.4 ${d-i4-4}(${d-An})++,${s1-i4-4}(${s1-An})++ */
38426 +  {
38427 +    { 0, 0, 0, 0 },
38428 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
38429 +    & ifmt_movea_d_indirect_with_pre_increment_4_s1_indirect_with_pre_increment_4, { 0x210ca10 }
38430 +  },
38431 +/* swapb.2 ${d-direct-addr},${s1-direct-addr} */
38432 +  {
38433 +    { 0, 0, 0, 0 },
38434 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), 0 } },
38435 +    & ifmt_movea_d_direct_s1_direct, { 0x100c100 }
38436 +  },
38437 +/* swapb.2 #${d-imm8},${s1-direct-addr} */
38438 +  {
38439 +    { 0, 0, 0, 0 },
38440 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), 0 } },
38441 +    & ifmt_move_2_d_immediate_2_s1_direct, { 0xc100 }
38442 +  },
38443 +/* swapb.2 (${d-An},${d-r}),${s1-direct-addr} */
38444 +  {
38445 +    { 0, 0, 0, 0 },
38446 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), 0 } },
38447 +    & ifmt_move_2_d_indirect_with_index_2_s1_direct, { 0x300c100 }
38448 +  },
38449 +/* swapb.2 ${d-imm7-2}(${d-An}),${s1-direct-addr} */
38450 +  {
38451 +    { 0, 0, 0, 0 },
38452 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), 0 } },
38453 +    & ifmt_move_2_d_indirect_with_offset_2_s1_direct, { 0x400c100 }
38454 +  },
38455 +/* swapb.2 (${d-An}),${s1-direct-addr} */
38456 +  {
38457 +    { 0, 0, 0, 0 },
38458 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), 0 } },
38459 +    & ifmt_move_2_d_indirect_2_s1_direct, { 0x400c100 }
38460 +  },
38461 +/* swapb.2 (${d-An})${d-i4-2}++,${s1-direct-addr} */
38462 +  {
38463 +    { 0, 0, 0, 0 },
38464 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_DIRECT_ADDR), 0 } },
38465 +    & ifmt_move_2_d_indirect_with_post_increment_2_s1_direct, { 0x200c100 }
38466 +  },
38467 +/* swapb.2 ${d-i4-2}(${d-An})++,${s1-direct-addr} */
38468 +  {
38469 +    { 0, 0, 0, 0 },
38470 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), 0 } },
38471 +    & ifmt_move_2_d_indirect_with_pre_increment_2_s1_direct, { 0x210c100 }
38472 +  },
38473 +/* swapb.2 ${d-direct-addr},#${s1-imm8} */
38474 +  {
38475 +    { 0, 0, 0, 0 },
38476 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), 0 } },
38477 +    & ifmt_movea_d_direct_s1_immediate, { 0x100c000 }
38478 +  },
38479 +/* swapb.2 #${d-imm8},#${s1-imm8} */
38480 +  {
38481 +    { 0, 0, 0, 0 },
38482 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), 0 } },
38483 +    & ifmt_move_2_d_immediate_2_s1_immediate, { 0xc000 }
38484 +  },
38485 +/* swapb.2 (${d-An},${d-r}),#${s1-imm8} */
38486 +  {
38487 +    { 0, 0, 0, 0 },
38488 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), 0 } },
38489 +    & ifmt_move_2_d_indirect_with_index_2_s1_immediate, { 0x300c000 }
38490 +  },
38491 +/* swapb.2 ${d-imm7-2}(${d-An}),#${s1-imm8} */
38492 +  {
38493 +    { 0, 0, 0, 0 },
38494 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } },
38495 +    & ifmt_move_2_d_indirect_with_offset_2_s1_immediate, { 0x400c000 }
38496 +  },
38497 +/* swapb.2 (${d-An}),#${s1-imm8} */
38498 +  {
38499 +    { 0, 0, 0, 0 },
38500 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } },
38501 +    & ifmt_move_2_d_indirect_2_s1_immediate, { 0x400c000 }
38502 +  },
38503 +/* swapb.2 (${d-An})${d-i4-2}++,#${s1-imm8} */
38504 +  {
38505 +    { 0, 0, 0, 0 },
38506 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '#', OP (S1_IMM8), 0 } },
38507 +    & ifmt_move_2_d_indirect_with_post_increment_2_s1_immediate, { 0x200c000 }
38508 +  },
38509 +/* swapb.2 ${d-i4-2}(${d-An})++,#${s1-imm8} */
38510 +  {
38511 +    { 0, 0, 0, 0 },
38512 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), 0 } },
38513 +    & ifmt_move_2_d_indirect_with_pre_increment_2_s1_immediate, { 0x210c000 }
38514 +  },
38515 +/* swapb.2 ${d-direct-addr},(${s1-An},${s1-r}) */
38516 +  {
38517 +    { 0, 0, 0, 0 },
38518 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
38519 +    & ifmt_move_2_d_direct_s1_indirect_with_index_2, { 0x100c300 }
38520 +  },
38521 +/* swapb.2 #${d-imm8},(${s1-An},${s1-r}) */
38522 +  {
38523 +    { 0, 0, 0, 0 },
38524 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
38525 +    & ifmt_move_2_d_immediate_2_s1_indirect_with_index_2, { 0xc300 }
38526 +  },
38527 +/* swapb.2 (${d-An},${d-r}),(${s1-An},${s1-r}) */
38528 +  {
38529 +    { 0, 0, 0, 0 },
38530 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
38531 +    & ifmt_move_2_d_indirect_with_index_2_s1_indirect_with_index_2, { 0x300c300 }
38532 +  },
38533 +/* swapb.2 ${d-imm7-2}(${d-An}),(${s1-An},${s1-r}) */
38534 +  {
38535 +    { 0, 0, 0, 0 },
38536 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
38537 +    & ifmt_move_2_d_indirect_with_offset_2_s1_indirect_with_index_2, { 0x400c300 }
38538 +  },
38539 +/* swapb.2 (${d-An}),(${s1-An},${s1-r}) */
38540 +  {
38541 +    { 0, 0, 0, 0 },
38542 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
38543 +    & ifmt_move_2_d_indirect_2_s1_indirect_with_index_2, { 0x400c300 }
38544 +  },
38545 +/* swapb.2 (${d-An})${d-i4-2}++,(${s1-An},${s1-r}) */
38546 +  {
38547 +    { 0, 0, 0, 0 },
38548 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
38549 +    & ifmt_move_2_d_indirect_with_post_increment_2_s1_indirect_with_index_2, { 0x200c300 }
38550 +  },
38551 +/* swapb.2 ${d-i4-2}(${d-An})++,(${s1-An},${s1-r}) */
38552 +  {
38553 +    { 0, 0, 0, 0 },
38554 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
38555 +    & ifmt_move_2_d_indirect_with_pre_increment_2_s1_indirect_with_index_2, { 0x210c300 }
38556 +  },
38557 +/* swapb.2 ${d-direct-addr},${s1-imm7-2}(${s1-An}) */
38558 +  {
38559 +    { 0, 0, 0, 0 },
38560 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } },
38561 +    & ifmt_move_2_d_direct_s1_indirect_with_offset_2, { 0x100c400 }
38562 +  },
38563 +/* swapb.2 #${d-imm8},${s1-imm7-2}(${s1-An}) */
38564 +  {
38565 +    { 0, 0, 0, 0 },
38566 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } },
38567 +    & ifmt_move_2_d_immediate_2_s1_indirect_with_offset_2, { 0xc400 }
38568 +  },
38569 +/* swapb.2 (${d-An},${d-r}),${s1-imm7-2}(${s1-An}) */
38570 +  {
38571 +    { 0, 0, 0, 0 },
38572 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } },
38573 +    & ifmt_move_2_d_indirect_with_index_2_s1_indirect_with_offset_2, { 0x300c400 }
38574 +  },
38575 +/* swapb.2 ${d-imm7-2}(${d-An}),${s1-imm7-2}(${s1-An}) */
38576 +  {
38577 +    { 0, 0, 0, 0 },
38578 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } },
38579 +    & ifmt_move_2_d_indirect_with_offset_2_s1_indirect_with_offset_2, { 0x400c400 }
38580 +  },
38581 +/* swapb.2 (${d-An}),${s1-imm7-2}(${s1-An}) */
38582 +  {
38583 +    { 0, 0, 0, 0 },
38584 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } },
38585 +    & ifmt_move_2_d_indirect_2_s1_indirect_with_offset_2, { 0x400c400 }
38586 +  },
38587 +/* swapb.2 (${d-An})${d-i4-2}++,${s1-imm7-2}(${s1-An}) */
38588 +  {
38589 +    { 0, 0, 0, 0 },
38590 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } },
38591 +    & ifmt_move_2_d_indirect_with_post_increment_2_s1_indirect_with_offset_2, { 0x200c400 }
38592 +  },
38593 +/* swapb.2 ${d-i4-2}(${d-An})++,${s1-imm7-2}(${s1-An}) */
38594 +  {
38595 +    { 0, 0, 0, 0 },
38596 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } },
38597 +    & ifmt_move_2_d_indirect_with_pre_increment_2_s1_indirect_with_offset_2, { 0x210c400 }
38598 +  },
38599 +/* swapb.2 ${d-direct-addr},(${s1-An}) */
38600 +  {
38601 +    { 0, 0, 0, 0 },
38602 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', 0 } },
38603 +    & ifmt_move_2_d_direct_s1_indirect_2, { 0x100c400 }
38604 +  },
38605 +/* swapb.2 #${d-imm8},(${s1-An}) */
38606 +  {
38607 +    { 0, 0, 0, 0 },
38608 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', 0 } },
38609 +    & ifmt_move_2_d_immediate_2_s1_indirect_2, { 0xc400 }
38610 +  },
38611 +/* swapb.2 (${d-An},${d-r}),(${s1-An}) */
38612 +  {
38613 +    { 0, 0, 0, 0 },
38614 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', 0 } },
38615 +    & ifmt_move_2_d_indirect_with_index_2_s1_indirect_2, { 0x300c400 }
38616 +  },
38617 +/* swapb.2 ${d-imm7-2}(${d-An}),(${s1-An}) */
38618 +  {
38619 +    { 0, 0, 0, 0 },
38620 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } },
38621 +    & ifmt_move_2_d_indirect_with_offset_2_s1_indirect_2, { 0x400c400 }
38622 +  },
38623 +/* swapb.2 (${d-An}),(${s1-An}) */
38624 +  {
38625 +    { 0, 0, 0, 0 },
38626 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } },
38627 +    & ifmt_move_2_d_indirect_2_s1_indirect_2, { 0x400c400 }
38628 +  },
38629 +/* swapb.2 (${d-An})${d-i4-2}++,(${s1-An}) */
38630 +  {
38631 +    { 0, 0, 0, 0 },
38632 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ')', 0 } },
38633 +    & ifmt_move_2_d_indirect_with_post_increment_2_s1_indirect_2, { 0x200c400 }
38634 +  },
38635 +/* swapb.2 ${d-i4-2}(${d-An})++,(${s1-An}) */
38636 +  {
38637 +    { 0, 0, 0, 0 },
38638 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', 0 } },
38639 +    & ifmt_move_2_d_indirect_with_pre_increment_2_s1_indirect_2, { 0x210c400 }
38640 +  },
38641 +/* swapb.2 ${d-direct-addr},(${s1-An})${s1-i4-2}++ */
38642 +  {
38643 +    { 0, 0, 0, 0 },
38644 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } },
38645 +    & ifmt_move_2_d_direct_s1_indirect_with_post_increment_2, { 0x100c200 }
38646 +  },
38647 +/* swapb.2 #${d-imm8},(${s1-An})${s1-i4-2}++ */
38648 +  {
38649 +    { 0, 0, 0, 0 },
38650 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } },
38651 +    & ifmt_move_2_d_immediate_2_s1_indirect_with_post_increment_2, { 0xc200 }
38652 +  },
38653 +/* swapb.2 (${d-An},${d-r}),(${s1-An})${s1-i4-2}++ */
38654 +  {
38655 +    { 0, 0, 0, 0 },
38656 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } },
38657 +    & ifmt_move_2_d_indirect_with_index_2_s1_indirect_with_post_increment_2, { 0x300c200 }
38658 +  },
38659 +/* swapb.2 ${d-imm7-2}(${d-An}),(${s1-An})${s1-i4-2}++ */
38660 +  {
38661 +    { 0, 0, 0, 0 },
38662 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } },
38663 +    & ifmt_move_2_d_indirect_with_offset_2_s1_indirect_with_post_increment_2, { 0x400c200 }
38664 +  },
38665 +/* swapb.2 (${d-An}),(${s1-An})${s1-i4-2}++ */
38666 +  {
38667 +    { 0, 0, 0, 0 },
38668 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } },
38669 +    & ifmt_move_2_d_indirect_2_s1_indirect_with_post_increment_2, { 0x400c200 }
38670 +  },
38671 +/* swapb.2 (${d-An})${d-i4-2}++,(${s1-An})${s1-i4-2}++ */
38672 +  {
38673 +    { 0, 0, 0, 0 },
38674 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } },
38675 +    & ifmt_move_2_d_indirect_with_post_increment_2_s1_indirect_with_post_increment_2, { 0x200c200 }
38676 +  },
38677 +/* swapb.2 ${d-i4-2}(${d-An})++,(${s1-An})${s1-i4-2}++ */
38678 +  {
38679 +    { 0, 0, 0, 0 },
38680 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } },
38681 +    & ifmt_move_2_d_indirect_with_pre_increment_2_s1_indirect_with_post_increment_2, { 0x210c200 }
38682 +  },
38683 +/* swapb.2 ${d-direct-addr},${s1-i4-2}(${s1-An})++ */
38684 +  {
38685 +    { 0, 0, 0, 0 },
38686 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } },
38687 +    & ifmt_move_2_d_direct_s1_indirect_with_pre_increment_2, { 0x100c210 }
38688 +  },
38689 +/* swapb.2 #${d-imm8},${s1-i4-2}(${s1-An})++ */
38690 +  {
38691 +    { 0, 0, 0, 0 },
38692 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } },
38693 +    & ifmt_move_2_d_immediate_2_s1_indirect_with_pre_increment_2, { 0xc210 }
38694 +  },
38695 +/* swapb.2 (${d-An},${d-r}),${s1-i4-2}(${s1-An})++ */
38696 +  {
38697 +    { 0, 0, 0, 0 },
38698 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } },
38699 +    & ifmt_move_2_d_indirect_with_index_2_s1_indirect_with_pre_increment_2, { 0x300c210 }
38700 +  },
38701 +/* swapb.2 ${d-imm7-2}(${d-An}),${s1-i4-2}(${s1-An})++ */
38702 +  {
38703 +    { 0, 0, 0, 0 },
38704 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } },
38705 +    & ifmt_move_2_d_indirect_with_offset_2_s1_indirect_with_pre_increment_2, { 0x400c210 }
38706 +  },
38707 +/* swapb.2 (${d-An}),${s1-i4-2}(${s1-An})++ */
38708 +  {
38709 +    { 0, 0, 0, 0 },
38710 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } },
38711 +    & ifmt_move_2_d_indirect_2_s1_indirect_with_pre_increment_2, { 0x400c210 }
38712 +  },
38713 +/* swapb.2 (${d-An})${d-i4-2}++,${s1-i4-2}(${s1-An})++ */
38714 +  {
38715 +    { 0, 0, 0, 0 },
38716 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } },
38717 +    & ifmt_move_2_d_indirect_with_post_increment_2_s1_indirect_with_pre_increment_2, { 0x200c210 }
38718 +  },
38719 +/* swapb.2 ${d-i4-2}(${d-An})++,${s1-i4-2}(${s1-An})++ */
38720 +  {
38721 +    { 0, 0, 0, 0 },
38722 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } },
38723 +    & ifmt_move_2_d_indirect_with_pre_increment_2_s1_indirect_with_pre_increment_2, { 0x210c210 }
38724 +  },
38725 +/* pdec ${d-direct-addr},${pdec-s1-imm7-4}(${s1-An}) */
38726 +  {
38727 +    { 0, 0, 0, 0 },
38728 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (PDEC_S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
38729 +    & ifmt_pdec_d_direct_pdec_s1_ea_indirect_with_offset_4, { 0x100f400 }
38730 +  },
38731 +/* pdec #${d-imm8},${pdec-s1-imm7-4}(${s1-An}) */
38732 +  {
38733 +    { 0, 0, 0, 0 },
38734 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (PDEC_S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
38735 +    & ifmt_pdec_d_immediate_4_pdec_s1_ea_indirect_with_offset_4, { 0xf400 }
38736 +  },
38737 +/* pdec (${d-An},${d-r}),${pdec-s1-imm7-4}(${s1-An}) */
38738 +  {
38739 +    { 0, 0, 0, 0 },
38740 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (PDEC_S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
38741 +    & ifmt_pdec_d_indirect_with_index_4_pdec_s1_ea_indirect_with_offset_4, { 0x300f400 }
38742 +  },
38743 +/* pdec ${d-imm7-4}(${d-An}),${pdec-s1-imm7-4}(${s1-An}) */
38744 +  {
38745 +    { 0, 0, 0, 0 },
38746 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (PDEC_S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
38747 +    & ifmt_pdec_d_indirect_with_offset_4_pdec_s1_ea_indirect_with_offset_4, { 0x400f400 }
38748 +  },
38749 +/* pdec (${d-An}),${pdec-s1-imm7-4}(${s1-An}) */
38750 +  {
38751 +    { 0, 0, 0, 0 },
38752 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (PDEC_S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
38753 +    & ifmt_pdec_d_indirect_4_pdec_s1_ea_indirect_with_offset_4, { 0x400f400 }
38754 +  },
38755 +/* pdec (${d-An})${d-i4-4}++,${pdec-s1-imm7-4}(${s1-An}) */
38756 +  {
38757 +    { 0, 0, 0, 0 },
38758 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (PDEC_S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
38759 +    & ifmt_pdec_d_indirect_with_post_increment_4_pdec_s1_ea_indirect_with_offset_4, { 0x200f400 }
38760 +  },
38761 +/* pdec ${d-i4-4}(${d-An})++,${pdec-s1-imm7-4}(${s1-An}) */
38762 +  {
38763 +    { 0, 0, 0, 0 },
38764 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (PDEC_S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
38765 +    & ifmt_pdec_d_indirect_with_pre_increment_4_pdec_s1_ea_indirect_with_offset_4, { 0x210f400 }
38766 +  },
38767 +/* lea.4 ${d-direct-addr},(${s1-An}) */
38768 +  {
38769 +    { 0, 0, 0, 0 },
38770 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', 0 } },
38771 +    & ifmt_lea_4_d_direct_s1_ea_indirect, { 0x100e400 }
38772 +  },
38773 +/* lea.4 #${d-imm8},(${s1-An}) */
38774 +  {
38775 +    { 0, 0, 0, 0 },
38776 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', 0 } },
38777 +    & ifmt_lea_4_d_immediate_4_s1_ea_indirect, { 0xe400 }
38778 +  },
38779 +/* lea.4 (${d-An},${d-r}),(${s1-An}) */
38780 +  {
38781 +    { 0, 0, 0, 0 },
38782 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', 0 } },
38783 +    & ifmt_lea_4_d_indirect_with_index_4_s1_ea_indirect, { 0x300e400 }
38784 +  },
38785 +/* lea.4 ${d-imm7-4}(${d-An}),(${s1-An}) */
38786 +  {
38787 +    { 0, 0, 0, 0 },
38788 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } },
38789 +    & ifmt_lea_4_d_indirect_with_offset_4_s1_ea_indirect, { 0x400e400 }
38790 +  },
38791 +/* lea.4 (${d-An}),(${s1-An}) */
38792 +  {
38793 +    { 0, 0, 0, 0 },
38794 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } },
38795 +    & ifmt_lea_4_d_indirect_4_s1_ea_indirect, { 0x400e400 }
38796 +  },
38797 +/* lea.4 (${d-An})${d-i4-4}++,(${s1-An}) */
38798 +  {
38799 +    { 0, 0, 0, 0 },
38800 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', 0 } },
38801 +    & ifmt_lea_4_d_indirect_with_post_increment_4_s1_ea_indirect, { 0x200e400 }
38802 +  },
38803 +/* lea.4 ${d-i4-4}(${d-An})++,(${s1-An}) */
38804 +  {
38805 +    { 0, 0, 0, 0 },
38806 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', 0 } },
38807 +    & ifmt_lea_4_d_indirect_with_pre_increment_4_s1_ea_indirect, { 0x210e400 }
38808 +  },
38809 +/* lea.4 ${d-direct-addr},${s1-imm7-4}(${s1-An}) */
38810 +  {
38811 +    { 0, 0, 0, 0 },
38812 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
38813 +    & ifmt_lea_4_d_direct_s1_ea_indirect_with_offset_4, { 0x100e400 }
38814 +  },
38815 +/* lea.4 #${d-imm8},${s1-imm7-4}(${s1-An}) */
38816 +  {
38817 +    { 0, 0, 0, 0 },
38818 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
38819 +    & ifmt_lea_4_d_immediate_4_s1_ea_indirect_with_offset_4, { 0xe400 }
38820 +  },
38821 +/* lea.4 (${d-An},${d-r}),${s1-imm7-4}(${s1-An}) */
38822 +  {
38823 +    { 0, 0, 0, 0 },
38824 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
38825 +    & ifmt_lea_4_d_indirect_with_index_4_s1_ea_indirect_with_offset_4, { 0x300e400 }
38826 +  },
38827 +/* lea.4 ${d-imm7-4}(${d-An}),${s1-imm7-4}(${s1-An}) */
38828 +  {
38829 +    { 0, 0, 0, 0 },
38830 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
38831 +    & ifmt_lea_4_d_indirect_with_offset_4_s1_ea_indirect_with_offset_4, { 0x400e400 }
38832 +  },
38833 +/* lea.4 (${d-An}),${s1-imm7-4}(${s1-An}) */
38834 +  {
38835 +    { 0, 0, 0, 0 },
38836 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
38837 +    & ifmt_lea_4_d_indirect_4_s1_ea_indirect_with_offset_4, { 0x400e400 }
38838 +  },
38839 +/* lea.4 (${d-An})${d-i4-4}++,${s1-imm7-4}(${s1-An}) */
38840 +  {
38841 +    { 0, 0, 0, 0 },
38842 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
38843 +    & ifmt_lea_4_d_indirect_with_post_increment_4_s1_ea_indirect_with_offset_4, { 0x200e400 }
38844 +  },
38845 +/* lea.4 ${d-i4-4}(${d-An})++,${s1-imm7-4}(${s1-An}) */
38846 +  {
38847 +    { 0, 0, 0, 0 },
38848 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
38849 +    & ifmt_lea_4_d_indirect_with_pre_increment_4_s1_ea_indirect_with_offset_4, { 0x210e400 }
38850 +  },
38851 +/* lea.4 ${d-direct-addr},(${s1-An},${s1-r}) */
38852 +  {
38853 +    { 0, 0, 0, 0 },
38854 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
38855 +    & ifmt_lea_4_d_direct_s1_ea_indirect_with_index_4, { 0x100e300 }
38856 +  },
38857 +/* lea.4 #${d-imm8},(${s1-An},${s1-r}) */
38858 +  {
38859 +    { 0, 0, 0, 0 },
38860 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
38861 +    & ifmt_lea_4_d_immediate_4_s1_ea_indirect_with_index_4, { 0xe300 }
38862 +  },
38863 +/* lea.4 (${d-An},${d-r}),(${s1-An},${s1-r}) */
38864 +  {
38865 +    { 0, 0, 0, 0 },
38866 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
38867 +    & ifmt_lea_4_d_indirect_with_index_4_s1_ea_indirect_with_index_4, { 0x300e300 }
38868 +  },
38869 +/* lea.4 ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}) */
38870 +  {
38871 +    { 0, 0, 0, 0 },
38872 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
38873 +    & ifmt_lea_4_d_indirect_with_offset_4_s1_ea_indirect_with_index_4, { 0x400e300 }
38874 +  },
38875 +/* lea.4 (${d-An}),(${s1-An},${s1-r}) */
38876 +  {
38877 +    { 0, 0, 0, 0 },
38878 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
38879 +    & ifmt_lea_4_d_indirect_4_s1_ea_indirect_with_index_4, { 0x400e300 }
38880 +  },
38881 +/* lea.4 (${d-An})${d-i4-4}++,(${s1-An},${s1-r}) */
38882 +  {
38883 +    { 0, 0, 0, 0 },
38884 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
38885 +    & ifmt_lea_4_d_indirect_with_post_increment_4_s1_ea_indirect_with_index_4, { 0x200e300 }
38886 +  },
38887 +/* lea.4 ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}) */
38888 +  {
38889 +    { 0, 0, 0, 0 },
38890 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
38891 +    & ifmt_lea_4_d_indirect_with_pre_increment_4_s1_ea_indirect_with_index_4, { 0x210e300 }
38892 +  },
38893 +/* lea.4 ${d-direct-addr},(${s1-An})${s1-i4-4}++ */
38894 +  {
38895 +    { 0, 0, 0, 0 },
38896 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
38897 +    & ifmt_lea_4_d_direct_s1_ea_indirect_with_post_increment_4, { 0x100e200 }
38898 +  },
38899 +/* lea.4 #${d-imm8},(${s1-An})${s1-i4-4}++ */
38900 +  {
38901 +    { 0, 0, 0, 0 },
38902 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
38903 +    & ifmt_lea_4_d_immediate_4_s1_ea_indirect_with_post_increment_4, { 0xe200 }
38904 +  },
38905 +/* lea.4 (${d-An},${d-r}),(${s1-An})${s1-i4-4}++ */
38906 +  {
38907 +    { 0, 0, 0, 0 },
38908 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
38909 +    & ifmt_lea_4_d_indirect_with_index_4_s1_ea_indirect_with_post_increment_4, { 0x300e200 }
38910 +  },
38911 +/* lea.4 ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-4}++ */
38912 +  {
38913 +    { 0, 0, 0, 0 },
38914 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
38915 +    & ifmt_lea_4_d_indirect_with_offset_4_s1_ea_indirect_with_post_increment_4, { 0x400e200 }
38916 +  },
38917 +/* lea.4 (${d-An}),(${s1-An})${s1-i4-4}++ */
38918 +  {
38919 +    { 0, 0, 0, 0 },
38920 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
38921 +    & ifmt_lea_4_d_indirect_4_s1_ea_indirect_with_post_increment_4, { 0x400e200 }
38922 +  },
38923 +/* lea.4 (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-4}++ */
38924 +  {
38925 +    { 0, 0, 0, 0 },
38926 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
38927 +    & ifmt_lea_4_d_indirect_with_post_increment_4_s1_ea_indirect_with_post_increment_4, { 0x200e200 }
38928 +  },
38929 +/* lea.4 ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-4}++ */
38930 +  {
38931 +    { 0, 0, 0, 0 },
38932 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
38933 +    & ifmt_lea_4_d_indirect_with_pre_increment_4_s1_ea_indirect_with_post_increment_4, { 0x210e200 }
38934 +  },
38935 +/* lea.4 ${d-direct-addr},${s1-i4-4}(${s1-An})++ */
38936 +  {
38937 +    { 0, 0, 0, 0 },
38938 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
38939 +    & ifmt_lea_4_d_direct_s1_ea_indirect_with_pre_increment_4, { 0x100e210 }
38940 +  },
38941 +/* lea.4 #${d-imm8},${s1-i4-4}(${s1-An})++ */
38942 +  {
38943 +    { 0, 0, 0, 0 },
38944 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
38945 +    & ifmt_lea_4_d_immediate_4_s1_ea_indirect_with_pre_increment_4, { 0xe210 }
38946 +  },
38947 +/* lea.4 (${d-An},${d-r}),${s1-i4-4}(${s1-An})++ */
38948 +  {
38949 +    { 0, 0, 0, 0 },
38950 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
38951 +    & ifmt_lea_4_d_indirect_with_index_4_s1_ea_indirect_with_pre_increment_4, { 0x300e210 }
38952 +  },
38953 +/* lea.4 ${d-imm7-4}(${d-An}),${s1-i4-4}(${s1-An})++ */
38954 +  {
38955 +    { 0, 0, 0, 0 },
38956 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
38957 +    & ifmt_lea_4_d_indirect_with_offset_4_s1_ea_indirect_with_pre_increment_4, { 0x400e210 }
38958 +  },
38959 +/* lea.4 (${d-An}),${s1-i4-4}(${s1-An})++ */
38960 +  {
38961 +    { 0, 0, 0, 0 },
38962 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
38963 +    & ifmt_lea_4_d_indirect_4_s1_ea_indirect_with_pre_increment_4, { 0x400e210 }
38964 +  },
38965 +/* lea.4 (${d-An})${d-i4-4}++,${s1-i4-4}(${s1-An})++ */
38966 +  {
38967 +    { 0, 0, 0, 0 },
38968 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
38969 +    & ifmt_lea_4_d_indirect_with_post_increment_4_s1_ea_indirect_with_pre_increment_4, { 0x200e210 }
38970 +  },
38971 +/* lea.4 ${d-i4-4}(${d-An})++,${s1-i4-4}(${s1-An})++ */
38972 +  {
38973 +    { 0, 0, 0, 0 },
38974 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
38975 +    & ifmt_lea_4_d_indirect_with_pre_increment_4_s1_ea_indirect_with_pre_increment_4, { 0x210e210 }
38976 +  },
38977 +/* lea.4 ${d-direct-addr},#${s1-imm8} */
38978 +  {
38979 +    { 0, 0, 0, 0 },
38980 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), 0 } },
38981 +    & ifmt_lea_4_d_direct_s1_ea_immediate, { 0x100e000 }
38982 +  },
38983 +/* lea.4 #${d-imm8},#${s1-imm8} */
38984 +  {
38985 +    { 0, 0, 0, 0 },
38986 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), 0 } },
38987 +    & ifmt_lea_4_d_immediate_4_s1_ea_immediate, { 0xe000 }
38988 +  },
38989 +/* lea.4 (${d-An},${d-r}),#${s1-imm8} */
38990 +  {
38991 +    { 0, 0, 0, 0 },
38992 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), 0 } },
38993 +    & ifmt_lea_4_d_indirect_with_index_4_s1_ea_immediate, { 0x300e000 }
38994 +  },
38995 +/* lea.4 ${d-imm7-4}(${d-An}),#${s1-imm8} */
38996 +  {
38997 +    { 0, 0, 0, 0 },
38998 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } },
38999 +    & ifmt_lea_4_d_indirect_with_offset_4_s1_ea_immediate, { 0x400e000 }
39000 +  },
39001 +/* lea.4 (${d-An}),#${s1-imm8} */
39002 +  {
39003 +    { 0, 0, 0, 0 },
39004 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } },
39005 +    & ifmt_lea_4_d_indirect_4_s1_ea_immediate, { 0x400e000 }
39006 +  },
39007 +/* lea.4 (${d-An})${d-i4-4}++,#${s1-imm8} */
39008 +  {
39009 +    { 0, 0, 0, 0 },
39010 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '#', OP (S1_IMM8), 0 } },
39011 +    & ifmt_lea_4_d_indirect_with_post_increment_4_s1_ea_immediate, { 0x200e000 }
39012 +  },
39013 +/* lea.4 ${d-i4-4}(${d-An})++,#${s1-imm8} */
39014 +  {
39015 +    { 0, 0, 0, 0 },
39016 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), 0 } },
39017 +    & ifmt_lea_4_d_indirect_with_pre_increment_4_s1_ea_immediate, { 0x210e000 }
39018 +  },
39019 +/* lea.2 ${d-direct-addr},(${s1-An}) */
39020 +  {
39021 +    { 0, 0, 0, 0 },
39022 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', 0 } },
39023 +    & ifmt_lea_4_d_direct_s1_ea_indirect, { 0x100ec00 }
39024 +  },
39025 +/* lea.2 #${d-imm8},(${s1-An}) */
39026 +  {
39027 +    { 0, 0, 0, 0 },
39028 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', 0 } },
39029 +    & ifmt_lea_4_d_immediate_4_s1_ea_indirect, { 0xec00 }
39030 +  },
39031 +/* lea.2 (${d-An},${d-r}),(${s1-An}) */
39032 +  {
39033 +    { 0, 0, 0, 0 },
39034 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', 0 } },
39035 +    & ifmt_lea_4_d_indirect_with_index_4_s1_ea_indirect, { 0x300ec00 }
39036 +  },
39037 +/* lea.2 ${d-imm7-4}(${d-An}),(${s1-An}) */
39038 +  {
39039 +    { 0, 0, 0, 0 },
39040 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } },
39041 +    & ifmt_lea_4_d_indirect_with_offset_4_s1_ea_indirect, { 0x400ec00 }
39042 +  },
39043 +/* lea.2 (${d-An}),(${s1-An}) */
39044 +  {
39045 +    { 0, 0, 0, 0 },
39046 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } },
39047 +    & ifmt_lea_4_d_indirect_4_s1_ea_indirect, { 0x400ec00 }
39048 +  },
39049 +/* lea.2 (${d-An})${d-i4-4}++,(${s1-An}) */
39050 +  {
39051 +    { 0, 0, 0, 0 },
39052 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', 0 } },
39053 +    & ifmt_lea_4_d_indirect_with_post_increment_4_s1_ea_indirect, { 0x200ec00 }
39054 +  },
39055 +/* lea.2 ${d-i4-4}(${d-An})++,(${s1-An}) */
39056 +  {
39057 +    { 0, 0, 0, 0 },
39058 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', 0 } },
39059 +    & ifmt_lea_4_d_indirect_with_pre_increment_4_s1_ea_indirect, { 0x210ec00 }
39060 +  },
39061 +/* lea.2 ${d-direct-addr},${s1-imm7-2}(${s1-An}) */
39062 +  {
39063 +    { 0, 0, 0, 0 },
39064 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } },
39065 +    & ifmt_lea_2_d_direct_s1_ea_indirect_with_offset_2, { 0x100ec00 }
39066 +  },
39067 +/* lea.2 #${d-imm8},${s1-imm7-2}(${s1-An}) */
39068 +  {
39069 +    { 0, 0, 0, 0 },
39070 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } },
39071 +    & ifmt_lea_2_d_immediate_4_s1_ea_indirect_with_offset_2, { 0xec00 }
39072 +  },
39073 +/* lea.2 (${d-An},${d-r}),${s1-imm7-2}(${s1-An}) */
39074 +  {
39075 +    { 0, 0, 0, 0 },
39076 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } },
39077 +    & ifmt_lea_2_d_indirect_with_index_4_s1_ea_indirect_with_offset_2, { 0x300ec00 }
39078 +  },
39079 +/* lea.2 ${d-imm7-4}(${d-An}),${s1-imm7-2}(${s1-An}) */
39080 +  {
39081 +    { 0, 0, 0, 0 },
39082 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } },
39083 +    & ifmt_lea_2_d_indirect_with_offset_4_s1_ea_indirect_with_offset_2, { 0x400ec00 }
39084 +  },
39085 +/* lea.2 (${d-An}),${s1-imm7-2}(${s1-An}) */
39086 +  {
39087 +    { 0, 0, 0, 0 },
39088 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } },
39089 +    & ifmt_lea_2_d_indirect_4_s1_ea_indirect_with_offset_2, { 0x400ec00 }
39090 +  },
39091 +/* lea.2 (${d-An})${d-i4-4}++,${s1-imm7-2}(${s1-An}) */
39092 +  {
39093 +    { 0, 0, 0, 0 },
39094 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } },
39095 +    & ifmt_lea_2_d_indirect_with_post_increment_4_s1_ea_indirect_with_offset_2, { 0x200ec00 }
39096 +  },
39097 +/* lea.2 ${d-i4-4}(${d-An})++,${s1-imm7-2}(${s1-An}) */
39098 +  {
39099 +    { 0, 0, 0, 0 },
39100 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } },
39101 +    & ifmt_lea_2_d_indirect_with_pre_increment_4_s1_ea_indirect_with_offset_2, { 0x210ec00 }
39102 +  },
39103 +/* lea.2 ${d-direct-addr},(${s1-An},${s1-r}) */
39104 +  {
39105 +    { 0, 0, 0, 0 },
39106 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
39107 +    & ifmt_lea_2_d_direct_s1_ea_indirect_with_index_2, { 0x100eb00 }
39108 +  },
39109 +/* lea.2 #${d-imm8},(${s1-An},${s1-r}) */
39110 +  {
39111 +    { 0, 0, 0, 0 },
39112 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
39113 +    & ifmt_lea_2_d_immediate_4_s1_ea_indirect_with_index_2, { 0xeb00 }
39114 +  },
39115 +/* lea.2 (${d-An},${d-r}),(${s1-An},${s1-r}) */
39116 +  {
39117 +    { 0, 0, 0, 0 },
39118 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
39119 +    & ifmt_lea_2_d_indirect_with_index_4_s1_ea_indirect_with_index_2, { 0x300eb00 }
39120 +  },
39121 +/* lea.2 ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}) */
39122 +  {
39123 +    { 0, 0, 0, 0 },
39124 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
39125 +    & ifmt_lea_2_d_indirect_with_offset_4_s1_ea_indirect_with_index_2, { 0x400eb00 }
39126 +  },
39127 +/* lea.2 (${d-An}),(${s1-An},${s1-r}) */
39128 +  {
39129 +    { 0, 0, 0, 0 },
39130 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
39131 +    & ifmt_lea_2_d_indirect_4_s1_ea_indirect_with_index_2, { 0x400eb00 }
39132 +  },
39133 +/* lea.2 (${d-An})${d-i4-4}++,(${s1-An},${s1-r}) */
39134 +  {
39135 +    { 0, 0, 0, 0 },
39136 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
39137 +    & ifmt_lea_2_d_indirect_with_post_increment_4_s1_ea_indirect_with_index_2, { 0x200eb00 }
39138 +  },
39139 +/* lea.2 ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}) */
39140 +  {
39141 +    { 0, 0, 0, 0 },
39142 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
39143 +    & ifmt_lea_2_d_indirect_with_pre_increment_4_s1_ea_indirect_with_index_2, { 0x210eb00 }
39144 +  },
39145 +/* lea.2 ${d-direct-addr},(${s1-An})${s1-i4-2}++ */
39146 +  {
39147 +    { 0, 0, 0, 0 },
39148 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } },
39149 +    & ifmt_lea_2_d_direct_s1_ea_indirect_with_post_increment_2, { 0x100ea00 }
39150 +  },
39151 +/* lea.2 #${d-imm8},(${s1-An})${s1-i4-2}++ */
39152 +  {
39153 +    { 0, 0, 0, 0 },
39154 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } },
39155 +    & ifmt_lea_2_d_immediate_4_s1_ea_indirect_with_post_increment_2, { 0xea00 }
39156 +  },
39157 +/* lea.2 (${d-An},${d-r}),(${s1-An})${s1-i4-2}++ */
39158 +  {
39159 +    { 0, 0, 0, 0 },
39160 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } },
39161 +    & ifmt_lea_2_d_indirect_with_index_4_s1_ea_indirect_with_post_increment_2, { 0x300ea00 }
39162 +  },
39163 +/* lea.2 ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-2}++ */
39164 +  {
39165 +    { 0, 0, 0, 0 },
39166 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } },
39167 +    & ifmt_lea_2_d_indirect_with_offset_4_s1_ea_indirect_with_post_increment_2, { 0x400ea00 }
39168 +  },
39169 +/* lea.2 (${d-An}),(${s1-An})${s1-i4-2}++ */
39170 +  {
39171 +    { 0, 0, 0, 0 },
39172 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } },
39173 +    & ifmt_lea_2_d_indirect_4_s1_ea_indirect_with_post_increment_2, { 0x400ea00 }
39174 +  },
39175 +/* lea.2 (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-2}++ */
39176 +  {
39177 +    { 0, 0, 0, 0 },
39178 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } },
39179 +    & ifmt_lea_2_d_indirect_with_post_increment_4_s1_ea_indirect_with_post_increment_2, { 0x200ea00 }
39180 +  },
39181 +/* lea.2 ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-2}++ */
39182 +  {
39183 +    { 0, 0, 0, 0 },
39184 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } },
39185 +    & ifmt_lea_2_d_indirect_with_pre_increment_4_s1_ea_indirect_with_post_increment_2, { 0x210ea00 }
39186 +  },
39187 +/* lea.2 ${d-direct-addr},${s1-i4-2}(${s1-An})++ */
39188 +  {
39189 +    { 0, 0, 0, 0 },
39190 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } },
39191 +    & ifmt_lea_2_d_direct_s1_ea_indirect_with_pre_increment_2, { 0x100ea10 }
39192 +  },
39193 +/* lea.2 #${d-imm8},${s1-i4-2}(${s1-An})++ */
39194 +  {
39195 +    { 0, 0, 0, 0 },
39196 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } },
39197 +    & ifmt_lea_2_d_immediate_4_s1_ea_indirect_with_pre_increment_2, { 0xea10 }
39198 +  },
39199 +/* lea.2 (${d-An},${d-r}),${s1-i4-2}(${s1-An})++ */
39200 +  {
39201 +    { 0, 0, 0, 0 },
39202 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } },
39203 +    & ifmt_lea_2_d_indirect_with_index_4_s1_ea_indirect_with_pre_increment_2, { 0x300ea10 }
39204 +  },
39205 +/* lea.2 ${d-imm7-4}(${d-An}),${s1-i4-2}(${s1-An})++ */
39206 +  {
39207 +    { 0, 0, 0, 0 },
39208 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } },
39209 +    & ifmt_lea_2_d_indirect_with_offset_4_s1_ea_indirect_with_pre_increment_2, { 0x400ea10 }
39210 +  },
39211 +/* lea.2 (${d-An}),${s1-i4-2}(${s1-An})++ */
39212 +  {
39213 +    { 0, 0, 0, 0 },
39214 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } },
39215 +    & ifmt_lea_2_d_indirect_4_s1_ea_indirect_with_pre_increment_2, { 0x400ea10 }
39216 +  },
39217 +/* lea.2 (${d-An})${d-i4-4}++,${s1-i4-2}(${s1-An})++ */
39218 +  {
39219 +    { 0, 0, 0, 0 },
39220 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } },
39221 +    & ifmt_lea_2_d_indirect_with_post_increment_4_s1_ea_indirect_with_pre_increment_2, { 0x200ea10 }
39222 +  },
39223 +/* lea.2 ${d-i4-4}(${d-An})++,${s1-i4-2}(${s1-An})++ */
39224 +  {
39225 +    { 0, 0, 0, 0 },
39226 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } },
39227 +    & ifmt_lea_2_d_indirect_with_pre_increment_4_s1_ea_indirect_with_pre_increment_2, { 0x210ea10 }
39228 +  },
39229 +/* lea.2 ${d-direct-addr},#${s1-imm8} */
39230 +  {
39231 +    { 0, 0, 0, 0 },
39232 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), 0 } },
39233 +    & ifmt_lea_4_d_direct_s1_ea_immediate, { 0x100e800 }
39234 +  },
39235 +/* lea.2 #${d-imm8},#${s1-imm8} */
39236 +  {
39237 +    { 0, 0, 0, 0 },
39238 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), 0 } },
39239 +    & ifmt_lea_4_d_immediate_4_s1_ea_immediate, { 0xe800 }
39240 +  },
39241 +/* lea.2 (${d-An},${d-r}),#${s1-imm8} */
39242 +  {
39243 +    { 0, 0, 0, 0 },
39244 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), 0 } },
39245 +    & ifmt_lea_4_d_indirect_with_index_4_s1_ea_immediate, { 0x300e800 }
39246 +  },
39247 +/* lea.2 ${d-imm7-4}(${d-An}),#${s1-imm8} */
39248 +  {
39249 +    { 0, 0, 0, 0 },
39250 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } },
39251 +    & ifmt_lea_4_d_indirect_with_offset_4_s1_ea_immediate, { 0x400e800 }
39252 +  },
39253 +/* lea.2 (${d-An}),#${s1-imm8} */
39254 +  {
39255 +    { 0, 0, 0, 0 },
39256 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } },
39257 +    & ifmt_lea_4_d_indirect_4_s1_ea_immediate, { 0x400e800 }
39258 +  },
39259 +/* lea.2 (${d-An})${d-i4-4}++,#${s1-imm8} */
39260 +  {
39261 +    { 0, 0, 0, 0 },
39262 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '#', OP (S1_IMM8), 0 } },
39263 +    & ifmt_lea_4_d_indirect_with_post_increment_4_s1_ea_immediate, { 0x200e800 }
39264 +  },
39265 +/* lea.2 ${d-i4-4}(${d-An})++,#${s1-imm8} */
39266 +  {
39267 +    { 0, 0, 0, 0 },
39268 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), 0 } },
39269 +    & ifmt_lea_4_d_indirect_with_pre_increment_4_s1_ea_immediate, { 0x210e800 }
39270 +  },
39271 +/* lea.1 ${d-direct-addr},(${s1-An}) */
39272 +  {
39273 +    { 0, 0, 0, 0 },
39274 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', 0 } },
39275 +    & ifmt_lea_4_d_direct_s1_ea_indirect, { 0x100fc00 }
39276 +  },
39277 +/* lea.1 #${d-imm8},(${s1-An}) */
39278 +  {
39279 +    { 0, 0, 0, 0 },
39280 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', 0 } },
39281 +    & ifmt_lea_4_d_immediate_4_s1_ea_indirect, { 0xfc00 }
39282 +  },
39283 +/* lea.1 (${d-An},${d-r}),(${s1-An}) */
39284 +  {
39285 +    { 0, 0, 0, 0 },
39286 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', 0 } },
39287 +    & ifmt_lea_4_d_indirect_with_index_4_s1_ea_indirect, { 0x300fc00 }
39288 +  },
39289 +/* lea.1 ${d-imm7-4}(${d-An}),(${s1-An}) */
39290 +  {
39291 +    { 0, 0, 0, 0 },
39292 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } },
39293 +    & ifmt_lea_4_d_indirect_with_offset_4_s1_ea_indirect, { 0x400fc00 }
39294 +  },
39295 +/* lea.1 (${d-An}),(${s1-An}) */
39296 +  {
39297 +    { 0, 0, 0, 0 },
39298 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } },
39299 +    & ifmt_lea_4_d_indirect_4_s1_ea_indirect, { 0x400fc00 }
39300 +  },
39301 +/* lea.1 (${d-An})${d-i4-4}++,(${s1-An}) */
39302 +  {
39303 +    { 0, 0, 0, 0 },
39304 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', 0 } },
39305 +    & ifmt_lea_4_d_indirect_with_post_increment_4_s1_ea_indirect, { 0x200fc00 }
39306 +  },
39307 +/* lea.1 ${d-i4-4}(${d-An})++,(${s1-An}) */
39308 +  {
39309 +    { 0, 0, 0, 0 },
39310 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', 0 } },
39311 +    & ifmt_lea_4_d_indirect_with_pre_increment_4_s1_ea_indirect, { 0x210fc00 }
39312 +  },
39313 +/* lea.1 ${d-direct-addr},${s1-imm7-1}(${s1-An}) */
39314 +  {
39315 +    { 0, 0, 0, 0 },
39316 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', 0 } },
39317 +    & ifmt_lea_1_d_direct_s1_ea_indirect_with_offset_1, { 0x100fc00 }
39318 +  },
39319 +/* lea.1 #${d-imm8},${s1-imm7-1}(${s1-An}) */
39320 +  {
39321 +    { 0, 0, 0, 0 },
39322 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', 0 } },
39323 +    & ifmt_lea_1_d_immediate_4_s1_ea_indirect_with_offset_1, { 0xfc00 }
39324 +  },
39325 +/* lea.1 (${d-An},${d-r}),${s1-imm7-1}(${s1-An}) */
39326 +  {
39327 +    { 0, 0, 0, 0 },
39328 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', 0 } },
39329 +    & ifmt_lea_1_d_indirect_with_index_4_s1_ea_indirect_with_offset_1, { 0x300fc00 }
39330 +  },
39331 +/* lea.1 ${d-imm7-4}(${d-An}),${s1-imm7-1}(${s1-An}) */
39332 +  {
39333 +    { 0, 0, 0, 0 },
39334 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', 0 } },
39335 +    & ifmt_lea_1_d_indirect_with_offset_4_s1_ea_indirect_with_offset_1, { 0x400fc00 }
39336 +  },
39337 +/* lea.1 (${d-An}),${s1-imm7-1}(${s1-An}) */
39338 +  {
39339 +    { 0, 0, 0, 0 },
39340 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', 0 } },
39341 +    & ifmt_lea_1_d_indirect_4_s1_ea_indirect_with_offset_1, { 0x400fc00 }
39342 +  },
39343 +/* lea.1 (${d-An})${d-i4-4}++,${s1-imm7-1}(${s1-An}) */
39344 +  {
39345 +    { 0, 0, 0, 0 },
39346 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', 0 } },
39347 +    & ifmt_lea_1_d_indirect_with_post_increment_4_s1_ea_indirect_with_offset_1, { 0x200fc00 }
39348 +  },
39349 +/* lea.1 ${d-i4-4}(${d-An})++,${s1-imm7-1}(${s1-An}) */
39350 +  {
39351 +    { 0, 0, 0, 0 },
39352 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', 0 } },
39353 +    & ifmt_lea_1_d_indirect_with_pre_increment_4_s1_ea_indirect_with_offset_1, { 0x210fc00 }
39354 +  },
39355 +/* lea.1 ${d-direct-addr},(${s1-An},${s1-r}) */
39356 +  {
39357 +    { 0, 0, 0, 0 },
39358 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
39359 +    & ifmt_lea_1_d_direct_s1_ea_indirect_with_index_1, { 0x100fb00 }
39360 +  },
39361 +/* lea.1 #${d-imm8},(${s1-An},${s1-r}) */
39362 +  {
39363 +    { 0, 0, 0, 0 },
39364 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
39365 +    & ifmt_lea_1_d_immediate_4_s1_ea_indirect_with_index_1, { 0xfb00 }
39366 +  },
39367 +/* lea.1 (${d-An},${d-r}),(${s1-An},${s1-r}) */
39368 +  {
39369 +    { 0, 0, 0, 0 },
39370 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
39371 +    & ifmt_lea_1_d_indirect_with_index_4_s1_ea_indirect_with_index_1, { 0x300fb00 }
39372 +  },
39373 +/* lea.1 ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}) */
39374 +  {
39375 +    { 0, 0, 0, 0 },
39376 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
39377 +    & ifmt_lea_1_d_indirect_with_offset_4_s1_ea_indirect_with_index_1, { 0x400fb00 }
39378 +  },
39379 +/* lea.1 (${d-An}),(${s1-An},${s1-r}) */
39380 +  {
39381 +    { 0, 0, 0, 0 },
39382 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
39383 +    & ifmt_lea_1_d_indirect_4_s1_ea_indirect_with_index_1, { 0x400fb00 }
39384 +  },
39385 +/* lea.1 (${d-An})${d-i4-4}++,(${s1-An},${s1-r}) */
39386 +  {
39387 +    { 0, 0, 0, 0 },
39388 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
39389 +    & ifmt_lea_1_d_indirect_with_post_increment_4_s1_ea_indirect_with_index_1, { 0x200fb00 }
39390 +  },
39391 +/* lea.1 ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}) */
39392 +  {
39393 +    { 0, 0, 0, 0 },
39394 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
39395 +    & ifmt_lea_1_d_indirect_with_pre_increment_4_s1_ea_indirect_with_index_1, { 0x210fb00 }
39396 +  },
39397 +/* lea.1 ${d-direct-addr},(${s1-An})${s1-i4-1}++ */
39398 +  {
39399 +    { 0, 0, 0, 0 },
39400 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', 0 } },
39401 +    & ifmt_lea_1_d_direct_s1_ea_indirect_with_post_increment_1, { 0x100fa00 }
39402 +  },
39403 +/* lea.1 #${d-imm8},(${s1-An})${s1-i4-1}++ */
39404 +  {
39405 +    { 0, 0, 0, 0 },
39406 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', 0 } },
39407 +    & ifmt_lea_1_d_immediate_4_s1_ea_indirect_with_post_increment_1, { 0xfa00 }
39408 +  },
39409 +/* lea.1 (${d-An},${d-r}),(${s1-An})${s1-i4-1}++ */
39410 +  {
39411 +    { 0, 0, 0, 0 },
39412 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', 0 } },
39413 +    & ifmt_lea_1_d_indirect_with_index_4_s1_ea_indirect_with_post_increment_1, { 0x300fa00 }
39414 +  },
39415 +/* lea.1 ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-1}++ */
39416 +  {
39417 +    { 0, 0, 0, 0 },
39418 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', 0 } },
39419 +    & ifmt_lea_1_d_indirect_with_offset_4_s1_ea_indirect_with_post_increment_1, { 0x400fa00 }
39420 +  },
39421 +/* lea.1 (${d-An}),(${s1-An})${s1-i4-1}++ */
39422 +  {
39423 +    { 0, 0, 0, 0 },
39424 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', 0 } },
39425 +    & ifmt_lea_1_d_indirect_4_s1_ea_indirect_with_post_increment_1, { 0x400fa00 }
39426 +  },
39427 +/* lea.1 (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-1}++ */
39428 +  {
39429 +    { 0, 0, 0, 0 },
39430 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', 0 } },
39431 +    & ifmt_lea_1_d_indirect_with_post_increment_4_s1_ea_indirect_with_post_increment_1, { 0x200fa00 }
39432 +  },
39433 +/* lea.1 ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-1}++ */
39434 +  {
39435 +    { 0, 0, 0, 0 },
39436 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', 0 } },
39437 +    & ifmt_lea_1_d_indirect_with_pre_increment_4_s1_ea_indirect_with_post_increment_1, { 0x210fa00 }
39438 +  },
39439 +/* lea.1 ${d-direct-addr},${s1-i4-1}(${s1-An})++ */
39440 +  {
39441 +    { 0, 0, 0, 0 },
39442 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', 0 } },
39443 +    & ifmt_lea_1_d_direct_s1_ea_indirect_with_pre_increment_1, { 0x100fa10 }
39444 +  },
39445 +/* lea.1 #${d-imm8},${s1-i4-1}(${s1-An})++ */
39446 +  {
39447 +    { 0, 0, 0, 0 },
39448 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', 0 } },
39449 +    & ifmt_lea_1_d_immediate_4_s1_ea_indirect_with_pre_increment_1, { 0xfa10 }
39450 +  },
39451 +/* lea.1 (${d-An},${d-r}),${s1-i4-1}(${s1-An})++ */
39452 +  {
39453 +    { 0, 0, 0, 0 },
39454 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', 0 } },
39455 +    & ifmt_lea_1_d_indirect_with_index_4_s1_ea_indirect_with_pre_increment_1, { 0x300fa10 }
39456 +  },
39457 +/* lea.1 ${d-imm7-4}(${d-An}),${s1-i4-1}(${s1-An})++ */
39458 +  {
39459 +    { 0, 0, 0, 0 },
39460 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', 0 } },
39461 +    & ifmt_lea_1_d_indirect_with_offset_4_s1_ea_indirect_with_pre_increment_1, { 0x400fa10 }
39462 +  },
39463 +/* lea.1 (${d-An}),${s1-i4-1}(${s1-An})++ */
39464 +  {
39465 +    { 0, 0, 0, 0 },
39466 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', 0 } },
39467 +    & ifmt_lea_1_d_indirect_4_s1_ea_indirect_with_pre_increment_1, { 0x400fa10 }
39468 +  },
39469 +/* lea.1 (${d-An})${d-i4-4}++,${s1-i4-1}(${s1-An})++ */
39470 +  {
39471 +    { 0, 0, 0, 0 },
39472 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', 0 } },
39473 +    & ifmt_lea_1_d_indirect_with_post_increment_4_s1_ea_indirect_with_pre_increment_1, { 0x200fa10 }
39474 +  },
39475 +/* lea.1 ${d-i4-4}(${d-An})++,${s1-i4-1}(${s1-An})++ */
39476 +  {
39477 +    { 0, 0, 0, 0 },
39478 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', 0 } },
39479 +    & ifmt_lea_1_d_indirect_with_pre_increment_4_s1_ea_indirect_with_pre_increment_1, { 0x210fa10 }
39480 +  },
39481 +/* lea.1 ${d-direct-addr},#${s1-imm8} */
39482 +  {
39483 +    { 0, 0, 0, 0 },
39484 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), 0 } },
39485 +    & ifmt_lea_4_d_direct_s1_ea_immediate, { 0x100f800 }
39486 +  },
39487 +/* lea.1 #${d-imm8},#${s1-imm8} */
39488 +  {
39489 +    { 0, 0, 0, 0 },
39490 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), 0 } },
39491 +    & ifmt_lea_4_d_immediate_4_s1_ea_immediate, { 0xf800 }
39492 +  },
39493 +/* lea.1 (${d-An},${d-r}),#${s1-imm8} */
39494 +  {
39495 +    { 0, 0, 0, 0 },
39496 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), 0 } },
39497 +    & ifmt_lea_4_d_indirect_with_index_4_s1_ea_immediate, { 0x300f800 }
39498 +  },
39499 +/* lea.1 ${d-imm7-4}(${d-An}),#${s1-imm8} */
39500 +  {
39501 +    { 0, 0, 0, 0 },
39502 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } },
39503 +    & ifmt_lea_4_d_indirect_with_offset_4_s1_ea_immediate, { 0x400f800 }
39504 +  },
39505 +/* lea.1 (${d-An}),#${s1-imm8} */
39506 +  {
39507 +    { 0, 0, 0, 0 },
39508 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } },
39509 +    & ifmt_lea_4_d_indirect_4_s1_ea_immediate, { 0x400f800 }
39510 +  },
39511 +/* lea.1 (${d-An})${d-i4-4}++,#${s1-imm8} */
39512 +  {
39513 +    { 0, 0, 0, 0 },
39514 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '#', OP (S1_IMM8), 0 } },
39515 +    & ifmt_lea_4_d_indirect_with_post_increment_4_s1_ea_immediate, { 0x200f800 }
39516 +  },
39517 +/* lea.1 ${d-i4-4}(${d-An})++,#${s1-imm8} */
39518 +  {
39519 +    { 0, 0, 0, 0 },
39520 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), 0 } },
39521 +    & ifmt_lea_4_d_indirect_with_pre_increment_4_s1_ea_immediate, { 0x210f800 }
39522 +  },
39523 +/* cmpi ${s1-direct-addr},#${imm16-1} */
39524 +  {
39525 +    { 0, 0, 0, 0 },
39526 +    { { MNEM, ' ', OP (S1_DIRECT_ADDR), ',', '#', OP (IMM16_1), 0 } },
39527 +    & ifmt_cmpi_s1_direct, { 0xc0000100 }
39528 +  },
39529 +/* cmpi #${s1-imm8},#${imm16-1} */
39530 +  {
39531 +    { 0, 0, 0, 0 },
39532 +    { { MNEM, ' ', '#', OP (S1_IMM8), ',', '#', OP (IMM16_1), 0 } },
39533 +    & ifmt_cmpi_s1_immediate, { 0xc0000000 }
39534 +  },
39535 +/* cmpi (${s1-An},${s1-r}),#${imm16-1} */
39536 +  {
39537 +    { 0, 0, 0, 0 },
39538 +    { { MNEM, ' ', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', '#', OP (IMM16_1), 0 } },
39539 +    & ifmt_cmpi_s1_indirect_with_index_2, { 0xc0000300 }
39540 +  },
39541 +/* cmpi ${s1-imm7-2}(${s1-An}),#${imm16-1} */
39542 +  {
39543 +    { 0, 0, 0, 0 },
39544 +    { { MNEM, ' ', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', '#', OP (IMM16_1), 0 } },
39545 +    & ifmt_cmpi_s1_indirect_with_offset_2, { 0xc0000400 }
39546 +  },
39547 +/* cmpi (${s1-An}),#${imm16-1} */
39548 +  {
39549 +    { 0, 0, 0, 0 },
39550 +    { { MNEM, ' ', '(', OP (S1_AN), ')', ',', '#', OP (IMM16_1), 0 } },
39551 +    & ifmt_cmpi_s1_indirect_2, { 0xc0000400 }
39552 +  },
39553 +/* cmpi (${s1-An})${s1-i4-2}++,#${imm16-1} */
39554 +  {
39555 +    { 0, 0, 0, 0 },
39556 +    { { MNEM, ' ', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', '#', OP (IMM16_1), 0 } },
39557 +    & ifmt_cmpi_s1_indirect_with_post_increment_2, { 0xc0000200 }
39558 +  },
39559 +/* cmpi ${s1-i4-2}(${s1-An})++,#${imm16-1} */
39560 +  {
39561 +    { 0, 0, 0, 0 },
39562 +    { { MNEM, ' ', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', '#', OP (IMM16_1), 0 } },
39563 +    & ifmt_cmpi_s1_indirect_with_pre_increment_2, { 0xc0000210 }
39564 +  },
39565 +/* pxadds.u ${d-direct-addr},${s1-direct-addr},${s2} */
39566 +  {
39567 +    { 0, 0, 0, 0 },
39568 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
39569 +    & ifmt_pxadds_u_d_direct_s1_direct, { 0xb1008100 }
39570 +  },
39571 +/* pxadds.u #${d-imm8},${s1-direct-addr},${s2} */
39572 +  {
39573 +    { 0, 0, 0, 0 },
39574 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
39575 +    & ifmt_pxadds_u_d_immediate_2_s1_direct, { 0xb0008100 }
39576 +  },
39577 +/* pxadds.u (${d-An},${d-r}),${s1-direct-addr},${s2} */
39578 +  {
39579 +    { 0, 0, 0, 0 },
39580 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
39581 +    & ifmt_pxadds_u_d_indirect_with_index_2_s1_direct, { 0xb3008100 }
39582 +  },
39583 +/* pxadds.u ${d-imm7-2}(${d-An}),${s1-direct-addr},${s2} */
39584 +  {
39585 +    { 0, 0, 0, 0 },
39586 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
39587 +    & ifmt_pxadds_u_d_indirect_with_offset_2_s1_direct, { 0xb4008100 }
39588 +  },
39589 +/* pxadds.u (${d-An}),${s1-direct-addr},${s2} */
39590 +  {
39591 +    { 0, 0, 0, 0 },
39592 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
39593 +    & ifmt_pxadds_u_d_indirect_2_s1_direct, { 0xb4008100 }
39594 +  },
39595 +/* pxadds.u (${d-An})${d-i4-2}++,${s1-direct-addr},${s2} */
39596 +  {
39597 +    { 0, 0, 0, 0 },
39598 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
39599 +    & ifmt_pxadds_u_d_indirect_with_post_increment_2_s1_direct, { 0xb2008100 }
39600 +  },
39601 +/* pxadds.u ${d-i4-2}(${d-An})++,${s1-direct-addr},${s2} */
39602 +  {
39603 +    { 0, 0, 0, 0 },
39604 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
39605 +    & ifmt_pxadds_u_d_indirect_with_pre_increment_2_s1_direct, { 0xb2108100 }
39606 +  },
39607 +/* pxadds.u ${d-direct-addr},#${s1-imm8},${s2} */
39608 +  {
39609 +    { 0, 0, 0, 0 },
39610 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
39611 +    & ifmt_pxadds_u_d_direct_s1_immediate, { 0xb1008000 }
39612 +  },
39613 +/* pxadds.u #${d-imm8},#${s1-imm8},${s2} */
39614 +  {
39615 +    { 0, 0, 0, 0 },
39616 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
39617 +    & ifmt_pxadds_u_d_immediate_2_s1_immediate, { 0xb0008000 }
39618 +  },
39619 +/* pxadds.u (${d-An},${d-r}),#${s1-imm8},${s2} */
39620 +  {
39621 +    { 0, 0, 0, 0 },
39622 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
39623 +    & ifmt_pxadds_u_d_indirect_with_index_2_s1_immediate, { 0xb3008000 }
39624 +  },
39625 +/* pxadds.u ${d-imm7-2}(${d-An}),#${s1-imm8},${s2} */
39626 +  {
39627 +    { 0, 0, 0, 0 },
39628 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
39629 +    & ifmt_pxadds_u_d_indirect_with_offset_2_s1_immediate, { 0xb4008000 }
39630 +  },
39631 +/* pxadds.u (${d-An}),#${s1-imm8},${s2} */
39632 +  {
39633 +    { 0, 0, 0, 0 },
39634 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
39635 +    & ifmt_pxadds_u_d_indirect_2_s1_immediate, { 0xb4008000 }
39636 +  },
39637 +/* pxadds.u (${d-An})${d-i4-2}++,#${s1-imm8},${s2} */
39638 +  {
39639 +    { 0, 0, 0, 0 },
39640 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
39641 +    & ifmt_pxadds_u_d_indirect_with_post_increment_2_s1_immediate, { 0xb2008000 }
39642 +  },
39643 +/* pxadds.u ${d-i4-2}(${d-An})++,#${s1-imm8},${s2} */
39644 +  {
39645 +    { 0, 0, 0, 0 },
39646 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
39647 +    & ifmt_pxadds_u_d_indirect_with_pre_increment_2_s1_immediate, { 0xb2108000 }
39648 +  },
39649 +/* pxadds.u ${d-direct-addr},(${s1-An},${s1-r}),${s2} */
39650 +  {
39651 +    { 0, 0, 0, 0 },
39652 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
39653 +    & ifmt_pxadds_u_d_direct_s1_indirect_with_index_4, { 0xb1008300 }
39654 +  },
39655 +/* pxadds.u #${d-imm8},(${s1-An},${s1-r}),${s2} */
39656 +  {
39657 +    { 0, 0, 0, 0 },
39658 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
39659 +    & ifmt_pxadds_u_d_immediate_2_s1_indirect_with_index_4, { 0xb0008300 }
39660 +  },
39661 +/* pxadds.u (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */
39662 +  {
39663 +    { 0, 0, 0, 0 },
39664 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
39665 +    & ifmt_pxadds_u_d_indirect_with_index_2_s1_indirect_with_index_4, { 0xb3008300 }
39666 +  },
39667 +/* pxadds.u ${d-imm7-2}(${d-An}),(${s1-An},${s1-r}),${s2} */
39668 +  {
39669 +    { 0, 0, 0, 0 },
39670 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
39671 +    & ifmt_pxadds_u_d_indirect_with_offset_2_s1_indirect_with_index_4, { 0xb4008300 }
39672 +  },
39673 +/* pxadds.u (${d-An}),(${s1-An},${s1-r}),${s2} */
39674 +  {
39675 +    { 0, 0, 0, 0 },
39676 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
39677 +    & ifmt_pxadds_u_d_indirect_2_s1_indirect_with_index_4, { 0xb4008300 }
39678 +  },
39679 +/* pxadds.u (${d-An})${d-i4-2}++,(${s1-An},${s1-r}),${s2} */
39680 +  {
39681 +    { 0, 0, 0, 0 },
39682 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
39683 +    & ifmt_pxadds_u_d_indirect_with_post_increment_2_s1_indirect_with_index_4, { 0xb2008300 }
39684 +  },
39685 +/* pxadds.u ${d-i4-2}(${d-An})++,(${s1-An},${s1-r}),${s2} */
39686 +  {
39687 +    { 0, 0, 0, 0 },
39688 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
39689 +    & ifmt_pxadds_u_d_indirect_with_pre_increment_2_s1_indirect_with_index_4, { 0xb2108300 }
39690 +  },
39691 +/* pxadds.u ${d-direct-addr},${s1-imm7-4}(${s1-An}),${s2} */
39692 +  {
39693 +    { 0, 0, 0, 0 },
39694 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
39695 +    & ifmt_pxadds_u_d_direct_s1_indirect_with_offset_4, { 0xb1008400 }
39696 +  },
39697 +/* pxadds.u #${d-imm8},${s1-imm7-4}(${s1-An}),${s2} */
39698 +  {
39699 +    { 0, 0, 0, 0 },
39700 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
39701 +    & ifmt_pxadds_u_d_immediate_2_s1_indirect_with_offset_4, { 0xb0008400 }
39702 +  },
39703 +/* pxadds.u (${d-An},${d-r}),${s1-imm7-4}(${s1-An}),${s2} */
39704 +  {
39705 +    { 0, 0, 0, 0 },
39706 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
39707 +    & ifmt_pxadds_u_d_indirect_with_index_2_s1_indirect_with_offset_4, { 0xb3008400 }
39708 +  },
39709 +/* pxadds.u ${d-imm7-2}(${d-An}),${s1-imm7-4}(${s1-An}),${s2} */
39710 +  {
39711 +    { 0, 0, 0, 0 },
39712 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
39713 +    & ifmt_pxadds_u_d_indirect_with_offset_2_s1_indirect_with_offset_4, { 0xb4008400 }
39714 +  },
39715 +/* pxadds.u (${d-An}),${s1-imm7-4}(${s1-An}),${s2} */
39716 +  {
39717 +    { 0, 0, 0, 0 },
39718 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
39719 +    & ifmt_pxadds_u_d_indirect_2_s1_indirect_with_offset_4, { 0xb4008400 }
39720 +  },
39721 +/* pxadds.u (${d-An})${d-i4-2}++,${s1-imm7-4}(${s1-An}),${s2} */
39722 +  {
39723 +    { 0, 0, 0, 0 },
39724 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
39725 +    & ifmt_pxadds_u_d_indirect_with_post_increment_2_s1_indirect_with_offset_4, { 0xb2008400 }
39726 +  },
39727 +/* pxadds.u ${d-i4-2}(${d-An})++,${s1-imm7-4}(${s1-An}),${s2} */
39728 +  {
39729 +    { 0, 0, 0, 0 },
39730 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
39731 +    & ifmt_pxadds_u_d_indirect_with_pre_increment_2_s1_indirect_with_offset_4, { 0xb2108400 }
39732 +  },
39733 +/* pxadds.u ${d-direct-addr},(${s1-An}),${s2} */
39734 +  {
39735 +    { 0, 0, 0, 0 },
39736 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
39737 +    & ifmt_pxadds_u_d_direct_s1_indirect_4, { 0xb1008400 }
39738 +  },
39739 +/* pxadds.u #${d-imm8},(${s1-An}),${s2} */
39740 +  {
39741 +    { 0, 0, 0, 0 },
39742 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
39743 +    & ifmt_pxadds_u_d_immediate_2_s1_indirect_4, { 0xb0008400 }
39744 +  },
39745 +/* pxadds.u (${d-An},${d-r}),(${s1-An}),${s2} */
39746 +  {
39747 +    { 0, 0, 0, 0 },
39748 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
39749 +    & ifmt_pxadds_u_d_indirect_with_index_2_s1_indirect_4, { 0xb3008400 }
39750 +  },
39751 +/* pxadds.u ${d-imm7-2}(${d-An}),(${s1-An}),${s2} */
39752 +  {
39753 +    { 0, 0, 0, 0 },
39754 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
39755 +    & ifmt_pxadds_u_d_indirect_with_offset_2_s1_indirect_4, { 0xb4008400 }
39756 +  },
39757 +/* pxadds.u (${d-An}),(${s1-An}),${s2} */
39758 +  {
39759 +    { 0, 0, 0, 0 },
39760 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
39761 +    & ifmt_pxadds_u_d_indirect_2_s1_indirect_4, { 0xb4008400 }
39762 +  },
39763 +/* pxadds.u (${d-An})${d-i4-2}++,(${s1-An}),${s2} */
39764 +  {
39765 +    { 0, 0, 0, 0 },
39766 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
39767 +    & ifmt_pxadds_u_d_indirect_with_post_increment_2_s1_indirect_4, { 0xb2008400 }
39768 +  },
39769 +/* pxadds.u ${d-i4-2}(${d-An})++,(${s1-An}),${s2} */
39770 +  {
39771 +    { 0, 0, 0, 0 },
39772 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
39773 +    & ifmt_pxadds_u_d_indirect_with_pre_increment_2_s1_indirect_4, { 0xb2108400 }
39774 +  },
39775 +/* pxadds.u ${d-direct-addr},(${s1-An})${s1-i4-4}++,${s2} */
39776 +  {
39777 +    { 0, 0, 0, 0 },
39778 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
39779 +    & ifmt_pxadds_u_d_direct_s1_indirect_with_post_increment_4, { 0xb1008200 }
39780 +  },
39781 +/* pxadds.u #${d-imm8},(${s1-An})${s1-i4-4}++,${s2} */
39782 +  {
39783 +    { 0, 0, 0, 0 },
39784 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
39785 +    & ifmt_pxadds_u_d_immediate_2_s1_indirect_with_post_increment_4, { 0xb0008200 }
39786 +  },
39787 +/* pxadds.u (${d-An},${d-r}),(${s1-An})${s1-i4-4}++,${s2} */
39788 +  {
39789 +    { 0, 0, 0, 0 },
39790 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
39791 +    & ifmt_pxadds_u_d_indirect_with_index_2_s1_indirect_with_post_increment_4, { 0xb3008200 }
39792 +  },
39793 +/* pxadds.u ${d-imm7-2}(${d-An}),(${s1-An})${s1-i4-4}++,${s2} */
39794 +  {
39795 +    { 0, 0, 0, 0 },
39796 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
39797 +    & ifmt_pxadds_u_d_indirect_with_offset_2_s1_indirect_with_post_increment_4, { 0xb4008200 }
39798 +  },
39799 +/* pxadds.u (${d-An}),(${s1-An})${s1-i4-4}++,${s2} */
39800 +  {
39801 +    { 0, 0, 0, 0 },
39802 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
39803 +    & ifmt_pxadds_u_d_indirect_2_s1_indirect_with_post_increment_4, { 0xb4008200 }
39804 +  },
39805 +/* pxadds.u (${d-An})${d-i4-2}++,(${s1-An})${s1-i4-4}++,${s2} */
39806 +  {
39807 +    { 0, 0, 0, 0 },
39808 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
39809 +    & ifmt_pxadds_u_d_indirect_with_post_increment_2_s1_indirect_with_post_increment_4, { 0xb2008200 }
39810 +  },
39811 +/* pxadds.u ${d-i4-2}(${d-An})++,(${s1-An})${s1-i4-4}++,${s2} */
39812 +  {
39813 +    { 0, 0, 0, 0 },
39814 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
39815 +    & ifmt_pxadds_u_d_indirect_with_pre_increment_2_s1_indirect_with_post_increment_4, { 0xb2108200 }
39816 +  },
39817 +/* pxadds.u ${d-direct-addr},${s1-i4-4}(${s1-An})++,${s2} */
39818 +  {
39819 +    { 0, 0, 0, 0 },
39820 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
39821 +    & ifmt_pxadds_u_d_direct_s1_indirect_with_pre_increment_4, { 0xb1008210 }
39822 +  },
39823 +/* pxadds.u #${d-imm8},${s1-i4-4}(${s1-An})++,${s2} */
39824 +  {
39825 +    { 0, 0, 0, 0 },
39826 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
39827 +    & ifmt_pxadds_u_d_immediate_2_s1_indirect_with_pre_increment_4, { 0xb0008210 }
39828 +  },
39829 +/* pxadds.u (${d-An},${d-r}),${s1-i4-4}(${s1-An})++,${s2} */
39830 +  {
39831 +    { 0, 0, 0, 0 },
39832 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
39833 +    & ifmt_pxadds_u_d_indirect_with_index_2_s1_indirect_with_pre_increment_4, { 0xb3008210 }
39834 +  },
39835 +/* pxadds.u ${d-imm7-2}(${d-An}),${s1-i4-4}(${s1-An})++,${s2} */
39836 +  {
39837 +    { 0, 0, 0, 0 },
39838 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
39839 +    & ifmt_pxadds_u_d_indirect_with_offset_2_s1_indirect_with_pre_increment_4, { 0xb4008210 }
39840 +  },
39841 +/* pxadds.u (${d-An}),${s1-i4-4}(${s1-An})++,${s2} */
39842 +  {
39843 +    { 0, 0, 0, 0 },
39844 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
39845 +    & ifmt_pxadds_u_d_indirect_2_s1_indirect_with_pre_increment_4, { 0xb4008210 }
39846 +  },
39847 +/* pxadds.u (${d-An})${d-i4-2}++,${s1-i4-4}(${s1-An})++,${s2} */
39848 +  {
39849 +    { 0, 0, 0, 0 },
39850 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
39851 +    & ifmt_pxadds_u_d_indirect_with_post_increment_2_s1_indirect_with_pre_increment_4, { 0xb2008210 }
39852 +  },
39853 +/* pxadds.u ${d-i4-2}(${d-An})++,${s1-i4-4}(${s1-An})++,${s2} */
39854 +  {
39855 +    { 0, 0, 0, 0 },
39856 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
39857 +    & ifmt_pxadds_u_d_indirect_with_pre_increment_2_s1_indirect_with_pre_increment_4, { 0xb2108210 }
39858 +  },
39859 +/* pxadds ${d-direct-addr},${s1-direct-addr},${s2} */
39860 +  {
39861 +    { 0, 0, 0, 0 },
39862 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
39863 +    & ifmt_pxadds_u_d_direct_s1_direct, { 0xb1000100 }
39864 +  },
39865 +/* pxadds #${d-imm8},${s1-direct-addr},${s2} */
39866 +  {
39867 +    { 0, 0, 0, 0 },
39868 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
39869 +    & ifmt_pxadds_u_d_immediate_2_s1_direct, { 0xb0000100 }
39870 +  },
39871 +/* pxadds (${d-An},${d-r}),${s1-direct-addr},${s2} */
39872 +  {
39873 +    { 0, 0, 0, 0 },
39874 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
39875 +    & ifmt_pxadds_u_d_indirect_with_index_2_s1_direct, { 0xb3000100 }
39876 +  },
39877 +/* pxadds ${d-imm7-2}(${d-An}),${s1-direct-addr},${s2} */
39878 +  {
39879 +    { 0, 0, 0, 0 },
39880 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
39881 +    & ifmt_pxadds_u_d_indirect_with_offset_2_s1_direct, { 0xb4000100 }
39882 +  },
39883 +/* pxadds (${d-An}),${s1-direct-addr},${s2} */
39884 +  {
39885 +    { 0, 0, 0, 0 },
39886 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
39887 +    & ifmt_pxadds_u_d_indirect_2_s1_direct, { 0xb4000100 }
39888 +  },
39889 +/* pxadds (${d-An})${d-i4-2}++,${s1-direct-addr},${s2} */
39890 +  {
39891 +    { 0, 0, 0, 0 },
39892 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
39893 +    & ifmt_pxadds_u_d_indirect_with_post_increment_2_s1_direct, { 0xb2000100 }
39894 +  },
39895 +/* pxadds ${d-i4-2}(${d-An})++,${s1-direct-addr},${s2} */
39896 +  {
39897 +    { 0, 0, 0, 0 },
39898 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
39899 +    & ifmt_pxadds_u_d_indirect_with_pre_increment_2_s1_direct, { 0xb2100100 }
39900 +  },
39901 +/* pxadds ${d-direct-addr},#${s1-imm8},${s2} */
39902 +  {
39903 +    { 0, 0, 0, 0 },
39904 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
39905 +    & ifmt_pxadds_u_d_direct_s1_immediate, { 0xb1000000 }
39906 +  },
39907 +/* pxadds #${d-imm8},#${s1-imm8},${s2} */
39908 +  {
39909 +    { 0, 0, 0, 0 },
39910 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
39911 +    & ifmt_pxadds_u_d_immediate_2_s1_immediate, { 0xb0000000 }
39912 +  },
39913 +/* pxadds (${d-An},${d-r}),#${s1-imm8},${s2} */
39914 +  {
39915 +    { 0, 0, 0, 0 },
39916 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
39917 +    & ifmt_pxadds_u_d_indirect_with_index_2_s1_immediate, { 0xb3000000 }
39918 +  },
39919 +/* pxadds ${d-imm7-2}(${d-An}),#${s1-imm8},${s2} */
39920 +  {
39921 +    { 0, 0, 0, 0 },
39922 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
39923 +    & ifmt_pxadds_u_d_indirect_with_offset_2_s1_immediate, { 0xb4000000 }
39924 +  },
39925 +/* pxadds (${d-An}),#${s1-imm8},${s2} */
39926 +  {
39927 +    { 0, 0, 0, 0 },
39928 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
39929 +    & ifmt_pxadds_u_d_indirect_2_s1_immediate, { 0xb4000000 }
39930 +  },
39931 +/* pxadds (${d-An})${d-i4-2}++,#${s1-imm8},${s2} */
39932 +  {
39933 +    { 0, 0, 0, 0 },
39934 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
39935 +    & ifmt_pxadds_u_d_indirect_with_post_increment_2_s1_immediate, { 0xb2000000 }
39936 +  },
39937 +/* pxadds ${d-i4-2}(${d-An})++,#${s1-imm8},${s2} */
39938 +  {
39939 +    { 0, 0, 0, 0 },
39940 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
39941 +    & ifmt_pxadds_u_d_indirect_with_pre_increment_2_s1_immediate, { 0xb2100000 }
39942 +  },
39943 +/* pxadds ${d-direct-addr},(${s1-An},${s1-r}),${s2} */
39944 +  {
39945 +    { 0, 0, 0, 0 },
39946 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
39947 +    & ifmt_pxadds_u_d_direct_s1_indirect_with_index_4, { 0xb1000300 }
39948 +  },
39949 +/* pxadds #${d-imm8},(${s1-An},${s1-r}),${s2} */
39950 +  {
39951 +    { 0, 0, 0, 0 },
39952 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
39953 +    & ifmt_pxadds_u_d_immediate_2_s1_indirect_with_index_4, { 0xb0000300 }
39954 +  },
39955 +/* pxadds (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */
39956 +  {
39957 +    { 0, 0, 0, 0 },
39958 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
39959 +    & ifmt_pxadds_u_d_indirect_with_index_2_s1_indirect_with_index_4, { 0xb3000300 }
39960 +  },
39961 +/* pxadds ${d-imm7-2}(${d-An}),(${s1-An},${s1-r}),${s2} */
39962 +  {
39963 +    { 0, 0, 0, 0 },
39964 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
39965 +    & ifmt_pxadds_u_d_indirect_with_offset_2_s1_indirect_with_index_4, { 0xb4000300 }
39966 +  },
39967 +/* pxadds (${d-An}),(${s1-An},${s1-r}),${s2} */
39968 +  {
39969 +    { 0, 0, 0, 0 },
39970 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
39971 +    & ifmt_pxadds_u_d_indirect_2_s1_indirect_with_index_4, { 0xb4000300 }
39972 +  },
39973 +/* pxadds (${d-An})${d-i4-2}++,(${s1-An},${s1-r}),${s2} */
39974 +  {
39975 +    { 0, 0, 0, 0 },
39976 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
39977 +    & ifmt_pxadds_u_d_indirect_with_post_increment_2_s1_indirect_with_index_4, { 0xb2000300 }
39978 +  },
39979 +/* pxadds ${d-i4-2}(${d-An})++,(${s1-An},${s1-r}),${s2} */
39980 +  {
39981 +    { 0, 0, 0, 0 },
39982 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
39983 +    & ifmt_pxadds_u_d_indirect_with_pre_increment_2_s1_indirect_with_index_4, { 0xb2100300 }
39984 +  },
39985 +/* pxadds ${d-direct-addr},${s1-imm7-4}(${s1-An}),${s2} */
39986 +  {
39987 +    { 0, 0, 0, 0 },
39988 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
39989 +    & ifmt_pxadds_u_d_direct_s1_indirect_with_offset_4, { 0xb1000400 }
39990 +  },
39991 +/* pxadds #${d-imm8},${s1-imm7-4}(${s1-An}),${s2} */
39992 +  {
39993 +    { 0, 0, 0, 0 },
39994 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
39995 +    & ifmt_pxadds_u_d_immediate_2_s1_indirect_with_offset_4, { 0xb0000400 }
39996 +  },
39997 +/* pxadds (${d-An},${d-r}),${s1-imm7-4}(${s1-An}),${s2} */
39998 +  {
39999 +    { 0, 0, 0, 0 },
40000 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
40001 +    & ifmt_pxadds_u_d_indirect_with_index_2_s1_indirect_with_offset_4, { 0xb3000400 }
40002 +  },
40003 +/* pxadds ${d-imm7-2}(${d-An}),${s1-imm7-4}(${s1-An}),${s2} */
40004 +  {
40005 +    { 0, 0, 0, 0 },
40006 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
40007 +    & ifmt_pxadds_u_d_indirect_with_offset_2_s1_indirect_with_offset_4, { 0xb4000400 }
40008 +  },
40009 +/* pxadds (${d-An}),${s1-imm7-4}(${s1-An}),${s2} */
40010 +  {
40011 +    { 0, 0, 0, 0 },
40012 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
40013 +    & ifmt_pxadds_u_d_indirect_2_s1_indirect_with_offset_4, { 0xb4000400 }
40014 +  },
40015 +/* pxadds (${d-An})${d-i4-2}++,${s1-imm7-4}(${s1-An}),${s2} */
40016 +  {
40017 +    { 0, 0, 0, 0 },
40018 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
40019 +    & ifmt_pxadds_u_d_indirect_with_post_increment_2_s1_indirect_with_offset_4, { 0xb2000400 }
40020 +  },
40021 +/* pxadds ${d-i4-2}(${d-An})++,${s1-imm7-4}(${s1-An}),${s2} */
40022 +  {
40023 +    { 0, 0, 0, 0 },
40024 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
40025 +    & ifmt_pxadds_u_d_indirect_with_pre_increment_2_s1_indirect_with_offset_4, { 0xb2100400 }
40026 +  },
40027 +/* pxadds ${d-direct-addr},(${s1-An}),${s2} */
40028 +  {
40029 +    { 0, 0, 0, 0 },
40030 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
40031 +    & ifmt_pxadds_u_d_direct_s1_indirect_4, { 0xb1000400 }
40032 +  },
40033 +/* pxadds #${d-imm8},(${s1-An}),${s2} */
40034 +  {
40035 +    { 0, 0, 0, 0 },
40036 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
40037 +    & ifmt_pxadds_u_d_immediate_2_s1_indirect_4, { 0xb0000400 }
40038 +  },
40039 +/* pxadds (${d-An},${d-r}),(${s1-An}),${s2} */
40040 +  {
40041 +    { 0, 0, 0, 0 },
40042 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
40043 +    & ifmt_pxadds_u_d_indirect_with_index_2_s1_indirect_4, { 0xb3000400 }
40044 +  },
40045 +/* pxadds ${d-imm7-2}(${d-An}),(${s1-An}),${s2} */
40046 +  {
40047 +    { 0, 0, 0, 0 },
40048 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
40049 +    & ifmt_pxadds_u_d_indirect_with_offset_2_s1_indirect_4, { 0xb4000400 }
40050 +  },
40051 +/* pxadds (${d-An}),(${s1-An}),${s2} */
40052 +  {
40053 +    { 0, 0, 0, 0 },
40054 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
40055 +    & ifmt_pxadds_u_d_indirect_2_s1_indirect_4, { 0xb4000400 }
40056 +  },
40057 +/* pxadds (${d-An})${d-i4-2}++,(${s1-An}),${s2} */
40058 +  {
40059 +    { 0, 0, 0, 0 },
40060 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
40061 +    & ifmt_pxadds_u_d_indirect_with_post_increment_2_s1_indirect_4, { 0xb2000400 }
40062 +  },
40063 +/* pxadds ${d-i4-2}(${d-An})++,(${s1-An}),${s2} */
40064 +  {
40065 +    { 0, 0, 0, 0 },
40066 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
40067 +    & ifmt_pxadds_u_d_indirect_with_pre_increment_2_s1_indirect_4, { 0xb2100400 }
40068 +  },
40069 +/* pxadds ${d-direct-addr},(${s1-An})${s1-i4-4}++,${s2} */
40070 +  {
40071 +    { 0, 0, 0, 0 },
40072 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
40073 +    & ifmt_pxadds_u_d_direct_s1_indirect_with_post_increment_4, { 0xb1000200 }
40074 +  },
40075 +/* pxadds #${d-imm8},(${s1-An})${s1-i4-4}++,${s2} */
40076 +  {
40077 +    { 0, 0, 0, 0 },
40078 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
40079 +    & ifmt_pxadds_u_d_immediate_2_s1_indirect_with_post_increment_4, { 0xb0000200 }
40080 +  },
40081 +/* pxadds (${d-An},${d-r}),(${s1-An})${s1-i4-4}++,${s2} */
40082 +  {
40083 +    { 0, 0, 0, 0 },
40084 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
40085 +    & ifmt_pxadds_u_d_indirect_with_index_2_s1_indirect_with_post_increment_4, { 0xb3000200 }
40086 +  },
40087 +/* pxadds ${d-imm7-2}(${d-An}),(${s1-An})${s1-i4-4}++,${s2} */
40088 +  {
40089 +    { 0, 0, 0, 0 },
40090 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
40091 +    & ifmt_pxadds_u_d_indirect_with_offset_2_s1_indirect_with_post_increment_4, { 0xb4000200 }
40092 +  },
40093 +/* pxadds (${d-An}),(${s1-An})${s1-i4-4}++,${s2} */
40094 +  {
40095 +    { 0, 0, 0, 0 },
40096 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
40097 +    & ifmt_pxadds_u_d_indirect_2_s1_indirect_with_post_increment_4, { 0xb4000200 }
40098 +  },
40099 +/* pxadds (${d-An})${d-i4-2}++,(${s1-An})${s1-i4-4}++,${s2} */
40100 +  {
40101 +    { 0, 0, 0, 0 },
40102 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
40103 +    & ifmt_pxadds_u_d_indirect_with_post_increment_2_s1_indirect_with_post_increment_4, { 0xb2000200 }
40104 +  },
40105 +/* pxadds ${d-i4-2}(${d-An})++,(${s1-An})${s1-i4-4}++,${s2} */
40106 +  {
40107 +    { 0, 0, 0, 0 },
40108 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
40109 +    & ifmt_pxadds_u_d_indirect_with_pre_increment_2_s1_indirect_with_post_increment_4, { 0xb2100200 }
40110 +  },
40111 +/* pxadds ${d-direct-addr},${s1-i4-4}(${s1-An})++,${s2} */
40112 +  {
40113 +    { 0, 0, 0, 0 },
40114 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
40115 +    & ifmt_pxadds_u_d_direct_s1_indirect_with_pre_increment_4, { 0xb1000210 }
40116 +  },
40117 +/* pxadds #${d-imm8},${s1-i4-4}(${s1-An})++,${s2} */
40118 +  {
40119 +    { 0, 0, 0, 0 },
40120 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
40121 +    & ifmt_pxadds_u_d_immediate_2_s1_indirect_with_pre_increment_4, { 0xb0000210 }
40122 +  },
40123 +/* pxadds (${d-An},${d-r}),${s1-i4-4}(${s1-An})++,${s2} */
40124 +  {
40125 +    { 0, 0, 0, 0 },
40126 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
40127 +    & ifmt_pxadds_u_d_indirect_with_index_2_s1_indirect_with_pre_increment_4, { 0xb3000210 }
40128 +  },
40129 +/* pxadds ${d-imm7-2}(${d-An}),${s1-i4-4}(${s1-An})++,${s2} */
40130 +  {
40131 +    { 0, 0, 0, 0 },
40132 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
40133 +    & ifmt_pxadds_u_d_indirect_with_offset_2_s1_indirect_with_pre_increment_4, { 0xb4000210 }
40134 +  },
40135 +/* pxadds (${d-An}),${s1-i4-4}(${s1-An})++,${s2} */
40136 +  {
40137 +    { 0, 0, 0, 0 },
40138 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
40139 +    & ifmt_pxadds_u_d_indirect_2_s1_indirect_with_pre_increment_4, { 0xb4000210 }
40140 +  },
40141 +/* pxadds (${d-An})${d-i4-2}++,${s1-i4-4}(${s1-An})++,${s2} */
40142 +  {
40143 +    { 0, 0, 0, 0 },
40144 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
40145 +    & ifmt_pxadds_u_d_indirect_with_post_increment_2_s1_indirect_with_pre_increment_4, { 0xb2000210 }
40146 +  },
40147 +/* pxadds ${d-i4-2}(${d-An})++,${s1-i4-4}(${s1-An})++,${s2} */
40148 +  {
40149 +    { 0, 0, 0, 0 },
40150 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
40151 +    & ifmt_pxadds_u_d_indirect_with_pre_increment_2_s1_indirect_with_pre_increment_4, { 0xb2100210 }
40152 +  },
40153 +/* pxhi.s ${Dn},${s1-direct-addr},${s2} */
40154 +  {
40155 +    { 0, 0, 0, 0 },
40156 +    { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
40157 +    & ifmt_pxhi_s_s1_direct, { 0x14408100 }
40158 +  },
40159 +/* pxhi.s ${Dn},#${s1-imm8},${s2} */
40160 +  {
40161 +    { 0, 0, 0, 0 },
40162 +    { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
40163 +    & ifmt_pxhi_s_s1_immediate, { 0x14408000 }
40164 +  },
40165 +/* pxhi.s ${Dn},(${s1-An},${s1-r}),${s2} */
40166 +  {
40167 +    { 0, 0, 0, 0 },
40168 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
40169 +    & ifmt_pxhi_s_s1_indirect_with_index_4, { 0x14408300 }
40170 +  },
40171 +/* pxhi.s ${Dn},${s1-imm7-4}(${s1-An}),${s2} */
40172 +  {
40173 +    { 0, 0, 0, 0 },
40174 +    { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
40175 +    & ifmt_pxhi_s_s1_indirect_with_offset_4, { 0x14408400 }
40176 +  },
40177 +/* pxhi.s ${Dn},(${s1-An}),${s2} */
40178 +  {
40179 +    { 0, 0, 0, 0 },
40180 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
40181 +    & ifmt_pxhi_s_s1_indirect_4, { 0x14408400 }
40182 +  },
40183 +/* pxhi.s ${Dn},(${s1-An})${s1-i4-4}++,${s2} */
40184 +  {
40185 +    { 0, 0, 0, 0 },
40186 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
40187 +    & ifmt_pxhi_s_s1_indirect_with_post_increment_4, { 0x14408200 }
40188 +  },
40189 +/* pxhi.s ${Dn},${s1-i4-4}(${s1-An})++,${s2} */
40190 +  {
40191 +    { 0, 0, 0, 0 },
40192 +    { { MNEM, ' ', OP (DN), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
40193 +    & ifmt_pxhi_s_s1_indirect_with_pre_increment_4, { 0x14408210 }
40194 +  },
40195 +/* pxhi ${Dn},${s1-direct-addr},${s2} */
40196 +  {
40197 +    { 0, 0, 0, 0 },
40198 +    { { MNEM, ' ', OP (DN), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
40199 +    & ifmt_pxhi_s_s1_direct, { 0x14000100 }
40200 +  },
40201 +/* pxhi ${Dn},#${s1-imm8},${s2} */
40202 +  {
40203 +    { 0, 0, 0, 0 },
40204 +    { { MNEM, ' ', OP (DN), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
40205 +    & ifmt_pxhi_s_s1_immediate, { 0x14000000 }
40206 +  },
40207 +/* pxhi ${Dn},(${s1-An},${s1-r}),${s2} */
40208 +  {
40209 +    { 0, 0, 0, 0 },
40210 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
40211 +    & ifmt_pxhi_s_s1_indirect_with_index_4, { 0x14000300 }
40212 +  },
40213 +/* pxhi ${Dn},${s1-imm7-4}(${s1-An}),${s2} */
40214 +  {
40215 +    { 0, 0, 0, 0 },
40216 +    { { MNEM, ' ', OP (DN), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
40217 +    & ifmt_pxhi_s_s1_indirect_with_offset_4, { 0x14000400 }
40218 +  },
40219 +/* pxhi ${Dn},(${s1-An}),${s2} */
40220 +  {
40221 +    { 0, 0, 0, 0 },
40222 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
40223 +    & ifmt_pxhi_s_s1_indirect_4, { 0x14000400 }
40224 +  },
40225 +/* pxhi ${Dn},(${s1-An})${s1-i4-4}++,${s2} */
40226 +  {
40227 +    { 0, 0, 0, 0 },
40228 +    { { MNEM, ' ', OP (DN), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
40229 +    & ifmt_pxhi_s_s1_indirect_with_post_increment_4, { 0x14000200 }
40230 +  },
40231 +/* pxhi ${Dn},${s1-i4-4}(${s1-An})++,${s2} */
40232 +  {
40233 +    { 0, 0, 0, 0 },
40234 +    { { MNEM, ' ', OP (DN), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
40235 +    & ifmt_pxhi_s_s1_indirect_with_pre_increment_4, { 0x14000210 }
40236 +  },
40237 +/* pxvi.s ${d-direct-addr},${s1-direct-addr},${s2} */
40238 +  {
40239 +    { 0, 0, 0, 0 },
40240 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
40241 +    & ifmt_pxadds_u_d_direct_s1_direct, { 0xa9008100 }
40242 +  },
40243 +/* pxvi.s #${d-imm8},${s1-direct-addr},${s2} */
40244 +  {
40245 +    { 0, 0, 0, 0 },
40246 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
40247 +    & ifmt_pxvi_s_d_immediate_4_s1_direct, { 0xa8008100 }
40248 +  },
40249 +/* pxvi.s (${d-An},${d-r}),${s1-direct-addr},${s2} */
40250 +  {
40251 +    { 0, 0, 0, 0 },
40252 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
40253 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_direct, { 0xab008100 }
40254 +  },
40255 +/* pxvi.s ${d-imm7-4}(${d-An}),${s1-direct-addr},${s2} */
40256 +  {
40257 +    { 0, 0, 0, 0 },
40258 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
40259 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_direct, { 0xac008100 }
40260 +  },
40261 +/* pxvi.s (${d-An}),${s1-direct-addr},${s2} */
40262 +  {
40263 +    { 0, 0, 0, 0 },
40264 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
40265 +    & ifmt_pxvi_s_d_indirect_4_s1_direct, { 0xac008100 }
40266 +  },
40267 +/* pxvi.s (${d-An})${d-i4-4}++,${s1-direct-addr},${s2} */
40268 +  {
40269 +    { 0, 0, 0, 0 },
40270 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
40271 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_direct, { 0xaa008100 }
40272 +  },
40273 +/* pxvi.s ${d-i4-4}(${d-An})++,${s1-direct-addr},${s2} */
40274 +  {
40275 +    { 0, 0, 0, 0 },
40276 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
40277 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_direct, { 0xaa108100 }
40278 +  },
40279 +/* pxvi.s ${d-direct-addr},#${s1-imm8},${s2} */
40280 +  {
40281 +    { 0, 0, 0, 0 },
40282 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
40283 +    & ifmt_pxadds_u_d_direct_s1_immediate, { 0xa9008000 }
40284 +  },
40285 +/* pxvi.s #${d-imm8},#${s1-imm8},${s2} */
40286 +  {
40287 +    { 0, 0, 0, 0 },
40288 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
40289 +    & ifmt_pxvi_s_d_immediate_4_s1_immediate, { 0xa8008000 }
40290 +  },
40291 +/* pxvi.s (${d-An},${d-r}),#${s1-imm8},${s2} */
40292 +  {
40293 +    { 0, 0, 0, 0 },
40294 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
40295 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_immediate, { 0xab008000 }
40296 +  },
40297 +/* pxvi.s ${d-imm7-4}(${d-An}),#${s1-imm8},${s2} */
40298 +  {
40299 +    { 0, 0, 0, 0 },
40300 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
40301 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_immediate, { 0xac008000 }
40302 +  },
40303 +/* pxvi.s (${d-An}),#${s1-imm8},${s2} */
40304 +  {
40305 +    { 0, 0, 0, 0 },
40306 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
40307 +    & ifmt_pxvi_s_d_indirect_4_s1_immediate, { 0xac008000 }
40308 +  },
40309 +/* pxvi.s (${d-An})${d-i4-4}++,#${s1-imm8},${s2} */
40310 +  {
40311 +    { 0, 0, 0, 0 },
40312 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
40313 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_immediate, { 0xaa008000 }
40314 +  },
40315 +/* pxvi.s ${d-i4-4}(${d-An})++,#${s1-imm8},${s2} */
40316 +  {
40317 +    { 0, 0, 0, 0 },
40318 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
40319 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_immediate, { 0xaa108000 }
40320 +  },
40321 +/* pxvi.s ${d-direct-addr},(${s1-An},${s1-r}),${s2} */
40322 +  {
40323 +    { 0, 0, 0, 0 },
40324 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
40325 +    & ifmt_pxadds_u_d_direct_s1_indirect_with_index_4, { 0xa9008300 }
40326 +  },
40327 +/* pxvi.s #${d-imm8},(${s1-An},${s1-r}),${s2} */
40328 +  {
40329 +    { 0, 0, 0, 0 },
40330 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
40331 +    & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_index_4, { 0xa8008300 }
40332 +  },
40333 +/* pxvi.s (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */
40334 +  {
40335 +    { 0, 0, 0, 0 },
40336 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
40337 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_index_4, { 0xab008300 }
40338 +  },
40339 +/* pxvi.s ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}),${s2} */
40340 +  {
40341 +    { 0, 0, 0, 0 },
40342 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
40343 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_index_4, { 0xac008300 }
40344 +  },
40345 +/* pxvi.s (${d-An}),(${s1-An},${s1-r}),${s2} */
40346 +  {
40347 +    { 0, 0, 0, 0 },
40348 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
40349 +    & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_index_4, { 0xac008300 }
40350 +  },
40351 +/* pxvi.s (${d-An})${d-i4-4}++,(${s1-An},${s1-r}),${s2} */
40352 +  {
40353 +    { 0, 0, 0, 0 },
40354 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
40355 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_index_4, { 0xaa008300 }
40356 +  },
40357 +/* pxvi.s ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}),${s2} */
40358 +  {
40359 +    { 0, 0, 0, 0 },
40360 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
40361 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_index_4, { 0xaa108300 }
40362 +  },
40363 +/* pxvi.s ${d-direct-addr},${s1-imm7-4}(${s1-An}),${s2} */
40364 +  {
40365 +    { 0, 0, 0, 0 },
40366 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
40367 +    & ifmt_pxadds_u_d_direct_s1_indirect_with_offset_4, { 0xa9008400 }
40368 +  },
40369 +/* pxvi.s #${d-imm8},${s1-imm7-4}(${s1-An}),${s2} */
40370 +  {
40371 +    { 0, 0, 0, 0 },
40372 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
40373 +    & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_offset_4, { 0xa8008400 }
40374 +  },
40375 +/* pxvi.s (${d-An},${d-r}),${s1-imm7-4}(${s1-An}),${s2} */
40376 +  {
40377 +    { 0, 0, 0, 0 },
40378 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
40379 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_offset_4, { 0xab008400 }
40380 +  },
40381 +/* pxvi.s ${d-imm7-4}(${d-An}),${s1-imm7-4}(${s1-An}),${s2} */
40382 +  {
40383 +    { 0, 0, 0, 0 },
40384 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
40385 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_offset_4, { 0xac008400 }
40386 +  },
40387 +/* pxvi.s (${d-An}),${s1-imm7-4}(${s1-An}),${s2} */
40388 +  {
40389 +    { 0, 0, 0, 0 },
40390 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
40391 +    & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_offset_4, { 0xac008400 }
40392 +  },
40393 +/* pxvi.s (${d-An})${d-i4-4}++,${s1-imm7-4}(${s1-An}),${s2} */
40394 +  {
40395 +    { 0, 0, 0, 0 },
40396 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
40397 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_offset_4, { 0xaa008400 }
40398 +  },
40399 +/* pxvi.s ${d-i4-4}(${d-An})++,${s1-imm7-4}(${s1-An}),${s2} */
40400 +  {
40401 +    { 0, 0, 0, 0 },
40402 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
40403 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_offset_4, { 0xaa108400 }
40404 +  },
40405 +/* pxvi.s ${d-direct-addr},(${s1-An}),${s2} */
40406 +  {
40407 +    { 0, 0, 0, 0 },
40408 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
40409 +    & ifmt_pxadds_u_d_direct_s1_indirect_4, { 0xa9008400 }
40410 +  },
40411 +/* pxvi.s #${d-imm8},(${s1-An}),${s2} */
40412 +  {
40413 +    { 0, 0, 0, 0 },
40414 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
40415 +    & ifmt_pxvi_s_d_immediate_4_s1_indirect_4, { 0xa8008400 }
40416 +  },
40417 +/* pxvi.s (${d-An},${d-r}),(${s1-An}),${s2} */
40418 +  {
40419 +    { 0, 0, 0, 0 },
40420 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
40421 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_4, { 0xab008400 }
40422 +  },
40423 +/* pxvi.s ${d-imm7-4}(${d-An}),(${s1-An}),${s2} */
40424 +  {
40425 +    { 0, 0, 0, 0 },
40426 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
40427 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_4, { 0xac008400 }
40428 +  },
40429 +/* pxvi.s (${d-An}),(${s1-An}),${s2} */
40430 +  {
40431 +    { 0, 0, 0, 0 },
40432 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
40433 +    & ifmt_pxvi_s_d_indirect_4_s1_indirect_4, { 0xac008400 }
40434 +  },
40435 +/* pxvi.s (${d-An})${d-i4-4}++,(${s1-An}),${s2} */
40436 +  {
40437 +    { 0, 0, 0, 0 },
40438 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
40439 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_4, { 0xaa008400 }
40440 +  },
40441 +/* pxvi.s ${d-i4-4}(${d-An})++,(${s1-An}),${s2} */
40442 +  {
40443 +    { 0, 0, 0, 0 },
40444 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
40445 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_4, { 0xaa108400 }
40446 +  },
40447 +/* pxvi.s ${d-direct-addr},(${s1-An})${s1-i4-4}++,${s2} */
40448 +  {
40449 +    { 0, 0, 0, 0 },
40450 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
40451 +    & ifmt_pxadds_u_d_direct_s1_indirect_with_post_increment_4, { 0xa9008200 }
40452 +  },
40453 +/* pxvi.s #${d-imm8},(${s1-An})${s1-i4-4}++,${s2} */
40454 +  {
40455 +    { 0, 0, 0, 0 },
40456 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
40457 +    & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_post_increment_4, { 0xa8008200 }
40458 +  },
40459 +/* pxvi.s (${d-An},${d-r}),(${s1-An})${s1-i4-4}++,${s2} */
40460 +  {
40461 +    { 0, 0, 0, 0 },
40462 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
40463 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_post_increment_4, { 0xab008200 }
40464 +  },
40465 +/* pxvi.s ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-4}++,${s2} */
40466 +  {
40467 +    { 0, 0, 0, 0 },
40468 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
40469 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_post_increment_4, { 0xac008200 }
40470 +  },
40471 +/* pxvi.s (${d-An}),(${s1-An})${s1-i4-4}++,${s2} */
40472 +  {
40473 +    { 0, 0, 0, 0 },
40474 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
40475 +    & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_post_increment_4, { 0xac008200 }
40476 +  },
40477 +/* pxvi.s (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-4}++,${s2} */
40478 +  {
40479 +    { 0, 0, 0, 0 },
40480 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
40481 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_post_increment_4, { 0xaa008200 }
40482 +  },
40483 +/* pxvi.s ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-4}++,${s2} */
40484 +  {
40485 +    { 0, 0, 0, 0 },
40486 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
40487 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_post_increment_4, { 0xaa108200 }
40488 +  },
40489 +/* pxvi.s ${d-direct-addr},${s1-i4-4}(${s1-An})++,${s2} */
40490 +  {
40491 +    { 0, 0, 0, 0 },
40492 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
40493 +    & ifmt_pxadds_u_d_direct_s1_indirect_with_pre_increment_4, { 0xa9008210 }
40494 +  },
40495 +/* pxvi.s #${d-imm8},${s1-i4-4}(${s1-An})++,${s2} */
40496 +  {
40497 +    { 0, 0, 0, 0 },
40498 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
40499 +    & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_pre_increment_4, { 0xa8008210 }
40500 +  },
40501 +/* pxvi.s (${d-An},${d-r}),${s1-i4-4}(${s1-An})++,${s2} */
40502 +  {
40503 +    { 0, 0, 0, 0 },
40504 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
40505 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_pre_increment_4, { 0xab008210 }
40506 +  },
40507 +/* pxvi.s ${d-imm7-4}(${d-An}),${s1-i4-4}(${s1-An})++,${s2} */
40508 +  {
40509 +    { 0, 0, 0, 0 },
40510 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
40511 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_pre_increment_4, { 0xac008210 }
40512 +  },
40513 +/* pxvi.s (${d-An}),${s1-i4-4}(${s1-An})++,${s2} */
40514 +  {
40515 +    { 0, 0, 0, 0 },
40516 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
40517 +    & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_pre_increment_4, { 0xac008210 }
40518 +  },
40519 +/* pxvi.s (${d-An})${d-i4-4}++,${s1-i4-4}(${s1-An})++,${s2} */
40520 +  {
40521 +    { 0, 0, 0, 0 },
40522 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
40523 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_pre_increment_4, { 0xaa008210 }
40524 +  },
40525 +/* pxvi.s ${d-i4-4}(${d-An})++,${s1-i4-4}(${s1-An})++,${s2} */
40526 +  {
40527 +    { 0, 0, 0, 0 },
40528 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
40529 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_pre_increment_4, { 0xaa108210 }
40530 +  },
40531 +/* pxvi ${d-direct-addr},${s1-direct-addr},${s2} */
40532 +  {
40533 +    { 0, 0, 0, 0 },
40534 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
40535 +    & ifmt_pxadds_u_d_direct_s1_direct, { 0xa9000100 }
40536 +  },
40537 +/* pxvi #${d-imm8},${s1-direct-addr},${s2} */
40538 +  {
40539 +    { 0, 0, 0, 0 },
40540 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
40541 +    & ifmt_pxvi_s_d_immediate_4_s1_direct, { 0xa8000100 }
40542 +  },
40543 +/* pxvi (${d-An},${d-r}),${s1-direct-addr},${s2} */
40544 +  {
40545 +    { 0, 0, 0, 0 },
40546 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
40547 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_direct, { 0xab000100 }
40548 +  },
40549 +/* pxvi ${d-imm7-4}(${d-An}),${s1-direct-addr},${s2} */
40550 +  {
40551 +    { 0, 0, 0, 0 },
40552 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
40553 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_direct, { 0xac000100 }
40554 +  },
40555 +/* pxvi (${d-An}),${s1-direct-addr},${s2} */
40556 +  {
40557 +    { 0, 0, 0, 0 },
40558 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
40559 +    & ifmt_pxvi_s_d_indirect_4_s1_direct, { 0xac000100 }
40560 +  },
40561 +/* pxvi (${d-An})${d-i4-4}++,${s1-direct-addr},${s2} */
40562 +  {
40563 +    { 0, 0, 0, 0 },
40564 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
40565 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_direct, { 0xaa000100 }
40566 +  },
40567 +/* pxvi ${d-i4-4}(${d-An})++,${s1-direct-addr},${s2} */
40568 +  {
40569 +    { 0, 0, 0, 0 },
40570 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
40571 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_direct, { 0xaa100100 }
40572 +  },
40573 +/* pxvi ${d-direct-addr},#${s1-imm8},${s2} */
40574 +  {
40575 +    { 0, 0, 0, 0 },
40576 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
40577 +    & ifmt_pxadds_u_d_direct_s1_immediate, { 0xa9000000 }
40578 +  },
40579 +/* pxvi #${d-imm8},#${s1-imm8},${s2} */
40580 +  {
40581 +    { 0, 0, 0, 0 },
40582 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
40583 +    & ifmt_pxvi_s_d_immediate_4_s1_immediate, { 0xa8000000 }
40584 +  },
40585 +/* pxvi (${d-An},${d-r}),#${s1-imm8},${s2} */
40586 +  {
40587 +    { 0, 0, 0, 0 },
40588 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
40589 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_immediate, { 0xab000000 }
40590 +  },
40591 +/* pxvi ${d-imm7-4}(${d-An}),#${s1-imm8},${s2} */
40592 +  {
40593 +    { 0, 0, 0, 0 },
40594 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
40595 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_immediate, { 0xac000000 }
40596 +  },
40597 +/* pxvi (${d-An}),#${s1-imm8},${s2} */
40598 +  {
40599 +    { 0, 0, 0, 0 },
40600 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
40601 +    & ifmt_pxvi_s_d_indirect_4_s1_immediate, { 0xac000000 }
40602 +  },
40603 +/* pxvi (${d-An})${d-i4-4}++,#${s1-imm8},${s2} */
40604 +  {
40605 +    { 0, 0, 0, 0 },
40606 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
40607 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_immediate, { 0xaa000000 }
40608 +  },
40609 +/* pxvi ${d-i4-4}(${d-An})++,#${s1-imm8},${s2} */
40610 +  {
40611 +    { 0, 0, 0, 0 },
40612 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
40613 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_immediate, { 0xaa100000 }
40614 +  },
40615 +/* pxvi ${d-direct-addr},(${s1-An},${s1-r}),${s2} */
40616 +  {
40617 +    { 0, 0, 0, 0 },
40618 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
40619 +    & ifmt_pxadds_u_d_direct_s1_indirect_with_index_4, { 0xa9000300 }
40620 +  },
40621 +/* pxvi #${d-imm8},(${s1-An},${s1-r}),${s2} */
40622 +  {
40623 +    { 0, 0, 0, 0 },
40624 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
40625 +    & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_index_4, { 0xa8000300 }
40626 +  },
40627 +/* pxvi (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */
40628 +  {
40629 +    { 0, 0, 0, 0 },
40630 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
40631 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_index_4, { 0xab000300 }
40632 +  },
40633 +/* pxvi ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}),${s2} */
40634 +  {
40635 +    { 0, 0, 0, 0 },
40636 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
40637 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_index_4, { 0xac000300 }
40638 +  },
40639 +/* pxvi (${d-An}),(${s1-An},${s1-r}),${s2} */
40640 +  {
40641 +    { 0, 0, 0, 0 },
40642 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
40643 +    & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_index_4, { 0xac000300 }
40644 +  },
40645 +/* pxvi (${d-An})${d-i4-4}++,(${s1-An},${s1-r}),${s2} */
40646 +  {
40647 +    { 0, 0, 0, 0 },
40648 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
40649 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_index_4, { 0xaa000300 }
40650 +  },
40651 +/* pxvi ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}),${s2} */
40652 +  {
40653 +    { 0, 0, 0, 0 },
40654 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
40655 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_index_4, { 0xaa100300 }
40656 +  },
40657 +/* pxvi ${d-direct-addr},${s1-imm7-4}(${s1-An}),${s2} */
40658 +  {
40659 +    { 0, 0, 0, 0 },
40660 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
40661 +    & ifmt_pxadds_u_d_direct_s1_indirect_with_offset_4, { 0xa9000400 }
40662 +  },
40663 +/* pxvi #${d-imm8},${s1-imm7-4}(${s1-An}),${s2} */
40664 +  {
40665 +    { 0, 0, 0, 0 },
40666 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
40667 +    & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_offset_4, { 0xa8000400 }
40668 +  },
40669 +/* pxvi (${d-An},${d-r}),${s1-imm7-4}(${s1-An}),${s2} */
40670 +  {
40671 +    { 0, 0, 0, 0 },
40672 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
40673 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_offset_4, { 0xab000400 }
40674 +  },
40675 +/* pxvi ${d-imm7-4}(${d-An}),${s1-imm7-4}(${s1-An}),${s2} */
40676 +  {
40677 +    { 0, 0, 0, 0 },
40678 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
40679 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_offset_4, { 0xac000400 }
40680 +  },
40681 +/* pxvi (${d-An}),${s1-imm7-4}(${s1-An}),${s2} */
40682 +  {
40683 +    { 0, 0, 0, 0 },
40684 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
40685 +    & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_offset_4, { 0xac000400 }
40686 +  },
40687 +/* pxvi (${d-An})${d-i4-4}++,${s1-imm7-4}(${s1-An}),${s2} */
40688 +  {
40689 +    { 0, 0, 0, 0 },
40690 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
40691 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_offset_4, { 0xaa000400 }
40692 +  },
40693 +/* pxvi ${d-i4-4}(${d-An})++,${s1-imm7-4}(${s1-An}),${s2} */
40694 +  {
40695 +    { 0, 0, 0, 0 },
40696 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
40697 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_offset_4, { 0xaa100400 }
40698 +  },
40699 +/* pxvi ${d-direct-addr},(${s1-An}),${s2} */
40700 +  {
40701 +    { 0, 0, 0, 0 },
40702 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
40703 +    & ifmt_pxadds_u_d_direct_s1_indirect_4, { 0xa9000400 }
40704 +  },
40705 +/* pxvi #${d-imm8},(${s1-An}),${s2} */
40706 +  {
40707 +    { 0, 0, 0, 0 },
40708 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
40709 +    & ifmt_pxvi_s_d_immediate_4_s1_indirect_4, { 0xa8000400 }
40710 +  },
40711 +/* pxvi (${d-An},${d-r}),(${s1-An}),${s2} */
40712 +  {
40713 +    { 0, 0, 0, 0 },
40714 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
40715 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_4, { 0xab000400 }
40716 +  },
40717 +/* pxvi ${d-imm7-4}(${d-An}),(${s1-An}),${s2} */
40718 +  {
40719 +    { 0, 0, 0, 0 },
40720 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
40721 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_4, { 0xac000400 }
40722 +  },
40723 +/* pxvi (${d-An}),(${s1-An}),${s2} */
40724 +  {
40725 +    { 0, 0, 0, 0 },
40726 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
40727 +    & ifmt_pxvi_s_d_indirect_4_s1_indirect_4, { 0xac000400 }
40728 +  },
40729 +/* pxvi (${d-An})${d-i4-4}++,(${s1-An}),${s2} */
40730 +  {
40731 +    { 0, 0, 0, 0 },
40732 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
40733 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_4, { 0xaa000400 }
40734 +  },
40735 +/* pxvi ${d-i4-4}(${d-An})++,(${s1-An}),${s2} */
40736 +  {
40737 +    { 0, 0, 0, 0 },
40738 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
40739 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_4, { 0xaa100400 }
40740 +  },
40741 +/* pxvi ${d-direct-addr},(${s1-An})${s1-i4-4}++,${s2} */
40742 +  {
40743 +    { 0, 0, 0, 0 },
40744 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
40745 +    & ifmt_pxadds_u_d_direct_s1_indirect_with_post_increment_4, { 0xa9000200 }
40746 +  },
40747 +/* pxvi #${d-imm8},(${s1-An})${s1-i4-4}++,${s2} */
40748 +  {
40749 +    { 0, 0, 0, 0 },
40750 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
40751 +    & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_post_increment_4, { 0xa8000200 }
40752 +  },
40753 +/* pxvi (${d-An},${d-r}),(${s1-An})${s1-i4-4}++,${s2} */
40754 +  {
40755 +    { 0, 0, 0, 0 },
40756 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
40757 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_post_increment_4, { 0xab000200 }
40758 +  },
40759 +/* pxvi ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-4}++,${s2} */
40760 +  {
40761 +    { 0, 0, 0, 0 },
40762 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
40763 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_post_increment_4, { 0xac000200 }
40764 +  },
40765 +/* pxvi (${d-An}),(${s1-An})${s1-i4-4}++,${s2} */
40766 +  {
40767 +    { 0, 0, 0, 0 },
40768 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
40769 +    & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_post_increment_4, { 0xac000200 }
40770 +  },
40771 +/* pxvi (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-4}++,${s2} */
40772 +  {
40773 +    { 0, 0, 0, 0 },
40774 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
40775 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_post_increment_4, { 0xaa000200 }
40776 +  },
40777 +/* pxvi ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-4}++,${s2} */
40778 +  {
40779 +    { 0, 0, 0, 0 },
40780 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
40781 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_post_increment_4, { 0xaa100200 }
40782 +  },
40783 +/* pxvi ${d-direct-addr},${s1-i4-4}(${s1-An})++,${s2} */
40784 +  {
40785 +    { 0, 0, 0, 0 },
40786 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
40787 +    & ifmt_pxadds_u_d_direct_s1_indirect_with_pre_increment_4, { 0xa9000210 }
40788 +  },
40789 +/* pxvi #${d-imm8},${s1-i4-4}(${s1-An})++,${s2} */
40790 +  {
40791 +    { 0, 0, 0, 0 },
40792 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
40793 +    & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_pre_increment_4, { 0xa8000210 }
40794 +  },
40795 +/* pxvi (${d-An},${d-r}),${s1-i4-4}(${s1-An})++,${s2} */
40796 +  {
40797 +    { 0, 0, 0, 0 },
40798 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
40799 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_pre_increment_4, { 0xab000210 }
40800 +  },
40801 +/* pxvi ${d-imm7-4}(${d-An}),${s1-i4-4}(${s1-An})++,${s2} */
40802 +  {
40803 +    { 0, 0, 0, 0 },
40804 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
40805 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_pre_increment_4, { 0xac000210 }
40806 +  },
40807 +/* pxvi (${d-An}),${s1-i4-4}(${s1-An})++,${s2} */
40808 +  {
40809 +    { 0, 0, 0, 0 },
40810 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
40811 +    & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_pre_increment_4, { 0xac000210 }
40812 +  },
40813 +/* pxvi (${d-An})${d-i4-4}++,${s1-i4-4}(${s1-An})++,${s2} */
40814 +  {
40815 +    { 0, 0, 0, 0 },
40816 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
40817 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_pre_increment_4, { 0xaa000210 }
40818 +  },
40819 +/* pxvi ${d-i4-4}(${d-An})++,${s1-i4-4}(${s1-An})++,${s2} */
40820 +  {
40821 +    { 0, 0, 0, 0 },
40822 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
40823 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_pre_increment_4, { 0xaa100210 }
40824 +  },
40825 +/* pxblend.t ${d-direct-addr},${s1-direct-addr},${s2} */
40826 +  {
40827 +    { 0, 0, 0, 0 },
40828 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
40829 +    & ifmt_pxadds_u_d_direct_s1_direct, { 0xa1008100 }
40830 +  },
40831 +/* pxblend.t #${d-imm8},${s1-direct-addr},${s2} */
40832 +  {
40833 +    { 0, 0, 0, 0 },
40834 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
40835 +    & ifmt_pxvi_s_d_immediate_4_s1_direct, { 0xa0008100 }
40836 +  },
40837 +/* pxblend.t (${d-An},${d-r}),${s1-direct-addr},${s2} */
40838 +  {
40839 +    { 0, 0, 0, 0 },
40840 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
40841 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_direct, { 0xa3008100 }
40842 +  },
40843 +/* pxblend.t ${d-imm7-4}(${d-An}),${s1-direct-addr},${s2} */
40844 +  {
40845 +    { 0, 0, 0, 0 },
40846 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
40847 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_direct, { 0xa4008100 }
40848 +  },
40849 +/* pxblend.t (${d-An}),${s1-direct-addr},${s2} */
40850 +  {
40851 +    { 0, 0, 0, 0 },
40852 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
40853 +    & ifmt_pxvi_s_d_indirect_4_s1_direct, { 0xa4008100 }
40854 +  },
40855 +/* pxblend.t (${d-An})${d-i4-4}++,${s1-direct-addr},${s2} */
40856 +  {
40857 +    { 0, 0, 0, 0 },
40858 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
40859 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_direct, { 0xa2008100 }
40860 +  },
40861 +/* pxblend.t ${d-i4-4}(${d-An})++,${s1-direct-addr},${s2} */
40862 +  {
40863 +    { 0, 0, 0, 0 },
40864 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
40865 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_direct, { 0xa2108100 }
40866 +  },
40867 +/* pxblend.t ${d-direct-addr},#${s1-imm8},${s2} */
40868 +  {
40869 +    { 0, 0, 0, 0 },
40870 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
40871 +    & ifmt_pxadds_u_d_direct_s1_immediate, { 0xa1008000 }
40872 +  },
40873 +/* pxblend.t #${d-imm8},#${s1-imm8},${s2} */
40874 +  {
40875 +    { 0, 0, 0, 0 },
40876 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
40877 +    & ifmt_pxvi_s_d_immediate_4_s1_immediate, { 0xa0008000 }
40878 +  },
40879 +/* pxblend.t (${d-An},${d-r}),#${s1-imm8},${s2} */
40880 +  {
40881 +    { 0, 0, 0, 0 },
40882 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
40883 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_immediate, { 0xa3008000 }
40884 +  },
40885 +/* pxblend.t ${d-imm7-4}(${d-An}),#${s1-imm8},${s2} */
40886 +  {
40887 +    { 0, 0, 0, 0 },
40888 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
40889 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_immediate, { 0xa4008000 }
40890 +  },
40891 +/* pxblend.t (${d-An}),#${s1-imm8},${s2} */
40892 +  {
40893 +    { 0, 0, 0, 0 },
40894 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
40895 +    & ifmt_pxvi_s_d_indirect_4_s1_immediate, { 0xa4008000 }
40896 +  },
40897 +/* pxblend.t (${d-An})${d-i4-4}++,#${s1-imm8},${s2} */
40898 +  {
40899 +    { 0, 0, 0, 0 },
40900 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
40901 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_immediate, { 0xa2008000 }
40902 +  },
40903 +/* pxblend.t ${d-i4-4}(${d-An})++,#${s1-imm8},${s2} */
40904 +  {
40905 +    { 0, 0, 0, 0 },
40906 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
40907 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_immediate, { 0xa2108000 }
40908 +  },
40909 +/* pxblend.t ${d-direct-addr},(${s1-An},${s1-r}),${s2} */
40910 +  {
40911 +    { 0, 0, 0, 0 },
40912 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
40913 +    & ifmt_pxadds_u_d_direct_s1_indirect_with_index_4, { 0xa1008300 }
40914 +  },
40915 +/* pxblend.t #${d-imm8},(${s1-An},${s1-r}),${s2} */
40916 +  {
40917 +    { 0, 0, 0, 0 },
40918 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
40919 +    & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_index_4, { 0xa0008300 }
40920 +  },
40921 +/* pxblend.t (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */
40922 +  {
40923 +    { 0, 0, 0, 0 },
40924 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
40925 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_index_4, { 0xa3008300 }
40926 +  },
40927 +/* pxblend.t ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}),${s2} */
40928 +  {
40929 +    { 0, 0, 0, 0 },
40930 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
40931 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_index_4, { 0xa4008300 }
40932 +  },
40933 +/* pxblend.t (${d-An}),(${s1-An},${s1-r}),${s2} */
40934 +  {
40935 +    { 0, 0, 0, 0 },
40936 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
40937 +    & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_index_4, { 0xa4008300 }
40938 +  },
40939 +/* pxblend.t (${d-An})${d-i4-4}++,(${s1-An},${s1-r}),${s2} */
40940 +  {
40941 +    { 0, 0, 0, 0 },
40942 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
40943 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_index_4, { 0xa2008300 }
40944 +  },
40945 +/* pxblend.t ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}),${s2} */
40946 +  {
40947 +    { 0, 0, 0, 0 },
40948 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
40949 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_index_4, { 0xa2108300 }
40950 +  },
40951 +/* pxblend.t ${d-direct-addr},${s1-imm7-4}(${s1-An}),${s2} */
40952 +  {
40953 +    { 0, 0, 0, 0 },
40954 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
40955 +    & ifmt_pxadds_u_d_direct_s1_indirect_with_offset_4, { 0xa1008400 }
40956 +  },
40957 +/* pxblend.t #${d-imm8},${s1-imm7-4}(${s1-An}),${s2} */
40958 +  {
40959 +    { 0, 0, 0, 0 },
40960 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
40961 +    & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_offset_4, { 0xa0008400 }
40962 +  },
40963 +/* pxblend.t (${d-An},${d-r}),${s1-imm7-4}(${s1-An}),${s2} */
40964 +  {
40965 +    { 0, 0, 0, 0 },
40966 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
40967 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_offset_4, { 0xa3008400 }
40968 +  },
40969 +/* pxblend.t ${d-imm7-4}(${d-An}),${s1-imm7-4}(${s1-An}),${s2} */
40970 +  {
40971 +    { 0, 0, 0, 0 },
40972 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
40973 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_offset_4, { 0xa4008400 }
40974 +  },
40975 +/* pxblend.t (${d-An}),${s1-imm7-4}(${s1-An}),${s2} */
40976 +  {
40977 +    { 0, 0, 0, 0 },
40978 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
40979 +    & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_offset_4, { 0xa4008400 }
40980 +  },
40981 +/* pxblend.t (${d-An})${d-i4-4}++,${s1-imm7-4}(${s1-An}),${s2} */
40982 +  {
40983 +    { 0, 0, 0, 0 },
40984 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
40985 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_offset_4, { 0xa2008400 }
40986 +  },
40987 +/* pxblend.t ${d-i4-4}(${d-An})++,${s1-imm7-4}(${s1-An}),${s2} */
40988 +  {
40989 +    { 0, 0, 0, 0 },
40990 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
40991 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_offset_4, { 0xa2108400 }
40992 +  },
40993 +/* pxblend.t ${d-direct-addr},(${s1-An}),${s2} */
40994 +  {
40995 +    { 0, 0, 0, 0 },
40996 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
40997 +    & ifmt_pxadds_u_d_direct_s1_indirect_4, { 0xa1008400 }
40998 +  },
40999 +/* pxblend.t #${d-imm8},(${s1-An}),${s2} */
41000 +  {
41001 +    { 0, 0, 0, 0 },
41002 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
41003 +    & ifmt_pxvi_s_d_immediate_4_s1_indirect_4, { 0xa0008400 }
41004 +  },
41005 +/* pxblend.t (${d-An},${d-r}),(${s1-An}),${s2} */
41006 +  {
41007 +    { 0, 0, 0, 0 },
41008 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
41009 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_4, { 0xa3008400 }
41010 +  },
41011 +/* pxblend.t ${d-imm7-4}(${d-An}),(${s1-An}),${s2} */
41012 +  {
41013 +    { 0, 0, 0, 0 },
41014 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
41015 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_4, { 0xa4008400 }
41016 +  },
41017 +/* pxblend.t (${d-An}),(${s1-An}),${s2} */
41018 +  {
41019 +    { 0, 0, 0, 0 },
41020 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
41021 +    & ifmt_pxvi_s_d_indirect_4_s1_indirect_4, { 0xa4008400 }
41022 +  },
41023 +/* pxblend.t (${d-An})${d-i4-4}++,(${s1-An}),${s2} */
41024 +  {
41025 +    { 0, 0, 0, 0 },
41026 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
41027 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_4, { 0xa2008400 }
41028 +  },
41029 +/* pxblend.t ${d-i4-4}(${d-An})++,(${s1-An}),${s2} */
41030 +  {
41031 +    { 0, 0, 0, 0 },
41032 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
41033 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_4, { 0xa2108400 }
41034 +  },
41035 +/* pxblend.t ${d-direct-addr},(${s1-An})${s1-i4-4}++,${s2} */
41036 +  {
41037 +    { 0, 0, 0, 0 },
41038 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
41039 +    & ifmt_pxadds_u_d_direct_s1_indirect_with_post_increment_4, { 0xa1008200 }
41040 +  },
41041 +/* pxblend.t #${d-imm8},(${s1-An})${s1-i4-4}++,${s2} */
41042 +  {
41043 +    { 0, 0, 0, 0 },
41044 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
41045 +    & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_post_increment_4, { 0xa0008200 }
41046 +  },
41047 +/* pxblend.t (${d-An},${d-r}),(${s1-An})${s1-i4-4}++,${s2} */
41048 +  {
41049 +    { 0, 0, 0, 0 },
41050 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
41051 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_post_increment_4, { 0xa3008200 }
41052 +  },
41053 +/* pxblend.t ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-4}++,${s2} */
41054 +  {
41055 +    { 0, 0, 0, 0 },
41056 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
41057 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_post_increment_4, { 0xa4008200 }
41058 +  },
41059 +/* pxblend.t (${d-An}),(${s1-An})${s1-i4-4}++,${s2} */
41060 +  {
41061 +    { 0, 0, 0, 0 },
41062 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
41063 +    & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_post_increment_4, { 0xa4008200 }
41064 +  },
41065 +/* pxblend.t (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-4}++,${s2} */
41066 +  {
41067 +    { 0, 0, 0, 0 },
41068 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
41069 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_post_increment_4, { 0xa2008200 }
41070 +  },
41071 +/* pxblend.t ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-4}++,${s2} */
41072 +  {
41073 +    { 0, 0, 0, 0 },
41074 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
41075 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_post_increment_4, { 0xa2108200 }
41076 +  },
41077 +/* pxblend.t ${d-direct-addr},${s1-i4-4}(${s1-An})++,${s2} */
41078 +  {
41079 +    { 0, 0, 0, 0 },
41080 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
41081 +    & ifmt_pxadds_u_d_direct_s1_indirect_with_pre_increment_4, { 0xa1008210 }
41082 +  },
41083 +/* pxblend.t #${d-imm8},${s1-i4-4}(${s1-An})++,${s2} */
41084 +  {
41085 +    { 0, 0, 0, 0 },
41086 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
41087 +    & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_pre_increment_4, { 0xa0008210 }
41088 +  },
41089 +/* pxblend.t (${d-An},${d-r}),${s1-i4-4}(${s1-An})++,${s2} */
41090 +  {
41091 +    { 0, 0, 0, 0 },
41092 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
41093 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_pre_increment_4, { 0xa3008210 }
41094 +  },
41095 +/* pxblend.t ${d-imm7-4}(${d-An}),${s1-i4-4}(${s1-An})++,${s2} */
41096 +  {
41097 +    { 0, 0, 0, 0 },
41098 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
41099 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_pre_increment_4, { 0xa4008210 }
41100 +  },
41101 +/* pxblend.t (${d-An}),${s1-i4-4}(${s1-An})++,${s2} */
41102 +  {
41103 +    { 0, 0, 0, 0 },
41104 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
41105 +    & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_pre_increment_4, { 0xa4008210 }
41106 +  },
41107 +/* pxblend.t (${d-An})${d-i4-4}++,${s1-i4-4}(${s1-An})++,${s2} */
41108 +  {
41109 +    { 0, 0, 0, 0 },
41110 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
41111 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_pre_increment_4, { 0xa2008210 }
41112 +  },
41113 +/* pxblend.t ${d-i4-4}(${d-An})++,${s1-i4-4}(${s1-An})++,${s2} */
41114 +  {
41115 +    { 0, 0, 0, 0 },
41116 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
41117 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_pre_increment_4, { 0xa2108210 }
41118 +  },
41119 +/* pxblend ${d-direct-addr},${s1-direct-addr},${s2} */
41120 +  {
41121 +    { 0, 0, 0, 0 },
41122 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
41123 +    & ifmt_pxadds_u_d_direct_s1_direct, { 0xa1000100 }
41124 +  },
41125 +/* pxblend #${d-imm8},${s1-direct-addr},${s2} */
41126 +  {
41127 +    { 0, 0, 0, 0 },
41128 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
41129 +    & ifmt_pxvi_s_d_immediate_4_s1_direct, { 0xa0000100 }
41130 +  },
41131 +/* pxblend (${d-An},${d-r}),${s1-direct-addr},${s2} */
41132 +  {
41133 +    { 0, 0, 0, 0 },
41134 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
41135 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_direct, { 0xa3000100 }
41136 +  },
41137 +/* pxblend ${d-imm7-4}(${d-An}),${s1-direct-addr},${s2} */
41138 +  {
41139 +    { 0, 0, 0, 0 },
41140 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
41141 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_direct, { 0xa4000100 }
41142 +  },
41143 +/* pxblend (${d-An}),${s1-direct-addr},${s2} */
41144 +  {
41145 +    { 0, 0, 0, 0 },
41146 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
41147 +    & ifmt_pxvi_s_d_indirect_4_s1_direct, { 0xa4000100 }
41148 +  },
41149 +/* pxblend (${d-An})${d-i4-4}++,${s1-direct-addr},${s2} */
41150 +  {
41151 +    { 0, 0, 0, 0 },
41152 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
41153 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_direct, { 0xa2000100 }
41154 +  },
41155 +/* pxblend ${d-i4-4}(${d-An})++,${s1-direct-addr},${s2} */
41156 +  {
41157 +    { 0, 0, 0, 0 },
41158 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
41159 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_direct, { 0xa2100100 }
41160 +  },
41161 +/* pxblend ${d-direct-addr},#${s1-imm8},${s2} */
41162 +  {
41163 +    { 0, 0, 0, 0 },
41164 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
41165 +    & ifmt_pxadds_u_d_direct_s1_immediate, { 0xa1000000 }
41166 +  },
41167 +/* pxblend #${d-imm8},#${s1-imm8},${s2} */
41168 +  {
41169 +    { 0, 0, 0, 0 },
41170 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
41171 +    & ifmt_pxvi_s_d_immediate_4_s1_immediate, { 0xa0000000 }
41172 +  },
41173 +/* pxblend (${d-An},${d-r}),#${s1-imm8},${s2} */
41174 +  {
41175 +    { 0, 0, 0, 0 },
41176 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
41177 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_immediate, { 0xa3000000 }
41178 +  },
41179 +/* pxblend ${d-imm7-4}(${d-An}),#${s1-imm8},${s2} */
41180 +  {
41181 +    { 0, 0, 0, 0 },
41182 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
41183 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_immediate, { 0xa4000000 }
41184 +  },
41185 +/* pxblend (${d-An}),#${s1-imm8},${s2} */
41186 +  {
41187 +    { 0, 0, 0, 0 },
41188 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
41189 +    & ifmt_pxvi_s_d_indirect_4_s1_immediate, { 0xa4000000 }
41190 +  },
41191 +/* pxblend (${d-An})${d-i4-4}++,#${s1-imm8},${s2} */
41192 +  {
41193 +    { 0, 0, 0, 0 },
41194 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
41195 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_immediate, { 0xa2000000 }
41196 +  },
41197 +/* pxblend ${d-i4-4}(${d-An})++,#${s1-imm8},${s2} */
41198 +  {
41199 +    { 0, 0, 0, 0 },
41200 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
41201 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_immediate, { 0xa2100000 }
41202 +  },
41203 +/* pxblend ${d-direct-addr},(${s1-An},${s1-r}),${s2} */
41204 +  {
41205 +    { 0, 0, 0, 0 },
41206 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
41207 +    & ifmt_pxadds_u_d_direct_s1_indirect_with_index_4, { 0xa1000300 }
41208 +  },
41209 +/* pxblend #${d-imm8},(${s1-An},${s1-r}),${s2} */
41210 +  {
41211 +    { 0, 0, 0, 0 },
41212 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
41213 +    & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_index_4, { 0xa0000300 }
41214 +  },
41215 +/* pxblend (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */
41216 +  {
41217 +    { 0, 0, 0, 0 },
41218 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
41219 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_index_4, { 0xa3000300 }
41220 +  },
41221 +/* pxblend ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}),${s2} */
41222 +  {
41223 +    { 0, 0, 0, 0 },
41224 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
41225 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_index_4, { 0xa4000300 }
41226 +  },
41227 +/* pxblend (${d-An}),(${s1-An},${s1-r}),${s2} */
41228 +  {
41229 +    { 0, 0, 0, 0 },
41230 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
41231 +    & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_index_4, { 0xa4000300 }
41232 +  },
41233 +/* pxblend (${d-An})${d-i4-4}++,(${s1-An},${s1-r}),${s2} */
41234 +  {
41235 +    { 0, 0, 0, 0 },
41236 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
41237 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_index_4, { 0xa2000300 }
41238 +  },
41239 +/* pxblend ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}),${s2} */
41240 +  {
41241 +    { 0, 0, 0, 0 },
41242 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
41243 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_index_4, { 0xa2100300 }
41244 +  },
41245 +/* pxblend ${d-direct-addr},${s1-imm7-4}(${s1-An}),${s2} */
41246 +  {
41247 +    { 0, 0, 0, 0 },
41248 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
41249 +    & ifmt_pxadds_u_d_direct_s1_indirect_with_offset_4, { 0xa1000400 }
41250 +  },
41251 +/* pxblend #${d-imm8},${s1-imm7-4}(${s1-An}),${s2} */
41252 +  {
41253 +    { 0, 0, 0, 0 },
41254 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
41255 +    & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_offset_4, { 0xa0000400 }
41256 +  },
41257 +/* pxblend (${d-An},${d-r}),${s1-imm7-4}(${s1-An}),${s2} */
41258 +  {
41259 +    { 0, 0, 0, 0 },
41260 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
41261 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_offset_4, { 0xa3000400 }
41262 +  },
41263 +/* pxblend ${d-imm7-4}(${d-An}),${s1-imm7-4}(${s1-An}),${s2} */
41264 +  {
41265 +    { 0, 0, 0, 0 },
41266 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
41267 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_offset_4, { 0xa4000400 }
41268 +  },
41269 +/* pxblend (${d-An}),${s1-imm7-4}(${s1-An}),${s2} */
41270 +  {
41271 +    { 0, 0, 0, 0 },
41272 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
41273 +    & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_offset_4, { 0xa4000400 }
41274 +  },
41275 +/* pxblend (${d-An})${d-i4-4}++,${s1-imm7-4}(${s1-An}),${s2} */
41276 +  {
41277 +    { 0, 0, 0, 0 },
41278 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
41279 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_offset_4, { 0xa2000400 }
41280 +  },
41281 +/* pxblend ${d-i4-4}(${d-An})++,${s1-imm7-4}(${s1-An}),${s2} */
41282 +  {
41283 +    { 0, 0, 0, 0 },
41284 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
41285 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_offset_4, { 0xa2100400 }
41286 +  },
41287 +/* pxblend ${d-direct-addr},(${s1-An}),${s2} */
41288 +  {
41289 +    { 0, 0, 0, 0 },
41290 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
41291 +    & ifmt_pxadds_u_d_direct_s1_indirect_4, { 0xa1000400 }
41292 +  },
41293 +/* pxblend #${d-imm8},(${s1-An}),${s2} */
41294 +  {
41295 +    { 0, 0, 0, 0 },
41296 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
41297 +    & ifmt_pxvi_s_d_immediate_4_s1_indirect_4, { 0xa0000400 }
41298 +  },
41299 +/* pxblend (${d-An},${d-r}),(${s1-An}),${s2} */
41300 +  {
41301 +    { 0, 0, 0, 0 },
41302 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
41303 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_4, { 0xa3000400 }
41304 +  },
41305 +/* pxblend ${d-imm7-4}(${d-An}),(${s1-An}),${s2} */
41306 +  {
41307 +    { 0, 0, 0, 0 },
41308 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
41309 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_4, { 0xa4000400 }
41310 +  },
41311 +/* pxblend (${d-An}),(${s1-An}),${s2} */
41312 +  {
41313 +    { 0, 0, 0, 0 },
41314 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
41315 +    & ifmt_pxvi_s_d_indirect_4_s1_indirect_4, { 0xa4000400 }
41316 +  },
41317 +/* pxblend (${d-An})${d-i4-4}++,(${s1-An}),${s2} */
41318 +  {
41319 +    { 0, 0, 0, 0 },
41320 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
41321 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_4, { 0xa2000400 }
41322 +  },
41323 +/* pxblend ${d-i4-4}(${d-An})++,(${s1-An}),${s2} */
41324 +  {
41325 +    { 0, 0, 0, 0 },
41326 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
41327 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_4, { 0xa2100400 }
41328 +  },
41329 +/* pxblend ${d-direct-addr},(${s1-An})${s1-i4-4}++,${s2} */
41330 +  {
41331 +    { 0, 0, 0, 0 },
41332 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
41333 +    & ifmt_pxadds_u_d_direct_s1_indirect_with_post_increment_4, { 0xa1000200 }
41334 +  },
41335 +/* pxblend #${d-imm8},(${s1-An})${s1-i4-4}++,${s2} */
41336 +  {
41337 +    { 0, 0, 0, 0 },
41338 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
41339 +    & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_post_increment_4, { 0xa0000200 }
41340 +  },
41341 +/* pxblend (${d-An},${d-r}),(${s1-An})${s1-i4-4}++,${s2} */
41342 +  {
41343 +    { 0, 0, 0, 0 },
41344 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
41345 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_post_increment_4, { 0xa3000200 }
41346 +  },
41347 +/* pxblend ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-4}++,${s2} */
41348 +  {
41349 +    { 0, 0, 0, 0 },
41350 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
41351 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_post_increment_4, { 0xa4000200 }
41352 +  },
41353 +/* pxblend (${d-An}),(${s1-An})${s1-i4-4}++,${s2} */
41354 +  {
41355 +    { 0, 0, 0, 0 },
41356 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
41357 +    & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_post_increment_4, { 0xa4000200 }
41358 +  },
41359 +/* pxblend (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-4}++,${s2} */
41360 +  {
41361 +    { 0, 0, 0, 0 },
41362 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
41363 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_post_increment_4, { 0xa2000200 }
41364 +  },
41365 +/* pxblend ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-4}++,${s2} */
41366 +  {
41367 +    { 0, 0, 0, 0 },
41368 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
41369 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_post_increment_4, { 0xa2100200 }
41370 +  },
41371 +/* pxblend ${d-direct-addr},${s1-i4-4}(${s1-An})++,${s2} */
41372 +  {
41373 +    { 0, 0, 0, 0 },
41374 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
41375 +    & ifmt_pxadds_u_d_direct_s1_indirect_with_pre_increment_4, { 0xa1000210 }
41376 +  },
41377 +/* pxblend #${d-imm8},${s1-i4-4}(${s1-An})++,${s2} */
41378 +  {
41379 +    { 0, 0, 0, 0 },
41380 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
41381 +    & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_pre_increment_4, { 0xa0000210 }
41382 +  },
41383 +/* pxblend (${d-An},${d-r}),${s1-i4-4}(${s1-An})++,${s2} */
41384 +  {
41385 +    { 0, 0, 0, 0 },
41386 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
41387 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_pre_increment_4, { 0xa3000210 }
41388 +  },
41389 +/* pxblend ${d-imm7-4}(${d-An}),${s1-i4-4}(${s1-An})++,${s2} */
41390 +  {
41391 +    { 0, 0, 0, 0 },
41392 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
41393 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_pre_increment_4, { 0xa4000210 }
41394 +  },
41395 +/* pxblend (${d-An}),${s1-i4-4}(${s1-An})++,${s2} */
41396 +  {
41397 +    { 0, 0, 0, 0 },
41398 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
41399 +    & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_pre_increment_4, { 0xa4000210 }
41400 +  },
41401 +/* pxblend (${d-An})${d-i4-4}++,${s1-i4-4}(${s1-An})++,${s2} */
41402 +  {
41403 +    { 0, 0, 0, 0 },
41404 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
41405 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_pre_increment_4, { 0xa2000210 }
41406 +  },
41407 +/* pxblend ${d-i4-4}(${d-An})++,${s1-i4-4}(${s1-An})++,${s2} */
41408 +  {
41409 +    { 0, 0, 0, 0 },
41410 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
41411 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_pre_increment_4, { 0xa2100210 }
41412 +  },
41413 +/* pxcnv.t ${d-direct-addr},${s1-direct-addr} */
41414 +  {
41415 +    { 0, 0, 0, 0 },
41416 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), 0 } },
41417 +    & ifmt_movea_d_direct_s1_direct, { 0x100d900 }
41418 +  },
41419 +/* pxcnv.t #${d-imm8},${s1-direct-addr} */
41420 +  {
41421 +    { 0, 0, 0, 0 },
41422 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), 0 } },
41423 +    & ifmt_move_2_d_immediate_2_s1_direct, { 0xd900 }
41424 +  },
41425 +/* pxcnv.t (${d-An},${d-r}),${s1-direct-addr} */
41426 +  {
41427 +    { 0, 0, 0, 0 },
41428 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), 0 } },
41429 +    & ifmt_move_2_d_indirect_with_index_2_s1_direct, { 0x300d900 }
41430 +  },
41431 +/* pxcnv.t ${d-imm7-2}(${d-An}),${s1-direct-addr} */
41432 +  {
41433 +    { 0, 0, 0, 0 },
41434 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), 0 } },
41435 +    & ifmt_move_2_d_indirect_with_offset_2_s1_direct, { 0x400d900 }
41436 +  },
41437 +/* pxcnv.t (${d-An}),${s1-direct-addr} */
41438 +  {
41439 +    { 0, 0, 0, 0 },
41440 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), 0 } },
41441 +    & ifmt_move_2_d_indirect_2_s1_direct, { 0x400d900 }
41442 +  },
41443 +/* pxcnv.t (${d-An})${d-i4-2}++,${s1-direct-addr} */
41444 +  {
41445 +    { 0, 0, 0, 0 },
41446 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_DIRECT_ADDR), 0 } },
41447 +    & ifmt_move_2_d_indirect_with_post_increment_2_s1_direct, { 0x200d900 }
41448 +  },
41449 +/* pxcnv.t ${d-i4-2}(${d-An})++,${s1-direct-addr} */
41450 +  {
41451 +    { 0, 0, 0, 0 },
41452 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), 0 } },
41453 +    & ifmt_move_2_d_indirect_with_pre_increment_2_s1_direct, { 0x210d900 }
41454 +  },
41455 +/* pxcnv.t ${d-direct-addr},#${s1-imm8} */
41456 +  {
41457 +    { 0, 0, 0, 0 },
41458 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), 0 } },
41459 +    & ifmt_movea_d_direct_s1_immediate, { 0x100d800 }
41460 +  },
41461 +/* pxcnv.t #${d-imm8},#${s1-imm8} */
41462 +  {
41463 +    { 0, 0, 0, 0 },
41464 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), 0 } },
41465 +    & ifmt_move_2_d_immediate_2_s1_immediate, { 0xd800 }
41466 +  },
41467 +/* pxcnv.t (${d-An},${d-r}),#${s1-imm8} */
41468 +  {
41469 +    { 0, 0, 0, 0 },
41470 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), 0 } },
41471 +    & ifmt_move_2_d_indirect_with_index_2_s1_immediate, { 0x300d800 }
41472 +  },
41473 +/* pxcnv.t ${d-imm7-2}(${d-An}),#${s1-imm8} */
41474 +  {
41475 +    { 0, 0, 0, 0 },
41476 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } },
41477 +    & ifmt_move_2_d_indirect_with_offset_2_s1_immediate, { 0x400d800 }
41478 +  },
41479 +/* pxcnv.t (${d-An}),#${s1-imm8} */
41480 +  {
41481 +    { 0, 0, 0, 0 },
41482 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } },
41483 +    & ifmt_move_2_d_indirect_2_s1_immediate, { 0x400d800 }
41484 +  },
41485 +/* pxcnv.t (${d-An})${d-i4-2}++,#${s1-imm8} */
41486 +  {
41487 +    { 0, 0, 0, 0 },
41488 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '#', OP (S1_IMM8), 0 } },
41489 +    & ifmt_move_2_d_indirect_with_post_increment_2_s1_immediate, { 0x200d800 }
41490 +  },
41491 +/* pxcnv.t ${d-i4-2}(${d-An})++,#${s1-imm8} */
41492 +  {
41493 +    { 0, 0, 0, 0 },
41494 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), 0 } },
41495 +    & ifmt_move_2_d_indirect_with_pre_increment_2_s1_immediate, { 0x210d800 }
41496 +  },
41497 +/* pxcnv.t ${d-direct-addr},(${s1-An},${s1-r}) */
41498 +  {
41499 +    { 0, 0, 0, 0 },
41500 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
41501 +    & ifmt_movea_d_direct_s1_indirect_with_index_4, { 0x100db00 }
41502 +  },
41503 +/* pxcnv.t #${d-imm8},(${s1-An},${s1-r}) */
41504 +  {
41505 +    { 0, 0, 0, 0 },
41506 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
41507 +    & ifmt_pxcnv_t_d_immediate_2_s1_indirect_with_index_4, { 0xdb00 }
41508 +  },
41509 +/* pxcnv.t (${d-An},${d-r}),(${s1-An},${s1-r}) */
41510 +  {
41511 +    { 0, 0, 0, 0 },
41512 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
41513 +    & ifmt_pxcnv_t_d_indirect_with_index_2_s1_indirect_with_index_4, { 0x300db00 }
41514 +  },
41515 +/* pxcnv.t ${d-imm7-2}(${d-An}),(${s1-An},${s1-r}) */
41516 +  {
41517 +    { 0, 0, 0, 0 },
41518 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
41519 +    & ifmt_pxcnv_t_d_indirect_with_offset_2_s1_indirect_with_index_4, { 0x400db00 }
41520 +  },
41521 +/* pxcnv.t (${d-An}),(${s1-An},${s1-r}) */
41522 +  {
41523 +    { 0, 0, 0, 0 },
41524 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
41525 +    & ifmt_pxcnv_t_d_indirect_2_s1_indirect_with_index_4, { 0x400db00 }
41526 +  },
41527 +/* pxcnv.t (${d-An})${d-i4-2}++,(${s1-An},${s1-r}) */
41528 +  {
41529 +    { 0, 0, 0, 0 },
41530 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
41531 +    & ifmt_pxcnv_t_d_indirect_with_post_increment_2_s1_indirect_with_index_4, { 0x200db00 }
41532 +  },
41533 +/* pxcnv.t ${d-i4-2}(${d-An})++,(${s1-An},${s1-r}) */
41534 +  {
41535 +    { 0, 0, 0, 0 },
41536 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
41537 +    & ifmt_pxcnv_t_d_indirect_with_pre_increment_2_s1_indirect_with_index_4, { 0x210db00 }
41538 +  },
41539 +/* pxcnv.t ${d-direct-addr},${s1-imm7-4}(${s1-An}) */
41540 +  {
41541 +    { 0, 0, 0, 0 },
41542 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
41543 +    & ifmt_movea_d_direct_s1_indirect_with_offset_4, { 0x100dc00 }
41544 +  },
41545 +/* pxcnv.t #${d-imm8},${s1-imm7-4}(${s1-An}) */
41546 +  {
41547 +    { 0, 0, 0, 0 },
41548 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
41549 +    & ifmt_pxcnv_t_d_immediate_2_s1_indirect_with_offset_4, { 0xdc00 }
41550 +  },
41551 +/* pxcnv.t (${d-An},${d-r}),${s1-imm7-4}(${s1-An}) */
41552 +  {
41553 +    { 0, 0, 0, 0 },
41554 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
41555 +    & ifmt_pxcnv_t_d_indirect_with_index_2_s1_indirect_with_offset_4, { 0x300dc00 }
41556 +  },
41557 +/* pxcnv.t ${d-imm7-2}(${d-An}),${s1-imm7-4}(${s1-An}) */
41558 +  {
41559 +    { 0, 0, 0, 0 },
41560 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
41561 +    & ifmt_pxcnv_t_d_indirect_with_offset_2_s1_indirect_with_offset_4, { 0x400dc00 }
41562 +  },
41563 +/* pxcnv.t (${d-An}),${s1-imm7-4}(${s1-An}) */
41564 +  {
41565 +    { 0, 0, 0, 0 },
41566 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
41567 +    & ifmt_pxcnv_t_d_indirect_2_s1_indirect_with_offset_4, { 0x400dc00 }
41568 +  },
41569 +/* pxcnv.t (${d-An})${d-i4-2}++,${s1-imm7-4}(${s1-An}) */
41570 +  {
41571 +    { 0, 0, 0, 0 },
41572 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
41573 +    & ifmt_pxcnv_t_d_indirect_with_post_increment_2_s1_indirect_with_offset_4, { 0x200dc00 }
41574 +  },
41575 +/* pxcnv.t ${d-i4-2}(${d-An})++,${s1-imm7-4}(${s1-An}) */
41576 +  {
41577 +    { 0, 0, 0, 0 },
41578 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
41579 +    & ifmt_pxcnv_t_d_indirect_with_pre_increment_2_s1_indirect_with_offset_4, { 0x210dc00 }
41580 +  },
41581 +/* pxcnv.t ${d-direct-addr},(${s1-An}) */
41582 +  {
41583 +    { 0, 0, 0, 0 },
41584 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', 0 } },
41585 +    & ifmt_movea_d_direct_s1_indirect_4, { 0x100dc00 }
41586 +  },
41587 +/* pxcnv.t #${d-imm8},(${s1-An}) */
41588 +  {
41589 +    { 0, 0, 0, 0 },
41590 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', 0 } },
41591 +    & ifmt_pxcnv_t_d_immediate_2_s1_indirect_4, { 0xdc00 }
41592 +  },
41593 +/* pxcnv.t (${d-An},${d-r}),(${s1-An}) */
41594 +  {
41595 +    { 0, 0, 0, 0 },
41596 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', 0 } },
41597 +    & ifmt_pxcnv_t_d_indirect_with_index_2_s1_indirect_4, { 0x300dc00 }
41598 +  },
41599 +/* pxcnv.t ${d-imm7-2}(${d-An}),(${s1-An}) */
41600 +  {
41601 +    { 0, 0, 0, 0 },
41602 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } },
41603 +    & ifmt_pxcnv_t_d_indirect_with_offset_2_s1_indirect_4, { 0x400dc00 }
41604 +  },
41605 +/* pxcnv.t (${d-An}),(${s1-An}) */
41606 +  {
41607 +    { 0, 0, 0, 0 },
41608 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } },
41609 +    & ifmt_pxcnv_t_d_indirect_2_s1_indirect_4, { 0x400dc00 }
41610 +  },
41611 +/* pxcnv.t (${d-An})${d-i4-2}++,(${s1-An}) */
41612 +  {
41613 +    { 0, 0, 0, 0 },
41614 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ')', 0 } },
41615 +    & ifmt_pxcnv_t_d_indirect_with_post_increment_2_s1_indirect_4, { 0x200dc00 }
41616 +  },
41617 +/* pxcnv.t ${d-i4-2}(${d-An})++,(${s1-An}) */
41618 +  {
41619 +    { 0, 0, 0, 0 },
41620 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', 0 } },
41621 +    & ifmt_pxcnv_t_d_indirect_with_pre_increment_2_s1_indirect_4, { 0x210dc00 }
41622 +  },
41623 +/* pxcnv.t ${d-direct-addr},(${s1-An})${s1-i4-4}++ */
41624 +  {
41625 +    { 0, 0, 0, 0 },
41626 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
41627 +    & ifmt_movea_d_direct_s1_indirect_with_post_increment_4, { 0x100da00 }
41628 +  },
41629 +/* pxcnv.t #${d-imm8},(${s1-An})${s1-i4-4}++ */
41630 +  {
41631 +    { 0, 0, 0, 0 },
41632 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
41633 +    & ifmt_pxcnv_t_d_immediate_2_s1_indirect_with_post_increment_4, { 0xda00 }
41634 +  },
41635 +/* pxcnv.t (${d-An},${d-r}),(${s1-An})${s1-i4-4}++ */
41636 +  {
41637 +    { 0, 0, 0, 0 },
41638 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
41639 +    & ifmt_pxcnv_t_d_indirect_with_index_2_s1_indirect_with_post_increment_4, { 0x300da00 }
41640 +  },
41641 +/* pxcnv.t ${d-imm7-2}(${d-An}),(${s1-An})${s1-i4-4}++ */
41642 +  {
41643 +    { 0, 0, 0, 0 },
41644 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
41645 +    & ifmt_pxcnv_t_d_indirect_with_offset_2_s1_indirect_with_post_increment_4, { 0x400da00 }
41646 +  },
41647 +/* pxcnv.t (${d-An}),(${s1-An})${s1-i4-4}++ */
41648 +  {
41649 +    { 0, 0, 0, 0 },
41650 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
41651 +    & ifmt_pxcnv_t_d_indirect_2_s1_indirect_with_post_increment_4, { 0x400da00 }
41652 +  },
41653 +/* pxcnv.t (${d-An})${d-i4-2}++,(${s1-An})${s1-i4-4}++ */
41654 +  {
41655 +    { 0, 0, 0, 0 },
41656 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
41657 +    & ifmt_pxcnv_t_d_indirect_with_post_increment_2_s1_indirect_with_post_increment_4, { 0x200da00 }
41658 +  },
41659 +/* pxcnv.t ${d-i4-2}(${d-An})++,(${s1-An})${s1-i4-4}++ */
41660 +  {
41661 +    { 0, 0, 0, 0 },
41662 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
41663 +    & ifmt_pxcnv_t_d_indirect_with_pre_increment_2_s1_indirect_with_post_increment_4, { 0x210da00 }
41664 +  },
41665 +/* pxcnv.t ${d-direct-addr},${s1-i4-4}(${s1-An})++ */
41666 +  {
41667 +    { 0, 0, 0, 0 },
41668 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
41669 +    & ifmt_movea_d_direct_s1_indirect_with_pre_increment_4, { 0x100da10 }
41670 +  },
41671 +/* pxcnv.t #${d-imm8},${s1-i4-4}(${s1-An})++ */
41672 +  {
41673 +    { 0, 0, 0, 0 },
41674 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
41675 +    & ifmt_pxcnv_t_d_immediate_2_s1_indirect_with_pre_increment_4, { 0xda10 }
41676 +  },
41677 +/* pxcnv.t (${d-An},${d-r}),${s1-i4-4}(${s1-An})++ */
41678 +  {
41679 +    { 0, 0, 0, 0 },
41680 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
41681 +    & ifmt_pxcnv_t_d_indirect_with_index_2_s1_indirect_with_pre_increment_4, { 0x300da10 }
41682 +  },
41683 +/* pxcnv.t ${d-imm7-2}(${d-An}),${s1-i4-4}(${s1-An})++ */
41684 +  {
41685 +    { 0, 0, 0, 0 },
41686 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
41687 +    & ifmt_pxcnv_t_d_indirect_with_offset_2_s1_indirect_with_pre_increment_4, { 0x400da10 }
41688 +  },
41689 +/* pxcnv.t (${d-An}),${s1-i4-4}(${s1-An})++ */
41690 +  {
41691 +    { 0, 0, 0, 0 },
41692 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
41693 +    & ifmt_pxcnv_t_d_indirect_2_s1_indirect_with_pre_increment_4, { 0x400da10 }
41694 +  },
41695 +/* pxcnv.t (${d-An})${d-i4-2}++,${s1-i4-4}(${s1-An})++ */
41696 +  {
41697 +    { 0, 0, 0, 0 },
41698 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
41699 +    & ifmt_pxcnv_t_d_indirect_with_post_increment_2_s1_indirect_with_pre_increment_4, { 0x200da10 }
41700 +  },
41701 +/* pxcnv.t ${d-i4-2}(${d-An})++,${s1-i4-4}(${s1-An})++ */
41702 +  {
41703 +    { 0, 0, 0, 0 },
41704 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
41705 +    & ifmt_pxcnv_t_d_indirect_with_pre_increment_2_s1_indirect_with_pre_increment_4, { 0x210da10 }
41706 +  },
41707 +/* pxcnv ${d-direct-addr},${s1-direct-addr} */
41708 +  {
41709 +    { 0, 0, 0, 0 },
41710 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), 0 } },
41711 +    & ifmt_movea_d_direct_s1_direct, { 0x100d100 }
41712 +  },
41713 +/* pxcnv #${d-imm8},${s1-direct-addr} */
41714 +  {
41715 +    { 0, 0, 0, 0 },
41716 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), 0 } },
41717 +    & ifmt_move_2_d_immediate_2_s1_direct, { 0xd100 }
41718 +  },
41719 +/* pxcnv (${d-An},${d-r}),${s1-direct-addr} */
41720 +  {
41721 +    { 0, 0, 0, 0 },
41722 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), 0 } },
41723 +    & ifmt_move_2_d_indirect_with_index_2_s1_direct, { 0x300d100 }
41724 +  },
41725 +/* pxcnv ${d-imm7-2}(${d-An}),${s1-direct-addr} */
41726 +  {
41727 +    { 0, 0, 0, 0 },
41728 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), 0 } },
41729 +    & ifmt_move_2_d_indirect_with_offset_2_s1_direct, { 0x400d100 }
41730 +  },
41731 +/* pxcnv (${d-An}),${s1-direct-addr} */
41732 +  {
41733 +    { 0, 0, 0, 0 },
41734 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), 0 } },
41735 +    & ifmt_move_2_d_indirect_2_s1_direct, { 0x400d100 }
41736 +  },
41737 +/* pxcnv (${d-An})${d-i4-2}++,${s1-direct-addr} */
41738 +  {
41739 +    { 0, 0, 0, 0 },
41740 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_DIRECT_ADDR), 0 } },
41741 +    & ifmt_move_2_d_indirect_with_post_increment_2_s1_direct, { 0x200d100 }
41742 +  },
41743 +/* pxcnv ${d-i4-2}(${d-An})++,${s1-direct-addr} */
41744 +  {
41745 +    { 0, 0, 0, 0 },
41746 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), 0 } },
41747 +    & ifmt_move_2_d_indirect_with_pre_increment_2_s1_direct, { 0x210d100 }
41748 +  },
41749 +/* pxcnv ${d-direct-addr},#${s1-imm8} */
41750 +  {
41751 +    { 0, 0, 0, 0 },
41752 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), 0 } },
41753 +    & ifmt_movea_d_direct_s1_immediate, { 0x100d000 }
41754 +  },
41755 +/* pxcnv #${d-imm8},#${s1-imm8} */
41756 +  {
41757 +    { 0, 0, 0, 0 },
41758 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), 0 } },
41759 +    & ifmt_move_2_d_immediate_2_s1_immediate, { 0xd000 }
41760 +  },
41761 +/* pxcnv (${d-An},${d-r}),#${s1-imm8} */
41762 +  {
41763 +    { 0, 0, 0, 0 },
41764 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), 0 } },
41765 +    & ifmt_move_2_d_indirect_with_index_2_s1_immediate, { 0x300d000 }
41766 +  },
41767 +/* pxcnv ${d-imm7-2}(${d-An}),#${s1-imm8} */
41768 +  {
41769 +    { 0, 0, 0, 0 },
41770 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } },
41771 +    & ifmt_move_2_d_indirect_with_offset_2_s1_immediate, { 0x400d000 }
41772 +  },
41773 +/* pxcnv (${d-An}),#${s1-imm8} */
41774 +  {
41775 +    { 0, 0, 0, 0 },
41776 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } },
41777 +    & ifmt_move_2_d_indirect_2_s1_immediate, { 0x400d000 }
41778 +  },
41779 +/* pxcnv (${d-An})${d-i4-2}++,#${s1-imm8} */
41780 +  {
41781 +    { 0, 0, 0, 0 },
41782 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '#', OP (S1_IMM8), 0 } },
41783 +    & ifmt_move_2_d_indirect_with_post_increment_2_s1_immediate, { 0x200d000 }
41784 +  },
41785 +/* pxcnv ${d-i4-2}(${d-An})++,#${s1-imm8} */
41786 +  {
41787 +    { 0, 0, 0, 0 },
41788 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), 0 } },
41789 +    & ifmt_move_2_d_indirect_with_pre_increment_2_s1_immediate, { 0x210d000 }
41790 +  },
41791 +/* pxcnv ${d-direct-addr},(${s1-An},${s1-r}) */
41792 +  {
41793 +    { 0, 0, 0, 0 },
41794 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
41795 +    & ifmt_movea_d_direct_s1_indirect_with_index_4, { 0x100d300 }
41796 +  },
41797 +/* pxcnv #${d-imm8},(${s1-An},${s1-r}) */
41798 +  {
41799 +    { 0, 0, 0, 0 },
41800 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
41801 +    & ifmt_pxcnv_t_d_immediate_2_s1_indirect_with_index_4, { 0xd300 }
41802 +  },
41803 +/* pxcnv (${d-An},${d-r}),(${s1-An},${s1-r}) */
41804 +  {
41805 +    { 0, 0, 0, 0 },
41806 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
41807 +    & ifmt_pxcnv_t_d_indirect_with_index_2_s1_indirect_with_index_4, { 0x300d300 }
41808 +  },
41809 +/* pxcnv ${d-imm7-2}(${d-An}),(${s1-An},${s1-r}) */
41810 +  {
41811 +    { 0, 0, 0, 0 },
41812 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
41813 +    & ifmt_pxcnv_t_d_indirect_with_offset_2_s1_indirect_with_index_4, { 0x400d300 }
41814 +  },
41815 +/* pxcnv (${d-An}),(${s1-An},${s1-r}) */
41816 +  {
41817 +    { 0, 0, 0, 0 },
41818 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
41819 +    & ifmt_pxcnv_t_d_indirect_2_s1_indirect_with_index_4, { 0x400d300 }
41820 +  },
41821 +/* pxcnv (${d-An})${d-i4-2}++,(${s1-An},${s1-r}) */
41822 +  {
41823 +    { 0, 0, 0, 0 },
41824 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
41825 +    & ifmt_pxcnv_t_d_indirect_with_post_increment_2_s1_indirect_with_index_4, { 0x200d300 }
41826 +  },
41827 +/* pxcnv ${d-i4-2}(${d-An})++,(${s1-An},${s1-r}) */
41828 +  {
41829 +    { 0, 0, 0, 0 },
41830 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
41831 +    & ifmt_pxcnv_t_d_indirect_with_pre_increment_2_s1_indirect_with_index_4, { 0x210d300 }
41832 +  },
41833 +/* pxcnv ${d-direct-addr},${s1-imm7-4}(${s1-An}) */
41834 +  {
41835 +    { 0, 0, 0, 0 },
41836 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
41837 +    & ifmt_movea_d_direct_s1_indirect_with_offset_4, { 0x100d400 }
41838 +  },
41839 +/* pxcnv #${d-imm8},${s1-imm7-4}(${s1-An}) */
41840 +  {
41841 +    { 0, 0, 0, 0 },
41842 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
41843 +    & ifmt_pxcnv_t_d_immediate_2_s1_indirect_with_offset_4, { 0xd400 }
41844 +  },
41845 +/* pxcnv (${d-An},${d-r}),${s1-imm7-4}(${s1-An}) */
41846 +  {
41847 +    { 0, 0, 0, 0 },
41848 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
41849 +    & ifmt_pxcnv_t_d_indirect_with_index_2_s1_indirect_with_offset_4, { 0x300d400 }
41850 +  },
41851 +/* pxcnv ${d-imm7-2}(${d-An}),${s1-imm7-4}(${s1-An}) */
41852 +  {
41853 +    { 0, 0, 0, 0 },
41854 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
41855 +    & ifmt_pxcnv_t_d_indirect_with_offset_2_s1_indirect_with_offset_4, { 0x400d400 }
41856 +  },
41857 +/* pxcnv (${d-An}),${s1-imm7-4}(${s1-An}) */
41858 +  {
41859 +    { 0, 0, 0, 0 },
41860 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
41861 +    & ifmt_pxcnv_t_d_indirect_2_s1_indirect_with_offset_4, { 0x400d400 }
41862 +  },
41863 +/* pxcnv (${d-An})${d-i4-2}++,${s1-imm7-4}(${s1-An}) */
41864 +  {
41865 +    { 0, 0, 0, 0 },
41866 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
41867 +    & ifmt_pxcnv_t_d_indirect_with_post_increment_2_s1_indirect_with_offset_4, { 0x200d400 }
41868 +  },
41869 +/* pxcnv ${d-i4-2}(${d-An})++,${s1-imm7-4}(${s1-An}) */
41870 +  {
41871 +    { 0, 0, 0, 0 },
41872 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
41873 +    & ifmt_pxcnv_t_d_indirect_with_pre_increment_2_s1_indirect_with_offset_4, { 0x210d400 }
41874 +  },
41875 +/* pxcnv ${d-direct-addr},(${s1-An}) */
41876 +  {
41877 +    { 0, 0, 0, 0 },
41878 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', 0 } },
41879 +    & ifmt_movea_d_direct_s1_indirect_4, { 0x100d400 }
41880 +  },
41881 +/* pxcnv #${d-imm8},(${s1-An}) */
41882 +  {
41883 +    { 0, 0, 0, 0 },
41884 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', 0 } },
41885 +    & ifmt_pxcnv_t_d_immediate_2_s1_indirect_4, { 0xd400 }
41886 +  },
41887 +/* pxcnv (${d-An},${d-r}),(${s1-An}) */
41888 +  {
41889 +    { 0, 0, 0, 0 },
41890 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', 0 } },
41891 +    & ifmt_pxcnv_t_d_indirect_with_index_2_s1_indirect_4, { 0x300d400 }
41892 +  },
41893 +/* pxcnv ${d-imm7-2}(${d-An}),(${s1-An}) */
41894 +  {
41895 +    { 0, 0, 0, 0 },
41896 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } },
41897 +    & ifmt_pxcnv_t_d_indirect_with_offset_2_s1_indirect_4, { 0x400d400 }
41898 +  },
41899 +/* pxcnv (${d-An}),(${s1-An}) */
41900 +  {
41901 +    { 0, 0, 0, 0 },
41902 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } },
41903 +    & ifmt_pxcnv_t_d_indirect_2_s1_indirect_4, { 0x400d400 }
41904 +  },
41905 +/* pxcnv (${d-An})${d-i4-2}++,(${s1-An}) */
41906 +  {
41907 +    { 0, 0, 0, 0 },
41908 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ')', 0 } },
41909 +    & ifmt_pxcnv_t_d_indirect_with_post_increment_2_s1_indirect_4, { 0x200d400 }
41910 +  },
41911 +/* pxcnv ${d-i4-2}(${d-An})++,(${s1-An}) */
41912 +  {
41913 +    { 0, 0, 0, 0 },
41914 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', 0 } },
41915 +    & ifmt_pxcnv_t_d_indirect_with_pre_increment_2_s1_indirect_4, { 0x210d400 }
41916 +  },
41917 +/* pxcnv ${d-direct-addr},(${s1-An})${s1-i4-4}++ */
41918 +  {
41919 +    { 0, 0, 0, 0 },
41920 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
41921 +    & ifmt_movea_d_direct_s1_indirect_with_post_increment_4, { 0x100d200 }
41922 +  },
41923 +/* pxcnv #${d-imm8},(${s1-An})${s1-i4-4}++ */
41924 +  {
41925 +    { 0, 0, 0, 0 },
41926 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
41927 +    & ifmt_pxcnv_t_d_immediate_2_s1_indirect_with_post_increment_4, { 0xd200 }
41928 +  },
41929 +/* pxcnv (${d-An},${d-r}),(${s1-An})${s1-i4-4}++ */
41930 +  {
41931 +    { 0, 0, 0, 0 },
41932 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
41933 +    & ifmt_pxcnv_t_d_indirect_with_index_2_s1_indirect_with_post_increment_4, { 0x300d200 }
41934 +  },
41935 +/* pxcnv ${d-imm7-2}(${d-An}),(${s1-An})${s1-i4-4}++ */
41936 +  {
41937 +    { 0, 0, 0, 0 },
41938 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
41939 +    & ifmt_pxcnv_t_d_indirect_with_offset_2_s1_indirect_with_post_increment_4, { 0x400d200 }
41940 +  },
41941 +/* pxcnv (${d-An}),(${s1-An})${s1-i4-4}++ */
41942 +  {
41943 +    { 0, 0, 0, 0 },
41944 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
41945 +    & ifmt_pxcnv_t_d_indirect_2_s1_indirect_with_post_increment_4, { 0x400d200 }
41946 +  },
41947 +/* pxcnv (${d-An})${d-i4-2}++,(${s1-An})${s1-i4-4}++ */
41948 +  {
41949 +    { 0, 0, 0, 0 },
41950 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
41951 +    & ifmt_pxcnv_t_d_indirect_with_post_increment_2_s1_indirect_with_post_increment_4, { 0x200d200 }
41952 +  },
41953 +/* pxcnv ${d-i4-2}(${d-An})++,(${s1-An})${s1-i4-4}++ */
41954 +  {
41955 +    { 0, 0, 0, 0 },
41956 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
41957 +    & ifmt_pxcnv_t_d_indirect_with_pre_increment_2_s1_indirect_with_post_increment_4, { 0x210d200 }
41958 +  },
41959 +/* pxcnv ${d-direct-addr},${s1-i4-4}(${s1-An})++ */
41960 +  {
41961 +    { 0, 0, 0, 0 },
41962 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
41963 +    & ifmt_movea_d_direct_s1_indirect_with_pre_increment_4, { 0x100d210 }
41964 +  },
41965 +/* pxcnv #${d-imm8},${s1-i4-4}(${s1-An})++ */
41966 +  {
41967 +    { 0, 0, 0, 0 },
41968 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
41969 +    & ifmt_pxcnv_t_d_immediate_2_s1_indirect_with_pre_increment_4, { 0xd210 }
41970 +  },
41971 +/* pxcnv (${d-An},${d-r}),${s1-i4-4}(${s1-An})++ */
41972 +  {
41973 +    { 0, 0, 0, 0 },
41974 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
41975 +    & ifmt_pxcnv_t_d_indirect_with_index_2_s1_indirect_with_pre_increment_4, { 0x300d210 }
41976 +  },
41977 +/* pxcnv ${d-imm7-2}(${d-An}),${s1-i4-4}(${s1-An})++ */
41978 +  {
41979 +    { 0, 0, 0, 0 },
41980 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
41981 +    & ifmt_pxcnv_t_d_indirect_with_offset_2_s1_indirect_with_pre_increment_4, { 0x400d210 }
41982 +  },
41983 +/* pxcnv (${d-An}),${s1-i4-4}(${s1-An})++ */
41984 +  {
41985 +    { 0, 0, 0, 0 },
41986 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
41987 +    & ifmt_pxcnv_t_d_indirect_2_s1_indirect_with_pre_increment_4, { 0x400d210 }
41988 +  },
41989 +/* pxcnv (${d-An})${d-i4-2}++,${s1-i4-4}(${s1-An})++ */
41990 +  {
41991 +    { 0, 0, 0, 0 },
41992 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
41993 +    & ifmt_pxcnv_t_d_indirect_with_post_increment_2_s1_indirect_with_pre_increment_4, { 0x200d210 }
41994 +  },
41995 +/* pxcnv ${d-i4-2}(${d-An})++,${s1-i4-4}(${s1-An})++ */
41996 +  {
41997 +    { 0, 0, 0, 0 },
41998 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
41999 +    & ifmt_pxcnv_t_d_indirect_with_pre_increment_2_s1_indirect_with_pre_increment_4, { 0x210d210 }
42000 +  },
42001 +/* subc ${d-direct-addr},${s1-direct-addr},${s2} */
42002 +  {
42003 +    { 0, 0, 0, 0 },
42004 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
42005 +    & ifmt_pxadds_u_d_direct_s1_direct, { 0x99000100 }
42006 +  },
42007 +/* subc #${d-imm8},${s1-direct-addr},${s2} */
42008 +  {
42009 +    { 0, 0, 0, 0 },
42010 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
42011 +    & ifmt_pxvi_s_d_immediate_4_s1_direct, { 0x98000100 }
42012 +  },
42013 +/* subc (${d-An},${d-r}),${s1-direct-addr},${s2} */
42014 +  {
42015 +    { 0, 0, 0, 0 },
42016 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
42017 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_direct, { 0x9b000100 }
42018 +  },
42019 +/* subc ${d-imm7-4}(${d-An}),${s1-direct-addr},${s2} */
42020 +  {
42021 +    { 0, 0, 0, 0 },
42022 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
42023 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_direct, { 0x9c000100 }
42024 +  },
42025 +/* subc (${d-An}),${s1-direct-addr},${s2} */
42026 +  {
42027 +    { 0, 0, 0, 0 },
42028 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
42029 +    & ifmt_pxvi_s_d_indirect_4_s1_direct, { 0x9c000100 }
42030 +  },
42031 +/* subc (${d-An})${d-i4-4}++,${s1-direct-addr},${s2} */
42032 +  {
42033 +    { 0, 0, 0, 0 },
42034 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
42035 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_direct, { 0x9a000100 }
42036 +  },
42037 +/* subc ${d-i4-4}(${d-An})++,${s1-direct-addr},${s2} */
42038 +  {
42039 +    { 0, 0, 0, 0 },
42040 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
42041 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_direct, { 0x9a100100 }
42042 +  },
42043 +/* subc ${d-direct-addr},#${s1-imm8},${s2} */
42044 +  {
42045 +    { 0, 0, 0, 0 },
42046 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
42047 +    & ifmt_pxadds_u_d_direct_s1_immediate, { 0x99000000 }
42048 +  },
42049 +/* subc #${d-imm8},#${s1-imm8},${s2} */
42050 +  {
42051 +    { 0, 0, 0, 0 },
42052 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
42053 +    & ifmt_pxvi_s_d_immediate_4_s1_immediate, { 0x98000000 }
42054 +  },
42055 +/* subc (${d-An},${d-r}),#${s1-imm8},${s2} */
42056 +  {
42057 +    { 0, 0, 0, 0 },
42058 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
42059 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_immediate, { 0x9b000000 }
42060 +  },
42061 +/* subc ${d-imm7-4}(${d-An}),#${s1-imm8},${s2} */
42062 +  {
42063 +    { 0, 0, 0, 0 },
42064 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
42065 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_immediate, { 0x9c000000 }
42066 +  },
42067 +/* subc (${d-An}),#${s1-imm8},${s2} */
42068 +  {
42069 +    { 0, 0, 0, 0 },
42070 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
42071 +    & ifmt_pxvi_s_d_indirect_4_s1_immediate, { 0x9c000000 }
42072 +  },
42073 +/* subc (${d-An})${d-i4-4}++,#${s1-imm8},${s2} */
42074 +  {
42075 +    { 0, 0, 0, 0 },
42076 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
42077 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_immediate, { 0x9a000000 }
42078 +  },
42079 +/* subc ${d-i4-4}(${d-An})++,#${s1-imm8},${s2} */
42080 +  {
42081 +    { 0, 0, 0, 0 },
42082 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
42083 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_immediate, { 0x9a100000 }
42084 +  },
42085 +/* subc ${d-direct-addr},(${s1-An},${s1-r}),${s2} */
42086 +  {
42087 +    { 0, 0, 0, 0 },
42088 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
42089 +    & ifmt_pxadds_u_d_direct_s1_indirect_with_index_4, { 0x99000300 }
42090 +  },
42091 +/* subc #${d-imm8},(${s1-An},${s1-r}),${s2} */
42092 +  {
42093 +    { 0, 0, 0, 0 },
42094 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
42095 +    & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_index_4, { 0x98000300 }
42096 +  },
42097 +/* subc (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */
42098 +  {
42099 +    { 0, 0, 0, 0 },
42100 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
42101 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_index_4, { 0x9b000300 }
42102 +  },
42103 +/* subc ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}),${s2} */
42104 +  {
42105 +    { 0, 0, 0, 0 },
42106 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
42107 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_index_4, { 0x9c000300 }
42108 +  },
42109 +/* subc (${d-An}),(${s1-An},${s1-r}),${s2} */
42110 +  {
42111 +    { 0, 0, 0, 0 },
42112 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
42113 +    & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_index_4, { 0x9c000300 }
42114 +  },
42115 +/* subc (${d-An})${d-i4-4}++,(${s1-An},${s1-r}),${s2} */
42116 +  {
42117 +    { 0, 0, 0, 0 },
42118 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
42119 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_index_4, { 0x9a000300 }
42120 +  },
42121 +/* subc ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}),${s2} */
42122 +  {
42123 +    { 0, 0, 0, 0 },
42124 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
42125 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_index_4, { 0x9a100300 }
42126 +  },
42127 +/* subc ${d-direct-addr},${s1-imm7-4}(${s1-An}),${s2} */
42128 +  {
42129 +    { 0, 0, 0, 0 },
42130 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
42131 +    & ifmt_pxadds_u_d_direct_s1_indirect_with_offset_4, { 0x99000400 }
42132 +  },
42133 +/* subc #${d-imm8},${s1-imm7-4}(${s1-An}),${s2} */
42134 +  {
42135 +    { 0, 0, 0, 0 },
42136 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
42137 +    & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_offset_4, { 0x98000400 }
42138 +  },
42139 +/* subc (${d-An},${d-r}),${s1-imm7-4}(${s1-An}),${s2} */
42140 +  {
42141 +    { 0, 0, 0, 0 },
42142 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
42143 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_offset_4, { 0x9b000400 }
42144 +  },
42145 +/* subc ${d-imm7-4}(${d-An}),${s1-imm7-4}(${s1-An}),${s2} */
42146 +  {
42147 +    { 0, 0, 0, 0 },
42148 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
42149 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_offset_4, { 0x9c000400 }
42150 +  },
42151 +/* subc (${d-An}),${s1-imm7-4}(${s1-An}),${s2} */
42152 +  {
42153 +    { 0, 0, 0, 0 },
42154 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
42155 +    & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_offset_4, { 0x9c000400 }
42156 +  },
42157 +/* subc (${d-An})${d-i4-4}++,${s1-imm7-4}(${s1-An}),${s2} */
42158 +  {
42159 +    { 0, 0, 0, 0 },
42160 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
42161 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_offset_4, { 0x9a000400 }
42162 +  },
42163 +/* subc ${d-i4-4}(${d-An})++,${s1-imm7-4}(${s1-An}),${s2} */
42164 +  {
42165 +    { 0, 0, 0, 0 },
42166 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
42167 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_offset_4, { 0x9a100400 }
42168 +  },
42169 +/* subc ${d-direct-addr},(${s1-An}),${s2} */
42170 +  {
42171 +    { 0, 0, 0, 0 },
42172 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
42173 +    & ifmt_pxadds_u_d_direct_s1_indirect_4, { 0x99000400 }
42174 +  },
42175 +/* subc #${d-imm8},(${s1-An}),${s2} */
42176 +  {
42177 +    { 0, 0, 0, 0 },
42178 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
42179 +    & ifmt_pxvi_s_d_immediate_4_s1_indirect_4, { 0x98000400 }
42180 +  },
42181 +/* subc (${d-An},${d-r}),(${s1-An}),${s2} */
42182 +  {
42183 +    { 0, 0, 0, 0 },
42184 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
42185 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_4, { 0x9b000400 }
42186 +  },
42187 +/* subc ${d-imm7-4}(${d-An}),(${s1-An}),${s2} */
42188 +  {
42189 +    { 0, 0, 0, 0 },
42190 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
42191 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_4, { 0x9c000400 }
42192 +  },
42193 +/* subc (${d-An}),(${s1-An}),${s2} */
42194 +  {
42195 +    { 0, 0, 0, 0 },
42196 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
42197 +    & ifmt_pxvi_s_d_indirect_4_s1_indirect_4, { 0x9c000400 }
42198 +  },
42199 +/* subc (${d-An})${d-i4-4}++,(${s1-An}),${s2} */
42200 +  {
42201 +    { 0, 0, 0, 0 },
42202 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
42203 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_4, { 0x9a000400 }
42204 +  },
42205 +/* subc ${d-i4-4}(${d-An})++,(${s1-An}),${s2} */
42206 +  {
42207 +    { 0, 0, 0, 0 },
42208 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
42209 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_4, { 0x9a100400 }
42210 +  },
42211 +/* subc ${d-direct-addr},(${s1-An})${s1-i4-4}++,${s2} */
42212 +  {
42213 +    { 0, 0, 0, 0 },
42214 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
42215 +    & ifmt_pxadds_u_d_direct_s1_indirect_with_post_increment_4, { 0x99000200 }
42216 +  },
42217 +/* subc #${d-imm8},(${s1-An})${s1-i4-4}++,${s2} */
42218 +  {
42219 +    { 0, 0, 0, 0 },
42220 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
42221 +    & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_post_increment_4, { 0x98000200 }
42222 +  },
42223 +/* subc (${d-An},${d-r}),(${s1-An})${s1-i4-4}++,${s2} */
42224 +  {
42225 +    { 0, 0, 0, 0 },
42226 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
42227 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_post_increment_4, { 0x9b000200 }
42228 +  },
42229 +/* subc ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-4}++,${s2} */
42230 +  {
42231 +    { 0, 0, 0, 0 },
42232 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
42233 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_post_increment_4, { 0x9c000200 }
42234 +  },
42235 +/* subc (${d-An}),(${s1-An})${s1-i4-4}++,${s2} */
42236 +  {
42237 +    { 0, 0, 0, 0 },
42238 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
42239 +    & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_post_increment_4, { 0x9c000200 }
42240 +  },
42241 +/* subc (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-4}++,${s2} */
42242 +  {
42243 +    { 0, 0, 0, 0 },
42244 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
42245 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_post_increment_4, { 0x9a000200 }
42246 +  },
42247 +/* subc ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-4}++,${s2} */
42248 +  {
42249 +    { 0, 0, 0, 0 },
42250 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
42251 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_post_increment_4, { 0x9a100200 }
42252 +  },
42253 +/* subc ${d-direct-addr},${s1-i4-4}(${s1-An})++,${s2} */
42254 +  {
42255 +    { 0, 0, 0, 0 },
42256 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
42257 +    & ifmt_pxadds_u_d_direct_s1_indirect_with_pre_increment_4, { 0x99000210 }
42258 +  },
42259 +/* subc #${d-imm8},${s1-i4-4}(${s1-An})++,${s2} */
42260 +  {
42261 +    { 0, 0, 0, 0 },
42262 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
42263 +    & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_pre_increment_4, { 0x98000210 }
42264 +  },
42265 +/* subc (${d-An},${d-r}),${s1-i4-4}(${s1-An})++,${s2} */
42266 +  {
42267 +    { 0, 0, 0, 0 },
42268 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
42269 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_pre_increment_4, { 0x9b000210 }
42270 +  },
42271 +/* subc ${d-imm7-4}(${d-An}),${s1-i4-4}(${s1-An})++,${s2} */
42272 +  {
42273 +    { 0, 0, 0, 0 },
42274 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
42275 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_pre_increment_4, { 0x9c000210 }
42276 +  },
42277 +/* subc (${d-An}),${s1-i4-4}(${s1-An})++,${s2} */
42278 +  {
42279 +    { 0, 0, 0, 0 },
42280 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
42281 +    & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_pre_increment_4, { 0x9c000210 }
42282 +  },
42283 +/* subc (${d-An})${d-i4-4}++,${s1-i4-4}(${s1-An})++,${s2} */
42284 +  {
42285 +    { 0, 0, 0, 0 },
42286 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
42287 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_pre_increment_4, { 0x9a000210 }
42288 +  },
42289 +/* subc ${d-i4-4}(${d-An})++,${s1-i4-4}(${s1-An})++,${s2} */
42290 +  {
42291 +    { 0, 0, 0, 0 },
42292 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
42293 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_pre_increment_4, { 0x9a100210 }
42294 +  },
42295 +/* addc ${d-direct-addr},${s1-direct-addr},${s2} */
42296 +  {
42297 +    { 0, 0, 0, 0 },
42298 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
42299 +    & ifmt_pxadds_u_d_direct_s1_direct, { 0x81000100 }
42300 +  },
42301 +/* addc #${d-imm8},${s1-direct-addr},${s2} */
42302 +  {
42303 +    { 0, 0, 0, 0 },
42304 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
42305 +    & ifmt_pxvi_s_d_immediate_4_s1_direct, { 0x80000100 }
42306 +  },
42307 +/* addc (${d-An},${d-r}),${s1-direct-addr},${s2} */
42308 +  {
42309 +    { 0, 0, 0, 0 },
42310 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
42311 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_direct, { 0x83000100 }
42312 +  },
42313 +/* addc ${d-imm7-4}(${d-An}),${s1-direct-addr},${s2} */
42314 +  {
42315 +    { 0, 0, 0, 0 },
42316 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
42317 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_direct, { 0x84000100 }
42318 +  },
42319 +/* addc (${d-An}),${s1-direct-addr},${s2} */
42320 +  {
42321 +    { 0, 0, 0, 0 },
42322 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
42323 +    & ifmt_pxvi_s_d_indirect_4_s1_direct, { 0x84000100 }
42324 +  },
42325 +/* addc (${d-An})${d-i4-4}++,${s1-direct-addr},${s2} */
42326 +  {
42327 +    { 0, 0, 0, 0 },
42328 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
42329 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_direct, { 0x82000100 }
42330 +  },
42331 +/* addc ${d-i4-4}(${d-An})++,${s1-direct-addr},${s2} */
42332 +  {
42333 +    { 0, 0, 0, 0 },
42334 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
42335 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_direct, { 0x82100100 }
42336 +  },
42337 +/* addc ${d-direct-addr},#${s1-imm8},${s2} */
42338 +  {
42339 +    { 0, 0, 0, 0 },
42340 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
42341 +    & ifmt_pxadds_u_d_direct_s1_immediate, { 0x81000000 }
42342 +  },
42343 +/* addc #${d-imm8},#${s1-imm8},${s2} */
42344 +  {
42345 +    { 0, 0, 0, 0 },
42346 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
42347 +    & ifmt_pxvi_s_d_immediate_4_s1_immediate, { 0x80000000 }
42348 +  },
42349 +/* addc (${d-An},${d-r}),#${s1-imm8},${s2} */
42350 +  {
42351 +    { 0, 0, 0, 0 },
42352 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
42353 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_immediate, { 0x83000000 }
42354 +  },
42355 +/* addc ${d-imm7-4}(${d-An}),#${s1-imm8},${s2} */
42356 +  {
42357 +    { 0, 0, 0, 0 },
42358 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
42359 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_immediate, { 0x84000000 }
42360 +  },
42361 +/* addc (${d-An}),#${s1-imm8},${s2} */
42362 +  {
42363 +    { 0, 0, 0, 0 },
42364 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
42365 +    & ifmt_pxvi_s_d_indirect_4_s1_immediate, { 0x84000000 }
42366 +  },
42367 +/* addc (${d-An})${d-i4-4}++,#${s1-imm8},${s2} */
42368 +  {
42369 +    { 0, 0, 0, 0 },
42370 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
42371 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_immediate, { 0x82000000 }
42372 +  },
42373 +/* addc ${d-i4-4}(${d-An})++,#${s1-imm8},${s2} */
42374 +  {
42375 +    { 0, 0, 0, 0 },
42376 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
42377 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_immediate, { 0x82100000 }
42378 +  },
42379 +/* addc ${d-direct-addr},(${s1-An},${s1-r}),${s2} */
42380 +  {
42381 +    { 0, 0, 0, 0 },
42382 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
42383 +    & ifmt_pxadds_u_d_direct_s1_indirect_with_index_4, { 0x81000300 }
42384 +  },
42385 +/* addc #${d-imm8},(${s1-An},${s1-r}),${s2} */
42386 +  {
42387 +    { 0, 0, 0, 0 },
42388 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
42389 +    & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_index_4, { 0x80000300 }
42390 +  },
42391 +/* addc (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */
42392 +  {
42393 +    { 0, 0, 0, 0 },
42394 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
42395 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_index_4, { 0x83000300 }
42396 +  },
42397 +/* addc ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}),${s2} */
42398 +  {
42399 +    { 0, 0, 0, 0 },
42400 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
42401 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_index_4, { 0x84000300 }
42402 +  },
42403 +/* addc (${d-An}),(${s1-An},${s1-r}),${s2} */
42404 +  {
42405 +    { 0, 0, 0, 0 },
42406 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
42407 +    & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_index_4, { 0x84000300 }
42408 +  },
42409 +/* addc (${d-An})${d-i4-4}++,(${s1-An},${s1-r}),${s2} */
42410 +  {
42411 +    { 0, 0, 0, 0 },
42412 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
42413 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_index_4, { 0x82000300 }
42414 +  },
42415 +/* addc ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}),${s2} */
42416 +  {
42417 +    { 0, 0, 0, 0 },
42418 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
42419 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_index_4, { 0x82100300 }
42420 +  },
42421 +/* addc ${d-direct-addr},${s1-imm7-4}(${s1-An}),${s2} */
42422 +  {
42423 +    { 0, 0, 0, 0 },
42424 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
42425 +    & ifmt_pxadds_u_d_direct_s1_indirect_with_offset_4, { 0x81000400 }
42426 +  },
42427 +/* addc #${d-imm8},${s1-imm7-4}(${s1-An}),${s2} */
42428 +  {
42429 +    { 0, 0, 0, 0 },
42430 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
42431 +    & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_offset_4, { 0x80000400 }
42432 +  },
42433 +/* addc (${d-An},${d-r}),${s1-imm7-4}(${s1-An}),${s2} */
42434 +  {
42435 +    { 0, 0, 0, 0 },
42436 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
42437 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_offset_4, { 0x83000400 }
42438 +  },
42439 +/* addc ${d-imm7-4}(${d-An}),${s1-imm7-4}(${s1-An}),${s2} */
42440 +  {
42441 +    { 0, 0, 0, 0 },
42442 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
42443 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_offset_4, { 0x84000400 }
42444 +  },
42445 +/* addc (${d-An}),${s1-imm7-4}(${s1-An}),${s2} */
42446 +  {
42447 +    { 0, 0, 0, 0 },
42448 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
42449 +    & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_offset_4, { 0x84000400 }
42450 +  },
42451 +/* addc (${d-An})${d-i4-4}++,${s1-imm7-4}(${s1-An}),${s2} */
42452 +  {
42453 +    { 0, 0, 0, 0 },
42454 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
42455 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_offset_4, { 0x82000400 }
42456 +  },
42457 +/* addc ${d-i4-4}(${d-An})++,${s1-imm7-4}(${s1-An}),${s2} */
42458 +  {
42459 +    { 0, 0, 0, 0 },
42460 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
42461 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_offset_4, { 0x82100400 }
42462 +  },
42463 +/* addc ${d-direct-addr},(${s1-An}),${s2} */
42464 +  {
42465 +    { 0, 0, 0, 0 },
42466 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
42467 +    & ifmt_pxadds_u_d_direct_s1_indirect_4, { 0x81000400 }
42468 +  },
42469 +/* addc #${d-imm8},(${s1-An}),${s2} */
42470 +  {
42471 +    { 0, 0, 0, 0 },
42472 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
42473 +    & ifmt_pxvi_s_d_immediate_4_s1_indirect_4, { 0x80000400 }
42474 +  },
42475 +/* addc (${d-An},${d-r}),(${s1-An}),${s2} */
42476 +  {
42477 +    { 0, 0, 0, 0 },
42478 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
42479 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_4, { 0x83000400 }
42480 +  },
42481 +/* addc ${d-imm7-4}(${d-An}),(${s1-An}),${s2} */
42482 +  {
42483 +    { 0, 0, 0, 0 },
42484 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
42485 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_4, { 0x84000400 }
42486 +  },
42487 +/* addc (${d-An}),(${s1-An}),${s2} */
42488 +  {
42489 +    { 0, 0, 0, 0 },
42490 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
42491 +    & ifmt_pxvi_s_d_indirect_4_s1_indirect_4, { 0x84000400 }
42492 +  },
42493 +/* addc (${d-An})${d-i4-4}++,(${s1-An}),${s2} */
42494 +  {
42495 +    { 0, 0, 0, 0 },
42496 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
42497 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_4, { 0x82000400 }
42498 +  },
42499 +/* addc ${d-i4-4}(${d-An})++,(${s1-An}),${s2} */
42500 +  {
42501 +    { 0, 0, 0, 0 },
42502 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
42503 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_4, { 0x82100400 }
42504 +  },
42505 +/* addc ${d-direct-addr},(${s1-An})${s1-i4-4}++,${s2} */
42506 +  {
42507 +    { 0, 0, 0, 0 },
42508 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
42509 +    & ifmt_pxadds_u_d_direct_s1_indirect_with_post_increment_4, { 0x81000200 }
42510 +  },
42511 +/* addc #${d-imm8},(${s1-An})${s1-i4-4}++,${s2} */
42512 +  {
42513 +    { 0, 0, 0, 0 },
42514 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
42515 +    & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_post_increment_4, { 0x80000200 }
42516 +  },
42517 +/* addc (${d-An},${d-r}),(${s1-An})${s1-i4-4}++,${s2} */
42518 +  {
42519 +    { 0, 0, 0, 0 },
42520 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
42521 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_post_increment_4, { 0x83000200 }
42522 +  },
42523 +/* addc ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-4}++,${s2} */
42524 +  {
42525 +    { 0, 0, 0, 0 },
42526 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
42527 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_post_increment_4, { 0x84000200 }
42528 +  },
42529 +/* addc (${d-An}),(${s1-An})${s1-i4-4}++,${s2} */
42530 +  {
42531 +    { 0, 0, 0, 0 },
42532 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
42533 +    & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_post_increment_4, { 0x84000200 }
42534 +  },
42535 +/* addc (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-4}++,${s2} */
42536 +  {
42537 +    { 0, 0, 0, 0 },
42538 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
42539 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_post_increment_4, { 0x82000200 }
42540 +  },
42541 +/* addc ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-4}++,${s2} */
42542 +  {
42543 +    { 0, 0, 0, 0 },
42544 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
42545 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_post_increment_4, { 0x82100200 }
42546 +  },
42547 +/* addc ${d-direct-addr},${s1-i4-4}(${s1-An})++,${s2} */
42548 +  {
42549 +    { 0, 0, 0, 0 },
42550 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
42551 +    & ifmt_pxadds_u_d_direct_s1_indirect_with_pre_increment_4, { 0x81000210 }
42552 +  },
42553 +/* addc #${d-imm8},${s1-i4-4}(${s1-An})++,${s2} */
42554 +  {
42555 +    { 0, 0, 0, 0 },
42556 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
42557 +    & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_pre_increment_4, { 0x80000210 }
42558 +  },
42559 +/* addc (${d-An},${d-r}),${s1-i4-4}(${s1-An})++,${s2} */
42560 +  {
42561 +    { 0, 0, 0, 0 },
42562 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
42563 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_pre_increment_4, { 0x83000210 }
42564 +  },
42565 +/* addc ${d-imm7-4}(${d-An}),${s1-i4-4}(${s1-An})++,${s2} */
42566 +  {
42567 +    { 0, 0, 0, 0 },
42568 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
42569 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_pre_increment_4, { 0x84000210 }
42570 +  },
42571 +/* addc (${d-An}),${s1-i4-4}(${s1-An})++,${s2} */
42572 +  {
42573 +    { 0, 0, 0, 0 },
42574 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
42575 +    & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_pre_increment_4, { 0x84000210 }
42576 +  },
42577 +/* addc (${d-An})${d-i4-4}++,${s1-i4-4}(${s1-An})++,${s2} */
42578 +  {
42579 +    { 0, 0, 0, 0 },
42580 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
42581 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_pre_increment_4, { 0x82000210 }
42582 +  },
42583 +/* addc ${d-i4-4}(${d-An})++,${s1-i4-4}(${s1-An})++,${s2} */
42584 +  {
42585 +    { 0, 0, 0, 0 },
42586 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
42587 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_pre_increment_4, { 0x82100210 }
42588 +  },
42589 +/* sub.1 ${d-direct-addr},${s1-direct-addr},${s2} */
42590 +  {
42591 +    { 0, 0, 0, 0 },
42592 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
42593 +    & ifmt_pxadds_u_d_direct_s1_direct, { 0x89008100 }
42594 +  },
42595 +/* sub.1 #${d-imm8},${s1-direct-addr},${s2} */
42596 +  {
42597 +    { 0, 0, 0, 0 },
42598 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
42599 +    & ifmt_sub_1_d_immediate_1_s1_direct, { 0x88008100 }
42600 +  },
42601 +/* sub.1 (${d-An},${d-r}),${s1-direct-addr},${s2} */
42602 +  {
42603 +    { 0, 0, 0, 0 },
42604 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
42605 +    & ifmt_sub_1_d_indirect_with_index_1_s1_direct, { 0x8b008100 }
42606 +  },
42607 +/* sub.1 ${d-imm7-1}(${d-An}),${s1-direct-addr},${s2} */
42608 +  {
42609 +    { 0, 0, 0, 0 },
42610 +    { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
42611 +    & ifmt_sub_1_d_indirect_with_offset_1_s1_direct, { 0x8c008100 }
42612 +  },
42613 +/* sub.1 (${d-An}),${s1-direct-addr},${s2} */
42614 +  {
42615 +    { 0, 0, 0, 0 },
42616 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
42617 +    & ifmt_sub_1_d_indirect_1_s1_direct, { 0x8c008100 }
42618 +  },
42619 +/* sub.1 (${d-An})${d-i4-1}++,${s1-direct-addr},${s2} */
42620 +  {
42621 +    { 0, 0, 0, 0 },
42622 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
42623 +    & ifmt_sub_1_d_indirect_with_post_increment_1_s1_direct, { 0x8a008100 }
42624 +  },
42625 +/* sub.1 ${d-i4-1}(${d-An})++,${s1-direct-addr},${s2} */
42626 +  {
42627 +    { 0, 0, 0, 0 },
42628 +    { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
42629 +    & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_direct, { 0x8a108100 }
42630 +  },
42631 +/* sub.1 ${d-direct-addr},#${s1-imm8},${s2} */
42632 +  {
42633 +    { 0, 0, 0, 0 },
42634 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
42635 +    & ifmt_pxadds_u_d_direct_s1_immediate, { 0x89008000 }
42636 +  },
42637 +/* sub.1 #${d-imm8},#${s1-imm8},${s2} */
42638 +  {
42639 +    { 0, 0, 0, 0 },
42640 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
42641 +    & ifmt_sub_1_d_immediate_1_s1_immediate, { 0x88008000 }
42642 +  },
42643 +/* sub.1 (${d-An},${d-r}),#${s1-imm8},${s2} */
42644 +  {
42645 +    { 0, 0, 0, 0 },
42646 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
42647 +    & ifmt_sub_1_d_indirect_with_index_1_s1_immediate, { 0x8b008000 }
42648 +  },
42649 +/* sub.1 ${d-imm7-1}(${d-An}),#${s1-imm8},${s2} */
42650 +  {
42651 +    { 0, 0, 0, 0 },
42652 +    { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
42653 +    & ifmt_sub_1_d_indirect_with_offset_1_s1_immediate, { 0x8c008000 }
42654 +  },
42655 +/* sub.1 (${d-An}),#${s1-imm8},${s2} */
42656 +  {
42657 +    { 0, 0, 0, 0 },
42658 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
42659 +    & ifmt_sub_1_d_indirect_1_s1_immediate, { 0x8c008000 }
42660 +  },
42661 +/* sub.1 (${d-An})${d-i4-1}++,#${s1-imm8},${s2} */
42662 +  {
42663 +    { 0, 0, 0, 0 },
42664 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
42665 +    & ifmt_sub_1_d_indirect_with_post_increment_1_s1_immediate, { 0x8a008000 }
42666 +  },
42667 +/* sub.1 ${d-i4-1}(${d-An})++,#${s1-imm8},${s2} */
42668 +  {
42669 +    { 0, 0, 0, 0 },
42670 +    { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
42671 +    & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_immediate, { 0x8a108000 }
42672 +  },
42673 +/* sub.1 ${d-direct-addr},(${s1-An},${s1-r}),${s2} */
42674 +  {
42675 +    { 0, 0, 0, 0 },
42676 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
42677 +    & ifmt_sub_1_d_direct_s1_indirect_with_index_1, { 0x89008300 }
42678 +  },
42679 +/* sub.1 #${d-imm8},(${s1-An},${s1-r}),${s2} */
42680 +  {
42681 +    { 0, 0, 0, 0 },
42682 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
42683 +    & ifmt_sub_1_d_immediate_1_s1_indirect_with_index_1, { 0x88008300 }
42684 +  },
42685 +/* sub.1 (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */
42686 +  {
42687 +    { 0, 0, 0, 0 },
42688 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
42689 +    & ifmt_sub_1_d_indirect_with_index_1_s1_indirect_with_index_1, { 0x8b008300 }
42690 +  },
42691 +/* sub.1 ${d-imm7-1}(${d-An}),(${s1-An},${s1-r}),${s2} */
42692 +  {
42693 +    { 0, 0, 0, 0 },
42694 +    { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
42695 +    & ifmt_sub_1_d_indirect_with_offset_1_s1_indirect_with_index_1, { 0x8c008300 }
42696 +  },
42697 +/* sub.1 (${d-An}),(${s1-An},${s1-r}),${s2} */
42698 +  {
42699 +    { 0, 0, 0, 0 },
42700 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
42701 +    & ifmt_sub_1_d_indirect_1_s1_indirect_with_index_1, { 0x8c008300 }
42702 +  },
42703 +/* sub.1 (${d-An})${d-i4-1}++,(${s1-An},${s1-r}),${s2} */
42704 +  {
42705 +    { 0, 0, 0, 0 },
42706 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
42707 +    & ifmt_sub_1_d_indirect_with_post_increment_1_s1_indirect_with_index_1, { 0x8a008300 }
42708 +  },
42709 +/* sub.1 ${d-i4-1}(${d-An})++,(${s1-An},${s1-r}),${s2} */
42710 +  {
42711 +    { 0, 0, 0, 0 },
42712 +    { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
42713 +    & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_indirect_with_index_1, { 0x8a108300 }
42714 +  },
42715 +/* sub.1 ${d-direct-addr},${s1-imm7-1}(${s1-An}),${s2} */
42716 +  {
42717 +    { 0, 0, 0, 0 },
42718 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
42719 +    & ifmt_sub_1_d_direct_s1_indirect_with_offset_1, { 0x89008400 }
42720 +  },
42721 +/* sub.1 #${d-imm8},${s1-imm7-1}(${s1-An}),${s2} */
42722 +  {
42723 +    { 0, 0, 0, 0 },
42724 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
42725 +    & ifmt_sub_1_d_immediate_1_s1_indirect_with_offset_1, { 0x88008400 }
42726 +  },
42727 +/* sub.1 (${d-An},${d-r}),${s1-imm7-1}(${s1-An}),${s2} */
42728 +  {
42729 +    { 0, 0, 0, 0 },
42730 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
42731 +    & ifmt_sub_1_d_indirect_with_index_1_s1_indirect_with_offset_1, { 0x8b008400 }
42732 +  },
42733 +/* sub.1 ${d-imm7-1}(${d-An}),${s1-imm7-1}(${s1-An}),${s2} */
42734 +  {
42735 +    { 0, 0, 0, 0 },
42736 +    { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
42737 +    & ifmt_sub_1_d_indirect_with_offset_1_s1_indirect_with_offset_1, { 0x8c008400 }
42738 +  },
42739 +/* sub.1 (${d-An}),${s1-imm7-1}(${s1-An}),${s2} */
42740 +  {
42741 +    { 0, 0, 0, 0 },
42742 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
42743 +    & ifmt_sub_1_d_indirect_1_s1_indirect_with_offset_1, { 0x8c008400 }
42744 +  },
42745 +/* sub.1 (${d-An})${d-i4-1}++,${s1-imm7-1}(${s1-An}),${s2} */
42746 +  {
42747 +    { 0, 0, 0, 0 },
42748 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
42749 +    & ifmt_sub_1_d_indirect_with_post_increment_1_s1_indirect_with_offset_1, { 0x8a008400 }
42750 +  },
42751 +/* sub.1 ${d-i4-1}(${d-An})++,${s1-imm7-1}(${s1-An}),${s2} */
42752 +  {
42753 +    { 0, 0, 0, 0 },
42754 +    { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
42755 +    & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_indirect_with_offset_1, { 0x8a108400 }
42756 +  },
42757 +/* sub.1 ${d-direct-addr},(${s1-An}),${s2} */
42758 +  {
42759 +    { 0, 0, 0, 0 },
42760 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
42761 +    & ifmt_sub_1_d_direct_s1_indirect_1, { 0x89008400 }
42762 +  },
42763 +/* sub.1 #${d-imm8},(${s1-An}),${s2} */
42764 +  {
42765 +    { 0, 0, 0, 0 },
42766 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
42767 +    & ifmt_sub_1_d_immediate_1_s1_indirect_1, { 0x88008400 }
42768 +  },
42769 +/* sub.1 (${d-An},${d-r}),(${s1-An}),${s2} */
42770 +  {
42771 +    { 0, 0, 0, 0 },
42772 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
42773 +    & ifmt_sub_1_d_indirect_with_index_1_s1_indirect_1, { 0x8b008400 }
42774 +  },
42775 +/* sub.1 ${d-imm7-1}(${d-An}),(${s1-An}),${s2} */
42776 +  {
42777 +    { 0, 0, 0, 0 },
42778 +    { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
42779 +    & ifmt_sub_1_d_indirect_with_offset_1_s1_indirect_1, { 0x8c008400 }
42780 +  },
42781 +/* sub.1 (${d-An}),(${s1-An}),${s2} */
42782 +  {
42783 +    { 0, 0, 0, 0 },
42784 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
42785 +    & ifmt_sub_1_d_indirect_1_s1_indirect_1, { 0x8c008400 }
42786 +  },
42787 +/* sub.1 (${d-An})${d-i4-1}++,(${s1-An}),${s2} */
42788 +  {
42789 +    { 0, 0, 0, 0 },
42790 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
42791 +    & ifmt_sub_1_d_indirect_with_post_increment_1_s1_indirect_1, { 0x8a008400 }
42792 +  },
42793 +/* sub.1 ${d-i4-1}(${d-An})++,(${s1-An}),${s2} */
42794 +  {
42795 +    { 0, 0, 0, 0 },
42796 +    { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
42797 +    & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_indirect_1, { 0x8a108400 }
42798 +  },
42799 +/* sub.1 ${d-direct-addr},(${s1-An})${s1-i4-1}++,${s2} */
42800 +  {
42801 +    { 0, 0, 0, 0 },
42802 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } },
42803 +    & ifmt_sub_1_d_direct_s1_indirect_with_post_increment_1, { 0x89008200 }
42804 +  },
42805 +/* sub.1 #${d-imm8},(${s1-An})${s1-i4-1}++,${s2} */
42806 +  {
42807 +    { 0, 0, 0, 0 },
42808 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } },
42809 +    & ifmt_sub_1_d_immediate_1_s1_indirect_with_post_increment_1, { 0x88008200 }
42810 +  },
42811 +/* sub.1 (${d-An},${d-r}),(${s1-An})${s1-i4-1}++,${s2} */
42812 +  {
42813 +    { 0, 0, 0, 0 },
42814 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } },
42815 +    & ifmt_sub_1_d_indirect_with_index_1_s1_indirect_with_post_increment_1, { 0x8b008200 }
42816 +  },
42817 +/* sub.1 ${d-imm7-1}(${d-An}),(${s1-An})${s1-i4-1}++,${s2} */
42818 +  {
42819 +    { 0, 0, 0, 0 },
42820 +    { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } },
42821 +    & ifmt_sub_1_d_indirect_with_offset_1_s1_indirect_with_post_increment_1, { 0x8c008200 }
42822 +  },
42823 +/* sub.1 (${d-An}),(${s1-An})${s1-i4-1}++,${s2} */
42824 +  {
42825 +    { 0, 0, 0, 0 },
42826 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } },
42827 +    & ifmt_sub_1_d_indirect_1_s1_indirect_with_post_increment_1, { 0x8c008200 }
42828 +  },
42829 +/* sub.1 (${d-An})${d-i4-1}++,(${s1-An})${s1-i4-1}++,${s2} */
42830 +  {
42831 +    { 0, 0, 0, 0 },
42832 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } },
42833 +    & ifmt_sub_1_d_indirect_with_post_increment_1_s1_indirect_with_post_increment_1, { 0x8a008200 }
42834 +  },
42835 +/* sub.1 ${d-i4-1}(${d-An})++,(${s1-An})${s1-i4-1}++,${s2} */
42836 +  {
42837 +    { 0, 0, 0, 0 },
42838 +    { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } },
42839 +    & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_indirect_with_post_increment_1, { 0x8a108200 }
42840 +  },
42841 +/* sub.1 ${d-direct-addr},${s1-i4-1}(${s1-An})++,${s2} */
42842 +  {
42843 +    { 0, 0, 0, 0 },
42844 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
42845 +    & ifmt_sub_1_d_direct_s1_indirect_with_pre_increment_1, { 0x89008210 }
42846 +  },
42847 +/* sub.1 #${d-imm8},${s1-i4-1}(${s1-An})++,${s2} */
42848 +  {
42849 +    { 0, 0, 0, 0 },
42850 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
42851 +    & ifmt_sub_1_d_immediate_1_s1_indirect_with_pre_increment_1, { 0x88008210 }
42852 +  },
42853 +/* sub.1 (${d-An},${d-r}),${s1-i4-1}(${s1-An})++,${s2} */
42854 +  {
42855 +    { 0, 0, 0, 0 },
42856 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
42857 +    & ifmt_sub_1_d_indirect_with_index_1_s1_indirect_with_pre_increment_1, { 0x8b008210 }
42858 +  },
42859 +/* sub.1 ${d-imm7-1}(${d-An}),${s1-i4-1}(${s1-An})++,${s2} */
42860 +  {
42861 +    { 0, 0, 0, 0 },
42862 +    { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
42863 +    & ifmt_sub_1_d_indirect_with_offset_1_s1_indirect_with_pre_increment_1, { 0x8c008210 }
42864 +  },
42865 +/* sub.1 (${d-An}),${s1-i4-1}(${s1-An})++,${s2} */
42866 +  {
42867 +    { 0, 0, 0, 0 },
42868 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
42869 +    & ifmt_sub_1_d_indirect_1_s1_indirect_with_pre_increment_1, { 0x8c008210 }
42870 +  },
42871 +/* sub.1 (${d-An})${d-i4-1}++,${s1-i4-1}(${s1-An})++,${s2} */
42872 +  {
42873 +    { 0, 0, 0, 0 },
42874 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
42875 +    & ifmt_sub_1_d_indirect_with_post_increment_1_s1_indirect_with_pre_increment_1, { 0x8a008210 }
42876 +  },
42877 +/* sub.1 ${d-i4-1}(${d-An})++,${s1-i4-1}(${s1-An})++,${s2} */
42878 +  {
42879 +    { 0, 0, 0, 0 },
42880 +    { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
42881 +    & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_indirect_with_pre_increment_1, { 0x8a108210 }
42882 +  },
42883 +/* sub.4 ${d-direct-addr},${s1-direct-addr},${s2} */
42884 +  {
42885 +    { 0, 0, 0, 0 },
42886 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
42887 +    & ifmt_pxadds_u_d_direct_s1_direct, { 0x91000100 }
42888 +  },
42889 +/* sub.4 #${d-imm8},${s1-direct-addr},${s2} */
42890 +  {
42891 +    { 0, 0, 0, 0 },
42892 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
42893 +    & ifmt_pxvi_s_d_immediate_4_s1_direct, { 0x90000100 }
42894 +  },
42895 +/* sub.4 (${d-An},${d-r}),${s1-direct-addr},${s2} */
42896 +  {
42897 +    { 0, 0, 0, 0 },
42898 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
42899 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_direct, { 0x93000100 }
42900 +  },
42901 +/* sub.4 ${d-imm7-4}(${d-An}),${s1-direct-addr},${s2} */
42902 +  {
42903 +    { 0, 0, 0, 0 },
42904 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
42905 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_direct, { 0x94000100 }
42906 +  },
42907 +/* sub.4 (${d-An}),${s1-direct-addr},${s2} */
42908 +  {
42909 +    { 0, 0, 0, 0 },
42910 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
42911 +    & ifmt_pxvi_s_d_indirect_4_s1_direct, { 0x94000100 }
42912 +  },
42913 +/* sub.4 (${d-An})${d-i4-4}++,${s1-direct-addr},${s2} */
42914 +  {
42915 +    { 0, 0, 0, 0 },
42916 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
42917 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_direct, { 0x92000100 }
42918 +  },
42919 +/* sub.4 ${d-i4-4}(${d-An})++,${s1-direct-addr},${s2} */
42920 +  {
42921 +    { 0, 0, 0, 0 },
42922 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
42923 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_direct, { 0x92100100 }
42924 +  },
42925 +/* sub.4 ${d-direct-addr},#${s1-imm8},${s2} */
42926 +  {
42927 +    { 0, 0, 0, 0 },
42928 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
42929 +    & ifmt_pxadds_u_d_direct_s1_immediate, { 0x91000000 }
42930 +  },
42931 +/* sub.4 #${d-imm8},#${s1-imm8},${s2} */
42932 +  {
42933 +    { 0, 0, 0, 0 },
42934 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
42935 +    & ifmt_pxvi_s_d_immediate_4_s1_immediate, { 0x90000000 }
42936 +  },
42937 +/* sub.4 (${d-An},${d-r}),#${s1-imm8},${s2} */
42938 +  {
42939 +    { 0, 0, 0, 0 },
42940 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
42941 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_immediate, { 0x93000000 }
42942 +  },
42943 +/* sub.4 ${d-imm7-4}(${d-An}),#${s1-imm8},${s2} */
42944 +  {
42945 +    { 0, 0, 0, 0 },
42946 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
42947 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_immediate, { 0x94000000 }
42948 +  },
42949 +/* sub.4 (${d-An}),#${s1-imm8},${s2} */
42950 +  {
42951 +    { 0, 0, 0, 0 },
42952 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
42953 +    & ifmt_pxvi_s_d_indirect_4_s1_immediate, { 0x94000000 }
42954 +  },
42955 +/* sub.4 (${d-An})${d-i4-4}++,#${s1-imm8},${s2} */
42956 +  {
42957 +    { 0, 0, 0, 0 },
42958 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
42959 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_immediate, { 0x92000000 }
42960 +  },
42961 +/* sub.4 ${d-i4-4}(${d-An})++,#${s1-imm8},${s2} */
42962 +  {
42963 +    { 0, 0, 0, 0 },
42964 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
42965 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_immediate, { 0x92100000 }
42966 +  },
42967 +/* sub.4 ${d-direct-addr},(${s1-An},${s1-r}),${s2} */
42968 +  {
42969 +    { 0, 0, 0, 0 },
42970 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
42971 +    & ifmt_pxadds_u_d_direct_s1_indirect_with_index_4, { 0x91000300 }
42972 +  },
42973 +/* sub.4 #${d-imm8},(${s1-An},${s1-r}),${s2} */
42974 +  {
42975 +    { 0, 0, 0, 0 },
42976 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
42977 +    & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_index_4, { 0x90000300 }
42978 +  },
42979 +/* sub.4 (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */
42980 +  {
42981 +    { 0, 0, 0, 0 },
42982 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
42983 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_index_4, { 0x93000300 }
42984 +  },
42985 +/* sub.4 ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}),${s2} */
42986 +  {
42987 +    { 0, 0, 0, 0 },
42988 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
42989 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_index_4, { 0x94000300 }
42990 +  },
42991 +/* sub.4 (${d-An}),(${s1-An},${s1-r}),${s2} */
42992 +  {
42993 +    { 0, 0, 0, 0 },
42994 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
42995 +    & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_index_4, { 0x94000300 }
42996 +  },
42997 +/* sub.4 (${d-An})${d-i4-4}++,(${s1-An},${s1-r}),${s2} */
42998 +  {
42999 +    { 0, 0, 0, 0 },
43000 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
43001 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_index_4, { 0x92000300 }
43002 +  },
43003 +/* sub.4 ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}),${s2} */
43004 +  {
43005 +    { 0, 0, 0, 0 },
43006 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
43007 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_index_4, { 0x92100300 }
43008 +  },
43009 +/* sub.4 ${d-direct-addr},${s1-imm7-4}(${s1-An}),${s2} */
43010 +  {
43011 +    { 0, 0, 0, 0 },
43012 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
43013 +    & ifmt_pxadds_u_d_direct_s1_indirect_with_offset_4, { 0x91000400 }
43014 +  },
43015 +/* sub.4 #${d-imm8},${s1-imm7-4}(${s1-An}),${s2} */
43016 +  {
43017 +    { 0, 0, 0, 0 },
43018 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
43019 +    & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_offset_4, { 0x90000400 }
43020 +  },
43021 +/* sub.4 (${d-An},${d-r}),${s1-imm7-4}(${s1-An}),${s2} */
43022 +  {
43023 +    { 0, 0, 0, 0 },
43024 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
43025 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_offset_4, { 0x93000400 }
43026 +  },
43027 +/* sub.4 ${d-imm7-4}(${d-An}),${s1-imm7-4}(${s1-An}),${s2} */
43028 +  {
43029 +    { 0, 0, 0, 0 },
43030 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
43031 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_offset_4, { 0x94000400 }
43032 +  },
43033 +/* sub.4 (${d-An}),${s1-imm7-4}(${s1-An}),${s2} */
43034 +  {
43035 +    { 0, 0, 0, 0 },
43036 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
43037 +    & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_offset_4, { 0x94000400 }
43038 +  },
43039 +/* sub.4 (${d-An})${d-i4-4}++,${s1-imm7-4}(${s1-An}),${s2} */
43040 +  {
43041 +    { 0, 0, 0, 0 },
43042 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
43043 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_offset_4, { 0x92000400 }
43044 +  },
43045 +/* sub.4 ${d-i4-4}(${d-An})++,${s1-imm7-4}(${s1-An}),${s2} */
43046 +  {
43047 +    { 0, 0, 0, 0 },
43048 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
43049 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_offset_4, { 0x92100400 }
43050 +  },
43051 +/* sub.4 ${d-direct-addr},(${s1-An}),${s2} */
43052 +  {
43053 +    { 0, 0, 0, 0 },
43054 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
43055 +    & ifmt_pxadds_u_d_direct_s1_indirect_4, { 0x91000400 }
43056 +  },
43057 +/* sub.4 #${d-imm8},(${s1-An}),${s2} */
43058 +  {
43059 +    { 0, 0, 0, 0 },
43060 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
43061 +    & ifmt_pxvi_s_d_immediate_4_s1_indirect_4, { 0x90000400 }
43062 +  },
43063 +/* sub.4 (${d-An},${d-r}),(${s1-An}),${s2} */
43064 +  {
43065 +    { 0, 0, 0, 0 },
43066 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
43067 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_4, { 0x93000400 }
43068 +  },
43069 +/* sub.4 ${d-imm7-4}(${d-An}),(${s1-An}),${s2} */
43070 +  {
43071 +    { 0, 0, 0, 0 },
43072 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
43073 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_4, { 0x94000400 }
43074 +  },
43075 +/* sub.4 (${d-An}),(${s1-An}),${s2} */
43076 +  {
43077 +    { 0, 0, 0, 0 },
43078 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
43079 +    & ifmt_pxvi_s_d_indirect_4_s1_indirect_4, { 0x94000400 }
43080 +  },
43081 +/* sub.4 (${d-An})${d-i4-4}++,(${s1-An}),${s2} */
43082 +  {
43083 +    { 0, 0, 0, 0 },
43084 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
43085 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_4, { 0x92000400 }
43086 +  },
43087 +/* sub.4 ${d-i4-4}(${d-An})++,(${s1-An}),${s2} */
43088 +  {
43089 +    { 0, 0, 0, 0 },
43090 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
43091 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_4, { 0x92100400 }
43092 +  },
43093 +/* sub.4 ${d-direct-addr},(${s1-An})${s1-i4-4}++,${s2} */
43094 +  {
43095 +    { 0, 0, 0, 0 },
43096 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
43097 +    & ifmt_pxadds_u_d_direct_s1_indirect_with_post_increment_4, { 0x91000200 }
43098 +  },
43099 +/* sub.4 #${d-imm8},(${s1-An})${s1-i4-4}++,${s2} */
43100 +  {
43101 +    { 0, 0, 0, 0 },
43102 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
43103 +    & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_post_increment_4, { 0x90000200 }
43104 +  },
43105 +/* sub.4 (${d-An},${d-r}),(${s1-An})${s1-i4-4}++,${s2} */
43106 +  {
43107 +    { 0, 0, 0, 0 },
43108 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
43109 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_post_increment_4, { 0x93000200 }
43110 +  },
43111 +/* sub.4 ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-4}++,${s2} */
43112 +  {
43113 +    { 0, 0, 0, 0 },
43114 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
43115 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_post_increment_4, { 0x94000200 }
43116 +  },
43117 +/* sub.4 (${d-An}),(${s1-An})${s1-i4-4}++,${s2} */
43118 +  {
43119 +    { 0, 0, 0, 0 },
43120 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
43121 +    & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_post_increment_4, { 0x94000200 }
43122 +  },
43123 +/* sub.4 (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-4}++,${s2} */
43124 +  {
43125 +    { 0, 0, 0, 0 },
43126 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
43127 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_post_increment_4, { 0x92000200 }
43128 +  },
43129 +/* sub.4 ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-4}++,${s2} */
43130 +  {
43131 +    { 0, 0, 0, 0 },
43132 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
43133 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_post_increment_4, { 0x92100200 }
43134 +  },
43135 +/* sub.4 ${d-direct-addr},${s1-i4-4}(${s1-An})++,${s2} */
43136 +  {
43137 +    { 0, 0, 0, 0 },
43138 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
43139 +    & ifmt_pxadds_u_d_direct_s1_indirect_with_pre_increment_4, { 0x91000210 }
43140 +  },
43141 +/* sub.4 #${d-imm8},${s1-i4-4}(${s1-An})++,${s2} */
43142 +  {
43143 +    { 0, 0, 0, 0 },
43144 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
43145 +    & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_pre_increment_4, { 0x90000210 }
43146 +  },
43147 +/* sub.4 (${d-An},${d-r}),${s1-i4-4}(${s1-An})++,${s2} */
43148 +  {
43149 +    { 0, 0, 0, 0 },
43150 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
43151 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_pre_increment_4, { 0x93000210 }
43152 +  },
43153 +/* sub.4 ${d-imm7-4}(${d-An}),${s1-i4-4}(${s1-An})++,${s2} */
43154 +  {
43155 +    { 0, 0, 0, 0 },
43156 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
43157 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_pre_increment_4, { 0x94000210 }
43158 +  },
43159 +/* sub.4 (${d-An}),${s1-i4-4}(${s1-An})++,${s2} */
43160 +  {
43161 +    { 0, 0, 0, 0 },
43162 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
43163 +    & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_pre_increment_4, { 0x94000210 }
43164 +  },
43165 +/* sub.4 (${d-An})${d-i4-4}++,${s1-i4-4}(${s1-An})++,${s2} */
43166 +  {
43167 +    { 0, 0, 0, 0 },
43168 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
43169 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_pre_increment_4, { 0x92000210 }
43170 +  },
43171 +/* sub.4 ${d-i4-4}(${d-An})++,${s1-i4-4}(${s1-An})++,${s2} */
43172 +  {
43173 +    { 0, 0, 0, 0 },
43174 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
43175 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_pre_increment_4, { 0x92100210 }
43176 +  },
43177 +/* sub.2 ${d-direct-addr},${s1-direct-addr},${s2} */
43178 +  {
43179 +    { 0, 0, 0, 0 },
43180 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
43181 +    & ifmt_pxadds_u_d_direct_s1_direct, { 0x89000100 }
43182 +  },
43183 +/* sub.2 #${d-imm8},${s1-direct-addr},${s2} */
43184 +  {
43185 +    { 0, 0, 0, 0 },
43186 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
43187 +    & ifmt_pxadds_u_d_immediate_2_s1_direct, { 0x88000100 }
43188 +  },
43189 +/* sub.2 (${d-An},${d-r}),${s1-direct-addr},${s2} */
43190 +  {
43191 +    { 0, 0, 0, 0 },
43192 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
43193 +    & ifmt_pxadds_u_d_indirect_with_index_2_s1_direct, { 0x8b000100 }
43194 +  },
43195 +/* sub.2 ${d-imm7-2}(${d-An}),${s1-direct-addr},${s2} */
43196 +  {
43197 +    { 0, 0, 0, 0 },
43198 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
43199 +    & ifmt_pxadds_u_d_indirect_with_offset_2_s1_direct, { 0x8c000100 }
43200 +  },
43201 +/* sub.2 (${d-An}),${s1-direct-addr},${s2} */
43202 +  {
43203 +    { 0, 0, 0, 0 },
43204 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
43205 +    & ifmt_pxadds_u_d_indirect_2_s1_direct, { 0x8c000100 }
43206 +  },
43207 +/* sub.2 (${d-An})${d-i4-2}++,${s1-direct-addr},${s2} */
43208 +  {
43209 +    { 0, 0, 0, 0 },
43210 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
43211 +    & ifmt_pxadds_u_d_indirect_with_post_increment_2_s1_direct, { 0x8a000100 }
43212 +  },
43213 +/* sub.2 ${d-i4-2}(${d-An})++,${s1-direct-addr},${s2} */
43214 +  {
43215 +    { 0, 0, 0, 0 },
43216 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
43217 +    & ifmt_pxadds_u_d_indirect_with_pre_increment_2_s1_direct, { 0x8a100100 }
43218 +  },
43219 +/* sub.2 ${d-direct-addr},#${s1-imm8},${s2} */
43220 +  {
43221 +    { 0, 0, 0, 0 },
43222 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
43223 +    & ifmt_pxadds_u_d_direct_s1_immediate, { 0x89000000 }
43224 +  },
43225 +/* sub.2 #${d-imm8},#${s1-imm8},${s2} */
43226 +  {
43227 +    { 0, 0, 0, 0 },
43228 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
43229 +    & ifmt_pxadds_u_d_immediate_2_s1_immediate, { 0x88000000 }
43230 +  },
43231 +/* sub.2 (${d-An},${d-r}),#${s1-imm8},${s2} */
43232 +  {
43233 +    { 0, 0, 0, 0 },
43234 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
43235 +    & ifmt_pxadds_u_d_indirect_with_index_2_s1_immediate, { 0x8b000000 }
43236 +  },
43237 +/* sub.2 ${d-imm7-2}(${d-An}),#${s1-imm8},${s2} */
43238 +  {
43239 +    { 0, 0, 0, 0 },
43240 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
43241 +    & ifmt_pxadds_u_d_indirect_with_offset_2_s1_immediate, { 0x8c000000 }
43242 +  },
43243 +/* sub.2 (${d-An}),#${s1-imm8},${s2} */
43244 +  {
43245 +    { 0, 0, 0, 0 },
43246 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
43247 +    & ifmt_pxadds_u_d_indirect_2_s1_immediate, { 0x8c000000 }
43248 +  },
43249 +/* sub.2 (${d-An})${d-i4-2}++,#${s1-imm8},${s2} */
43250 +  {
43251 +    { 0, 0, 0, 0 },
43252 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
43253 +    & ifmt_pxadds_u_d_indirect_with_post_increment_2_s1_immediate, { 0x8a000000 }
43254 +  },
43255 +/* sub.2 ${d-i4-2}(${d-An})++,#${s1-imm8},${s2} */
43256 +  {
43257 +    { 0, 0, 0, 0 },
43258 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
43259 +    & ifmt_pxadds_u_d_indirect_with_pre_increment_2_s1_immediate, { 0x8a100000 }
43260 +  },
43261 +/* sub.2 ${d-direct-addr},(${s1-An},${s1-r}),${s2} */
43262 +  {
43263 +    { 0, 0, 0, 0 },
43264 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
43265 +    & ifmt_sub_2_d_direct_s1_indirect_with_index_2, { 0x89000300 }
43266 +  },
43267 +/* sub.2 #${d-imm8},(${s1-An},${s1-r}),${s2} */
43268 +  {
43269 +    { 0, 0, 0, 0 },
43270 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
43271 +    & ifmt_sub_2_d_immediate_2_s1_indirect_with_index_2, { 0x88000300 }
43272 +  },
43273 +/* sub.2 (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */
43274 +  {
43275 +    { 0, 0, 0, 0 },
43276 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
43277 +    & ifmt_sub_2_d_indirect_with_index_2_s1_indirect_with_index_2, { 0x8b000300 }
43278 +  },
43279 +/* sub.2 ${d-imm7-2}(${d-An}),(${s1-An},${s1-r}),${s2} */
43280 +  {
43281 +    { 0, 0, 0, 0 },
43282 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
43283 +    & ifmt_sub_2_d_indirect_with_offset_2_s1_indirect_with_index_2, { 0x8c000300 }
43284 +  },
43285 +/* sub.2 (${d-An}),(${s1-An},${s1-r}),${s2} */
43286 +  {
43287 +    { 0, 0, 0, 0 },
43288 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
43289 +    & ifmt_sub_2_d_indirect_2_s1_indirect_with_index_2, { 0x8c000300 }
43290 +  },
43291 +/* sub.2 (${d-An})${d-i4-2}++,(${s1-An},${s1-r}),${s2} */
43292 +  {
43293 +    { 0, 0, 0, 0 },
43294 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
43295 +    & ifmt_sub_2_d_indirect_with_post_increment_2_s1_indirect_with_index_2, { 0x8a000300 }
43296 +  },
43297 +/* sub.2 ${d-i4-2}(${d-An})++,(${s1-An},${s1-r}),${s2} */
43298 +  {
43299 +    { 0, 0, 0, 0 },
43300 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
43301 +    & ifmt_sub_2_d_indirect_with_pre_increment_2_s1_indirect_with_index_2, { 0x8a100300 }
43302 +  },
43303 +/* sub.2 ${d-direct-addr},${s1-imm7-2}(${s1-An}),${s2} */
43304 +  {
43305 +    { 0, 0, 0, 0 },
43306 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
43307 +    & ifmt_sub_2_d_direct_s1_indirect_with_offset_2, { 0x89000400 }
43308 +  },
43309 +/* sub.2 #${d-imm8},${s1-imm7-2}(${s1-An}),${s2} */
43310 +  {
43311 +    { 0, 0, 0, 0 },
43312 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
43313 +    & ifmt_sub_2_d_immediate_2_s1_indirect_with_offset_2, { 0x88000400 }
43314 +  },
43315 +/* sub.2 (${d-An},${d-r}),${s1-imm7-2}(${s1-An}),${s2} */
43316 +  {
43317 +    { 0, 0, 0, 0 },
43318 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
43319 +    & ifmt_sub_2_d_indirect_with_index_2_s1_indirect_with_offset_2, { 0x8b000400 }
43320 +  },
43321 +/* sub.2 ${d-imm7-2}(${d-An}),${s1-imm7-2}(${s1-An}),${s2} */
43322 +  {
43323 +    { 0, 0, 0, 0 },
43324 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
43325 +    & ifmt_sub_2_d_indirect_with_offset_2_s1_indirect_with_offset_2, { 0x8c000400 }
43326 +  },
43327 +/* sub.2 (${d-An}),${s1-imm7-2}(${s1-An}),${s2} */
43328 +  {
43329 +    { 0, 0, 0, 0 },
43330 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
43331 +    & ifmt_sub_2_d_indirect_2_s1_indirect_with_offset_2, { 0x8c000400 }
43332 +  },
43333 +/* sub.2 (${d-An})${d-i4-2}++,${s1-imm7-2}(${s1-An}),${s2} */
43334 +  {
43335 +    { 0, 0, 0, 0 },
43336 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
43337 +    & ifmt_sub_2_d_indirect_with_post_increment_2_s1_indirect_with_offset_2, { 0x8a000400 }
43338 +  },
43339 +/* sub.2 ${d-i4-2}(${d-An})++,${s1-imm7-2}(${s1-An}),${s2} */
43340 +  {
43341 +    { 0, 0, 0, 0 },
43342 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
43343 +    & ifmt_sub_2_d_indirect_with_pre_increment_2_s1_indirect_with_offset_2, { 0x8a100400 }
43344 +  },
43345 +/* sub.2 ${d-direct-addr},(${s1-An}),${s2} */
43346 +  {
43347 +    { 0, 0, 0, 0 },
43348 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
43349 +    & ifmt_sub_2_d_direct_s1_indirect_2, { 0x89000400 }
43350 +  },
43351 +/* sub.2 #${d-imm8},(${s1-An}),${s2} */
43352 +  {
43353 +    { 0, 0, 0, 0 },
43354 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
43355 +    & ifmt_sub_2_d_immediate_2_s1_indirect_2, { 0x88000400 }
43356 +  },
43357 +/* sub.2 (${d-An},${d-r}),(${s1-An}),${s2} */
43358 +  {
43359 +    { 0, 0, 0, 0 },
43360 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
43361 +    & ifmt_sub_2_d_indirect_with_index_2_s1_indirect_2, { 0x8b000400 }
43362 +  },
43363 +/* sub.2 ${d-imm7-2}(${d-An}),(${s1-An}),${s2} */
43364 +  {
43365 +    { 0, 0, 0, 0 },
43366 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
43367 +    & ifmt_sub_2_d_indirect_with_offset_2_s1_indirect_2, { 0x8c000400 }
43368 +  },
43369 +/* sub.2 (${d-An}),(${s1-An}),${s2} */
43370 +  {
43371 +    { 0, 0, 0, 0 },
43372 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
43373 +    & ifmt_sub_2_d_indirect_2_s1_indirect_2, { 0x8c000400 }
43374 +  },
43375 +/* sub.2 (${d-An})${d-i4-2}++,(${s1-An}),${s2} */
43376 +  {
43377 +    { 0, 0, 0, 0 },
43378 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
43379 +    & ifmt_sub_2_d_indirect_with_post_increment_2_s1_indirect_2, { 0x8a000400 }
43380 +  },
43381 +/* sub.2 ${d-i4-2}(${d-An})++,(${s1-An}),${s2} */
43382 +  {
43383 +    { 0, 0, 0, 0 },
43384 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
43385 +    & ifmt_sub_2_d_indirect_with_pre_increment_2_s1_indirect_2, { 0x8a100400 }
43386 +  },
43387 +/* sub.2 ${d-direct-addr},(${s1-An})${s1-i4-2}++,${s2} */
43388 +  {
43389 +    { 0, 0, 0, 0 },
43390 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } },
43391 +    & ifmt_sub_2_d_direct_s1_indirect_with_post_increment_2, { 0x89000200 }
43392 +  },
43393 +/* sub.2 #${d-imm8},(${s1-An})${s1-i4-2}++,${s2} */
43394 +  {
43395 +    { 0, 0, 0, 0 },
43396 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } },
43397 +    & ifmt_sub_2_d_immediate_2_s1_indirect_with_post_increment_2, { 0x88000200 }
43398 +  },
43399 +/* sub.2 (${d-An},${d-r}),(${s1-An})${s1-i4-2}++,${s2} */
43400 +  {
43401 +    { 0, 0, 0, 0 },
43402 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } },
43403 +    & ifmt_sub_2_d_indirect_with_index_2_s1_indirect_with_post_increment_2, { 0x8b000200 }
43404 +  },
43405 +/* sub.2 ${d-imm7-2}(${d-An}),(${s1-An})${s1-i4-2}++,${s2} */
43406 +  {
43407 +    { 0, 0, 0, 0 },
43408 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } },
43409 +    & ifmt_sub_2_d_indirect_with_offset_2_s1_indirect_with_post_increment_2, { 0x8c000200 }
43410 +  },
43411 +/* sub.2 (${d-An}),(${s1-An})${s1-i4-2}++,${s2} */
43412 +  {
43413 +    { 0, 0, 0, 0 },
43414 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } },
43415 +    & ifmt_sub_2_d_indirect_2_s1_indirect_with_post_increment_2, { 0x8c000200 }
43416 +  },
43417 +/* sub.2 (${d-An})${d-i4-2}++,(${s1-An})${s1-i4-2}++,${s2} */
43418 +  {
43419 +    { 0, 0, 0, 0 },
43420 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } },
43421 +    & ifmt_sub_2_d_indirect_with_post_increment_2_s1_indirect_with_post_increment_2, { 0x8a000200 }
43422 +  },
43423 +/* sub.2 ${d-i4-2}(${d-An})++,(${s1-An})${s1-i4-2}++,${s2} */
43424 +  {
43425 +    { 0, 0, 0, 0 },
43426 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } },
43427 +    & ifmt_sub_2_d_indirect_with_pre_increment_2_s1_indirect_with_post_increment_2, { 0x8a100200 }
43428 +  },
43429 +/* sub.2 ${d-direct-addr},${s1-i4-2}(${s1-An})++,${s2} */
43430 +  {
43431 +    { 0, 0, 0, 0 },
43432 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
43433 +    & ifmt_sub_2_d_direct_s1_indirect_with_pre_increment_2, { 0x89000210 }
43434 +  },
43435 +/* sub.2 #${d-imm8},${s1-i4-2}(${s1-An})++,${s2} */
43436 +  {
43437 +    { 0, 0, 0, 0 },
43438 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
43439 +    & ifmt_sub_2_d_immediate_2_s1_indirect_with_pre_increment_2, { 0x88000210 }
43440 +  },
43441 +/* sub.2 (${d-An},${d-r}),${s1-i4-2}(${s1-An})++,${s2} */
43442 +  {
43443 +    { 0, 0, 0, 0 },
43444 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
43445 +    & ifmt_sub_2_d_indirect_with_index_2_s1_indirect_with_pre_increment_2, { 0x8b000210 }
43446 +  },
43447 +/* sub.2 ${d-imm7-2}(${d-An}),${s1-i4-2}(${s1-An})++,${s2} */
43448 +  {
43449 +    { 0, 0, 0, 0 },
43450 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
43451 +    & ifmt_sub_2_d_indirect_with_offset_2_s1_indirect_with_pre_increment_2, { 0x8c000210 }
43452 +  },
43453 +/* sub.2 (${d-An}),${s1-i4-2}(${s1-An})++,${s2} */
43454 +  {
43455 +    { 0, 0, 0, 0 },
43456 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
43457 +    & ifmt_sub_2_d_indirect_2_s1_indirect_with_pre_increment_2, { 0x8c000210 }
43458 +  },
43459 +/* sub.2 (${d-An})${d-i4-2}++,${s1-i4-2}(${s1-An})++,${s2} */
43460 +  {
43461 +    { 0, 0, 0, 0 },
43462 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
43463 +    & ifmt_sub_2_d_indirect_with_post_increment_2_s1_indirect_with_pre_increment_2, { 0x8a000210 }
43464 +  },
43465 +/* sub.2 ${d-i4-2}(${d-An})++,${s1-i4-2}(${s1-An})++,${s2} */
43466 +  {
43467 +    { 0, 0, 0, 0 },
43468 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
43469 +    & ifmt_sub_2_d_indirect_with_pre_increment_2_s1_indirect_with_pre_increment_2, { 0x8a100210 }
43470 +  },
43471 +/* add.1 ${d-direct-addr},${s1-direct-addr},${s2} */
43472 +  {
43473 +    { 0, 0, 0, 0 },
43474 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
43475 +    & ifmt_pxadds_u_d_direct_s1_direct, { 0x71008100 }
43476 +  },
43477 +/* add.1 #${d-imm8},${s1-direct-addr},${s2} */
43478 +  {
43479 +    { 0, 0, 0, 0 },
43480 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
43481 +    & ifmt_sub_1_d_immediate_1_s1_direct, { 0x70008100 }
43482 +  },
43483 +/* add.1 (${d-An},${d-r}),${s1-direct-addr},${s2} */
43484 +  {
43485 +    { 0, 0, 0, 0 },
43486 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
43487 +    & ifmt_sub_1_d_indirect_with_index_1_s1_direct, { 0x73008100 }
43488 +  },
43489 +/* add.1 ${d-imm7-1}(${d-An}),${s1-direct-addr},${s2} */
43490 +  {
43491 +    { 0, 0, 0, 0 },
43492 +    { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
43493 +    & ifmt_sub_1_d_indirect_with_offset_1_s1_direct, { 0x74008100 }
43494 +  },
43495 +/* add.1 (${d-An}),${s1-direct-addr},${s2} */
43496 +  {
43497 +    { 0, 0, 0, 0 },
43498 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
43499 +    & ifmt_sub_1_d_indirect_1_s1_direct, { 0x74008100 }
43500 +  },
43501 +/* add.1 (${d-An})${d-i4-1}++,${s1-direct-addr},${s2} */
43502 +  {
43503 +    { 0, 0, 0, 0 },
43504 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
43505 +    & ifmt_sub_1_d_indirect_with_post_increment_1_s1_direct, { 0x72008100 }
43506 +  },
43507 +/* add.1 ${d-i4-1}(${d-An})++,${s1-direct-addr},${s2} */
43508 +  {
43509 +    { 0, 0, 0, 0 },
43510 +    { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
43511 +    & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_direct, { 0x72108100 }
43512 +  },
43513 +/* add.1 ${d-direct-addr},#${s1-imm8},${s2} */
43514 +  {
43515 +    { 0, 0, 0, 0 },
43516 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
43517 +    & ifmt_pxadds_u_d_direct_s1_immediate, { 0x71008000 }
43518 +  },
43519 +/* add.1 #${d-imm8},#${s1-imm8},${s2} */
43520 +  {
43521 +    { 0, 0, 0, 0 },
43522 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
43523 +    & ifmt_sub_1_d_immediate_1_s1_immediate, { 0x70008000 }
43524 +  },
43525 +/* add.1 (${d-An},${d-r}),#${s1-imm8},${s2} */
43526 +  {
43527 +    { 0, 0, 0, 0 },
43528 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
43529 +    & ifmt_sub_1_d_indirect_with_index_1_s1_immediate, { 0x73008000 }
43530 +  },
43531 +/* add.1 ${d-imm7-1}(${d-An}),#${s1-imm8},${s2} */
43532 +  {
43533 +    { 0, 0, 0, 0 },
43534 +    { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
43535 +    & ifmt_sub_1_d_indirect_with_offset_1_s1_immediate, { 0x74008000 }
43536 +  },
43537 +/* add.1 (${d-An}),#${s1-imm8},${s2} */
43538 +  {
43539 +    { 0, 0, 0, 0 },
43540 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
43541 +    & ifmt_sub_1_d_indirect_1_s1_immediate, { 0x74008000 }
43542 +  },
43543 +/* add.1 (${d-An})${d-i4-1}++,#${s1-imm8},${s2} */
43544 +  {
43545 +    { 0, 0, 0, 0 },
43546 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
43547 +    & ifmt_sub_1_d_indirect_with_post_increment_1_s1_immediate, { 0x72008000 }
43548 +  },
43549 +/* add.1 ${d-i4-1}(${d-An})++,#${s1-imm8},${s2} */
43550 +  {
43551 +    { 0, 0, 0, 0 },
43552 +    { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
43553 +    & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_immediate, { 0x72108000 }
43554 +  },
43555 +/* add.1 ${d-direct-addr},(${s1-An},${s1-r}),${s2} */
43556 +  {
43557 +    { 0, 0, 0, 0 },
43558 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
43559 +    & ifmt_sub_1_d_direct_s1_indirect_with_index_1, { 0x71008300 }
43560 +  },
43561 +/* add.1 #${d-imm8},(${s1-An},${s1-r}),${s2} */
43562 +  {
43563 +    { 0, 0, 0, 0 },
43564 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
43565 +    & ifmt_sub_1_d_immediate_1_s1_indirect_with_index_1, { 0x70008300 }
43566 +  },
43567 +/* add.1 (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */
43568 +  {
43569 +    { 0, 0, 0, 0 },
43570 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
43571 +    & ifmt_sub_1_d_indirect_with_index_1_s1_indirect_with_index_1, { 0x73008300 }
43572 +  },
43573 +/* add.1 ${d-imm7-1}(${d-An}),(${s1-An},${s1-r}),${s2} */
43574 +  {
43575 +    { 0, 0, 0, 0 },
43576 +    { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
43577 +    & ifmt_sub_1_d_indirect_with_offset_1_s1_indirect_with_index_1, { 0x74008300 }
43578 +  },
43579 +/* add.1 (${d-An}),(${s1-An},${s1-r}),${s2} */
43580 +  {
43581 +    { 0, 0, 0, 0 },
43582 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
43583 +    & ifmt_sub_1_d_indirect_1_s1_indirect_with_index_1, { 0x74008300 }
43584 +  },
43585 +/* add.1 (${d-An})${d-i4-1}++,(${s1-An},${s1-r}),${s2} */
43586 +  {
43587 +    { 0, 0, 0, 0 },
43588 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
43589 +    & ifmt_sub_1_d_indirect_with_post_increment_1_s1_indirect_with_index_1, { 0x72008300 }
43590 +  },
43591 +/* add.1 ${d-i4-1}(${d-An})++,(${s1-An},${s1-r}),${s2} */
43592 +  {
43593 +    { 0, 0, 0, 0 },
43594 +    { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
43595 +    & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_indirect_with_index_1, { 0x72108300 }
43596 +  },
43597 +/* add.1 ${d-direct-addr},${s1-imm7-1}(${s1-An}),${s2} */
43598 +  {
43599 +    { 0, 0, 0, 0 },
43600 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
43601 +    & ifmt_sub_1_d_direct_s1_indirect_with_offset_1, { 0x71008400 }
43602 +  },
43603 +/* add.1 #${d-imm8},${s1-imm7-1}(${s1-An}),${s2} */
43604 +  {
43605 +    { 0, 0, 0, 0 },
43606 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
43607 +    & ifmt_sub_1_d_immediate_1_s1_indirect_with_offset_1, { 0x70008400 }
43608 +  },
43609 +/* add.1 (${d-An},${d-r}),${s1-imm7-1}(${s1-An}),${s2} */
43610 +  {
43611 +    { 0, 0, 0, 0 },
43612 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
43613 +    & ifmt_sub_1_d_indirect_with_index_1_s1_indirect_with_offset_1, { 0x73008400 }
43614 +  },
43615 +/* add.1 ${d-imm7-1}(${d-An}),${s1-imm7-1}(${s1-An}),${s2} */
43616 +  {
43617 +    { 0, 0, 0, 0 },
43618 +    { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
43619 +    & ifmt_sub_1_d_indirect_with_offset_1_s1_indirect_with_offset_1, { 0x74008400 }
43620 +  },
43621 +/* add.1 (${d-An}),${s1-imm7-1}(${s1-An}),${s2} */
43622 +  {
43623 +    { 0, 0, 0, 0 },
43624 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
43625 +    & ifmt_sub_1_d_indirect_1_s1_indirect_with_offset_1, { 0x74008400 }
43626 +  },
43627 +/* add.1 (${d-An})${d-i4-1}++,${s1-imm7-1}(${s1-An}),${s2} */
43628 +  {
43629 +    { 0, 0, 0, 0 },
43630 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
43631 +    & ifmt_sub_1_d_indirect_with_post_increment_1_s1_indirect_with_offset_1, { 0x72008400 }
43632 +  },
43633 +/* add.1 ${d-i4-1}(${d-An})++,${s1-imm7-1}(${s1-An}),${s2} */
43634 +  {
43635 +    { 0, 0, 0, 0 },
43636 +    { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
43637 +    & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_indirect_with_offset_1, { 0x72108400 }
43638 +  },
43639 +/* add.1 ${d-direct-addr},(${s1-An}),${s2} */
43640 +  {
43641 +    { 0, 0, 0, 0 },
43642 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
43643 +    & ifmt_sub_1_d_direct_s1_indirect_1, { 0x71008400 }
43644 +  },
43645 +/* add.1 #${d-imm8},(${s1-An}),${s2} */
43646 +  {
43647 +    { 0, 0, 0, 0 },
43648 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
43649 +    & ifmt_sub_1_d_immediate_1_s1_indirect_1, { 0x70008400 }
43650 +  },
43651 +/* add.1 (${d-An},${d-r}),(${s1-An}),${s2} */
43652 +  {
43653 +    { 0, 0, 0, 0 },
43654 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
43655 +    & ifmt_sub_1_d_indirect_with_index_1_s1_indirect_1, { 0x73008400 }
43656 +  },
43657 +/* add.1 ${d-imm7-1}(${d-An}),(${s1-An}),${s2} */
43658 +  {
43659 +    { 0, 0, 0, 0 },
43660 +    { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
43661 +    & ifmt_sub_1_d_indirect_with_offset_1_s1_indirect_1, { 0x74008400 }
43662 +  },
43663 +/* add.1 (${d-An}),(${s1-An}),${s2} */
43664 +  {
43665 +    { 0, 0, 0, 0 },
43666 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
43667 +    & ifmt_sub_1_d_indirect_1_s1_indirect_1, { 0x74008400 }
43668 +  },
43669 +/* add.1 (${d-An})${d-i4-1}++,(${s1-An}),${s2} */
43670 +  {
43671 +    { 0, 0, 0, 0 },
43672 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
43673 +    & ifmt_sub_1_d_indirect_with_post_increment_1_s1_indirect_1, { 0x72008400 }
43674 +  },
43675 +/* add.1 ${d-i4-1}(${d-An})++,(${s1-An}),${s2} */
43676 +  {
43677 +    { 0, 0, 0, 0 },
43678 +    { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
43679 +    & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_indirect_1, { 0x72108400 }
43680 +  },
43681 +/* add.1 ${d-direct-addr},(${s1-An})${s1-i4-1}++,${s2} */
43682 +  {
43683 +    { 0, 0, 0, 0 },
43684 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } },
43685 +    & ifmt_sub_1_d_direct_s1_indirect_with_post_increment_1, { 0x71008200 }
43686 +  },
43687 +/* add.1 #${d-imm8},(${s1-An})${s1-i4-1}++,${s2} */
43688 +  {
43689 +    { 0, 0, 0, 0 },
43690 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } },
43691 +    & ifmt_sub_1_d_immediate_1_s1_indirect_with_post_increment_1, { 0x70008200 }
43692 +  },
43693 +/* add.1 (${d-An},${d-r}),(${s1-An})${s1-i4-1}++,${s2} */
43694 +  {
43695 +    { 0, 0, 0, 0 },
43696 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } },
43697 +    & ifmt_sub_1_d_indirect_with_index_1_s1_indirect_with_post_increment_1, { 0x73008200 }
43698 +  },
43699 +/* add.1 ${d-imm7-1}(${d-An}),(${s1-An})${s1-i4-1}++,${s2} */
43700 +  {
43701 +    { 0, 0, 0, 0 },
43702 +    { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } },
43703 +    & ifmt_sub_1_d_indirect_with_offset_1_s1_indirect_with_post_increment_1, { 0x74008200 }
43704 +  },
43705 +/* add.1 (${d-An}),(${s1-An})${s1-i4-1}++,${s2} */
43706 +  {
43707 +    { 0, 0, 0, 0 },
43708 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } },
43709 +    & ifmt_sub_1_d_indirect_1_s1_indirect_with_post_increment_1, { 0x74008200 }
43710 +  },
43711 +/* add.1 (${d-An})${d-i4-1}++,(${s1-An})${s1-i4-1}++,${s2} */
43712 +  {
43713 +    { 0, 0, 0, 0 },
43714 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } },
43715 +    & ifmt_sub_1_d_indirect_with_post_increment_1_s1_indirect_with_post_increment_1, { 0x72008200 }
43716 +  },
43717 +/* add.1 ${d-i4-1}(${d-An})++,(${s1-An})${s1-i4-1}++,${s2} */
43718 +  {
43719 +    { 0, 0, 0, 0 },
43720 +    { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } },
43721 +    & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_indirect_with_post_increment_1, { 0x72108200 }
43722 +  },
43723 +/* add.1 ${d-direct-addr},${s1-i4-1}(${s1-An})++,${s2} */
43724 +  {
43725 +    { 0, 0, 0, 0 },
43726 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
43727 +    & ifmt_sub_1_d_direct_s1_indirect_with_pre_increment_1, { 0x71008210 }
43728 +  },
43729 +/* add.1 #${d-imm8},${s1-i4-1}(${s1-An})++,${s2} */
43730 +  {
43731 +    { 0, 0, 0, 0 },
43732 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
43733 +    & ifmt_sub_1_d_immediate_1_s1_indirect_with_pre_increment_1, { 0x70008210 }
43734 +  },
43735 +/* add.1 (${d-An},${d-r}),${s1-i4-1}(${s1-An})++,${s2} */
43736 +  {
43737 +    { 0, 0, 0, 0 },
43738 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
43739 +    & ifmt_sub_1_d_indirect_with_index_1_s1_indirect_with_pre_increment_1, { 0x73008210 }
43740 +  },
43741 +/* add.1 ${d-imm7-1}(${d-An}),${s1-i4-1}(${s1-An})++,${s2} */
43742 +  {
43743 +    { 0, 0, 0, 0 },
43744 +    { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
43745 +    & ifmt_sub_1_d_indirect_with_offset_1_s1_indirect_with_pre_increment_1, { 0x74008210 }
43746 +  },
43747 +/* add.1 (${d-An}),${s1-i4-1}(${s1-An})++,${s2} */
43748 +  {
43749 +    { 0, 0, 0, 0 },
43750 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
43751 +    & ifmt_sub_1_d_indirect_1_s1_indirect_with_pre_increment_1, { 0x74008210 }
43752 +  },
43753 +/* add.1 (${d-An})${d-i4-1}++,${s1-i4-1}(${s1-An})++,${s2} */
43754 +  {
43755 +    { 0, 0, 0, 0 },
43756 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
43757 +    & ifmt_sub_1_d_indirect_with_post_increment_1_s1_indirect_with_pre_increment_1, { 0x72008210 }
43758 +  },
43759 +/* add.1 ${d-i4-1}(${d-An})++,${s1-i4-1}(${s1-An})++,${s2} */
43760 +  {
43761 +    { 0, 0, 0, 0 },
43762 +    { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
43763 +    & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_indirect_with_pre_increment_1, { 0x72108210 }
43764 +  },
43765 +/* add.4 ${d-direct-addr},${s1-direct-addr},${s2} */
43766 +  {
43767 +    { 0, 0, 0, 0 },
43768 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
43769 +    & ifmt_pxadds_u_d_direct_s1_direct, { 0x79000100 }
43770 +  },
43771 +/* add.4 #${d-imm8},${s1-direct-addr},${s2} */
43772 +  {
43773 +    { 0, 0, 0, 0 },
43774 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
43775 +    & ifmt_pxvi_s_d_immediate_4_s1_direct, { 0x78000100 }
43776 +  },
43777 +/* add.4 (${d-An},${d-r}),${s1-direct-addr},${s2} */
43778 +  {
43779 +    { 0, 0, 0, 0 },
43780 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
43781 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_direct, { 0x7b000100 }
43782 +  },
43783 +/* add.4 ${d-imm7-4}(${d-An}),${s1-direct-addr},${s2} */
43784 +  {
43785 +    { 0, 0, 0, 0 },
43786 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
43787 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_direct, { 0x7c000100 }
43788 +  },
43789 +/* add.4 (${d-An}),${s1-direct-addr},${s2} */
43790 +  {
43791 +    { 0, 0, 0, 0 },
43792 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
43793 +    & ifmt_pxvi_s_d_indirect_4_s1_direct, { 0x7c000100 }
43794 +  },
43795 +/* add.4 (${d-An})${d-i4-4}++,${s1-direct-addr},${s2} */
43796 +  {
43797 +    { 0, 0, 0, 0 },
43798 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
43799 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_direct, { 0x7a000100 }
43800 +  },
43801 +/* add.4 ${d-i4-4}(${d-An})++,${s1-direct-addr},${s2} */
43802 +  {
43803 +    { 0, 0, 0, 0 },
43804 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
43805 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_direct, { 0x7a100100 }
43806 +  },
43807 +/* add.4 ${d-direct-addr},#${s1-imm8},${s2} */
43808 +  {
43809 +    { 0, 0, 0, 0 },
43810 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
43811 +    & ifmt_pxadds_u_d_direct_s1_immediate, { 0x79000000 }
43812 +  },
43813 +/* add.4 #${d-imm8},#${s1-imm8},${s2} */
43814 +  {
43815 +    { 0, 0, 0, 0 },
43816 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
43817 +    & ifmt_pxvi_s_d_immediate_4_s1_immediate, { 0x78000000 }
43818 +  },
43819 +/* add.4 (${d-An},${d-r}),#${s1-imm8},${s2} */
43820 +  {
43821 +    { 0, 0, 0, 0 },
43822 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
43823 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_immediate, { 0x7b000000 }
43824 +  },
43825 +/* add.4 ${d-imm7-4}(${d-An}),#${s1-imm8},${s2} */
43826 +  {
43827 +    { 0, 0, 0, 0 },
43828 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
43829 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_immediate, { 0x7c000000 }
43830 +  },
43831 +/* add.4 (${d-An}),#${s1-imm8},${s2} */
43832 +  {
43833 +    { 0, 0, 0, 0 },
43834 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
43835 +    & ifmt_pxvi_s_d_indirect_4_s1_immediate, { 0x7c000000 }
43836 +  },
43837 +/* add.4 (${d-An})${d-i4-4}++,#${s1-imm8},${s2} */
43838 +  {
43839 +    { 0, 0, 0, 0 },
43840 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
43841 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_immediate, { 0x7a000000 }
43842 +  },
43843 +/* add.4 ${d-i4-4}(${d-An})++,#${s1-imm8},${s2} */
43844 +  {
43845 +    { 0, 0, 0, 0 },
43846 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
43847 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_immediate, { 0x7a100000 }
43848 +  },
43849 +/* add.4 ${d-direct-addr},(${s1-An},${s1-r}),${s2} */
43850 +  {
43851 +    { 0, 0, 0, 0 },
43852 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
43853 +    & ifmt_pxadds_u_d_direct_s1_indirect_with_index_4, { 0x79000300 }
43854 +  },
43855 +/* add.4 #${d-imm8},(${s1-An},${s1-r}),${s2} */
43856 +  {
43857 +    { 0, 0, 0, 0 },
43858 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
43859 +    & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_index_4, { 0x78000300 }
43860 +  },
43861 +/* add.4 (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */
43862 +  {
43863 +    { 0, 0, 0, 0 },
43864 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
43865 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_index_4, { 0x7b000300 }
43866 +  },
43867 +/* add.4 ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}),${s2} */
43868 +  {
43869 +    { 0, 0, 0, 0 },
43870 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
43871 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_index_4, { 0x7c000300 }
43872 +  },
43873 +/* add.4 (${d-An}),(${s1-An},${s1-r}),${s2} */
43874 +  {
43875 +    { 0, 0, 0, 0 },
43876 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
43877 +    & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_index_4, { 0x7c000300 }
43878 +  },
43879 +/* add.4 (${d-An})${d-i4-4}++,(${s1-An},${s1-r}),${s2} */
43880 +  {
43881 +    { 0, 0, 0, 0 },
43882 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
43883 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_index_4, { 0x7a000300 }
43884 +  },
43885 +/* add.4 ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}),${s2} */
43886 +  {
43887 +    { 0, 0, 0, 0 },
43888 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
43889 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_index_4, { 0x7a100300 }
43890 +  },
43891 +/* add.4 ${d-direct-addr},${s1-imm7-4}(${s1-An}),${s2} */
43892 +  {
43893 +    { 0, 0, 0, 0 },
43894 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
43895 +    & ifmt_pxadds_u_d_direct_s1_indirect_with_offset_4, { 0x79000400 }
43896 +  },
43897 +/* add.4 #${d-imm8},${s1-imm7-4}(${s1-An}),${s2} */
43898 +  {
43899 +    { 0, 0, 0, 0 },
43900 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
43901 +    & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_offset_4, { 0x78000400 }
43902 +  },
43903 +/* add.4 (${d-An},${d-r}),${s1-imm7-4}(${s1-An}),${s2} */
43904 +  {
43905 +    { 0, 0, 0, 0 },
43906 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
43907 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_offset_4, { 0x7b000400 }
43908 +  },
43909 +/* add.4 ${d-imm7-4}(${d-An}),${s1-imm7-4}(${s1-An}),${s2} */
43910 +  {
43911 +    { 0, 0, 0, 0 },
43912 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
43913 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_offset_4, { 0x7c000400 }
43914 +  },
43915 +/* add.4 (${d-An}),${s1-imm7-4}(${s1-An}),${s2} */
43916 +  {
43917 +    { 0, 0, 0, 0 },
43918 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
43919 +    & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_offset_4, { 0x7c000400 }
43920 +  },
43921 +/* add.4 (${d-An})${d-i4-4}++,${s1-imm7-4}(${s1-An}),${s2} */
43922 +  {
43923 +    { 0, 0, 0, 0 },
43924 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
43925 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_offset_4, { 0x7a000400 }
43926 +  },
43927 +/* add.4 ${d-i4-4}(${d-An})++,${s1-imm7-4}(${s1-An}),${s2} */
43928 +  {
43929 +    { 0, 0, 0, 0 },
43930 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
43931 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_offset_4, { 0x7a100400 }
43932 +  },
43933 +/* add.4 ${d-direct-addr},(${s1-An}),${s2} */
43934 +  {
43935 +    { 0, 0, 0, 0 },
43936 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
43937 +    & ifmt_pxadds_u_d_direct_s1_indirect_4, { 0x79000400 }
43938 +  },
43939 +/* add.4 #${d-imm8},(${s1-An}),${s2} */
43940 +  {
43941 +    { 0, 0, 0, 0 },
43942 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
43943 +    & ifmt_pxvi_s_d_immediate_4_s1_indirect_4, { 0x78000400 }
43944 +  },
43945 +/* add.4 (${d-An},${d-r}),(${s1-An}),${s2} */
43946 +  {
43947 +    { 0, 0, 0, 0 },
43948 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
43949 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_4, { 0x7b000400 }
43950 +  },
43951 +/* add.4 ${d-imm7-4}(${d-An}),(${s1-An}),${s2} */
43952 +  {
43953 +    { 0, 0, 0, 0 },
43954 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
43955 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_4, { 0x7c000400 }
43956 +  },
43957 +/* add.4 (${d-An}),(${s1-An}),${s2} */
43958 +  {
43959 +    { 0, 0, 0, 0 },
43960 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
43961 +    & ifmt_pxvi_s_d_indirect_4_s1_indirect_4, { 0x7c000400 }
43962 +  },
43963 +/* add.4 (${d-An})${d-i4-4}++,(${s1-An}),${s2} */
43964 +  {
43965 +    { 0, 0, 0, 0 },
43966 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
43967 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_4, { 0x7a000400 }
43968 +  },
43969 +/* add.4 ${d-i4-4}(${d-An})++,(${s1-An}),${s2} */
43970 +  {
43971 +    { 0, 0, 0, 0 },
43972 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
43973 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_4, { 0x7a100400 }
43974 +  },
43975 +/* add.4 ${d-direct-addr},(${s1-An})${s1-i4-4}++,${s2} */
43976 +  {
43977 +    { 0, 0, 0, 0 },
43978 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
43979 +    & ifmt_pxadds_u_d_direct_s1_indirect_with_post_increment_4, { 0x79000200 }
43980 +  },
43981 +/* add.4 #${d-imm8},(${s1-An})${s1-i4-4}++,${s2} */
43982 +  {
43983 +    { 0, 0, 0, 0 },
43984 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
43985 +    & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_post_increment_4, { 0x78000200 }
43986 +  },
43987 +/* add.4 (${d-An},${d-r}),(${s1-An})${s1-i4-4}++,${s2} */
43988 +  {
43989 +    { 0, 0, 0, 0 },
43990 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
43991 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_post_increment_4, { 0x7b000200 }
43992 +  },
43993 +/* add.4 ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-4}++,${s2} */
43994 +  {
43995 +    { 0, 0, 0, 0 },
43996 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
43997 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_post_increment_4, { 0x7c000200 }
43998 +  },
43999 +/* add.4 (${d-An}),(${s1-An})${s1-i4-4}++,${s2} */
44000 +  {
44001 +    { 0, 0, 0, 0 },
44002 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
44003 +    & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_post_increment_4, { 0x7c000200 }
44004 +  },
44005 +/* add.4 (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-4}++,${s2} */
44006 +  {
44007 +    { 0, 0, 0, 0 },
44008 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
44009 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_post_increment_4, { 0x7a000200 }
44010 +  },
44011 +/* add.4 ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-4}++,${s2} */
44012 +  {
44013 +    { 0, 0, 0, 0 },
44014 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
44015 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_post_increment_4, { 0x7a100200 }
44016 +  },
44017 +/* add.4 ${d-direct-addr},${s1-i4-4}(${s1-An})++,${s2} */
44018 +  {
44019 +    { 0, 0, 0, 0 },
44020 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
44021 +    & ifmt_pxadds_u_d_direct_s1_indirect_with_pre_increment_4, { 0x79000210 }
44022 +  },
44023 +/* add.4 #${d-imm8},${s1-i4-4}(${s1-An})++,${s2} */
44024 +  {
44025 +    { 0, 0, 0, 0 },
44026 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
44027 +    & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_pre_increment_4, { 0x78000210 }
44028 +  },
44029 +/* add.4 (${d-An},${d-r}),${s1-i4-4}(${s1-An})++,${s2} */
44030 +  {
44031 +    { 0, 0, 0, 0 },
44032 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
44033 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_pre_increment_4, { 0x7b000210 }
44034 +  },
44035 +/* add.4 ${d-imm7-4}(${d-An}),${s1-i4-4}(${s1-An})++,${s2} */
44036 +  {
44037 +    { 0, 0, 0, 0 },
44038 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
44039 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_pre_increment_4, { 0x7c000210 }
44040 +  },
44041 +/* add.4 (${d-An}),${s1-i4-4}(${s1-An})++,${s2} */
44042 +  {
44043 +    { 0, 0, 0, 0 },
44044 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
44045 +    & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_pre_increment_4, { 0x7c000210 }
44046 +  },
44047 +/* add.4 (${d-An})${d-i4-4}++,${s1-i4-4}(${s1-An})++,${s2} */
44048 +  {
44049 +    { 0, 0, 0, 0 },
44050 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
44051 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_pre_increment_4, { 0x7a000210 }
44052 +  },
44053 +/* add.4 ${d-i4-4}(${d-An})++,${s1-i4-4}(${s1-An})++,${s2} */
44054 +  {
44055 +    { 0, 0, 0, 0 },
44056 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
44057 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_pre_increment_4, { 0x7a100210 }
44058 +  },
44059 +/* add.2 ${d-direct-addr},${s1-direct-addr},${s2} */
44060 +  {
44061 +    { 0, 0, 0, 0 },
44062 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
44063 +    & ifmt_pxadds_u_d_direct_s1_direct, { 0x71000100 }
44064 +  },
44065 +/* add.2 #${d-imm8},${s1-direct-addr},${s2} */
44066 +  {
44067 +    { 0, 0, 0, 0 },
44068 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
44069 +    & ifmt_pxadds_u_d_immediate_2_s1_direct, { 0x70000100 }
44070 +  },
44071 +/* add.2 (${d-An},${d-r}),${s1-direct-addr},${s2} */
44072 +  {
44073 +    { 0, 0, 0, 0 },
44074 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
44075 +    & ifmt_pxadds_u_d_indirect_with_index_2_s1_direct, { 0x73000100 }
44076 +  },
44077 +/* add.2 ${d-imm7-2}(${d-An}),${s1-direct-addr},${s2} */
44078 +  {
44079 +    { 0, 0, 0, 0 },
44080 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
44081 +    & ifmt_pxadds_u_d_indirect_with_offset_2_s1_direct, { 0x74000100 }
44082 +  },
44083 +/* add.2 (${d-An}),${s1-direct-addr},${s2} */
44084 +  {
44085 +    { 0, 0, 0, 0 },
44086 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
44087 +    & ifmt_pxadds_u_d_indirect_2_s1_direct, { 0x74000100 }
44088 +  },
44089 +/* add.2 (${d-An})${d-i4-2}++,${s1-direct-addr},${s2} */
44090 +  {
44091 +    { 0, 0, 0, 0 },
44092 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
44093 +    & ifmt_pxadds_u_d_indirect_with_post_increment_2_s1_direct, { 0x72000100 }
44094 +  },
44095 +/* add.2 ${d-i4-2}(${d-An})++,${s1-direct-addr},${s2} */
44096 +  {
44097 +    { 0, 0, 0, 0 },
44098 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
44099 +    & ifmt_pxadds_u_d_indirect_with_pre_increment_2_s1_direct, { 0x72100100 }
44100 +  },
44101 +/* add.2 ${d-direct-addr},#${s1-imm8},${s2} */
44102 +  {
44103 +    { 0, 0, 0, 0 },
44104 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
44105 +    & ifmt_pxadds_u_d_direct_s1_immediate, { 0x71000000 }
44106 +  },
44107 +/* add.2 #${d-imm8},#${s1-imm8},${s2} */
44108 +  {
44109 +    { 0, 0, 0, 0 },
44110 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
44111 +    & ifmt_pxadds_u_d_immediate_2_s1_immediate, { 0x70000000 }
44112 +  },
44113 +/* add.2 (${d-An},${d-r}),#${s1-imm8},${s2} */
44114 +  {
44115 +    { 0, 0, 0, 0 },
44116 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
44117 +    & ifmt_pxadds_u_d_indirect_with_index_2_s1_immediate, { 0x73000000 }
44118 +  },
44119 +/* add.2 ${d-imm7-2}(${d-An}),#${s1-imm8},${s2} */
44120 +  {
44121 +    { 0, 0, 0, 0 },
44122 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
44123 +    & ifmt_pxadds_u_d_indirect_with_offset_2_s1_immediate, { 0x74000000 }
44124 +  },
44125 +/* add.2 (${d-An}),#${s1-imm8},${s2} */
44126 +  {
44127 +    { 0, 0, 0, 0 },
44128 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
44129 +    & ifmt_pxadds_u_d_indirect_2_s1_immediate, { 0x74000000 }
44130 +  },
44131 +/* add.2 (${d-An})${d-i4-2}++,#${s1-imm8},${s2} */
44132 +  {
44133 +    { 0, 0, 0, 0 },
44134 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
44135 +    & ifmt_pxadds_u_d_indirect_with_post_increment_2_s1_immediate, { 0x72000000 }
44136 +  },
44137 +/* add.2 ${d-i4-2}(${d-An})++,#${s1-imm8},${s2} */
44138 +  {
44139 +    { 0, 0, 0, 0 },
44140 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
44141 +    & ifmt_pxadds_u_d_indirect_with_pre_increment_2_s1_immediate, { 0x72100000 }
44142 +  },
44143 +/* add.2 ${d-direct-addr},(${s1-An},${s1-r}),${s2} */
44144 +  {
44145 +    { 0, 0, 0, 0 },
44146 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
44147 +    & ifmt_sub_2_d_direct_s1_indirect_with_index_2, { 0x71000300 }
44148 +  },
44149 +/* add.2 #${d-imm8},(${s1-An},${s1-r}),${s2} */
44150 +  {
44151 +    { 0, 0, 0, 0 },
44152 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
44153 +    & ifmt_sub_2_d_immediate_2_s1_indirect_with_index_2, { 0x70000300 }
44154 +  },
44155 +/* add.2 (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */
44156 +  {
44157 +    { 0, 0, 0, 0 },
44158 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
44159 +    & ifmt_sub_2_d_indirect_with_index_2_s1_indirect_with_index_2, { 0x73000300 }
44160 +  },
44161 +/* add.2 ${d-imm7-2}(${d-An}),(${s1-An},${s1-r}),${s2} */
44162 +  {
44163 +    { 0, 0, 0, 0 },
44164 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
44165 +    & ifmt_sub_2_d_indirect_with_offset_2_s1_indirect_with_index_2, { 0x74000300 }
44166 +  },
44167 +/* add.2 (${d-An}),(${s1-An},${s1-r}),${s2} */
44168 +  {
44169 +    { 0, 0, 0, 0 },
44170 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
44171 +    & ifmt_sub_2_d_indirect_2_s1_indirect_with_index_2, { 0x74000300 }
44172 +  },
44173 +/* add.2 (${d-An})${d-i4-2}++,(${s1-An},${s1-r}),${s2} */
44174 +  {
44175 +    { 0, 0, 0, 0 },
44176 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
44177 +    & ifmt_sub_2_d_indirect_with_post_increment_2_s1_indirect_with_index_2, { 0x72000300 }
44178 +  },
44179 +/* add.2 ${d-i4-2}(${d-An})++,(${s1-An},${s1-r}),${s2} */
44180 +  {
44181 +    { 0, 0, 0, 0 },
44182 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
44183 +    & ifmt_sub_2_d_indirect_with_pre_increment_2_s1_indirect_with_index_2, { 0x72100300 }
44184 +  },
44185 +/* add.2 ${d-direct-addr},${s1-imm7-2}(${s1-An}),${s2} */
44186 +  {
44187 +    { 0, 0, 0, 0 },
44188 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
44189 +    & ifmt_sub_2_d_direct_s1_indirect_with_offset_2, { 0x71000400 }
44190 +  },
44191 +/* add.2 #${d-imm8},${s1-imm7-2}(${s1-An}),${s2} */
44192 +  {
44193 +    { 0, 0, 0, 0 },
44194 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
44195 +    & ifmt_sub_2_d_immediate_2_s1_indirect_with_offset_2, { 0x70000400 }
44196 +  },
44197 +/* add.2 (${d-An},${d-r}),${s1-imm7-2}(${s1-An}),${s2} */
44198 +  {
44199 +    { 0, 0, 0, 0 },
44200 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
44201 +    & ifmt_sub_2_d_indirect_with_index_2_s1_indirect_with_offset_2, { 0x73000400 }
44202 +  },
44203 +/* add.2 ${d-imm7-2}(${d-An}),${s1-imm7-2}(${s1-An}),${s2} */
44204 +  {
44205 +    { 0, 0, 0, 0 },
44206 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
44207 +    & ifmt_sub_2_d_indirect_with_offset_2_s1_indirect_with_offset_2, { 0x74000400 }
44208 +  },
44209 +/* add.2 (${d-An}),${s1-imm7-2}(${s1-An}),${s2} */
44210 +  {
44211 +    { 0, 0, 0, 0 },
44212 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
44213 +    & ifmt_sub_2_d_indirect_2_s1_indirect_with_offset_2, { 0x74000400 }
44214 +  },
44215 +/* add.2 (${d-An})${d-i4-2}++,${s1-imm7-2}(${s1-An}),${s2} */
44216 +  {
44217 +    { 0, 0, 0, 0 },
44218 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
44219 +    & ifmt_sub_2_d_indirect_with_post_increment_2_s1_indirect_with_offset_2, { 0x72000400 }
44220 +  },
44221 +/* add.2 ${d-i4-2}(${d-An})++,${s1-imm7-2}(${s1-An}),${s2} */
44222 +  {
44223 +    { 0, 0, 0, 0 },
44224 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
44225 +    & ifmt_sub_2_d_indirect_with_pre_increment_2_s1_indirect_with_offset_2, { 0x72100400 }
44226 +  },
44227 +/* add.2 ${d-direct-addr},(${s1-An}),${s2} */
44228 +  {
44229 +    { 0, 0, 0, 0 },
44230 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
44231 +    & ifmt_sub_2_d_direct_s1_indirect_2, { 0x71000400 }
44232 +  },
44233 +/* add.2 #${d-imm8},(${s1-An}),${s2} */
44234 +  {
44235 +    { 0, 0, 0, 0 },
44236 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
44237 +    & ifmt_sub_2_d_immediate_2_s1_indirect_2, { 0x70000400 }
44238 +  },
44239 +/* add.2 (${d-An},${d-r}),(${s1-An}),${s2} */
44240 +  {
44241 +    { 0, 0, 0, 0 },
44242 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
44243 +    & ifmt_sub_2_d_indirect_with_index_2_s1_indirect_2, { 0x73000400 }
44244 +  },
44245 +/* add.2 ${d-imm7-2}(${d-An}),(${s1-An}),${s2} */
44246 +  {
44247 +    { 0, 0, 0, 0 },
44248 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
44249 +    & ifmt_sub_2_d_indirect_with_offset_2_s1_indirect_2, { 0x74000400 }
44250 +  },
44251 +/* add.2 (${d-An}),(${s1-An}),${s2} */
44252 +  {
44253 +    { 0, 0, 0, 0 },
44254 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
44255 +    & ifmt_sub_2_d_indirect_2_s1_indirect_2, { 0x74000400 }
44256 +  },
44257 +/* add.2 (${d-An})${d-i4-2}++,(${s1-An}),${s2} */
44258 +  {
44259 +    { 0, 0, 0, 0 },
44260 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
44261 +    & ifmt_sub_2_d_indirect_with_post_increment_2_s1_indirect_2, { 0x72000400 }
44262 +  },
44263 +/* add.2 ${d-i4-2}(${d-An})++,(${s1-An}),${s2} */
44264 +  {
44265 +    { 0, 0, 0, 0 },
44266 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
44267 +    & ifmt_sub_2_d_indirect_with_pre_increment_2_s1_indirect_2, { 0x72100400 }
44268 +  },
44269 +/* add.2 ${d-direct-addr},(${s1-An})${s1-i4-2}++,${s2} */
44270 +  {
44271 +    { 0, 0, 0, 0 },
44272 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } },
44273 +    & ifmt_sub_2_d_direct_s1_indirect_with_post_increment_2, { 0x71000200 }
44274 +  },
44275 +/* add.2 #${d-imm8},(${s1-An})${s1-i4-2}++,${s2} */
44276 +  {
44277 +    { 0, 0, 0, 0 },
44278 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } },
44279 +    & ifmt_sub_2_d_immediate_2_s1_indirect_with_post_increment_2, { 0x70000200 }
44280 +  },
44281 +/* add.2 (${d-An},${d-r}),(${s1-An})${s1-i4-2}++,${s2} */
44282 +  {
44283 +    { 0, 0, 0, 0 },
44284 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } },
44285 +    & ifmt_sub_2_d_indirect_with_index_2_s1_indirect_with_post_increment_2, { 0x73000200 }
44286 +  },
44287 +/* add.2 ${d-imm7-2}(${d-An}),(${s1-An})${s1-i4-2}++,${s2} */
44288 +  {
44289 +    { 0, 0, 0, 0 },
44290 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } },
44291 +    & ifmt_sub_2_d_indirect_with_offset_2_s1_indirect_with_post_increment_2, { 0x74000200 }
44292 +  },
44293 +/* add.2 (${d-An}),(${s1-An})${s1-i4-2}++,${s2} */
44294 +  {
44295 +    { 0, 0, 0, 0 },
44296 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } },
44297 +    & ifmt_sub_2_d_indirect_2_s1_indirect_with_post_increment_2, { 0x74000200 }
44298 +  },
44299 +/* add.2 (${d-An})${d-i4-2}++,(${s1-An})${s1-i4-2}++,${s2} */
44300 +  {
44301 +    { 0, 0, 0, 0 },
44302 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } },
44303 +    & ifmt_sub_2_d_indirect_with_post_increment_2_s1_indirect_with_post_increment_2, { 0x72000200 }
44304 +  },
44305 +/* add.2 ${d-i4-2}(${d-An})++,(${s1-An})${s1-i4-2}++,${s2} */
44306 +  {
44307 +    { 0, 0, 0, 0 },
44308 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } },
44309 +    & ifmt_sub_2_d_indirect_with_pre_increment_2_s1_indirect_with_post_increment_2, { 0x72100200 }
44310 +  },
44311 +/* add.2 ${d-direct-addr},${s1-i4-2}(${s1-An})++,${s2} */
44312 +  {
44313 +    { 0, 0, 0, 0 },
44314 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
44315 +    & ifmt_sub_2_d_direct_s1_indirect_with_pre_increment_2, { 0x71000210 }
44316 +  },
44317 +/* add.2 #${d-imm8},${s1-i4-2}(${s1-An})++,${s2} */
44318 +  {
44319 +    { 0, 0, 0, 0 },
44320 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
44321 +    & ifmt_sub_2_d_immediate_2_s1_indirect_with_pre_increment_2, { 0x70000210 }
44322 +  },
44323 +/* add.2 (${d-An},${d-r}),${s1-i4-2}(${s1-An})++,${s2} */
44324 +  {
44325 +    { 0, 0, 0, 0 },
44326 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
44327 +    & ifmt_sub_2_d_indirect_with_index_2_s1_indirect_with_pre_increment_2, { 0x73000210 }
44328 +  },
44329 +/* add.2 ${d-imm7-2}(${d-An}),${s1-i4-2}(${s1-An})++,${s2} */
44330 +  {
44331 +    { 0, 0, 0, 0 },
44332 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
44333 +    & ifmt_sub_2_d_indirect_with_offset_2_s1_indirect_with_pre_increment_2, { 0x74000210 }
44334 +  },
44335 +/* add.2 (${d-An}),${s1-i4-2}(${s1-An})++,${s2} */
44336 +  {
44337 +    { 0, 0, 0, 0 },
44338 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
44339 +    & ifmt_sub_2_d_indirect_2_s1_indirect_with_pre_increment_2, { 0x74000210 }
44340 +  },
44341 +/* add.2 (${d-An})${d-i4-2}++,${s1-i4-2}(${s1-An})++,${s2} */
44342 +  {
44343 +    { 0, 0, 0, 0 },
44344 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
44345 +    & ifmt_sub_2_d_indirect_with_post_increment_2_s1_indirect_with_pre_increment_2, { 0x72000210 }
44346 +  },
44347 +/* add.2 ${d-i4-2}(${d-An})++,${s1-i4-2}(${s1-An})++,${s2} */
44348 +  {
44349 +    { 0, 0, 0, 0 },
44350 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
44351 +    & ifmt_sub_2_d_indirect_with_pre_increment_2_s1_indirect_with_pre_increment_2, { 0x72100210 }
44352 +  },
44353 +/* not.4 ${d-direct-addr},${s1-direct-addr} */
44354 +  {
44355 +    { 0, 0, 0, 0 },
44356 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), 0 } },
44357 +    & ifmt_movea_d_direct_s1_direct, { 0x1005100 }
44358 +  },
44359 +/* not.4 #${d-imm8},${s1-direct-addr} */
44360 +  {
44361 +    { 0, 0, 0, 0 },
44362 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), 0 } },
44363 +    & ifmt_movea_d_immediate_4_s1_direct, { 0x5100 }
44364 +  },
44365 +/* not.4 (${d-An},${d-r}),${s1-direct-addr} */
44366 +  {
44367 +    { 0, 0, 0, 0 },
44368 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), 0 } },
44369 +    & ifmt_movea_d_indirect_with_index_4_s1_direct, { 0x3005100 }
44370 +  },
44371 +/* not.4 ${d-imm7-4}(${d-An}),${s1-direct-addr} */
44372 +  {
44373 +    { 0, 0, 0, 0 },
44374 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), 0 } },
44375 +    & ifmt_movea_d_indirect_with_offset_4_s1_direct, { 0x4005100 }
44376 +  },
44377 +/* not.4 (${d-An}),${s1-direct-addr} */
44378 +  {
44379 +    { 0, 0, 0, 0 },
44380 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), 0 } },
44381 +    & ifmt_movea_d_indirect_4_s1_direct, { 0x4005100 }
44382 +  },
44383 +/* not.4 (${d-An})${d-i4-4}++,${s1-direct-addr} */
44384 +  {
44385 +    { 0, 0, 0, 0 },
44386 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_DIRECT_ADDR), 0 } },
44387 +    & ifmt_movea_d_indirect_with_post_increment_4_s1_direct, { 0x2005100 }
44388 +  },
44389 +/* not.4 ${d-i4-4}(${d-An})++,${s1-direct-addr} */
44390 +  {
44391 +    { 0, 0, 0, 0 },
44392 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), 0 } },
44393 +    & ifmt_movea_d_indirect_with_pre_increment_4_s1_direct, { 0x2105100 }
44394 +  },
44395 +/* not.4 ${d-direct-addr},#${s1-imm8} */
44396 +  {
44397 +    { 0, 0, 0, 0 },
44398 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), 0 } },
44399 +    & ifmt_movea_d_direct_s1_immediate, { 0x1005000 }
44400 +  },
44401 +/* not.4 #${d-imm8},#${s1-imm8} */
44402 +  {
44403 +    { 0, 0, 0, 0 },
44404 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), 0 } },
44405 +    & ifmt_movea_d_immediate_4_s1_immediate, { 0x5000 }
44406 +  },
44407 +/* not.4 (${d-An},${d-r}),#${s1-imm8} */
44408 +  {
44409 +    { 0, 0, 0, 0 },
44410 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), 0 } },
44411 +    & ifmt_movea_d_indirect_with_index_4_s1_immediate, { 0x3005000 }
44412 +  },
44413 +/* not.4 ${d-imm7-4}(${d-An}),#${s1-imm8} */
44414 +  {
44415 +    { 0, 0, 0, 0 },
44416 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } },
44417 +    & ifmt_movea_d_indirect_with_offset_4_s1_immediate, { 0x4005000 }
44418 +  },
44419 +/* not.4 (${d-An}),#${s1-imm8} */
44420 +  {
44421 +    { 0, 0, 0, 0 },
44422 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } },
44423 +    & ifmt_movea_d_indirect_4_s1_immediate, { 0x4005000 }
44424 +  },
44425 +/* not.4 (${d-An})${d-i4-4}++,#${s1-imm8} */
44426 +  {
44427 +    { 0, 0, 0, 0 },
44428 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '#', OP (S1_IMM8), 0 } },
44429 +    & ifmt_movea_d_indirect_with_post_increment_4_s1_immediate, { 0x2005000 }
44430 +  },
44431 +/* not.4 ${d-i4-4}(${d-An})++,#${s1-imm8} */
44432 +  {
44433 +    { 0, 0, 0, 0 },
44434 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), 0 } },
44435 +    & ifmt_movea_d_indirect_with_pre_increment_4_s1_immediate, { 0x2105000 }
44436 +  },
44437 +/* not.4 ${d-direct-addr},(${s1-An},${s1-r}) */
44438 +  {
44439 +    { 0, 0, 0, 0 },
44440 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
44441 +    & ifmt_movea_d_direct_s1_indirect_with_index_4, { 0x1005300 }
44442 +  },
44443 +/* not.4 #${d-imm8},(${s1-An},${s1-r}) */
44444 +  {
44445 +    { 0, 0, 0, 0 },
44446 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
44447 +    & ifmt_movea_d_immediate_4_s1_indirect_with_index_4, { 0x5300 }
44448 +  },
44449 +/* not.4 (${d-An},${d-r}),(${s1-An},${s1-r}) */
44450 +  {
44451 +    { 0, 0, 0, 0 },
44452 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
44453 +    & ifmt_movea_d_indirect_with_index_4_s1_indirect_with_index_4, { 0x3005300 }
44454 +  },
44455 +/* not.4 ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}) */
44456 +  {
44457 +    { 0, 0, 0, 0 },
44458 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
44459 +    & ifmt_movea_d_indirect_with_offset_4_s1_indirect_with_index_4, { 0x4005300 }
44460 +  },
44461 +/* not.4 (${d-An}),(${s1-An},${s1-r}) */
44462 +  {
44463 +    { 0, 0, 0, 0 },
44464 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
44465 +    & ifmt_movea_d_indirect_4_s1_indirect_with_index_4, { 0x4005300 }
44466 +  },
44467 +/* not.4 (${d-An})${d-i4-4}++,(${s1-An},${s1-r}) */
44468 +  {
44469 +    { 0, 0, 0, 0 },
44470 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
44471 +    & ifmt_movea_d_indirect_with_post_increment_4_s1_indirect_with_index_4, { 0x2005300 }
44472 +  },
44473 +/* not.4 ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}) */
44474 +  {
44475 +    { 0, 0, 0, 0 },
44476 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
44477 +    & ifmt_movea_d_indirect_with_pre_increment_4_s1_indirect_with_index_4, { 0x2105300 }
44478 +  },
44479 +/* not.4 ${d-direct-addr},${s1-imm7-4}(${s1-An}) */
44480 +  {
44481 +    { 0, 0, 0, 0 },
44482 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
44483 +    & ifmt_movea_d_direct_s1_indirect_with_offset_4, { 0x1005400 }
44484 +  },
44485 +/* not.4 #${d-imm8},${s1-imm7-4}(${s1-An}) */
44486 +  {
44487 +    { 0, 0, 0, 0 },
44488 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
44489 +    & ifmt_movea_d_immediate_4_s1_indirect_with_offset_4, { 0x5400 }
44490 +  },
44491 +/* not.4 (${d-An},${d-r}),${s1-imm7-4}(${s1-An}) */
44492 +  {
44493 +    { 0, 0, 0, 0 },
44494 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
44495 +    & ifmt_movea_d_indirect_with_index_4_s1_indirect_with_offset_4, { 0x3005400 }
44496 +  },
44497 +/* not.4 ${d-imm7-4}(${d-An}),${s1-imm7-4}(${s1-An}) */
44498 +  {
44499 +    { 0, 0, 0, 0 },
44500 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
44501 +    & ifmt_movea_d_indirect_with_offset_4_s1_indirect_with_offset_4, { 0x4005400 }
44502 +  },
44503 +/* not.4 (${d-An}),${s1-imm7-4}(${s1-An}) */
44504 +  {
44505 +    { 0, 0, 0, 0 },
44506 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
44507 +    & ifmt_movea_d_indirect_4_s1_indirect_with_offset_4, { 0x4005400 }
44508 +  },
44509 +/* not.4 (${d-An})${d-i4-4}++,${s1-imm7-4}(${s1-An}) */
44510 +  {
44511 +    { 0, 0, 0, 0 },
44512 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
44513 +    & ifmt_movea_d_indirect_with_post_increment_4_s1_indirect_with_offset_4, { 0x2005400 }
44514 +  },
44515 +/* not.4 ${d-i4-4}(${d-An})++,${s1-imm7-4}(${s1-An}) */
44516 +  {
44517 +    { 0, 0, 0, 0 },
44518 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', 0 } },
44519 +    & ifmt_movea_d_indirect_with_pre_increment_4_s1_indirect_with_offset_4, { 0x2105400 }
44520 +  },
44521 +/* not.4 ${d-direct-addr},(${s1-An}) */
44522 +  {
44523 +    { 0, 0, 0, 0 },
44524 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', 0 } },
44525 +    & ifmt_movea_d_direct_s1_indirect_4, { 0x1005400 }
44526 +  },
44527 +/* not.4 #${d-imm8},(${s1-An}) */
44528 +  {
44529 +    { 0, 0, 0, 0 },
44530 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', 0 } },
44531 +    & ifmt_movea_d_immediate_4_s1_indirect_4, { 0x5400 }
44532 +  },
44533 +/* not.4 (${d-An},${d-r}),(${s1-An}) */
44534 +  {
44535 +    { 0, 0, 0, 0 },
44536 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', 0 } },
44537 +    & ifmt_movea_d_indirect_with_index_4_s1_indirect_4, { 0x3005400 }
44538 +  },
44539 +/* not.4 ${d-imm7-4}(${d-An}),(${s1-An}) */
44540 +  {
44541 +    { 0, 0, 0, 0 },
44542 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } },
44543 +    & ifmt_movea_d_indirect_with_offset_4_s1_indirect_4, { 0x4005400 }
44544 +  },
44545 +/* not.4 (${d-An}),(${s1-An}) */
44546 +  {
44547 +    { 0, 0, 0, 0 },
44548 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } },
44549 +    & ifmt_movea_d_indirect_4_s1_indirect_4, { 0x4005400 }
44550 +  },
44551 +/* not.4 (${d-An})${d-i4-4}++,(${s1-An}) */
44552 +  {
44553 +    { 0, 0, 0, 0 },
44554 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', 0 } },
44555 +    & ifmt_movea_d_indirect_with_post_increment_4_s1_indirect_4, { 0x2005400 }
44556 +  },
44557 +/* not.4 ${d-i4-4}(${d-An})++,(${s1-An}) */
44558 +  {
44559 +    { 0, 0, 0, 0 },
44560 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', 0 } },
44561 +    & ifmt_movea_d_indirect_with_pre_increment_4_s1_indirect_4, { 0x2105400 }
44562 +  },
44563 +/* not.4 ${d-direct-addr},(${s1-An})${s1-i4-4}++ */
44564 +  {
44565 +    { 0, 0, 0, 0 },
44566 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
44567 +    & ifmt_movea_d_direct_s1_indirect_with_post_increment_4, { 0x1005200 }
44568 +  },
44569 +/* not.4 #${d-imm8},(${s1-An})${s1-i4-4}++ */
44570 +  {
44571 +    { 0, 0, 0, 0 },
44572 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
44573 +    & ifmt_movea_d_immediate_4_s1_indirect_with_post_increment_4, { 0x5200 }
44574 +  },
44575 +/* not.4 (${d-An},${d-r}),(${s1-An})${s1-i4-4}++ */
44576 +  {
44577 +    { 0, 0, 0, 0 },
44578 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
44579 +    & ifmt_movea_d_indirect_with_index_4_s1_indirect_with_post_increment_4, { 0x3005200 }
44580 +  },
44581 +/* not.4 ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-4}++ */
44582 +  {
44583 +    { 0, 0, 0, 0 },
44584 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
44585 +    & ifmt_movea_d_indirect_with_offset_4_s1_indirect_with_post_increment_4, { 0x4005200 }
44586 +  },
44587 +/* not.4 (${d-An}),(${s1-An})${s1-i4-4}++ */
44588 +  {
44589 +    { 0, 0, 0, 0 },
44590 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
44591 +    & ifmt_movea_d_indirect_4_s1_indirect_with_post_increment_4, { 0x4005200 }
44592 +  },
44593 +/* not.4 (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-4}++ */
44594 +  {
44595 +    { 0, 0, 0, 0 },
44596 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
44597 +    & ifmt_movea_d_indirect_with_post_increment_4_s1_indirect_with_post_increment_4, { 0x2005200 }
44598 +  },
44599 +/* not.4 ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-4}++ */
44600 +  {
44601 +    { 0, 0, 0, 0 },
44602 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', 0 } },
44603 +    & ifmt_movea_d_indirect_with_pre_increment_4_s1_indirect_with_post_increment_4, { 0x2105200 }
44604 +  },
44605 +/* not.4 ${d-direct-addr},${s1-i4-4}(${s1-An})++ */
44606 +  {
44607 +    { 0, 0, 0, 0 },
44608 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
44609 +    & ifmt_movea_d_direct_s1_indirect_with_pre_increment_4, { 0x1005210 }
44610 +  },
44611 +/* not.4 #${d-imm8},${s1-i4-4}(${s1-An})++ */
44612 +  {
44613 +    { 0, 0, 0, 0 },
44614 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
44615 +    & ifmt_movea_d_immediate_4_s1_indirect_with_pre_increment_4, { 0x5210 }
44616 +  },
44617 +/* not.4 (${d-An},${d-r}),${s1-i4-4}(${s1-An})++ */
44618 +  {
44619 +    { 0, 0, 0, 0 },
44620 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
44621 +    & ifmt_movea_d_indirect_with_index_4_s1_indirect_with_pre_increment_4, { 0x3005210 }
44622 +  },
44623 +/* not.4 ${d-imm7-4}(${d-An}),${s1-i4-4}(${s1-An})++ */
44624 +  {
44625 +    { 0, 0, 0, 0 },
44626 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
44627 +    & ifmt_movea_d_indirect_with_offset_4_s1_indirect_with_pre_increment_4, { 0x4005210 }
44628 +  },
44629 +/* not.4 (${d-An}),${s1-i4-4}(${s1-An})++ */
44630 +  {
44631 +    { 0, 0, 0, 0 },
44632 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
44633 +    & ifmt_movea_d_indirect_4_s1_indirect_with_pre_increment_4, { 0x4005210 }
44634 +  },
44635 +/* not.4 (${d-An})${d-i4-4}++,${s1-i4-4}(${s1-An})++ */
44636 +  {
44637 +    { 0, 0, 0, 0 },
44638 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
44639 +    & ifmt_movea_d_indirect_with_post_increment_4_s1_indirect_with_pre_increment_4, { 0x2005210 }
44640 +  },
44641 +/* not.4 ${d-i4-4}(${d-An})++,${s1-i4-4}(${s1-An})++ */
44642 +  {
44643 +    { 0, 0, 0, 0 },
44644 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', 0 } },
44645 +    & ifmt_movea_d_indirect_with_pre_increment_4_s1_indirect_with_pre_increment_4, { 0x2105210 }
44646 +  },
44647 +/* not.2 ${d-direct-addr},${s1-direct-addr} */
44648 +  {
44649 +    { 0, 0, 0, 0 },
44650 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), 0 } },
44651 +    & ifmt_movea_d_direct_s1_direct, { 0x1005900 }
44652 +  },
44653 +/* not.2 #${d-imm8},${s1-direct-addr} */
44654 +  {
44655 +    { 0, 0, 0, 0 },
44656 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), 0 } },
44657 +    & ifmt_move_2_d_immediate_2_s1_direct, { 0x5900 }
44658 +  },
44659 +/* not.2 (${d-An},${d-r}),${s1-direct-addr} */
44660 +  {
44661 +    { 0, 0, 0, 0 },
44662 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), 0 } },
44663 +    & ifmt_move_2_d_indirect_with_index_2_s1_direct, { 0x3005900 }
44664 +  },
44665 +/* not.2 ${d-imm7-2}(${d-An}),${s1-direct-addr} */
44666 +  {
44667 +    { 0, 0, 0, 0 },
44668 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), 0 } },
44669 +    & ifmt_move_2_d_indirect_with_offset_2_s1_direct, { 0x4005900 }
44670 +  },
44671 +/* not.2 (${d-An}),${s1-direct-addr} */
44672 +  {
44673 +    { 0, 0, 0, 0 },
44674 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), 0 } },
44675 +    & ifmt_move_2_d_indirect_2_s1_direct, { 0x4005900 }
44676 +  },
44677 +/* not.2 (${d-An})${d-i4-2}++,${s1-direct-addr} */
44678 +  {
44679 +    { 0, 0, 0, 0 },
44680 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_DIRECT_ADDR), 0 } },
44681 +    & ifmt_move_2_d_indirect_with_post_increment_2_s1_direct, { 0x2005900 }
44682 +  },
44683 +/* not.2 ${d-i4-2}(${d-An})++,${s1-direct-addr} */
44684 +  {
44685 +    { 0, 0, 0, 0 },
44686 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), 0 } },
44687 +    & ifmt_move_2_d_indirect_with_pre_increment_2_s1_direct, { 0x2105900 }
44688 +  },
44689 +/* not.2 ${d-direct-addr},#${s1-imm8} */
44690 +  {
44691 +    { 0, 0, 0, 0 },
44692 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), 0 } },
44693 +    & ifmt_movea_d_direct_s1_immediate, { 0x1005800 }
44694 +  },
44695 +/* not.2 #${d-imm8},#${s1-imm8} */
44696 +  {
44697 +    { 0, 0, 0, 0 },
44698 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), 0 } },
44699 +    & ifmt_move_2_d_immediate_2_s1_immediate, { 0x5800 }
44700 +  },
44701 +/* not.2 (${d-An},${d-r}),#${s1-imm8} */
44702 +  {
44703 +    { 0, 0, 0, 0 },
44704 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), 0 } },
44705 +    & ifmt_move_2_d_indirect_with_index_2_s1_immediate, { 0x3005800 }
44706 +  },
44707 +/* not.2 ${d-imm7-2}(${d-An}),#${s1-imm8} */
44708 +  {
44709 +    { 0, 0, 0, 0 },
44710 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } },
44711 +    & ifmt_move_2_d_indirect_with_offset_2_s1_immediate, { 0x4005800 }
44712 +  },
44713 +/* not.2 (${d-An}),#${s1-imm8} */
44714 +  {
44715 +    { 0, 0, 0, 0 },
44716 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), 0 } },
44717 +    & ifmt_move_2_d_indirect_2_s1_immediate, { 0x4005800 }
44718 +  },
44719 +/* not.2 (${d-An})${d-i4-2}++,#${s1-imm8} */
44720 +  {
44721 +    { 0, 0, 0, 0 },
44722 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '#', OP (S1_IMM8), 0 } },
44723 +    & ifmt_move_2_d_indirect_with_post_increment_2_s1_immediate, { 0x2005800 }
44724 +  },
44725 +/* not.2 ${d-i4-2}(${d-An})++,#${s1-imm8} */
44726 +  {
44727 +    { 0, 0, 0, 0 },
44728 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), 0 } },
44729 +    & ifmt_move_2_d_indirect_with_pre_increment_2_s1_immediate, { 0x2105800 }
44730 +  },
44731 +/* not.2 ${d-direct-addr},(${s1-An},${s1-r}) */
44732 +  {
44733 +    { 0, 0, 0, 0 },
44734 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
44735 +    & ifmt_move_2_d_direct_s1_indirect_with_index_2, { 0x1005b00 }
44736 +  },
44737 +/* not.2 #${d-imm8},(${s1-An},${s1-r}) */
44738 +  {
44739 +    { 0, 0, 0, 0 },
44740 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
44741 +    & ifmt_move_2_d_immediate_2_s1_indirect_with_index_2, { 0x5b00 }
44742 +  },
44743 +/* not.2 (${d-An},${d-r}),(${s1-An},${s1-r}) */
44744 +  {
44745 +    { 0, 0, 0, 0 },
44746 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
44747 +    & ifmt_move_2_d_indirect_with_index_2_s1_indirect_with_index_2, { 0x3005b00 }
44748 +  },
44749 +/* not.2 ${d-imm7-2}(${d-An}),(${s1-An},${s1-r}) */
44750 +  {
44751 +    { 0, 0, 0, 0 },
44752 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
44753 +    & ifmt_move_2_d_indirect_with_offset_2_s1_indirect_with_index_2, { 0x4005b00 }
44754 +  },
44755 +/* not.2 (${d-An}),(${s1-An},${s1-r}) */
44756 +  {
44757 +    { 0, 0, 0, 0 },
44758 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
44759 +    & ifmt_move_2_d_indirect_2_s1_indirect_with_index_2, { 0x4005b00 }
44760 +  },
44761 +/* not.2 (${d-An})${d-i4-2}++,(${s1-An},${s1-r}) */
44762 +  {
44763 +    { 0, 0, 0, 0 },
44764 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
44765 +    & ifmt_move_2_d_indirect_with_post_increment_2_s1_indirect_with_index_2, { 0x2005b00 }
44766 +  },
44767 +/* not.2 ${d-i4-2}(${d-An})++,(${s1-An},${s1-r}) */
44768 +  {
44769 +    { 0, 0, 0, 0 },
44770 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', 0 } },
44771 +    & ifmt_move_2_d_indirect_with_pre_increment_2_s1_indirect_with_index_2, { 0x2105b00 }
44772 +  },
44773 +/* not.2 ${d-direct-addr},${s1-imm7-2}(${s1-An}) */
44774 +  {
44775 +    { 0, 0, 0, 0 },
44776 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } },
44777 +    & ifmt_move_2_d_direct_s1_indirect_with_offset_2, { 0x1005c00 }
44778 +  },
44779 +/* not.2 #${d-imm8},${s1-imm7-2}(${s1-An}) */
44780 +  {
44781 +    { 0, 0, 0, 0 },
44782 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } },
44783 +    & ifmt_move_2_d_immediate_2_s1_indirect_with_offset_2, { 0x5c00 }
44784 +  },
44785 +/* not.2 (${d-An},${d-r}),${s1-imm7-2}(${s1-An}) */
44786 +  {
44787 +    { 0, 0, 0, 0 },
44788 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } },
44789 +    & ifmt_move_2_d_indirect_with_index_2_s1_indirect_with_offset_2, { 0x3005c00 }
44790 +  },
44791 +/* not.2 ${d-imm7-2}(${d-An}),${s1-imm7-2}(${s1-An}) */
44792 +  {
44793 +    { 0, 0, 0, 0 },
44794 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } },
44795 +    & ifmt_move_2_d_indirect_with_offset_2_s1_indirect_with_offset_2, { 0x4005c00 }
44796 +  },
44797 +/* not.2 (${d-An}),${s1-imm7-2}(${s1-An}) */
44798 +  {
44799 +    { 0, 0, 0, 0 },
44800 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } },
44801 +    & ifmt_move_2_d_indirect_2_s1_indirect_with_offset_2, { 0x4005c00 }
44802 +  },
44803 +/* not.2 (${d-An})${d-i4-2}++,${s1-imm7-2}(${s1-An}) */
44804 +  {
44805 +    { 0, 0, 0, 0 },
44806 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } },
44807 +    & ifmt_move_2_d_indirect_with_post_increment_2_s1_indirect_with_offset_2, { 0x2005c00 }
44808 +  },
44809 +/* not.2 ${d-i4-2}(${d-An})++,${s1-imm7-2}(${s1-An}) */
44810 +  {
44811 +    { 0, 0, 0, 0 },
44812 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', 0 } },
44813 +    & ifmt_move_2_d_indirect_with_pre_increment_2_s1_indirect_with_offset_2, { 0x2105c00 }
44814 +  },
44815 +/* not.2 ${d-direct-addr},(${s1-An}) */
44816 +  {
44817 +    { 0, 0, 0, 0 },
44818 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', 0 } },
44819 +    & ifmt_move_2_d_direct_s1_indirect_2, { 0x1005c00 }
44820 +  },
44821 +/* not.2 #${d-imm8},(${s1-An}) */
44822 +  {
44823 +    { 0, 0, 0, 0 },
44824 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', 0 } },
44825 +    & ifmt_move_2_d_immediate_2_s1_indirect_2, { 0x5c00 }
44826 +  },
44827 +/* not.2 (${d-An},${d-r}),(${s1-An}) */
44828 +  {
44829 +    { 0, 0, 0, 0 },
44830 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', 0 } },
44831 +    & ifmt_move_2_d_indirect_with_index_2_s1_indirect_2, { 0x3005c00 }
44832 +  },
44833 +/* not.2 ${d-imm7-2}(${d-An}),(${s1-An}) */
44834 +  {
44835 +    { 0, 0, 0, 0 },
44836 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } },
44837 +    & ifmt_move_2_d_indirect_with_offset_2_s1_indirect_2, { 0x4005c00 }
44838 +  },
44839 +/* not.2 (${d-An}),(${s1-An}) */
44840 +  {
44841 +    { 0, 0, 0, 0 },
44842 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', 0 } },
44843 +    & ifmt_move_2_d_indirect_2_s1_indirect_2, { 0x4005c00 }
44844 +  },
44845 +/* not.2 (${d-An})${d-i4-2}++,(${s1-An}) */
44846 +  {
44847 +    { 0, 0, 0, 0 },
44848 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ')', 0 } },
44849 +    & ifmt_move_2_d_indirect_with_post_increment_2_s1_indirect_2, { 0x2005c00 }
44850 +  },
44851 +/* not.2 ${d-i4-2}(${d-An})++,(${s1-An}) */
44852 +  {
44853 +    { 0, 0, 0, 0 },
44854 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', 0 } },
44855 +    & ifmt_move_2_d_indirect_with_pre_increment_2_s1_indirect_2, { 0x2105c00 }
44856 +  },
44857 +/* not.2 ${d-direct-addr},(${s1-An})${s1-i4-2}++ */
44858 +  {
44859 +    { 0, 0, 0, 0 },
44860 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } },
44861 +    & ifmt_move_2_d_direct_s1_indirect_with_post_increment_2, { 0x1005a00 }
44862 +  },
44863 +/* not.2 #${d-imm8},(${s1-An})${s1-i4-2}++ */
44864 +  {
44865 +    { 0, 0, 0, 0 },
44866 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } },
44867 +    & ifmt_move_2_d_immediate_2_s1_indirect_with_post_increment_2, { 0x5a00 }
44868 +  },
44869 +/* not.2 (${d-An},${d-r}),(${s1-An})${s1-i4-2}++ */
44870 +  {
44871 +    { 0, 0, 0, 0 },
44872 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } },
44873 +    & ifmt_move_2_d_indirect_with_index_2_s1_indirect_with_post_increment_2, { 0x3005a00 }
44874 +  },
44875 +/* not.2 ${d-imm7-2}(${d-An}),(${s1-An})${s1-i4-2}++ */
44876 +  {
44877 +    { 0, 0, 0, 0 },
44878 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } },
44879 +    & ifmt_move_2_d_indirect_with_offset_2_s1_indirect_with_post_increment_2, { 0x4005a00 }
44880 +  },
44881 +/* not.2 (${d-An}),(${s1-An})${s1-i4-2}++ */
44882 +  {
44883 +    { 0, 0, 0, 0 },
44884 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } },
44885 +    & ifmt_move_2_d_indirect_2_s1_indirect_with_post_increment_2, { 0x4005a00 }
44886 +  },
44887 +/* not.2 (${d-An})${d-i4-2}++,(${s1-An})${s1-i4-2}++ */
44888 +  {
44889 +    { 0, 0, 0, 0 },
44890 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } },
44891 +    & ifmt_move_2_d_indirect_with_post_increment_2_s1_indirect_with_post_increment_2, { 0x2005a00 }
44892 +  },
44893 +/* not.2 ${d-i4-2}(${d-An})++,(${s1-An})${s1-i4-2}++ */
44894 +  {
44895 +    { 0, 0, 0, 0 },
44896 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', 0 } },
44897 +    & ifmt_move_2_d_indirect_with_pre_increment_2_s1_indirect_with_post_increment_2, { 0x2105a00 }
44898 +  },
44899 +/* not.2 ${d-direct-addr},${s1-i4-2}(${s1-An})++ */
44900 +  {
44901 +    { 0, 0, 0, 0 },
44902 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } },
44903 +    & ifmt_move_2_d_direct_s1_indirect_with_pre_increment_2, { 0x1005a10 }
44904 +  },
44905 +/* not.2 #${d-imm8},${s1-i4-2}(${s1-An})++ */
44906 +  {
44907 +    { 0, 0, 0, 0 },
44908 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } },
44909 +    & ifmt_move_2_d_immediate_2_s1_indirect_with_pre_increment_2, { 0x5a10 }
44910 +  },
44911 +/* not.2 (${d-An},${d-r}),${s1-i4-2}(${s1-An})++ */
44912 +  {
44913 +    { 0, 0, 0, 0 },
44914 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } },
44915 +    & ifmt_move_2_d_indirect_with_index_2_s1_indirect_with_pre_increment_2, { 0x3005a10 }
44916 +  },
44917 +/* not.2 ${d-imm7-2}(${d-An}),${s1-i4-2}(${s1-An})++ */
44918 +  {
44919 +    { 0, 0, 0, 0 },
44920 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } },
44921 +    & ifmt_move_2_d_indirect_with_offset_2_s1_indirect_with_pre_increment_2, { 0x4005a10 }
44922 +  },
44923 +/* not.2 (${d-An}),${s1-i4-2}(${s1-An})++ */
44924 +  {
44925 +    { 0, 0, 0, 0 },
44926 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } },
44927 +    & ifmt_move_2_d_indirect_2_s1_indirect_with_pre_increment_2, { 0x4005a10 }
44928 +  },
44929 +/* not.2 (${d-An})${d-i4-2}++,${s1-i4-2}(${s1-An})++ */
44930 +  {
44931 +    { 0, 0, 0, 0 },
44932 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } },
44933 +    & ifmt_move_2_d_indirect_with_post_increment_2_s1_indirect_with_pre_increment_2, { 0x2005a10 }
44934 +  },
44935 +/* not.2 ${d-i4-2}(${d-An})++,${s1-i4-2}(${s1-An})++ */
44936 +  {
44937 +    { 0, 0, 0, 0 },
44938 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', 0 } },
44939 +    & ifmt_move_2_d_indirect_with_pre_increment_2_s1_indirect_with_pre_increment_2, { 0x2105a10 }
44940 +  },
44941 +/* xor.1 ${d-direct-addr},${s1-direct-addr},${s2} */
44942 +  {
44943 +    { 0, 0, 0, 0 },
44944 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
44945 +    & ifmt_pxadds_u_d_direct_s1_direct, { 0x61008100 }
44946 +  },
44947 +/* xor.1 #${d-imm8},${s1-direct-addr},${s2} */
44948 +  {
44949 +    { 0, 0, 0, 0 },
44950 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
44951 +    & ifmt_sub_1_d_immediate_1_s1_direct, { 0x60008100 }
44952 +  },
44953 +/* xor.1 (${d-An},${d-r}),${s1-direct-addr},${s2} */
44954 +  {
44955 +    { 0, 0, 0, 0 },
44956 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
44957 +    & ifmt_sub_1_d_indirect_with_index_1_s1_direct, { 0x63008100 }
44958 +  },
44959 +/* xor.1 ${d-imm7-1}(${d-An}),${s1-direct-addr},${s2} */
44960 +  {
44961 +    { 0, 0, 0, 0 },
44962 +    { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
44963 +    & ifmt_sub_1_d_indirect_with_offset_1_s1_direct, { 0x64008100 }
44964 +  },
44965 +/* xor.1 (${d-An}),${s1-direct-addr},${s2} */
44966 +  {
44967 +    { 0, 0, 0, 0 },
44968 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
44969 +    & ifmt_sub_1_d_indirect_1_s1_direct, { 0x64008100 }
44970 +  },
44971 +/* xor.1 (${d-An})${d-i4-1}++,${s1-direct-addr},${s2} */
44972 +  {
44973 +    { 0, 0, 0, 0 },
44974 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
44975 +    & ifmt_sub_1_d_indirect_with_post_increment_1_s1_direct, { 0x62008100 }
44976 +  },
44977 +/* xor.1 ${d-i4-1}(${d-An})++,${s1-direct-addr},${s2} */
44978 +  {
44979 +    { 0, 0, 0, 0 },
44980 +    { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
44981 +    & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_direct, { 0x62108100 }
44982 +  },
44983 +/* xor.1 ${d-direct-addr},#${s1-imm8},${s2} */
44984 +  {
44985 +    { 0, 0, 0, 0 },
44986 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
44987 +    & ifmt_pxadds_u_d_direct_s1_immediate, { 0x61008000 }
44988 +  },
44989 +/* xor.1 #${d-imm8},#${s1-imm8},${s2} */
44990 +  {
44991 +    { 0, 0, 0, 0 },
44992 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
44993 +    & ifmt_sub_1_d_immediate_1_s1_immediate, { 0x60008000 }
44994 +  },
44995 +/* xor.1 (${d-An},${d-r}),#${s1-imm8},${s2} */
44996 +  {
44997 +    { 0, 0, 0, 0 },
44998 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
44999 +    & ifmt_sub_1_d_indirect_with_index_1_s1_immediate, { 0x63008000 }
45000 +  },
45001 +/* xor.1 ${d-imm7-1}(${d-An}),#${s1-imm8},${s2} */
45002 +  {
45003 +    { 0, 0, 0, 0 },
45004 +    { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
45005 +    & ifmt_sub_1_d_indirect_with_offset_1_s1_immediate, { 0x64008000 }
45006 +  },
45007 +/* xor.1 (${d-An}),#${s1-imm8},${s2} */
45008 +  {
45009 +    { 0, 0, 0, 0 },
45010 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
45011 +    & ifmt_sub_1_d_indirect_1_s1_immediate, { 0x64008000 }
45012 +  },
45013 +/* xor.1 (${d-An})${d-i4-1}++,#${s1-imm8},${s2} */
45014 +  {
45015 +    { 0, 0, 0, 0 },
45016 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
45017 +    & ifmt_sub_1_d_indirect_with_post_increment_1_s1_immediate, { 0x62008000 }
45018 +  },
45019 +/* xor.1 ${d-i4-1}(${d-An})++,#${s1-imm8},${s2} */
45020 +  {
45021 +    { 0, 0, 0, 0 },
45022 +    { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
45023 +    & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_immediate, { 0x62108000 }
45024 +  },
45025 +/* xor.1 ${d-direct-addr},(${s1-An},${s1-r}),${s2} */
45026 +  {
45027 +    { 0, 0, 0, 0 },
45028 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
45029 +    & ifmt_sub_1_d_direct_s1_indirect_with_index_1, { 0x61008300 }
45030 +  },
45031 +/* xor.1 #${d-imm8},(${s1-An},${s1-r}),${s2} */
45032 +  {
45033 +    { 0, 0, 0, 0 },
45034 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
45035 +    & ifmt_sub_1_d_immediate_1_s1_indirect_with_index_1, { 0x60008300 }
45036 +  },
45037 +/* xor.1 (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */
45038 +  {
45039 +    { 0, 0, 0, 0 },
45040 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
45041 +    & ifmt_sub_1_d_indirect_with_index_1_s1_indirect_with_index_1, { 0x63008300 }
45042 +  },
45043 +/* xor.1 ${d-imm7-1}(${d-An}),(${s1-An},${s1-r}),${s2} */
45044 +  {
45045 +    { 0, 0, 0, 0 },
45046 +    { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
45047 +    & ifmt_sub_1_d_indirect_with_offset_1_s1_indirect_with_index_1, { 0x64008300 }
45048 +  },
45049 +/* xor.1 (${d-An}),(${s1-An},${s1-r}),${s2} */
45050 +  {
45051 +    { 0, 0, 0, 0 },
45052 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
45053 +    & ifmt_sub_1_d_indirect_1_s1_indirect_with_index_1, { 0x64008300 }
45054 +  },
45055 +/* xor.1 (${d-An})${d-i4-1}++,(${s1-An},${s1-r}),${s2} */
45056 +  {
45057 +    { 0, 0, 0, 0 },
45058 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
45059 +    & ifmt_sub_1_d_indirect_with_post_increment_1_s1_indirect_with_index_1, { 0x62008300 }
45060 +  },
45061 +/* xor.1 ${d-i4-1}(${d-An})++,(${s1-An},${s1-r}),${s2} */
45062 +  {
45063 +    { 0, 0, 0, 0 },
45064 +    { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
45065 +    & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_indirect_with_index_1, { 0x62108300 }
45066 +  },
45067 +/* xor.1 ${d-direct-addr},${s1-imm7-1}(${s1-An}),${s2} */
45068 +  {
45069 +    { 0, 0, 0, 0 },
45070 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
45071 +    & ifmt_sub_1_d_direct_s1_indirect_with_offset_1, { 0x61008400 }
45072 +  },
45073 +/* xor.1 #${d-imm8},${s1-imm7-1}(${s1-An}),${s2} */
45074 +  {
45075 +    { 0, 0, 0, 0 },
45076 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
45077 +    & ifmt_sub_1_d_immediate_1_s1_indirect_with_offset_1, { 0x60008400 }
45078 +  },
45079 +/* xor.1 (${d-An},${d-r}),${s1-imm7-1}(${s1-An}),${s2} */
45080 +  {
45081 +    { 0, 0, 0, 0 },
45082 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
45083 +    & ifmt_sub_1_d_indirect_with_index_1_s1_indirect_with_offset_1, { 0x63008400 }
45084 +  },
45085 +/* xor.1 ${d-imm7-1}(${d-An}),${s1-imm7-1}(${s1-An}),${s2} */
45086 +  {
45087 +    { 0, 0, 0, 0 },
45088 +    { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
45089 +    & ifmt_sub_1_d_indirect_with_offset_1_s1_indirect_with_offset_1, { 0x64008400 }
45090 +  },
45091 +/* xor.1 (${d-An}),${s1-imm7-1}(${s1-An}),${s2} */
45092 +  {
45093 +    { 0, 0, 0, 0 },
45094 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
45095 +    & ifmt_sub_1_d_indirect_1_s1_indirect_with_offset_1, { 0x64008400 }
45096 +  },
45097 +/* xor.1 (${d-An})${d-i4-1}++,${s1-imm7-1}(${s1-An}),${s2} */
45098 +  {
45099 +    { 0, 0, 0, 0 },
45100 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
45101 +    & ifmt_sub_1_d_indirect_with_post_increment_1_s1_indirect_with_offset_1, { 0x62008400 }
45102 +  },
45103 +/* xor.1 ${d-i4-1}(${d-An})++,${s1-imm7-1}(${s1-An}),${s2} */
45104 +  {
45105 +    { 0, 0, 0, 0 },
45106 +    { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
45107 +    & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_indirect_with_offset_1, { 0x62108400 }
45108 +  },
45109 +/* xor.1 ${d-direct-addr},(${s1-An}),${s2} */
45110 +  {
45111 +    { 0, 0, 0, 0 },
45112 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
45113 +    & ifmt_sub_1_d_direct_s1_indirect_1, { 0x61008400 }
45114 +  },
45115 +/* xor.1 #${d-imm8},(${s1-An}),${s2} */
45116 +  {
45117 +    { 0, 0, 0, 0 },
45118 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
45119 +    & ifmt_sub_1_d_immediate_1_s1_indirect_1, { 0x60008400 }
45120 +  },
45121 +/* xor.1 (${d-An},${d-r}),(${s1-An}),${s2} */
45122 +  {
45123 +    { 0, 0, 0, 0 },
45124 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
45125 +    & ifmt_sub_1_d_indirect_with_index_1_s1_indirect_1, { 0x63008400 }
45126 +  },
45127 +/* xor.1 ${d-imm7-1}(${d-An}),(${s1-An}),${s2} */
45128 +  {
45129 +    { 0, 0, 0, 0 },
45130 +    { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
45131 +    & ifmt_sub_1_d_indirect_with_offset_1_s1_indirect_1, { 0x64008400 }
45132 +  },
45133 +/* xor.1 (${d-An}),(${s1-An}),${s2} */
45134 +  {
45135 +    { 0, 0, 0, 0 },
45136 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
45137 +    & ifmt_sub_1_d_indirect_1_s1_indirect_1, { 0x64008400 }
45138 +  },
45139 +/* xor.1 (${d-An})${d-i4-1}++,(${s1-An}),${s2} */
45140 +  {
45141 +    { 0, 0, 0, 0 },
45142 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
45143 +    & ifmt_sub_1_d_indirect_with_post_increment_1_s1_indirect_1, { 0x62008400 }
45144 +  },
45145 +/* xor.1 ${d-i4-1}(${d-An})++,(${s1-An}),${s2} */
45146 +  {
45147 +    { 0, 0, 0, 0 },
45148 +    { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
45149 +    & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_indirect_1, { 0x62108400 }
45150 +  },
45151 +/* xor.1 ${d-direct-addr},(${s1-An})${s1-i4-1}++,${s2} */
45152 +  {
45153 +    { 0, 0, 0, 0 },
45154 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } },
45155 +    & ifmt_sub_1_d_direct_s1_indirect_with_post_increment_1, { 0x61008200 }
45156 +  },
45157 +/* xor.1 #${d-imm8},(${s1-An})${s1-i4-1}++,${s2} */
45158 +  {
45159 +    { 0, 0, 0, 0 },
45160 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } },
45161 +    & ifmt_sub_1_d_immediate_1_s1_indirect_with_post_increment_1, { 0x60008200 }
45162 +  },
45163 +/* xor.1 (${d-An},${d-r}),(${s1-An})${s1-i4-1}++,${s2} */
45164 +  {
45165 +    { 0, 0, 0, 0 },
45166 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } },
45167 +    & ifmt_sub_1_d_indirect_with_index_1_s1_indirect_with_post_increment_1, { 0x63008200 }
45168 +  },
45169 +/* xor.1 ${d-imm7-1}(${d-An}),(${s1-An})${s1-i4-1}++,${s2} */
45170 +  {
45171 +    { 0, 0, 0, 0 },
45172 +    { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } },
45173 +    & ifmt_sub_1_d_indirect_with_offset_1_s1_indirect_with_post_increment_1, { 0x64008200 }
45174 +  },
45175 +/* xor.1 (${d-An}),(${s1-An})${s1-i4-1}++,${s2} */
45176 +  {
45177 +    { 0, 0, 0, 0 },
45178 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } },
45179 +    & ifmt_sub_1_d_indirect_1_s1_indirect_with_post_increment_1, { 0x64008200 }
45180 +  },
45181 +/* xor.1 (${d-An})${d-i4-1}++,(${s1-An})${s1-i4-1}++,${s2} */
45182 +  {
45183 +    { 0, 0, 0, 0 },
45184 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } },
45185 +    & ifmt_sub_1_d_indirect_with_post_increment_1_s1_indirect_with_post_increment_1, { 0x62008200 }
45186 +  },
45187 +/* xor.1 ${d-i4-1}(${d-An})++,(${s1-An})${s1-i4-1}++,${s2} */
45188 +  {
45189 +    { 0, 0, 0, 0 },
45190 +    { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } },
45191 +    & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_indirect_with_post_increment_1, { 0x62108200 }
45192 +  },
45193 +/* xor.1 ${d-direct-addr},${s1-i4-1}(${s1-An})++,${s2} */
45194 +  {
45195 +    { 0, 0, 0, 0 },
45196 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
45197 +    & ifmt_sub_1_d_direct_s1_indirect_with_pre_increment_1, { 0x61008210 }
45198 +  },
45199 +/* xor.1 #${d-imm8},${s1-i4-1}(${s1-An})++,${s2} */
45200 +  {
45201 +    { 0, 0, 0, 0 },
45202 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
45203 +    & ifmt_sub_1_d_immediate_1_s1_indirect_with_pre_increment_1, { 0x60008210 }
45204 +  },
45205 +/* xor.1 (${d-An},${d-r}),${s1-i4-1}(${s1-An})++,${s2} */
45206 +  {
45207 +    { 0, 0, 0, 0 },
45208 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
45209 +    & ifmt_sub_1_d_indirect_with_index_1_s1_indirect_with_pre_increment_1, { 0x63008210 }
45210 +  },
45211 +/* xor.1 ${d-imm7-1}(${d-An}),${s1-i4-1}(${s1-An})++,${s2} */
45212 +  {
45213 +    { 0, 0, 0, 0 },
45214 +    { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
45215 +    & ifmt_sub_1_d_indirect_with_offset_1_s1_indirect_with_pre_increment_1, { 0x64008210 }
45216 +  },
45217 +/* xor.1 (${d-An}),${s1-i4-1}(${s1-An})++,${s2} */
45218 +  {
45219 +    { 0, 0, 0, 0 },
45220 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
45221 +    & ifmt_sub_1_d_indirect_1_s1_indirect_with_pre_increment_1, { 0x64008210 }
45222 +  },
45223 +/* xor.1 (${d-An})${d-i4-1}++,${s1-i4-1}(${s1-An})++,${s2} */
45224 +  {
45225 +    { 0, 0, 0, 0 },
45226 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
45227 +    & ifmt_sub_1_d_indirect_with_post_increment_1_s1_indirect_with_pre_increment_1, { 0x62008210 }
45228 +  },
45229 +/* xor.1 ${d-i4-1}(${d-An})++,${s1-i4-1}(${s1-An})++,${s2} */
45230 +  {
45231 +    { 0, 0, 0, 0 },
45232 +    { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
45233 +    & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_indirect_with_pre_increment_1, { 0x62108210 }
45234 +  },
45235 +/* or.1 ${d-direct-addr},${s1-direct-addr},${s2} */
45236 +  {
45237 +    { 0, 0, 0, 0 },
45238 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
45239 +    & ifmt_pxadds_u_d_direct_s1_direct, { 0x51008100 }
45240 +  },
45241 +/* or.1 #${d-imm8},${s1-direct-addr},${s2} */
45242 +  {
45243 +    { 0, 0, 0, 0 },
45244 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
45245 +    & ifmt_sub_1_d_immediate_1_s1_direct, { 0x50008100 }
45246 +  },
45247 +/* or.1 (${d-An},${d-r}),${s1-direct-addr},${s2} */
45248 +  {
45249 +    { 0, 0, 0, 0 },
45250 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
45251 +    & ifmt_sub_1_d_indirect_with_index_1_s1_direct, { 0x53008100 }
45252 +  },
45253 +/* or.1 ${d-imm7-1}(${d-An}),${s1-direct-addr},${s2} */
45254 +  {
45255 +    { 0, 0, 0, 0 },
45256 +    { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
45257 +    & ifmt_sub_1_d_indirect_with_offset_1_s1_direct, { 0x54008100 }
45258 +  },
45259 +/* or.1 (${d-An}),${s1-direct-addr},${s2} */
45260 +  {
45261 +    { 0, 0, 0, 0 },
45262 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
45263 +    & ifmt_sub_1_d_indirect_1_s1_direct, { 0x54008100 }
45264 +  },
45265 +/* or.1 (${d-An})${d-i4-1}++,${s1-direct-addr},${s2} */
45266 +  {
45267 +    { 0, 0, 0, 0 },
45268 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
45269 +    & ifmt_sub_1_d_indirect_with_post_increment_1_s1_direct, { 0x52008100 }
45270 +  },
45271 +/* or.1 ${d-i4-1}(${d-An})++,${s1-direct-addr},${s2} */
45272 +  {
45273 +    { 0, 0, 0, 0 },
45274 +    { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
45275 +    & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_direct, { 0x52108100 }
45276 +  },
45277 +/* or.1 ${d-direct-addr},#${s1-imm8},${s2} */
45278 +  {
45279 +    { 0, 0, 0, 0 },
45280 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
45281 +    & ifmt_pxadds_u_d_direct_s1_immediate, { 0x51008000 }
45282 +  },
45283 +/* or.1 #${d-imm8},#${s1-imm8},${s2} */
45284 +  {
45285 +    { 0, 0, 0, 0 },
45286 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
45287 +    & ifmt_sub_1_d_immediate_1_s1_immediate, { 0x50008000 }
45288 +  },
45289 +/* or.1 (${d-An},${d-r}),#${s1-imm8},${s2} */
45290 +  {
45291 +    { 0, 0, 0, 0 },
45292 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
45293 +    & ifmt_sub_1_d_indirect_with_index_1_s1_immediate, { 0x53008000 }
45294 +  },
45295 +/* or.1 ${d-imm7-1}(${d-An}),#${s1-imm8},${s2} */
45296 +  {
45297 +    { 0, 0, 0, 0 },
45298 +    { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
45299 +    & ifmt_sub_1_d_indirect_with_offset_1_s1_immediate, { 0x54008000 }
45300 +  },
45301 +/* or.1 (${d-An}),#${s1-imm8},${s2} */
45302 +  {
45303 +    { 0, 0, 0, 0 },
45304 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
45305 +    & ifmt_sub_1_d_indirect_1_s1_immediate, { 0x54008000 }
45306 +  },
45307 +/* or.1 (${d-An})${d-i4-1}++,#${s1-imm8},${s2} */
45308 +  {
45309 +    { 0, 0, 0, 0 },
45310 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
45311 +    & ifmt_sub_1_d_indirect_with_post_increment_1_s1_immediate, { 0x52008000 }
45312 +  },
45313 +/* or.1 ${d-i4-1}(${d-An})++,#${s1-imm8},${s2} */
45314 +  {
45315 +    { 0, 0, 0, 0 },
45316 +    { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
45317 +    & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_immediate, { 0x52108000 }
45318 +  },
45319 +/* or.1 ${d-direct-addr},(${s1-An},${s1-r}),${s2} */
45320 +  {
45321 +    { 0, 0, 0, 0 },
45322 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
45323 +    & ifmt_sub_1_d_direct_s1_indirect_with_index_1, { 0x51008300 }
45324 +  },
45325 +/* or.1 #${d-imm8},(${s1-An},${s1-r}),${s2} */
45326 +  {
45327 +    { 0, 0, 0, 0 },
45328 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
45329 +    & ifmt_sub_1_d_immediate_1_s1_indirect_with_index_1, { 0x50008300 }
45330 +  },
45331 +/* or.1 (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */
45332 +  {
45333 +    { 0, 0, 0, 0 },
45334 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
45335 +    & ifmt_sub_1_d_indirect_with_index_1_s1_indirect_with_index_1, { 0x53008300 }
45336 +  },
45337 +/* or.1 ${d-imm7-1}(${d-An}),(${s1-An},${s1-r}),${s2} */
45338 +  {
45339 +    { 0, 0, 0, 0 },
45340 +    { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
45341 +    & ifmt_sub_1_d_indirect_with_offset_1_s1_indirect_with_index_1, { 0x54008300 }
45342 +  },
45343 +/* or.1 (${d-An}),(${s1-An},${s1-r}),${s2} */
45344 +  {
45345 +    { 0, 0, 0, 0 },
45346 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
45347 +    & ifmt_sub_1_d_indirect_1_s1_indirect_with_index_1, { 0x54008300 }
45348 +  },
45349 +/* or.1 (${d-An})${d-i4-1}++,(${s1-An},${s1-r}),${s2} */
45350 +  {
45351 +    { 0, 0, 0, 0 },
45352 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
45353 +    & ifmt_sub_1_d_indirect_with_post_increment_1_s1_indirect_with_index_1, { 0x52008300 }
45354 +  },
45355 +/* or.1 ${d-i4-1}(${d-An})++,(${s1-An},${s1-r}),${s2} */
45356 +  {
45357 +    { 0, 0, 0, 0 },
45358 +    { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
45359 +    & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_indirect_with_index_1, { 0x52108300 }
45360 +  },
45361 +/* or.1 ${d-direct-addr},${s1-imm7-1}(${s1-An}),${s2} */
45362 +  {
45363 +    { 0, 0, 0, 0 },
45364 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
45365 +    & ifmt_sub_1_d_direct_s1_indirect_with_offset_1, { 0x51008400 }
45366 +  },
45367 +/* or.1 #${d-imm8},${s1-imm7-1}(${s1-An}),${s2} */
45368 +  {
45369 +    { 0, 0, 0, 0 },
45370 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
45371 +    & ifmt_sub_1_d_immediate_1_s1_indirect_with_offset_1, { 0x50008400 }
45372 +  },
45373 +/* or.1 (${d-An},${d-r}),${s1-imm7-1}(${s1-An}),${s2} */
45374 +  {
45375 +    { 0, 0, 0, 0 },
45376 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
45377 +    & ifmt_sub_1_d_indirect_with_index_1_s1_indirect_with_offset_1, { 0x53008400 }
45378 +  },
45379 +/* or.1 ${d-imm7-1}(${d-An}),${s1-imm7-1}(${s1-An}),${s2} */
45380 +  {
45381 +    { 0, 0, 0, 0 },
45382 +    { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
45383 +    & ifmt_sub_1_d_indirect_with_offset_1_s1_indirect_with_offset_1, { 0x54008400 }
45384 +  },
45385 +/* or.1 (${d-An}),${s1-imm7-1}(${s1-An}),${s2} */
45386 +  {
45387 +    { 0, 0, 0, 0 },
45388 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
45389 +    & ifmt_sub_1_d_indirect_1_s1_indirect_with_offset_1, { 0x54008400 }
45390 +  },
45391 +/* or.1 (${d-An})${d-i4-1}++,${s1-imm7-1}(${s1-An}),${s2} */
45392 +  {
45393 +    { 0, 0, 0, 0 },
45394 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
45395 +    & ifmt_sub_1_d_indirect_with_post_increment_1_s1_indirect_with_offset_1, { 0x52008400 }
45396 +  },
45397 +/* or.1 ${d-i4-1}(${d-An})++,${s1-imm7-1}(${s1-An}),${s2} */
45398 +  {
45399 +    { 0, 0, 0, 0 },
45400 +    { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
45401 +    & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_indirect_with_offset_1, { 0x52108400 }
45402 +  },
45403 +/* or.1 ${d-direct-addr},(${s1-An}),${s2} */
45404 +  {
45405 +    { 0, 0, 0, 0 },
45406 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
45407 +    & ifmt_sub_1_d_direct_s1_indirect_1, { 0x51008400 }
45408 +  },
45409 +/* or.1 #${d-imm8},(${s1-An}),${s2} */
45410 +  {
45411 +    { 0, 0, 0, 0 },
45412 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
45413 +    & ifmt_sub_1_d_immediate_1_s1_indirect_1, { 0x50008400 }
45414 +  },
45415 +/* or.1 (${d-An},${d-r}),(${s1-An}),${s2} */
45416 +  {
45417 +    { 0, 0, 0, 0 },
45418 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
45419 +    & ifmt_sub_1_d_indirect_with_index_1_s1_indirect_1, { 0x53008400 }
45420 +  },
45421 +/* or.1 ${d-imm7-1}(${d-An}),(${s1-An}),${s2} */
45422 +  {
45423 +    { 0, 0, 0, 0 },
45424 +    { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
45425 +    & ifmt_sub_1_d_indirect_with_offset_1_s1_indirect_1, { 0x54008400 }
45426 +  },
45427 +/* or.1 (${d-An}),(${s1-An}),${s2} */
45428 +  {
45429 +    { 0, 0, 0, 0 },
45430 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
45431 +    & ifmt_sub_1_d_indirect_1_s1_indirect_1, { 0x54008400 }
45432 +  },
45433 +/* or.1 (${d-An})${d-i4-1}++,(${s1-An}),${s2} */
45434 +  {
45435 +    { 0, 0, 0, 0 },
45436 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
45437 +    & ifmt_sub_1_d_indirect_with_post_increment_1_s1_indirect_1, { 0x52008400 }
45438 +  },
45439 +/* or.1 ${d-i4-1}(${d-An})++,(${s1-An}),${s2} */
45440 +  {
45441 +    { 0, 0, 0, 0 },
45442 +    { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
45443 +    & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_indirect_1, { 0x52108400 }
45444 +  },
45445 +/* or.1 ${d-direct-addr},(${s1-An})${s1-i4-1}++,${s2} */
45446 +  {
45447 +    { 0, 0, 0, 0 },
45448 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } },
45449 +    & ifmt_sub_1_d_direct_s1_indirect_with_post_increment_1, { 0x51008200 }
45450 +  },
45451 +/* or.1 #${d-imm8},(${s1-An})${s1-i4-1}++,${s2} */
45452 +  {
45453 +    { 0, 0, 0, 0 },
45454 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } },
45455 +    & ifmt_sub_1_d_immediate_1_s1_indirect_with_post_increment_1, { 0x50008200 }
45456 +  },
45457 +/* or.1 (${d-An},${d-r}),(${s1-An})${s1-i4-1}++,${s2} */
45458 +  {
45459 +    { 0, 0, 0, 0 },
45460 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } },
45461 +    & ifmt_sub_1_d_indirect_with_index_1_s1_indirect_with_post_increment_1, { 0x53008200 }
45462 +  },
45463 +/* or.1 ${d-imm7-1}(${d-An}),(${s1-An})${s1-i4-1}++,${s2} */
45464 +  {
45465 +    { 0, 0, 0, 0 },
45466 +    { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } },
45467 +    & ifmt_sub_1_d_indirect_with_offset_1_s1_indirect_with_post_increment_1, { 0x54008200 }
45468 +  },
45469 +/* or.1 (${d-An}),(${s1-An})${s1-i4-1}++,${s2} */
45470 +  {
45471 +    { 0, 0, 0, 0 },
45472 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } },
45473 +    & ifmt_sub_1_d_indirect_1_s1_indirect_with_post_increment_1, { 0x54008200 }
45474 +  },
45475 +/* or.1 (${d-An})${d-i4-1}++,(${s1-An})${s1-i4-1}++,${s2} */
45476 +  {
45477 +    { 0, 0, 0, 0 },
45478 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } },
45479 +    & ifmt_sub_1_d_indirect_with_post_increment_1_s1_indirect_with_post_increment_1, { 0x52008200 }
45480 +  },
45481 +/* or.1 ${d-i4-1}(${d-An})++,(${s1-An})${s1-i4-1}++,${s2} */
45482 +  {
45483 +    { 0, 0, 0, 0 },
45484 +    { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } },
45485 +    & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_indirect_with_post_increment_1, { 0x52108200 }
45486 +  },
45487 +/* or.1 ${d-direct-addr},${s1-i4-1}(${s1-An})++,${s2} */
45488 +  {
45489 +    { 0, 0, 0, 0 },
45490 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
45491 +    & ifmt_sub_1_d_direct_s1_indirect_with_pre_increment_1, { 0x51008210 }
45492 +  },
45493 +/* or.1 #${d-imm8},${s1-i4-1}(${s1-An})++,${s2} */
45494 +  {
45495 +    { 0, 0, 0, 0 },
45496 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
45497 +    & ifmt_sub_1_d_immediate_1_s1_indirect_with_pre_increment_1, { 0x50008210 }
45498 +  },
45499 +/* or.1 (${d-An},${d-r}),${s1-i4-1}(${s1-An})++,${s2} */
45500 +  {
45501 +    { 0, 0, 0, 0 },
45502 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
45503 +    & ifmt_sub_1_d_indirect_with_index_1_s1_indirect_with_pre_increment_1, { 0x53008210 }
45504 +  },
45505 +/* or.1 ${d-imm7-1}(${d-An}),${s1-i4-1}(${s1-An})++,${s2} */
45506 +  {
45507 +    { 0, 0, 0, 0 },
45508 +    { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
45509 +    & ifmt_sub_1_d_indirect_with_offset_1_s1_indirect_with_pre_increment_1, { 0x54008210 }
45510 +  },
45511 +/* or.1 (${d-An}),${s1-i4-1}(${s1-An})++,${s2} */
45512 +  {
45513 +    { 0, 0, 0, 0 },
45514 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
45515 +    & ifmt_sub_1_d_indirect_1_s1_indirect_with_pre_increment_1, { 0x54008210 }
45516 +  },
45517 +/* or.1 (${d-An})${d-i4-1}++,${s1-i4-1}(${s1-An})++,${s2} */
45518 +  {
45519 +    { 0, 0, 0, 0 },
45520 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
45521 +    & ifmt_sub_1_d_indirect_with_post_increment_1_s1_indirect_with_pre_increment_1, { 0x52008210 }
45522 +  },
45523 +/* or.1 ${d-i4-1}(${d-An})++,${s1-i4-1}(${s1-An})++,${s2} */
45524 +  {
45525 +    { 0, 0, 0, 0 },
45526 +    { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
45527 +    & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_indirect_with_pre_increment_1, { 0x52108210 }
45528 +  },
45529 +/* and.1 ${d-direct-addr},${s1-direct-addr},${s2} */
45530 +  {
45531 +    { 0, 0, 0, 0 },
45532 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
45533 +    & ifmt_pxadds_u_d_direct_s1_direct, { 0x41008100 }
45534 +  },
45535 +/* and.1 #${d-imm8},${s1-direct-addr},${s2} */
45536 +  {
45537 +    { 0, 0, 0, 0 },
45538 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
45539 +    & ifmt_sub_1_d_immediate_1_s1_direct, { 0x40008100 }
45540 +  },
45541 +/* and.1 (${d-An},${d-r}),${s1-direct-addr},${s2} */
45542 +  {
45543 +    { 0, 0, 0, 0 },
45544 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
45545 +    & ifmt_sub_1_d_indirect_with_index_1_s1_direct, { 0x43008100 }
45546 +  },
45547 +/* and.1 ${d-imm7-1}(${d-An}),${s1-direct-addr},${s2} */
45548 +  {
45549 +    { 0, 0, 0, 0 },
45550 +    { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
45551 +    & ifmt_sub_1_d_indirect_with_offset_1_s1_direct, { 0x44008100 }
45552 +  },
45553 +/* and.1 (${d-An}),${s1-direct-addr},${s2} */
45554 +  {
45555 +    { 0, 0, 0, 0 },
45556 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
45557 +    & ifmt_sub_1_d_indirect_1_s1_direct, { 0x44008100 }
45558 +  },
45559 +/* and.1 (${d-An})${d-i4-1}++,${s1-direct-addr},${s2} */
45560 +  {
45561 +    { 0, 0, 0, 0 },
45562 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
45563 +    & ifmt_sub_1_d_indirect_with_post_increment_1_s1_direct, { 0x42008100 }
45564 +  },
45565 +/* and.1 ${d-i4-1}(${d-An})++,${s1-direct-addr},${s2} */
45566 +  {
45567 +    { 0, 0, 0, 0 },
45568 +    { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
45569 +    & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_direct, { 0x42108100 }
45570 +  },
45571 +/* and.1 ${d-direct-addr},#${s1-imm8},${s2} */
45572 +  {
45573 +    { 0, 0, 0, 0 },
45574 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
45575 +    & ifmt_pxadds_u_d_direct_s1_immediate, { 0x41008000 }
45576 +  },
45577 +/* and.1 #${d-imm8},#${s1-imm8},${s2} */
45578 +  {
45579 +    { 0, 0, 0, 0 },
45580 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
45581 +    & ifmt_sub_1_d_immediate_1_s1_immediate, { 0x40008000 }
45582 +  },
45583 +/* and.1 (${d-An},${d-r}),#${s1-imm8},${s2} */
45584 +  {
45585 +    { 0, 0, 0, 0 },
45586 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
45587 +    & ifmt_sub_1_d_indirect_with_index_1_s1_immediate, { 0x43008000 }
45588 +  },
45589 +/* and.1 ${d-imm7-1}(${d-An}),#${s1-imm8},${s2} */
45590 +  {
45591 +    { 0, 0, 0, 0 },
45592 +    { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
45593 +    & ifmt_sub_1_d_indirect_with_offset_1_s1_immediate, { 0x44008000 }
45594 +  },
45595 +/* and.1 (${d-An}),#${s1-imm8},${s2} */
45596 +  {
45597 +    { 0, 0, 0, 0 },
45598 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
45599 +    & ifmt_sub_1_d_indirect_1_s1_immediate, { 0x44008000 }
45600 +  },
45601 +/* and.1 (${d-An})${d-i4-1}++,#${s1-imm8},${s2} */
45602 +  {
45603 +    { 0, 0, 0, 0 },
45604 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
45605 +    & ifmt_sub_1_d_indirect_with_post_increment_1_s1_immediate, { 0x42008000 }
45606 +  },
45607 +/* and.1 ${d-i4-1}(${d-An})++,#${s1-imm8},${s2} */
45608 +  {
45609 +    { 0, 0, 0, 0 },
45610 +    { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
45611 +    & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_immediate, { 0x42108000 }
45612 +  },
45613 +/* and.1 ${d-direct-addr},(${s1-An},${s1-r}),${s2} */
45614 +  {
45615 +    { 0, 0, 0, 0 },
45616 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
45617 +    & ifmt_sub_1_d_direct_s1_indirect_with_index_1, { 0x41008300 }
45618 +  },
45619 +/* and.1 #${d-imm8},(${s1-An},${s1-r}),${s2} */
45620 +  {
45621 +    { 0, 0, 0, 0 },
45622 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
45623 +    & ifmt_sub_1_d_immediate_1_s1_indirect_with_index_1, { 0x40008300 }
45624 +  },
45625 +/* and.1 (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */
45626 +  {
45627 +    { 0, 0, 0, 0 },
45628 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
45629 +    & ifmt_sub_1_d_indirect_with_index_1_s1_indirect_with_index_1, { 0x43008300 }
45630 +  },
45631 +/* and.1 ${d-imm7-1}(${d-An}),(${s1-An},${s1-r}),${s2} */
45632 +  {
45633 +    { 0, 0, 0, 0 },
45634 +    { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
45635 +    & ifmt_sub_1_d_indirect_with_offset_1_s1_indirect_with_index_1, { 0x44008300 }
45636 +  },
45637 +/* and.1 (${d-An}),(${s1-An},${s1-r}),${s2} */
45638 +  {
45639 +    { 0, 0, 0, 0 },
45640 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
45641 +    & ifmt_sub_1_d_indirect_1_s1_indirect_with_index_1, { 0x44008300 }
45642 +  },
45643 +/* and.1 (${d-An})${d-i4-1}++,(${s1-An},${s1-r}),${s2} */
45644 +  {
45645 +    { 0, 0, 0, 0 },
45646 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
45647 +    & ifmt_sub_1_d_indirect_with_post_increment_1_s1_indirect_with_index_1, { 0x42008300 }
45648 +  },
45649 +/* and.1 ${d-i4-1}(${d-An})++,(${s1-An},${s1-r}),${s2} */
45650 +  {
45651 +    { 0, 0, 0, 0 },
45652 +    { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
45653 +    & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_indirect_with_index_1, { 0x42108300 }
45654 +  },
45655 +/* and.1 ${d-direct-addr},${s1-imm7-1}(${s1-An}),${s2} */
45656 +  {
45657 +    { 0, 0, 0, 0 },
45658 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
45659 +    & ifmt_sub_1_d_direct_s1_indirect_with_offset_1, { 0x41008400 }
45660 +  },
45661 +/* and.1 #${d-imm8},${s1-imm7-1}(${s1-An}),${s2} */
45662 +  {
45663 +    { 0, 0, 0, 0 },
45664 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
45665 +    & ifmt_sub_1_d_immediate_1_s1_indirect_with_offset_1, { 0x40008400 }
45666 +  },
45667 +/* and.1 (${d-An},${d-r}),${s1-imm7-1}(${s1-An}),${s2} */
45668 +  {
45669 +    { 0, 0, 0, 0 },
45670 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
45671 +    & ifmt_sub_1_d_indirect_with_index_1_s1_indirect_with_offset_1, { 0x43008400 }
45672 +  },
45673 +/* and.1 ${d-imm7-1}(${d-An}),${s1-imm7-1}(${s1-An}),${s2} */
45674 +  {
45675 +    { 0, 0, 0, 0 },
45676 +    { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
45677 +    & ifmt_sub_1_d_indirect_with_offset_1_s1_indirect_with_offset_1, { 0x44008400 }
45678 +  },
45679 +/* and.1 (${d-An}),${s1-imm7-1}(${s1-An}),${s2} */
45680 +  {
45681 +    { 0, 0, 0, 0 },
45682 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
45683 +    & ifmt_sub_1_d_indirect_1_s1_indirect_with_offset_1, { 0x44008400 }
45684 +  },
45685 +/* and.1 (${d-An})${d-i4-1}++,${s1-imm7-1}(${s1-An}),${s2} */
45686 +  {
45687 +    { 0, 0, 0, 0 },
45688 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
45689 +    & ifmt_sub_1_d_indirect_with_post_increment_1_s1_indirect_with_offset_1, { 0x42008400 }
45690 +  },
45691 +/* and.1 ${d-i4-1}(${d-An})++,${s1-imm7-1}(${s1-An}),${s2} */
45692 +  {
45693 +    { 0, 0, 0, 0 },
45694 +    { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_1), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
45695 +    & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_indirect_with_offset_1, { 0x42108400 }
45696 +  },
45697 +/* and.1 ${d-direct-addr},(${s1-An}),${s2} */
45698 +  {
45699 +    { 0, 0, 0, 0 },
45700 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
45701 +    & ifmt_sub_1_d_direct_s1_indirect_1, { 0x41008400 }
45702 +  },
45703 +/* and.1 #${d-imm8},(${s1-An}),${s2} */
45704 +  {
45705 +    { 0, 0, 0, 0 },
45706 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
45707 +    & ifmt_sub_1_d_immediate_1_s1_indirect_1, { 0x40008400 }
45708 +  },
45709 +/* and.1 (${d-An},${d-r}),(${s1-An}),${s2} */
45710 +  {
45711 +    { 0, 0, 0, 0 },
45712 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
45713 +    & ifmt_sub_1_d_indirect_with_index_1_s1_indirect_1, { 0x43008400 }
45714 +  },
45715 +/* and.1 ${d-imm7-1}(${d-An}),(${s1-An}),${s2} */
45716 +  {
45717 +    { 0, 0, 0, 0 },
45718 +    { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
45719 +    & ifmt_sub_1_d_indirect_with_offset_1_s1_indirect_1, { 0x44008400 }
45720 +  },
45721 +/* and.1 (${d-An}),(${s1-An}),${s2} */
45722 +  {
45723 +    { 0, 0, 0, 0 },
45724 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
45725 +    & ifmt_sub_1_d_indirect_1_s1_indirect_1, { 0x44008400 }
45726 +  },
45727 +/* and.1 (${d-An})${d-i4-1}++,(${s1-An}),${s2} */
45728 +  {
45729 +    { 0, 0, 0, 0 },
45730 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
45731 +    & ifmt_sub_1_d_indirect_with_post_increment_1_s1_indirect_1, { 0x42008400 }
45732 +  },
45733 +/* and.1 ${d-i4-1}(${d-An})++,(${s1-An}),${s2} */
45734 +  {
45735 +    { 0, 0, 0, 0 },
45736 +    { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
45737 +    & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_indirect_1, { 0x42108400 }
45738 +  },
45739 +/* and.1 ${d-direct-addr},(${s1-An})${s1-i4-1}++,${s2} */
45740 +  {
45741 +    { 0, 0, 0, 0 },
45742 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } },
45743 +    & ifmt_sub_1_d_direct_s1_indirect_with_post_increment_1, { 0x41008200 }
45744 +  },
45745 +/* and.1 #${d-imm8},(${s1-An})${s1-i4-1}++,${s2} */
45746 +  {
45747 +    { 0, 0, 0, 0 },
45748 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } },
45749 +    & ifmt_sub_1_d_immediate_1_s1_indirect_with_post_increment_1, { 0x40008200 }
45750 +  },
45751 +/* and.1 (${d-An},${d-r}),(${s1-An})${s1-i4-1}++,${s2} */
45752 +  {
45753 +    { 0, 0, 0, 0 },
45754 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } },
45755 +    & ifmt_sub_1_d_indirect_with_index_1_s1_indirect_with_post_increment_1, { 0x43008200 }
45756 +  },
45757 +/* and.1 ${d-imm7-1}(${d-An}),(${s1-An})${s1-i4-1}++,${s2} */
45758 +  {
45759 +    { 0, 0, 0, 0 },
45760 +    { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } },
45761 +    & ifmt_sub_1_d_indirect_with_offset_1_s1_indirect_with_post_increment_1, { 0x44008200 }
45762 +  },
45763 +/* and.1 (${d-An}),(${s1-An})${s1-i4-1}++,${s2} */
45764 +  {
45765 +    { 0, 0, 0, 0 },
45766 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } },
45767 +    & ifmt_sub_1_d_indirect_1_s1_indirect_with_post_increment_1, { 0x44008200 }
45768 +  },
45769 +/* and.1 (${d-An})${d-i4-1}++,(${s1-An})${s1-i4-1}++,${s2} */
45770 +  {
45771 +    { 0, 0, 0, 0 },
45772 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } },
45773 +    & ifmt_sub_1_d_indirect_with_post_increment_1_s1_indirect_with_post_increment_1, { 0x42008200 }
45774 +  },
45775 +/* and.1 ${d-i4-1}(${d-An})++,(${s1-An})${s1-i4-1}++,${s2} */
45776 +  {
45777 +    { 0, 0, 0, 0 },
45778 +    { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_1), '+', '+', ',', OP (S2), 0 } },
45779 +    & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_indirect_with_post_increment_1, { 0x42108200 }
45780 +  },
45781 +/* and.1 ${d-direct-addr},${s1-i4-1}(${s1-An})++,${s2} */
45782 +  {
45783 +    { 0, 0, 0, 0 },
45784 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
45785 +    & ifmt_sub_1_d_direct_s1_indirect_with_pre_increment_1, { 0x41008210 }
45786 +  },
45787 +/* and.1 #${d-imm8},${s1-i4-1}(${s1-An})++,${s2} */
45788 +  {
45789 +    { 0, 0, 0, 0 },
45790 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
45791 +    & ifmt_sub_1_d_immediate_1_s1_indirect_with_pre_increment_1, { 0x40008210 }
45792 +  },
45793 +/* and.1 (${d-An},${d-r}),${s1-i4-1}(${s1-An})++,${s2} */
45794 +  {
45795 +    { 0, 0, 0, 0 },
45796 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
45797 +    & ifmt_sub_1_d_indirect_with_index_1_s1_indirect_with_pre_increment_1, { 0x43008210 }
45798 +  },
45799 +/* and.1 ${d-imm7-1}(${d-An}),${s1-i4-1}(${s1-An})++,${s2} */
45800 +  {
45801 +    { 0, 0, 0, 0 },
45802 +    { { MNEM, ' ', OP (D_IMM7_1), '(', OP (D_AN), ')', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
45803 +    & ifmt_sub_1_d_indirect_with_offset_1_s1_indirect_with_pre_increment_1, { 0x44008210 }
45804 +  },
45805 +/* and.1 (${d-An}),${s1-i4-1}(${s1-An})++,${s2} */
45806 +  {
45807 +    { 0, 0, 0, 0 },
45808 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
45809 +    & ifmt_sub_1_d_indirect_1_s1_indirect_with_pre_increment_1, { 0x44008210 }
45810 +  },
45811 +/* and.1 (${d-An})${d-i4-1}++,${s1-i4-1}(${s1-An})++,${s2} */
45812 +  {
45813 +    { 0, 0, 0, 0 },
45814 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_1), '+', '+', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
45815 +    & ifmt_sub_1_d_indirect_with_post_increment_1_s1_indirect_with_pre_increment_1, { 0x42008210 }
45816 +  },
45817 +/* and.1 ${d-i4-1}(${d-An})++,${s1-i4-1}(${s1-An})++,${s2} */
45818 +  {
45819 +    { 0, 0, 0, 0 },
45820 +    { { MNEM, ' ', OP (D_I4_1), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_1), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
45821 +    & ifmt_sub_1_d_indirect_with_pre_increment_1_s1_indirect_with_pre_increment_1, { 0x42108210 }
45822 +  },
45823 +/* xor.4 ${d-direct-addr},${s1-direct-addr},${s2} */
45824 +  {
45825 +    { 0, 0, 0, 0 },
45826 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
45827 +    & ifmt_pxadds_u_d_direct_s1_direct, { 0x69000100 }
45828 +  },
45829 +/* xor.4 #${d-imm8},${s1-direct-addr},${s2} */
45830 +  {
45831 +    { 0, 0, 0, 0 },
45832 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
45833 +    & ifmt_pxvi_s_d_immediate_4_s1_direct, { 0x68000100 }
45834 +  },
45835 +/* xor.4 (${d-An},${d-r}),${s1-direct-addr},${s2} */
45836 +  {
45837 +    { 0, 0, 0, 0 },
45838 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
45839 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_direct, { 0x6b000100 }
45840 +  },
45841 +/* xor.4 ${d-imm7-4}(${d-An}),${s1-direct-addr},${s2} */
45842 +  {
45843 +    { 0, 0, 0, 0 },
45844 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
45845 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_direct, { 0x6c000100 }
45846 +  },
45847 +/* xor.4 (${d-An}),${s1-direct-addr},${s2} */
45848 +  {
45849 +    { 0, 0, 0, 0 },
45850 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
45851 +    & ifmt_pxvi_s_d_indirect_4_s1_direct, { 0x6c000100 }
45852 +  },
45853 +/* xor.4 (${d-An})${d-i4-4}++,${s1-direct-addr},${s2} */
45854 +  {
45855 +    { 0, 0, 0, 0 },
45856 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
45857 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_direct, { 0x6a000100 }
45858 +  },
45859 +/* xor.4 ${d-i4-4}(${d-An})++,${s1-direct-addr},${s2} */
45860 +  {
45861 +    { 0, 0, 0, 0 },
45862 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
45863 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_direct, { 0x6a100100 }
45864 +  },
45865 +/* xor.4 ${d-direct-addr},#${s1-imm8},${s2} */
45866 +  {
45867 +    { 0, 0, 0, 0 },
45868 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
45869 +    & ifmt_pxadds_u_d_direct_s1_immediate, { 0x69000000 }
45870 +  },
45871 +/* xor.4 #${d-imm8},#${s1-imm8},${s2} */
45872 +  {
45873 +    { 0, 0, 0, 0 },
45874 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
45875 +    & ifmt_pxvi_s_d_immediate_4_s1_immediate, { 0x68000000 }
45876 +  },
45877 +/* xor.4 (${d-An},${d-r}),#${s1-imm8},${s2} */
45878 +  {
45879 +    { 0, 0, 0, 0 },
45880 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
45881 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_immediate, { 0x6b000000 }
45882 +  },
45883 +/* xor.4 ${d-imm7-4}(${d-An}),#${s1-imm8},${s2} */
45884 +  {
45885 +    { 0, 0, 0, 0 },
45886 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
45887 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_immediate, { 0x6c000000 }
45888 +  },
45889 +/* xor.4 (${d-An}),#${s1-imm8},${s2} */
45890 +  {
45891 +    { 0, 0, 0, 0 },
45892 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
45893 +    & ifmt_pxvi_s_d_indirect_4_s1_immediate, { 0x6c000000 }
45894 +  },
45895 +/* xor.4 (${d-An})${d-i4-4}++,#${s1-imm8},${s2} */
45896 +  {
45897 +    { 0, 0, 0, 0 },
45898 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
45899 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_immediate, { 0x6a000000 }
45900 +  },
45901 +/* xor.4 ${d-i4-4}(${d-An})++,#${s1-imm8},${s2} */
45902 +  {
45903 +    { 0, 0, 0, 0 },
45904 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
45905 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_immediate, { 0x6a100000 }
45906 +  },
45907 +/* xor.4 ${d-direct-addr},(${s1-An},${s1-r}),${s2} */
45908 +  {
45909 +    { 0, 0, 0, 0 },
45910 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
45911 +    & ifmt_pxadds_u_d_direct_s1_indirect_with_index_4, { 0x69000300 }
45912 +  },
45913 +/* xor.4 #${d-imm8},(${s1-An},${s1-r}),${s2} */
45914 +  {
45915 +    { 0, 0, 0, 0 },
45916 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
45917 +    & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_index_4, { 0x68000300 }
45918 +  },
45919 +/* xor.4 (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */
45920 +  {
45921 +    { 0, 0, 0, 0 },
45922 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
45923 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_index_4, { 0x6b000300 }
45924 +  },
45925 +/* xor.4 ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}),${s2} */
45926 +  {
45927 +    { 0, 0, 0, 0 },
45928 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
45929 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_index_4, { 0x6c000300 }
45930 +  },
45931 +/* xor.4 (${d-An}),(${s1-An},${s1-r}),${s2} */
45932 +  {
45933 +    { 0, 0, 0, 0 },
45934 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
45935 +    & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_index_4, { 0x6c000300 }
45936 +  },
45937 +/* xor.4 (${d-An})${d-i4-4}++,(${s1-An},${s1-r}),${s2} */
45938 +  {
45939 +    { 0, 0, 0, 0 },
45940 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
45941 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_index_4, { 0x6a000300 }
45942 +  },
45943 +/* xor.4 ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}),${s2} */
45944 +  {
45945 +    { 0, 0, 0, 0 },
45946 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
45947 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_index_4, { 0x6a100300 }
45948 +  },
45949 +/* xor.4 ${d-direct-addr},${s1-imm7-4}(${s1-An}),${s2} */
45950 +  {
45951 +    { 0, 0, 0, 0 },
45952 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
45953 +    & ifmt_pxadds_u_d_direct_s1_indirect_with_offset_4, { 0x69000400 }
45954 +  },
45955 +/* xor.4 #${d-imm8},${s1-imm7-4}(${s1-An}),${s2} */
45956 +  {
45957 +    { 0, 0, 0, 0 },
45958 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
45959 +    & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_offset_4, { 0x68000400 }
45960 +  },
45961 +/* xor.4 (${d-An},${d-r}),${s1-imm7-4}(${s1-An}),${s2} */
45962 +  {
45963 +    { 0, 0, 0, 0 },
45964 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
45965 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_offset_4, { 0x6b000400 }
45966 +  },
45967 +/* xor.4 ${d-imm7-4}(${d-An}),${s1-imm7-4}(${s1-An}),${s2} */
45968 +  {
45969 +    { 0, 0, 0, 0 },
45970 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
45971 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_offset_4, { 0x6c000400 }
45972 +  },
45973 +/* xor.4 (${d-An}),${s1-imm7-4}(${s1-An}),${s2} */
45974 +  {
45975 +    { 0, 0, 0, 0 },
45976 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
45977 +    & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_offset_4, { 0x6c000400 }
45978 +  },
45979 +/* xor.4 (${d-An})${d-i4-4}++,${s1-imm7-4}(${s1-An}),${s2} */
45980 +  {
45981 +    { 0, 0, 0, 0 },
45982 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
45983 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_offset_4, { 0x6a000400 }
45984 +  },
45985 +/* xor.4 ${d-i4-4}(${d-An})++,${s1-imm7-4}(${s1-An}),${s2} */
45986 +  {
45987 +    { 0, 0, 0, 0 },
45988 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
45989 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_offset_4, { 0x6a100400 }
45990 +  },
45991 +/* xor.4 ${d-direct-addr},(${s1-An}),${s2} */
45992 +  {
45993 +    { 0, 0, 0, 0 },
45994 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
45995 +    & ifmt_pxadds_u_d_direct_s1_indirect_4, { 0x69000400 }
45996 +  },
45997 +/* xor.4 #${d-imm8},(${s1-An}),${s2} */
45998 +  {
45999 +    { 0, 0, 0, 0 },
46000 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
46001 +    & ifmt_pxvi_s_d_immediate_4_s1_indirect_4, { 0x68000400 }
46002 +  },
46003 +/* xor.4 (${d-An},${d-r}),(${s1-An}),${s2} */
46004 +  {
46005 +    { 0, 0, 0, 0 },
46006 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
46007 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_4, { 0x6b000400 }
46008 +  },
46009 +/* xor.4 ${d-imm7-4}(${d-An}),(${s1-An}),${s2} */
46010 +  {
46011 +    { 0, 0, 0, 0 },
46012 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
46013 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_4, { 0x6c000400 }
46014 +  },
46015 +/* xor.4 (${d-An}),(${s1-An}),${s2} */
46016 +  {
46017 +    { 0, 0, 0, 0 },
46018 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
46019 +    & ifmt_pxvi_s_d_indirect_4_s1_indirect_4, { 0x6c000400 }
46020 +  },
46021 +/* xor.4 (${d-An})${d-i4-4}++,(${s1-An}),${s2} */
46022 +  {
46023 +    { 0, 0, 0, 0 },
46024 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
46025 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_4, { 0x6a000400 }
46026 +  },
46027 +/* xor.4 ${d-i4-4}(${d-An})++,(${s1-An}),${s2} */
46028 +  {
46029 +    { 0, 0, 0, 0 },
46030 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
46031 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_4, { 0x6a100400 }
46032 +  },
46033 +/* xor.4 ${d-direct-addr},(${s1-An})${s1-i4-4}++,${s2} */
46034 +  {
46035 +    { 0, 0, 0, 0 },
46036 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
46037 +    & ifmt_pxadds_u_d_direct_s1_indirect_with_post_increment_4, { 0x69000200 }
46038 +  },
46039 +/* xor.4 #${d-imm8},(${s1-An})${s1-i4-4}++,${s2} */
46040 +  {
46041 +    { 0, 0, 0, 0 },
46042 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
46043 +    & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_post_increment_4, { 0x68000200 }
46044 +  },
46045 +/* xor.4 (${d-An},${d-r}),(${s1-An})${s1-i4-4}++,${s2} */
46046 +  {
46047 +    { 0, 0, 0, 0 },
46048 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
46049 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_post_increment_4, { 0x6b000200 }
46050 +  },
46051 +/* xor.4 ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-4}++,${s2} */
46052 +  {
46053 +    { 0, 0, 0, 0 },
46054 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
46055 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_post_increment_4, { 0x6c000200 }
46056 +  },
46057 +/* xor.4 (${d-An}),(${s1-An})${s1-i4-4}++,${s2} */
46058 +  {
46059 +    { 0, 0, 0, 0 },
46060 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
46061 +    & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_post_increment_4, { 0x6c000200 }
46062 +  },
46063 +/* xor.4 (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-4}++,${s2} */
46064 +  {
46065 +    { 0, 0, 0, 0 },
46066 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
46067 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_post_increment_4, { 0x6a000200 }
46068 +  },
46069 +/* xor.4 ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-4}++,${s2} */
46070 +  {
46071 +    { 0, 0, 0, 0 },
46072 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
46073 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_post_increment_4, { 0x6a100200 }
46074 +  },
46075 +/* xor.4 ${d-direct-addr},${s1-i4-4}(${s1-An})++,${s2} */
46076 +  {
46077 +    { 0, 0, 0, 0 },
46078 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
46079 +    & ifmt_pxadds_u_d_direct_s1_indirect_with_pre_increment_4, { 0x69000210 }
46080 +  },
46081 +/* xor.4 #${d-imm8},${s1-i4-4}(${s1-An})++,${s2} */
46082 +  {
46083 +    { 0, 0, 0, 0 },
46084 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
46085 +    & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_pre_increment_4, { 0x68000210 }
46086 +  },
46087 +/* xor.4 (${d-An},${d-r}),${s1-i4-4}(${s1-An})++,${s2} */
46088 +  {
46089 +    { 0, 0, 0, 0 },
46090 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
46091 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_pre_increment_4, { 0x6b000210 }
46092 +  },
46093 +/* xor.4 ${d-imm7-4}(${d-An}),${s1-i4-4}(${s1-An})++,${s2} */
46094 +  {
46095 +    { 0, 0, 0, 0 },
46096 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
46097 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_pre_increment_4, { 0x6c000210 }
46098 +  },
46099 +/* xor.4 (${d-An}),${s1-i4-4}(${s1-An})++,${s2} */
46100 +  {
46101 +    { 0, 0, 0, 0 },
46102 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
46103 +    & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_pre_increment_4, { 0x6c000210 }
46104 +  },
46105 +/* xor.4 (${d-An})${d-i4-4}++,${s1-i4-4}(${s1-An})++,${s2} */
46106 +  {
46107 +    { 0, 0, 0, 0 },
46108 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
46109 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_pre_increment_4, { 0x6a000210 }
46110 +  },
46111 +/* xor.4 ${d-i4-4}(${d-An})++,${s1-i4-4}(${s1-An})++,${s2} */
46112 +  {
46113 +    { 0, 0, 0, 0 },
46114 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
46115 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_pre_increment_4, { 0x6a100210 }
46116 +  },
46117 +/* xor.2 ${d-direct-addr},${s1-direct-addr},${s2} */
46118 +  {
46119 +    { 0, 0, 0, 0 },
46120 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
46121 +    & ifmt_pxadds_u_d_direct_s1_direct, { 0x61000100 }
46122 +  },
46123 +/* xor.2 #${d-imm8},${s1-direct-addr},${s2} */
46124 +  {
46125 +    { 0, 0, 0, 0 },
46126 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
46127 +    & ifmt_pxadds_u_d_immediate_2_s1_direct, { 0x60000100 }
46128 +  },
46129 +/* xor.2 (${d-An},${d-r}),${s1-direct-addr},${s2} */
46130 +  {
46131 +    { 0, 0, 0, 0 },
46132 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
46133 +    & ifmt_pxadds_u_d_indirect_with_index_2_s1_direct, { 0x63000100 }
46134 +  },
46135 +/* xor.2 ${d-imm7-2}(${d-An}),${s1-direct-addr},${s2} */
46136 +  {
46137 +    { 0, 0, 0, 0 },
46138 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
46139 +    & ifmt_pxadds_u_d_indirect_with_offset_2_s1_direct, { 0x64000100 }
46140 +  },
46141 +/* xor.2 (${d-An}),${s1-direct-addr},${s2} */
46142 +  {
46143 +    { 0, 0, 0, 0 },
46144 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
46145 +    & ifmt_pxadds_u_d_indirect_2_s1_direct, { 0x64000100 }
46146 +  },
46147 +/* xor.2 (${d-An})${d-i4-2}++,${s1-direct-addr},${s2} */
46148 +  {
46149 +    { 0, 0, 0, 0 },
46150 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
46151 +    & ifmt_pxadds_u_d_indirect_with_post_increment_2_s1_direct, { 0x62000100 }
46152 +  },
46153 +/* xor.2 ${d-i4-2}(${d-An})++,${s1-direct-addr},${s2} */
46154 +  {
46155 +    { 0, 0, 0, 0 },
46156 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
46157 +    & ifmt_pxadds_u_d_indirect_with_pre_increment_2_s1_direct, { 0x62100100 }
46158 +  },
46159 +/* xor.2 ${d-direct-addr},#${s1-imm8},${s2} */
46160 +  {
46161 +    { 0, 0, 0, 0 },
46162 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
46163 +    & ifmt_pxadds_u_d_direct_s1_immediate, { 0x61000000 }
46164 +  },
46165 +/* xor.2 #${d-imm8},#${s1-imm8},${s2} */
46166 +  {
46167 +    { 0, 0, 0, 0 },
46168 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
46169 +    & ifmt_pxadds_u_d_immediate_2_s1_immediate, { 0x60000000 }
46170 +  },
46171 +/* xor.2 (${d-An},${d-r}),#${s1-imm8},${s2} */
46172 +  {
46173 +    { 0, 0, 0, 0 },
46174 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
46175 +    & ifmt_pxadds_u_d_indirect_with_index_2_s1_immediate, { 0x63000000 }
46176 +  },
46177 +/* xor.2 ${d-imm7-2}(${d-An}),#${s1-imm8},${s2} */
46178 +  {
46179 +    { 0, 0, 0, 0 },
46180 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
46181 +    & ifmt_pxadds_u_d_indirect_with_offset_2_s1_immediate, { 0x64000000 }
46182 +  },
46183 +/* xor.2 (${d-An}),#${s1-imm8},${s2} */
46184 +  {
46185 +    { 0, 0, 0, 0 },
46186 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
46187 +    & ifmt_pxadds_u_d_indirect_2_s1_immediate, { 0x64000000 }
46188 +  },
46189 +/* xor.2 (${d-An})${d-i4-2}++,#${s1-imm8},${s2} */
46190 +  {
46191 +    { 0, 0, 0, 0 },
46192 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
46193 +    & ifmt_pxadds_u_d_indirect_with_post_increment_2_s1_immediate, { 0x62000000 }
46194 +  },
46195 +/* xor.2 ${d-i4-2}(${d-An})++,#${s1-imm8},${s2} */
46196 +  {
46197 +    { 0, 0, 0, 0 },
46198 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
46199 +    & ifmt_pxadds_u_d_indirect_with_pre_increment_2_s1_immediate, { 0x62100000 }
46200 +  },
46201 +/* xor.2 ${d-direct-addr},(${s1-An},${s1-r}),${s2} */
46202 +  {
46203 +    { 0, 0, 0, 0 },
46204 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
46205 +    & ifmt_sub_2_d_direct_s1_indirect_with_index_2, { 0x61000300 }
46206 +  },
46207 +/* xor.2 #${d-imm8},(${s1-An},${s1-r}),${s2} */
46208 +  {
46209 +    { 0, 0, 0, 0 },
46210 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
46211 +    & ifmt_sub_2_d_immediate_2_s1_indirect_with_index_2, { 0x60000300 }
46212 +  },
46213 +/* xor.2 (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */
46214 +  {
46215 +    { 0, 0, 0, 0 },
46216 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
46217 +    & ifmt_sub_2_d_indirect_with_index_2_s1_indirect_with_index_2, { 0x63000300 }
46218 +  },
46219 +/* xor.2 ${d-imm7-2}(${d-An}),(${s1-An},${s1-r}),${s2} */
46220 +  {
46221 +    { 0, 0, 0, 0 },
46222 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
46223 +    & ifmt_sub_2_d_indirect_with_offset_2_s1_indirect_with_index_2, { 0x64000300 }
46224 +  },
46225 +/* xor.2 (${d-An}),(${s1-An},${s1-r}),${s2} */
46226 +  {
46227 +    { 0, 0, 0, 0 },
46228 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
46229 +    & ifmt_sub_2_d_indirect_2_s1_indirect_with_index_2, { 0x64000300 }
46230 +  },
46231 +/* xor.2 (${d-An})${d-i4-2}++,(${s1-An},${s1-r}),${s2} */
46232 +  {
46233 +    { 0, 0, 0, 0 },
46234 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
46235 +    & ifmt_sub_2_d_indirect_with_post_increment_2_s1_indirect_with_index_2, { 0x62000300 }
46236 +  },
46237 +/* xor.2 ${d-i4-2}(${d-An})++,(${s1-An},${s1-r}),${s2} */
46238 +  {
46239 +    { 0, 0, 0, 0 },
46240 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
46241 +    & ifmt_sub_2_d_indirect_with_pre_increment_2_s1_indirect_with_index_2, { 0x62100300 }
46242 +  },
46243 +/* xor.2 ${d-direct-addr},${s1-imm7-2}(${s1-An}),${s2} */
46244 +  {
46245 +    { 0, 0, 0, 0 },
46246 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
46247 +    & ifmt_sub_2_d_direct_s1_indirect_with_offset_2, { 0x61000400 }
46248 +  },
46249 +/* xor.2 #${d-imm8},${s1-imm7-2}(${s1-An}),${s2} */
46250 +  {
46251 +    { 0, 0, 0, 0 },
46252 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
46253 +    & ifmt_sub_2_d_immediate_2_s1_indirect_with_offset_2, { 0x60000400 }
46254 +  },
46255 +/* xor.2 (${d-An},${d-r}),${s1-imm7-2}(${s1-An}),${s2} */
46256 +  {
46257 +    { 0, 0, 0, 0 },
46258 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
46259 +    & ifmt_sub_2_d_indirect_with_index_2_s1_indirect_with_offset_2, { 0x63000400 }
46260 +  },
46261 +/* xor.2 ${d-imm7-2}(${d-An}),${s1-imm7-2}(${s1-An}),${s2} */
46262 +  {
46263 +    { 0, 0, 0, 0 },
46264 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
46265 +    & ifmt_sub_2_d_indirect_with_offset_2_s1_indirect_with_offset_2, { 0x64000400 }
46266 +  },
46267 +/* xor.2 (${d-An}),${s1-imm7-2}(${s1-An}),${s2} */
46268 +  {
46269 +    { 0, 0, 0, 0 },
46270 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
46271 +    & ifmt_sub_2_d_indirect_2_s1_indirect_with_offset_2, { 0x64000400 }
46272 +  },
46273 +/* xor.2 (${d-An})${d-i4-2}++,${s1-imm7-2}(${s1-An}),${s2} */
46274 +  {
46275 +    { 0, 0, 0, 0 },
46276 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
46277 +    & ifmt_sub_2_d_indirect_with_post_increment_2_s1_indirect_with_offset_2, { 0x62000400 }
46278 +  },
46279 +/* xor.2 ${d-i4-2}(${d-An})++,${s1-imm7-2}(${s1-An}),${s2} */
46280 +  {
46281 +    { 0, 0, 0, 0 },
46282 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
46283 +    & ifmt_sub_2_d_indirect_with_pre_increment_2_s1_indirect_with_offset_2, { 0x62100400 }
46284 +  },
46285 +/* xor.2 ${d-direct-addr},(${s1-An}),${s2} */
46286 +  {
46287 +    { 0, 0, 0, 0 },
46288 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
46289 +    & ifmt_sub_2_d_direct_s1_indirect_2, { 0x61000400 }
46290 +  },
46291 +/* xor.2 #${d-imm8},(${s1-An}),${s2} */
46292 +  {
46293 +    { 0, 0, 0, 0 },
46294 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
46295 +    & ifmt_sub_2_d_immediate_2_s1_indirect_2, { 0x60000400 }
46296 +  },
46297 +/* xor.2 (${d-An},${d-r}),(${s1-An}),${s2} */
46298 +  {
46299 +    { 0, 0, 0, 0 },
46300 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
46301 +    & ifmt_sub_2_d_indirect_with_index_2_s1_indirect_2, { 0x63000400 }
46302 +  },
46303 +/* xor.2 ${d-imm7-2}(${d-An}),(${s1-An}),${s2} */
46304 +  {
46305 +    { 0, 0, 0, 0 },
46306 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
46307 +    & ifmt_sub_2_d_indirect_with_offset_2_s1_indirect_2, { 0x64000400 }
46308 +  },
46309 +/* xor.2 (${d-An}),(${s1-An}),${s2} */
46310 +  {
46311 +    { 0, 0, 0, 0 },
46312 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
46313 +    & ifmt_sub_2_d_indirect_2_s1_indirect_2, { 0x64000400 }
46314 +  },
46315 +/* xor.2 (${d-An})${d-i4-2}++,(${s1-An}),${s2} */
46316 +  {
46317 +    { 0, 0, 0, 0 },
46318 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
46319 +    & ifmt_sub_2_d_indirect_with_post_increment_2_s1_indirect_2, { 0x62000400 }
46320 +  },
46321 +/* xor.2 ${d-i4-2}(${d-An})++,(${s1-An}),${s2} */
46322 +  {
46323 +    { 0, 0, 0, 0 },
46324 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
46325 +    & ifmt_sub_2_d_indirect_with_pre_increment_2_s1_indirect_2, { 0x62100400 }
46326 +  },
46327 +/* xor.2 ${d-direct-addr},(${s1-An})${s1-i4-2}++,${s2} */
46328 +  {
46329 +    { 0, 0, 0, 0 },
46330 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } },
46331 +    & ifmt_sub_2_d_direct_s1_indirect_with_post_increment_2, { 0x61000200 }
46332 +  },
46333 +/* xor.2 #${d-imm8},(${s1-An})${s1-i4-2}++,${s2} */
46334 +  {
46335 +    { 0, 0, 0, 0 },
46336 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } },
46337 +    & ifmt_sub_2_d_immediate_2_s1_indirect_with_post_increment_2, { 0x60000200 }
46338 +  },
46339 +/* xor.2 (${d-An},${d-r}),(${s1-An})${s1-i4-2}++,${s2} */
46340 +  {
46341 +    { 0, 0, 0, 0 },
46342 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } },
46343 +    & ifmt_sub_2_d_indirect_with_index_2_s1_indirect_with_post_increment_2, { 0x63000200 }
46344 +  },
46345 +/* xor.2 ${d-imm7-2}(${d-An}),(${s1-An})${s1-i4-2}++,${s2} */
46346 +  {
46347 +    { 0, 0, 0, 0 },
46348 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } },
46349 +    & ifmt_sub_2_d_indirect_with_offset_2_s1_indirect_with_post_increment_2, { 0x64000200 }
46350 +  },
46351 +/* xor.2 (${d-An}),(${s1-An})${s1-i4-2}++,${s2} */
46352 +  {
46353 +    { 0, 0, 0, 0 },
46354 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } },
46355 +    & ifmt_sub_2_d_indirect_2_s1_indirect_with_post_increment_2, { 0x64000200 }
46356 +  },
46357 +/* xor.2 (${d-An})${d-i4-2}++,(${s1-An})${s1-i4-2}++,${s2} */
46358 +  {
46359 +    { 0, 0, 0, 0 },
46360 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } },
46361 +    & ifmt_sub_2_d_indirect_with_post_increment_2_s1_indirect_with_post_increment_2, { 0x62000200 }
46362 +  },
46363 +/* xor.2 ${d-i4-2}(${d-An})++,(${s1-An})${s1-i4-2}++,${s2} */
46364 +  {
46365 +    { 0, 0, 0, 0 },
46366 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } },
46367 +    & ifmt_sub_2_d_indirect_with_pre_increment_2_s1_indirect_with_post_increment_2, { 0x62100200 }
46368 +  },
46369 +/* xor.2 ${d-direct-addr},${s1-i4-2}(${s1-An})++,${s2} */
46370 +  {
46371 +    { 0, 0, 0, 0 },
46372 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
46373 +    & ifmt_sub_2_d_direct_s1_indirect_with_pre_increment_2, { 0x61000210 }
46374 +  },
46375 +/* xor.2 #${d-imm8},${s1-i4-2}(${s1-An})++,${s2} */
46376 +  {
46377 +    { 0, 0, 0, 0 },
46378 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
46379 +    & ifmt_sub_2_d_immediate_2_s1_indirect_with_pre_increment_2, { 0x60000210 }
46380 +  },
46381 +/* xor.2 (${d-An},${d-r}),${s1-i4-2}(${s1-An})++,${s2} */
46382 +  {
46383 +    { 0, 0, 0, 0 },
46384 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
46385 +    & ifmt_sub_2_d_indirect_with_index_2_s1_indirect_with_pre_increment_2, { 0x63000210 }
46386 +  },
46387 +/* xor.2 ${d-imm7-2}(${d-An}),${s1-i4-2}(${s1-An})++,${s2} */
46388 +  {
46389 +    { 0, 0, 0, 0 },
46390 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
46391 +    & ifmt_sub_2_d_indirect_with_offset_2_s1_indirect_with_pre_increment_2, { 0x64000210 }
46392 +  },
46393 +/* xor.2 (${d-An}),${s1-i4-2}(${s1-An})++,${s2} */
46394 +  {
46395 +    { 0, 0, 0, 0 },
46396 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
46397 +    & ifmt_sub_2_d_indirect_2_s1_indirect_with_pre_increment_2, { 0x64000210 }
46398 +  },
46399 +/* xor.2 (${d-An})${d-i4-2}++,${s1-i4-2}(${s1-An})++,${s2} */
46400 +  {
46401 +    { 0, 0, 0, 0 },
46402 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
46403 +    & ifmt_sub_2_d_indirect_with_post_increment_2_s1_indirect_with_pre_increment_2, { 0x62000210 }
46404 +  },
46405 +/* xor.2 ${d-i4-2}(${d-An})++,${s1-i4-2}(${s1-An})++,${s2} */
46406 +  {
46407 +    { 0, 0, 0, 0 },
46408 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
46409 +    & ifmt_sub_2_d_indirect_with_pre_increment_2_s1_indirect_with_pre_increment_2, { 0x62100210 }
46410 +  },
46411 +/* or.4 ${d-direct-addr},${s1-direct-addr},${s2} */
46412 +  {
46413 +    { 0, 0, 0, 0 },
46414 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
46415 +    & ifmt_pxadds_u_d_direct_s1_direct, { 0x59000100 }
46416 +  },
46417 +/* or.4 #${d-imm8},${s1-direct-addr},${s2} */
46418 +  {
46419 +    { 0, 0, 0, 0 },
46420 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
46421 +    & ifmt_pxvi_s_d_immediate_4_s1_direct, { 0x58000100 }
46422 +  },
46423 +/* or.4 (${d-An},${d-r}),${s1-direct-addr},${s2} */
46424 +  {
46425 +    { 0, 0, 0, 0 },
46426 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
46427 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_direct, { 0x5b000100 }
46428 +  },
46429 +/* or.4 ${d-imm7-4}(${d-An}),${s1-direct-addr},${s2} */
46430 +  {
46431 +    { 0, 0, 0, 0 },
46432 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
46433 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_direct, { 0x5c000100 }
46434 +  },
46435 +/* or.4 (${d-An}),${s1-direct-addr},${s2} */
46436 +  {
46437 +    { 0, 0, 0, 0 },
46438 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
46439 +    & ifmt_pxvi_s_d_indirect_4_s1_direct, { 0x5c000100 }
46440 +  },
46441 +/* or.4 (${d-An})${d-i4-4}++,${s1-direct-addr},${s2} */
46442 +  {
46443 +    { 0, 0, 0, 0 },
46444 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
46445 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_direct, { 0x5a000100 }
46446 +  },
46447 +/* or.4 ${d-i4-4}(${d-An})++,${s1-direct-addr},${s2} */
46448 +  {
46449 +    { 0, 0, 0, 0 },
46450 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
46451 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_direct, { 0x5a100100 }
46452 +  },
46453 +/* or.4 ${d-direct-addr},#${s1-imm8},${s2} */
46454 +  {
46455 +    { 0, 0, 0, 0 },
46456 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
46457 +    & ifmt_pxadds_u_d_direct_s1_immediate, { 0x59000000 }
46458 +  },
46459 +/* or.4 #${d-imm8},#${s1-imm8},${s2} */
46460 +  {
46461 +    { 0, 0, 0, 0 },
46462 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
46463 +    & ifmt_pxvi_s_d_immediate_4_s1_immediate, { 0x58000000 }
46464 +  },
46465 +/* or.4 (${d-An},${d-r}),#${s1-imm8},${s2} */
46466 +  {
46467 +    { 0, 0, 0, 0 },
46468 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
46469 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_immediate, { 0x5b000000 }
46470 +  },
46471 +/* or.4 ${d-imm7-4}(${d-An}),#${s1-imm8},${s2} */
46472 +  {
46473 +    { 0, 0, 0, 0 },
46474 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
46475 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_immediate, { 0x5c000000 }
46476 +  },
46477 +/* or.4 (${d-An}),#${s1-imm8},${s2} */
46478 +  {
46479 +    { 0, 0, 0, 0 },
46480 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
46481 +    & ifmt_pxvi_s_d_indirect_4_s1_immediate, { 0x5c000000 }
46482 +  },
46483 +/* or.4 (${d-An})${d-i4-4}++,#${s1-imm8},${s2} */
46484 +  {
46485 +    { 0, 0, 0, 0 },
46486 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
46487 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_immediate, { 0x5a000000 }
46488 +  },
46489 +/* or.4 ${d-i4-4}(${d-An})++,#${s1-imm8},${s2} */
46490 +  {
46491 +    { 0, 0, 0, 0 },
46492 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
46493 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_immediate, { 0x5a100000 }
46494 +  },
46495 +/* or.4 ${d-direct-addr},(${s1-An},${s1-r}),${s2} */
46496 +  {
46497 +    { 0, 0, 0, 0 },
46498 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
46499 +    & ifmt_pxadds_u_d_direct_s1_indirect_with_index_4, { 0x59000300 }
46500 +  },
46501 +/* or.4 #${d-imm8},(${s1-An},${s1-r}),${s2} */
46502 +  {
46503 +    { 0, 0, 0, 0 },
46504 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
46505 +    & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_index_4, { 0x58000300 }
46506 +  },
46507 +/* or.4 (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */
46508 +  {
46509 +    { 0, 0, 0, 0 },
46510 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
46511 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_index_4, { 0x5b000300 }
46512 +  },
46513 +/* or.4 ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}),${s2} */
46514 +  {
46515 +    { 0, 0, 0, 0 },
46516 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
46517 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_index_4, { 0x5c000300 }
46518 +  },
46519 +/* or.4 (${d-An}),(${s1-An},${s1-r}),${s2} */
46520 +  {
46521 +    { 0, 0, 0, 0 },
46522 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
46523 +    & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_index_4, { 0x5c000300 }
46524 +  },
46525 +/* or.4 (${d-An})${d-i4-4}++,(${s1-An},${s1-r}),${s2} */
46526 +  {
46527 +    { 0, 0, 0, 0 },
46528 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
46529 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_index_4, { 0x5a000300 }
46530 +  },
46531 +/* or.4 ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}),${s2} */
46532 +  {
46533 +    { 0, 0, 0, 0 },
46534 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
46535 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_index_4, { 0x5a100300 }
46536 +  },
46537 +/* or.4 ${d-direct-addr},${s1-imm7-4}(${s1-An}),${s2} */
46538 +  {
46539 +    { 0, 0, 0, 0 },
46540 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
46541 +    & ifmt_pxadds_u_d_direct_s1_indirect_with_offset_4, { 0x59000400 }
46542 +  },
46543 +/* or.4 #${d-imm8},${s1-imm7-4}(${s1-An}),${s2} */
46544 +  {
46545 +    { 0, 0, 0, 0 },
46546 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
46547 +    & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_offset_4, { 0x58000400 }
46548 +  },
46549 +/* or.4 (${d-An},${d-r}),${s1-imm7-4}(${s1-An}),${s2} */
46550 +  {
46551 +    { 0, 0, 0, 0 },
46552 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
46553 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_offset_4, { 0x5b000400 }
46554 +  },
46555 +/* or.4 ${d-imm7-4}(${d-An}),${s1-imm7-4}(${s1-An}),${s2} */
46556 +  {
46557 +    { 0, 0, 0, 0 },
46558 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
46559 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_offset_4, { 0x5c000400 }
46560 +  },
46561 +/* or.4 (${d-An}),${s1-imm7-4}(${s1-An}),${s2} */
46562 +  {
46563 +    { 0, 0, 0, 0 },
46564 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
46565 +    & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_offset_4, { 0x5c000400 }
46566 +  },
46567 +/* or.4 (${d-An})${d-i4-4}++,${s1-imm7-4}(${s1-An}),${s2} */
46568 +  {
46569 +    { 0, 0, 0, 0 },
46570 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
46571 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_offset_4, { 0x5a000400 }
46572 +  },
46573 +/* or.4 ${d-i4-4}(${d-An})++,${s1-imm7-4}(${s1-An}),${s2} */
46574 +  {
46575 +    { 0, 0, 0, 0 },
46576 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
46577 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_offset_4, { 0x5a100400 }
46578 +  },
46579 +/* or.4 ${d-direct-addr},(${s1-An}),${s2} */
46580 +  {
46581 +    { 0, 0, 0, 0 },
46582 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
46583 +    & ifmt_pxadds_u_d_direct_s1_indirect_4, { 0x59000400 }
46584 +  },
46585 +/* or.4 #${d-imm8},(${s1-An}),${s2} */
46586 +  {
46587 +    { 0, 0, 0, 0 },
46588 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
46589 +    & ifmt_pxvi_s_d_immediate_4_s1_indirect_4, { 0x58000400 }
46590 +  },
46591 +/* or.4 (${d-An},${d-r}),(${s1-An}),${s2} */
46592 +  {
46593 +    { 0, 0, 0, 0 },
46594 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
46595 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_4, { 0x5b000400 }
46596 +  },
46597 +/* or.4 ${d-imm7-4}(${d-An}),(${s1-An}),${s2} */
46598 +  {
46599 +    { 0, 0, 0, 0 },
46600 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
46601 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_4, { 0x5c000400 }
46602 +  },
46603 +/* or.4 (${d-An}),(${s1-An}),${s2} */
46604 +  {
46605 +    { 0, 0, 0, 0 },
46606 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
46607 +    & ifmt_pxvi_s_d_indirect_4_s1_indirect_4, { 0x5c000400 }
46608 +  },
46609 +/* or.4 (${d-An})${d-i4-4}++,(${s1-An}),${s2} */
46610 +  {
46611 +    { 0, 0, 0, 0 },
46612 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
46613 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_4, { 0x5a000400 }
46614 +  },
46615 +/* or.4 ${d-i4-4}(${d-An})++,(${s1-An}),${s2} */
46616 +  {
46617 +    { 0, 0, 0, 0 },
46618 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
46619 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_4, { 0x5a100400 }
46620 +  },
46621 +/* or.4 ${d-direct-addr},(${s1-An})${s1-i4-4}++,${s2} */
46622 +  {
46623 +    { 0, 0, 0, 0 },
46624 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
46625 +    & ifmt_pxadds_u_d_direct_s1_indirect_with_post_increment_4, { 0x59000200 }
46626 +  },
46627 +/* or.4 #${d-imm8},(${s1-An})${s1-i4-4}++,${s2} */
46628 +  {
46629 +    { 0, 0, 0, 0 },
46630 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
46631 +    & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_post_increment_4, { 0x58000200 }
46632 +  },
46633 +/* or.4 (${d-An},${d-r}),(${s1-An})${s1-i4-4}++,${s2} */
46634 +  {
46635 +    { 0, 0, 0, 0 },
46636 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
46637 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_post_increment_4, { 0x5b000200 }
46638 +  },
46639 +/* or.4 ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-4}++,${s2} */
46640 +  {
46641 +    { 0, 0, 0, 0 },
46642 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
46643 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_post_increment_4, { 0x5c000200 }
46644 +  },
46645 +/* or.4 (${d-An}),(${s1-An})${s1-i4-4}++,${s2} */
46646 +  {
46647 +    { 0, 0, 0, 0 },
46648 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
46649 +    & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_post_increment_4, { 0x5c000200 }
46650 +  },
46651 +/* or.4 (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-4}++,${s2} */
46652 +  {
46653 +    { 0, 0, 0, 0 },
46654 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
46655 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_post_increment_4, { 0x5a000200 }
46656 +  },
46657 +/* or.4 ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-4}++,${s2} */
46658 +  {
46659 +    { 0, 0, 0, 0 },
46660 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
46661 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_post_increment_4, { 0x5a100200 }
46662 +  },
46663 +/* or.4 ${d-direct-addr},${s1-i4-4}(${s1-An})++,${s2} */
46664 +  {
46665 +    { 0, 0, 0, 0 },
46666 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
46667 +    & ifmt_pxadds_u_d_direct_s1_indirect_with_pre_increment_4, { 0x59000210 }
46668 +  },
46669 +/* or.4 #${d-imm8},${s1-i4-4}(${s1-An})++,${s2} */
46670 +  {
46671 +    { 0, 0, 0, 0 },
46672 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
46673 +    & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_pre_increment_4, { 0x58000210 }
46674 +  },
46675 +/* or.4 (${d-An},${d-r}),${s1-i4-4}(${s1-An})++,${s2} */
46676 +  {
46677 +    { 0, 0, 0, 0 },
46678 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
46679 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_pre_increment_4, { 0x5b000210 }
46680 +  },
46681 +/* or.4 ${d-imm7-4}(${d-An}),${s1-i4-4}(${s1-An})++,${s2} */
46682 +  {
46683 +    { 0, 0, 0, 0 },
46684 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
46685 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_pre_increment_4, { 0x5c000210 }
46686 +  },
46687 +/* or.4 (${d-An}),${s1-i4-4}(${s1-An})++,${s2} */
46688 +  {
46689 +    { 0, 0, 0, 0 },
46690 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
46691 +    & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_pre_increment_4, { 0x5c000210 }
46692 +  },
46693 +/* or.4 (${d-An})${d-i4-4}++,${s1-i4-4}(${s1-An})++,${s2} */
46694 +  {
46695 +    { 0, 0, 0, 0 },
46696 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
46697 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_pre_increment_4, { 0x5a000210 }
46698 +  },
46699 +/* or.4 ${d-i4-4}(${d-An})++,${s1-i4-4}(${s1-An})++,${s2} */
46700 +  {
46701 +    { 0, 0, 0, 0 },
46702 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
46703 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_pre_increment_4, { 0x5a100210 }
46704 +  },
46705 +/* or.2 ${d-direct-addr},${s1-direct-addr},${s2} */
46706 +  {
46707 +    { 0, 0, 0, 0 },
46708 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
46709 +    & ifmt_pxadds_u_d_direct_s1_direct, { 0x51000100 }
46710 +  },
46711 +/* or.2 #${d-imm8},${s1-direct-addr},${s2} */
46712 +  {
46713 +    { 0, 0, 0, 0 },
46714 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
46715 +    & ifmt_pxadds_u_d_immediate_2_s1_direct, { 0x50000100 }
46716 +  },
46717 +/* or.2 (${d-An},${d-r}),${s1-direct-addr},${s2} */
46718 +  {
46719 +    { 0, 0, 0, 0 },
46720 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
46721 +    & ifmt_pxadds_u_d_indirect_with_index_2_s1_direct, { 0x53000100 }
46722 +  },
46723 +/* or.2 ${d-imm7-2}(${d-An}),${s1-direct-addr},${s2} */
46724 +  {
46725 +    { 0, 0, 0, 0 },
46726 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
46727 +    & ifmt_pxadds_u_d_indirect_with_offset_2_s1_direct, { 0x54000100 }
46728 +  },
46729 +/* or.2 (${d-An}),${s1-direct-addr},${s2} */
46730 +  {
46731 +    { 0, 0, 0, 0 },
46732 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
46733 +    & ifmt_pxadds_u_d_indirect_2_s1_direct, { 0x54000100 }
46734 +  },
46735 +/* or.2 (${d-An})${d-i4-2}++,${s1-direct-addr},${s2} */
46736 +  {
46737 +    { 0, 0, 0, 0 },
46738 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
46739 +    & ifmt_pxadds_u_d_indirect_with_post_increment_2_s1_direct, { 0x52000100 }
46740 +  },
46741 +/* or.2 ${d-i4-2}(${d-An})++,${s1-direct-addr},${s2} */
46742 +  {
46743 +    { 0, 0, 0, 0 },
46744 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
46745 +    & ifmt_pxadds_u_d_indirect_with_pre_increment_2_s1_direct, { 0x52100100 }
46746 +  },
46747 +/* or.2 ${d-direct-addr},#${s1-imm8},${s2} */
46748 +  {
46749 +    { 0, 0, 0, 0 },
46750 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
46751 +    & ifmt_pxadds_u_d_direct_s1_immediate, { 0x51000000 }
46752 +  },
46753 +/* or.2 #${d-imm8},#${s1-imm8},${s2} */
46754 +  {
46755 +    { 0, 0, 0, 0 },
46756 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
46757 +    & ifmt_pxadds_u_d_immediate_2_s1_immediate, { 0x50000000 }
46758 +  },
46759 +/* or.2 (${d-An},${d-r}),#${s1-imm8},${s2} */
46760 +  {
46761 +    { 0, 0, 0, 0 },
46762 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
46763 +    & ifmt_pxadds_u_d_indirect_with_index_2_s1_immediate, { 0x53000000 }
46764 +  },
46765 +/* or.2 ${d-imm7-2}(${d-An}),#${s1-imm8},${s2} */
46766 +  {
46767 +    { 0, 0, 0, 0 },
46768 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
46769 +    & ifmt_pxadds_u_d_indirect_with_offset_2_s1_immediate, { 0x54000000 }
46770 +  },
46771 +/* or.2 (${d-An}),#${s1-imm8},${s2} */
46772 +  {
46773 +    { 0, 0, 0, 0 },
46774 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
46775 +    & ifmt_pxadds_u_d_indirect_2_s1_immediate, { 0x54000000 }
46776 +  },
46777 +/* or.2 (${d-An})${d-i4-2}++,#${s1-imm8},${s2} */
46778 +  {
46779 +    { 0, 0, 0, 0 },
46780 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
46781 +    & ifmt_pxadds_u_d_indirect_with_post_increment_2_s1_immediate, { 0x52000000 }
46782 +  },
46783 +/* or.2 ${d-i4-2}(${d-An})++,#${s1-imm8},${s2} */
46784 +  {
46785 +    { 0, 0, 0, 0 },
46786 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
46787 +    & ifmt_pxadds_u_d_indirect_with_pre_increment_2_s1_immediate, { 0x52100000 }
46788 +  },
46789 +/* or.2 ${d-direct-addr},(${s1-An},${s1-r}),${s2} */
46790 +  {
46791 +    { 0, 0, 0, 0 },
46792 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
46793 +    & ifmt_sub_2_d_direct_s1_indirect_with_index_2, { 0x51000300 }
46794 +  },
46795 +/* or.2 #${d-imm8},(${s1-An},${s1-r}),${s2} */
46796 +  {
46797 +    { 0, 0, 0, 0 },
46798 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
46799 +    & ifmt_sub_2_d_immediate_2_s1_indirect_with_index_2, { 0x50000300 }
46800 +  },
46801 +/* or.2 (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */
46802 +  {
46803 +    { 0, 0, 0, 0 },
46804 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
46805 +    & ifmt_sub_2_d_indirect_with_index_2_s1_indirect_with_index_2, { 0x53000300 }
46806 +  },
46807 +/* or.2 ${d-imm7-2}(${d-An}),(${s1-An},${s1-r}),${s2} */
46808 +  {
46809 +    { 0, 0, 0, 0 },
46810 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
46811 +    & ifmt_sub_2_d_indirect_with_offset_2_s1_indirect_with_index_2, { 0x54000300 }
46812 +  },
46813 +/* or.2 (${d-An}),(${s1-An},${s1-r}),${s2} */
46814 +  {
46815 +    { 0, 0, 0, 0 },
46816 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
46817 +    & ifmt_sub_2_d_indirect_2_s1_indirect_with_index_2, { 0x54000300 }
46818 +  },
46819 +/* or.2 (${d-An})${d-i4-2}++,(${s1-An},${s1-r}),${s2} */
46820 +  {
46821 +    { 0, 0, 0, 0 },
46822 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
46823 +    & ifmt_sub_2_d_indirect_with_post_increment_2_s1_indirect_with_index_2, { 0x52000300 }
46824 +  },
46825 +/* or.2 ${d-i4-2}(${d-An})++,(${s1-An},${s1-r}),${s2} */
46826 +  {
46827 +    { 0, 0, 0, 0 },
46828 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
46829 +    & ifmt_sub_2_d_indirect_with_pre_increment_2_s1_indirect_with_index_2, { 0x52100300 }
46830 +  },
46831 +/* or.2 ${d-direct-addr},${s1-imm7-2}(${s1-An}),${s2} */
46832 +  {
46833 +    { 0, 0, 0, 0 },
46834 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
46835 +    & ifmt_sub_2_d_direct_s1_indirect_with_offset_2, { 0x51000400 }
46836 +  },
46837 +/* or.2 #${d-imm8},${s1-imm7-2}(${s1-An}),${s2} */
46838 +  {
46839 +    { 0, 0, 0, 0 },
46840 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
46841 +    & ifmt_sub_2_d_immediate_2_s1_indirect_with_offset_2, { 0x50000400 }
46842 +  },
46843 +/* or.2 (${d-An},${d-r}),${s1-imm7-2}(${s1-An}),${s2} */
46844 +  {
46845 +    { 0, 0, 0, 0 },
46846 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
46847 +    & ifmt_sub_2_d_indirect_with_index_2_s1_indirect_with_offset_2, { 0x53000400 }
46848 +  },
46849 +/* or.2 ${d-imm7-2}(${d-An}),${s1-imm7-2}(${s1-An}),${s2} */
46850 +  {
46851 +    { 0, 0, 0, 0 },
46852 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
46853 +    & ifmt_sub_2_d_indirect_with_offset_2_s1_indirect_with_offset_2, { 0x54000400 }
46854 +  },
46855 +/* or.2 (${d-An}),${s1-imm7-2}(${s1-An}),${s2} */
46856 +  {
46857 +    { 0, 0, 0, 0 },
46858 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
46859 +    & ifmt_sub_2_d_indirect_2_s1_indirect_with_offset_2, { 0x54000400 }
46860 +  },
46861 +/* or.2 (${d-An})${d-i4-2}++,${s1-imm7-2}(${s1-An}),${s2} */
46862 +  {
46863 +    { 0, 0, 0, 0 },
46864 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
46865 +    & ifmt_sub_2_d_indirect_with_post_increment_2_s1_indirect_with_offset_2, { 0x52000400 }
46866 +  },
46867 +/* or.2 ${d-i4-2}(${d-An})++,${s1-imm7-2}(${s1-An}),${s2} */
46868 +  {
46869 +    { 0, 0, 0, 0 },
46870 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
46871 +    & ifmt_sub_2_d_indirect_with_pre_increment_2_s1_indirect_with_offset_2, { 0x52100400 }
46872 +  },
46873 +/* or.2 ${d-direct-addr},(${s1-An}),${s2} */
46874 +  {
46875 +    { 0, 0, 0, 0 },
46876 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
46877 +    & ifmt_sub_2_d_direct_s1_indirect_2, { 0x51000400 }
46878 +  },
46879 +/* or.2 #${d-imm8},(${s1-An}),${s2} */
46880 +  {
46881 +    { 0, 0, 0, 0 },
46882 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
46883 +    & ifmt_sub_2_d_immediate_2_s1_indirect_2, { 0x50000400 }
46884 +  },
46885 +/* or.2 (${d-An},${d-r}),(${s1-An}),${s2} */
46886 +  {
46887 +    { 0, 0, 0, 0 },
46888 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
46889 +    & ifmt_sub_2_d_indirect_with_index_2_s1_indirect_2, { 0x53000400 }
46890 +  },
46891 +/* or.2 ${d-imm7-2}(${d-An}),(${s1-An}),${s2} */
46892 +  {
46893 +    { 0, 0, 0, 0 },
46894 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
46895 +    & ifmt_sub_2_d_indirect_with_offset_2_s1_indirect_2, { 0x54000400 }
46896 +  },
46897 +/* or.2 (${d-An}),(${s1-An}),${s2} */
46898 +  {
46899 +    { 0, 0, 0, 0 },
46900 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
46901 +    & ifmt_sub_2_d_indirect_2_s1_indirect_2, { 0x54000400 }
46902 +  },
46903 +/* or.2 (${d-An})${d-i4-2}++,(${s1-An}),${s2} */
46904 +  {
46905 +    { 0, 0, 0, 0 },
46906 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
46907 +    & ifmt_sub_2_d_indirect_with_post_increment_2_s1_indirect_2, { 0x52000400 }
46908 +  },
46909 +/* or.2 ${d-i4-2}(${d-An})++,(${s1-An}),${s2} */
46910 +  {
46911 +    { 0, 0, 0, 0 },
46912 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
46913 +    & ifmt_sub_2_d_indirect_with_pre_increment_2_s1_indirect_2, { 0x52100400 }
46914 +  },
46915 +/* or.2 ${d-direct-addr},(${s1-An})${s1-i4-2}++,${s2} */
46916 +  {
46917 +    { 0, 0, 0, 0 },
46918 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } },
46919 +    & ifmt_sub_2_d_direct_s1_indirect_with_post_increment_2, { 0x51000200 }
46920 +  },
46921 +/* or.2 #${d-imm8},(${s1-An})${s1-i4-2}++,${s2} */
46922 +  {
46923 +    { 0, 0, 0, 0 },
46924 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } },
46925 +    & ifmt_sub_2_d_immediate_2_s1_indirect_with_post_increment_2, { 0x50000200 }
46926 +  },
46927 +/* or.2 (${d-An},${d-r}),(${s1-An})${s1-i4-2}++,${s2} */
46928 +  {
46929 +    { 0, 0, 0, 0 },
46930 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } },
46931 +    & ifmt_sub_2_d_indirect_with_index_2_s1_indirect_with_post_increment_2, { 0x53000200 }
46932 +  },
46933 +/* or.2 ${d-imm7-2}(${d-An}),(${s1-An})${s1-i4-2}++,${s2} */
46934 +  {
46935 +    { 0, 0, 0, 0 },
46936 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } },
46937 +    & ifmt_sub_2_d_indirect_with_offset_2_s1_indirect_with_post_increment_2, { 0x54000200 }
46938 +  },
46939 +/* or.2 (${d-An}),(${s1-An})${s1-i4-2}++,${s2} */
46940 +  {
46941 +    { 0, 0, 0, 0 },
46942 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } },
46943 +    & ifmt_sub_2_d_indirect_2_s1_indirect_with_post_increment_2, { 0x54000200 }
46944 +  },
46945 +/* or.2 (${d-An})${d-i4-2}++,(${s1-An})${s1-i4-2}++,${s2} */
46946 +  {
46947 +    { 0, 0, 0, 0 },
46948 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } },
46949 +    & ifmt_sub_2_d_indirect_with_post_increment_2_s1_indirect_with_post_increment_2, { 0x52000200 }
46950 +  },
46951 +/* or.2 ${d-i4-2}(${d-An})++,(${s1-An})${s1-i4-2}++,${s2} */
46952 +  {
46953 +    { 0, 0, 0, 0 },
46954 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } },
46955 +    & ifmt_sub_2_d_indirect_with_pre_increment_2_s1_indirect_with_post_increment_2, { 0x52100200 }
46956 +  },
46957 +/* or.2 ${d-direct-addr},${s1-i4-2}(${s1-An})++,${s2} */
46958 +  {
46959 +    { 0, 0, 0, 0 },
46960 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
46961 +    & ifmt_sub_2_d_direct_s1_indirect_with_pre_increment_2, { 0x51000210 }
46962 +  },
46963 +/* or.2 #${d-imm8},${s1-i4-2}(${s1-An})++,${s2} */
46964 +  {
46965 +    { 0, 0, 0, 0 },
46966 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
46967 +    & ifmt_sub_2_d_immediate_2_s1_indirect_with_pre_increment_2, { 0x50000210 }
46968 +  },
46969 +/* or.2 (${d-An},${d-r}),${s1-i4-2}(${s1-An})++,${s2} */
46970 +  {
46971 +    { 0, 0, 0, 0 },
46972 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
46973 +    & ifmt_sub_2_d_indirect_with_index_2_s1_indirect_with_pre_increment_2, { 0x53000210 }
46974 +  },
46975 +/* or.2 ${d-imm7-2}(${d-An}),${s1-i4-2}(${s1-An})++,${s2} */
46976 +  {
46977 +    { 0, 0, 0, 0 },
46978 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
46979 +    & ifmt_sub_2_d_indirect_with_offset_2_s1_indirect_with_pre_increment_2, { 0x54000210 }
46980 +  },
46981 +/* or.2 (${d-An}),${s1-i4-2}(${s1-An})++,${s2} */
46982 +  {
46983 +    { 0, 0, 0, 0 },
46984 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
46985 +    & ifmt_sub_2_d_indirect_2_s1_indirect_with_pre_increment_2, { 0x54000210 }
46986 +  },
46987 +/* or.2 (${d-An})${d-i4-2}++,${s1-i4-2}(${s1-An})++,${s2} */
46988 +  {
46989 +    { 0, 0, 0, 0 },
46990 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
46991 +    & ifmt_sub_2_d_indirect_with_post_increment_2_s1_indirect_with_pre_increment_2, { 0x52000210 }
46992 +  },
46993 +/* or.2 ${d-i4-2}(${d-An})++,${s1-i4-2}(${s1-An})++,${s2} */
46994 +  {
46995 +    { 0, 0, 0, 0 },
46996 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
46997 +    & ifmt_sub_2_d_indirect_with_pre_increment_2_s1_indirect_with_pre_increment_2, { 0x52100210 }
46998 +  },
46999 +/* and.4 ${d-direct-addr},${s1-direct-addr},${s2} */
47000 +  {
47001 +    { 0, 0, 0, 0 },
47002 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
47003 +    & ifmt_pxadds_u_d_direct_s1_direct, { 0x49000100 }
47004 +  },
47005 +/* and.4 #${d-imm8},${s1-direct-addr},${s2} */
47006 +  {
47007 +    { 0, 0, 0, 0 },
47008 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
47009 +    & ifmt_pxvi_s_d_immediate_4_s1_direct, { 0x48000100 }
47010 +  },
47011 +/* and.4 (${d-An},${d-r}),${s1-direct-addr},${s2} */
47012 +  {
47013 +    { 0, 0, 0, 0 },
47014 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
47015 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_direct, { 0x4b000100 }
47016 +  },
47017 +/* and.4 ${d-imm7-4}(${d-An}),${s1-direct-addr},${s2} */
47018 +  {
47019 +    { 0, 0, 0, 0 },
47020 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
47021 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_direct, { 0x4c000100 }
47022 +  },
47023 +/* and.4 (${d-An}),${s1-direct-addr},${s2} */
47024 +  {
47025 +    { 0, 0, 0, 0 },
47026 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
47027 +    & ifmt_pxvi_s_d_indirect_4_s1_direct, { 0x4c000100 }
47028 +  },
47029 +/* and.4 (${d-An})${d-i4-4}++,${s1-direct-addr},${s2} */
47030 +  {
47031 +    { 0, 0, 0, 0 },
47032 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
47033 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_direct, { 0x4a000100 }
47034 +  },
47035 +/* and.4 ${d-i4-4}(${d-An})++,${s1-direct-addr},${s2} */
47036 +  {
47037 +    { 0, 0, 0, 0 },
47038 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
47039 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_direct, { 0x4a100100 }
47040 +  },
47041 +/* and.4 ${d-direct-addr},#${s1-imm8},${s2} */
47042 +  {
47043 +    { 0, 0, 0, 0 },
47044 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
47045 +    & ifmt_pxadds_u_d_direct_s1_immediate, { 0x49000000 }
47046 +  },
47047 +/* and.4 #${d-imm8},#${s1-imm8},${s2} */
47048 +  {
47049 +    { 0, 0, 0, 0 },
47050 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
47051 +    & ifmt_pxvi_s_d_immediate_4_s1_immediate, { 0x48000000 }
47052 +  },
47053 +/* and.4 (${d-An},${d-r}),#${s1-imm8},${s2} */
47054 +  {
47055 +    { 0, 0, 0, 0 },
47056 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
47057 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_immediate, { 0x4b000000 }
47058 +  },
47059 +/* and.4 ${d-imm7-4}(${d-An}),#${s1-imm8},${s2} */
47060 +  {
47061 +    { 0, 0, 0, 0 },
47062 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
47063 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_immediate, { 0x4c000000 }
47064 +  },
47065 +/* and.4 (${d-An}),#${s1-imm8},${s2} */
47066 +  {
47067 +    { 0, 0, 0, 0 },
47068 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
47069 +    & ifmt_pxvi_s_d_indirect_4_s1_immediate, { 0x4c000000 }
47070 +  },
47071 +/* and.4 (${d-An})${d-i4-4}++,#${s1-imm8},${s2} */
47072 +  {
47073 +    { 0, 0, 0, 0 },
47074 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
47075 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_immediate, { 0x4a000000 }
47076 +  },
47077 +/* and.4 ${d-i4-4}(${d-An})++,#${s1-imm8},${s2} */
47078 +  {
47079 +    { 0, 0, 0, 0 },
47080 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
47081 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_immediate, { 0x4a100000 }
47082 +  },
47083 +/* and.4 ${d-direct-addr},(${s1-An},${s1-r}),${s2} */
47084 +  {
47085 +    { 0, 0, 0, 0 },
47086 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
47087 +    & ifmt_pxadds_u_d_direct_s1_indirect_with_index_4, { 0x49000300 }
47088 +  },
47089 +/* and.4 #${d-imm8},(${s1-An},${s1-r}),${s2} */
47090 +  {
47091 +    { 0, 0, 0, 0 },
47092 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
47093 +    & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_index_4, { 0x48000300 }
47094 +  },
47095 +/* and.4 (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */
47096 +  {
47097 +    { 0, 0, 0, 0 },
47098 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
47099 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_index_4, { 0x4b000300 }
47100 +  },
47101 +/* and.4 ${d-imm7-4}(${d-An}),(${s1-An},${s1-r}),${s2} */
47102 +  {
47103 +    { 0, 0, 0, 0 },
47104 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
47105 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_index_4, { 0x4c000300 }
47106 +  },
47107 +/* and.4 (${d-An}),(${s1-An},${s1-r}),${s2} */
47108 +  {
47109 +    { 0, 0, 0, 0 },
47110 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
47111 +    & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_index_4, { 0x4c000300 }
47112 +  },
47113 +/* and.4 (${d-An})${d-i4-4}++,(${s1-An},${s1-r}),${s2} */
47114 +  {
47115 +    { 0, 0, 0, 0 },
47116 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
47117 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_index_4, { 0x4a000300 }
47118 +  },
47119 +/* and.4 ${d-i4-4}(${d-An})++,(${s1-An},${s1-r}),${s2} */
47120 +  {
47121 +    { 0, 0, 0, 0 },
47122 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
47123 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_index_4, { 0x4a100300 }
47124 +  },
47125 +/* and.4 ${d-direct-addr},${s1-imm7-4}(${s1-An}),${s2} */
47126 +  {
47127 +    { 0, 0, 0, 0 },
47128 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
47129 +    & ifmt_pxadds_u_d_direct_s1_indirect_with_offset_4, { 0x49000400 }
47130 +  },
47131 +/* and.4 #${d-imm8},${s1-imm7-4}(${s1-An}),${s2} */
47132 +  {
47133 +    { 0, 0, 0, 0 },
47134 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
47135 +    & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_offset_4, { 0x48000400 }
47136 +  },
47137 +/* and.4 (${d-An},${d-r}),${s1-imm7-4}(${s1-An}),${s2} */
47138 +  {
47139 +    { 0, 0, 0, 0 },
47140 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
47141 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_offset_4, { 0x4b000400 }
47142 +  },
47143 +/* and.4 ${d-imm7-4}(${d-An}),${s1-imm7-4}(${s1-An}),${s2} */
47144 +  {
47145 +    { 0, 0, 0, 0 },
47146 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
47147 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_offset_4, { 0x4c000400 }
47148 +  },
47149 +/* and.4 (${d-An}),${s1-imm7-4}(${s1-An}),${s2} */
47150 +  {
47151 +    { 0, 0, 0, 0 },
47152 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
47153 +    & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_offset_4, { 0x4c000400 }
47154 +  },
47155 +/* and.4 (${d-An})${d-i4-4}++,${s1-imm7-4}(${s1-An}),${s2} */
47156 +  {
47157 +    { 0, 0, 0, 0 },
47158 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
47159 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_offset_4, { 0x4a000400 }
47160 +  },
47161 +/* and.4 ${d-i4-4}(${d-An})++,${s1-imm7-4}(${s1-An}),${s2} */
47162 +  {
47163 +    { 0, 0, 0, 0 },
47164 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_4), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
47165 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_offset_4, { 0x4a100400 }
47166 +  },
47167 +/* and.4 ${d-direct-addr},(${s1-An}),${s2} */
47168 +  {
47169 +    { 0, 0, 0, 0 },
47170 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
47171 +    & ifmt_pxadds_u_d_direct_s1_indirect_4, { 0x49000400 }
47172 +  },
47173 +/* and.4 #${d-imm8},(${s1-An}),${s2} */
47174 +  {
47175 +    { 0, 0, 0, 0 },
47176 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
47177 +    & ifmt_pxvi_s_d_immediate_4_s1_indirect_4, { 0x48000400 }
47178 +  },
47179 +/* and.4 (${d-An},${d-r}),(${s1-An}),${s2} */
47180 +  {
47181 +    { 0, 0, 0, 0 },
47182 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
47183 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_4, { 0x4b000400 }
47184 +  },
47185 +/* and.4 ${d-imm7-4}(${d-An}),(${s1-An}),${s2} */
47186 +  {
47187 +    { 0, 0, 0, 0 },
47188 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
47189 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_4, { 0x4c000400 }
47190 +  },
47191 +/* and.4 (${d-An}),(${s1-An}),${s2} */
47192 +  {
47193 +    { 0, 0, 0, 0 },
47194 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
47195 +    & ifmt_pxvi_s_d_indirect_4_s1_indirect_4, { 0x4c000400 }
47196 +  },
47197 +/* and.4 (${d-An})${d-i4-4}++,(${s1-An}),${s2} */
47198 +  {
47199 +    { 0, 0, 0, 0 },
47200 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
47201 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_4, { 0x4a000400 }
47202 +  },
47203 +/* and.4 ${d-i4-4}(${d-An})++,(${s1-An}),${s2} */
47204 +  {
47205 +    { 0, 0, 0, 0 },
47206 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
47207 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_4, { 0x4a100400 }
47208 +  },
47209 +/* and.4 ${d-direct-addr},(${s1-An})${s1-i4-4}++,${s2} */
47210 +  {
47211 +    { 0, 0, 0, 0 },
47212 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
47213 +    & ifmt_pxadds_u_d_direct_s1_indirect_with_post_increment_4, { 0x49000200 }
47214 +  },
47215 +/* and.4 #${d-imm8},(${s1-An})${s1-i4-4}++,${s2} */
47216 +  {
47217 +    { 0, 0, 0, 0 },
47218 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
47219 +    & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_post_increment_4, { 0x48000200 }
47220 +  },
47221 +/* and.4 (${d-An},${d-r}),(${s1-An})${s1-i4-4}++,${s2} */
47222 +  {
47223 +    { 0, 0, 0, 0 },
47224 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
47225 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_post_increment_4, { 0x4b000200 }
47226 +  },
47227 +/* and.4 ${d-imm7-4}(${d-An}),(${s1-An})${s1-i4-4}++,${s2} */
47228 +  {
47229 +    { 0, 0, 0, 0 },
47230 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
47231 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_post_increment_4, { 0x4c000200 }
47232 +  },
47233 +/* and.4 (${d-An}),(${s1-An})${s1-i4-4}++,${s2} */
47234 +  {
47235 +    { 0, 0, 0, 0 },
47236 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
47237 +    & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_post_increment_4, { 0x4c000200 }
47238 +  },
47239 +/* and.4 (${d-An})${d-i4-4}++,(${s1-An})${s1-i4-4}++,${s2} */
47240 +  {
47241 +    { 0, 0, 0, 0 },
47242 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
47243 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_post_increment_4, { 0x4a000200 }
47244 +  },
47245 +/* and.4 ${d-i4-4}(${d-An})++,(${s1-An})${s1-i4-4}++,${s2} */
47246 +  {
47247 +    { 0, 0, 0, 0 },
47248 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_4), '+', '+', ',', OP (S2), 0 } },
47249 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_post_increment_4, { 0x4a100200 }
47250 +  },
47251 +/* and.4 ${d-direct-addr},${s1-i4-4}(${s1-An})++,${s2} */
47252 +  {
47253 +    { 0, 0, 0, 0 },
47254 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
47255 +    & ifmt_pxadds_u_d_direct_s1_indirect_with_pre_increment_4, { 0x49000210 }
47256 +  },
47257 +/* and.4 #${d-imm8},${s1-i4-4}(${s1-An})++,${s2} */
47258 +  {
47259 +    { 0, 0, 0, 0 },
47260 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
47261 +    & ifmt_pxvi_s_d_immediate_4_s1_indirect_with_pre_increment_4, { 0x48000210 }
47262 +  },
47263 +/* and.4 (${d-An},${d-r}),${s1-i4-4}(${s1-An})++,${s2} */
47264 +  {
47265 +    { 0, 0, 0, 0 },
47266 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
47267 +    & ifmt_pxvi_s_d_indirect_with_index_4_s1_indirect_with_pre_increment_4, { 0x4b000210 }
47268 +  },
47269 +/* and.4 ${d-imm7-4}(${d-An}),${s1-i4-4}(${s1-An})++,${s2} */
47270 +  {
47271 +    { 0, 0, 0, 0 },
47272 +    { { MNEM, ' ', OP (D_IMM7_4), '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
47273 +    & ifmt_pxvi_s_d_indirect_with_offset_4_s1_indirect_with_pre_increment_4, { 0x4c000210 }
47274 +  },
47275 +/* and.4 (${d-An}),${s1-i4-4}(${s1-An})++,${s2} */
47276 +  {
47277 +    { 0, 0, 0, 0 },
47278 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
47279 +    & ifmt_pxvi_s_d_indirect_4_s1_indirect_with_pre_increment_4, { 0x4c000210 }
47280 +  },
47281 +/* and.4 (${d-An})${d-i4-4}++,${s1-i4-4}(${s1-An})++,${s2} */
47282 +  {
47283 +    { 0, 0, 0, 0 },
47284 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_4), '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
47285 +    & ifmt_pxvi_s_d_indirect_with_post_increment_4_s1_indirect_with_pre_increment_4, { 0x4a000210 }
47286 +  },
47287 +/* and.4 ${d-i4-4}(${d-An})++,${s1-i4-4}(${s1-An})++,${s2} */
47288 +  {
47289 +    { 0, 0, 0, 0 },
47290 +    { { MNEM, ' ', OP (D_I4_4), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_4), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
47291 +    & ifmt_pxvi_s_d_indirect_with_pre_increment_4_s1_indirect_with_pre_increment_4, { 0x4a100210 }
47292 +  },
47293 +/* and.2 ${d-direct-addr},${s1-direct-addr},${s2} */
47294 +  {
47295 +    { 0, 0, 0, 0 },
47296 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
47297 +    & ifmt_pxadds_u_d_direct_s1_direct, { 0x41000100 }
47298 +  },
47299 +/* and.2 #${d-imm8},${s1-direct-addr},${s2} */
47300 +  {
47301 +    { 0, 0, 0, 0 },
47302 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
47303 +    & ifmt_pxadds_u_d_immediate_2_s1_direct, { 0x40000100 }
47304 +  },
47305 +/* and.2 (${d-An},${d-r}),${s1-direct-addr},${s2} */
47306 +  {
47307 +    { 0, 0, 0, 0 },
47308 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
47309 +    & ifmt_pxadds_u_d_indirect_with_index_2_s1_direct, { 0x43000100 }
47310 +  },
47311 +/* and.2 ${d-imm7-2}(${d-An}),${s1-direct-addr},${s2} */
47312 +  {
47313 +    { 0, 0, 0, 0 },
47314 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
47315 +    & ifmt_pxadds_u_d_indirect_with_offset_2_s1_direct, { 0x44000100 }
47316 +  },
47317 +/* and.2 (${d-An}),${s1-direct-addr},${s2} */
47318 +  {
47319 +    { 0, 0, 0, 0 },
47320 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
47321 +    & ifmt_pxadds_u_d_indirect_2_s1_direct, { 0x44000100 }
47322 +  },
47323 +/* and.2 (${d-An})${d-i4-2}++,${s1-direct-addr},${s2} */
47324 +  {
47325 +    { 0, 0, 0, 0 },
47326 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
47327 +    & ifmt_pxadds_u_d_indirect_with_post_increment_2_s1_direct, { 0x42000100 }
47328 +  },
47329 +/* and.2 ${d-i4-2}(${d-An})++,${s1-direct-addr},${s2} */
47330 +  {
47331 +    { 0, 0, 0, 0 },
47332 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_DIRECT_ADDR), ',', OP (S2), 0 } },
47333 +    & ifmt_pxadds_u_d_indirect_with_pre_increment_2_s1_direct, { 0x42100100 }
47334 +  },
47335 +/* and.2 ${d-direct-addr},#${s1-imm8},${s2} */
47336 +  {
47337 +    { 0, 0, 0, 0 },
47338 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
47339 +    & ifmt_pxadds_u_d_direct_s1_immediate, { 0x41000000 }
47340 +  },
47341 +/* and.2 #${d-imm8},#${s1-imm8},${s2} */
47342 +  {
47343 +    { 0, 0, 0, 0 },
47344 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
47345 +    & ifmt_pxadds_u_d_immediate_2_s1_immediate, { 0x40000000 }
47346 +  },
47347 +/* and.2 (${d-An},${d-r}),#${s1-imm8},${s2} */
47348 +  {
47349 +    { 0, 0, 0, 0 },
47350 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
47351 +    & ifmt_pxadds_u_d_indirect_with_index_2_s1_immediate, { 0x43000000 }
47352 +  },
47353 +/* and.2 ${d-imm7-2}(${d-An}),#${s1-imm8},${s2} */
47354 +  {
47355 +    { 0, 0, 0, 0 },
47356 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
47357 +    & ifmt_pxadds_u_d_indirect_with_offset_2_s1_immediate, { 0x44000000 }
47358 +  },
47359 +/* and.2 (${d-An}),#${s1-imm8},${s2} */
47360 +  {
47361 +    { 0, 0, 0, 0 },
47362 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
47363 +    & ifmt_pxadds_u_d_indirect_2_s1_immediate, { 0x44000000 }
47364 +  },
47365 +/* and.2 (${d-An})${d-i4-2}++,#${s1-imm8},${s2} */
47366 +  {
47367 +    { 0, 0, 0, 0 },
47368 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
47369 +    & ifmt_pxadds_u_d_indirect_with_post_increment_2_s1_immediate, { 0x42000000 }
47370 +  },
47371 +/* and.2 ${d-i4-2}(${d-An})++,#${s1-imm8},${s2} */
47372 +  {
47373 +    { 0, 0, 0, 0 },
47374 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '#', OP (S1_IMM8), ',', OP (S2), 0 } },
47375 +    & ifmt_pxadds_u_d_indirect_with_pre_increment_2_s1_immediate, { 0x42100000 }
47376 +  },
47377 +/* and.2 ${d-direct-addr},(${s1-An},${s1-r}),${s2} */
47378 +  {
47379 +    { 0, 0, 0, 0 },
47380 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
47381 +    & ifmt_sub_2_d_direct_s1_indirect_with_index_2, { 0x41000300 }
47382 +  },
47383 +/* and.2 #${d-imm8},(${s1-An},${s1-r}),${s2} */
47384 +  {
47385 +    { 0, 0, 0, 0 },
47386 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
47387 +    & ifmt_sub_2_d_immediate_2_s1_indirect_with_index_2, { 0x40000300 }
47388 +  },
47389 +/* and.2 (${d-An},${d-r}),(${s1-An},${s1-r}),${s2} */
47390 +  {
47391 +    { 0, 0, 0, 0 },
47392 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
47393 +    & ifmt_sub_2_d_indirect_with_index_2_s1_indirect_with_index_2, { 0x43000300 }
47394 +  },
47395 +/* and.2 ${d-imm7-2}(${d-An}),(${s1-An},${s1-r}),${s2} */
47396 +  {
47397 +    { 0, 0, 0, 0 },
47398 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
47399 +    & ifmt_sub_2_d_indirect_with_offset_2_s1_indirect_with_index_2, { 0x44000300 }
47400 +  },
47401 +/* and.2 (${d-An}),(${s1-An},${s1-r}),${s2} */
47402 +  {
47403 +    { 0, 0, 0, 0 },
47404 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
47405 +    & ifmt_sub_2_d_indirect_2_s1_indirect_with_index_2, { 0x44000300 }
47406 +  },
47407 +/* and.2 (${d-An})${d-i4-2}++,(${s1-An},${s1-r}),${s2} */
47408 +  {
47409 +    { 0, 0, 0, 0 },
47410 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
47411 +    & ifmt_sub_2_d_indirect_with_post_increment_2_s1_indirect_with_index_2, { 0x42000300 }
47412 +  },
47413 +/* and.2 ${d-i4-2}(${d-An})++,(${s1-An},${s1-r}),${s2} */
47414 +  {
47415 +    { 0, 0, 0, 0 },
47416 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ',', OP (S1_R), ')', ',', OP (S2), 0 } },
47417 +    & ifmt_sub_2_d_indirect_with_pre_increment_2_s1_indirect_with_index_2, { 0x42100300 }
47418 +  },
47419 +/* and.2 ${d-direct-addr},${s1-imm7-2}(${s1-An}),${s2} */
47420 +  {
47421 +    { 0, 0, 0, 0 },
47422 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
47423 +    & ifmt_sub_2_d_direct_s1_indirect_with_offset_2, { 0x41000400 }
47424 +  },
47425 +/* and.2 #${d-imm8},${s1-imm7-2}(${s1-An}),${s2} */
47426 +  {
47427 +    { 0, 0, 0, 0 },
47428 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
47429 +    & ifmt_sub_2_d_immediate_2_s1_indirect_with_offset_2, { 0x40000400 }
47430 +  },
47431 +/* and.2 (${d-An},${d-r}),${s1-imm7-2}(${s1-An}),${s2} */
47432 +  {
47433 +    { 0, 0, 0, 0 },
47434 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
47435 +    & ifmt_sub_2_d_indirect_with_index_2_s1_indirect_with_offset_2, { 0x43000400 }
47436 +  },
47437 +/* and.2 ${d-imm7-2}(${d-An}),${s1-imm7-2}(${s1-An}),${s2} */
47438 +  {
47439 +    { 0, 0, 0, 0 },
47440 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
47441 +    & ifmt_sub_2_d_indirect_with_offset_2_s1_indirect_with_offset_2, { 0x44000400 }
47442 +  },
47443 +/* and.2 (${d-An}),${s1-imm7-2}(${s1-An}),${s2} */
47444 +  {
47445 +    { 0, 0, 0, 0 },
47446 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
47447 +    & ifmt_sub_2_d_indirect_2_s1_indirect_with_offset_2, { 0x44000400 }
47448 +  },
47449 +/* and.2 (${d-An})${d-i4-2}++,${s1-imm7-2}(${s1-An}),${s2} */
47450 +  {
47451 +    { 0, 0, 0, 0 },
47452 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
47453 +    & ifmt_sub_2_d_indirect_with_post_increment_2_s1_indirect_with_offset_2, { 0x42000400 }
47454 +  },
47455 +/* and.2 ${d-i4-2}(${d-An})++,${s1-imm7-2}(${s1-An}),${s2} */
47456 +  {
47457 +    { 0, 0, 0, 0 },
47458 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_IMM7_2), '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
47459 +    & ifmt_sub_2_d_indirect_with_pre_increment_2_s1_indirect_with_offset_2, { 0x42100400 }
47460 +  },
47461 +/* and.2 ${d-direct-addr},(${s1-An}),${s2} */
47462 +  {
47463 +    { 0, 0, 0, 0 },
47464 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
47465 +    & ifmt_sub_2_d_direct_s1_indirect_2, { 0x41000400 }
47466 +  },
47467 +/* and.2 #${d-imm8},(${s1-An}),${s2} */
47468 +  {
47469 +    { 0, 0, 0, 0 },
47470 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
47471 +    & ifmt_sub_2_d_immediate_2_s1_indirect_2, { 0x40000400 }
47472 +  },
47473 +/* and.2 (${d-An},${d-r}),(${s1-An}),${s2} */
47474 +  {
47475 +    { 0, 0, 0, 0 },
47476 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
47477 +    & ifmt_sub_2_d_indirect_with_index_2_s1_indirect_2, { 0x43000400 }
47478 +  },
47479 +/* and.2 ${d-imm7-2}(${d-An}),(${s1-An}),${s2} */
47480 +  {
47481 +    { 0, 0, 0, 0 },
47482 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
47483 +    & ifmt_sub_2_d_indirect_with_offset_2_s1_indirect_2, { 0x44000400 }
47484 +  },
47485 +/* and.2 (${d-An}),(${s1-An}),${s2} */
47486 +  {
47487 +    { 0, 0, 0, 0 },
47488 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
47489 +    & ifmt_sub_2_d_indirect_2_s1_indirect_2, { 0x44000400 }
47490 +  },
47491 +/* and.2 (${d-An})${d-i4-2}++,(${s1-An}),${s2} */
47492 +  {
47493 +    { 0, 0, 0, 0 },
47494 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
47495 +    & ifmt_sub_2_d_indirect_with_post_increment_2_s1_indirect_2, { 0x42000400 }
47496 +  },
47497 +/* and.2 ${d-i4-2}(${d-An})++,(${s1-An}),${s2} */
47498 +  {
47499 +    { 0, 0, 0, 0 },
47500 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', ',', OP (S2), 0 } },
47501 +    & ifmt_sub_2_d_indirect_with_pre_increment_2_s1_indirect_2, { 0x42100400 }
47502 +  },
47503 +/* and.2 ${d-direct-addr},(${s1-An})${s1-i4-2}++,${s2} */
47504 +  {
47505 +    { 0, 0, 0, 0 },
47506 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } },
47507 +    & ifmt_sub_2_d_direct_s1_indirect_with_post_increment_2, { 0x41000200 }
47508 +  },
47509 +/* and.2 #${d-imm8},(${s1-An})${s1-i4-2}++,${s2} */
47510 +  {
47511 +    { 0, 0, 0, 0 },
47512 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } },
47513 +    & ifmt_sub_2_d_immediate_2_s1_indirect_with_post_increment_2, { 0x40000200 }
47514 +  },
47515 +/* and.2 (${d-An},${d-r}),(${s1-An})${s1-i4-2}++,${s2} */
47516 +  {
47517 +    { 0, 0, 0, 0 },
47518 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } },
47519 +    & ifmt_sub_2_d_indirect_with_index_2_s1_indirect_with_post_increment_2, { 0x43000200 }
47520 +  },
47521 +/* and.2 ${d-imm7-2}(${d-An}),(${s1-An})${s1-i4-2}++,${s2} */
47522 +  {
47523 +    { 0, 0, 0, 0 },
47524 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } },
47525 +    & ifmt_sub_2_d_indirect_with_offset_2_s1_indirect_with_post_increment_2, { 0x44000200 }
47526 +  },
47527 +/* and.2 (${d-An}),(${s1-An})${s1-i4-2}++,${s2} */
47528 +  {
47529 +    { 0, 0, 0, 0 },
47530 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } },
47531 +    & ifmt_sub_2_d_indirect_2_s1_indirect_with_post_increment_2, { 0x44000200 }
47532 +  },
47533 +/* and.2 (${d-An})${d-i4-2}++,(${s1-An})${s1-i4-2}++,${s2} */
47534 +  {
47535 +    { 0, 0, 0, 0 },
47536 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } },
47537 +    & ifmt_sub_2_d_indirect_with_post_increment_2_s1_indirect_with_post_increment_2, { 0x42000200 }
47538 +  },
47539 +/* and.2 ${d-i4-2}(${d-An})++,(${s1-An})${s1-i4-2}++,${s2} */
47540 +  {
47541 +    { 0, 0, 0, 0 },
47542 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', '(', OP (S1_AN), ')', OP (S1_I4_2), '+', '+', ',', OP (S2), 0 } },
47543 +    & ifmt_sub_2_d_indirect_with_pre_increment_2_s1_indirect_with_post_increment_2, { 0x42100200 }
47544 +  },
47545 +/* and.2 ${d-direct-addr},${s1-i4-2}(${s1-An})++,${s2} */
47546 +  {
47547 +    { 0, 0, 0, 0 },
47548 +    { { MNEM, ' ', OP (D_DIRECT_ADDR), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
47549 +    & ifmt_sub_2_d_direct_s1_indirect_with_pre_increment_2, { 0x41000210 }
47550 +  },
47551 +/* and.2 #${d-imm8},${s1-i4-2}(${s1-An})++,${s2} */
47552 +  {
47553 +    { 0, 0, 0, 0 },
47554 +    { { MNEM, ' ', '#', OP (D_IMM8), ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
47555 +    & ifmt_sub_2_d_immediate_2_s1_indirect_with_pre_increment_2, { 0x40000210 }
47556 +  },
47557 +/* and.2 (${d-An},${d-r}),${s1-i4-2}(${s1-An})++,${s2} */
47558 +  {
47559 +    { 0, 0, 0, 0 },
47560 +    { { MNEM, ' ', '(', OP (D_AN), ',', OP (D_R), ')', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
47561 +    & ifmt_sub_2_d_indirect_with_index_2_s1_indirect_with_pre_increment_2, { 0x43000210 }
47562 +  },
47563 +/* and.2 ${d-imm7-2}(${d-An}),${s1-i4-2}(${s1-An})++,${s2} */
47564 +  {
47565 +    { 0, 0, 0, 0 },
47566 +    { { MNEM, ' ', OP (D_IMM7_2), '(', OP (D_AN), ')', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
47567 +    & ifmt_sub_2_d_indirect_with_offset_2_s1_indirect_with_pre_increment_2, { 0x44000210 }
47568 +  },
47569 +/* and.2 (${d-An}),${s1-i4-2}(${s1-An})++,${s2} */
47570 +  {
47571 +    { 0, 0, 0, 0 },
47572 +    { { MNEM, ' ', '(', OP (D_AN), ')', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
47573 +    & ifmt_sub_2_d_indirect_2_s1_indirect_with_pre_increment_2, { 0x44000210 }
47574 +  },
47575 +/* and.2 (${d-An})${d-i4-2}++,${s1-i4-2}(${s1-An})++,${s2} */
47576 +  {
47577 +    { 0, 0, 0, 0 },
47578 +    { { MNEM, ' ', '(', OP (D_AN), ')', OP (D_I4_2), '+', '+', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
47579 +    & ifmt_sub_2_d_indirect_with_post_increment_2_s1_indirect_with_pre_increment_2, { 0x42000210 }
47580 +  },
47581 +/* and.2 ${d-i4-2}(${d-An})++,${s1-i4-2}(${s1-An})++,${s2} */
47582 +  {
47583 +    { 0, 0, 0, 0 },
47584 +    { { MNEM, ' ', OP (D_I4_2), '(', OP (D_AN), ')', '+', '+', ',', OP (S1_I4_2), '(', OP (S1_AN), ')', '+', '+', ',', OP (S2), 0 } },
47585 +    & ifmt_sub_2_d_indirect_with_pre_increment_2_s1_indirect_with_pre_increment_2, { 0x42100210 }
47586 +  },
47587 +/* moveai ${An},#${imm24} */
47588 +  {
47589 +    { 0, 0, 0, 0 },
47590 +    { { MNEM, ' ', OP (AN), ',', '#', OP (IMM24), 0 } },
47591 +    & ifmt_moveai, { 0xe0000000 }
47592 +  },
47593 +/* __nop__ */
47594 +  {
47595 +    { 0, 0, 0, 0 },
47596 +    { { MNEM, 0 } },
47597 +    & ifmt_nop_insn, { 0xc8000000 }
47598 +  },
47599 +/* jmp${cc}${C}${P} $offset21 */
47600 +  {
47601 +    { 0, 0, 0, 0 },
47602 +    { { MNEM, OP (CC), OP (C), OP (P), ' ', OP (OFFSET21), 0 } },
47603 +    & ifmt_jmpcc, { 0xd0000000 }
47604 +  },
47605 +/* call $An,$offset24 */
47606 +  {
47607 +    { 0, 0, 0, 0 },
47608 +    { { MNEM, ' ', OP (AN), ',', OP (OFFSET24), 0 } },
47609 +    & ifmt_call, { 0xd8000000 }
47610 +  },
47611 +/* calli ${An},${offset16}(${Am}) */
47612 +  {
47613 +    { 0, 0, 0, 0 },
47614 +    { { MNEM, ' ', OP (AN), ',', OP (OFFSET16), '(', OP (AM), ')', 0 } },
47615 +    & ifmt_calli, { 0xf0000000 }
47616 +  },
47617 +/* suspend */
47618 +  {
47619 +    { 0, 0, 0, 0 },
47620 +    { { MNEM, 0 } },
47621 +    & ifmt_suspend, { 0x800 }
47622 +  },
47623 +/* __clracc__ ${dsp-destA} */
47624 +  {
47625 +    { 0, 0, 0, 0 },
47626 +    { { MNEM, ' ', OP (DSP_DESTA), 0 } },
47627 +    & ifmt_dsp_clracc, { 0x36400100 }
47628 +  },
47629 +/* __unused__00_11 */
47630 +  {
47631 +    { 0, 0, 0, 0 },
47632 +    { { MNEM, 0 } },
47633 +    & ifmt_unused_00_11, { 0x8800 }
47634 +  },
47635 +/* __unused__00_13 */
47636 +  {
47637 +    { 0, 0, 0, 0 },
47638 +    { { MNEM, 0 } },
47639 +    & ifmt_unused_00_11, { 0x9800 }
47640 +  },
47641 +/* __unused__00_14 */
47642 +  {
47643 +    { 0, 0, 0, 0 },
47644 +    { { MNEM, 0 } },
47645 +    & ifmt_unused_00_11, { 0xa000 }
47646 +  },
47647 +/* __unused__00_16 */
47648 +  {
47649 +    { 0, 0, 0, 0 },
47650 +    { { MNEM, 0 } },
47651 +    & ifmt_unused_00_11, { 0xb000 }
47652 +  },
47653 +/* __unused__02_04 */
47654 +  {
47655 +    { 0, 0, 0, 0 },
47656 +    { { MNEM, 0 } },
47657 +    & ifmt_unused_02_04, { 0x10800000 }
47658 +  },
47659 +/* __unused__02_07 */
47660 +  {
47661 +    { 0, 0, 0, 0 },
47662 +    { { MNEM, 0 } },
47663 +    & ifmt_unused_02_04, { 0x10e00000 }
47664 +  },
47665 +/* __unused__02_0D */
47666 +  {
47667 +    { 0, 0, 0, 0 },
47668 +    { { MNEM, 0 } },
47669 +    & ifmt_unused_02_04, { 0x11a00000 }
47670 +  },
47671 +/* __unused__02_0E */
47672 +  {
47673 +    { 0, 0, 0, 0 },
47674 +    { { MNEM, 0 } },
47675 +    & ifmt_unused_02_04, { 0x11c00000 }
47676 +  },
47677 +/* __unused__02_0F */
47678 +  {
47679 +    { 0, 0, 0, 0 },
47680 +    { { MNEM, 0 } },
47681 +    & ifmt_unused_02_04, { 0x11e00000 }
47682 +  },
47683 +/* __unused__02_17 */
47684 +  {
47685 +    { 0, 0, 0, 0 },
47686 +    { { MNEM, 0 } },
47687 +    & ifmt_unused_02_04, { 0x12e00000 }
47688 +  },
47689 +/* __unused__02_19 */
47690 +  {
47691 +    { 0, 0, 0, 0 },
47692 +    { { MNEM, 0 } },
47693 +    & ifmt_unused_02_04, { 0x13200000 }
47694 +  },
47695 +/* __unused__02_1B */
47696 +  {
47697 +    { 0, 0, 0, 0 },
47698 +    { { MNEM, 0 } },
47699 +    & ifmt_unused_02_04, { 0x13600000 }
47700 +  },
47701 +/* __unused__02_1D */
47702 +  {
47703 +    { 0, 0, 0, 0 },
47704 +    { { MNEM, 0 } },
47705 +    & ifmt_unused_02_04, { 0x13a00000 }
47706 +  },
47707 +/* __unused__01 */
47708 +  {
47709 +    { 0, 0, 0, 0 },
47710 +    { { MNEM, 0 } },
47711 +    & ifmt_unused_01, { 0x8000000 }
47712 +  },
47713 +/* __unused__03 */
47714 +  {
47715 +    { 0, 0, 0, 0 },
47716 +    { { MNEM, 0 } },
47717 +    & ifmt_unused_01, { 0x18000000 }
47718 +  },
47719 +/* __unused__07 */
47720 +  {
47721 +    { 0, 0, 0, 0 },
47722 +    { { MNEM, 0 } },
47723 +    & ifmt_unused_01, { 0x38000000 }
47724 +  },
47725 +/* __unused__17 */
47726 +  {
47727 +    { 0, 0, 0, 0 },
47728 +    { { MNEM, 0 } },
47729 +    & ifmt_unused_01, { 0xb8000000 }
47730 +  },
47731 +/* __unused__1D */
47732 +  {
47733 +    { 0, 0, 0, 0 },
47734 +    { { MNEM, 0 } },
47735 +    & ifmt_unused_01, { 0xe8000000 }
47736 +  },
47737 +/* __unused__1F */
47738 +  {
47739 +    { 0, 0, 0, 0 },
47740 +    { { MNEM, 0 } },
47741 +    & ifmt_unused_01, { 0xf8000000 }
47742 +  },
47743 +/* __unused__DSP_06 */
47744 +  {
47745 +    { 0, 0, 0, 0 },
47746 +    { { MNEM, 0 } },
47747 +    & ifmt_unused_DSP_06, { 0x30c00000 }
47748 +  },
47749 +/* __unused__DSP_0b */
47750 +  {
47751 +    { 0, 0, 0, 0 },
47752 +    { { MNEM, 0 } },
47753 +    & ifmt_unused_DSP_06, { 0x31600000 }
47754 +  },
47755 +/* __unused__DSP_0c */
47756 +  {
47757 +    { 0, 0, 0, 0 },
47758 +    { { MNEM, 0 } },
47759 +    & ifmt_unused_DSP_06, { 0x31800000 }
47760 +  },
47761 +/* __unused__DSP_0d */
47762 +  {
47763 +    { 0, 0, 0, 0 },
47764 +    { { MNEM, 0 } },
47765 +    & ifmt_unused_DSP_06, { 0x31a00000 }
47766 +  },
47767 +/* __unused__DSP_0e */
47768 +  {
47769 +    { 0, 0, 0, 0 },
47770 +    { { MNEM, 0 } },
47771 +    & ifmt_unused_DSP_06, { 0x31c00000 }
47772 +  },
47773 +/* __unused__DSP_0f */
47774 +  {
47775 +    { 0, 0, 0, 0 },
47776 +    { { MNEM, 0 } },
47777 +    & ifmt_unused_DSP_06, { 0x31e00000 }
47778 +  },
47779 +/* __unused__DSP_14 */
47780 +  {
47781 +    { 0, 0, 0, 0 },
47782 +    { { MNEM, 0 } },
47783 +    & ifmt_unused_DSP_06, { 0x32800000 }
47784 +  },
47785 +/* __unused__DSP_15 */
47786 +  {
47787 +    { 0, 0, 0, 0 },
47788 +    { { MNEM, 0 } },
47789 +    & ifmt_unused_DSP_06, { 0x32a00000 }
47790 +  },
47791 +/* __unused__DSP_16 */
47792 +  {
47793 +    { 0, 0, 0, 0 },
47794 +    { { MNEM, 0 } },
47795 +    & ifmt_unused_DSP_06, { 0x32c00000 }
47796 +  },
47797 +/* __unused__DSP_17 */
47798 +  {
47799 +    { 0, 0, 0, 0 },
47800 +    { { MNEM, 0 } },
47801 +    & ifmt_unused_DSP_06, { 0x32e00000 }
47802 +  },
47803 +/* __unused__DSP_18 */
47804 +  {
47805 +    { 0, 0, 0, 0 },
47806 +    { { MNEM, 0 } },
47807 +    & ifmt_unused_DSP_06, { 0x33000000 }
47808 +  },
47809 +/* __unused__DSP_19 */
47810 +  {
47811 +    { 0, 0, 0, 0 },
47812 +    { { MNEM, 0 } },
47813 +    & ifmt_unused_DSP_06, { 0x33200000 }
47814 +  },
47815 +/* __unused__DSP_1a */
47816 +  {
47817 +    { 0, 0, 0, 0 },
47818 +    { { MNEM, 0 } },
47819 +    & ifmt_unused_DSP_06, { 0x33400000 }
47820 +  },
47821 +/* __unused__DSP_1b */
47822 +  {
47823 +    { 0, 0, 0, 0 },
47824 +    { { MNEM, 0 } },
47825 +    & ifmt_unused_DSP_06, { 0x33600000 }
47826 +  },
47827 +/* __unused__DSP_1c */
47828 +  {
47829 +    { 0, 0, 0, 0 },
47830 +    { { MNEM, 0 } },
47831 +    & ifmt_unused_DSP_06, { 0x33800000 }
47832 +  },
47833 +/* __unused__DSP_1d */
47834 +  {
47835 +    { 0, 0, 0, 0 },
47836 +    { { MNEM, 0 } },
47837 +    & ifmt_unused_DSP_06, { 0x33a00000 }
47838 +  },
47839 +/* __unused__DSP_1e */
47840 +  {
47841 +    { 0, 0, 0, 0 },
47842 +    { { MNEM, 0 } },
47843 +    & ifmt_unused_DSP_06, { 0x33c00000 }
47844 +  },
47845 +/* __unused__DSP_1f */
47846 +  {
47847 +    { 0, 0, 0, 0 },
47848 +    { { MNEM, 0 } },
47849 +    & ifmt_unused_DSP_06, { 0x33e00000 }
47850 +  },
47851 +};
47852 +
47853 +#undef A
47854 +#undef OPERAND
47855 +#undef MNEM
47856 +#undef OP
47857 +
47858 +/* Formats for ALIAS macro-insns.  */
47859 +
47860 +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
47861 +#define F(f) & ubicom32_cgen_ifld_table[UBICOM32_##f]
47862 +#else
47863 +#define F(f) & ubicom32_cgen_ifld_table[UBICOM32_/**/f]
47864 +#endif
47865 +static const CGEN_IFMT ifmt_nop ATTRIBUTE_UNUSED = {
47866 +  32, 32, 0xffffffff, { { F (F_OP1) }, { F (F_D) }, { F (F_IMM16_2) }, { 0 } }
47867 +};
47868 +
47869 +static const CGEN_IFMT ifmt_dsp_clracc_macro ATTRIBUTE_UNUSED = {
47870 +  32, 32, 0xfffeffff, { { F (F_OP1) }, { F (F_OPEXT) }, { F (F_DSP_DESTA) }, { F (F_S1) }, { F (F_DSP_S2_SEL) }, { F (F_BIT5) }, { F (F_DSP_T) }, { F (F_DSP_C) }, { F (F_BIT26) }, { F (F_DSP_R) }, { 0 } }
47871 +};
47872 +
47873 +#undef F
47874 +
47875 +/* Each non-simple macro entry points to an array of expansion possibilities.  */
47876 +
47877 +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
47878 +#define A(a) (1 << CGEN_INSN_##a)
47879 +#else
47880 +#define A(a) (1 << CGEN_INSN_/**/a)
47881 +#endif
47882 +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
47883 +#define OPERAND(op) UBICOM32_OPERAND_##op
47884 +#else
47885 +#define OPERAND(op) UBICOM32_OPERAND_/**/op
47886 +#endif
47887 +#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
47888 +#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
47889 +
47890 +/* The macro instruction table.  */
47891 +
47892 +static const CGEN_IBASE ubicom32_cgen_macro_insn_table[] =
47893 +{
47894 +/* nop */
47895 +  {
47896 +    -1, "nop", "nop", 32,
47897 +    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
47898 +  },
47899 +/* clracc ${dsp-destA} */
47900 +  {
47901 +    -1, "dsp-clracc-macro", "clracc", 32,
47902 +    { 0|A(ALIAS), { { { (1<<MACH_UBICOM32DSP)|(1<<MACH_UBICOM32_VER4), 0 } } } }
47903 +  },
47904 +};
47905 +
47906 +/* The macro instruction opcode table.  */
47907 +
47908 +static const CGEN_OPCODE ubicom32_cgen_macro_insn_opcode_table[] =
47909 +{
47910 +/* nop */
47911 +  {
47912 +    { 0, 0, 0, 0 },
47913 +    { { MNEM, 0 } },
47914 +    & ifmt_nop, { 0xc8000000 }
47915 +  },
47916 +/* clracc ${dsp-destA} */
47917 +  {
47918 +    { 0, 0, 0, 0 },
47919 +    { { MNEM, ' ', OP (DSP_DESTA), 0 } },
47920 +    & ifmt_dsp_clracc_macro, { 0x36400100 }
47921 +  },
47922 +};
47923 +
47924 +#undef A
47925 +#undef OPERAND
47926 +#undef MNEM
47927 +#undef OP
47928 +
47929 +#ifndef CGEN_ASM_HASH_P
47930 +#define CGEN_ASM_HASH_P(insn) 1
47931 +#endif
47932 +
47933 +#ifndef CGEN_DIS_HASH_P
47934 +#define CGEN_DIS_HASH_P(insn) 1
47935 +#endif
47936 +
47937 +/* Return non-zero if INSN is to be added to the hash table.
47938 +   Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file.  */
47939 +
47940 +static int
47941 +asm_hash_insn_p (insn)
47942 +     const CGEN_INSN *insn ATTRIBUTE_UNUSED;
47943 +{
47944 +  return CGEN_ASM_HASH_P (insn);
47945 +}
47946 +
47947 +static int
47948 +dis_hash_insn_p (insn)
47949 +     const CGEN_INSN *insn;
47950 +{
47951 +  /* If building the hash table and the NO-DIS attribute is present,
47952 +     ignore.  */
47953 +  if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_NO_DIS))
47954 +    return 0;
47955 +  return CGEN_DIS_HASH_P (insn);
47956 +}
47957 +
47958 +#ifndef CGEN_ASM_HASH
47959 +#define CGEN_ASM_HASH_SIZE 127
47960 +#ifdef CGEN_MNEMONIC_OPERANDS
47961 +#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE)
47962 +#else
47963 +#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) /*FIXME*/
47964 +#endif
47965 +#endif
47966 +
47967 +/* It doesn't make much sense to provide a default here,
47968 +   but while this is under development we do.
47969 +   BUFFER is a pointer to the bytes of the insn, target order.
47970 +   VALUE is the first base_insn_bitsize bits as an int in host order.  */
47971 +
47972 +#ifndef CGEN_DIS_HASH
47973 +#define CGEN_DIS_HASH_SIZE 256
47974 +#define CGEN_DIS_HASH(buf, value) (*(unsigned char *) (buf))
47975 +#endif
47976 +
47977 +/* The result is the hash value of the insn.
47978 +   Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file.  */
47979 +
47980 +static unsigned int
47981 +asm_hash_insn (mnem)
47982 +     const char * mnem;
47983 +{
47984 +  return CGEN_ASM_HASH (mnem);
47985 +}
47986 +
47987 +/* BUF is a pointer to the bytes of the insn, target order.
47988 +   VALUE is the first base_insn_bitsize bits as an int in host order.  */
47989 +
47990 +static unsigned int
47991 +dis_hash_insn (buf, value)
47992 +     const char * buf ATTRIBUTE_UNUSED;
47993 +     CGEN_INSN_INT value ATTRIBUTE_UNUSED;
47994 +{
47995 +  return CGEN_DIS_HASH (buf, value);
47996 +}
47997 +
47998 +/* Set the recorded length of the insn in the CGEN_FIELDS struct.  */
47999 +
48000 +static void
48001 +set_fields_bitsize (CGEN_FIELDS *fields, int size)
48002 +{
48003 +  CGEN_FIELDS_BITSIZE (fields) = size;
48004 +}
48005 +
48006 +/* Function to call before using the operand instance table.
48007 +   This plugs the opcode entries and macro instructions into the cpu table.  */
48008 +
48009 +void
48010 +ubicom32_cgen_init_opcode_table (CGEN_CPU_DESC cd)
48011 +{
48012 +  int i;
48013 +  int num_macros = (sizeof (ubicom32_cgen_macro_insn_table) /
48014 +                   sizeof (ubicom32_cgen_macro_insn_table[0]));
48015 +  const CGEN_IBASE *ib = & ubicom32_cgen_macro_insn_table[0];
48016 +  const CGEN_OPCODE *oc = & ubicom32_cgen_macro_insn_opcode_table[0];
48017 +  CGEN_INSN *insns = xmalloc (num_macros * sizeof (CGEN_INSN));
48018 +
48019 +  memset (insns, 0, num_macros * sizeof (CGEN_INSN));
48020 +  for (i = 0; i < num_macros; ++i)
48021 +    {
48022 +      insns[i].base = &ib[i];
48023 +      insns[i].opcode = &oc[i];
48024 +      ubicom32_cgen_build_insn_regex (& insns[i]);
48025 +    }
48026 +  cd->macro_insn_table.init_entries = insns;
48027 +  cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE);
48028 +  cd->macro_insn_table.num_init_entries = num_macros;
48029 +
48030 +  oc = & ubicom32_cgen_insn_opcode_table[0];
48031 +  insns = (CGEN_INSN *) cd->insn_table.init_entries;
48032 +  for (i = 0; i < MAX_INSNS; ++i)
48033 +    {
48034 +      insns[i].opcode = &oc[i];
48035 +      ubicom32_cgen_build_insn_regex (& insns[i]);
48036 +    }
48037 +
48038 +  cd->sizeof_fields = sizeof (CGEN_FIELDS);
48039 +  cd->set_fields_bitsize = set_fields_bitsize;
48040 +
48041 +  cd->asm_hash_p = asm_hash_insn_p;
48042 +  cd->asm_hash = asm_hash_insn;
48043 +  cd->asm_hash_size = CGEN_ASM_HASH_SIZE;
48044 +
48045 +  cd->dis_hash_p = dis_hash_insn_p;
48046 +  cd->dis_hash = dis_hash_insn;
48047 +  cd->dis_hash_size = CGEN_DIS_HASH_SIZE;
48048 +}
48049 --- /dev/null
48050 +++ b/opcodes/ubicom32-opc.h
48051 @@ -0,0 +1,868 @@
48052 +/* Instruction opcode header for ubicom32.
48053 +
48054 +THIS FILE IS MACHINE GENERATED WITH CGEN.
48055 +
48056 +Copyright 1996-2007 Free Software Foundation, Inc.
48057 +
48058 +This file is part of the GNU Binutils and/or GDB, the GNU debugger.
48059 +
48060 +   This file is free software; you can redistribute it and/or modify
48061 +   it under the terms of the GNU General Public License as published by
48062 +   the Free Software Foundation; either version 3, or (at your option)
48063 +   any later version.
48064 +
48065 +   It is distributed in the hope that it will be useful, but WITHOUT
48066 +   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
48067 +   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
48068 +   License for more details.
48069 +
48070 +   You should have received a copy of the GNU General Public License along
48071 +   with this program; if not, write to the Free Software Foundation, Inc.,
48072 +   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
48073 +
48074 +*/
48075 +
48076 +#ifndef UBICOM32_OPC_H
48077 +#define UBICOM32_OPC_H
48078 +
48079 +/* -- opc.h */
48080 +
48081 +/* Check applicability of instructions against machines.  */
48082 +#define CGEN_VALIDATE_INSN_SUPPORTED
48083 +extern int ubicom32_cgen_insn_supported
48084 +  PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *));
48085 +
48086 +/* Allows reason codes to be output when assembler errors occur.  */
48087 +#define CGEN_VERBOSE_ASSEMBLER_ERRORS
48088 +
48089 +/* Override disassembly hashing */
48090 +
48091 +#define CGEN_DIS_HASH_SIZE 32
48092 +#define CGEN_DIS_HASH(buf,value) ubicom32_dis_hash(buf,value)
48093 +
48094 +#define CGEN_ASM_HASH_SIZE 509
48095 +#define CGEN_ASM_HASH(insn) ubicom32_asm_hash(insn)
48096 +
48097 +extern unsigned int ubicom32_dis_hash (const char *buf, CGEN_INSN_INT value);
48098 +extern unsigned int ubicom32_asm_hash (const char *insn);
48099 +
48100 +/* Structure used to map between directly addressable registers and
48101 +   their human-readable names.  Used by both the assembler and the
48102 +   disassembler.
48103 +*/
48104 +struct ubicom32_cgen_data_space_map {
48105 +       long address;
48106 +       char *name;
48107 +        int  type;
48108 +};
48109 +
48110 +extern struct ubicom32_cgen_data_space_map ubicom32_cgen_data_space_map_mars[];
48111 +extern struct ubicom32_cgen_data_space_map ubicom32_cgen_data_space_map_mercury[];
48112 +
48113 +#define A0_ADDRESS 0x80
48114 +#define A1_ADDRESS (A0_ADDRESS + 4)
48115 +#define A2_ADDRESS (A0_ADDRESS + 8)
48116 +#define A3_ADDRESS (A0_ADDRESS + 12)
48117 +#define A4_ADDRESS (A0_ADDRESS + 16)
48118 +#define A5_ADDRESS (A0_ADDRESS + 20)
48119 +#define A6_ADDRESS (A0_ADDRESS + 24)
48120 +#define A7_ADDRESS (A0_ADDRESS + 28)
48121 +
48122 +/* XXX */
48123 +typedef unsigned char UQI;
48124 +
48125 +\f
48126 +/* -- opc.c */
48127 +/* Enum declaration for ubicom32 instruction types.  */
48128 +typedef enum cgen_insn_type {
48129 +  UBICOM32_INSN_INVALID, UBICOM32_INSN_DSP_MSUB_2_S1_DIRECT_DSP_SRC2_DATA_REG_ADDSUB2, UBICOM32_INSN_DSP_MSUB_2_S1_IMMEDIATE_DSP_SRC2_DATA_REG_ADDSUB2, UBICOM32_INSN_DSP_MSUB_2_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_DATA_REG_ADDSUB2
48130 + , UBICOM32_INSN_DSP_MSUB_2_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_DATA_REG_ADDSUB2, UBICOM32_INSN_DSP_MSUB_2_S1_INDIRECT_2_DSP_SRC2_DATA_REG_ADDSUB2, UBICOM32_INSN_DSP_MSUB_2_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_DATA_REG_ADDSUB2, UBICOM32_INSN_DSP_MSUB_2_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_DATA_REG_ADDSUB2
48131 + , UBICOM32_INSN_DSP_MSUB_2_S1_DIRECT_DSP_SRC2_REG_ACC_REG_ADDSUB, UBICOM32_INSN_DSP_MSUB_2_S1_IMMEDIATE_DSP_SRC2_REG_ACC_REG_ADDSUB, UBICOM32_INSN_DSP_MSUB_2_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_REG_ACC_REG_ADDSUB, UBICOM32_INSN_DSP_MSUB_2_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_REG_ACC_REG_ADDSUB
48132 + , UBICOM32_INSN_DSP_MSUB_2_S1_INDIRECT_2_DSP_SRC2_REG_ACC_REG_ADDSUB, UBICOM32_INSN_DSP_MSUB_2_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_REG_ACC_REG_ADDSUB, UBICOM32_INSN_DSP_MSUB_2_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_REG_ACC_REG_ADDSUB, UBICOM32_INSN_DSP_MSUB_2_S1_DIRECT_DSP_IMM_BIT5_ADDSUB2
48133 + , UBICOM32_INSN_DSP_MSUB_2_S1_IMMEDIATE_DSP_IMM_BIT5_ADDSUB2, UBICOM32_INSN_DSP_MSUB_2_S1_INDIRECT_WITH_INDEX_2_DSP_IMM_BIT5_ADDSUB2, UBICOM32_INSN_DSP_MSUB_2_S1_INDIRECT_WITH_OFFSET_2_DSP_IMM_BIT5_ADDSUB2, UBICOM32_INSN_DSP_MSUB_2_S1_INDIRECT_2_DSP_IMM_BIT5_ADDSUB2
48134 + , UBICOM32_INSN_DSP_MSUB_2_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_IMM_BIT5_ADDSUB2, UBICOM32_INSN_DSP_MSUB_2_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_IMM_BIT5_ADDSUB2, UBICOM32_INSN_DSP_MSUB_4_S1_DIRECT_DSP_SRC2_DATA_REG_ADDSUB, UBICOM32_INSN_DSP_MSUB_4_S1_IMMEDIATE_DSP_SRC2_DATA_REG_ADDSUB
48135 + , UBICOM32_INSN_DSP_MSUB_4_S1_INDIRECT_WITH_INDEX_4_DSP_SRC2_DATA_REG_ADDSUB, UBICOM32_INSN_DSP_MSUB_4_S1_INDIRECT_WITH_OFFSET_4_DSP_SRC2_DATA_REG_ADDSUB, UBICOM32_INSN_DSP_MSUB_4_S1_INDIRECT_4_DSP_SRC2_DATA_REG_ADDSUB, UBICOM32_INSN_DSP_MSUB_4_S1_INDIRECT_WITH_POST_INCREMENT_4_DSP_SRC2_DATA_REG_ADDSUB
48136 + , UBICOM32_INSN_DSP_MSUB_4_S1_INDIRECT_WITH_PRE_INCREMENT_4_DSP_SRC2_DATA_REG_ADDSUB, UBICOM32_INSN_DSP_MSUB_4_S1_DIRECT_DSP_SRC2_REG_ACC_REG_ADDSUB, UBICOM32_INSN_DSP_MSUB_4_S1_IMMEDIATE_DSP_SRC2_REG_ACC_REG_ADDSUB, UBICOM32_INSN_DSP_MSUB_4_S1_INDIRECT_WITH_INDEX_4_DSP_SRC2_REG_ACC_REG_ADDSUB
48137 + , UBICOM32_INSN_DSP_MSUB_4_S1_INDIRECT_WITH_OFFSET_4_DSP_SRC2_REG_ACC_REG_ADDSUB, UBICOM32_INSN_DSP_MSUB_4_S1_INDIRECT_4_DSP_SRC2_REG_ACC_REG_ADDSUB, UBICOM32_INSN_DSP_MSUB_4_S1_INDIRECT_WITH_POST_INCREMENT_4_DSP_SRC2_REG_ACC_REG_ADDSUB, UBICOM32_INSN_DSP_MSUB_4_S1_INDIRECT_WITH_PRE_INCREMENT_4_DSP_SRC2_REG_ACC_REG_ADDSUB
48138 + , UBICOM32_INSN_DSP_MSUB_4_S1_DIRECT_DSP_IMM_BIT5_ADDSUB, UBICOM32_INSN_DSP_MSUB_4_S1_IMMEDIATE_DSP_IMM_BIT5_ADDSUB, UBICOM32_INSN_DSP_MSUB_4_S1_INDIRECT_WITH_INDEX_4_DSP_IMM_BIT5_ADDSUB, UBICOM32_INSN_DSP_MSUB_4_S1_INDIRECT_WITH_OFFSET_4_DSP_IMM_BIT5_ADDSUB
48139 + , UBICOM32_INSN_DSP_MSUB_4_S1_INDIRECT_4_DSP_IMM_BIT5_ADDSUB, UBICOM32_INSN_DSP_MSUB_4_S1_INDIRECT_WITH_POST_INCREMENT_4_DSP_IMM_BIT5_ADDSUB, UBICOM32_INSN_DSP_MSUB_4_S1_INDIRECT_WITH_PRE_INCREMENT_4_DSP_IMM_BIT5_ADDSUB, UBICOM32_INSN_DSP_MADD_2_S1_DIRECT_DSP_SRC2_DATA_REG_ADDSUB2
48140 + , UBICOM32_INSN_DSP_MADD_2_S1_IMMEDIATE_DSP_SRC2_DATA_REG_ADDSUB2, UBICOM32_INSN_DSP_MADD_2_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_DATA_REG_ADDSUB2, UBICOM32_INSN_DSP_MADD_2_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_DATA_REG_ADDSUB2, UBICOM32_INSN_DSP_MADD_2_S1_INDIRECT_2_DSP_SRC2_DATA_REG_ADDSUB2
48141 + , UBICOM32_INSN_DSP_MADD_2_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_DATA_REG_ADDSUB2, UBICOM32_INSN_DSP_MADD_2_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_DATA_REG_ADDSUB2, UBICOM32_INSN_DSP_MADD_2_S1_DIRECT_DSP_SRC2_REG_ACC_REG_ADDSUB, UBICOM32_INSN_DSP_MADD_2_S1_IMMEDIATE_DSP_SRC2_REG_ACC_REG_ADDSUB
48142 + , UBICOM32_INSN_DSP_MADD_2_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_REG_ACC_REG_ADDSUB, UBICOM32_INSN_DSP_MADD_2_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_REG_ACC_REG_ADDSUB, UBICOM32_INSN_DSP_MADD_2_S1_INDIRECT_2_DSP_SRC2_REG_ACC_REG_ADDSUB, UBICOM32_INSN_DSP_MADD_2_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_REG_ACC_REG_ADDSUB
48143 + , UBICOM32_INSN_DSP_MADD_2_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_REG_ACC_REG_ADDSUB, UBICOM32_INSN_DSP_MADD_2_S1_DIRECT_DSP_IMM_BIT5_ADDSUB2, UBICOM32_INSN_DSP_MADD_2_S1_IMMEDIATE_DSP_IMM_BIT5_ADDSUB2, UBICOM32_INSN_DSP_MADD_2_S1_INDIRECT_WITH_INDEX_2_DSP_IMM_BIT5_ADDSUB2
48144 + , UBICOM32_INSN_DSP_MADD_2_S1_INDIRECT_WITH_OFFSET_2_DSP_IMM_BIT5_ADDSUB2, UBICOM32_INSN_DSP_MADD_2_S1_INDIRECT_2_DSP_IMM_BIT5_ADDSUB2, UBICOM32_INSN_DSP_MADD_2_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_IMM_BIT5_ADDSUB2, UBICOM32_INSN_DSP_MADD_2_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_IMM_BIT5_ADDSUB2
48145 + , UBICOM32_INSN_DSP_MADD_4_S1_DIRECT_DSP_SRC2_DATA_REG_ADDSUB, UBICOM32_INSN_DSP_MADD_4_S1_IMMEDIATE_DSP_SRC2_DATA_REG_ADDSUB, UBICOM32_INSN_DSP_MADD_4_S1_INDIRECT_WITH_INDEX_4_DSP_SRC2_DATA_REG_ADDSUB, UBICOM32_INSN_DSP_MADD_4_S1_INDIRECT_WITH_OFFSET_4_DSP_SRC2_DATA_REG_ADDSUB
48146 + , UBICOM32_INSN_DSP_MADD_4_S1_INDIRECT_4_DSP_SRC2_DATA_REG_ADDSUB, UBICOM32_INSN_DSP_MADD_4_S1_INDIRECT_WITH_POST_INCREMENT_4_DSP_SRC2_DATA_REG_ADDSUB, UBICOM32_INSN_DSP_MADD_4_S1_INDIRECT_WITH_PRE_INCREMENT_4_DSP_SRC2_DATA_REG_ADDSUB, UBICOM32_INSN_DSP_MADD_4_S1_DIRECT_DSP_SRC2_REG_ACC_REG_ADDSUB
48147 + , UBICOM32_INSN_DSP_MADD_4_S1_IMMEDIATE_DSP_SRC2_REG_ACC_REG_ADDSUB, UBICOM32_INSN_DSP_MADD_4_S1_INDIRECT_WITH_INDEX_4_DSP_SRC2_REG_ACC_REG_ADDSUB, UBICOM32_INSN_DSP_MADD_4_S1_INDIRECT_WITH_OFFSET_4_DSP_SRC2_REG_ACC_REG_ADDSUB, UBICOM32_INSN_DSP_MADD_4_S1_INDIRECT_4_DSP_SRC2_REG_ACC_REG_ADDSUB
48148 + , UBICOM32_INSN_DSP_MADD_4_S1_INDIRECT_WITH_POST_INCREMENT_4_DSP_SRC2_REG_ACC_REG_ADDSUB, UBICOM32_INSN_DSP_MADD_4_S1_INDIRECT_WITH_PRE_INCREMENT_4_DSP_SRC2_REG_ACC_REG_ADDSUB, UBICOM32_INSN_DSP_MADD_4_S1_DIRECT_DSP_IMM_BIT5_ADDSUB, UBICOM32_INSN_DSP_MADD_4_S1_IMMEDIATE_DSP_IMM_BIT5_ADDSUB
48149 + , UBICOM32_INSN_DSP_MADD_4_S1_INDIRECT_WITH_INDEX_4_DSP_IMM_BIT5_ADDSUB, UBICOM32_INSN_DSP_MADD_4_S1_INDIRECT_WITH_OFFSET_4_DSP_IMM_BIT5_ADDSUB, UBICOM32_INSN_DSP_MADD_4_S1_INDIRECT_4_DSP_IMM_BIT5_ADDSUB, UBICOM32_INSN_DSP_MADD_4_S1_INDIRECT_WITH_POST_INCREMENT_4_DSP_IMM_BIT5_ADDSUB
48150 + , UBICOM32_INSN_DSP_MADD_4_S1_INDIRECT_WITH_PRE_INCREMENT_4_DSP_IMM_BIT5_ADDSUB, UBICOM32_INSN_DSP_MSUF_S1_DIRECT_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MSUF_S1_IMMEDIATE_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MSUF_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_DATA_REG
48151 + , UBICOM32_INSN_DSP_MSUF_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MSUF_S1_INDIRECT_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MSUF_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MSUF_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_DATA_REG
48152 + , UBICOM32_INSN_DSP_MSUF_S1_DIRECT_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MSUF_S1_IMMEDIATE_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MSUF_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MSUF_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_REG_ACC_REG_MUL
48153 + , UBICOM32_INSN_DSP_MSUF_S1_INDIRECT_2_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MSUF_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MSUF_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MSUF_S1_DIRECT_DSP_IMM_BIT5
48154 + , UBICOM32_INSN_DSP_MSUF_S1_IMMEDIATE_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MSUF_S1_INDIRECT_WITH_INDEX_2_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MSUF_S1_INDIRECT_WITH_OFFSET_2_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MSUF_S1_INDIRECT_2_DSP_IMM_BIT5
48155 + , UBICOM32_INSN_DSP_MSUF_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MSUF_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MACUS_S1_DIRECT_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MACUS_S1_IMMEDIATE_DSP_SRC2_DATA_REG
48156 + , UBICOM32_INSN_DSP_MACUS_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MACUS_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MACUS_S1_INDIRECT_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MACUS_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_DATA_REG
48157 + , UBICOM32_INSN_DSP_MACUS_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MACUS_S1_DIRECT_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MACUS_S1_IMMEDIATE_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MACUS_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_REG_ACC_REG_MUL
48158 + , UBICOM32_INSN_DSP_MACUS_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MACUS_S1_INDIRECT_2_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MACUS_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MACUS_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_REG_ACC_REG_MUL
48159 + , UBICOM32_INSN_DSP_MACUS_S1_DIRECT_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MACUS_S1_IMMEDIATE_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MACUS_S1_INDIRECT_WITH_INDEX_2_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MACUS_S1_INDIRECT_WITH_OFFSET_2_DSP_IMM_BIT5
48160 + , UBICOM32_INSN_DSP_MACUS_S1_INDIRECT_2_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MACUS_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MACUS_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MACF_S1_DIRECT_DSP_SRC2_DATA_REG
48161 + , UBICOM32_INSN_DSP_MACF_S1_IMMEDIATE_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MACF_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MACF_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MACF_S1_INDIRECT_2_DSP_SRC2_DATA_REG
48162 + , UBICOM32_INSN_DSP_MACF_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MACF_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MACF_S1_DIRECT_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MACF_S1_IMMEDIATE_DSP_SRC2_REG_ACC_REG_MUL
48163 + , UBICOM32_INSN_DSP_MACF_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MACF_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MACF_S1_INDIRECT_2_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MACF_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_REG_ACC_REG_MUL
48164 + , UBICOM32_INSN_DSP_MACF_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MACF_S1_DIRECT_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MACF_S1_IMMEDIATE_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MACF_S1_INDIRECT_WITH_INDEX_2_DSP_IMM_BIT5
48165 + , UBICOM32_INSN_DSP_MACF_S1_INDIRECT_WITH_OFFSET_2_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MACF_S1_INDIRECT_2_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MACF_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MACF_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_IMM_BIT5
48166 + , UBICOM32_INSN_DSP_MULF_S1_DIRECT_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MULF_S1_IMMEDIATE_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MULF_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MULF_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_DATA_REG
48167 + , UBICOM32_INSN_DSP_MULF_S1_INDIRECT_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MULF_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MULF_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MULF_S1_DIRECT_DSP_SRC2_REG_ACC_REG_MUL
48168 + , UBICOM32_INSN_DSP_MULF_S1_IMMEDIATE_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MULF_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MULF_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MULF_S1_INDIRECT_2_DSP_SRC2_REG_ACC_REG_MUL
48169 + , UBICOM32_INSN_DSP_MULF_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MULF_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MULF_S1_DIRECT_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MULF_S1_IMMEDIATE_DSP_IMM_BIT5
48170 + , UBICOM32_INSN_DSP_MULF_S1_INDIRECT_WITH_INDEX_2_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MULF_S1_INDIRECT_WITH_OFFSET_2_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MULF_S1_INDIRECT_2_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MULF_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_IMM_BIT5
48171 + , UBICOM32_INSN_DSP_MULF_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MACU_S1_DIRECT_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MACU_S1_IMMEDIATE_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MACU_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_DATA_REG
48172 + , UBICOM32_INSN_DSP_MACU_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MACU_S1_INDIRECT_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MACU_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MACU_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_DATA_REG
48173 + , UBICOM32_INSN_DSP_MACU_S1_DIRECT_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MACU_S1_IMMEDIATE_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MACU_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MACU_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_REG_ACC_REG_MUL
48174 + , UBICOM32_INSN_DSP_MACU_S1_INDIRECT_2_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MACU_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MACU_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MACU_S1_DIRECT_DSP_IMM_BIT5
48175 + , UBICOM32_INSN_DSP_MACU_S1_IMMEDIATE_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MACU_S1_INDIRECT_WITH_INDEX_2_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MACU_S1_INDIRECT_WITH_OFFSET_2_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MACU_S1_INDIRECT_2_DSP_IMM_BIT5
48176 + , UBICOM32_INSN_DSP_MACU_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MACU_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MULU_4_S1_DIRECT_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MULU_4_S1_IMMEDIATE_DSP_SRC2_DATA_REG
48177 + , UBICOM32_INSN_DSP_MULU_4_S1_INDIRECT_WITH_INDEX_4_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MULU_4_S1_INDIRECT_WITH_OFFSET_4_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MULU_4_S1_INDIRECT_4_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MULU_4_S1_INDIRECT_WITH_POST_INCREMENT_4_DSP_SRC2_DATA_REG
48178 + , UBICOM32_INSN_DSP_MULU_4_S1_INDIRECT_WITH_PRE_INCREMENT_4_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MULU_4_S1_DIRECT_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MULU_4_S1_IMMEDIATE_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MULU_4_S1_INDIRECT_WITH_INDEX_4_DSP_SRC2_REG_ACC_REG_MUL
48179 + , UBICOM32_INSN_DSP_MULU_4_S1_INDIRECT_WITH_OFFSET_4_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MULU_4_S1_INDIRECT_4_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MULU_4_S1_INDIRECT_WITH_POST_INCREMENT_4_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MULU_4_S1_INDIRECT_WITH_PRE_INCREMENT_4_DSP_SRC2_REG_ACC_REG_MUL
48180 + , UBICOM32_INSN_DSP_MULU_4_S1_DIRECT_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MULU_4_S1_IMMEDIATE_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MULU_4_S1_INDIRECT_WITH_INDEX_4_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MULU_4_S1_INDIRECT_WITH_OFFSET_4_DSP_IMM_BIT5
48181 + , UBICOM32_INSN_DSP_MULU_4_S1_INDIRECT_4_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MULU_4_S1_INDIRECT_WITH_POST_INCREMENT_4_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MULU_4_S1_INDIRECT_WITH_PRE_INCREMENT_4_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MULU_S1_DIRECT_DSP_SRC2_DATA_REG
48182 + , UBICOM32_INSN_DSP_MULU_S1_IMMEDIATE_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MULU_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MULU_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MULU_S1_INDIRECT_2_DSP_SRC2_DATA_REG
48183 + , UBICOM32_INSN_DSP_MULU_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MULU_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MULU_S1_DIRECT_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MULU_S1_IMMEDIATE_DSP_SRC2_REG_ACC_REG_MUL
48184 + , UBICOM32_INSN_DSP_MULU_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MULU_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MULU_S1_INDIRECT_2_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MULU_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_REG_ACC_REG_MUL
48185 + , UBICOM32_INSN_DSP_MULU_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MULU_S1_DIRECT_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MULU_S1_IMMEDIATE_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MULU_S1_INDIRECT_WITH_INDEX_2_DSP_IMM_BIT5
48186 + , UBICOM32_INSN_DSP_MULU_S1_INDIRECT_WITH_OFFSET_2_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MULU_S1_INDIRECT_2_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MULU_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MULU_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_IMM_BIT5
48187 + , UBICOM32_INSN_DSP_MACS_S1_DIRECT_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MACS_S1_IMMEDIATE_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MACS_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MACS_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_DATA_REG
48188 + , UBICOM32_INSN_DSP_MACS_S1_INDIRECT_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MACS_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MACS_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MACS_S1_DIRECT_DSP_SRC2_REG_ACC_REG_MUL
48189 + , UBICOM32_INSN_DSP_MACS_S1_IMMEDIATE_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MACS_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MACS_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MACS_S1_INDIRECT_2_DSP_SRC2_REG_ACC_REG_MUL
48190 + , UBICOM32_INSN_DSP_MACS_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MACS_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MACS_S1_DIRECT_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MACS_S1_IMMEDIATE_DSP_IMM_BIT5
48191 + , UBICOM32_INSN_DSP_MACS_S1_INDIRECT_WITH_INDEX_2_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MACS_S1_INDIRECT_WITH_OFFSET_2_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MACS_S1_INDIRECT_2_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MACS_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_IMM_BIT5
48192 + , UBICOM32_INSN_DSP_MACS_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MULS_4_S1_DIRECT_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MULS_4_S1_IMMEDIATE_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MULS_4_S1_INDIRECT_WITH_INDEX_4_DSP_SRC2_DATA_REG
48193 + , UBICOM32_INSN_DSP_MULS_4_S1_INDIRECT_WITH_OFFSET_4_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MULS_4_S1_INDIRECT_4_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MULS_4_S1_INDIRECT_WITH_POST_INCREMENT_4_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MULS_4_S1_INDIRECT_WITH_PRE_INCREMENT_4_DSP_SRC2_DATA_REG
48194 + , UBICOM32_INSN_DSP_MULS_4_S1_DIRECT_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MULS_4_S1_IMMEDIATE_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MULS_4_S1_INDIRECT_WITH_INDEX_4_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MULS_4_S1_INDIRECT_WITH_OFFSET_4_DSP_SRC2_REG_ACC_REG_MUL
48195 + , UBICOM32_INSN_DSP_MULS_4_S1_INDIRECT_4_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MULS_4_S1_INDIRECT_WITH_POST_INCREMENT_4_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MULS_4_S1_INDIRECT_WITH_PRE_INCREMENT_4_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MULS_4_S1_DIRECT_DSP_IMM_BIT5
48196 + , UBICOM32_INSN_DSP_MULS_4_S1_IMMEDIATE_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MULS_4_S1_INDIRECT_WITH_INDEX_4_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MULS_4_S1_INDIRECT_WITH_OFFSET_4_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MULS_4_S1_INDIRECT_4_DSP_IMM_BIT5
48197 + , UBICOM32_INSN_DSP_MULS_4_S1_INDIRECT_WITH_POST_INCREMENT_4_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MULS_4_S1_INDIRECT_WITH_PRE_INCREMENT_4_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MULS_S1_DIRECT_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MULS_S1_IMMEDIATE_DSP_SRC2_DATA_REG
48198 + , UBICOM32_INSN_DSP_MULS_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MULS_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MULS_S1_INDIRECT_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MULS_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_DATA_REG
48199 + , UBICOM32_INSN_DSP_MULS_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_DSP_MULS_S1_DIRECT_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MULS_S1_IMMEDIATE_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MULS_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_REG_ACC_REG_MUL
48200 + , UBICOM32_INSN_DSP_MULS_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MULS_S1_INDIRECT_2_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MULS_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_REG_ACC_REG_MUL, UBICOM32_INSN_DSP_MULS_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_REG_ACC_REG_MUL
48201 + , UBICOM32_INSN_DSP_MULS_S1_DIRECT_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MULS_S1_IMMEDIATE_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MULS_S1_INDIRECT_WITH_INDEX_2_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MULS_S1_INDIRECT_WITH_OFFSET_2_DSP_IMM_BIT5
48202 + , UBICOM32_INSN_DSP_MULS_S1_INDIRECT_2_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MULS_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_IMM_BIT5, UBICOM32_INSN_DSP_MULS_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_IMM_BIT5, UBICOM32_INSN_IERASE_D_PEA_INDIRECT_WITH_INDEX
48203 + , UBICOM32_INSN_IERASE_D_PEA_INDIRECT_WITH_OFFSET, UBICOM32_INSN_IERASE_D_PEA_INDIRECT, UBICOM32_INSN_IERASE_D_PEA_INDIRECT_WITH_POST_INCREMENT, UBICOM32_INSN_IERASE_D_PEA_INDIRECT_WITH_PRE_INCREMENT
48204 + , UBICOM32_INSN_IREAD_S1_EA_INDIRECT, UBICOM32_INSN_IREAD_S1_EA_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_IREAD_S1_EA_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_IREAD_S1_EA_INDIRECT_WITH_PRE_INCREMENT_4
48205 + , UBICOM32_INSN_IREAD_S1_EA_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_INDEX_S1_DIRECT, UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_OFFSET_S1_DIRECT, UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_S1_DIRECT
48206 + , UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_POST_INCREMENT_S1_DIRECT, UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_PRE_INCREMENT_S1_DIRECT, UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_INDEX_S1_IMMEDIATE, UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_OFFSET_S1_IMMEDIATE
48207 + , UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_S1_IMMEDIATE, UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_POST_INCREMENT_S1_IMMEDIATE, UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_PRE_INCREMENT_S1_IMMEDIATE, UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_INDEX_S1_INDIRECT_WITH_INDEX_4
48208 + , UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_OFFSET_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_POST_INCREMENT_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_PRE_INCREMENT_S1_INDIRECT_WITH_INDEX_4
48209 + , UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_INDEX_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_OFFSET_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_POST_INCREMENT_S1_INDIRECT_WITH_OFFSET_4
48210 + , UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_PRE_INCREMENT_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_INDEX_S1_INDIRECT_4, UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_OFFSET_S1_INDIRECT_4, UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_S1_INDIRECT_4
48211 + , UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_POST_INCREMENT_S1_INDIRECT_4, UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_PRE_INCREMENT_S1_INDIRECT_4, UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_INDEX_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_OFFSET_S1_INDIRECT_WITH_POST_INCREMENT_4
48212 + , UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_POST_INCREMENT_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_PRE_INCREMENT_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_INDEX_S1_INDIRECT_WITH_PRE_INCREMENT_4
48213 + , UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_OFFSET_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_POST_INCREMENT_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_IWRITE_D_PEA_INDIRECT_WITH_PRE_INCREMENT_S1_INDIRECT_WITH_PRE_INCREMENT_4
48214 + , UBICOM32_INSN_SETCSR_S1_DIRECT, UBICOM32_INSN_SETCSR_S1_IMMEDIATE, UBICOM32_INSN_SETCSR_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_SETCSR_S1_INDIRECT_WITH_OFFSET_4
48215 + , UBICOM32_INSN_SETCSR_S1_INDIRECT_4, UBICOM32_INSN_SETCSR_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_SETCSR_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_BKPT_S1_DIRECT
48216 + , UBICOM32_INSN_BKPT_S1_IMMEDIATE, UBICOM32_INSN_BKPT_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_BKPT_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_BKPT_S1_INDIRECT_4
48217 + , UBICOM32_INSN_BKPT_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_BKPT_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_RET_S1_DIRECT, UBICOM32_INSN_RET_S1_IMMEDIATE
48218 + , UBICOM32_INSN_RET_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_RET_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_RET_S1_INDIRECT_4, UBICOM32_INSN_RET_S1_INDIRECT_WITH_POST_INCREMENT_4
48219 + , UBICOM32_INSN_RET_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_MOVEA_D_DIRECT_S1_DIRECT, UBICOM32_INSN_MOVEA_D_IMMEDIATE_4_S1_DIRECT, UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_INDEX_4_S1_DIRECT
48220 + , UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_OFFSET_4_S1_DIRECT, UBICOM32_INSN_MOVEA_D_INDIRECT_4_S1_DIRECT, UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_POST_INCREMENT_4_S1_DIRECT, UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_DIRECT
48221 + , UBICOM32_INSN_MOVEA_D_DIRECT_S1_IMMEDIATE, UBICOM32_INSN_MOVEA_D_IMMEDIATE_4_S1_IMMEDIATE, UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_INDEX_4_S1_IMMEDIATE, UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_OFFSET_4_S1_IMMEDIATE
48222 + , UBICOM32_INSN_MOVEA_D_INDIRECT_4_S1_IMMEDIATE, UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_POST_INCREMENT_4_S1_IMMEDIATE, UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_IMMEDIATE, UBICOM32_INSN_MOVEA_D_DIRECT_S1_INDIRECT_WITH_INDEX_4
48223 + , UBICOM32_INSN_MOVEA_D_IMMEDIATE_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_MOVEA_D_INDIRECT_4_S1_INDIRECT_WITH_INDEX_4
48224 + , UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_MOVEA_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_MOVEA_D_IMMEDIATE_4_S1_INDIRECT_WITH_OFFSET_4
48225 + , UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_MOVEA_D_INDIRECT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4
48226 + , UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_MOVEA_D_DIRECT_S1_INDIRECT_4, UBICOM32_INSN_MOVEA_D_IMMEDIATE_4_S1_INDIRECT_4, UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_4
48227 + , UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_4, UBICOM32_INSN_MOVEA_D_INDIRECT_4_S1_INDIRECT_4, UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_4, UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_4
48228 + , UBICOM32_INSN_MOVEA_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_MOVEA_D_IMMEDIATE_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_POST_INCREMENT_4
48229 + , UBICOM32_INSN_MOVEA_D_INDIRECT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_MOVEA_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4
48230 + , UBICOM32_INSN_MOVEA_D_IMMEDIATE_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_MOVEA_D_INDIRECT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4
48231 + , UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_MOVEA_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_MOVE_4_D_DIRECT_S1_DIRECT, UBICOM32_INSN_MOVE_4_D_IMMEDIATE_4_S1_DIRECT
48232 + , UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_INDEX_4_S1_DIRECT, UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_OFFSET_4_S1_DIRECT, UBICOM32_INSN_MOVE_4_D_INDIRECT_4_S1_DIRECT, UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_DIRECT
48233 + , UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_DIRECT, UBICOM32_INSN_MOVE_4_D_DIRECT_S1_IMMEDIATE, UBICOM32_INSN_MOVE_4_D_IMMEDIATE_4_S1_IMMEDIATE, UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_INDEX_4_S1_IMMEDIATE
48234 + , UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_OFFSET_4_S1_IMMEDIATE, UBICOM32_INSN_MOVE_4_D_INDIRECT_4_S1_IMMEDIATE, UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_IMMEDIATE, UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_IMMEDIATE
48235 + , UBICOM32_INSN_MOVE_4_D_DIRECT_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_MOVE_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_INDEX_4
48236 + , UBICOM32_INSN_MOVE_4_D_INDIRECT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_MOVE_4_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4
48237 + , UBICOM32_INSN_MOVE_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_MOVE_4_D_INDIRECT_4_S1_INDIRECT_WITH_OFFSET_4
48238 + , UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_MOVE_4_D_DIRECT_S1_INDIRECT_4, UBICOM32_INSN_MOVE_4_D_IMMEDIATE_4_S1_INDIRECT_4
48239 + , UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_4, UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_4, UBICOM32_INSN_MOVE_4_D_INDIRECT_4_S1_INDIRECT_4, UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_4
48240 + , UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_4, UBICOM32_INSN_MOVE_4_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_MOVE_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_POST_INCREMENT_4
48241 + , UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_MOVE_4_D_INDIRECT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4
48242 + , UBICOM32_INSN_MOVE_4_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_MOVE_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_PRE_INCREMENT_4
48243 + , UBICOM32_INSN_MOVE_4_D_INDIRECT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_MOVE_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_COMPATIBILITY_IREAD_S1_EA_INDIRECT
48244 + , UBICOM32_INSN_COMPATIBILITY_IREAD_S1_EA_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_COMPATIBILITY_IREAD_S1_EA_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_COMPATIBILITY_IREAD_S1_EA_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_COMPATIBILITY_IREAD_S1_EA_INDIRECT_WITH_OFFSET_4
48245 + , UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_INDEX_S1_DIRECT, UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_OFFSET_S1_DIRECT, UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_S1_DIRECT, UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_POST_INCREMENT_S1_DIRECT
48246 + , UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_PRE_INCREMENT_S1_DIRECT, UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_INDEX_S1_IMMEDIATE, UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_OFFSET_S1_IMMEDIATE, UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_S1_IMMEDIATE
48247 + , UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_POST_INCREMENT_S1_IMMEDIATE, UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_PRE_INCREMENT_S1_IMMEDIATE, UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_INDEX_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_OFFSET_S1_INDIRECT_WITH_INDEX_4
48248 + , UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_POST_INCREMENT_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_PRE_INCREMENT_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_INDEX_S1_INDIRECT_WITH_OFFSET_4
48249 + , UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_OFFSET_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_POST_INCREMENT_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_PRE_INCREMENT_S1_INDIRECT_WITH_OFFSET_4
48250 + , UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_INDEX_S1_INDIRECT_4, UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_OFFSET_S1_INDIRECT_4, UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_S1_INDIRECT_4, UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_POST_INCREMENT_S1_INDIRECT_4
48251 + , UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_PRE_INCREMENT_S1_INDIRECT_4, UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_INDEX_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_OFFSET_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4
48252 + , UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_POST_INCREMENT_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_PRE_INCREMENT_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_INDEX_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_OFFSET_S1_INDIRECT_WITH_PRE_INCREMENT_4
48253 + , UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_POST_INCREMENT_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_COMPATIBILITY_IWRITE_D_PEA_INDIRECT_WITH_PRE_INCREMENT_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_MOVE_2_D_DIRECT_S1_DIRECT
48254 + , UBICOM32_INSN_MOVE_2_D_IMMEDIATE_2_S1_DIRECT, UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_INDEX_2_S1_DIRECT, UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_OFFSET_2_S1_DIRECT, UBICOM32_INSN_MOVE_2_D_INDIRECT_2_S1_DIRECT
48255 + , UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_DIRECT, UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_DIRECT, UBICOM32_INSN_MOVE_2_D_DIRECT_S1_IMMEDIATE, UBICOM32_INSN_MOVE_2_D_IMMEDIATE_2_S1_IMMEDIATE
48256 + , UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_INDEX_2_S1_IMMEDIATE, UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_OFFSET_2_S1_IMMEDIATE, UBICOM32_INSN_MOVE_2_D_INDIRECT_2_S1_IMMEDIATE, UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_IMMEDIATE
48257 + , UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_IMMEDIATE, UBICOM32_INSN_MOVE_2_D_DIRECT_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_MOVE_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_INDEX_2
48258 + , UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_MOVE_2_D_INDIRECT_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_INDEX_2
48259 + , UBICOM32_INSN_MOVE_2_D_DIRECT_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_MOVE_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_OFFSET_2
48260 + , UBICOM32_INSN_MOVE_2_D_INDIRECT_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_MOVE_2_D_DIRECT_S1_INDIRECT_2
48261 + , UBICOM32_INSN_MOVE_2_D_IMMEDIATE_2_S1_INDIRECT_2, UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_2, UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_2, UBICOM32_INSN_MOVE_2_D_INDIRECT_2_S1_INDIRECT_2
48262 + , UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_2, UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_2, UBICOM32_INSN_MOVE_2_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_MOVE_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_POST_INCREMENT_2
48263 + , UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_MOVE_2_D_INDIRECT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_2
48264 + , UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_MOVE_2_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_MOVE_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_PRE_INCREMENT_2
48265 + , UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_MOVE_2_D_INDIRECT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_MOVE_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2
48266 + , UBICOM32_INSN_MOVE_1_D_DIRECT_S1_DIRECT, UBICOM32_INSN_MOVE_1_D_IMMEDIATE_1_S1_DIRECT, UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_INDEX_1_S1_DIRECT, UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_OFFSET_1_S1_DIRECT
48267 + , UBICOM32_INSN_MOVE_1_D_INDIRECT_1_S1_DIRECT, UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_DIRECT, UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_DIRECT, UBICOM32_INSN_MOVE_1_D_DIRECT_S1_IMMEDIATE
48268 + , UBICOM32_INSN_MOVE_1_D_IMMEDIATE_1_S1_IMMEDIATE, UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_INDEX_1_S1_IMMEDIATE, UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_OFFSET_1_S1_IMMEDIATE, UBICOM32_INSN_MOVE_1_D_INDIRECT_1_S1_IMMEDIATE
48269 + , UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_IMMEDIATE, UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_IMMEDIATE, UBICOM32_INSN_MOVE_1_D_DIRECT_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_MOVE_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_INDEX_1
48270 + , UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_MOVE_1_D_INDIRECT_1_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_INDEX_1
48271 + , UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_MOVE_1_D_DIRECT_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_MOVE_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_OFFSET_1
48272 + , UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_MOVE_1_D_INDIRECT_1_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_OFFSET_1
48273 + , UBICOM32_INSN_MOVE_1_D_DIRECT_S1_INDIRECT_1, UBICOM32_INSN_MOVE_1_D_IMMEDIATE_1_S1_INDIRECT_1, UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_1, UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_1
48274 + , UBICOM32_INSN_MOVE_1_D_INDIRECT_1_S1_INDIRECT_1, UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_1, UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_1, UBICOM32_INSN_MOVE_1_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_1
48275 + , UBICOM32_INSN_MOVE_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_MOVE_1_D_INDIRECT_1_S1_INDIRECT_WITH_POST_INCREMENT_1
48276 + , UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_MOVE_1_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_MOVE_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_PRE_INCREMENT_1
48277 + , UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_MOVE_1_D_INDIRECT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1
48278 + , UBICOM32_INSN_MOVE_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_EXT_2_D_DIRECT_S1_DIRECT, UBICOM32_INSN_EXT_2_D_IMMEDIATE_2_S1_DIRECT, UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_INDEX_2_S1_DIRECT
48279 + , UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_OFFSET_2_S1_DIRECT, UBICOM32_INSN_EXT_2_D_INDIRECT_2_S1_DIRECT, UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_DIRECT, UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_DIRECT
48280 + , UBICOM32_INSN_EXT_2_D_DIRECT_S1_IMMEDIATE, UBICOM32_INSN_EXT_2_D_IMMEDIATE_2_S1_IMMEDIATE, UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_INDEX_2_S1_IMMEDIATE, UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_OFFSET_2_S1_IMMEDIATE
48281 + , UBICOM32_INSN_EXT_2_D_INDIRECT_2_S1_IMMEDIATE, UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_IMMEDIATE, UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_IMMEDIATE, UBICOM32_INSN_EXT_2_D_DIRECT_S1_INDIRECT_WITH_INDEX_2
48282 + , UBICOM32_INSN_EXT_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_EXT_2_D_INDIRECT_2_S1_INDIRECT_WITH_INDEX_2
48283 + , UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_EXT_2_D_DIRECT_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_EXT_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_OFFSET_2
48284 + , UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_EXT_2_D_INDIRECT_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_2
48285 + , UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_EXT_2_D_DIRECT_S1_INDIRECT_2, UBICOM32_INSN_EXT_2_D_IMMEDIATE_2_S1_INDIRECT_2, UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_2
48286 + , UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_2, UBICOM32_INSN_EXT_2_D_INDIRECT_2_S1_INDIRECT_2, UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_2, UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_2
48287 + , UBICOM32_INSN_EXT_2_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_EXT_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_POST_INCREMENT_2
48288 + , UBICOM32_INSN_EXT_2_D_INDIRECT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_EXT_2_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_2
48289 + , UBICOM32_INSN_EXT_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_EXT_2_D_INDIRECT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2
48290 + , UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_EXT_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_EXT_1_D_DIRECT_S1_DIRECT, UBICOM32_INSN_EXT_1_D_IMMEDIATE_1_S1_DIRECT
48291 + , UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_INDEX_1_S1_DIRECT, UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_OFFSET_1_S1_DIRECT, UBICOM32_INSN_EXT_1_D_INDIRECT_1_S1_DIRECT, UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_DIRECT
48292 + , UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_DIRECT, UBICOM32_INSN_EXT_1_D_DIRECT_S1_IMMEDIATE, UBICOM32_INSN_EXT_1_D_IMMEDIATE_1_S1_IMMEDIATE, UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_INDEX_1_S1_IMMEDIATE
48293 + , UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_OFFSET_1_S1_IMMEDIATE, UBICOM32_INSN_EXT_1_D_INDIRECT_1_S1_IMMEDIATE, UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_IMMEDIATE, UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_IMMEDIATE
48294 + , UBICOM32_INSN_EXT_1_D_DIRECT_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_EXT_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_INDEX_1
48295 + , UBICOM32_INSN_EXT_1_D_INDIRECT_1_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_EXT_1_D_DIRECT_S1_INDIRECT_WITH_OFFSET_1
48296 + , UBICOM32_INSN_EXT_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_EXT_1_D_INDIRECT_1_S1_INDIRECT_WITH_OFFSET_1
48297 + , UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_EXT_1_D_DIRECT_S1_INDIRECT_1, UBICOM32_INSN_EXT_1_D_IMMEDIATE_1_S1_INDIRECT_1
48298 + , UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_1, UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_1, UBICOM32_INSN_EXT_1_D_INDIRECT_1_S1_INDIRECT_1, UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_1
48299 + , UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_1, UBICOM32_INSN_EXT_1_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_EXT_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_POST_INCREMENT_1
48300 + , UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_EXT_1_D_INDIRECT_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_POST_INCREMENT_1
48301 + , UBICOM32_INSN_EXT_1_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_EXT_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_PRE_INCREMENT_1
48302 + , UBICOM32_INSN_EXT_1_D_INDIRECT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_EXT_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_MOVEI_D_DIRECT
48303 + , UBICOM32_INSN_MOVEI_D_IMMEDIATE_2, UBICOM32_INSN_MOVEI_D_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_MOVEI_D_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_MOVEI_D_INDIRECT_2
48304 + , UBICOM32_INSN_MOVEI_D_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_MOVEI_D_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_BCLR_D_DIRECT_S1_DIRECT, UBICOM32_INSN_BCLR_D_IMMEDIATE_4_S1_DIRECT
48305 + , UBICOM32_INSN_BCLR_D_INDIRECT_WITH_INDEX_4_S1_DIRECT, UBICOM32_INSN_BCLR_D_INDIRECT_WITH_OFFSET_4_S1_DIRECT, UBICOM32_INSN_BCLR_D_INDIRECT_4_S1_DIRECT, UBICOM32_INSN_BCLR_D_INDIRECT_WITH_POST_INCREMENT_4_S1_DIRECT
48306 + , UBICOM32_INSN_BCLR_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_DIRECT, UBICOM32_INSN_BCLR_D_DIRECT_S1_IMMEDIATE, UBICOM32_INSN_BCLR_D_IMMEDIATE_4_S1_IMMEDIATE, UBICOM32_INSN_BCLR_D_INDIRECT_WITH_INDEX_4_S1_IMMEDIATE
48307 + , UBICOM32_INSN_BCLR_D_INDIRECT_WITH_OFFSET_4_S1_IMMEDIATE, UBICOM32_INSN_BCLR_D_INDIRECT_4_S1_IMMEDIATE, UBICOM32_INSN_BCLR_D_INDIRECT_WITH_POST_INCREMENT_4_S1_IMMEDIATE, UBICOM32_INSN_BCLR_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_IMMEDIATE
48308 + , UBICOM32_INSN_BCLR_D_DIRECT_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_BCLR_D_IMMEDIATE_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_BCLR_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_BCLR_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_INDEX_4
48309 + , UBICOM32_INSN_BCLR_D_INDIRECT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_BCLR_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_BCLR_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_BCLR_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4
48310 + , UBICOM32_INSN_BCLR_D_IMMEDIATE_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_BCLR_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_BCLR_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_BCLR_D_INDIRECT_4_S1_INDIRECT_WITH_OFFSET_4
48311 + , UBICOM32_INSN_BCLR_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_BCLR_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_BCLR_D_DIRECT_S1_INDIRECT_4, UBICOM32_INSN_BCLR_D_IMMEDIATE_4_S1_INDIRECT_4
48312 + , UBICOM32_INSN_BCLR_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_4, UBICOM32_INSN_BCLR_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_4, UBICOM32_INSN_BCLR_D_INDIRECT_4_S1_INDIRECT_4, UBICOM32_INSN_BCLR_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_4
48313 + , UBICOM32_INSN_BCLR_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_4, UBICOM32_INSN_BCLR_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_BCLR_D_IMMEDIATE_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_BCLR_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_POST_INCREMENT_4
48314 + , UBICOM32_INSN_BCLR_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_BCLR_D_INDIRECT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_BCLR_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_BCLR_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4
48315 + , UBICOM32_INSN_BCLR_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_BCLR_D_IMMEDIATE_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_BCLR_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_BCLR_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_PRE_INCREMENT_4
48316 + , UBICOM32_INSN_BCLR_D_INDIRECT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_BCLR_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_BCLR_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_BSET_D_DIRECT_S1_DIRECT
48317 + , UBICOM32_INSN_BSET_D_IMMEDIATE_4_S1_DIRECT, UBICOM32_INSN_BSET_D_INDIRECT_WITH_INDEX_4_S1_DIRECT, UBICOM32_INSN_BSET_D_INDIRECT_WITH_OFFSET_4_S1_DIRECT, UBICOM32_INSN_BSET_D_INDIRECT_4_S1_DIRECT
48318 + , UBICOM32_INSN_BSET_D_INDIRECT_WITH_POST_INCREMENT_4_S1_DIRECT, UBICOM32_INSN_BSET_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_DIRECT, UBICOM32_INSN_BSET_D_DIRECT_S1_IMMEDIATE, UBICOM32_INSN_BSET_D_IMMEDIATE_4_S1_IMMEDIATE
48319 + , UBICOM32_INSN_BSET_D_INDIRECT_WITH_INDEX_4_S1_IMMEDIATE, UBICOM32_INSN_BSET_D_INDIRECT_WITH_OFFSET_4_S1_IMMEDIATE, UBICOM32_INSN_BSET_D_INDIRECT_4_S1_IMMEDIATE, UBICOM32_INSN_BSET_D_INDIRECT_WITH_POST_INCREMENT_4_S1_IMMEDIATE
48320 + , UBICOM32_INSN_BSET_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_IMMEDIATE, UBICOM32_INSN_BSET_D_DIRECT_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_BSET_D_IMMEDIATE_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_BSET_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_INDEX_4
48321 + , UBICOM32_INSN_BSET_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_BSET_D_INDIRECT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_BSET_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_BSET_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4
48322 + , UBICOM32_INSN_BSET_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_BSET_D_IMMEDIATE_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_BSET_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_BSET_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_OFFSET_4
48323 + , UBICOM32_INSN_BSET_D_INDIRECT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_BSET_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_BSET_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_BSET_D_DIRECT_S1_INDIRECT_4
48324 + , UBICOM32_INSN_BSET_D_IMMEDIATE_4_S1_INDIRECT_4, UBICOM32_INSN_BSET_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_4, UBICOM32_INSN_BSET_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_4, UBICOM32_INSN_BSET_D_INDIRECT_4_S1_INDIRECT_4
48325 + , UBICOM32_INSN_BSET_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_4, UBICOM32_INSN_BSET_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_4, UBICOM32_INSN_BSET_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_BSET_D_IMMEDIATE_4_S1_INDIRECT_WITH_POST_INCREMENT_4
48326 + , UBICOM32_INSN_BSET_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_BSET_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_BSET_D_INDIRECT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_BSET_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4
48327 + , UBICOM32_INSN_BSET_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_BSET_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_BSET_D_IMMEDIATE_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_BSET_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_PRE_INCREMENT_4
48328 + , UBICOM32_INSN_BSET_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_BSET_D_INDIRECT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_BSET_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_BSET_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4
48329 + , UBICOM32_INSN_BTST_S1_DIRECT_IMM_BIT5, UBICOM32_INSN_BTST_S1_IMMEDIATE_IMM_BIT5, UBICOM32_INSN_BTST_S1_INDIRECT_WITH_INDEX_4_IMM_BIT5, UBICOM32_INSN_BTST_S1_INDIRECT_WITH_OFFSET_4_IMM_BIT5
48330 + , UBICOM32_INSN_BTST_S1_INDIRECT_4_IMM_BIT5, UBICOM32_INSN_BTST_S1_INDIRECT_WITH_POST_INCREMENT_4_IMM_BIT5, UBICOM32_INSN_BTST_S1_INDIRECT_WITH_PRE_INCREMENT_4_IMM_BIT5, UBICOM32_INSN_BTST_S1_DIRECT_DYN_REG
48331 + , UBICOM32_INSN_BTST_S1_IMMEDIATE_DYN_REG, UBICOM32_INSN_BTST_S1_INDIRECT_WITH_INDEX_4_DYN_REG, UBICOM32_INSN_BTST_S1_INDIRECT_WITH_OFFSET_4_DYN_REG, UBICOM32_INSN_BTST_S1_INDIRECT_4_DYN_REG
48332 + , UBICOM32_INSN_BTST_S1_INDIRECT_WITH_POST_INCREMENT_4_DYN_REG, UBICOM32_INSN_BTST_S1_INDIRECT_WITH_PRE_INCREMENT_4_DYN_REG, UBICOM32_INSN_SHMRG_2_IMM_BIT5_S1_DIRECT, UBICOM32_INSN_SHMRG_2_DYN_REG_S1_DIRECT
48333 + , UBICOM32_INSN_SHMRG_2_IMM_BIT5_S1_IMMEDIATE, UBICOM32_INSN_SHMRG_2_DYN_REG_S1_IMMEDIATE, UBICOM32_INSN_SHMRG_2_IMM_BIT5_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_SHMRG_2_DYN_REG_S1_INDIRECT_WITH_INDEX_2
48334 + , UBICOM32_INSN_SHMRG_2_IMM_BIT5_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_SHMRG_2_DYN_REG_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_SHMRG_2_IMM_BIT5_S1_INDIRECT_2, UBICOM32_INSN_SHMRG_2_DYN_REG_S1_INDIRECT_2
48335 + , UBICOM32_INSN_SHMRG_2_IMM_BIT5_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_SHMRG_2_DYN_REG_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_SHMRG_2_IMM_BIT5_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_SHMRG_2_DYN_REG_S1_INDIRECT_WITH_PRE_INCREMENT_2
48336 + , UBICOM32_INSN_SHMRG_1_IMM_BIT5_S1_DIRECT, UBICOM32_INSN_SHMRG_1_DYN_REG_S1_DIRECT, UBICOM32_INSN_SHMRG_1_IMM_BIT5_S1_IMMEDIATE, UBICOM32_INSN_SHMRG_1_DYN_REG_S1_IMMEDIATE
48337 + , UBICOM32_INSN_SHMRG_1_IMM_BIT5_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_SHMRG_1_DYN_REG_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_SHMRG_1_IMM_BIT5_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_SHMRG_1_DYN_REG_S1_INDIRECT_WITH_OFFSET_1
48338 + , UBICOM32_INSN_SHMRG_1_IMM_BIT5_S1_INDIRECT_1, UBICOM32_INSN_SHMRG_1_DYN_REG_S1_INDIRECT_1, UBICOM32_INSN_SHMRG_1_IMM_BIT5_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_SHMRG_1_DYN_REG_S1_INDIRECT_WITH_POST_INCREMENT_1
48339 + , UBICOM32_INSN_SHMRG_1_IMM_BIT5_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_SHMRG_1_DYN_REG_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_CRCGEN_S1_DIRECT_IMM_BIT5, UBICOM32_INSN_CRCGEN_S1_IMMEDIATE_IMM_BIT5
48340 + , UBICOM32_INSN_CRCGEN_S1_INDIRECT_WITH_INDEX_1_IMM_BIT5, UBICOM32_INSN_CRCGEN_S1_INDIRECT_WITH_OFFSET_1_IMM_BIT5, UBICOM32_INSN_CRCGEN_S1_INDIRECT_1_IMM_BIT5, UBICOM32_INSN_CRCGEN_S1_INDIRECT_WITH_POST_INCREMENT_1_IMM_BIT5
48341 + , UBICOM32_INSN_CRCGEN_S1_INDIRECT_WITH_PRE_INCREMENT_1_IMM_BIT5, UBICOM32_INSN_CRCGEN_S1_DIRECT_DYN_REG, UBICOM32_INSN_CRCGEN_S1_IMMEDIATE_DYN_REG, UBICOM32_INSN_CRCGEN_S1_INDIRECT_WITH_INDEX_1_DYN_REG
48342 + , UBICOM32_INSN_CRCGEN_S1_INDIRECT_WITH_OFFSET_1_DYN_REG, UBICOM32_INSN_CRCGEN_S1_INDIRECT_1_DYN_REG, UBICOM32_INSN_CRCGEN_S1_INDIRECT_WITH_POST_INCREMENT_1_DYN_REG, UBICOM32_INSN_CRCGEN_S1_INDIRECT_WITH_PRE_INCREMENT_1_DYN_REG
48343 + , UBICOM32_INSN_BFEXTU_S1_DIRECT_IMM_BIT5, UBICOM32_INSN_BFEXTU_S1_IMMEDIATE_IMM_BIT5, UBICOM32_INSN_BFEXTU_S1_INDIRECT_WITH_INDEX_4_IMM_BIT5, UBICOM32_INSN_BFEXTU_S1_INDIRECT_WITH_OFFSET_4_IMM_BIT5
48344 + , UBICOM32_INSN_BFEXTU_S1_INDIRECT_4_IMM_BIT5, UBICOM32_INSN_BFEXTU_S1_INDIRECT_WITH_POST_INCREMENT_4_IMM_BIT5, UBICOM32_INSN_BFEXTU_S1_INDIRECT_WITH_PRE_INCREMENT_4_IMM_BIT5, UBICOM32_INSN_BFEXTU_S1_DIRECT_DYN_REG
48345 + , UBICOM32_INSN_BFEXTU_S1_IMMEDIATE_DYN_REG, UBICOM32_INSN_BFEXTU_S1_INDIRECT_WITH_INDEX_4_DYN_REG, UBICOM32_INSN_BFEXTU_S1_INDIRECT_WITH_OFFSET_4_DYN_REG, UBICOM32_INSN_BFEXTU_S1_INDIRECT_4_DYN_REG
48346 + , UBICOM32_INSN_BFEXTU_S1_INDIRECT_WITH_POST_INCREMENT_4_DYN_REG, UBICOM32_INSN_BFEXTU_S1_INDIRECT_WITH_PRE_INCREMENT_4_DYN_REG, UBICOM32_INSN_BFRVRS_S1_DIRECT_IMM_BIT5, UBICOM32_INSN_BFRVRS_S1_IMMEDIATE_IMM_BIT5
48347 + , UBICOM32_INSN_BFRVRS_S1_INDIRECT_WITH_INDEX_4_IMM_BIT5, UBICOM32_INSN_BFRVRS_S1_INDIRECT_WITH_OFFSET_4_IMM_BIT5, UBICOM32_INSN_BFRVRS_S1_INDIRECT_4_IMM_BIT5, UBICOM32_INSN_BFRVRS_S1_INDIRECT_WITH_POST_INCREMENT_4_IMM_BIT5
48348 + , UBICOM32_INSN_BFRVRS_S1_INDIRECT_WITH_PRE_INCREMENT_4_IMM_BIT5, UBICOM32_INSN_BFRVRS_S1_DIRECT_DYN_REG, UBICOM32_INSN_BFRVRS_S1_IMMEDIATE_DYN_REG, UBICOM32_INSN_BFRVRS_S1_INDIRECT_WITH_INDEX_4_DYN_REG
48349 + , UBICOM32_INSN_BFRVRS_S1_INDIRECT_WITH_OFFSET_4_DYN_REG, UBICOM32_INSN_BFRVRS_S1_INDIRECT_4_DYN_REG, UBICOM32_INSN_BFRVRS_S1_INDIRECT_WITH_POST_INCREMENT_4_DYN_REG, UBICOM32_INSN_BFRVRS_S1_INDIRECT_WITH_PRE_INCREMENT_4_DYN_REG
48350 + , UBICOM32_INSN_MERGE_S1_DIRECT_IMM_BIT5, UBICOM32_INSN_MERGE_S1_IMMEDIATE_IMM_BIT5, UBICOM32_INSN_MERGE_S1_INDIRECT_WITH_INDEX_4_IMM_BIT5, UBICOM32_INSN_MERGE_S1_INDIRECT_WITH_OFFSET_4_IMM_BIT5
48351 + , UBICOM32_INSN_MERGE_S1_INDIRECT_4_IMM_BIT5, UBICOM32_INSN_MERGE_S1_INDIRECT_WITH_POST_INCREMENT_4_IMM_BIT5, UBICOM32_INSN_MERGE_S1_INDIRECT_WITH_PRE_INCREMENT_4_IMM_BIT5, UBICOM32_INSN_MERGE_S1_DIRECT_DYN_REG
48352 + , UBICOM32_INSN_MERGE_S1_IMMEDIATE_DYN_REG, UBICOM32_INSN_MERGE_S1_INDIRECT_WITH_INDEX_4_DYN_REG, UBICOM32_INSN_MERGE_S1_INDIRECT_WITH_OFFSET_4_DYN_REG, UBICOM32_INSN_MERGE_S1_INDIRECT_4_DYN_REG
48353 + , UBICOM32_INSN_MERGE_S1_INDIRECT_WITH_POST_INCREMENT_4_DYN_REG, UBICOM32_INSN_MERGE_S1_INDIRECT_WITH_PRE_INCREMENT_4_DYN_REG, UBICOM32_INSN_SHFTD_S1_DIRECT_IMM_BIT5, UBICOM32_INSN_SHFTD_S1_IMMEDIATE_IMM_BIT5
48354 + , UBICOM32_INSN_SHFTD_S1_INDIRECT_WITH_INDEX_4_IMM_BIT5, UBICOM32_INSN_SHFTD_S1_INDIRECT_WITH_OFFSET_4_IMM_BIT5, UBICOM32_INSN_SHFTD_S1_INDIRECT_4_IMM_BIT5, UBICOM32_INSN_SHFTD_S1_INDIRECT_WITH_POST_INCREMENT_4_IMM_BIT5
48355 + , UBICOM32_INSN_SHFTD_S1_INDIRECT_WITH_PRE_INCREMENT_4_IMM_BIT5, UBICOM32_INSN_SHFTD_S1_DIRECT_DYN_REG, UBICOM32_INSN_SHFTD_S1_IMMEDIATE_DYN_REG, UBICOM32_INSN_SHFTD_S1_INDIRECT_WITH_INDEX_4_DYN_REG
48356 + , UBICOM32_INSN_SHFTD_S1_INDIRECT_WITH_OFFSET_4_DYN_REG, UBICOM32_INSN_SHFTD_S1_INDIRECT_4_DYN_REG, UBICOM32_INSN_SHFTD_S1_INDIRECT_WITH_POST_INCREMENT_4_DYN_REG, UBICOM32_INSN_SHFTD_S1_INDIRECT_WITH_PRE_INCREMENT_4_DYN_REG
48357 + , UBICOM32_INSN_ASR_1_IMM_BIT5_S1_DIRECT, UBICOM32_INSN_ASR_1_DYN_REG_S1_DIRECT, UBICOM32_INSN_ASR_1_IMM_BIT5_S1_IMMEDIATE, UBICOM32_INSN_ASR_1_DYN_REG_S1_IMMEDIATE
48358 + , UBICOM32_INSN_ASR_1_IMM_BIT5_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_ASR_1_DYN_REG_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_ASR_1_IMM_BIT5_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_ASR_1_DYN_REG_S1_INDIRECT_WITH_OFFSET_1
48359 + , UBICOM32_INSN_ASR_1_IMM_BIT5_S1_INDIRECT_1, UBICOM32_INSN_ASR_1_DYN_REG_S1_INDIRECT_1, UBICOM32_INSN_ASR_1_IMM_BIT5_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_ASR_1_DYN_REG_S1_INDIRECT_WITH_POST_INCREMENT_1
48360 + , UBICOM32_INSN_ASR_1_IMM_BIT5_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_ASR_1_DYN_REG_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_LSL_1_IMM_BIT5_S1_DIRECT, UBICOM32_INSN_LSL_1_DYN_REG_S1_DIRECT
48361 + , UBICOM32_INSN_LSL_1_IMM_BIT5_S1_IMMEDIATE, UBICOM32_INSN_LSL_1_DYN_REG_S1_IMMEDIATE, UBICOM32_INSN_LSL_1_IMM_BIT5_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_LSL_1_DYN_REG_S1_INDIRECT_WITH_INDEX_1
48362 + , UBICOM32_INSN_LSL_1_IMM_BIT5_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_LSL_1_DYN_REG_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_LSL_1_IMM_BIT5_S1_INDIRECT_1, UBICOM32_INSN_LSL_1_DYN_REG_S1_INDIRECT_1
48363 + , UBICOM32_INSN_LSL_1_IMM_BIT5_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_LSL_1_DYN_REG_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_LSL_1_IMM_BIT5_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_LSL_1_DYN_REG_S1_INDIRECT_WITH_PRE_INCREMENT_1
48364 + , UBICOM32_INSN_LSR_1_IMM_BIT5_S1_DIRECT, UBICOM32_INSN_LSR_1_DYN_REG_S1_DIRECT, UBICOM32_INSN_LSR_1_IMM_BIT5_S1_IMMEDIATE, UBICOM32_INSN_LSR_1_DYN_REG_S1_IMMEDIATE
48365 + , UBICOM32_INSN_LSR_1_IMM_BIT5_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_LSR_1_DYN_REG_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_LSR_1_IMM_BIT5_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_LSR_1_DYN_REG_S1_INDIRECT_WITH_OFFSET_1
48366 + , UBICOM32_INSN_LSR_1_IMM_BIT5_S1_INDIRECT_1, UBICOM32_INSN_LSR_1_DYN_REG_S1_INDIRECT_1, UBICOM32_INSN_LSR_1_IMM_BIT5_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_LSR_1_DYN_REG_S1_INDIRECT_WITH_POST_INCREMENT_1
48367 + , UBICOM32_INSN_LSR_1_IMM_BIT5_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_LSR_1_DYN_REG_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_ASR_2_IMM_BIT5_S1_DIRECT, UBICOM32_INSN_ASR_2_DYN_REG_S1_DIRECT
48368 + , UBICOM32_INSN_ASR_2_IMM_BIT5_S1_IMMEDIATE, UBICOM32_INSN_ASR_2_DYN_REG_S1_IMMEDIATE, UBICOM32_INSN_ASR_2_IMM_BIT5_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_ASR_2_DYN_REG_S1_INDIRECT_WITH_INDEX_2
48369 + , UBICOM32_INSN_ASR_2_IMM_BIT5_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_ASR_2_DYN_REG_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_ASR_2_IMM_BIT5_S1_INDIRECT_2, UBICOM32_INSN_ASR_2_DYN_REG_S1_INDIRECT_2
48370 + , UBICOM32_INSN_ASR_2_IMM_BIT5_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_ASR_2_DYN_REG_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_ASR_2_IMM_BIT5_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_ASR_2_DYN_REG_S1_INDIRECT_WITH_PRE_INCREMENT_2
48371 + , UBICOM32_INSN_LSL_2_IMM_BIT5_S1_DIRECT, UBICOM32_INSN_LSL_2_DYN_REG_S1_DIRECT, UBICOM32_INSN_LSL_2_IMM_BIT5_S1_IMMEDIATE, UBICOM32_INSN_LSL_2_DYN_REG_S1_IMMEDIATE
48372 + , UBICOM32_INSN_LSL_2_IMM_BIT5_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_LSL_2_DYN_REG_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_LSL_2_IMM_BIT5_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_LSL_2_DYN_REG_S1_INDIRECT_WITH_OFFSET_2
48373 + , UBICOM32_INSN_LSL_2_IMM_BIT5_S1_INDIRECT_2, UBICOM32_INSN_LSL_2_DYN_REG_S1_INDIRECT_2, UBICOM32_INSN_LSL_2_IMM_BIT5_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_LSL_2_DYN_REG_S1_INDIRECT_WITH_POST_INCREMENT_2
48374 + , UBICOM32_INSN_LSL_2_IMM_BIT5_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_LSL_2_DYN_REG_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_LSR_2_IMM_BIT5_S1_DIRECT, UBICOM32_INSN_LSR_2_DYN_REG_S1_DIRECT
48375 + , UBICOM32_INSN_LSR_2_IMM_BIT5_S1_IMMEDIATE, UBICOM32_INSN_LSR_2_DYN_REG_S1_IMMEDIATE, UBICOM32_INSN_LSR_2_IMM_BIT5_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_LSR_2_DYN_REG_S1_INDIRECT_WITH_INDEX_2
48376 + , UBICOM32_INSN_LSR_2_IMM_BIT5_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_LSR_2_DYN_REG_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_LSR_2_IMM_BIT5_S1_INDIRECT_2, UBICOM32_INSN_LSR_2_DYN_REG_S1_INDIRECT_2
48377 + , UBICOM32_INSN_LSR_2_IMM_BIT5_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_LSR_2_DYN_REG_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_LSR_2_IMM_BIT5_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_LSR_2_DYN_REG_S1_INDIRECT_WITH_PRE_INCREMENT_2
48378 + , UBICOM32_INSN_ASR_4_IMM_BIT5_S1_DIRECT, UBICOM32_INSN_ASR_4_DYN_REG_S1_DIRECT, UBICOM32_INSN_ASR_4_IMM_BIT5_S1_IMMEDIATE, UBICOM32_INSN_ASR_4_DYN_REG_S1_IMMEDIATE
48379 + , UBICOM32_INSN_ASR_4_IMM_BIT5_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_ASR_4_DYN_REG_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_ASR_4_IMM_BIT5_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_ASR_4_DYN_REG_S1_INDIRECT_WITH_OFFSET_4
48380 + , UBICOM32_INSN_ASR_4_IMM_BIT5_S1_INDIRECT_4, UBICOM32_INSN_ASR_4_DYN_REG_S1_INDIRECT_4, UBICOM32_INSN_ASR_4_IMM_BIT5_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_ASR_4_DYN_REG_S1_INDIRECT_WITH_POST_INCREMENT_4
48381 + , UBICOM32_INSN_ASR_4_IMM_BIT5_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_ASR_4_DYN_REG_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_LSL_4_IMM_BIT5_S1_DIRECT, UBICOM32_INSN_LSL_4_DYN_REG_S1_DIRECT
48382 + , UBICOM32_INSN_LSL_4_IMM_BIT5_S1_IMMEDIATE, UBICOM32_INSN_LSL_4_DYN_REG_S1_IMMEDIATE, UBICOM32_INSN_LSL_4_IMM_BIT5_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_LSL_4_DYN_REG_S1_INDIRECT_WITH_INDEX_4
48383 + , UBICOM32_INSN_LSL_4_IMM_BIT5_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_LSL_4_DYN_REG_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_LSL_4_IMM_BIT5_S1_INDIRECT_4, UBICOM32_INSN_LSL_4_DYN_REG_S1_INDIRECT_4
48384 + , UBICOM32_INSN_LSL_4_IMM_BIT5_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_LSL_4_DYN_REG_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_LSL_4_IMM_BIT5_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_LSL_4_DYN_REG_S1_INDIRECT_WITH_PRE_INCREMENT_4
48385 + , UBICOM32_INSN_LSR_4_IMM_BIT5_S1_DIRECT, UBICOM32_INSN_LSR_4_DYN_REG_S1_DIRECT, UBICOM32_INSN_LSR_4_IMM_BIT5_S1_IMMEDIATE, UBICOM32_INSN_LSR_4_DYN_REG_S1_IMMEDIATE
48386 + , UBICOM32_INSN_LSR_4_IMM_BIT5_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_LSR_4_DYN_REG_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_LSR_4_IMM_BIT5_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_LSR_4_DYN_REG_S1_INDIRECT_WITH_OFFSET_4
48387 + , UBICOM32_INSN_LSR_4_IMM_BIT5_S1_INDIRECT_4, UBICOM32_INSN_LSR_4_DYN_REG_S1_INDIRECT_4, UBICOM32_INSN_LSR_4_IMM_BIT5_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_LSR_4_DYN_REG_S1_INDIRECT_WITH_POST_INCREMENT_4
48388 + , UBICOM32_INSN_LSR_4_IMM_BIT5_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_LSR_4_DYN_REG_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_COMPATIBILITY_MAC_S1_DIRECT_DSP_SRC2_DATA_REG, UBICOM32_INSN_COMPATIBILITY_MAC_S1_IMMEDIATE_DSP_SRC2_DATA_REG
48389 + , UBICOM32_INSN_COMPATIBILITY_MAC_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_COMPATIBILITY_MAC_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_COMPATIBILITY_MAC_S1_INDIRECT_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_COMPATIBILITY_MAC_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_DATA_REG
48390 + , UBICOM32_INSN_COMPATIBILITY_MAC_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_COMPATIBILITY_MAC_S1_DIRECT_DSP_IMM_BIT5, UBICOM32_INSN_COMPATIBILITY_MAC_S1_IMMEDIATE_DSP_IMM_BIT5, UBICOM32_INSN_COMPATIBILITY_MAC_S1_INDIRECT_WITH_INDEX_2_DSP_IMM_BIT5
48391 + , UBICOM32_INSN_COMPATIBILITY_MAC_S1_INDIRECT_WITH_OFFSET_2_DSP_IMM_BIT5, UBICOM32_INSN_COMPATIBILITY_MAC_S1_INDIRECT_2_DSP_IMM_BIT5, UBICOM32_INSN_COMPATIBILITY_MAC_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_IMM_BIT5, UBICOM32_INSN_COMPATIBILITY_MAC_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_IMM_BIT5
48392 + , UBICOM32_INSN_MAC_S1_DIRECT_IMM_BIT5, UBICOM32_INSN_MAC_S1_IMMEDIATE_IMM_BIT5, UBICOM32_INSN_MAC_S1_INDIRECT_WITH_INDEX_2_IMM_BIT5, UBICOM32_INSN_MAC_S1_INDIRECT_WITH_OFFSET_2_IMM_BIT5
48393 + , UBICOM32_INSN_MAC_S1_INDIRECT_2_IMM_BIT5, UBICOM32_INSN_MAC_S1_INDIRECT_WITH_POST_INCREMENT_2_IMM_BIT5, UBICOM32_INSN_MAC_S1_INDIRECT_WITH_PRE_INCREMENT_2_IMM_BIT5, UBICOM32_INSN_MAC_S1_DIRECT_DYN_REG
48394 + , UBICOM32_INSN_MAC_S1_IMMEDIATE_DYN_REG, UBICOM32_INSN_MAC_S1_INDIRECT_WITH_INDEX_2_DYN_REG, UBICOM32_INSN_MAC_S1_INDIRECT_WITH_OFFSET_2_DYN_REG, UBICOM32_INSN_MAC_S1_INDIRECT_2_DYN_REG
48395 + , UBICOM32_INSN_MAC_S1_INDIRECT_WITH_POST_INCREMENT_2_DYN_REG, UBICOM32_INSN_MAC_S1_INDIRECT_WITH_PRE_INCREMENT_2_DYN_REG, UBICOM32_INSN_COMPATIBILITY_MULF_S1_DIRECT_DSP_SRC2_DATA_REG, UBICOM32_INSN_COMPATIBILITY_MULF_S1_IMMEDIATE_DSP_SRC2_DATA_REG
48396 + , UBICOM32_INSN_COMPATIBILITY_MULF_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_COMPATIBILITY_MULF_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_COMPATIBILITY_MULF_S1_INDIRECT_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_COMPATIBILITY_MULF_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_DATA_REG
48397 + , UBICOM32_INSN_COMPATIBILITY_MULF_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_COMPATIBILITY_MULF_S1_DIRECT_DSP_IMM_BIT5, UBICOM32_INSN_COMPATIBILITY_MULF_S1_IMMEDIATE_DSP_IMM_BIT5, UBICOM32_INSN_COMPATIBILITY_MULF_S1_INDIRECT_WITH_INDEX_2_DSP_IMM_BIT5
48398 + , UBICOM32_INSN_COMPATIBILITY_MULF_S1_INDIRECT_WITH_OFFSET_2_DSP_IMM_BIT5, UBICOM32_INSN_COMPATIBILITY_MULF_S1_INDIRECT_2_DSP_IMM_BIT5, UBICOM32_INSN_COMPATIBILITY_MULF_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_IMM_BIT5, UBICOM32_INSN_COMPATIBILITY_MULF_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_IMM_BIT5
48399 + , UBICOM32_INSN_MULF_S1_DIRECT_IMM_BIT5, UBICOM32_INSN_MULF_S1_IMMEDIATE_IMM_BIT5, UBICOM32_INSN_MULF_S1_INDIRECT_WITH_INDEX_2_IMM_BIT5, UBICOM32_INSN_MULF_S1_INDIRECT_WITH_OFFSET_2_IMM_BIT5
48400 + , UBICOM32_INSN_MULF_S1_INDIRECT_2_IMM_BIT5, UBICOM32_INSN_MULF_S1_INDIRECT_WITH_POST_INCREMENT_2_IMM_BIT5, UBICOM32_INSN_MULF_S1_INDIRECT_WITH_PRE_INCREMENT_2_IMM_BIT5, UBICOM32_INSN_MULF_S1_DIRECT_DYN_REG
48401 + , UBICOM32_INSN_MULF_S1_IMMEDIATE_DYN_REG, UBICOM32_INSN_MULF_S1_INDIRECT_WITH_INDEX_2_DYN_REG, UBICOM32_INSN_MULF_S1_INDIRECT_WITH_OFFSET_2_DYN_REG, UBICOM32_INSN_MULF_S1_INDIRECT_2_DYN_REG
48402 + , UBICOM32_INSN_MULF_S1_INDIRECT_WITH_POST_INCREMENT_2_DYN_REG, UBICOM32_INSN_MULF_S1_INDIRECT_WITH_PRE_INCREMENT_2_DYN_REG, UBICOM32_INSN_COMPATIBILITY_MULU_S1_DIRECT_DSP_SRC2_DATA_REG, UBICOM32_INSN_COMPATIBILITY_MULU_S1_IMMEDIATE_DSP_SRC2_DATA_REG
48403 + , UBICOM32_INSN_COMPATIBILITY_MULU_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_COMPATIBILITY_MULU_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_COMPATIBILITY_MULU_S1_INDIRECT_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_COMPATIBILITY_MULU_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_DATA_REG
48404 + , UBICOM32_INSN_COMPATIBILITY_MULU_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_COMPATIBILITY_MULU_S1_DIRECT_DSP_IMM_BIT5, UBICOM32_INSN_COMPATIBILITY_MULU_S1_IMMEDIATE_DSP_IMM_BIT5, UBICOM32_INSN_COMPATIBILITY_MULU_S1_INDIRECT_WITH_INDEX_2_DSP_IMM_BIT5
48405 + , UBICOM32_INSN_COMPATIBILITY_MULU_S1_INDIRECT_WITH_OFFSET_2_DSP_IMM_BIT5, UBICOM32_INSN_COMPATIBILITY_MULU_S1_INDIRECT_2_DSP_IMM_BIT5, UBICOM32_INSN_COMPATIBILITY_MULU_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_IMM_BIT5, UBICOM32_INSN_COMPATIBILITY_MULU_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_IMM_BIT5
48406 + , UBICOM32_INSN_MULU_S1_DIRECT_IMM_BIT5, UBICOM32_INSN_MULU_S1_IMMEDIATE_IMM_BIT5, UBICOM32_INSN_MULU_S1_INDIRECT_WITH_INDEX_2_IMM_BIT5, UBICOM32_INSN_MULU_S1_INDIRECT_WITH_OFFSET_2_IMM_BIT5
48407 + , UBICOM32_INSN_MULU_S1_INDIRECT_2_IMM_BIT5, UBICOM32_INSN_MULU_S1_INDIRECT_WITH_POST_INCREMENT_2_IMM_BIT5, UBICOM32_INSN_MULU_S1_INDIRECT_WITH_PRE_INCREMENT_2_IMM_BIT5, UBICOM32_INSN_MULU_S1_DIRECT_DYN_REG
48408 + , UBICOM32_INSN_MULU_S1_IMMEDIATE_DYN_REG, UBICOM32_INSN_MULU_S1_INDIRECT_WITH_INDEX_2_DYN_REG, UBICOM32_INSN_MULU_S1_INDIRECT_WITH_OFFSET_2_DYN_REG, UBICOM32_INSN_MULU_S1_INDIRECT_2_DYN_REG
48409 + , UBICOM32_INSN_MULU_S1_INDIRECT_WITH_POST_INCREMENT_2_DYN_REG, UBICOM32_INSN_MULU_S1_INDIRECT_WITH_PRE_INCREMENT_2_DYN_REG, UBICOM32_INSN_COMPATIBILITY_MULS_S1_DIRECT_DSP_SRC2_DATA_REG, UBICOM32_INSN_COMPATIBILITY_MULS_S1_IMMEDIATE_DSP_SRC2_DATA_REG
48410 + , UBICOM32_INSN_COMPATIBILITY_MULS_S1_INDIRECT_WITH_INDEX_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_COMPATIBILITY_MULS_S1_INDIRECT_WITH_OFFSET_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_COMPATIBILITY_MULS_S1_INDIRECT_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_COMPATIBILITY_MULS_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_SRC2_DATA_REG
48411 + , UBICOM32_INSN_COMPATIBILITY_MULS_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_SRC2_DATA_REG, UBICOM32_INSN_COMPATIBILITY_MULS_S1_DIRECT_DSP_IMM_BIT5, UBICOM32_INSN_COMPATIBILITY_MULS_S1_IMMEDIATE_DSP_IMM_BIT5, UBICOM32_INSN_COMPATIBILITY_MULS_S1_INDIRECT_WITH_INDEX_2_DSP_IMM_BIT5
48412 + , UBICOM32_INSN_COMPATIBILITY_MULS_S1_INDIRECT_WITH_OFFSET_2_DSP_IMM_BIT5, UBICOM32_INSN_COMPATIBILITY_MULS_S1_INDIRECT_2_DSP_IMM_BIT5, UBICOM32_INSN_COMPATIBILITY_MULS_S1_INDIRECT_WITH_POST_INCREMENT_2_DSP_IMM_BIT5, UBICOM32_INSN_COMPATIBILITY_MULS_S1_INDIRECT_WITH_PRE_INCREMENT_2_DSP_IMM_BIT5
48413 + , UBICOM32_INSN_MULS_S1_DIRECT_IMM_BIT5, UBICOM32_INSN_MULS_S1_IMMEDIATE_IMM_BIT5, UBICOM32_INSN_MULS_S1_INDIRECT_WITH_INDEX_2_IMM_BIT5, UBICOM32_INSN_MULS_S1_INDIRECT_WITH_OFFSET_2_IMM_BIT5
48414 + , UBICOM32_INSN_MULS_S1_INDIRECT_2_IMM_BIT5, UBICOM32_INSN_MULS_S1_INDIRECT_WITH_POST_INCREMENT_2_IMM_BIT5, UBICOM32_INSN_MULS_S1_INDIRECT_WITH_PRE_INCREMENT_2_IMM_BIT5, UBICOM32_INSN_MULS_S1_DIRECT_DYN_REG
48415 + , UBICOM32_INSN_MULS_S1_IMMEDIATE_DYN_REG, UBICOM32_INSN_MULS_S1_INDIRECT_WITH_INDEX_2_DYN_REG, UBICOM32_INSN_MULS_S1_INDIRECT_WITH_OFFSET_2_DYN_REG, UBICOM32_INSN_MULS_S1_INDIRECT_2_DYN_REG
48416 + , UBICOM32_INSN_MULS_S1_INDIRECT_WITH_POST_INCREMENT_2_DYN_REG, UBICOM32_INSN_MULS_S1_INDIRECT_WITH_PRE_INCREMENT_2_DYN_REG, UBICOM32_INSN_SWAPB_4_D_DIRECT_S1_DIRECT, UBICOM32_INSN_SWAPB_4_D_IMMEDIATE_4_S1_DIRECT
48417 + , UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_INDEX_4_S1_DIRECT, UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_OFFSET_4_S1_DIRECT, UBICOM32_INSN_SWAPB_4_D_INDIRECT_4_S1_DIRECT, UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_DIRECT
48418 + , UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_DIRECT, UBICOM32_INSN_SWAPB_4_D_DIRECT_S1_IMMEDIATE, UBICOM32_INSN_SWAPB_4_D_IMMEDIATE_4_S1_IMMEDIATE, UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_INDEX_4_S1_IMMEDIATE
48419 + , UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_OFFSET_4_S1_IMMEDIATE, UBICOM32_INSN_SWAPB_4_D_INDIRECT_4_S1_IMMEDIATE, UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_IMMEDIATE, UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_IMMEDIATE
48420 + , UBICOM32_INSN_SWAPB_4_D_DIRECT_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_SWAPB_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_INDEX_4
48421 + , UBICOM32_INSN_SWAPB_4_D_INDIRECT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_SWAPB_4_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4
48422 + , UBICOM32_INSN_SWAPB_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_SWAPB_4_D_INDIRECT_4_S1_INDIRECT_WITH_OFFSET_4
48423 + , UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_SWAPB_4_D_DIRECT_S1_INDIRECT_4, UBICOM32_INSN_SWAPB_4_D_IMMEDIATE_4_S1_INDIRECT_4
48424 + , UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_4, UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_4, UBICOM32_INSN_SWAPB_4_D_INDIRECT_4_S1_INDIRECT_4, UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_4
48425 + , UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_4, UBICOM32_INSN_SWAPB_4_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_SWAPB_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_POST_INCREMENT_4
48426 + , UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_SWAPB_4_D_INDIRECT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4
48427 + , UBICOM32_INSN_SWAPB_4_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_SWAPB_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_PRE_INCREMENT_4
48428 + , UBICOM32_INSN_SWAPB_4_D_INDIRECT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_SWAPB_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_SWAPB_2_D_DIRECT_S1_DIRECT
48429 + , UBICOM32_INSN_SWAPB_2_D_IMMEDIATE_2_S1_DIRECT, UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_INDEX_2_S1_DIRECT, UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_OFFSET_2_S1_DIRECT, UBICOM32_INSN_SWAPB_2_D_INDIRECT_2_S1_DIRECT
48430 + , UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_DIRECT, UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_DIRECT, UBICOM32_INSN_SWAPB_2_D_DIRECT_S1_IMMEDIATE, UBICOM32_INSN_SWAPB_2_D_IMMEDIATE_2_S1_IMMEDIATE
48431 + , UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_INDEX_2_S1_IMMEDIATE, UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_OFFSET_2_S1_IMMEDIATE, UBICOM32_INSN_SWAPB_2_D_INDIRECT_2_S1_IMMEDIATE, UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_IMMEDIATE
48432 + , UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_IMMEDIATE, UBICOM32_INSN_SWAPB_2_D_DIRECT_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_SWAPB_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_INDEX_2
48433 + , UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_SWAPB_2_D_INDIRECT_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_INDEX_2
48434 + , UBICOM32_INSN_SWAPB_2_D_DIRECT_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_SWAPB_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_OFFSET_2
48435 + , UBICOM32_INSN_SWAPB_2_D_INDIRECT_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_SWAPB_2_D_DIRECT_S1_INDIRECT_2
48436 + , UBICOM32_INSN_SWAPB_2_D_IMMEDIATE_2_S1_INDIRECT_2, UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_2, UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_2, UBICOM32_INSN_SWAPB_2_D_INDIRECT_2_S1_INDIRECT_2
48437 + , UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_2, UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_2, UBICOM32_INSN_SWAPB_2_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_SWAPB_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_POST_INCREMENT_2
48438 + , UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_SWAPB_2_D_INDIRECT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_2
48439 + , UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_SWAPB_2_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_SWAPB_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_PRE_INCREMENT_2
48440 + , UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_SWAPB_2_D_INDIRECT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_SWAPB_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2
48441 + , UBICOM32_INSN_PDEC_D_DIRECT_PDEC_S1_EA_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PDEC_D_IMMEDIATE_4_PDEC_S1_EA_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PDEC_D_INDIRECT_WITH_INDEX_4_PDEC_S1_EA_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PDEC_D_INDIRECT_WITH_OFFSET_4_PDEC_S1_EA_INDIRECT_WITH_OFFSET_4
48442 + , UBICOM32_INSN_PDEC_D_INDIRECT_4_PDEC_S1_EA_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PDEC_D_INDIRECT_WITH_POST_INCREMENT_4_PDEC_S1_EA_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PDEC_D_INDIRECT_WITH_PRE_INCREMENT_4_PDEC_S1_EA_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_LEA_4_D_DIRECT_S1_EA_INDIRECT
48443 + , UBICOM32_INSN_LEA_4_D_IMMEDIATE_4_S1_EA_INDIRECT, UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_INDEX_4_S1_EA_INDIRECT, UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_OFFSET_4_S1_EA_INDIRECT, UBICOM32_INSN_LEA_4_D_INDIRECT_4_S1_EA_INDIRECT
48444 + , UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_EA_INDIRECT, UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_EA_INDIRECT, UBICOM32_INSN_LEA_4_D_DIRECT_S1_EA_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_LEA_4_D_IMMEDIATE_4_S1_EA_INDIRECT_WITH_OFFSET_4
48445 + , UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_INDEX_4_S1_EA_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_OFFSET_4_S1_EA_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_LEA_4_D_INDIRECT_4_S1_EA_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_EA_INDIRECT_WITH_OFFSET_4
48446 + , UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_EA_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_LEA_4_D_DIRECT_S1_EA_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_LEA_4_D_IMMEDIATE_4_S1_EA_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_INDEX_4_S1_EA_INDIRECT_WITH_INDEX_4
48447 + , UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_OFFSET_4_S1_EA_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_LEA_4_D_INDIRECT_4_S1_EA_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_EA_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_EA_INDIRECT_WITH_INDEX_4
48448 + , UBICOM32_INSN_LEA_4_D_DIRECT_S1_EA_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_LEA_4_D_IMMEDIATE_4_S1_EA_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_INDEX_4_S1_EA_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_OFFSET_4_S1_EA_INDIRECT_WITH_POST_INCREMENT_4
48449 + , UBICOM32_INSN_LEA_4_D_INDIRECT_4_S1_EA_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_EA_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_EA_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_LEA_4_D_DIRECT_S1_EA_INDIRECT_WITH_PRE_INCREMENT_4
48450 + , UBICOM32_INSN_LEA_4_D_IMMEDIATE_4_S1_EA_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_INDEX_4_S1_EA_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_OFFSET_4_S1_EA_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_LEA_4_D_INDIRECT_4_S1_EA_INDIRECT_WITH_PRE_INCREMENT_4
48451 + , UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_EA_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_EA_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_LEA_4_D_DIRECT_S1_EA_IMMEDIATE, UBICOM32_INSN_LEA_4_D_IMMEDIATE_4_S1_EA_IMMEDIATE
48452 + , UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_INDEX_4_S1_EA_IMMEDIATE, UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_OFFSET_4_S1_EA_IMMEDIATE, UBICOM32_INSN_LEA_4_D_INDIRECT_4_S1_EA_IMMEDIATE, UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_EA_IMMEDIATE
48453 + , UBICOM32_INSN_LEA_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_EA_IMMEDIATE, UBICOM32_INSN_LEA_2_D_DIRECT_S1_EA_INDIRECT, UBICOM32_INSN_LEA_2_D_IMMEDIATE_4_S1_EA_INDIRECT, UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_INDEX_4_S1_EA_INDIRECT
48454 + , UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_OFFSET_4_S1_EA_INDIRECT, UBICOM32_INSN_LEA_2_D_INDIRECT_4_S1_EA_INDIRECT, UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_POST_INCREMENT_4_S1_EA_INDIRECT, UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_EA_INDIRECT
48455 + , UBICOM32_INSN_LEA_2_D_DIRECT_S1_EA_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_LEA_2_D_IMMEDIATE_4_S1_EA_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_INDEX_4_S1_EA_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_OFFSET_4_S1_EA_INDIRECT_WITH_OFFSET_2
48456 + , UBICOM32_INSN_LEA_2_D_INDIRECT_4_S1_EA_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_POST_INCREMENT_4_S1_EA_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_EA_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_LEA_2_D_DIRECT_S1_EA_INDIRECT_WITH_INDEX_2
48457 + , UBICOM32_INSN_LEA_2_D_IMMEDIATE_4_S1_EA_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_INDEX_4_S1_EA_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_OFFSET_4_S1_EA_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_LEA_2_D_INDIRECT_4_S1_EA_INDIRECT_WITH_INDEX_2
48458 + , UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_POST_INCREMENT_4_S1_EA_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_EA_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_LEA_2_D_DIRECT_S1_EA_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_LEA_2_D_IMMEDIATE_4_S1_EA_INDIRECT_WITH_POST_INCREMENT_2
48459 + , UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_INDEX_4_S1_EA_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_OFFSET_4_S1_EA_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_LEA_2_D_INDIRECT_4_S1_EA_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_POST_INCREMENT_4_S1_EA_INDIRECT_WITH_POST_INCREMENT_2
48460 + , UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_EA_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_LEA_2_D_DIRECT_S1_EA_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_LEA_2_D_IMMEDIATE_4_S1_EA_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_INDEX_4_S1_EA_INDIRECT_WITH_PRE_INCREMENT_2
48461 + , UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_OFFSET_4_S1_EA_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_LEA_2_D_INDIRECT_4_S1_EA_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_POST_INCREMENT_4_S1_EA_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_EA_INDIRECT_WITH_PRE_INCREMENT_2
48462 + , UBICOM32_INSN_LEA_2_D_DIRECT_S1_EA_IMMEDIATE, UBICOM32_INSN_LEA_2_D_IMMEDIATE_4_S1_EA_IMMEDIATE, UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_INDEX_4_S1_EA_IMMEDIATE, UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_OFFSET_4_S1_EA_IMMEDIATE
48463 + , UBICOM32_INSN_LEA_2_D_INDIRECT_4_S1_EA_IMMEDIATE, UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_POST_INCREMENT_4_S1_EA_IMMEDIATE, UBICOM32_INSN_LEA_2_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_EA_IMMEDIATE, UBICOM32_INSN_LEA_1_D_DIRECT_S1_EA_INDIRECT
48464 + , UBICOM32_INSN_LEA_1_D_IMMEDIATE_4_S1_EA_INDIRECT, UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_INDEX_4_S1_EA_INDIRECT, UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_OFFSET_4_S1_EA_INDIRECT, UBICOM32_INSN_LEA_1_D_INDIRECT_4_S1_EA_INDIRECT
48465 + , UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_POST_INCREMENT_4_S1_EA_INDIRECT, UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_EA_INDIRECT, UBICOM32_INSN_LEA_1_D_DIRECT_S1_EA_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_LEA_1_D_IMMEDIATE_4_S1_EA_INDIRECT_WITH_OFFSET_1
48466 + , UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_INDEX_4_S1_EA_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_OFFSET_4_S1_EA_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_LEA_1_D_INDIRECT_4_S1_EA_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_POST_INCREMENT_4_S1_EA_INDIRECT_WITH_OFFSET_1
48467 + , UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_EA_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_LEA_1_D_DIRECT_S1_EA_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_LEA_1_D_IMMEDIATE_4_S1_EA_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_INDEX_4_S1_EA_INDIRECT_WITH_INDEX_1
48468 + , UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_OFFSET_4_S1_EA_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_LEA_1_D_INDIRECT_4_S1_EA_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_POST_INCREMENT_4_S1_EA_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_EA_INDIRECT_WITH_INDEX_1
48469 + , UBICOM32_INSN_LEA_1_D_DIRECT_S1_EA_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_LEA_1_D_IMMEDIATE_4_S1_EA_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_INDEX_4_S1_EA_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_OFFSET_4_S1_EA_INDIRECT_WITH_POST_INCREMENT_1
48470 + , UBICOM32_INSN_LEA_1_D_INDIRECT_4_S1_EA_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_POST_INCREMENT_4_S1_EA_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_EA_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_LEA_1_D_DIRECT_S1_EA_INDIRECT_WITH_PRE_INCREMENT_1
48471 + , UBICOM32_INSN_LEA_1_D_IMMEDIATE_4_S1_EA_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_INDEX_4_S1_EA_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_OFFSET_4_S1_EA_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_LEA_1_D_INDIRECT_4_S1_EA_INDIRECT_WITH_PRE_INCREMENT_1
48472 + , UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_POST_INCREMENT_4_S1_EA_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_EA_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_LEA_1_D_DIRECT_S1_EA_IMMEDIATE, UBICOM32_INSN_LEA_1_D_IMMEDIATE_4_S1_EA_IMMEDIATE
48473 + , UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_INDEX_4_S1_EA_IMMEDIATE, UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_OFFSET_4_S1_EA_IMMEDIATE, UBICOM32_INSN_LEA_1_D_INDIRECT_4_S1_EA_IMMEDIATE, UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_POST_INCREMENT_4_S1_EA_IMMEDIATE
48474 + , UBICOM32_INSN_LEA_1_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_EA_IMMEDIATE, UBICOM32_INSN_CMPI_S1_DIRECT, UBICOM32_INSN_CMPI_S1_IMMEDIATE, UBICOM32_INSN_CMPI_S1_INDIRECT_WITH_INDEX_2
48475 + , UBICOM32_INSN_CMPI_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_CMPI_S1_INDIRECT_2, UBICOM32_INSN_CMPI_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_CMPI_S1_INDIRECT_WITH_PRE_INCREMENT_2
48476 + , UBICOM32_INSN_PXADDS_U_D_DIRECT_S1_DIRECT, UBICOM32_INSN_PXADDS_U_D_IMMEDIATE_2_S1_DIRECT, UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_INDEX_2_S1_DIRECT, UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_OFFSET_2_S1_DIRECT
48477 + , UBICOM32_INSN_PXADDS_U_D_INDIRECT_2_S1_DIRECT, UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_POST_INCREMENT_2_S1_DIRECT, UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_DIRECT, UBICOM32_INSN_PXADDS_U_D_DIRECT_S1_IMMEDIATE
48478 + , UBICOM32_INSN_PXADDS_U_D_IMMEDIATE_2_S1_IMMEDIATE, UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_INDEX_2_S1_IMMEDIATE, UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_OFFSET_2_S1_IMMEDIATE, UBICOM32_INSN_PXADDS_U_D_INDIRECT_2_S1_IMMEDIATE
48479 + , UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_POST_INCREMENT_2_S1_IMMEDIATE, UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_IMMEDIATE, UBICOM32_INSN_PXADDS_U_D_DIRECT_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXADDS_U_D_IMMEDIATE_2_S1_INDIRECT_WITH_INDEX_4
48480 + , UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXADDS_U_D_INDIRECT_2_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_INDEX_4
48481 + , UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXADDS_U_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXADDS_U_D_IMMEDIATE_2_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_OFFSET_4
48482 + , UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXADDS_U_D_INDIRECT_2_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_4
48483 + , UBICOM32_INSN_PXADDS_U_D_DIRECT_S1_INDIRECT_4, UBICOM32_INSN_PXADDS_U_D_IMMEDIATE_2_S1_INDIRECT_4, UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_4, UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_4
48484 + , UBICOM32_INSN_PXADDS_U_D_INDIRECT_2_S1_INDIRECT_4, UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_4, UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_4, UBICOM32_INSN_PXADDS_U_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4
48485 + , UBICOM32_INSN_PXADDS_U_D_IMMEDIATE_2_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXADDS_U_D_INDIRECT_2_S1_INDIRECT_WITH_POST_INCREMENT_4
48486 + , UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXADDS_U_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXADDS_U_D_IMMEDIATE_2_S1_INDIRECT_WITH_PRE_INCREMENT_4
48487 + , UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXADDS_U_D_INDIRECT_2_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_4
48488 + , UBICOM32_INSN_PXADDS_U_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXADDS_D_DIRECT_S1_DIRECT, UBICOM32_INSN_PXADDS_D_IMMEDIATE_2_S1_DIRECT, UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_INDEX_2_S1_DIRECT
48489 + , UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_OFFSET_2_S1_DIRECT, UBICOM32_INSN_PXADDS_D_INDIRECT_2_S1_DIRECT, UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_POST_INCREMENT_2_S1_DIRECT, UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_DIRECT
48490 + , UBICOM32_INSN_PXADDS_D_DIRECT_S1_IMMEDIATE, UBICOM32_INSN_PXADDS_D_IMMEDIATE_2_S1_IMMEDIATE, UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_INDEX_2_S1_IMMEDIATE, UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_OFFSET_2_S1_IMMEDIATE
48491 + , UBICOM32_INSN_PXADDS_D_INDIRECT_2_S1_IMMEDIATE, UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_POST_INCREMENT_2_S1_IMMEDIATE, UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_IMMEDIATE, UBICOM32_INSN_PXADDS_D_DIRECT_S1_INDIRECT_WITH_INDEX_4
48492 + , UBICOM32_INSN_PXADDS_D_IMMEDIATE_2_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXADDS_D_INDIRECT_2_S1_INDIRECT_WITH_INDEX_4
48493 + , UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXADDS_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXADDS_D_IMMEDIATE_2_S1_INDIRECT_WITH_OFFSET_4
48494 + , UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXADDS_D_INDIRECT_2_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_4
48495 + , UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXADDS_D_DIRECT_S1_INDIRECT_4, UBICOM32_INSN_PXADDS_D_IMMEDIATE_2_S1_INDIRECT_4, UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_4
48496 + , UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_4, UBICOM32_INSN_PXADDS_D_INDIRECT_2_S1_INDIRECT_4, UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_4, UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_4
48497 + , UBICOM32_INSN_PXADDS_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXADDS_D_IMMEDIATE_2_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_POST_INCREMENT_4
48498 + , UBICOM32_INSN_PXADDS_D_INDIRECT_2_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXADDS_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4
48499 + , UBICOM32_INSN_PXADDS_D_IMMEDIATE_2_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXADDS_D_INDIRECT_2_S1_INDIRECT_WITH_PRE_INCREMENT_4
48500 + , UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXADDS_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXHI_S_S1_DIRECT, UBICOM32_INSN_PXHI_S_S1_IMMEDIATE
48501 + , UBICOM32_INSN_PXHI_S_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXHI_S_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXHI_S_S1_INDIRECT_4, UBICOM32_INSN_PXHI_S_S1_INDIRECT_WITH_POST_INCREMENT_4
48502 + , UBICOM32_INSN_PXHI_S_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXHI_S1_DIRECT, UBICOM32_INSN_PXHI_S1_IMMEDIATE, UBICOM32_INSN_PXHI_S1_INDIRECT_WITH_INDEX_4
48503 + , UBICOM32_INSN_PXHI_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXHI_S1_INDIRECT_4, UBICOM32_INSN_PXHI_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXHI_S1_INDIRECT_WITH_PRE_INCREMENT_4
48504 + , UBICOM32_INSN_PXVI_S_D_DIRECT_S1_DIRECT, UBICOM32_INSN_PXVI_S_D_IMMEDIATE_4_S1_DIRECT, UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_INDEX_4_S1_DIRECT, UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_OFFSET_4_S1_DIRECT
48505 + , UBICOM32_INSN_PXVI_S_D_INDIRECT_4_S1_DIRECT, UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_POST_INCREMENT_4_S1_DIRECT, UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_DIRECT, UBICOM32_INSN_PXVI_S_D_DIRECT_S1_IMMEDIATE
48506 + , UBICOM32_INSN_PXVI_S_D_IMMEDIATE_4_S1_IMMEDIATE, UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_INDEX_4_S1_IMMEDIATE, UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_OFFSET_4_S1_IMMEDIATE, UBICOM32_INSN_PXVI_S_D_INDIRECT_4_S1_IMMEDIATE
48507 + , UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_POST_INCREMENT_4_S1_IMMEDIATE, UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_IMMEDIATE, UBICOM32_INSN_PXVI_S_D_DIRECT_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXVI_S_D_IMMEDIATE_4_S1_INDIRECT_WITH_INDEX_4
48508 + , UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXVI_S_D_INDIRECT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4
48509 + , UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXVI_S_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXVI_S_D_IMMEDIATE_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_OFFSET_4
48510 + , UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXVI_S_D_INDIRECT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4
48511 + , UBICOM32_INSN_PXVI_S_D_DIRECT_S1_INDIRECT_4, UBICOM32_INSN_PXVI_S_D_IMMEDIATE_4_S1_INDIRECT_4, UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_4, UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_4
48512 + , UBICOM32_INSN_PXVI_S_D_INDIRECT_4_S1_INDIRECT_4, UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_4, UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_4, UBICOM32_INSN_PXVI_S_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4
48513 + , UBICOM32_INSN_PXVI_S_D_IMMEDIATE_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXVI_S_D_INDIRECT_4_S1_INDIRECT_WITH_POST_INCREMENT_4
48514 + , UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXVI_S_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXVI_S_D_IMMEDIATE_4_S1_INDIRECT_WITH_PRE_INCREMENT_4
48515 + , UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXVI_S_D_INDIRECT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4
48516 + , UBICOM32_INSN_PXVI_S_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXVI_D_DIRECT_S1_DIRECT, UBICOM32_INSN_PXVI_D_IMMEDIATE_4_S1_DIRECT, UBICOM32_INSN_PXVI_D_INDIRECT_WITH_INDEX_4_S1_DIRECT
48517 + , UBICOM32_INSN_PXVI_D_INDIRECT_WITH_OFFSET_4_S1_DIRECT, UBICOM32_INSN_PXVI_D_INDIRECT_4_S1_DIRECT, UBICOM32_INSN_PXVI_D_INDIRECT_WITH_POST_INCREMENT_4_S1_DIRECT, UBICOM32_INSN_PXVI_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_DIRECT
48518 + , UBICOM32_INSN_PXVI_D_DIRECT_S1_IMMEDIATE, UBICOM32_INSN_PXVI_D_IMMEDIATE_4_S1_IMMEDIATE, UBICOM32_INSN_PXVI_D_INDIRECT_WITH_INDEX_4_S1_IMMEDIATE, UBICOM32_INSN_PXVI_D_INDIRECT_WITH_OFFSET_4_S1_IMMEDIATE
48519 + , UBICOM32_INSN_PXVI_D_INDIRECT_4_S1_IMMEDIATE, UBICOM32_INSN_PXVI_D_INDIRECT_WITH_POST_INCREMENT_4_S1_IMMEDIATE, UBICOM32_INSN_PXVI_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_IMMEDIATE, UBICOM32_INSN_PXVI_D_DIRECT_S1_INDIRECT_WITH_INDEX_4
48520 + , UBICOM32_INSN_PXVI_D_IMMEDIATE_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXVI_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXVI_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXVI_D_INDIRECT_4_S1_INDIRECT_WITH_INDEX_4
48521 + , UBICOM32_INSN_PXVI_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXVI_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXVI_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXVI_D_IMMEDIATE_4_S1_INDIRECT_WITH_OFFSET_4
48522 + , UBICOM32_INSN_PXVI_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXVI_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXVI_D_INDIRECT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXVI_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4
48523 + , UBICOM32_INSN_PXVI_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXVI_D_DIRECT_S1_INDIRECT_4, UBICOM32_INSN_PXVI_D_IMMEDIATE_4_S1_INDIRECT_4, UBICOM32_INSN_PXVI_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_4
48524 + , UBICOM32_INSN_PXVI_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_4, UBICOM32_INSN_PXVI_D_INDIRECT_4_S1_INDIRECT_4, UBICOM32_INSN_PXVI_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_4, UBICOM32_INSN_PXVI_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_4
48525 + , UBICOM32_INSN_PXVI_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXVI_D_IMMEDIATE_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXVI_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXVI_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_POST_INCREMENT_4
48526 + , UBICOM32_INSN_PXVI_D_INDIRECT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXVI_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXVI_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXVI_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4
48527 + , UBICOM32_INSN_PXVI_D_IMMEDIATE_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXVI_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXVI_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXVI_D_INDIRECT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4
48528 + , UBICOM32_INSN_PXVI_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXVI_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXBLEND_T_D_DIRECT_S1_DIRECT, UBICOM32_INSN_PXBLEND_T_D_IMMEDIATE_4_S1_DIRECT
48529 + , UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_INDEX_4_S1_DIRECT, UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_OFFSET_4_S1_DIRECT, UBICOM32_INSN_PXBLEND_T_D_INDIRECT_4_S1_DIRECT, UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_POST_INCREMENT_4_S1_DIRECT
48530 + , UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_DIRECT, UBICOM32_INSN_PXBLEND_T_D_DIRECT_S1_IMMEDIATE, UBICOM32_INSN_PXBLEND_T_D_IMMEDIATE_4_S1_IMMEDIATE, UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_INDEX_4_S1_IMMEDIATE
48531 + , UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_OFFSET_4_S1_IMMEDIATE, UBICOM32_INSN_PXBLEND_T_D_INDIRECT_4_S1_IMMEDIATE, UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_POST_INCREMENT_4_S1_IMMEDIATE, UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_IMMEDIATE
48532 + , UBICOM32_INSN_PXBLEND_T_D_DIRECT_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXBLEND_T_D_IMMEDIATE_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_INDEX_4
48533 + , UBICOM32_INSN_PXBLEND_T_D_INDIRECT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXBLEND_T_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4
48534 + , UBICOM32_INSN_PXBLEND_T_D_IMMEDIATE_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXBLEND_T_D_INDIRECT_4_S1_INDIRECT_WITH_OFFSET_4
48535 + , UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXBLEND_T_D_DIRECT_S1_INDIRECT_4, UBICOM32_INSN_PXBLEND_T_D_IMMEDIATE_4_S1_INDIRECT_4
48536 + , UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_4, UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_4, UBICOM32_INSN_PXBLEND_T_D_INDIRECT_4_S1_INDIRECT_4, UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_4
48537 + , UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_4, UBICOM32_INSN_PXBLEND_T_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXBLEND_T_D_IMMEDIATE_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_POST_INCREMENT_4
48538 + , UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXBLEND_T_D_INDIRECT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4
48539 + , UBICOM32_INSN_PXBLEND_T_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXBLEND_T_D_IMMEDIATE_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_PRE_INCREMENT_4
48540 + , UBICOM32_INSN_PXBLEND_T_D_INDIRECT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXBLEND_T_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXBLEND_D_DIRECT_S1_DIRECT
48541 + , UBICOM32_INSN_PXBLEND_D_IMMEDIATE_4_S1_DIRECT, UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_INDEX_4_S1_DIRECT, UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_OFFSET_4_S1_DIRECT, UBICOM32_INSN_PXBLEND_D_INDIRECT_4_S1_DIRECT
48542 + , UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_POST_INCREMENT_4_S1_DIRECT, UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_DIRECT, UBICOM32_INSN_PXBLEND_D_DIRECT_S1_IMMEDIATE, UBICOM32_INSN_PXBLEND_D_IMMEDIATE_4_S1_IMMEDIATE
48543 + , UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_INDEX_4_S1_IMMEDIATE, UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_OFFSET_4_S1_IMMEDIATE, UBICOM32_INSN_PXBLEND_D_INDIRECT_4_S1_IMMEDIATE, UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_POST_INCREMENT_4_S1_IMMEDIATE
48544 + , UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_IMMEDIATE, UBICOM32_INSN_PXBLEND_D_DIRECT_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXBLEND_D_IMMEDIATE_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_INDEX_4
48545 + , UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXBLEND_D_INDIRECT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4
48546 + , UBICOM32_INSN_PXBLEND_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXBLEND_D_IMMEDIATE_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_OFFSET_4
48547 + , UBICOM32_INSN_PXBLEND_D_INDIRECT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXBLEND_D_DIRECT_S1_INDIRECT_4
48548 + , UBICOM32_INSN_PXBLEND_D_IMMEDIATE_4_S1_INDIRECT_4, UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_4, UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_4, UBICOM32_INSN_PXBLEND_D_INDIRECT_4_S1_INDIRECT_4
48549 + , UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_4, UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_4, UBICOM32_INSN_PXBLEND_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXBLEND_D_IMMEDIATE_4_S1_INDIRECT_WITH_POST_INCREMENT_4
48550 + , UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXBLEND_D_INDIRECT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4
48551 + , UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXBLEND_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXBLEND_D_IMMEDIATE_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_PRE_INCREMENT_4
48552 + , UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXBLEND_D_INDIRECT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXBLEND_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4
48553 + , UBICOM32_INSN_PXCNV_T_D_DIRECT_S1_DIRECT, UBICOM32_INSN_PXCNV_T_D_IMMEDIATE_2_S1_DIRECT, UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_INDEX_2_S1_DIRECT, UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_OFFSET_2_S1_DIRECT
48554 + , UBICOM32_INSN_PXCNV_T_D_INDIRECT_2_S1_DIRECT, UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_POST_INCREMENT_2_S1_DIRECT, UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_DIRECT, UBICOM32_INSN_PXCNV_T_D_DIRECT_S1_IMMEDIATE
48555 + , UBICOM32_INSN_PXCNV_T_D_IMMEDIATE_2_S1_IMMEDIATE, UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_INDEX_2_S1_IMMEDIATE, UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_OFFSET_2_S1_IMMEDIATE, UBICOM32_INSN_PXCNV_T_D_INDIRECT_2_S1_IMMEDIATE
48556 + , UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_POST_INCREMENT_2_S1_IMMEDIATE, UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_IMMEDIATE, UBICOM32_INSN_PXCNV_T_D_DIRECT_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXCNV_T_D_IMMEDIATE_2_S1_INDIRECT_WITH_INDEX_4
48557 + , UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXCNV_T_D_INDIRECT_2_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_INDEX_4
48558 + , UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXCNV_T_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXCNV_T_D_IMMEDIATE_2_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_OFFSET_4
48559 + , UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXCNV_T_D_INDIRECT_2_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_4
48560 + , UBICOM32_INSN_PXCNV_T_D_DIRECT_S1_INDIRECT_4, UBICOM32_INSN_PXCNV_T_D_IMMEDIATE_2_S1_INDIRECT_4, UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_4, UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_4
48561 + , UBICOM32_INSN_PXCNV_T_D_INDIRECT_2_S1_INDIRECT_4, UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_4, UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_4, UBICOM32_INSN_PXCNV_T_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4
48562 + , UBICOM32_INSN_PXCNV_T_D_IMMEDIATE_2_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXCNV_T_D_INDIRECT_2_S1_INDIRECT_WITH_POST_INCREMENT_4
48563 + , UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXCNV_T_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXCNV_T_D_IMMEDIATE_2_S1_INDIRECT_WITH_PRE_INCREMENT_4
48564 + , UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXCNV_T_D_INDIRECT_2_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_4
48565 + , UBICOM32_INSN_PXCNV_T_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXCNV_D_DIRECT_S1_DIRECT, UBICOM32_INSN_PXCNV_D_IMMEDIATE_2_S1_DIRECT, UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_INDEX_2_S1_DIRECT
48566 + , UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_OFFSET_2_S1_DIRECT, UBICOM32_INSN_PXCNV_D_INDIRECT_2_S1_DIRECT, UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_POST_INCREMENT_2_S1_DIRECT, UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_DIRECT
48567 + , UBICOM32_INSN_PXCNV_D_DIRECT_S1_IMMEDIATE, UBICOM32_INSN_PXCNV_D_IMMEDIATE_2_S1_IMMEDIATE, UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_INDEX_2_S1_IMMEDIATE, UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_OFFSET_2_S1_IMMEDIATE
48568 + , UBICOM32_INSN_PXCNV_D_INDIRECT_2_S1_IMMEDIATE, UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_POST_INCREMENT_2_S1_IMMEDIATE, UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_IMMEDIATE, UBICOM32_INSN_PXCNV_D_DIRECT_S1_INDIRECT_WITH_INDEX_4
48569 + , UBICOM32_INSN_PXCNV_D_IMMEDIATE_2_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXCNV_D_INDIRECT_2_S1_INDIRECT_WITH_INDEX_4
48570 + , UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_PXCNV_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXCNV_D_IMMEDIATE_2_S1_INDIRECT_WITH_OFFSET_4
48571 + , UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXCNV_D_INDIRECT_2_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_4
48572 + , UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_PXCNV_D_DIRECT_S1_INDIRECT_4, UBICOM32_INSN_PXCNV_D_IMMEDIATE_2_S1_INDIRECT_4, UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_4
48573 + , UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_4, UBICOM32_INSN_PXCNV_D_INDIRECT_2_S1_INDIRECT_4, UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_4, UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_4
48574 + , UBICOM32_INSN_PXCNV_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXCNV_D_IMMEDIATE_2_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_POST_INCREMENT_4
48575 + , UBICOM32_INSN_PXCNV_D_INDIRECT_2_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_PXCNV_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4
48576 + , UBICOM32_INSN_PXCNV_D_IMMEDIATE_2_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXCNV_D_INDIRECT_2_S1_INDIRECT_WITH_PRE_INCREMENT_4
48577 + , UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_PXCNV_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_SUBC_D_DIRECT_S1_DIRECT, UBICOM32_INSN_SUBC_D_IMMEDIATE_4_S1_DIRECT
48578 + , UBICOM32_INSN_SUBC_D_INDIRECT_WITH_INDEX_4_S1_DIRECT, UBICOM32_INSN_SUBC_D_INDIRECT_WITH_OFFSET_4_S1_DIRECT, UBICOM32_INSN_SUBC_D_INDIRECT_4_S1_DIRECT, UBICOM32_INSN_SUBC_D_INDIRECT_WITH_POST_INCREMENT_4_S1_DIRECT
48579 + , UBICOM32_INSN_SUBC_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_DIRECT, UBICOM32_INSN_SUBC_D_DIRECT_S1_IMMEDIATE, UBICOM32_INSN_SUBC_D_IMMEDIATE_4_S1_IMMEDIATE, UBICOM32_INSN_SUBC_D_INDIRECT_WITH_INDEX_4_S1_IMMEDIATE
48580 + , UBICOM32_INSN_SUBC_D_INDIRECT_WITH_OFFSET_4_S1_IMMEDIATE, UBICOM32_INSN_SUBC_D_INDIRECT_4_S1_IMMEDIATE, UBICOM32_INSN_SUBC_D_INDIRECT_WITH_POST_INCREMENT_4_S1_IMMEDIATE, UBICOM32_INSN_SUBC_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_IMMEDIATE
48581 + , UBICOM32_INSN_SUBC_D_DIRECT_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_SUBC_D_IMMEDIATE_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_SUBC_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_SUBC_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_INDEX_4
48582 + , UBICOM32_INSN_SUBC_D_INDIRECT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_SUBC_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_SUBC_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_SUBC_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4
48583 + , UBICOM32_INSN_SUBC_D_IMMEDIATE_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_SUBC_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_SUBC_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_SUBC_D_INDIRECT_4_S1_INDIRECT_WITH_OFFSET_4
48584 + , UBICOM32_INSN_SUBC_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_SUBC_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_SUBC_D_DIRECT_S1_INDIRECT_4, UBICOM32_INSN_SUBC_D_IMMEDIATE_4_S1_INDIRECT_4
48585 + , UBICOM32_INSN_SUBC_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_4, UBICOM32_INSN_SUBC_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_4, UBICOM32_INSN_SUBC_D_INDIRECT_4_S1_INDIRECT_4, UBICOM32_INSN_SUBC_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_4
48586 + , UBICOM32_INSN_SUBC_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_4, UBICOM32_INSN_SUBC_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_SUBC_D_IMMEDIATE_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_SUBC_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_POST_INCREMENT_4
48587 + , UBICOM32_INSN_SUBC_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_SUBC_D_INDIRECT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_SUBC_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_SUBC_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4
48588 + , UBICOM32_INSN_SUBC_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_SUBC_D_IMMEDIATE_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_SUBC_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_SUBC_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_PRE_INCREMENT_4
48589 + , UBICOM32_INSN_SUBC_D_INDIRECT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_SUBC_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_SUBC_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_ADDC_D_DIRECT_S1_DIRECT
48590 + , UBICOM32_INSN_ADDC_D_IMMEDIATE_4_S1_DIRECT, UBICOM32_INSN_ADDC_D_INDIRECT_WITH_INDEX_4_S1_DIRECT, UBICOM32_INSN_ADDC_D_INDIRECT_WITH_OFFSET_4_S1_DIRECT, UBICOM32_INSN_ADDC_D_INDIRECT_4_S1_DIRECT
48591 + , UBICOM32_INSN_ADDC_D_INDIRECT_WITH_POST_INCREMENT_4_S1_DIRECT, UBICOM32_INSN_ADDC_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_DIRECT, UBICOM32_INSN_ADDC_D_DIRECT_S1_IMMEDIATE, UBICOM32_INSN_ADDC_D_IMMEDIATE_4_S1_IMMEDIATE
48592 + , UBICOM32_INSN_ADDC_D_INDIRECT_WITH_INDEX_4_S1_IMMEDIATE, UBICOM32_INSN_ADDC_D_INDIRECT_WITH_OFFSET_4_S1_IMMEDIATE, UBICOM32_INSN_ADDC_D_INDIRECT_4_S1_IMMEDIATE, UBICOM32_INSN_ADDC_D_INDIRECT_WITH_POST_INCREMENT_4_S1_IMMEDIATE
48593 + , UBICOM32_INSN_ADDC_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_IMMEDIATE, UBICOM32_INSN_ADDC_D_DIRECT_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_ADDC_D_IMMEDIATE_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_ADDC_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_INDEX_4
48594 + , UBICOM32_INSN_ADDC_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_ADDC_D_INDIRECT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_ADDC_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_ADDC_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4
48595 + , UBICOM32_INSN_ADDC_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_ADDC_D_IMMEDIATE_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_ADDC_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_ADDC_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_OFFSET_4
48596 + , UBICOM32_INSN_ADDC_D_INDIRECT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_ADDC_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_ADDC_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_ADDC_D_DIRECT_S1_INDIRECT_4
48597 + , UBICOM32_INSN_ADDC_D_IMMEDIATE_4_S1_INDIRECT_4, UBICOM32_INSN_ADDC_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_4, UBICOM32_INSN_ADDC_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_4, UBICOM32_INSN_ADDC_D_INDIRECT_4_S1_INDIRECT_4
48598 + , UBICOM32_INSN_ADDC_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_4, UBICOM32_INSN_ADDC_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_4, UBICOM32_INSN_ADDC_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_ADDC_D_IMMEDIATE_4_S1_INDIRECT_WITH_POST_INCREMENT_4
48599 + , UBICOM32_INSN_ADDC_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_ADDC_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_ADDC_D_INDIRECT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_ADDC_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4
48600 + , UBICOM32_INSN_ADDC_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_ADDC_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_ADDC_D_IMMEDIATE_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_ADDC_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_PRE_INCREMENT_4
48601 + , UBICOM32_INSN_ADDC_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_ADDC_D_INDIRECT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_ADDC_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_ADDC_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4
48602 + , UBICOM32_INSN_SUB_1_D_DIRECT_S1_DIRECT, UBICOM32_INSN_SUB_1_D_IMMEDIATE_1_S1_DIRECT, UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_INDEX_1_S1_DIRECT, UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_OFFSET_1_S1_DIRECT
48603 + , UBICOM32_INSN_SUB_1_D_INDIRECT_1_S1_DIRECT, UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_DIRECT, UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_DIRECT, UBICOM32_INSN_SUB_1_D_DIRECT_S1_IMMEDIATE
48604 + , UBICOM32_INSN_SUB_1_D_IMMEDIATE_1_S1_IMMEDIATE, UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_INDEX_1_S1_IMMEDIATE, UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_OFFSET_1_S1_IMMEDIATE, UBICOM32_INSN_SUB_1_D_INDIRECT_1_S1_IMMEDIATE
48605 + , UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_IMMEDIATE, UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_IMMEDIATE, UBICOM32_INSN_SUB_1_D_DIRECT_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_SUB_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_INDEX_1
48606 + , UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_SUB_1_D_INDIRECT_1_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_INDEX_1
48607 + , UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_SUB_1_D_DIRECT_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_SUB_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_OFFSET_1
48608 + , UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_SUB_1_D_INDIRECT_1_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_OFFSET_1
48609 + , UBICOM32_INSN_SUB_1_D_DIRECT_S1_INDIRECT_1, UBICOM32_INSN_SUB_1_D_IMMEDIATE_1_S1_INDIRECT_1, UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_1, UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_1
48610 + , UBICOM32_INSN_SUB_1_D_INDIRECT_1_S1_INDIRECT_1, UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_1, UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_1, UBICOM32_INSN_SUB_1_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_1
48611 + , UBICOM32_INSN_SUB_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_SUB_1_D_INDIRECT_1_S1_INDIRECT_WITH_POST_INCREMENT_1
48612 + , UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_SUB_1_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_SUB_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_PRE_INCREMENT_1
48613 + , UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_SUB_1_D_INDIRECT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1
48614 + , UBICOM32_INSN_SUB_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_SUB_4_D_DIRECT_S1_DIRECT, UBICOM32_INSN_SUB_4_D_IMMEDIATE_4_S1_DIRECT, UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_INDEX_4_S1_DIRECT
48615 + , UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_OFFSET_4_S1_DIRECT, UBICOM32_INSN_SUB_4_D_INDIRECT_4_S1_DIRECT, UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_DIRECT, UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_DIRECT
48616 + , UBICOM32_INSN_SUB_4_D_DIRECT_S1_IMMEDIATE, UBICOM32_INSN_SUB_4_D_IMMEDIATE_4_S1_IMMEDIATE, UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_INDEX_4_S1_IMMEDIATE, UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_OFFSET_4_S1_IMMEDIATE
48617 + , UBICOM32_INSN_SUB_4_D_INDIRECT_4_S1_IMMEDIATE, UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_IMMEDIATE, UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_IMMEDIATE, UBICOM32_INSN_SUB_4_D_DIRECT_S1_INDIRECT_WITH_INDEX_4
48618 + , UBICOM32_INSN_SUB_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_SUB_4_D_INDIRECT_4_S1_INDIRECT_WITH_INDEX_4
48619 + , UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_SUB_4_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_SUB_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_OFFSET_4
48620 + , UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_SUB_4_D_INDIRECT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4
48621 + , UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_SUB_4_D_DIRECT_S1_INDIRECT_4, UBICOM32_INSN_SUB_4_D_IMMEDIATE_4_S1_INDIRECT_4, UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_4
48622 + , UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_4, UBICOM32_INSN_SUB_4_D_INDIRECT_4_S1_INDIRECT_4, UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_4, UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_4
48623 + , UBICOM32_INSN_SUB_4_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_SUB_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_POST_INCREMENT_4
48624 + , UBICOM32_INSN_SUB_4_D_INDIRECT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_SUB_4_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4
48625 + , UBICOM32_INSN_SUB_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_SUB_4_D_INDIRECT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4
48626 + , UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_SUB_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_SUB_2_D_DIRECT_S1_DIRECT, UBICOM32_INSN_SUB_2_D_IMMEDIATE_2_S1_DIRECT
48627 + , UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_INDEX_2_S1_DIRECT, UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_OFFSET_2_S1_DIRECT, UBICOM32_INSN_SUB_2_D_INDIRECT_2_S1_DIRECT, UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_DIRECT
48628 + , UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_DIRECT, UBICOM32_INSN_SUB_2_D_DIRECT_S1_IMMEDIATE, UBICOM32_INSN_SUB_2_D_IMMEDIATE_2_S1_IMMEDIATE, UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_INDEX_2_S1_IMMEDIATE
48629 + , UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_OFFSET_2_S1_IMMEDIATE, UBICOM32_INSN_SUB_2_D_INDIRECT_2_S1_IMMEDIATE, UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_IMMEDIATE, UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_IMMEDIATE
48630 + , UBICOM32_INSN_SUB_2_D_DIRECT_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_SUB_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_INDEX_2
48631 + , UBICOM32_INSN_SUB_2_D_INDIRECT_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_SUB_2_D_DIRECT_S1_INDIRECT_WITH_OFFSET_2
48632 + , UBICOM32_INSN_SUB_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_SUB_2_D_INDIRECT_2_S1_INDIRECT_WITH_OFFSET_2
48633 + , UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_SUB_2_D_DIRECT_S1_INDIRECT_2, UBICOM32_INSN_SUB_2_D_IMMEDIATE_2_S1_INDIRECT_2
48634 + , UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_2, UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_2, UBICOM32_INSN_SUB_2_D_INDIRECT_2_S1_INDIRECT_2, UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_2
48635 + , UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_2, UBICOM32_INSN_SUB_2_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_SUB_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_POST_INCREMENT_2
48636 + , UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_SUB_2_D_INDIRECT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_2
48637 + , UBICOM32_INSN_SUB_2_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_SUB_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_PRE_INCREMENT_2
48638 + , UBICOM32_INSN_SUB_2_D_INDIRECT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_SUB_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_ADD_1_D_DIRECT_S1_DIRECT
48639 + , UBICOM32_INSN_ADD_1_D_IMMEDIATE_1_S1_DIRECT, UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_INDEX_1_S1_DIRECT, UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_OFFSET_1_S1_DIRECT, UBICOM32_INSN_ADD_1_D_INDIRECT_1_S1_DIRECT
48640 + , UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_DIRECT, UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_DIRECT, UBICOM32_INSN_ADD_1_D_DIRECT_S1_IMMEDIATE, UBICOM32_INSN_ADD_1_D_IMMEDIATE_1_S1_IMMEDIATE
48641 + , UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_INDEX_1_S1_IMMEDIATE, UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_OFFSET_1_S1_IMMEDIATE, UBICOM32_INSN_ADD_1_D_INDIRECT_1_S1_IMMEDIATE, UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_IMMEDIATE
48642 + , UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_IMMEDIATE, UBICOM32_INSN_ADD_1_D_DIRECT_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_ADD_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_INDEX_1
48643 + , UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_ADD_1_D_INDIRECT_1_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_INDEX_1
48644 + , UBICOM32_INSN_ADD_1_D_DIRECT_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_ADD_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_OFFSET_1
48645 + , UBICOM32_INSN_ADD_1_D_INDIRECT_1_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_ADD_1_D_DIRECT_S1_INDIRECT_1
48646 + , UBICOM32_INSN_ADD_1_D_IMMEDIATE_1_S1_INDIRECT_1, UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_1, UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_1, UBICOM32_INSN_ADD_1_D_INDIRECT_1_S1_INDIRECT_1
48647 + , UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_1, UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_1, UBICOM32_INSN_ADD_1_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_ADD_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_POST_INCREMENT_1
48648 + , UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_ADD_1_D_INDIRECT_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_POST_INCREMENT_1
48649 + , UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_ADD_1_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_ADD_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_PRE_INCREMENT_1
48650 + , UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_ADD_1_D_INDIRECT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_ADD_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1
48651 + , UBICOM32_INSN_ADD_4_D_DIRECT_S1_DIRECT, UBICOM32_INSN_ADD_4_D_IMMEDIATE_4_S1_DIRECT, UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_INDEX_4_S1_DIRECT, UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_OFFSET_4_S1_DIRECT
48652 + , UBICOM32_INSN_ADD_4_D_INDIRECT_4_S1_DIRECT, UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_DIRECT, UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_DIRECT, UBICOM32_INSN_ADD_4_D_DIRECT_S1_IMMEDIATE
48653 + , UBICOM32_INSN_ADD_4_D_IMMEDIATE_4_S1_IMMEDIATE, UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_INDEX_4_S1_IMMEDIATE, UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_OFFSET_4_S1_IMMEDIATE, UBICOM32_INSN_ADD_4_D_INDIRECT_4_S1_IMMEDIATE
48654 + , UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_IMMEDIATE, UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_IMMEDIATE, UBICOM32_INSN_ADD_4_D_DIRECT_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_ADD_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_INDEX_4
48655 + , UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_ADD_4_D_INDIRECT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4
48656 + , UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_ADD_4_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_ADD_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_OFFSET_4
48657 + , UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_ADD_4_D_INDIRECT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4
48658 + , UBICOM32_INSN_ADD_4_D_DIRECT_S1_INDIRECT_4, UBICOM32_INSN_ADD_4_D_IMMEDIATE_4_S1_INDIRECT_4, UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_4, UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_4
48659 + , UBICOM32_INSN_ADD_4_D_INDIRECT_4_S1_INDIRECT_4, UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_4, UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_4, UBICOM32_INSN_ADD_4_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4
48660 + , UBICOM32_INSN_ADD_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_ADD_4_D_INDIRECT_4_S1_INDIRECT_WITH_POST_INCREMENT_4
48661 + , UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_ADD_4_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_ADD_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_PRE_INCREMENT_4
48662 + , UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_ADD_4_D_INDIRECT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4
48663 + , UBICOM32_INSN_ADD_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_ADD_2_D_DIRECT_S1_DIRECT, UBICOM32_INSN_ADD_2_D_IMMEDIATE_2_S1_DIRECT, UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_INDEX_2_S1_DIRECT
48664 + , UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_OFFSET_2_S1_DIRECT, UBICOM32_INSN_ADD_2_D_INDIRECT_2_S1_DIRECT, UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_DIRECT, UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_DIRECT
48665 + , UBICOM32_INSN_ADD_2_D_DIRECT_S1_IMMEDIATE, UBICOM32_INSN_ADD_2_D_IMMEDIATE_2_S1_IMMEDIATE, UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_INDEX_2_S1_IMMEDIATE, UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_OFFSET_2_S1_IMMEDIATE
48666 + , UBICOM32_INSN_ADD_2_D_INDIRECT_2_S1_IMMEDIATE, UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_IMMEDIATE, UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_IMMEDIATE, UBICOM32_INSN_ADD_2_D_DIRECT_S1_INDIRECT_WITH_INDEX_2
48667 + , UBICOM32_INSN_ADD_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_ADD_2_D_INDIRECT_2_S1_INDIRECT_WITH_INDEX_2
48668 + , UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_ADD_2_D_DIRECT_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_ADD_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_OFFSET_2
48669 + , UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_ADD_2_D_INDIRECT_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_2
48670 + , UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_ADD_2_D_DIRECT_S1_INDIRECT_2, UBICOM32_INSN_ADD_2_D_IMMEDIATE_2_S1_INDIRECT_2, UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_2
48671 + , UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_2, UBICOM32_INSN_ADD_2_D_INDIRECT_2_S1_INDIRECT_2, UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_2, UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_2
48672 + , UBICOM32_INSN_ADD_2_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_ADD_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_POST_INCREMENT_2
48673 + , UBICOM32_INSN_ADD_2_D_INDIRECT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_ADD_2_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_2
48674 + , UBICOM32_INSN_ADD_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_ADD_2_D_INDIRECT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2
48675 + , UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_ADD_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_NOT_4_D_DIRECT_S1_DIRECT, UBICOM32_INSN_NOT_4_D_IMMEDIATE_4_S1_DIRECT
48676 + , UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_INDEX_4_S1_DIRECT, UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_OFFSET_4_S1_DIRECT, UBICOM32_INSN_NOT_4_D_INDIRECT_4_S1_DIRECT, UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_DIRECT
48677 + , UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_DIRECT, UBICOM32_INSN_NOT_4_D_DIRECT_S1_IMMEDIATE, UBICOM32_INSN_NOT_4_D_IMMEDIATE_4_S1_IMMEDIATE, UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_INDEX_4_S1_IMMEDIATE
48678 + , UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_OFFSET_4_S1_IMMEDIATE, UBICOM32_INSN_NOT_4_D_INDIRECT_4_S1_IMMEDIATE, UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_IMMEDIATE, UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_IMMEDIATE
48679 + , UBICOM32_INSN_NOT_4_D_DIRECT_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_NOT_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_INDEX_4
48680 + , UBICOM32_INSN_NOT_4_D_INDIRECT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_NOT_4_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4
48681 + , UBICOM32_INSN_NOT_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_NOT_4_D_INDIRECT_4_S1_INDIRECT_WITH_OFFSET_4
48682 + , UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_NOT_4_D_DIRECT_S1_INDIRECT_4, UBICOM32_INSN_NOT_4_D_IMMEDIATE_4_S1_INDIRECT_4
48683 + , UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_4, UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_4, UBICOM32_INSN_NOT_4_D_INDIRECT_4_S1_INDIRECT_4, UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_4
48684 + , UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_4, UBICOM32_INSN_NOT_4_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_NOT_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_POST_INCREMENT_4
48685 + , UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_NOT_4_D_INDIRECT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4
48686 + , UBICOM32_INSN_NOT_4_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_NOT_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_PRE_INCREMENT_4
48687 + , UBICOM32_INSN_NOT_4_D_INDIRECT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_NOT_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_NOT_2_D_DIRECT_S1_DIRECT
48688 + , UBICOM32_INSN_NOT_2_D_IMMEDIATE_2_S1_DIRECT, UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_INDEX_2_S1_DIRECT, UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_OFFSET_2_S1_DIRECT, UBICOM32_INSN_NOT_2_D_INDIRECT_2_S1_DIRECT
48689 + , UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_DIRECT, UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_DIRECT, UBICOM32_INSN_NOT_2_D_DIRECT_S1_IMMEDIATE, UBICOM32_INSN_NOT_2_D_IMMEDIATE_2_S1_IMMEDIATE
48690 + , UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_INDEX_2_S1_IMMEDIATE, UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_OFFSET_2_S1_IMMEDIATE, UBICOM32_INSN_NOT_2_D_INDIRECT_2_S1_IMMEDIATE, UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_IMMEDIATE
48691 + , UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_IMMEDIATE, UBICOM32_INSN_NOT_2_D_DIRECT_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_NOT_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_INDEX_2
48692 + , UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_NOT_2_D_INDIRECT_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_INDEX_2
48693 + , UBICOM32_INSN_NOT_2_D_DIRECT_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_NOT_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_OFFSET_2
48694 + , UBICOM32_INSN_NOT_2_D_INDIRECT_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_NOT_2_D_DIRECT_S1_INDIRECT_2
48695 + , UBICOM32_INSN_NOT_2_D_IMMEDIATE_2_S1_INDIRECT_2, UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_2, UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_2, UBICOM32_INSN_NOT_2_D_INDIRECT_2_S1_INDIRECT_2
48696 + , UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_2, UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_2, UBICOM32_INSN_NOT_2_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_NOT_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_POST_INCREMENT_2
48697 + , UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_NOT_2_D_INDIRECT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_2
48698 + , UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_NOT_2_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_NOT_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_PRE_INCREMENT_2
48699 + , UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_NOT_2_D_INDIRECT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_NOT_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2
48700 + , UBICOM32_INSN_XOR_1_D_DIRECT_S1_DIRECT, UBICOM32_INSN_XOR_1_D_IMMEDIATE_1_S1_DIRECT, UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_INDEX_1_S1_DIRECT, UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_OFFSET_1_S1_DIRECT
48701 + , UBICOM32_INSN_XOR_1_D_INDIRECT_1_S1_DIRECT, UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_DIRECT, UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_DIRECT, UBICOM32_INSN_XOR_1_D_DIRECT_S1_IMMEDIATE
48702 + , UBICOM32_INSN_XOR_1_D_IMMEDIATE_1_S1_IMMEDIATE, UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_INDEX_1_S1_IMMEDIATE, UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_OFFSET_1_S1_IMMEDIATE, UBICOM32_INSN_XOR_1_D_INDIRECT_1_S1_IMMEDIATE
48703 + , UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_IMMEDIATE, UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_IMMEDIATE, UBICOM32_INSN_XOR_1_D_DIRECT_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_XOR_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_INDEX_1
48704 + , UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_XOR_1_D_INDIRECT_1_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_INDEX_1
48705 + , UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_XOR_1_D_DIRECT_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_XOR_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_OFFSET_1
48706 + , UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_XOR_1_D_INDIRECT_1_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_OFFSET_1
48707 + , UBICOM32_INSN_XOR_1_D_DIRECT_S1_INDIRECT_1, UBICOM32_INSN_XOR_1_D_IMMEDIATE_1_S1_INDIRECT_1, UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_1, UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_1
48708 + , UBICOM32_INSN_XOR_1_D_INDIRECT_1_S1_INDIRECT_1, UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_1, UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_1, UBICOM32_INSN_XOR_1_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_1
48709 + , UBICOM32_INSN_XOR_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_XOR_1_D_INDIRECT_1_S1_INDIRECT_WITH_POST_INCREMENT_1
48710 + , UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_XOR_1_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_XOR_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_PRE_INCREMENT_1
48711 + , UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_XOR_1_D_INDIRECT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1
48712 + , UBICOM32_INSN_XOR_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_OR_1_D_DIRECT_S1_DIRECT, UBICOM32_INSN_OR_1_D_IMMEDIATE_1_S1_DIRECT, UBICOM32_INSN_OR_1_D_INDIRECT_WITH_INDEX_1_S1_DIRECT
48713 + , UBICOM32_INSN_OR_1_D_INDIRECT_WITH_OFFSET_1_S1_DIRECT, UBICOM32_INSN_OR_1_D_INDIRECT_1_S1_DIRECT, UBICOM32_INSN_OR_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_DIRECT, UBICOM32_INSN_OR_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_DIRECT
48714 + , UBICOM32_INSN_OR_1_D_DIRECT_S1_IMMEDIATE, UBICOM32_INSN_OR_1_D_IMMEDIATE_1_S1_IMMEDIATE, UBICOM32_INSN_OR_1_D_INDIRECT_WITH_INDEX_1_S1_IMMEDIATE, UBICOM32_INSN_OR_1_D_INDIRECT_WITH_OFFSET_1_S1_IMMEDIATE
48715 + , UBICOM32_INSN_OR_1_D_INDIRECT_1_S1_IMMEDIATE, UBICOM32_INSN_OR_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_IMMEDIATE, UBICOM32_INSN_OR_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_IMMEDIATE, UBICOM32_INSN_OR_1_D_DIRECT_S1_INDIRECT_WITH_INDEX_1
48716 + , UBICOM32_INSN_OR_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_OR_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_OR_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_OR_1_D_INDIRECT_1_S1_INDIRECT_WITH_INDEX_1
48717 + , UBICOM32_INSN_OR_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_OR_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_OR_1_D_DIRECT_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_OR_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_OFFSET_1
48718 + , UBICOM32_INSN_OR_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_OR_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_OR_1_D_INDIRECT_1_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_OR_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_OFFSET_1
48719 + , UBICOM32_INSN_OR_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_OR_1_D_DIRECT_S1_INDIRECT_1, UBICOM32_INSN_OR_1_D_IMMEDIATE_1_S1_INDIRECT_1, UBICOM32_INSN_OR_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_1
48720 + , UBICOM32_INSN_OR_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_1, UBICOM32_INSN_OR_1_D_INDIRECT_1_S1_INDIRECT_1, UBICOM32_INSN_OR_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_1, UBICOM32_INSN_OR_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_1
48721 + , UBICOM32_INSN_OR_1_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_OR_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_OR_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_OR_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_POST_INCREMENT_1
48722 + , UBICOM32_INSN_OR_1_D_INDIRECT_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_OR_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_OR_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_OR_1_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_1
48723 + , UBICOM32_INSN_OR_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_OR_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_OR_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_OR_1_D_INDIRECT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1
48724 + , UBICOM32_INSN_OR_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_OR_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_AND_1_D_DIRECT_S1_DIRECT, UBICOM32_INSN_AND_1_D_IMMEDIATE_1_S1_DIRECT
48725 + , UBICOM32_INSN_AND_1_D_INDIRECT_WITH_INDEX_1_S1_DIRECT, UBICOM32_INSN_AND_1_D_INDIRECT_WITH_OFFSET_1_S1_DIRECT, UBICOM32_INSN_AND_1_D_INDIRECT_1_S1_DIRECT, UBICOM32_INSN_AND_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_DIRECT
48726 + , UBICOM32_INSN_AND_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_DIRECT, UBICOM32_INSN_AND_1_D_DIRECT_S1_IMMEDIATE, UBICOM32_INSN_AND_1_D_IMMEDIATE_1_S1_IMMEDIATE, UBICOM32_INSN_AND_1_D_INDIRECT_WITH_INDEX_1_S1_IMMEDIATE
48727 + , UBICOM32_INSN_AND_1_D_INDIRECT_WITH_OFFSET_1_S1_IMMEDIATE, UBICOM32_INSN_AND_1_D_INDIRECT_1_S1_IMMEDIATE, UBICOM32_INSN_AND_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_IMMEDIATE, UBICOM32_INSN_AND_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_IMMEDIATE
48728 + , UBICOM32_INSN_AND_1_D_DIRECT_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_AND_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_AND_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_AND_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_INDEX_1
48729 + , UBICOM32_INSN_AND_1_D_INDIRECT_1_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_AND_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_AND_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_INDEX_1, UBICOM32_INSN_AND_1_D_DIRECT_S1_INDIRECT_WITH_OFFSET_1
48730 + , UBICOM32_INSN_AND_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_AND_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_AND_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_AND_1_D_INDIRECT_1_S1_INDIRECT_WITH_OFFSET_1
48731 + , UBICOM32_INSN_AND_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_AND_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_OFFSET_1, UBICOM32_INSN_AND_1_D_DIRECT_S1_INDIRECT_1, UBICOM32_INSN_AND_1_D_IMMEDIATE_1_S1_INDIRECT_1
48732 + , UBICOM32_INSN_AND_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_1, UBICOM32_INSN_AND_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_1, UBICOM32_INSN_AND_1_D_INDIRECT_1_S1_INDIRECT_1, UBICOM32_INSN_AND_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_1
48733 + , UBICOM32_INSN_AND_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_1, UBICOM32_INSN_AND_1_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_AND_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_AND_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_POST_INCREMENT_1
48734 + , UBICOM32_INSN_AND_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_AND_1_D_INDIRECT_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_AND_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_POST_INCREMENT_1, UBICOM32_INSN_AND_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_POST_INCREMENT_1
48735 + , UBICOM32_INSN_AND_1_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_AND_1_D_IMMEDIATE_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_AND_1_D_INDIRECT_WITH_INDEX_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_AND_1_D_INDIRECT_WITH_OFFSET_1_S1_INDIRECT_WITH_PRE_INCREMENT_1
48736 + , UBICOM32_INSN_AND_1_D_INDIRECT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_AND_1_D_INDIRECT_WITH_POST_INCREMENT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_AND_1_D_INDIRECT_WITH_PRE_INCREMENT_1_S1_INDIRECT_WITH_PRE_INCREMENT_1, UBICOM32_INSN_XOR_4_D_DIRECT_S1_DIRECT
48737 + , UBICOM32_INSN_XOR_4_D_IMMEDIATE_4_S1_DIRECT, UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_INDEX_4_S1_DIRECT, UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_OFFSET_4_S1_DIRECT, UBICOM32_INSN_XOR_4_D_INDIRECT_4_S1_DIRECT
48738 + , UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_DIRECT, UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_DIRECT, UBICOM32_INSN_XOR_4_D_DIRECT_S1_IMMEDIATE, UBICOM32_INSN_XOR_4_D_IMMEDIATE_4_S1_IMMEDIATE
48739 + , UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_INDEX_4_S1_IMMEDIATE, UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_OFFSET_4_S1_IMMEDIATE, UBICOM32_INSN_XOR_4_D_INDIRECT_4_S1_IMMEDIATE, UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_IMMEDIATE
48740 + , UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_IMMEDIATE, UBICOM32_INSN_XOR_4_D_DIRECT_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_XOR_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_INDEX_4
48741 + , UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_XOR_4_D_INDIRECT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4
48742 + , UBICOM32_INSN_XOR_4_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_XOR_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_OFFSET_4
48743 + , UBICOM32_INSN_XOR_4_D_INDIRECT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_XOR_4_D_DIRECT_S1_INDIRECT_4
48744 + , UBICOM32_INSN_XOR_4_D_IMMEDIATE_4_S1_INDIRECT_4, UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_4, UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_4, UBICOM32_INSN_XOR_4_D_INDIRECT_4_S1_INDIRECT_4
48745 + , UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_4, UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_4, UBICOM32_INSN_XOR_4_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_XOR_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_POST_INCREMENT_4
48746 + , UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_XOR_4_D_INDIRECT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4
48747 + , UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_XOR_4_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_XOR_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_PRE_INCREMENT_4
48748 + , UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_XOR_4_D_INDIRECT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_XOR_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4
48749 + , UBICOM32_INSN_XOR_2_D_DIRECT_S1_DIRECT, UBICOM32_INSN_XOR_2_D_IMMEDIATE_2_S1_DIRECT, UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_INDEX_2_S1_DIRECT, UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_OFFSET_2_S1_DIRECT
48750 + , UBICOM32_INSN_XOR_2_D_INDIRECT_2_S1_DIRECT, UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_DIRECT, UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_DIRECT, UBICOM32_INSN_XOR_2_D_DIRECT_S1_IMMEDIATE
48751 + , UBICOM32_INSN_XOR_2_D_IMMEDIATE_2_S1_IMMEDIATE, UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_INDEX_2_S1_IMMEDIATE, UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_OFFSET_2_S1_IMMEDIATE, UBICOM32_INSN_XOR_2_D_INDIRECT_2_S1_IMMEDIATE
48752 + , UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_IMMEDIATE, UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_IMMEDIATE, UBICOM32_INSN_XOR_2_D_DIRECT_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_XOR_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_INDEX_2
48753 + , UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_XOR_2_D_INDIRECT_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_INDEX_2
48754 + , UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_XOR_2_D_DIRECT_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_XOR_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_OFFSET_2
48755 + , UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_XOR_2_D_INDIRECT_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_2
48756 + , UBICOM32_INSN_XOR_2_D_DIRECT_S1_INDIRECT_2, UBICOM32_INSN_XOR_2_D_IMMEDIATE_2_S1_INDIRECT_2, UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_2, UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_2
48757 + , UBICOM32_INSN_XOR_2_D_INDIRECT_2_S1_INDIRECT_2, UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_2, UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_2, UBICOM32_INSN_XOR_2_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_2
48758 + , UBICOM32_INSN_XOR_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_XOR_2_D_INDIRECT_2_S1_INDIRECT_WITH_POST_INCREMENT_2
48759 + , UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_XOR_2_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_XOR_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_PRE_INCREMENT_2
48760 + , UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_XOR_2_D_INDIRECT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2
48761 + , UBICOM32_INSN_XOR_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_OR_4_D_DIRECT_S1_DIRECT, UBICOM32_INSN_OR_4_D_IMMEDIATE_4_S1_DIRECT, UBICOM32_INSN_OR_4_D_INDIRECT_WITH_INDEX_4_S1_DIRECT
48762 + , UBICOM32_INSN_OR_4_D_INDIRECT_WITH_OFFSET_4_S1_DIRECT, UBICOM32_INSN_OR_4_D_INDIRECT_4_S1_DIRECT, UBICOM32_INSN_OR_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_DIRECT, UBICOM32_INSN_OR_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_DIRECT
48763 + , UBICOM32_INSN_OR_4_D_DIRECT_S1_IMMEDIATE, UBICOM32_INSN_OR_4_D_IMMEDIATE_4_S1_IMMEDIATE, UBICOM32_INSN_OR_4_D_INDIRECT_WITH_INDEX_4_S1_IMMEDIATE, UBICOM32_INSN_OR_4_D_INDIRECT_WITH_OFFSET_4_S1_IMMEDIATE
48764 + , UBICOM32_INSN_OR_4_D_INDIRECT_4_S1_IMMEDIATE, UBICOM32_INSN_OR_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_IMMEDIATE, UBICOM32_INSN_OR_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_IMMEDIATE, UBICOM32_INSN_OR_4_D_DIRECT_S1_INDIRECT_WITH_INDEX_4
48765 + , UBICOM32_INSN_OR_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_OR_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_OR_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_OR_4_D_INDIRECT_4_S1_INDIRECT_WITH_INDEX_4
48766 + , UBICOM32_INSN_OR_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_OR_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_OR_4_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_OR_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_OFFSET_4
48767 + , UBICOM32_INSN_OR_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_OR_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_OR_4_D_INDIRECT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_OR_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4
48768 + , UBICOM32_INSN_OR_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_OR_4_D_DIRECT_S1_INDIRECT_4, UBICOM32_INSN_OR_4_D_IMMEDIATE_4_S1_INDIRECT_4, UBICOM32_INSN_OR_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_4
48769 + , UBICOM32_INSN_OR_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_4, UBICOM32_INSN_OR_4_D_INDIRECT_4_S1_INDIRECT_4, UBICOM32_INSN_OR_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_4, UBICOM32_INSN_OR_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_4
48770 + , UBICOM32_INSN_OR_4_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_OR_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_OR_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_OR_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_POST_INCREMENT_4
48771 + , UBICOM32_INSN_OR_4_D_INDIRECT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_OR_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_OR_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_OR_4_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4
48772 + , UBICOM32_INSN_OR_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_OR_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_OR_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_OR_4_D_INDIRECT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4
48773 + , UBICOM32_INSN_OR_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_OR_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_OR_2_D_DIRECT_S1_DIRECT, UBICOM32_INSN_OR_2_D_IMMEDIATE_2_S1_DIRECT
48774 + , UBICOM32_INSN_OR_2_D_INDIRECT_WITH_INDEX_2_S1_DIRECT, UBICOM32_INSN_OR_2_D_INDIRECT_WITH_OFFSET_2_S1_DIRECT, UBICOM32_INSN_OR_2_D_INDIRECT_2_S1_DIRECT, UBICOM32_INSN_OR_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_DIRECT
48775 + , UBICOM32_INSN_OR_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_DIRECT, UBICOM32_INSN_OR_2_D_DIRECT_S1_IMMEDIATE, UBICOM32_INSN_OR_2_D_IMMEDIATE_2_S1_IMMEDIATE, UBICOM32_INSN_OR_2_D_INDIRECT_WITH_INDEX_2_S1_IMMEDIATE
48776 + , UBICOM32_INSN_OR_2_D_INDIRECT_WITH_OFFSET_2_S1_IMMEDIATE, UBICOM32_INSN_OR_2_D_INDIRECT_2_S1_IMMEDIATE, UBICOM32_INSN_OR_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_IMMEDIATE, UBICOM32_INSN_OR_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_IMMEDIATE
48777 + , UBICOM32_INSN_OR_2_D_DIRECT_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_OR_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_OR_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_OR_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_INDEX_2
48778 + , UBICOM32_INSN_OR_2_D_INDIRECT_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_OR_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_OR_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_OR_2_D_DIRECT_S1_INDIRECT_WITH_OFFSET_2
48779 + , UBICOM32_INSN_OR_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_OR_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_OR_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_OR_2_D_INDIRECT_2_S1_INDIRECT_WITH_OFFSET_2
48780 + , UBICOM32_INSN_OR_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_OR_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_OR_2_D_DIRECT_S1_INDIRECT_2, UBICOM32_INSN_OR_2_D_IMMEDIATE_2_S1_INDIRECT_2
48781 + , UBICOM32_INSN_OR_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_2, UBICOM32_INSN_OR_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_2, UBICOM32_INSN_OR_2_D_INDIRECT_2_S1_INDIRECT_2, UBICOM32_INSN_OR_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_2
48782 + , UBICOM32_INSN_OR_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_2, UBICOM32_INSN_OR_2_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_OR_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_OR_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_POST_INCREMENT_2
48783 + , UBICOM32_INSN_OR_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_OR_2_D_INDIRECT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_OR_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_OR_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_2
48784 + , UBICOM32_INSN_OR_2_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_OR_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_OR_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_OR_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_PRE_INCREMENT_2
48785 + , UBICOM32_INSN_OR_2_D_INDIRECT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_OR_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_OR_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_AND_4_D_DIRECT_S1_DIRECT
48786 + , UBICOM32_INSN_AND_4_D_IMMEDIATE_4_S1_DIRECT, UBICOM32_INSN_AND_4_D_INDIRECT_WITH_INDEX_4_S1_DIRECT, UBICOM32_INSN_AND_4_D_INDIRECT_WITH_OFFSET_4_S1_DIRECT, UBICOM32_INSN_AND_4_D_INDIRECT_4_S1_DIRECT
48787 + , UBICOM32_INSN_AND_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_DIRECT, UBICOM32_INSN_AND_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_DIRECT, UBICOM32_INSN_AND_4_D_DIRECT_S1_IMMEDIATE, UBICOM32_INSN_AND_4_D_IMMEDIATE_4_S1_IMMEDIATE
48788 + , UBICOM32_INSN_AND_4_D_INDIRECT_WITH_INDEX_4_S1_IMMEDIATE, UBICOM32_INSN_AND_4_D_INDIRECT_WITH_OFFSET_4_S1_IMMEDIATE, UBICOM32_INSN_AND_4_D_INDIRECT_4_S1_IMMEDIATE, UBICOM32_INSN_AND_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_IMMEDIATE
48789 + , UBICOM32_INSN_AND_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_IMMEDIATE, UBICOM32_INSN_AND_4_D_DIRECT_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_AND_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_AND_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_INDEX_4
48790 + , UBICOM32_INSN_AND_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_AND_4_D_INDIRECT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_AND_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4, UBICOM32_INSN_AND_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_INDEX_4
48791 + , UBICOM32_INSN_AND_4_D_DIRECT_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_AND_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_AND_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_AND_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_OFFSET_4
48792 + , UBICOM32_INSN_AND_4_D_INDIRECT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_AND_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_AND_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_OFFSET_4, UBICOM32_INSN_AND_4_D_DIRECT_S1_INDIRECT_4
48793 + , UBICOM32_INSN_AND_4_D_IMMEDIATE_4_S1_INDIRECT_4, UBICOM32_INSN_AND_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_4, UBICOM32_INSN_AND_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_4, UBICOM32_INSN_AND_4_D_INDIRECT_4_S1_INDIRECT_4
48794 + , UBICOM32_INSN_AND_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_4, UBICOM32_INSN_AND_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_4, UBICOM32_INSN_AND_4_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_AND_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_POST_INCREMENT_4
48795 + , UBICOM32_INSN_AND_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_AND_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_AND_4_D_INDIRECT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_AND_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4
48796 + , UBICOM32_INSN_AND_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_POST_INCREMENT_4, UBICOM32_INSN_AND_4_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_AND_4_D_IMMEDIATE_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_AND_4_D_INDIRECT_WITH_INDEX_4_S1_INDIRECT_WITH_PRE_INCREMENT_4
48797 + , UBICOM32_INSN_AND_4_D_INDIRECT_WITH_OFFSET_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_AND_4_D_INDIRECT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_AND_4_D_INDIRECT_WITH_POST_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4, UBICOM32_INSN_AND_4_D_INDIRECT_WITH_PRE_INCREMENT_4_S1_INDIRECT_WITH_PRE_INCREMENT_4
48798 + , UBICOM32_INSN_AND_2_D_DIRECT_S1_DIRECT, UBICOM32_INSN_AND_2_D_IMMEDIATE_2_S1_DIRECT, UBICOM32_INSN_AND_2_D_INDIRECT_WITH_INDEX_2_S1_DIRECT, UBICOM32_INSN_AND_2_D_INDIRECT_WITH_OFFSET_2_S1_DIRECT
48799 + , UBICOM32_INSN_AND_2_D_INDIRECT_2_S1_DIRECT, UBICOM32_INSN_AND_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_DIRECT, UBICOM32_INSN_AND_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_DIRECT, UBICOM32_INSN_AND_2_D_DIRECT_S1_IMMEDIATE
48800 + , UBICOM32_INSN_AND_2_D_IMMEDIATE_2_S1_IMMEDIATE, UBICOM32_INSN_AND_2_D_INDIRECT_WITH_INDEX_2_S1_IMMEDIATE, UBICOM32_INSN_AND_2_D_INDIRECT_WITH_OFFSET_2_S1_IMMEDIATE, UBICOM32_INSN_AND_2_D_INDIRECT_2_S1_IMMEDIATE
48801 + , UBICOM32_INSN_AND_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_IMMEDIATE, UBICOM32_INSN_AND_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_IMMEDIATE, UBICOM32_INSN_AND_2_D_DIRECT_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_AND_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_INDEX_2
48802 + , UBICOM32_INSN_AND_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_AND_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_AND_2_D_INDIRECT_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_AND_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_INDEX_2
48803 + , UBICOM32_INSN_AND_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_INDEX_2, UBICOM32_INSN_AND_2_D_DIRECT_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_AND_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_AND_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_OFFSET_2
48804 + , UBICOM32_INSN_AND_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_AND_2_D_INDIRECT_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_AND_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_2, UBICOM32_INSN_AND_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_OFFSET_2
48805 + , UBICOM32_INSN_AND_2_D_DIRECT_S1_INDIRECT_2, UBICOM32_INSN_AND_2_D_IMMEDIATE_2_S1_INDIRECT_2, UBICOM32_INSN_AND_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_2, UBICOM32_INSN_AND_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_2
48806 + , UBICOM32_INSN_AND_2_D_INDIRECT_2_S1_INDIRECT_2, UBICOM32_INSN_AND_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_2, UBICOM32_INSN_AND_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_2, UBICOM32_INSN_AND_2_D_DIRECT_S1_INDIRECT_WITH_POST_INCREMENT_2
48807 + , UBICOM32_INSN_AND_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_AND_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_AND_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_AND_2_D_INDIRECT_2_S1_INDIRECT_WITH_POST_INCREMENT_2
48808 + , UBICOM32_INSN_AND_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_AND_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_POST_INCREMENT_2, UBICOM32_INSN_AND_2_D_DIRECT_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_AND_2_D_IMMEDIATE_2_S1_INDIRECT_WITH_PRE_INCREMENT_2
48809 + , UBICOM32_INSN_AND_2_D_INDIRECT_WITH_INDEX_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_AND_2_D_INDIRECT_WITH_OFFSET_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_AND_2_D_INDIRECT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_AND_2_D_INDIRECT_WITH_POST_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2
48810 + , UBICOM32_INSN_AND_2_D_INDIRECT_WITH_PRE_INCREMENT_2_S1_INDIRECT_WITH_PRE_INCREMENT_2, UBICOM32_INSN_MOVEAI, UBICOM32_INSN_NOP_INSN, UBICOM32_INSN_JMPCC
48811 + , UBICOM32_INSN_CALL, UBICOM32_INSN_CALLI, UBICOM32_INSN_SUSPEND, UBICOM32_INSN_DSP_CLRACC
48812 + , UBICOM32_INSN_UNUSED_00_11, UBICOM32_INSN_UNUSED_00_13, UBICOM32_INSN_UNUSED_00_14, UBICOM32_INSN_UNUSED_00_16
48813 + , UBICOM32_INSN_UNUSED_02_04, UBICOM32_INSN_UNUSED_02_07, UBICOM32_INSN_UNUSED_02_0D, UBICOM32_INSN_UNUSED_02_0E
48814 + , UBICOM32_INSN_UNUSED_02_0F, UBICOM32_INSN_UNUSED_02_17, UBICOM32_INSN_UNUSED_02_19, UBICOM32_INSN_UNUSED_02_1B
48815 + , UBICOM32_INSN_UNUSED_02_1D, UBICOM32_INSN_UNUSED_01, UBICOM32_INSN_UNUSED_03, UBICOM32_INSN_UNUSED_07
48816 + , UBICOM32_INSN_UNUSED_17, UBICOM32_INSN_UNUSED_1D, UBICOM32_INSN_UNUSED_1F, UBICOM32_INSN_UNUSED_DSP_06
48817 + , UBICOM32_INSN_UNUSED_DSP_0B, UBICOM32_INSN_UNUSED_DSP_0C, UBICOM32_INSN_UNUSED_DSP_0D, UBICOM32_INSN_UNUSED_DSP_0E
48818 + , UBICOM32_INSN_UNUSED_DSP_0F, UBICOM32_INSN_UNUSED_DSP_14, UBICOM32_INSN_UNUSED_DSP_15, UBICOM32_INSN_UNUSED_DSP_16
48819 + , UBICOM32_INSN_UNUSED_DSP_17, UBICOM32_INSN_UNUSED_DSP_18, UBICOM32_INSN_UNUSED_DSP_19, UBICOM32_INSN_UNUSED_DSP_1A
48820 + , UBICOM32_INSN_UNUSED_DSP_1B, UBICOM32_INSN_UNUSED_DSP_1C, UBICOM32_INSN_UNUSED_DSP_1D, UBICOM32_INSN_UNUSED_DSP_1E
48821 + , UBICOM32_INSN_UNUSED_DSP_1F
48822 +} CGEN_INSN_TYPE;
48823 +
48824 +/* Index of `invalid' insn place holder.  */
48825 +#define CGEN_INSN_INVALID UBICOM32_INSN_INVALID
48826 +
48827 +/* Total number of insns in table.  */
48828 +#define MAX_INSNS ((int) UBICOM32_INSN_UNUSED_DSP_1F + 1)
48829 +
48830 +/* This struct records data prior to insertion or after extraction.  */
48831 +struct cgen_fields
48832 +{
48833 +  int length;
48834 +  long f_nil;
48835 +  long f_anyof;
48836 +  long f_d;
48837 +  long f_d_bit10;
48838 +  long f_d_type;
48839 +  long f_d_r;
48840 +  long f_d_M;
48841 +  long f_d_i4_1;
48842 +  long f_d_i4_2;
48843 +  long f_d_i4_4;
48844 +  long f_d_An;
48845 +  long f_d_direct;
48846 +  long f_d_imm8;
48847 +  long f_d_imm7_t;
48848 +  long f_d_imm7_b;
48849 +  long f_d_imm7_1;
48850 +  long f_d_imm7_2;
48851 +  long f_d_imm7_4;
48852 +  long f_s1;
48853 +  long f_s1_bit10;
48854 +  long f_s1_type;
48855 +  long f_s1_r;
48856 +  long f_s1_M;
48857 +  long f_s1_i4_1;
48858 +  long f_s1_i4_2;
48859 +  long f_s1_i4_4;
48860 +  long f_s1_An;
48861 +  long f_s1_direct;
48862 +  long f_s1_imm8;
48863 +  long f_s1_imm7_t;
48864 +  long f_s1_imm7_b;
48865 +  long f_s1_imm7_1;
48866 +  long f_s1_imm7_2;
48867 +  long f_s1_imm7_4;
48868 +  long f_op1;
48869 +  long f_op2;
48870 +  long f_bit26;
48871 +  long f_opext;
48872 +  long f_cond;
48873 +  long f_imm16_1;
48874 +  long f_imm16_2;
48875 +  long f_o21;
48876 +  long f_o23_21;
48877 +  long f_o20_0;
48878 +  long f_o24;
48879 +  long f_imm23_21;
48880 +  long f_imm24;
48881 +  long f_o15_13;
48882 +  long f_o12_8;
48883 +  long f_o7_5;
48884 +  long f_o4_0;
48885 +  long f_o16;
48886 +  long f_An;
48887 +  long f_Am;
48888 +  long f_Dn;
48889 +  long f_bit5;
48890 +  long f_P;
48891 +  long f_C;
48892 +  long f_int;
48893 +  long f_dsp_C;
48894 +  long f_dsp_T;
48895 +  long f_dsp_S2_sel;
48896 +  long f_dsp_R;
48897 +  long f_dsp_destA;
48898 +  long f_dsp_b15;
48899 +  long f_dsp_S2;
48900 +  long f_dsp_J;
48901 +  long f_s2;
48902 +  long f_b15;
48903 +};
48904 +
48905 +#define CGEN_INIT_PARSE(od) \
48906 +{\
48907 +}
48908 +#define CGEN_INIT_INSERT(od) \
48909 +{\
48910 +}
48911 +#define CGEN_INIT_EXTRACT(od) \
48912 +{\
48913 +}
48914 +#define CGEN_INIT_PRINT(od) \
48915 +{\
48916 +}
48917 +
48918 +
48919 +#endif /* UBICOM32_OPC_H */
48920 --- /dev/null
48921 +++ b/ubicom32.exp
48922 @@ -0,0 +1,45 @@
48923 +# Expect control file for DEJAGNU test system and ubicom32
48924 +#
48925 +
48926 +# Needed for isnative.
48927 +load_lib "framework.exp"
48928 +
48929 +# Turn off plum-hall testing
48930 +#
48931 +set PLUMHALL no
48932 +set PLUMHALL_99b no
48933 +
48934 +# And Perennial too
48935 +set PERENNIAL_C no
48936 +set PERENNIAL_CLASSIC_C yes
48937 +
48938 +set UNDERSCORES yes
48939 +
48940 +if ![info exists tool] {
48941 +    set run_multiple_targets 0;
48942 +} elseif { $tool == "g++" || $tool == "gcc" || $tool == "gdb"} {
48943 +    set run_multiple_targets 1;
48944 +} else {
48945 +    set run_multiple_targets 0;
48946 +}
48947 +
48948 +verbose "Global Config FIle: target_triplet is $target_triplet" 2
48949 +global target_list
48950 +case "$target_triplet" in {
48951 +    { "ubicom32-*" } {
48952 +        set target_list "ubicom32-sid"
48953 +    }
48954 +
48955 +    { "ip3k-*" } {
48956 +        set target_list "ip3k-sid"
48957 +    }
48958 +
48959 +    default {
48960 +        set target_list { "unix" }
48961 +    }
48962 +}
48963 +
48964 +if { ! $run_multiple_targets } {
48965 +    set target_list [lindex $target_list 0];
48966 +}
48967 +