target/linux/xburst/patches-2.6.35/003-clock_api.patch

   1 From dd6ffa07b42d40ff680ce9bce34da88cf8920837 Mon Sep 17 00:00:00 2001
   2 From: Lars-Peter Clausen <lars@metafoo.de>
   3 Date: Sat, 17 Jul 2010 11:10:00 +0000
   4 Subject: [PATCH] MIPS: JZ4740: Add clock API support.
   5
   6 Add support for managing the clocks found on JZ4740 SoC through the
   7 Linux clock API.
   8
   9 Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
  10 Cc: linux-mips@linux-mips.org
  11 Cc: linux-kernel@vger.kernel.org
  12 Patchwork: https://patchwork.linux-mips.org/patch/1466/
  13 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
  14 ---
  15  arch/mips/include/asm/mach-jz4740/clock.h |   28 +
  16  arch/mips/jz4740/clock-debugfs.c          |  109 ++++
  17  arch/mips/jz4740/clock.c                  |  924 +++++++++++++++++++++++++++++
  18  arch/mips/jz4740/clock.h                  |   76 +++
  19  4 files changed, 1137 insertions(+), 0 deletions(-)
  20  create mode 100644 arch/mips/include/asm/mach-jz4740/clock.h
  21  create mode 100644 arch/mips/jz4740/clock-debugfs.c
  22  create mode 100644 arch/mips/jz4740/clock.c
  23  create mode 100644 arch/mips/jz4740/clock.h
  24
  25 --- /dev/null
  26 +++ b/arch/mips/include/asm/mach-jz4740/clock.h
  27 @@ -0,0 +1,28 @@
  28 +/*
  29 + *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
  30 + *
  31 + *  This program is free software; you can redistribute it and/or modify it
  32 + *  under  the terms of the GNU General  Public License as published by the
  33 + *  Free Software Foundation;  either version 2 of the License, or (at your
  34 + *  option) any later version.
  35 + *
  36 + *  You should have received a copy of the GNU General Public License along
  37 + *  with this program; if not, write to the Free Software Foundation, Inc.,
  38 + *  675 Mass Ave, Cambridge, MA 02139, USA.
  39 + *
  40 + */
  41 +
  42 +#ifndef __ASM_JZ4740_CLOCK_H__
  43 +#define __ASM_JZ4740_CLOCK_H__
  44 +
  45 +enum jz4740_wait_mode {
  46 +       JZ4740_WAIT_MODE_IDLE,
  47 +       JZ4740_WAIT_MODE_SLEEP,
  48 +};
  49 +
  50 +void jz4740_clock_set_wait_mode(enum jz4740_wait_mode mode);
  51 +
  52 +void jz4740_clock_udc_enable_auto_suspend(void);
  53 +void jz4740_clock_udc_disable_auto_suspend(void);
  54 +
  55 +#endif
  56 --- /dev/null
  57 +++ b/arch/mips/jz4740/clock-debugfs.c
  58 @@ -0,0 +1,109 @@
  59 +/*
  60 + *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
  61 + *  JZ4740 SoC clock support debugfs entries
  62 + *
  63 + *  This program is free software; you can redistribute it and/or modify it
  64 + *  under  the terms of the GNU General  Public License as published by the
  65 + *  Free Software Foundation;  either version 2 of the License, or (at your
  66 + *  option) any later version.
  67 + *
  68 + *  You should have received a copy of the GNU General Public License along
  69 + *  with this program; if not, write to the Free Software Foundation, Inc.,
  70 + *  675 Mass Ave, Cambridge, MA 02139, USA.
  71 + *
  72 + */
  73 +
  74 +#include <linux/kernel.h>
  75 +#include <linux/module.h>
  76 +#include <linux/clk.h>
  77 +#include <linux/err.h>
  78 +
  79 +#include <linux/debugfs.h>
  80 +#include <linux/uaccess.h>
  81 +
  82 +#include <asm/mach-jz4740/clock.h>
  83 +#include "clock.h"
  84 +
  85 +static struct dentry *jz4740_clock_debugfs;
  86 +
  87 +static int jz4740_clock_debugfs_show_enabled(void *data, uint64_t *value)
  88 +{
  89 +       struct clk *clk = data;
  90 +       *value = clk_is_enabled(clk);
  91 +
  92 +       return 0;
  93 +}
  94 +
  95 +static int jz4740_clock_debugfs_set_enabled(void *data, uint64_t value)
  96 +{
  97 +       struct clk *clk = data;
  98 +
  99 +       if (value)
 100 +               return clk_enable(clk);
 101 +       else
 102 +               clk_disable(clk);
 103 +
 104 +       return 0;
 105 +}
 106 +
 107 +DEFINE_SIMPLE_ATTRIBUTE(jz4740_clock_debugfs_ops_enabled,
 108 +       jz4740_clock_debugfs_show_enabled,
 109 +       jz4740_clock_debugfs_set_enabled,
 110 +       "%llu\n");
 111 +
 112 +static int jz4740_clock_debugfs_show_rate(void *data, uint64_t *value)
 113 +{
 114 +       struct clk *clk = data;
 115 +       *value = clk_get_rate(clk);
 116 +
 117 +       return 0;
 118 +}
 119 +
 120 +DEFINE_SIMPLE_ATTRIBUTE(jz4740_clock_debugfs_ops_rate,
 121 +       jz4740_clock_debugfs_show_rate,
 122 +       NULL,
 123 +       "%llu\n");
 124 +
 125 +void jz4740_clock_debugfs_add_clk(struct clk *clk)
 126 +{
 127 +       if (!jz4740_clock_debugfs)
 128 +               return;
 129 +
 130 +       clk->debugfs_entry = debugfs_create_dir(clk->name, jz4740_clock_debugfs);
 131 +       debugfs_create_file("rate", S_IWUGO | S_IRUGO, clk->debugfs_entry, clk,
 132 +                               &jz4740_clock_debugfs_ops_rate);
 133 +       debugfs_create_file("enabled", S_IRUGO, clk->debugfs_entry, clk,
 134 +                               &jz4740_clock_debugfs_ops_enabled);
 135 +
 136 +       if (clk->parent) {
 137 +               char parent_path[100];
 138 +               snprintf(parent_path, 100, "../%s", clk->parent->name);
 139 +               clk->debugfs_parent_entry = debugfs_create_symlink("parent",
 140 +                                               clk->debugfs_entry,
 141 +                                               parent_path);
 142 +       }
 143 +}
 144 +
 145 +/* TODO: Locking */
 146 +void jz4740_clock_debugfs_update_parent(struct clk *clk)
 147 +{
 148 +       if (clk->debugfs_parent_entry)
 149 +               debugfs_remove(clk->debugfs_parent_entry);
 150 +
 151 +       if (clk->parent) {
 152 +               char parent_path[100];
 153 +               snprintf(parent_path, 100, "../%s", clk->parent->name);
 154 +               clk->debugfs_parent_entry = debugfs_create_symlink("parent",
 155 +                                               clk->debugfs_entry,
 156 +                                               parent_path);
 157 +       } else {
 158 +               clk->debugfs_parent_entry = NULL;
 159 +       }
 160 +}
 161 +
 162 +void jz4740_clock_debugfs_init(void)
 163 +{
 164 +       jz4740_clock_debugfs = debugfs_create_dir("jz4740-clock", NULL);
 165 +       if (IS_ERR(jz4740_clock_debugfs))
 166 +               jz4740_clock_debugfs = NULL;
 167 +}
 168 --- /dev/null
 169 +++ b/arch/mips/jz4740/clock.c
 170 @@ -0,0 +1,924 @@
 171 +/*
 172 + *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
 173 + *  JZ4740 SoC clock support
 174 + *
 175 + *  This program is free software; you can redistribute it and/or modify it
 176 + *  under  the terms of the GNU General  Public License as published by the
 177 + *  Free Software Foundation;  either version 2 of the License, or (at your
 178 + *  option) any later version.
 179 + *
 180 + *  You should have received a copy of the GNU General Public License along
 181 + *  with this program; if not, write to the Free Software Foundation, Inc.,
 182 + *  675 Mass Ave, Cambridge, MA 02139, USA.
 183 + *
 184 + */
 185 +
 186 +#include <linux/kernel.h>
 187 +#include <linux/errno.h>
 188 +#include <linux/clk.h>
 189 +#include <linux/spinlock.h>
 190 +#include <linux/io.h>
 191 +#include <linux/module.h>
 192 +#include <linux/list.h>
 193 +#include <linux/err.h>
 194 +
 195 +#include <asm/mach-jz4740/clock.h>
 196 +#include <asm/mach-jz4740/base.h>
 197 +
 198 +#include "clock.h"
 199 +
 200 +#define JZ_REG_CLOCK_CTRL      0x00
 201 +#define JZ_REG_CLOCK_LOW_POWER 0x04
 202 +#define JZ_REG_CLOCK_PLL       0x10
 203 +#define JZ_REG_CLOCK_GATE      0x20
 204 +#define JZ_REG_CLOCK_SLEEP_CTRL        0x24
 205 +#define JZ_REG_CLOCK_I2S       0x60
 206 +#define JZ_REG_CLOCK_LCD       0x64
 207 +#define JZ_REG_CLOCK_MMC       0x68
 208 +#define JZ_REG_CLOCK_UHC       0x6C
 209 +#define JZ_REG_CLOCK_SPI       0x74
 210 +
 211 +#define JZ_CLOCK_CTRL_I2S_SRC_PLL      BIT(31)
 212 +#define JZ_CLOCK_CTRL_KO_ENABLE                BIT(30)
 213 +#define JZ_CLOCK_CTRL_UDC_SRC_PLL      BIT(29)
 214 +#define JZ_CLOCK_CTRL_UDIV_MASK                0x1f800000
 215 +#define JZ_CLOCK_CTRL_CHANGE_ENABLE    BIT(22)
 216 +#define JZ_CLOCK_CTRL_PLL_HALF         BIT(21)
 217 +#define JZ_CLOCK_CTRL_LDIV_MASK                0x001f0000
 218 +#define JZ_CLOCK_CTRL_UDIV_OFFSET      23
 219 +#define JZ_CLOCK_CTRL_LDIV_OFFSET      16
 220 +#define JZ_CLOCK_CTRL_MDIV_OFFSET      12
 221 +#define JZ_CLOCK_CTRL_PDIV_OFFSET       8
 222 +#define JZ_CLOCK_CTRL_HDIV_OFFSET       4
 223 +#define JZ_CLOCK_CTRL_CDIV_OFFSET       0
 224 +
 225 +#define JZ_CLOCK_GATE_UART0    BIT(0)
 226 +#define JZ_CLOCK_GATE_TCU      BIT(1)
 227 +#define JZ_CLOCK_GATE_RTC      BIT(2)
 228 +#define JZ_CLOCK_GATE_I2C      BIT(3)
 229 +#define JZ_CLOCK_GATE_SPI      BIT(4)
 230 +#define JZ_CLOCK_GATE_AIC      BIT(5)
 231 +#define JZ_CLOCK_GATE_I2S      BIT(6)
 232 +#define JZ_CLOCK_GATE_MMC      BIT(7)
 233 +#define JZ_CLOCK_GATE_ADC      BIT(8)
 234 +#define JZ_CLOCK_GATE_CIM      BIT(9)
 235 +#define JZ_CLOCK_GATE_LCD      BIT(10)
 236 +#define JZ_CLOCK_GATE_UDC      BIT(11)
 237 +#define JZ_CLOCK_GATE_DMAC     BIT(12)
 238 +#define JZ_CLOCK_GATE_IPU      BIT(13)
 239 +#define JZ_CLOCK_GATE_UHC      BIT(14)
 240 +#define JZ_CLOCK_GATE_UART1    BIT(15)
 241 +
 242 +#define JZ_CLOCK_I2S_DIV_MASK          0x01ff
 243 +
 244 +#define JZ_CLOCK_LCD_DIV_MASK          0x01ff
 245 +
 246 +#define JZ_CLOCK_MMC_DIV_MASK          0x001f
 247 +
 248 +#define JZ_CLOCK_UHC_DIV_MASK          0x000f
 249 +
 250 +#define JZ_CLOCK_SPI_SRC_PLL           BIT(31)
 251 +#define JZ_CLOCK_SPI_DIV_MASK          0x000f
 252 +
 253 +#define JZ_CLOCK_PLL_M_MASK            0x01ff
 254 +#define JZ_CLOCK_PLL_N_MASK            0x001f
 255 +#define JZ_CLOCK_PLL_OD_MASK           0x0003
 256 +#define JZ_CLOCK_PLL_STABLE            BIT(10)
 257 +#define JZ_CLOCK_PLL_BYPASS            BIT(9)
 258 +#define JZ_CLOCK_PLL_ENABLED           BIT(8)
 259 +#define JZ_CLOCK_PLL_STABLIZE_MASK     0x000f
 260 +#define JZ_CLOCK_PLL_M_OFFSET          23
 261 +#define JZ_CLOCK_PLL_N_OFFSET          18
 262 +#define JZ_CLOCK_PLL_OD_OFFSET         16
 263 +
 264 +#define JZ_CLOCK_LOW_POWER_MODE_DOZE BIT(2)
 265 +#define JZ_CLOCK_LOW_POWER_MODE_SLEEP BIT(0)
 266 +
 267 +#define JZ_CLOCK_SLEEP_CTRL_SUSPEND_UHC BIT(7)
 268 +#define JZ_CLOCK_SLEEP_CTRL_ENABLE_UDC BIT(6)
 269 +
 270 +static void __iomem *jz_clock_base;
 271 +static spinlock_t jz_clock_lock;
 272 +static LIST_HEAD(jz_clocks);
 273 +
 274 +struct main_clk {
 275 +       struct clk clk;
 276 +       uint32_t div_offset;
 277 +};
 278 +
 279 +struct divided_clk {
 280 +       struct clk clk;
 281 +       uint32_t reg;
 282 +       uint32_t mask;
 283 +};
 284 +
 285 +struct static_clk {
 286 +       struct clk clk;
 287 +       unsigned long rate;
 288 +};
 289 +
 290 +static uint32_t jz_clk_reg_read(int reg)
 291 +{
 292 +       return readl(jz_clock_base + reg);
 293 +}
 294 +
 295 +static void jz_clk_reg_write_mask(int reg, uint32_t val, uint32_t mask)
 296 +{
 297 +       uint32_t val2;
 298 +
 299 +       spin_lock(&jz_clock_lock);
 300 +       val2 = readl(jz_clock_base + reg);
 301 +       val2 &= ~mask;
 302 +       val2 |= val;
 303 +       writel(val2, jz_clock_base + reg);
 304 +       spin_unlock(&jz_clock_lock);
 305 +}
 306 +
 307 +static void jz_clk_reg_set_bits(int reg, uint32_t mask)
 308 +{
 309 +       uint32_t val;
 310 +
 311 +       spin_lock(&jz_clock_lock);
 312 +       val = readl(jz_clock_base + reg);
 313 +       val |= mask;
 314 +       writel(val, jz_clock_base + reg);
 315 +       spin_unlock(&jz_clock_lock);
 316 +}
 317 +
 318 +static void jz_clk_reg_clear_bits(int reg, uint32_t mask)
 319 +{
 320 +       uint32_t val;
 321 +
 322 +       spin_lock(&jz_clock_lock);
 323 +       val = readl(jz_clock_base + reg);
 324 +       val &= ~mask;
 325 +       writel(val, jz_clock_base + reg);
 326 +       spin_unlock(&jz_clock_lock);
 327 +}
 328 +
 329 +static int jz_clk_enable_gating(struct clk *clk)
 330 +{
 331 +       if (clk->gate_bit == JZ4740_CLK_NOT_GATED)
 332 +               return -EINVAL;
 333 +
 334 +       jz_clk_reg_clear_bits(JZ_REG_CLOCK_GATE, clk->gate_bit);
 335 +       return 0;
 336 +}
 337 +
 338 +static int jz_clk_disable_gating(struct clk *clk)
 339 +{
 340 +       if (clk->gate_bit == JZ4740_CLK_NOT_GATED)
 341 +               return -EINVAL;
 342 +
 343 +       jz_clk_reg_set_bits(JZ_REG_CLOCK_GATE, clk->gate_bit);
 344 +       return 0;
 345 +}
 346 +
 347 +static int jz_clk_is_enabled_gating(struct clk *clk)
 348 +{
 349 +       if (clk->gate_bit == JZ4740_CLK_NOT_GATED)
 350 +               return 1;
 351 +
 352 +       return !(jz_clk_reg_read(JZ_REG_CLOCK_GATE) & clk->gate_bit);
 353 +}
 354 +
 355 +static unsigned long jz_clk_static_get_rate(struct clk *clk)
 356 +{
 357 +       return ((struct static_clk *)clk)->rate;
 358 +}
 359 +
 360 +static int jz_clk_ko_enable(struct clk *clk)
 361 +{
 362 +       jz_clk_reg_set_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_KO_ENABLE);
 363 +       return 0;
 364 +}
 365 +
 366 +static int jz_clk_ko_disable(struct clk *clk)
 367 +{
 368 +       jz_clk_reg_clear_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_KO_ENABLE);
 369 +       return 0;
 370 +}
 371 +
 372 +static int jz_clk_ko_is_enabled(struct clk *clk)
 373 +{
 374 +       return !!(jz_clk_reg_read(JZ_REG_CLOCK_CTRL) & JZ_CLOCK_CTRL_KO_ENABLE);
 375 +}
 376 +
 377 +static const int pllno[] = {1, 2, 2, 4};
 378 +
 379 +static unsigned long jz_clk_pll_get_rate(struct clk *clk)
 380 +{
 381 +       uint32_t val;
 382 +       int m;
 383 +       int n;
 384 +       int od;
 385 +
 386 +       val = jz_clk_reg_read(JZ_REG_CLOCK_PLL);
 387 +
 388 +       if (val & JZ_CLOCK_PLL_BYPASS)
 389 +               return clk_get_rate(clk->parent);
 390 +
 391 +       m = ((val >> 23) & 0x1ff) + 2;
 392 +       n = ((val >> 18) & 0x1f) + 2;
 393 +       od = (val >> 16) & 0x3;
 394 +
 395 +       return ((clk_get_rate(clk->parent) / n) * m) / pllno[od];
 396 +}
 397 +
 398 +static unsigned long jz_clk_pll_half_get_rate(struct clk *clk)
 399 +{
 400 +       uint32_t reg;
 401 +
 402 +       reg = jz_clk_reg_read(JZ_REG_CLOCK_CTRL);
 403 +       if (reg & JZ_CLOCK_CTRL_PLL_HALF)
 404 +               return jz_clk_pll_get_rate(clk->parent);
 405 +       return jz_clk_pll_get_rate(clk->parent) >> 1;
 406 +}
 407 +
 408 +static const int jz_clk_main_divs[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
 409 +
 410 +static unsigned long jz_clk_main_round_rate(struct clk *clk, unsigned long rate)
 411 +{
 412 +       unsigned long parent_rate = jz_clk_pll_get_rate(clk->parent);
 413 +       int div;
 414 +
 415 +       div = parent_rate / rate;
 416 +       if (div > 32)
 417 +               return parent_rate / 32;
 418 +       else if (div < 1)
 419 +               return parent_rate;
 420 +
 421 +       div &= (0x3 << (ffs(div) - 1));
 422 +
 423 +       return parent_rate / div;
 424 +}
 425 +
 426 +static unsigned long jz_clk_main_get_rate(struct clk *clk)
 427 +{
 428 +       struct main_clk *mclk = (struct main_clk *)clk;
 429 +       uint32_t div;
 430 +
 431 +       div = jz_clk_reg_read(JZ_REG_CLOCK_CTRL);
 432 +
 433 +       div >>= mclk->div_offset;
 434 +       div &= 0xf;
 435 +
 436 +       if (div >= ARRAY_SIZE(jz_clk_main_divs))
 437 +               div = ARRAY_SIZE(jz_clk_main_divs) - 1;
 438 +
 439 +       return jz_clk_pll_get_rate(clk->parent) / jz_clk_main_divs[div];
 440 +}
 441 +
 442 +static int jz_clk_main_set_rate(struct clk *clk, unsigned long rate)
 443 +{
 444 +       struct main_clk *mclk = (struct main_clk *)clk;
 445 +       int i;
 446 +       int div;
 447 +       unsigned long parent_rate = jz_clk_pll_get_rate(clk->parent);
 448 +
 449 +       rate = jz_clk_main_round_rate(clk, rate);
 450 +
 451 +       div = parent_rate / rate;
 452 +
 453 +       i = (ffs(div) - 1) << 1;
 454 +       if (i > 0 && !(div & BIT(i-1)))
 455 +               i -= 1;
 456 +
 457 +       jz_clk_reg_write_mask(JZ_REG_CLOCK_CTRL, i << mclk->div_offset,
 458 +                               0xf << mclk->div_offset);
 459 +
 460 +       return 0;
 461 +}
 462 +
 463 +static struct clk_ops jz_clk_static_ops = {
 464 +       .get_rate = jz_clk_static_get_rate,
 465 +       .enable = jz_clk_enable_gating,
 466 +       .disable = jz_clk_disable_gating,
 467 +       .is_enabled = jz_clk_is_enabled_gating,
 468 +};
 469 +
 470 +static struct static_clk jz_clk_ext = {
 471 +       .clk = {
 472 +               .name = "ext",
 473 +               .gate_bit = JZ4740_CLK_NOT_GATED,
 474 +               .ops = &jz_clk_static_ops,
 475 +       },
 476 +};
 477 +
 478 +static struct clk_ops jz_clk_pll_ops = {
 479 +       .get_rate = jz_clk_pll_get_rate,
 480 +};
 481 +
 482 +static struct clk jz_clk_pll = {
 483 +       .name = "pll",
 484 +       .parent = &jz_clk_ext.clk,
 485 +       .ops = &jz_clk_pll_ops,
 486 +};
 487 +
 488 +static struct clk_ops jz_clk_pll_half_ops = {
 489 +       .get_rate = jz_clk_pll_half_get_rate,
 490 +};
 491 +
 492 +static struct clk jz_clk_pll_half = {
 493 +       .name = "pll half",
 494 +       .parent = &jz_clk_pll,
 495 +       .ops = &jz_clk_pll_half_ops,
 496 +};
 497 +
 498 +static const struct clk_ops jz_clk_main_ops = {
 499 +       .get_rate = jz_clk_main_get_rate,
 500 +       .set_rate = jz_clk_main_set_rate,
 501 +       .round_rate = jz_clk_main_round_rate,
 502 +};
 503 +
 504 +static struct main_clk jz_clk_cpu = {
 505 +       .clk = {
 506 +               .name = "cclk",
 507 +               .parent = &jz_clk_pll,
 508 +               .ops = &jz_clk_main_ops,
 509 +       },
 510 +       .div_offset = JZ_CLOCK_CTRL_CDIV_OFFSET,
 511 +};
 512 +
 513 +static struct main_clk jz_clk_memory = {
 514 +       .clk = {
 515 +               .name = "mclk",
 516 +               .parent = &jz_clk_pll,
 517 +               .ops = &jz_clk_main_ops,
 518 +       },
 519 +       .div_offset = JZ_CLOCK_CTRL_MDIV_OFFSET,
 520 +};
 521 +
 522 +static struct main_clk jz_clk_high_speed_peripheral = {
 523 +       .clk = {
 524 +               .name = "hclk",
 525 +               .parent = &jz_clk_pll,
 526 +               .ops = &jz_clk_main_ops,
 527 +       },
 528 +       .div_offset = JZ_CLOCK_CTRL_HDIV_OFFSET,
 529 +};
 530 +
 531 +
 532 +static struct main_clk jz_clk_low_speed_peripheral = {
 533 +       .clk = {
 534 +               .name = "pclk",
 535 +               .parent = &jz_clk_pll,
 536 +               .ops = &jz_clk_main_ops,
 537 +       },
 538 +       .div_offset = JZ_CLOCK_CTRL_PDIV_OFFSET,
 539 +};
 540 +
 541 +static const struct clk_ops jz_clk_ko_ops = {
 542 +       .enable = jz_clk_ko_enable,
 543 +       .disable = jz_clk_ko_disable,
 544 +       .is_enabled = jz_clk_ko_is_enabled,
 545 +};
 546 +
 547 +static struct clk jz_clk_ko = {
 548 +       .name = "cko",
 549 +       .parent = &jz_clk_memory.clk,
 550 +       .ops = &jz_clk_ko_ops,
 551 +};
 552 +
 553 +static int jz_clk_spi_set_parent(struct clk *clk, struct clk *parent)
 554 +{
 555 +       if (parent == &jz_clk_pll)
 556 +               jz_clk_reg_set_bits(JZ_CLOCK_SPI_SRC_PLL, JZ_REG_CLOCK_SPI);
 557 +       else if (parent == &jz_clk_ext.clk)
 558 +               jz_clk_reg_clear_bits(JZ_CLOCK_SPI_SRC_PLL, JZ_REG_CLOCK_SPI);
 559 +       else
 560 +               return -EINVAL;
 561 +
 562 +       clk->parent = parent;
 563 +
 564 +       return 0;
 565 +}
 566 +
 567 +static int jz_clk_i2s_set_parent(struct clk *clk, struct clk *parent)
 568 +{
 569 +       if (parent == &jz_clk_pll_half)
 570 +               jz_clk_reg_set_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_I2S_SRC_PLL);
 571 +       else if (parent == &jz_clk_ext.clk)
 572 +               jz_clk_reg_clear_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_I2S_SRC_PLL);
 573 +       else
 574 +               return -EINVAL;
 575 +
 576 +       clk->parent = parent;
 577 +
 578 +       return 0;
 579 +}
 580 +
 581 +static int jz_clk_udc_enable(struct clk *clk)
 582 +{
 583 +       jz_clk_reg_set_bits(JZ_REG_CLOCK_SLEEP_CTRL,
 584 +                       JZ_CLOCK_SLEEP_CTRL_ENABLE_UDC);
 585 +
 586 +       return 0;
 587 +}
 588 +
 589 +static int jz_clk_udc_disable(struct clk *clk)
 590 +{
 591 +       jz_clk_reg_clear_bits(JZ_REG_CLOCK_SLEEP_CTRL,
 592 +                       JZ_CLOCK_SLEEP_CTRL_ENABLE_UDC);
 593 +
 594 +       return 0;
 595 +}
 596 +
 597 +static int jz_clk_udc_is_enabled(struct clk *clk)
 598 +{
 599 +       return !!(jz_clk_reg_read(JZ_REG_CLOCK_SLEEP_CTRL) &
 600 +                       JZ_CLOCK_SLEEP_CTRL_ENABLE_UDC);
 601 +}
 602 +
 603 +static int jz_clk_udc_set_parent(struct clk *clk, struct clk *parent)
 604 +{
 605 +       if (parent == &jz_clk_pll_half)
 606 +               jz_clk_reg_set_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_UDC_SRC_PLL);
 607 +       else if (parent == &jz_clk_ext.clk)
 608 +               jz_clk_reg_clear_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_UDC_SRC_PLL);
 609 +       else
 610 +               return -EINVAL;
 611 +
 612 +       clk->parent = parent;
 613 +
 614 +       return 0;
 615 +}
 616 +
 617 +static int jz_clk_udc_set_rate(struct clk *clk, unsigned long rate)
 618 +{
 619 +       int div;
 620 +
 621 +       if (clk->parent == &jz_clk_ext.clk)
 622 +               return -EINVAL;
 623 +
 624 +       div = clk_get_rate(clk->parent) / rate - 1;
 625 +
 626 +       if (div < 0)
 627 +               div = 0;
 628 +       else if (div > 63)
 629 +               div = 63;
 630 +
 631 +       jz_clk_reg_write_mask(JZ_REG_CLOCK_CTRL, div << JZ_CLOCK_CTRL_UDIV_OFFSET,
 632 +                               JZ_CLOCK_CTRL_UDIV_MASK);
 633 +       return 0;
 634 +}
 635 +
 636 +static unsigned long jz_clk_udc_get_rate(struct clk *clk)
 637 +{
 638 +       int div;
 639 +
 640 +       if (clk->parent == &jz_clk_ext.clk)
 641 +               return clk_get_rate(clk->parent);
 642 +
 643 +       div = (jz_clk_reg_read(JZ_REG_CLOCK_CTRL) & JZ_CLOCK_CTRL_UDIV_MASK);
 644 +       div >>= JZ_CLOCK_CTRL_UDIV_OFFSET;
 645 +       div += 1;
 646 +
 647 +       return clk_get_rate(clk->parent) / div;
 648 +}
 649 +
 650 +static unsigned long jz_clk_divided_get_rate(struct clk *clk)
 651 +{
 652 +       struct divided_clk *dclk = (struct divided_clk *)clk;
 653 +       int div;
 654 +
 655 +       if (clk->parent == &jz_clk_ext.clk)
 656 +               return clk_get_rate(clk->parent);
 657 +
 658 +       div = (jz_clk_reg_read(dclk->reg) & dclk->mask) + 1;
 659 +
 660 +       return clk_get_rate(clk->parent) / div;
 661 +}
 662 +
 663 +static int jz_clk_divided_set_rate(struct clk *clk, unsigned long rate)
 664 +{
 665 +       struct divided_clk *dclk = (struct divided_clk *)clk;
 666 +       int div;
 667 +
 668 +       if (clk->parent == &jz_clk_ext.clk)
 669 +               return -EINVAL;
 670 +
 671 +       div = clk_get_rate(clk->parent) / rate - 1;
 672 +
 673 +       if (div < 0)
 674 +               div = 0;
 675 +       else if (div > dclk->mask)
 676 +               div = dclk->mask;
 677 +
 678 +       jz_clk_reg_write_mask(dclk->reg, div, dclk->mask);
 679 +
 680 +       return 0;
 681 +}
 682 +
 683 +static unsigned long jz_clk_ldclk_round_rate(struct clk *clk, unsigned long rate)
 684 +{
 685 +       int div;
 686 +       unsigned long parent_rate = jz_clk_pll_half_get_rate(clk->parent);
 687 +
 688 +       if (rate > 150000000)
 689 +               return 150000000;
 690 +
 691 +       div = parent_rate / rate;
 692 +       if (div < 1)
 693 +               div = 1;
 694 +       else if (div > 32)
 695 +               div = 32;
 696 +
 697 +       return parent_rate / div;
 698 +}
 699 +
 700 +static int jz_clk_ldclk_set_rate(struct clk *clk, unsigned long rate)
 701 +{
 702 +       int div;
 703 +
 704 +       if (rate > 150000000)
 705 +               return -EINVAL;
 706 +
 707 +       div = jz_clk_pll_half_get_rate(clk->parent) / rate - 1;
 708 +       if (div < 0)
 709 +               div = 0;
 710 +       else if (div > 31)
 711 +               div = 31;
 712 +
 713 +       jz_clk_reg_write_mask(JZ_REG_CLOCK_CTRL, div << JZ_CLOCK_CTRL_LDIV_OFFSET,
 714 +                               JZ_CLOCK_CTRL_LDIV_MASK);
 715 +
 716 +       return 0;
 717 +}
 718 +
 719 +static unsigned long jz_clk_ldclk_get_rate(struct clk *clk)
 720 +{
 721 +       int div;
 722 +
 723 +       div = jz_clk_reg_read(JZ_REG_CLOCK_CTRL) & JZ_CLOCK_CTRL_LDIV_MASK;
 724 +       div >>= JZ_CLOCK_CTRL_LDIV_OFFSET;
 725 +
 726 +       return jz_clk_pll_half_get_rate(clk->parent) / (div + 1);
 727 +}
 728 +
 729 +static const struct clk_ops jz_clk_ops_ld = {
 730 +       .set_rate = jz_clk_ldclk_set_rate,
 731 +       .get_rate = jz_clk_ldclk_get_rate,
 732 +       .round_rate = jz_clk_ldclk_round_rate,
 733 +       .enable = jz_clk_enable_gating,
 734 +       .disable = jz_clk_disable_gating,
 735 +       .is_enabled = jz_clk_is_enabled_gating,
 736 +};
 737 +
 738 +static struct clk jz_clk_ld = {
 739 +       .name = "lcd",
 740 +       .gate_bit = JZ_CLOCK_GATE_LCD,
 741 +       .parent = &jz_clk_pll_half,
 742 +       .ops = &jz_clk_ops_ld,
 743 +};
 744 +
 745 +static const struct clk_ops jz_clk_i2s_ops = {
 746 +       .set_rate = jz_clk_divided_set_rate,
 747 +       .get_rate = jz_clk_divided_get_rate,
 748 +       .enable = jz_clk_enable_gating,
 749 +       .disable = jz_clk_disable_gating,
 750 +       .is_enabled = jz_clk_is_enabled_gating,
 751 +       .set_parent = jz_clk_i2s_set_parent,
 752 +};
 753 +
 754 +static const struct clk_ops jz_clk_spi_ops = {
 755 +       .set_rate = jz_clk_divided_set_rate,
 756 +       .get_rate = jz_clk_divided_get_rate,
 757 +       .enable = jz_clk_enable_gating,
 758 +       .disable = jz_clk_disable_gating,
 759 +       .is_enabled = jz_clk_is_enabled_gating,
 760 +       .set_parent = jz_clk_spi_set_parent,
 761 +};
 762 +
 763 +static const struct clk_ops jz_clk_divided_ops = {
 764 +       .set_rate = jz_clk_divided_set_rate,
 765 +       .get_rate = jz_clk_divided_get_rate,
 766 +       .enable = jz_clk_enable_gating,
 767 +       .disable = jz_clk_disable_gating,
 768 +       .is_enabled = jz_clk_is_enabled_gating,
 769 +};
 770 +
 771 +static struct divided_clk jz4740_clock_divided_clks[] = {
 772 +       [0] = {
 773 +               .clk = {
 774 +                       .name = "i2s",
 775 +                       .parent = &jz_clk_ext.clk,
 776 +                       .gate_bit = JZ_CLOCK_GATE_I2S,
 777 +                       .ops = &jz_clk_i2s_ops,
 778 +               },
 779 +               .reg = JZ_REG_CLOCK_I2S,
 780 +               .mask = JZ_CLOCK_I2S_DIV_MASK,
 781 +       },
 782 +       [1] = {
 783 +               .clk = {
 784 +                       .name = "spi",
 785 +                       .parent = &jz_clk_ext.clk,
 786 +                       .gate_bit = JZ_CLOCK_GATE_SPI,
 787 +                       .ops = &jz_clk_spi_ops,
 788 +               },
 789 +               .reg = JZ_REG_CLOCK_SPI,
 790 +               .mask = JZ_CLOCK_SPI_DIV_MASK,
 791 +       },
 792 +       [2] = {
 793 +               .clk = {
 794 +                       .name = "lcd_pclk",
 795 +                       .parent = &jz_clk_pll_half,
 796 +                       .gate_bit = JZ4740_CLK_NOT_GATED,
 797 +                       .ops = &jz_clk_divided_ops,
 798 +               },
 799 +               .reg = JZ_REG_CLOCK_LCD,
 800 +               .mask = JZ_CLOCK_LCD_DIV_MASK,
 801 +       },
 802 +       [3] = {
 803 +               .clk = {
 804 +                       .name = "mmc",
 805 +                       .parent = &jz_clk_pll_half,
 806 +                       .gate_bit = JZ_CLOCK_GATE_MMC,
 807 +                       .ops = &jz_clk_divided_ops,
 808 +               },
 809 +               .reg = JZ_REG_CLOCK_MMC,
 810 +               .mask = JZ_CLOCK_MMC_DIV_MASK,
 811 +       },
 812 +       [4] = {
 813 +               .clk = {
 814 +                       .name = "uhc",
 815 +                       .parent = &jz_clk_pll_half,
 816 +                       .gate_bit = JZ_CLOCK_GATE_UHC,
 817 +                       .ops = &jz_clk_divided_ops,
 818 +               },
 819 +               .reg = JZ_REG_CLOCK_UHC,
 820 +               .mask = JZ_CLOCK_UHC_DIV_MASK,
 821 +       },
 822 +};
 823 +
 824 +static const struct clk_ops jz_clk_udc_ops = {
 825 +       .set_parent = jz_clk_udc_set_parent,
 826 +       .set_rate = jz_clk_udc_set_rate,
 827 +       .get_rate = jz_clk_udc_get_rate,
 828 +       .enable = jz_clk_udc_enable,
 829 +       .disable = jz_clk_udc_disable,
 830 +       .is_enabled = jz_clk_udc_is_enabled,
 831 +};
 832 +
 833 +static const struct clk_ops jz_clk_simple_ops = {
 834 +       .enable = jz_clk_enable_gating,
 835 +       .disable = jz_clk_disable_gating,
 836 +       .is_enabled = jz_clk_is_enabled_gating,
 837 +};
 838 +
 839 +static struct clk jz4740_clock_simple_clks[] = {
 840 +       [0] = {
 841 +               .name = "udc",
 842 +               .parent = &jz_clk_ext.clk,
 843 +               .ops = &jz_clk_udc_ops,
 844 +       },
 845 +       [1] = {
 846 +               .name = "uart0",
 847 +               .parent = &jz_clk_ext.clk,
 848 +               .gate_bit = JZ_CLOCK_GATE_UART0,
 849 +               .ops = &jz_clk_simple_ops,
 850 +       },
 851 +       [2] = {
 852 +               .name = "uart1",
 853 +               .parent = &jz_clk_ext.clk,
 854 +               .gate_bit = JZ_CLOCK_GATE_UART1,
 855 +               .ops = &jz_clk_simple_ops,
 856 +       },
 857 +       [3] = {
 858 +               .name = "dma",
 859 +               .parent = &jz_clk_high_speed_peripheral.clk,
 860 +               .gate_bit = JZ_CLOCK_GATE_UART0,
 861 +               .ops = &jz_clk_simple_ops,
 862 +       },
 863 +       [4] = {
 864 +               .name = "ipu",
 865 +               .parent = &jz_clk_high_speed_peripheral.clk,
 866 +               .gate_bit = JZ_CLOCK_GATE_IPU,
 867 +               .ops = &jz_clk_simple_ops,
 868 +       },
 869 +       [5] = {
 870 +               .name = "adc",
 871 +               .parent = &jz_clk_ext.clk,
 872 +               .gate_bit = JZ_CLOCK_GATE_ADC,
 873 +               .ops = &jz_clk_simple_ops,
 874 +       },
 875 +       [6] = {
 876 +               .name = "i2c",
 877 +               .parent = &jz_clk_ext.clk,
 878 +               .gate_bit = JZ_CLOCK_GATE_I2C,
 879 +               .ops = &jz_clk_simple_ops,
 880 +       },
 881 +       [7] = {
 882 +               .name = "aic",
 883 +               .parent = &jz_clk_ext.clk,
 884 +               .gate_bit = JZ_CLOCK_GATE_AIC,
 885 +               .ops = &jz_clk_simple_ops,
 886 +       },
 887 +};
 888 +
 889 +static struct static_clk jz_clk_rtc = {
 890 +       .clk = {
 891 +               .name = "rtc",
 892 +               .gate_bit = JZ_CLOCK_GATE_RTC,
 893 +               .ops = &jz_clk_static_ops,
 894 +       },
 895 +       .rate = 32768,
 896 +};
 897 +
 898 +int clk_enable(struct clk *clk)
 899 +{
 900 +       if (!clk->ops->enable)
 901 +               return -EINVAL;
 902 +
 903 +       return clk->ops->enable(clk);
 904 +}
 905 +EXPORT_SYMBOL_GPL(clk_enable);
 906 +
 907 +void clk_disable(struct clk *clk)
 908 +{
 909 +       if (clk->ops->disable)
 910 +               clk->ops->disable(clk);
 911 +}
 912 +EXPORT_SYMBOL_GPL(clk_disable);
 913 +
 914 +int clk_is_enabled(struct clk *clk)
 915 +{
 916 +       if (clk->ops->is_enabled)
 917 +               return clk->ops->is_enabled(clk);
 918 +
 919 +       return 1;
 920 +}
 921 +
 922 +unsigned long clk_get_rate(struct clk *clk)
 923 +{
 924 +       if (clk->ops->get_rate)
 925 +               return clk->ops->get_rate(clk);
 926 +       if (clk->parent)
 927 +               return clk_get_rate(clk->parent);
 928 +
 929 +       return -EINVAL;
 930 +}
 931 +EXPORT_SYMBOL_GPL(clk_get_rate);
 932 +
 933 +int clk_set_rate(struct clk *clk, unsigned long rate)
 934 +{
 935 +       if (!clk->ops->set_rate)
 936 +               return -EINVAL;
 937 +       return clk->ops->set_rate(clk, rate);
 938 +}
 939 +EXPORT_SYMBOL_GPL(clk_set_rate);
 940 +
 941 +long clk_round_rate(struct clk *clk, unsigned long rate)
 942 +{
 943 +       if (clk->ops->round_rate)
 944 +               return clk->ops->round_rate(clk, rate);
 945 +
 946 +       return -EINVAL;
 947 +}
 948 +EXPORT_SYMBOL_GPL(clk_round_rate);
 949 +
 950 +int clk_set_parent(struct clk *clk, struct clk *parent)
 951 +{
 952 +       int ret;
 953 +       int enabled;
 954 +
 955 +       if (!clk->ops->set_parent)
 956 +               return -EINVAL;
 957 +
 958 +       enabled = clk_is_enabled(clk);
 959 +       if (enabled)
 960 +               clk_disable(clk);
 961 +       ret = clk->ops->set_parent(clk, parent);
 962 +       if (enabled)
 963 +               clk_enable(clk);
 964 +
 965 +       jz4740_clock_debugfs_update_parent(clk);
 966 +
 967 +       return ret;
 968 +}
 969 +EXPORT_SYMBOL_GPL(clk_set_parent);
 970 +
 971 +struct clk *clk_get(struct device *dev, const char *name)
 972 +{
 973 +       struct clk *clk;
 974 +
 975 +       list_for_each_entry(clk, &jz_clocks, list) {
 976 +               if (strcmp(clk->name, name) == 0)
 977 +                       return clk;
 978 +       }
 979 +       return ERR_PTR(-ENXIO);
 980 +}
 981 +EXPORT_SYMBOL_GPL(clk_get);
 982 +
 983 +void clk_put(struct clk *clk)
 984 +{
 985 +}
 986 +EXPORT_SYMBOL_GPL(clk_put);
 987 +
 988 +static inline void clk_add(struct clk *clk)
 989 +{
 990 +       list_add_tail(&clk->list, &jz_clocks);
 991 +
 992 +       jz4740_clock_debugfs_add_clk(clk);
 993 +}
 994 +
 995 +static void clk_register_clks(void)
 996 +{
 997 +       size_t i;
 998 +
 999 +       clk_add(&jz_clk_ext.clk);
1000 +       clk_add(&jz_clk_pll);
1001 +       clk_add(&jz_clk_pll_half);
1002 +       clk_add(&jz_clk_cpu.clk);
1003 +       clk_add(&jz_clk_high_speed_peripheral.clk);
1004 +       clk_add(&jz_clk_low_speed_peripheral.clk);
1005 +       clk_add(&jz_clk_ko);
1006 +       clk_add(&jz_clk_ld);
1007 +       clk_add(&jz_clk_rtc.clk);
1008 +
1009 +       for (i = 0; i < ARRAY_SIZE(jz4740_clock_divided_clks); ++i)
1010 +               clk_add(&jz4740_clock_divided_clks[i].clk);
1011 +
1012 +       for (i = 0; i < ARRAY_SIZE(jz4740_clock_simple_clks); ++i)
1013 +               clk_add(&jz4740_clock_simple_clks[i]);
1014 +}
1015 +
1016 +void jz4740_clock_set_wait_mode(enum jz4740_wait_mode mode)
1017 +{
1018 +       switch (mode) {
1019 +       case JZ4740_WAIT_MODE_IDLE:
1020 +               jz_clk_reg_clear_bits(JZ_REG_CLOCK_LOW_POWER, JZ_CLOCK_LOW_POWER_MODE_SLEEP);
1021 +               break;
1022 +       case JZ4740_WAIT_MODE_SLEEP:
1023 +               jz_clk_reg_set_bits(JZ_REG_CLOCK_LOW_POWER, JZ_CLOCK_LOW_POWER_MODE_SLEEP);
1024 +               break;
1025 +       }
1026 +}
1027 +
1028 +void jz4740_clock_udc_disable_auto_suspend(void)
1029 +{
1030 +       jz_clk_reg_clear_bits(JZ_REG_CLOCK_GATE, JZ_CLOCK_GATE_UDC);
1031 +}
1032 +EXPORT_SYMBOL_GPL(jz4740_clock_udc_disable_auto_suspend);
1033 +
1034 +void jz4740_clock_udc_enable_auto_suspend(void)
1035 +{
1036 +       jz_clk_reg_set_bits(JZ_REG_CLOCK_GATE, JZ_CLOCK_GATE_UDC);
1037 +}
1038 +EXPORT_SYMBOL_GPL(jz4740_clock_udc_enable_auto_suspend);
1039 +
1040 +void jz4740_clock_suspend(void)
1041 +{
1042 +       jz_clk_reg_set_bits(JZ_REG_CLOCK_GATE,
1043 +               JZ_CLOCK_GATE_TCU | JZ_CLOCK_GATE_DMAC | JZ_CLOCK_GATE_UART0);
1044 +
1045 +       jz_clk_reg_clear_bits(JZ_REG_CLOCK_PLL, JZ_CLOCK_PLL_ENABLED);
1046 +}
1047 +
1048 +void jz4740_clock_resume(void)
1049 +{
1050 +       uint32_t pll;
1051 +
1052 +       jz_clk_reg_set_bits(JZ_REG_CLOCK_PLL, JZ_CLOCK_PLL_ENABLED);
1053 +
1054 +       do {
1055 +               pll = jz_clk_reg_read(JZ_REG_CLOCK_PLL);
1056 +       } while (!(pll & JZ_CLOCK_PLL_STABLE));
1057 +
1058 +       jz_clk_reg_clear_bits(JZ_REG_CLOCK_GATE,
1059 +               JZ_CLOCK_GATE_TCU | JZ_CLOCK_GATE_DMAC | JZ_CLOCK_GATE_UART0);
1060 +}
1061 +
1062 +static int jz4740_clock_init(void)
1063 +{
1064 +       uint32_t val;
1065 +
1066 +       jz_clock_base = ioremap(JZ4740_CPM_BASE_ADDR, 0x100);
1067 +       if (!jz_clock_base)
1068 +               return -EBUSY;
1069 +
1070 +       spin_lock_init(&jz_clock_lock);
1071 +
1072 +       jz_clk_ext.rate = jz4740_clock_bdata.ext_rate;
1073 +       jz_clk_rtc.rate = jz4740_clock_bdata.rtc_rate;
1074 +
1075 +       val = jz_clk_reg_read(JZ_REG_CLOCK_SPI);
1076 +
1077 +       if (val & JZ_CLOCK_SPI_SRC_PLL)
1078 +               jz4740_clock_divided_clks[1].clk.parent = &jz_clk_pll_half;
1079 +
1080 +       val = jz_clk_reg_read(JZ_REG_CLOCK_CTRL);
1081 +
1082 +       if (val & JZ_CLOCK_CTRL_I2S_SRC_PLL)
1083 +               jz4740_clock_divided_clks[0].clk.parent = &jz_clk_pll_half;
1084 +
1085 +       if (val & JZ_CLOCK_CTRL_UDC_SRC_PLL)
1086 +               jz4740_clock_simple_clks[0].parent = &jz_clk_pll_half;
1087 +
1088 +       jz4740_clock_debugfs_init();
1089 +
1090 +       clk_register_clks();
1091 +
1092 +       return 0;
1093 +}
1094 +arch_initcall(jz4740_clock_init);
1095 --- /dev/null
1096 +++ b/arch/mips/jz4740/clock.h
1097 @@ -0,0 +1,76 @@
1098 +/*
1099 + *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
1100 + *  JZ4740 SoC clock support
1101 + *
1102 + *  This program is free software; you can redistribute         it and/or modify it
1103 + *  under  the terms of         the GNU General  Public License as published by the
1104 + *  Free Software Foundation;  either version 2 of the License, or (at your
1105 + *  option) any later version.
1106 + *
1107 + *  You should have received a copy of the  GNU General Public License along
1108 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
1109 + *  675 Mass Ave, Cambridge, MA 02139, USA.
1110 + *
1111 + */
1112 +
1113 +#ifndef __MIPS_JZ4740_CLOCK_H__
1114 +#define __MIPS_JZ4740_CLOCK_H__
1115 +
1116 +#include <linux/list.h>
1117 +
1118 +struct jz4740_clock_board_data {
1119 +       unsigned long ext_rate;
1120 +       unsigned long rtc_rate;
1121 +};
1122 +
1123 +extern struct jz4740_clock_board_data jz4740_clock_bdata;
1124 +
1125 +void jz4740_clock_suspend(void);
1126 +void jz4740_clock_resume(void);
1127 +
1128 +struct clk;
1129 +
1130 +struct clk_ops {
1131 +       unsigned long (*get_rate)(struct clk *clk);
1132 +       unsigned long (*round_rate)(struct clk *clk, unsigned long rate);
1133 +       int (*set_rate)(struct clk *clk, unsigned long rate);
1134 +       int (*enable)(struct clk *clk);
1135 +       int (*disable)(struct clk *clk);
1136 +       int (*is_enabled)(struct clk *clk);
1137 +
1138 +       int (*set_parent)(struct clk *clk, struct clk *parent);
1139 +
1140 +};
1141 +
1142 +struct clk {
1143 +       const char *name;
1144 +       struct clk *parent;
1145 +
1146 +       uint32_t gate_bit;
1147 +
1148 +       const struct clk_ops *ops;
1149 +
1150 +       struct list_head list;
1151 +
1152 +#ifdef CONFIG_DEBUG_FS
1153 +       struct dentry *debugfs_entry;
1154 +       struct dentry *debugfs_parent_entry;
1155 +#endif
1156 +
1157 +};
1158 +
1159 +#define JZ4740_CLK_NOT_GATED ((uint32_t)-1)
1160 +
1161 +int clk_is_enabled(struct clk *clk);
1162 +
1163 +#ifdef CONFIG_DEBUG_FS
1164 +void jz4740_clock_debugfs_init(void);
1165 +void jz4740_clock_debugfs_add_clk(struct clk *clk);
1166 +void jz4740_clock_debugfs_update_parent(struct clk *clk);
1167 +#else
1168 +static inline void jz4740_clock_debugfs_init(void) {};
1169 +static inline void jz4740_clock_debugfs_add_clk(struct clk *clk) {};
1170 +static inline void jz4740_clock_debugfs_update_parent(struct clk *clk) {};
1171 +#endif
1172 +
1173 +#endif