target/linux/xburst/files-2.6.32/drivers/mtd/nand/jz4740_nand.c

   1 /*
   2  *  Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
   3  *      JZ4720/JZ4740 SoC NAND controller driver
   4  *
   5  *  This program is free software; you can redistribute  it and/or modify it
   6  *  under  the terms of  the GNU General  Public License as published by the
   7  *  Free Software Foundation;  either version 2 of the  License, or (at your
   8  *  option) any later version.
   9  *
  10  *  You should have received a copy of the  GNU General Public License along
  11  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  12  *  675 Mass Ave, Cambridge, MA 02139, USA.
  13  *
  14  */
  15
  16 #include <linux/ioport.h>
  17 #include <linux/platform_device.h>
  18
  19 #include <linux/mtd/mtd.h>
  20 #include <linux/mtd/nand.h>
  21 #include <linux/mtd/partitions.h>
  22
  23 #include <linux/mtd/jz4740_nand.h>
  24 #include <linux/gpio.h>
  25
  26 #define JZ_REG_NAND_CTRL        0x50
  27 #define JZ_REG_NAND_ECC_CTRL    0x100
  28 #define JZ_REG_NAND_DATA        0x104
  29 #define JZ_REG_NAND_PAR0        0x108
  30 #define JZ_REG_NAND_PAR1        0x10C
  31 #define JZ_REG_NAND_PAR2        0x110
  32 #define JZ_REG_NAND_IRQ_STAT    0x114
  33 #define JZ_REG_NAND_IRQ_CTRL    0x118
  34 #define JZ_REG_NAND_ERR(x)      (0x11C + (x << 2))
  35
  36 #define JZ_NAND_ECC_CTRL_PAR_READY      BIT(4)
  37 #define JZ_NAND_ECC_CTRL_ENCODING       BIT(3)
  38 #define JZ_NAND_ECC_CTRL_RS             BIT(2)
  39 #define JZ_NAND_ECC_CTRL_RESET          BIT(1)
  40 #define JZ_NAND_ECC_CTRL_ENABLE         BIT(0)
  41
  42 #define JZ_NAND_STATUS_ERR_COUNT        (BIT(31) | BIT(30) | BIT(29))
  43 #define JZ_NAND_STATUS_PAD_FINISH       BIT(4)
  44 #define JZ_NAND_STATUS_DEC_FINISH       BIT(3)
  45 #define JZ_NAND_STATUS_ENC_FINISH       BIT(2)
  46 #define JZ_NAND_STATUS_UNCOR_ERROR      BIT(1)
  47 #define JZ_NAND_STATUS_ERROR            BIT(0)
  48
  49 #define JZ_NAND_CTRL_ENABLE_CHIP(x) BIT(x << 1)
  50 #define JZ_NAND_CTRL_ASSERT_CHIP(x) BIT((x << 1) + 1)
  51
  52 #define JZ_NAND_DATA_ADDR ((void __iomem *)0xB8000000)
  53 #define JZ_NAND_CMD_ADDR (JZ_NAND_DATA_ADDR + 0x8000)
  54 #define JZ_NAND_ADDR_ADDR (JZ_NAND_DATA_ADDR + 0x10000)
  55
  56 struct jz_nand {
  57         struct mtd_info mtd;
  58         struct nand_chip chip;
  59         void __iomem *base;
  60         struct resource *mem;
  61
  62         struct jz_nand_platform_data *pdata;
  63 };
  64
  65 static inline struct jz_nand *mtd_to_jz_nand(struct mtd_info *mtd)
  66 {
  67         return container_of(mtd, struct jz_nand, mtd);
  68 }
  69
  70 static void jz_nand_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl)
  71 {
  72         struct jz_nand *nand = mtd_to_jz_nand(mtd);
  73         struct nand_chip *chip = mtd->priv;
  74         uint32_t reg;
  75
  76         if (ctrl & NAND_CTRL_CHANGE) {
  77                 BUG_ON((ctrl & NAND_ALE) && (ctrl & NAND_CLE));
  78                 if (ctrl & NAND_ALE)
  79                         chip->IO_ADDR_W = JZ_NAND_ADDR_ADDR;
  80                 else if (ctrl & NAND_CLE)
  81                         chip->IO_ADDR_W = JZ_NAND_CMD_ADDR;
  82                 else
  83                         chip->IO_ADDR_W = JZ_NAND_DATA_ADDR;
  84
  85                 reg = readl(nand->base + JZ_REG_NAND_CTRL);
  86                 if ( ctrl & NAND_NCE )
  87                         reg |= JZ_NAND_CTRL_ASSERT_CHIP(0);
  88                 else
  89                         reg &= ~JZ_NAND_CTRL_ASSERT_CHIP(0);
  90                 writel(reg, nand->base + JZ_REG_NAND_CTRL);
  91         }
  92         if (dat != NAND_CMD_NONE)
  93                 writeb(dat, chip->IO_ADDR_W);
  94 }
  95
  96 static int jz_nand_dev_ready(struct mtd_info *mtd)
  97 {
  98         struct jz_nand *nand = mtd_to_jz_nand(mtd);
  99         return gpio_get_value_cansleep(nand->pdata->busy_gpio);
 100 }
 101
 102 static void jz_nand_hwctl(struct mtd_info *mtd, int mode)
 103 {
 104         struct jz_nand *nand = mtd_to_jz_nand(mtd);
 105         uint32_t reg;
 106
 107
 108         writel(0, nand->base + JZ_REG_NAND_IRQ_STAT);
 109         reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
 110
 111         reg |= JZ_NAND_ECC_CTRL_RESET;
 112         reg |= JZ_NAND_ECC_CTRL_ENABLE;
 113         reg |= JZ_NAND_ECC_CTRL_RS;
 114
 115         switch(mode) {
 116         case NAND_ECC_READ:
 117                 reg &= ~JZ_NAND_ECC_CTRL_ENCODING;
 118                 break;
 119         case NAND_ECC_WRITE:
 120                 reg |= JZ_NAND_ECC_CTRL_ENCODING;
 121                 break;
 122         default:
 123                 break;
 124         }
 125
 126         writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
 127 }
 128
 129 static int jz_nand_calculate_ecc_rs(struct mtd_info* mtd, const uint8_t* dat,
 130                                         uint8_t *ecc_code)
 131 {
 132         struct jz_nand *nand = mtd_to_jz_nand(mtd);
 133         uint32_t reg, status;
 134         int i;
 135
 136         do {
 137                 status = readl(nand->base + JZ_REG_NAND_IRQ_STAT);
 138         } while(!(status & JZ_NAND_STATUS_ENC_FINISH));
 139
 140         reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
 141         reg &= ~JZ_NAND_ECC_CTRL_ENABLE;
 142         writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
 143
 144         for (i = 0; i < 9; ++i) {
 145                 ecc_code[i] = readb(nand->base + JZ_REG_NAND_PAR0 + i);
 146         }
 147
 148         return 0;
 149 }
 150
 151 static void correct_data(uint8_t *dat, int index, int mask)
 152 {
 153         int offset = index & 0x7;
 154         uint16_t data;
 155         printk("correct: ");
 156
 157         index += (index >> 3);
 158
 159         data = dat[index];
 160         data |= dat[index+1] << 8;
 161
 162         printk("0x%x -> ", data);
 163
 164         mask ^= (data >> offset) & 0x1ff;
 165         data &= ~(0x1ff << offset);
 166         data |= (mask << offset);
 167
 168         printk("0x%x\n", data);
 169
 170         dat[index] = data & 0xff;
 171         dat[index+1] = (data >> 8) & 0xff;
 172 }
 173
 174 static int jz_nand_correct_ecc_rs(struct mtd_info* mtd, uint8_t *dat,
 175                                   uint8_t *read_ecc, uint8_t *calc_ecc)
 176 {
 177         struct jz_nand *nand = mtd_to_jz_nand(mtd);
 178         int i, error_count, index;
 179         uint32_t reg, status, error;
 180
 181         for(i = 0; i < 9; ++i) {
 182                 if (read_ecc[i] != 0xff)
 183                         break;
 184         }
 185         if (i == 9) {
 186                 for (i = 0; i < nand->chip.ecc.size; ++i) {
 187                         if (dat[i] != 0xff)
 188                                 break;
 189                 }
 190                 if (i == nand->chip.ecc.size)
 191                         return 0;
 192         }
 193
 194         for(i = 0; i < 9; ++i)
 195                 writeb(read_ecc[i], nand->base + JZ_REG_NAND_PAR0 + i);
 196
 197         reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
 198         reg |= JZ_NAND_ECC_CTRL_PAR_READY;
 199         writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
 200
 201         do {
 202                 status = readl(nand->base + JZ_REG_NAND_IRQ_STAT);
 203         } while (!(status & JZ_NAND_STATUS_DEC_FINISH));
 204
 205         reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
 206         reg &= ~JZ_NAND_ECC_CTRL_ENABLE;
 207         writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
 208
 209         if (status & JZ_NAND_STATUS_ERROR) {
 210                 if (status & JZ_NAND_STATUS_UNCOR_ERROR) {
 211                         printk("uncorrectable ecc:");
 212                         for(i = 0; i < 9; ++i)
 213                                 printk(" 0x%x", read_ecc[i]);
 214                         printk("\n");
 215                         printk("uncorrectable data:");
 216                         for(i = 0; i < 32; ++i)
 217                                 printk(" 0x%x", dat[i]);
 218                         printk("\n");
 219                         return -1;
 220                 }
 221
 222                 error_count = (status & JZ_NAND_STATUS_ERR_COUNT) >> 29;
 223
 224                 printk("error_count: %d %x\n", error_count, status);
 225
 226                 for(i = 0; i < error_count; ++i) {
 227                         error = readl(nand->base + JZ_REG_NAND_ERR(i));
 228                         index = ((error >> 16) & 0x1ff) - 1;
 229                         if (index >= 0 && index < 512) {
 230                                 correct_data(dat, index, error & 0x1ff);
 231                         }
 232                 }
 233
 234                 return error_count;
 235         }
 236
 237         return 0;
 238 }
 239
 240
 241
 242 #ifdef CONFIG_MTD_CMDLINE_PARTS
 243 static const char *part_probes[] = {"cmdline", NULL};
 244 #endif
 245
 246 static int __devinit jz_nand_probe(struct platform_device *pdev)
 247 {
 248         int ret;
 249         struct jz_nand *nand;
 250         struct nand_chip *chip;
 251         struct mtd_info *mtd;
 252         struct jz_nand_platform_data *pdata = pdev->dev.platform_data;
 253 #ifdef CONFIG_MTD_PARTITIONS
 254         struct mtd_partition *partition_info;
 255         int num_partitions = 0;
 256 #endif
 257
 258         nand = kzalloc(sizeof(*nand), GFP_KERNEL);
 259         if (!nand) {
 260                 dev_err(&pdev->dev, "Failed to allocate device structure.\n");
 261                 return -ENOMEM;
 262         }
 263
 264         nand->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 265         if (!nand->mem) {
 266                 dev_err(&pdev->dev, "Failed to get platform mmio memory\n");
 267                 ret = -ENOENT;
 268                 goto err_free;
 269         }
 270
 271         nand->mem = request_mem_region(nand->mem->start, resource_size(nand->mem),
 272                                         pdev->name);
 273
 274         if (!nand->mem) {
 275                 dev_err(&pdev->dev, "Failed to request mmio memory region\n");
 276                 ret = -EBUSY;
 277                 goto err_free;
 278         }
 279
 280         nand->base = ioremap(nand->mem->start, resource_size(nand->mem));
 281
 282         if (!nand->base) {
 283                 dev_err(&pdev->dev, "Faild to ioremap mmio memory region\n");
 284                 ret = -EBUSY;
 285                 goto err_release_mem;
 286         }
 287
 288         if (pdata && gpio_is_valid(pdata->busy_gpio)) {
 289                 ret = gpio_request(pdata->busy_gpio, "jz nand busy line");
 290                 if (ret) {
 291                         dev_err(&pdev->dev, "Failed to request busy gpio %d: %d\n",
 292                                         pdata->busy_gpio, ret);
 293                         goto err_iounmap;
 294                 }
 295         }
 296
 297         mtd             = &nand->mtd;
 298         chip            = &nand->chip;
 299         mtd->priv       = chip;
 300         mtd->owner      = THIS_MODULE;
 301         mtd->name       = "jz4740-nand";
 302
 303         chip->ecc.hwctl         = jz_nand_hwctl;
 304
 305         chip->ecc.calculate     = jz_nand_calculate_ecc_rs;
 306         chip->ecc.correct       = jz_nand_correct_ecc_rs;
 307         chip->ecc.mode          = NAND_ECC_HW;
 308         chip->ecc.size          = 512;
 309         chip->ecc.bytes         = 9;
 310         if (pdata)
 311                 chip->ecc.layout = pdata->ecc_layout;
 312
 313         chip->chip_delay = 50;
 314         chip->cmd_ctrl = jz_nand_cmd_ctrl;
 315
 316         if (pdata && gpio_is_valid(pdata->busy_gpio))
 317                 chip->dev_ready = jz_nand_dev_ready;
 318
 319         chip->IO_ADDR_R = JZ_NAND_DATA_ADDR;
 320         chip->IO_ADDR_W = JZ_NAND_DATA_ADDR;
 321
 322         nand->pdata = pdata;
 323         platform_set_drvdata(pdev, nand);
 324
 325         ret = nand_scan_ident(mtd, 1);
 326         if (ret) {
 327                 dev_err(&pdev->dev,  "Failed to scan nand\n");
 328                 goto err_gpio_free;
 329         }
 330
 331         if (pdata && pdata->ident_callback) {
 332                 pdata->ident_callback(pdev, chip, &pdata->partitions, &pdata->num_partitions);
 333         }
 334
 335         ret = nand_scan_tail(mtd);
 336         if (ret) {
 337                 dev_err(&pdev->dev,  "Failed to scan nand\n");
 338                 goto err_gpio_free;
 339         }
 340
 341 #ifdef CONFIG_MTD_PARTITIONS
 342 #ifdef CONFIG_MTD_CMDLINE_PARTS
 343         num_partitions = parse_mtd_partitions(mtd, part_probes,
 344                                                 &partition_info, 0);
 345 #endif
 346         if (num_partitions <= 0 && pdata) {
 347                 num_partitions = pdata->num_partitions;
 348                 partition_info = pdata->partitions;
 349         }
 350
 351         if (num_partitions > 0)
 352                 ret = add_mtd_partitions(mtd, partition_info, num_partitions);
 353         else
 354 #endif
 355         ret = add_mtd_device(mtd);
 356
 357         if (ret) {
 358                 dev_err(&pdev->dev, "Failed to add mtd device\n");
 359                 goto err_nand_release;
 360         }
 361
 362         dev_info(&pdev->dev, "Successfully registered JZ4740 NAND driver\n");
 363
 364         return 0;
 365 err_nand_release:
 366         nand_release(&nand->mtd);
 367 err_gpio_free:
 368         platform_set_drvdata(pdev, NULL);
 369         gpio_free(pdata->busy_gpio);
 370 err_iounmap:
 371         iounmap(nand->base);
 372 err_release_mem:
 373         release_mem_region(nand->mem->start, resource_size(nand->mem));
 374 err_free:
 375         kfree(nand);
 376         return ret;
 377 }
 378
 379 static void __devexit jz_nand_remove(struct platform_device *pdev)
 380 {
 381         struct jz_nand *nand = platform_get_drvdata(pdev);
 382
 383         nand_release(&nand->mtd);
 384
 385         iounmap(nand->base);
 386
 387         release_mem_region(nand->mem->start, resource_size(nand->mem));
 388
 389         platform_set_drvdata(pdev, NULL);
 390         kfree(nand);
 391 }
 392
 393 struct platform_driver jz_nand_driver = {
 394         .probe = jz_nand_probe,
 395         .remove = __devexit_p(jz_nand_probe),
 396         .driver = {
 397                 .name = "jz4740-nand",
 398                 .owner = THIS_MODULE,
 399         },
 400 };
 401
 402 static int __init jz_nand_init(void)
 403 {
 404         return platform_driver_register(&jz_nand_driver);
 405 }
 406 module_init(jz_nand_init);
 407
 408 static void __exit jz_nand_exit(void)
 409 {
 410         platform_driver_unregister(&jz_nand_driver);
 411 }
 412 module_exit(jz_nand_exit);
 413
 414 MODULE_LICENSE("GPL");
 415 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
 416 MODULE_DESCRIPTION("NAND controller driver for JZ4720/JZ4740 SoC");
 417 MODULE_ALIAS("platform:jz4740-nand");
 418 MODULE_ALIAS("platform:jz4720-nand");