target/linux/sunxi/patches-4.4/103-clk-sunxi-add-h3-clksupport.patch

   1 From ab6e23a4e388f5f2696b8e92c350f845142da118 Mon Sep 17 00:00:00 2001
   2 From: Jens Kuske <jenskuske@gmail.com>
   3 Date: Fri, 4 Dec 2015 22:24:40 +0100
   4 Subject: [PATCH] clk: sunxi: Add H3 clocks support
   5
   6 The H3 clock control unit is similar to the those of other sun8i family
   7 members like the A23.
   8
   9 It adds a new bus gates clock similar to the simple gates, but with a
  10 different parent clock for each single gate.
  11 Some of the gates use the new AHB2 clock as parent, whose clock source
  12 is muxable between AHB1 and PLL6/2. The documentation isn't totally clear
  13 about which devices belong to AHB2 now, especially USB EHIC/OHIC, so it
  14 is mostly based on Allwinner kernel source code.
  15
  16 Signed-off-by: Jens Kuske <jenskuske@gmail.com>
  17 Acked-by: Rob Herring <robh@kernel.org>
  18 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  19 ---
  20  Documentation/devicetree/bindings/clock/sunxi.txt |   2 +
  21  drivers/clk/sunxi/Makefile                        |   1 +
  22  drivers/clk/sunxi/clk-sun8i-bus-gates.c           | 112 ++++++++++++++++++++++
  23  drivers/clk/sunxi/clk-sunxi.c                     |   6 ++
  24  4 files changed, 121 insertions(+)
  25  create mode 100644 drivers/clk/sunxi/clk-sun8i-bus-gates.c
  26
  27 --- a/drivers/clk/sunxi/Makefile
  28 +++ b/drivers/clk/sunxi/Makefile
  29 @@ -10,6 +10,7 @@ obj-y += clk-a10-pll2.o
  30  obj-y += clk-a20-gmac.o
  31  obj-y += clk-mod0.o
  32  obj-y += clk-simple-gates.o
  33 +obj-y += clk-sun8i-bus-gates.o
  34  obj-y += clk-sun8i-mbus.o
  35  obj-y += clk-sun9i-core.o
  36  obj-y += clk-sun9i-mmc.o
  37 --- /dev/null
  38 +++ b/drivers/clk/sunxi/clk-sun8i-bus-gates.c
  39 @@ -0,0 +1,112 @@
  40 +/*
  41 + * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
  42 + *
  43 + * Based on clk-simple-gates.c, which is:
  44 + * Copyright 2015 Maxime Ripard
  45 + *
  46 + * Maxime Ripard <maxime.ripard@free-electrons.com>
  47 + *
  48 + * This program is free software; you can redistribute it and/or modify
  49 + * it under the terms of the GNU General Public License as published by
  50 + * the Free Software Foundation; either version 2 of the License, or
  51 + * (at your option) any later version.
  52 + *
  53 + * This program is distributed in the hope that it will be useful,
  54 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  55 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  56 + * GNU General Public License for more details.
  57 + */
  58 +
  59 +#include <linux/clk.h>
  60 +#include <linux/clk-provider.h>
  61 +#include <linux/of.h>
  62 +#include <linux/of_address.h>
  63 +#include <linux/slab.h>
  64 +#include <linux/spinlock.h>
  65 +
  66 +static DEFINE_SPINLOCK(gates_lock);
  67 +
  68 +static void __init sun8i_h3_bus_gates_init(struct device_node *node)
  69 +{
  70 +       static const char * const names[] = { "ahb1", "ahb2", "apb1", "apb2" };
  71 +       enum { AHB1, AHB2, APB1, APB2, PARENT_MAX } clk_parent;
  72 +       const char *parents[PARENT_MAX];
  73 +       struct clk_onecell_data *clk_data;
  74 +       const char *clk_name;
  75 +       struct property *prop;
  76 +       struct resource res;
  77 +       void __iomem *clk_reg;
  78 +       void __iomem *reg;
  79 +       const __be32 *p;
  80 +       int number, i;
  81 +       u8 clk_bit;
  82 +       u32 index;
  83 +
  84 +       reg = of_io_request_and_map(node, 0, of_node_full_name(node));
  85 +       if (IS_ERR(reg))
  86 +               return;
  87 +
  88 +       for (i = 0; i < ARRAY_SIZE(names); i++) {
  89 +               index = of_property_match_string(node, "clock-names",
  90 +                                                names[i]);
  91 +               if (index < 0)
  92 +                       return;
  93 +
  94 +               parents[i] = of_clk_get_parent_name(node, index);
  95 +       }
  96 +
  97 +       clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
  98 +       if (!clk_data)
  99 +               goto err_unmap;
 100 +
 101 +       number = of_property_count_u32_elems(node, "clock-indices");
 102 +       of_property_read_u32_index(node, "clock-indices", number - 1, &number);
 103 +
 104 +       clk_data->clks = kcalloc(number + 1, sizeof(struct clk *), GFP_KERNEL);
 105 +       if (!clk_data->clks)
 106 +               goto err_free_data;
 107 +
 108 +       i = 0;
 109 +       of_property_for_each_u32(node, "clock-indices", prop, p, index) {
 110 +               of_property_read_string_index(node, "clock-output-names",
 111 +                                             i, &clk_name);
 112 +
 113 +               if (index == 17 || (index >= 29 && index <= 31))
 114 +                       clk_parent = AHB2;
 115 +               else if (index <= 63 || index >= 128)
 116 +                       clk_parent = AHB1;
 117 +               else if (index >= 64 && index <= 95)
 118 +                       clk_parent = APB1;
 119 +               else if (index >= 96 && index <= 127)
 120 +                       clk_parent = APB2;
 121 +
 122 +               clk_reg = reg + 4 * (index / 32);
 123 +               clk_bit = index % 32;
 124 +
 125 +               clk_data->clks[index] = clk_register_gate(NULL, clk_name,
 126 +                                                         parents[clk_parent],
 127 +                                                         0, clk_reg, clk_bit,
 128 +                                                         0, &gates_lock);
 129 +               i++;
 130 +
 131 +               if (IS_ERR(clk_data->clks[index])) {
 132 +                       WARN_ON(true);
 133 +                       continue;
 134 +               }
 135 +       }
 136 +
 137 +       clk_data->clk_num = number + 1;
 138 +       of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 139 +
 140 +       return;
 141 +
 142 +err_free_data:
 143 +       kfree(clk_data);
 144 +err_unmap:
 145 +       iounmap(reg);
 146 +       of_address_to_resource(node, 0, &res);
 147 +       release_mem_region(res.start, resource_size(&res));
 148 +}
 149 +
 150 +CLK_OF_DECLARE(sun8i_h3_bus_gates, "allwinner,sun8i-h3-bus-gates-clk",
 151 +              sun8i_h3_bus_gates_init);
 152 --- a/drivers/clk/sunxi/clk-sunxi.c
 153 +++ b/drivers/clk/sunxi/clk-sunxi.c
 154 @@ -778,6 +778,10 @@ static const struct mux_data sun6i_a31_a
 155         .shift = 12,
 156  };
 157
 158 +static const struct mux_data sun8i_h3_ahb2_mux_data __initconst = {
 159 +       .shift = 0,
 160 +};
 161 +
 162  static void __init sunxi_mux_clk_setup(struct device_node *node,
 163                                        struct mux_data *data)
 164  {
 165 @@ -1130,6 +1134,7 @@ static const struct of_device_id clk_div
 166  static const struct of_device_id clk_mux_match[] __initconst = {
 167         {.compatible = "allwinner,sun4i-a10-cpu-clk", .data = &sun4i_cpu_mux_data,},
 168         {.compatible = "allwinner,sun6i-a31-ahb1-mux-clk", .data = &sun6i_a31_ahb1_mux_data,},
 169 +       {.compatible = "allwinner,sun8i-h3-ahb2-clk", .data = &sun8i_h3_ahb2_mux_data,},
 170         {}
 171  };
 172
 173 @@ -1212,6 +1217,7 @@ CLK_OF_DECLARE(sun6i_a31_clk_init, "allw
 174  CLK_OF_DECLARE(sun6i_a31s_clk_init, "allwinner,sun6i-a31s", sun6i_init_clocks);
 175  CLK_OF_DECLARE(sun8i_a23_clk_init, "allwinner,sun8i-a23", sun6i_init_clocks);
 176  CLK_OF_DECLARE(sun8i_a33_clk_init, "allwinner,sun8i-a33", sun6i_init_clocks);
 177 +CLK_OF_DECLARE(sun8i_h3_clk_init, "allwinner,sun8i-h3", sun6i_init_clocks);
 178
 179  static void __init sun9i_init_clocks(struct device_node *node)
 180  {