target/linux/sunxi/patches-3.14/250-pwm-add-driver.patch

   1 diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
   2 index 5b34ff29ea38..178b017be827 100644
   3 --- a/drivers/pwm/Kconfig
   4 +++ b/drivers/pwm/Kconfig
   5 @@ -217,6 +217,15 @@ config PWM_SPEAR
   6           To compile this driver as a module, choose M here: the module
   7           will be called pwm-spear.
   8
   9 +config PWM_SUNXI
  10 +       tristate "Allwinner PWM support"
  11 +       depends on ARCH_SUNXI || COMPILE_TEST
  12 +       help
  13 +         Generic PWM framework driver for Allwinner SoCs.
  14 +
  15 +         To compile this driver as a module, choose M here: the module
  16 +         will be called pwm-sunxi.
  17 +
  18  config PWM_TEGRA
  19         tristate "NVIDIA Tegra PWM support"
  20         depends on ARCH_TEGRA
  21 diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
  22 index e57d2c38a794..39997ea2e276 100644
  23 --- a/drivers/pwm/Makefile
  24 +++ b/drivers/pwm/Makefile
  25 @@ -19,6 +19,7 @@ obj-$(CONFIG_PWM_PXA)         += pwm-pxa.o
  26  obj-$(CONFIG_PWM_RENESAS_TPU)  += pwm-renesas-tpu.o
  27  obj-$(CONFIG_PWM_SAMSUNG)      += pwm-samsung.o
  28  obj-$(CONFIG_PWM_SPEAR)                += pwm-spear.o
  29 +obj-$(CONFIG_PWM_SUNXI)                += pwm-sunxi.o
  30  obj-$(CONFIG_PWM_TEGRA)                += pwm-tegra.o
  31  obj-$(CONFIG_PWM_TIECAP)       += pwm-tiecap.o
  32  obj-$(CONFIG_PWM_TIEHRPWM)     += pwm-tiehrpwm.o
  33 diff --git a/drivers/pwm/pwm-sunxi.c b/drivers/pwm/pwm-sunxi.c
  34 new file mode 100644
  35 index 000000000000..e7c3ca1d3c42
  36 --- /dev/null
  37 +++ b/drivers/pwm/pwm-sunxi.c
  38 @@ -0,0 +1,338 @@
  39 +/*
  40 + * Driver for Allwinner Pulse Width Modulation Controller
  41 + *
  42 + * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
  43 + *
  44 + * Licensed under GPLv2.
  45 + */
  46 +
  47 +#include <linux/bitops.h>
  48 +#include <linux/clk.h>
  49 +#include <linux/err.h>
  50 +#include <linux/io.h>
  51 +#include <linux/of.h>
  52 +#include <linux/of_device.h>
  53 +#include <linux/platform_device.h>
  54 +#include <linux/pwm.h>
  55 +#include <linux/module.h>
  56 +#include <linux/mutex.h>
  57 +#include <linux/slab.h>
  58 +
  59 +#define PWM_CTRL_REG           0x0
  60 +
  61 +#define PWM_CH_PRD_BASE                0x4
  62 +#define PWM_CH_PRD_OFF         0x4
  63 +#define PWM_CH_PRD(x)          (PWM_CH_PRD_BASE + PWM_CH_PRD_OFF * (x))
  64 +
  65 +#define PWMCH_OFFSET           15
  66 +#define PWM_PRESCAL_MASK       GENMASK(3, 0)
  67 +#define PWM_PRESCAL_OFF                0
  68 +#define PWM_EN                 BIT(4)
  69 +#define PWM_ACT_STATE          BIT(5)
  70 +#define PWM_CLK_GATING         BIT(6)
  71 +#define PWM_MODE               BIT(7)
  72 +#define PWM_PULSE              BIT(8)
  73 +#define PWM_BYPASS             BIT(9)
  74 +
  75 +#define PWM_RDY_BASE           28
  76 +#define PWM_RDY_OFF            1
  77 +#define PWM_RDY(x)             BIT(PWM_RDY_BASE + PWM_RDY_OFF * (x))
  78 +
  79 +#define PWM_PRD_ACT_MASK       GENMASK(7, 0)
  80 +#define PWM_PRD(x)             ((x - 1) << 16)
  81 +#define PWM_PRD_MASK           GENMASK(7, 0)
  82 +
  83 +#define        BIT_CH(bit, chan)       (bit << (chan * PWMCH_OFFSET))
  84 +
  85 +u32 prescal_table[] = { 120, 180, 240, 360, 480, 0, 0, 0,
  86 +                       12000, 24000, 36000, 48000, 72000,
  87 +                       0, 0, 1 };
  88 +
  89 +struct sunxi_pwm_data {
  90 +       bool has_rdy;
  91 +};
  92 +
  93 +struct sunxi_pwm_chip {
  94 +       struct pwm_chip chip;
  95 +       struct clk *clk;
  96 +       void __iomem *base;
  97 +       struct mutex ctrl_lock;
  98 +       const struct sunxi_pwm_data *data;
  99 +};
 100 +
 101 +#define to_sunxi_pwm_chip(chip) container_of(chip, struct sunxi_pwm_chip, chip)
 102 +
 103 +static inline u32 sunxi_pwm_readl(struct sunxi_pwm_chip *chip,
 104 +                                 unsigned long offset)
 105 +{
 106 +       return readl(chip->base + offset);
 107 +}
 108 +
 109 +static inline void sunxi_pwm_writel(struct sunxi_pwm_chip *chip,
 110 +                                   unsigned long offset, unsigned long val)
 111 +{
 112 +       writel(val, chip->base + offset);
 113 +}
 114 +
 115 +static int sunxi_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
 116 +                           int duty_ns, int period_ns)
 117 +{
 118 +       struct sunxi_pwm_chip *sunxi_pwm = to_sunxi_pwm_chip(chip);
 119 +       u32 clk_rate, prd, dty;
 120 +       u64 div;
 121 +       u32 val, clk_gate;
 122 +       int i, ret;
 123 +
 124 +       clk_rate = clk_get_rate(sunxi_pwm->clk);
 125 +
 126 +       /* First, test without any divider */
 127 +       i = PWM_PRESCAL_MASK;
 128 +       div = clk_rate * period_ns;
 129 +       do_div(div, 1000000000);
 130 +       if (div > PWM_PRD_MASK) {
 131 +               /* Then go up from the first divider */
 132 +               for (i = 0; i < PWM_PRESCAL_MASK; i++) {
 133 +                       if (!prescal_table[i])
 134 +                               continue;
 135 +                       div = clk_rate / prescal_table[i];
 136 +                       div = div * period_ns;
 137 +                       do_div(div, 1000000000);
 138 +                       if (div <= PWM_PRD_MASK)
 139 +                               break;
 140 +               }
 141 +       }
 142 +
 143 +       if (div > PWM_PRD_MASK) {
 144 +               dev_err(chip->dev, "prescaler exceeds the maximum value\n");
 145 +               return -EINVAL;
 146 +       }
 147 +
 148 +       prd = div;
 149 +       div *= duty_ns;
 150 +       do_div(div, period_ns);
 151 +       dty = div;
 152 +
 153 +       ret = clk_prepare_enable(sunxi_pwm->clk);
 154 +       if (ret) {
 155 +               dev_err(chip->dev, "failed to enable PWM clock\n");
 156 +               return ret;
 157 +       }
 158 +
 159 +       mutex_lock(&sunxi_pwm->ctrl_lock);
 160 +       val = sunxi_pwm_readl(sunxi_pwm, PWM_CTRL_REG);
 161 +
 162 +       if (sunxi_pwm->data->has_rdy && (val & PWM_RDY(pwm->hwpwm))) {
 163 +               mutex_unlock(&sunxi_pwm->ctrl_lock);
 164 +               clk_disable_unprepare(sunxi_pwm->clk);
 165 +               return -EBUSY;
 166 +       }
 167 +
 168 +       clk_gate = val & BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
 169 +       if (clk_gate) {
 170 +               val &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
 171 +               sunxi_pwm_writel(sunxi_pwm, PWM_CTRL_REG, val);
 172 +       }
 173 +
 174 +       val = sunxi_pwm_readl(sunxi_pwm, PWM_CTRL_REG);
 175 +       val &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm);
 176 +       val |= i;
 177 +       sunxi_pwm_writel(sunxi_pwm, PWM_CTRL_REG, val);
 178 +
 179 +       sunxi_pwm_writel(sunxi_pwm, PWM_CH_PRD(pwm->hwpwm), dty | PWM_PRD(prd));
 180 +
 181 +       if (clk_gate) {
 182 +               val = sunxi_pwm_readl(sunxi_pwm, PWM_CTRL_REG);
 183 +               val |= clk_gate;
 184 +               sunxi_pwm_writel(sunxi_pwm, PWM_CTRL_REG, val);
 185 +       }
 186 +
 187 +       mutex_unlock(&sunxi_pwm->ctrl_lock);
 188 +       clk_disable_unprepare(sunxi_pwm->clk);
 189 +
 190 +       return 0;
 191 +}
 192 +
 193 +static int sunxi_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
 194 +                                 enum pwm_polarity polarity)
 195 +{
 196 +       struct sunxi_pwm_chip *sunxi_pwm = to_sunxi_pwm_chip(chip);
 197 +       u32 val;
 198 +       int ret;
 199 +
 200 +       ret = clk_prepare_enable(sunxi_pwm->clk);
 201 +       if (ret) {
 202 +               dev_err(chip->dev, "failed to enable PWM clock\n");
 203 +               return ret;
 204 +       }
 205 +
 206 +       mutex_lock(&sunxi_pwm->ctrl_lock);
 207 +       val = sunxi_pwm_readl(sunxi_pwm, PWM_CTRL_REG);
 208 +
 209 +       if (polarity != PWM_POLARITY_NORMAL)
 210 +               val &= ~BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
 211 +       else
 212 +               val |= BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
 213 +
 214 +
 215 +       sunxi_pwm_writel(sunxi_pwm, PWM_CTRL_REG, val);
 216 +
 217 +       mutex_unlock(&sunxi_pwm->ctrl_lock);
 218 +       clk_disable_unprepare(sunxi_pwm->clk);
 219 +
 220 +       return 0;
 221 +}
 222 +
 223 +static int sunxi_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
 224 +{
 225 +       struct sunxi_pwm_chip *sunxi_pwm = to_sunxi_pwm_chip(chip);
 226 +       u32 val;
 227 +       int ret;
 228 +
 229 +       ret = clk_prepare_enable(sunxi_pwm->clk);
 230 +       if (ret) {
 231 +               dev_err(chip->dev, "failed to enable PWM clock\n");
 232 +               return ret;
 233 +       }
 234 +
 235 +       mutex_lock(&sunxi_pwm->ctrl_lock);
 236 +       val = sunxi_pwm_readl(sunxi_pwm, PWM_CTRL_REG);
 237 +       val |= BIT_CH(PWM_EN, pwm->hwpwm);
 238 +       val |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
 239 +       sunxi_pwm_writel(sunxi_pwm, PWM_CTRL_REG, val);
 240 +       mutex_unlock(&sunxi_pwm->ctrl_lock);
 241 +
 242 +       return 0;
 243 +}
 244 +
 245 +static void sunxi_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
 246 +{
 247 +       struct sunxi_pwm_chip *sunxi_pwm = to_sunxi_pwm_chip(chip);
 248 +       u32 val;
 249 +
 250 +       mutex_lock(&sunxi_pwm->ctrl_lock);
 251 +       val = sunxi_pwm_readl(sunxi_pwm, PWM_CTRL_REG);
 252 +       val &= ~BIT_CH(PWM_EN, pwm->hwpwm);
 253 +       val &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
 254 +       sunxi_pwm_writel(sunxi_pwm, PWM_CTRL_REG, val);
 255 +       mutex_unlock(&sunxi_pwm->ctrl_lock);
 256 +
 257 +       clk_disable_unprepare(sunxi_pwm->clk);
 258 +}
 259 +
 260 +static const struct pwm_ops sunxi_pwm_ops = {
 261 +       .config = sunxi_pwm_config,
 262 +       .set_polarity = sunxi_pwm_set_polarity,
 263 +       .enable = sunxi_pwm_enable,
 264 +       .disable = sunxi_pwm_disable,
 265 +       .owner = THIS_MODULE,
 266 +};
 267 +
 268 +static const struct sunxi_pwm_data sunxi_pwm_data_a10 = {
 269 +       .has_rdy = false,
 270 +};
 271 +
 272 +static const struct sunxi_pwm_data sunxi_pwm_data_a20 = {
 273 +       .has_rdy = true,
 274 +};
 275 +
 276 +static const struct of_device_id sunxi_pwm_dt_ids[] = {
 277 +       {
 278 +               .compatible = "allwinner,sun4i-a10-pwm",
 279 +               .data = &sunxi_pwm_data_a10,
 280 +       }, {
 281 +               .compatible = "allwinner,sun7i-a20-pwm",
 282 +               .data = &sunxi_pwm_data_a20,
 283 +       }, {
 284 +               /* sentinel */
 285 +       },
 286 +};
 287 +MODULE_DEVICE_TABLE(of, sunxi_pwm_dt_ids);
 288 +
 289 +static int sunxi_pwm_probe(struct platform_device *pdev)
 290 +{
 291 +       struct sunxi_pwm_chip *sunxi_pwm;
 292 +       struct resource *res;
 293 +       int ret;
 294 +
 295 +       const struct of_device_id *match;
 296 +
 297 +       match = of_match_device(sunxi_pwm_dt_ids, &pdev->dev);
 298 +       if (!match || !match->data)
 299 +               return -ENODEV;
 300 +
 301 +       sunxi_pwm = devm_kzalloc(&pdev->dev, sizeof(*sunxi_pwm), GFP_KERNEL);
 302 +       if (!sunxi_pwm)
 303 +               return -ENOMEM;
 304 +
 305 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 306 +       sunxi_pwm->base = devm_ioremap_resource(&pdev->dev, res);
 307 +       if (IS_ERR(sunxi_pwm->base))
 308 +               return PTR_ERR(sunxi_pwm->base);
 309 +
 310 +       sunxi_pwm->clk = devm_clk_get(&pdev->dev, NULL);
 311 +       if (IS_ERR(sunxi_pwm->clk))
 312 +               return PTR_ERR(sunxi_pwm->clk);
 313 +
 314 +       sunxi_pwm->chip.dev = &pdev->dev;
 315 +       sunxi_pwm->chip.ops = &sunxi_pwm_ops;
 316 +
 317 +       sunxi_pwm->chip.base = -1;
 318 +       sunxi_pwm->chip.npwm = 2;
 319 +       sunxi_pwm->chip.can_sleep = true;
 320 +       sunxi_pwm->chip.of_xlate = of_pwm_xlate_with_flags;
 321 +       sunxi_pwm->chip.of_pwm_n_cells = 3;
 322 +       sunxi_pwm->data = match->data;
 323 +
 324 +       mutex_init(&sunxi_pwm->ctrl_lock);
 325 +
 326 +       ret = clk_prepare_enable(sunxi_pwm->clk);
 327 +       if (ret) {
 328 +               dev_err(&pdev->dev, "failed to enable PWM clock\n");
 329 +               goto error;
 330 +       }
 331 +
 332 +       /* By default, the polarity is inversed, set it to normal */
 333 +       sunxi_pwm_writel(sunxi_pwm, PWM_CTRL_REG,
 334 +                        BIT_CH(PWM_ACT_STATE, 0) |
 335 +                        BIT_CH(PWM_ACT_STATE, 1));
 336 +       clk_disable_unprepare(sunxi_pwm->clk);
 337 +
 338 +       ret = pwmchip_add(&sunxi_pwm->chip);
 339 +       if (ret < 0) {
 340 +               dev_err(&pdev->dev, "failed to add PWM chip %d\n", ret);
 341 +               goto error;
 342 +       }
 343 +
 344 +       platform_set_drvdata(pdev, sunxi_pwm);
 345 +
 346 +       return ret;
 347 +
 348 +error:
 349 +       mutex_destroy(&sunxi_pwm->ctrl_lock);
 350 +       clk_disable_unprepare(sunxi_pwm->clk);
 351 +       return ret;
 352 +}
 353 +
 354 +static int sunxi_pwm_remove(struct platform_device *pdev)
 355 +{
 356 +       struct sunxi_pwm_chip *sunxi_pwm = platform_get_drvdata(pdev);
 357 +
 358 +       mutex_destroy(&sunxi_pwm->ctrl_lock);
 359 +
 360 +       return pwmchip_remove(&sunxi_pwm->chip);
 361 +}
 362 +
 363 +static struct platform_driver sunxi_pwm_driver = {
 364 +       .driver = {
 365 +               .name = "sunxi-pwm",
 366 +               .of_match_table = sunxi_pwm_dt_ids,
 367 +       },
 368 +       .probe = sunxi_pwm_probe,
 369 +       .remove = sunxi_pwm_remove,
 370 +};
 371 +module_platform_driver(sunxi_pwm_driver);
 372 +
 373 +MODULE_ALIAS("platform:sunxi-pwm");
 374 +MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@free-electrons.com>");
 375 +MODULE_DESCRIPTION("Allwinner PWM driver");
 376 +MODULE_LICENSE("GPL v2");